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drivers/net/yellowfin.c: Use (pr|netdev)_<level> macro helpers
[net-next-2.6.git] / drivers / net / tehuti.c
CommitLineData
1a348ccc
AG		 1/*
2 * Tehuti Networks(R) Network Driver
3 * ethtool interface implementation
4 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12/*
13 * RX HW/SW interaction overview
14 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
15 * There are 2 types of RX communication channels betwean driver and NIC.
16 * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
17 * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
18 * info about buffer's location, size and ID. An ID field is used to identify a
19 * buffer when it's returned with data via RXD Fifo (see below)
20 * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
21 * filled by HW and is readen by SW. Each descriptor holds status and ID.
22 * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
23 * via dma moves it into host memory, builds new RXD descriptor with same ID,
24 * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
25 *
26 * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos.
27 * One holds 1.5K packets and another - 26K packets. Depending on incoming
28 * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
29 * filled with data, HW builds new RXD descriptor for it and push it into single
30 * RXD Fifo.
31 *
32 * RX SW Data Structures
33 * ~~~~~~~~~~~~~~~~~~~~~
34 * skb db - used to keep track of all skbs owned by SW and their dma addresses.
35 * For RX case, ownership lasts from allocating new empty skb for RXF until
36 * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own
37 * skb db. Implemented as array with bitmask.
38 * fifo - keeps info about fifo's size and location, relevant HW registers,
39 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
40 * Implemented as simple struct.
41 *
42 * RX SW Execution Flow
43 * ~~~~~~~~~~~~~~~~~~~~
44 * Upon initialization (ifconfig up) driver creates RX fifos and initializes
45 * relevant registers. At the end of init phase, driver enables interrupts.
46 * NIC sees that there is no RXF buffers and raises
47 * RD_INTR interrupt, isr fills skbs and Rx begins.
48 * Driver has two receive operation modes:
49 * NAPI - interrupt-driven mixed with polling
50 * interrupt-driven only
51 *
52 * Interrupt-driven only flow is following. When buffer is ready, HW raises
53 * interrupt and isr is called. isr collects all available packets
54 * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit.
55
56 * Rx buffer allocation note
57 * ~~~~~~~~~~~~~~~~~~~~~~~~~
58 * Driver cares to feed such amount of RxF descriptors that respective amount of
59 * RxD descriptors can not fill entire RxD fifo. The main reason is lack of
60 * overflow check in Bordeaux for RxD fifo free/used size.
61 * FIXME: this is NOT fully implemented, more work should be done
62 *
63 */
64
865a21a5
JP		 65#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
66
1a348ccc 67#include "tehuti.h"
1a348ccc 68
865a21a5 69static struct pci_device_id __devinitdata bdx_pci_tbl[] = {
1a348ccc
AG		 70 {0x1FC9, 0x3009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
71 {0x1FC9, 0x3010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
72 {0x1FC9, 0x3014, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
73 {0}
74};
75
76MODULE_DEVICE_TABLE(pci, bdx_pci_tbl);
77
78/* Definitions needed by ISR or NAPI functions */
79static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f);
80static void bdx_tx_cleanup(struct bdx_priv *priv);
81static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget);
82
83/* Definitions needed by FW loading */
84static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size);
85
86/* Definitions needed by hw_start */
87static int bdx_tx_init(struct bdx_priv *priv);
88static int bdx_rx_init(struct bdx_priv *priv);
89
90/* Definitions needed by bdx_close */
91static void bdx_rx_free(struct bdx_priv *priv);
92static void bdx_tx_free(struct bdx_priv *priv);
93
94/* Definitions needed by bdx_probe */
95static void bdx_ethtool_ops(struct net_device *netdev);
96
97/*************************************************************************
98 * Print Info *
99 *************************************************************************/
100
101static void print_hw_id(struct pci_dev *pdev)
102{
103 struct pci_nic *nic = pci_get_drvdata(pdev);
104 u16 pci_link_status = 0;
105 u16 pci_ctrl = 0;
106
107 pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status);
108 pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl);
109
865a21a5
JP		 110 pr_info("%s%s\n", BDX_NIC_NAME,
111 nic->port_num == 1 ? "" : ", 2-Port");
112 pr_info("srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n",
113 readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF,
114 readl(nic->regs + FPGA_SEED),
115 GET_LINK_STATUS_LANES(pci_link_status),
116 GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl));
1a348ccc
AG		 117}
118
119static void print_fw_id(struct pci_nic *nic)
120{
865a21a5 121 pr_info("fw 0x%x\n", readl(nic->regs + FW_VER));
1a348ccc
AG		 122}
123
124static void print_eth_id(struct net_device *ndev)
125{
865a21a5
JP		 126 netdev_info(ndev, "%s, Port %c\n",
127 BDX_NIC_NAME, (ndev->if_port == 0) ? 'A' : 'B');
1a348ccc
AG		 128
129}
130
131/*************************************************************************
132 * Code *
133 *************************************************************************/
134
135#define bdx_enable_interrupts(priv) \
136 do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
137#define bdx_disable_interrupts(priv) \
138 do { WRITE_REG(priv, regIMR, 0); } while (0)
139
140/* bdx_fifo_init
141 * create TX/RX descriptor fifo for host-NIC communication.
142 * 1K extra space is allocated at the end of the fifo to simplify
143 * processing of descriptors that wraps around fifo's end
144 * @priv - NIC private structure
145 * @f - fifo to initialize
146 * @fsz_type - fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
147 * @reg_XXX - offsets of registers relative to base address
148 *
149 * Returns 0 on success, negative value on failure
150 *
151 */
152static int
153bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type,
154 u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR)
155{
156 u16 memsz = FIFO_SIZE * (1 << fsz_type);
157
158 memset(f, 0, sizeof(struct fifo));
159 /* pci_alloc_consistent gives us 4k-aligned memory */
160 f->va = pci_alloc_consistent(priv->pdev,
161 memsz + FIFO_EXTRA_SPACE, &f->da);
162 if (!f->va) {
865a21a5 163 pr_err("pci_alloc_consistent failed\n");
1a348ccc
AG		 164 RET(-ENOMEM);
165 }
166 f->reg_CFG0 = reg_CFG0;
167 f->reg_CFG1 = reg_CFG1;
168 f->reg_RPTR = reg_RPTR;
169 f->reg_WPTR = reg_WPTR;
170 f->rptr = 0;
171 f->wptr = 0;
172 f->memsz = memsz;
173 f->size_mask = memsz - 1;
174 WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
175 WRITE_REG(priv, reg_CFG1, H32_64(f->da));
176
177 RET(0);
178}
179
180/* bdx_fifo_free - free all resources used by fifo
181 * @priv - NIC private structure
182 * @f - fifo to release
183 */
184static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f)
185{
186 ENTER;
187 if (f->va) {
188 pci_free_consistent(priv->pdev,
189 f->memsz + FIFO_EXTRA_SPACE, f->va, f->da);
190 f->va = NULL;
191 }
192 RET();
193}
194
195/*
196 * bdx_link_changed - notifies OS about hw link state.
197 * @bdx_priv - hw adapter structure
198 */
199static void bdx_link_changed(struct bdx_priv *priv)
200{
201 u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT;
202
203 if (!link) {
204 if (netif_carrier_ok(priv->ndev)) {
205 netif_stop_queue(priv->ndev);
206 netif_carrier_off(priv->ndev);
865a21a5 207 netdev_err(priv->ndev, "Link Down\n");
1a348ccc
AG		 208 }
209 } else {
210 if (!netif_carrier_ok(priv->ndev)) {
211 netif_wake_queue(priv->ndev);
212 netif_carrier_on(priv->ndev);
865a21a5 213 netdev_err(priv->ndev, "Link Up\n");
1a348ccc
AG		 214 }
215 }
216}
217
218static void bdx_isr_extra(struct bdx_priv *priv, u32 isr)
219{
220 if (isr & IR_RX_FREE_0) {
221 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
222 DBG("RX_FREE_0\n");
223 }
224
225 if (isr & IR_LNKCHG0)
226 bdx_link_changed(priv);
227
228 if (isr & IR_PCIE_LINK)
865a21a5 229 netdev_err(priv->ndev, "PCI-E Link Fault\n");
1a348ccc
AG		 230
231 if (isr & IR_PCIE_TOUT)
865a21a5 232 netdev_err(priv->ndev, "PCI-E Time Out\n");
1a348ccc
AG		 233
234}
235
236/* bdx_isr - Interrupt Service Routine for Bordeaux NIC
237 * @irq - interrupt number
238 * @ndev - network device
239 * @regs - CPU registers
240 *
241 * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise
242 *
243 * It reads ISR register to know interrupt reasons, and proceed them one by one.
244 * Reasons of interest are:
245 * RX_DESC - new packet has arrived and RXD fifo holds its descriptor
246 * RX_FREE - number of free Rx buffers in RXF fifo gets low
247 * TX_FREE - packet was transmited and RXF fifo holds its descriptor
248 */
249
250static irqreturn_t bdx_isr_napi(int irq, void *dev)
251{
252 struct net_device *ndev = dev;
8f15ea42 253 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 254 u32 isr;
255
256 ENTER;
257 isr = (READ_REG(priv, regISR) & IR_RUN);
258 if (unlikely(!isr)) {
259 bdx_enable_interrupts(priv);
260 return IRQ_NONE; /* Not our interrupt */
261 }
262
263 if (isr & IR_EXTRA)
264 bdx_isr_extra(priv, isr);
265
266 if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) {
288379f0
BH		 267 if (likely(napi_schedule_prep(&priv->napi))) {
268 __napi_schedule(&priv->napi);
1a348ccc
AG		 269 RET(IRQ_HANDLED);
270 } else {
271 /* NOTE: we get here if intr has slipped into window
272 * between these lines in bdx_poll:
273 * bdx_enable_interrupts(priv);
274 * return 0;
275 * currently intrs are disabled (since we read ISR),
276 * and we have failed to register next poll.
277 * so we read the regs to trigger chip
278 * and allow further interupts. */
279 READ_REG(priv, regTXF_WPTR_0);
280 READ_REG(priv, regRXD_WPTR_0);
281 }
282 }
283
284 bdx_enable_interrupts(priv);
285 RET(IRQ_HANDLED);
286}
287
288static int bdx_poll(struct napi_struct *napi, int budget)
289{
290 struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi);
1a348ccc
AG		 291 int work_done;
292
293 ENTER;
294 bdx_tx_cleanup(priv);
295 work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget);
296 if ((work_done < budget) ||
297 (priv->napi_stop++ >= 30)) {
298 DBG("rx poll is done. backing to isr-driven\n");
299
300 /* from time to time we exit to let NAPI layer release
301 * device lock and allow waiting tasks (eg rmmod) to advance) */
302 priv->napi_stop = 0;
303
288379f0 304 napi_complete(napi);
1a348ccc
AG		 305 bdx_enable_interrupts(priv);
306 }
307 return work_done;
308}
309
310/* bdx_fw_load - loads firmware to NIC
311 * @priv - NIC private structure
312 * Firmware is loaded via TXD fifo, so it must be initialized first.
313 * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC
314 * can have few of them). So all drivers use semaphore register to choose one
315 * that will actually load FW to NIC.
316 */
317
318static int bdx_fw_load(struct bdx_priv *priv)
319{
06e1f9ff 320 const struct firmware *fw = NULL;
1a348ccc 321 int master, i;
06e1f9ff 322 int rc;
1a348ccc
AG		 323
324 ENTER;
325 master = READ_REG(priv, regINIT_SEMAPHORE);
326 if (!READ_REG(priv, regINIT_STATUS) && master) {
06e1f9ff
BH		 327 rc = request_firmware(&fw, "tehuti/firmware.bin", &priv->pdev->dev);
328 if (rc)
329 goto out;
330 bdx_tx_push_desc_safe(priv, (char *)fw->data, fw->size);
1a348ccc
AG		 331 mdelay(100);
332 }
333 for (i = 0; i < 200; i++) {
06e1f9ff
BH		 334 if (READ_REG(priv, regINIT_STATUS)) {
335 rc = 0;
336 goto out;
337 }
1a348ccc
AG		 338 mdelay(2);
339 }
06e1f9ff
BH		 340 rc = -EIO;
341out:
1a348ccc
AG		 342 if (master)
343 WRITE_REG(priv, regINIT_SEMAPHORE, 1);
06e1f9ff
BH		 344 if (fw)
345 release_firmware(fw);
1a348ccc 346
06e1f9ff 347 if (rc) {
865a21a5 348 netdev_err(priv->ndev, "firmware loading failed\n");
06e1f9ff
BH		 349 if (rc == -EIO)
350 DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",
351 READ_REG(priv, regVPC),
352 READ_REG(priv, regVIC),
353 READ_REG(priv, regINIT_STATUS), i);
354 RET(rc);
1a348ccc
AG		 355 } else {
356 DBG("%s: firmware loading success\n", priv->ndev->name);
357 RET(0);
358 }
359}
360
361static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv)
362{
363 u32 val;
364
365 ENTER;
366 DBG("mac0=%x mac1=%x mac2=%x\n",
367 READ_REG(priv, regUNC_MAC0_A),
368 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
369
370 val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);
371 WRITE_REG(priv, regUNC_MAC2_A, val);
372 val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]);
373 WRITE_REG(priv, regUNC_MAC1_A, val);
374 val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]);
375 WRITE_REG(priv, regUNC_MAC0_A, val);
376
377 DBG("mac0=%x mac1=%x mac2=%x\n",
378 READ_REG(priv, regUNC_MAC0_A),
379 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
380 RET();
381}
382
383/* bdx_hw_start - inits registers and starts HW's Rx and Tx engines
384 * @priv - NIC private structure
385 */
386static int bdx_hw_start(struct bdx_priv *priv)
387{
388 int rc = -EIO;
389 struct net_device *ndev = priv->ndev;
390
391 ENTER;
392 bdx_link_changed(priv);
393
394 /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */
395 WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);
396 WRITE_REG(priv, regPAUSE_QUANT, 0x96);
397 WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);
398 WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);
399 WRITE_REG(priv, regRX_FULLNESS, 0);
400 WRITE_REG(priv, regTX_FULLNESS, 0);
401 WRITE_REG(priv, regCTRLST,
402 regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA);
403
404 WRITE_REG(priv, regVGLB, 0);
405 WRITE_REG(priv, regMAX_FRAME_A,
406 priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL);
407
408 DBG("RDINTCM=%08x\n", priv->rdintcm); /*NOTE: test script uses this */
409 WRITE_REG(priv, regRDINTCM0, priv->rdintcm);
410 WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */
411
412 DBG("TDINTCM=%08x\n", priv->tdintcm); /*NOTE: test script uses this */
413 WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */
414
415 /* Enable timer interrupt once in 2 secs. */
416 /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */
417 bdx_restore_mac(priv->ndev, priv);
418
419 WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |
420 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB);
421
249658d5 422#define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI) ? 0 : IRQF_SHARED)
cb001a1f
JP		 423
424 rc = request_irq(priv->pdev->irq, bdx_isr_napi, BDX_IRQ_TYPE,
425 ndev->name, ndev);
426 if (rc)
1a348ccc
AG		 427 goto err_irq;
428 bdx_enable_interrupts(priv);
429
430 RET(0);
431
432err_irq:
433 RET(rc);
434}
435
436static void bdx_hw_stop(struct bdx_priv *priv)
437{
438 ENTER;
439 bdx_disable_interrupts(priv);
440 free_irq(priv->pdev->irq, priv->ndev);
441
442 netif_carrier_off(priv->ndev);
443 netif_stop_queue(priv->ndev);
444
445 RET();
446}
447
448static int bdx_hw_reset_direct(void __iomem *regs)
449{
450 u32 val, i;
451 ENTER;
452
453 /* reset sequences: read, write 1, read, write 0 */
454 val = readl(regs + regCLKPLL);
455 writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);
456 udelay(50);
457 val = readl(regs + regCLKPLL);
458 writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL);
459
460 /* check that the PLLs are locked and reset ended */
461 for (i = 0; i < 70; i++, mdelay(10))
462 if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
463 /* do any PCI-E read transaction */
464 readl(regs + regRXD_CFG0_0);
465 return 0;
466 }
865a21a5 467 pr_err("HW reset failed\n");
1a348ccc
AG		 468 return 1; /* failure */
469}
470
471static int bdx_hw_reset(struct bdx_priv *priv)
472{
473 u32 val, i;
474 ENTER;
475
476 if (priv->port == 0) {
477 /* reset sequences: read, write 1, read, write 0 */
478 val = READ_REG(priv, regCLKPLL);
479 WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);
480 udelay(50);
481 val = READ_REG(priv, regCLKPLL);
482 WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);
483 }
484 /* check that the PLLs are locked and reset ended */
485 for (i = 0; i < 70; i++, mdelay(10))
486 if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
487 /* do any PCI-E read transaction */
488 READ_REG(priv, regRXD_CFG0_0);
489 return 0;
490 }
865a21a5 491 pr_err("HW reset failed\n");
1a348ccc
AG		 492 return 1; /* failure */
493}
494
495static int bdx_sw_reset(struct bdx_priv *priv)
496{
497 int i;
498
499 ENTER;
500 /* 1. load MAC (obsolete) */
501 /* 2. disable Rx (and Tx) */
502 WRITE_REG(priv, regGMAC_RXF_A, 0);
503 mdelay(100);
504 /* 3. disable port */
505 WRITE_REG(priv, regDIS_PORT, 1);
506 /* 4. disable queue */
507 WRITE_REG(priv, regDIS_QU, 1);
508 /* 5. wait until hw is disabled */
509 for (i = 0; i < 50; i++) {
510 if (READ_REG(priv, regRST_PORT) & 1)
511 break;
512 mdelay(10);
513 }
514 if (i == 50)
865a21a5 515 netdev_err(priv->ndev, "SW reset timeout. continuing anyway\n");
1a348ccc
AG		 516
517 /* 6. disable intrs */
518 WRITE_REG(priv, regRDINTCM0, 0);
519 WRITE_REG(priv, regTDINTCM0, 0);
520 WRITE_REG(priv, regIMR, 0);
521 READ_REG(priv, regISR);
522
523 /* 7. reset queue */
524 WRITE_REG(priv, regRST_QU, 1);
525 /* 8. reset port */
526 WRITE_REG(priv, regRST_PORT, 1);
527 /* 9. zero all read and write pointers */
528 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
529 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
530 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
531 WRITE_REG(priv, i, 0);
532 /* 10. unseet port disable */
533 WRITE_REG(priv, regDIS_PORT, 0);
534 /* 11. unset queue disable */
535 WRITE_REG(priv, regDIS_QU, 0);
536 /* 12. unset queue reset */
537 WRITE_REG(priv, regRST_QU, 0);
538 /* 13. unset port reset */
539 WRITE_REG(priv, regRST_PORT, 0);
540 /* 14. enable Rx */
541 /* skiped. will be done later */
542 /* 15. save MAC (obsolete) */
543 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
544 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
545
546 RET(0);
547}
548
549/* bdx_reset - performs right type of reset depending on hw type */
550static int bdx_reset(struct bdx_priv *priv)
551{
552 ENTER;
553 RET((priv->pdev->device == 0x3009)
554 ? bdx_hw_reset(priv)
555 : bdx_sw_reset(priv));
556}
557
558/**
559 * bdx_close - Disables a network interface
560 * @netdev: network interface device structure
561 *
562 * Returns 0, this is not allowed to fail
563 *
564 * The close entry point is called when an interface is de-activated
565 * by the OS. The hardware is still under the drivers control, but
566 * needs to be disabled. A global MAC reset is issued to stop the
567 * hardware, and all transmit and receive resources are freed.
568 **/
569static int bdx_close(struct net_device *ndev)
570{
571 struct bdx_priv *priv = NULL;
572
573 ENTER;
8f15ea42 574 priv = netdev_priv(ndev);
1a348ccc
AG		 575
576 napi_disable(&priv->napi);
577
578 bdx_reset(priv);
579 bdx_hw_stop(priv);
580 bdx_rx_free(priv);
581 bdx_tx_free(priv);
582 RET(0);
583}
584
585/**
586 * bdx_open - Called when a network interface is made active
587 * @netdev: network interface device structure
588 *
589 * Returns 0 on success, negative value on failure
590 *
591 * The open entry point is called when a network interface is made
592 * active by the system (IFF_UP). At this point all resources needed
593 * for transmit and receive operations are allocated, the interrupt
594 * handler is registered with the OS, the watchdog timer is started,
595 * and the stack is notified that the interface is ready.
596 **/
597static int bdx_open(struct net_device *ndev)
598{
599 struct bdx_priv *priv;
600 int rc;
601
602 ENTER;
8f15ea42 603 priv = netdev_priv(ndev);
1a348ccc
AG		 604 bdx_reset(priv);
605 if (netif_running(ndev))
606 netif_stop_queue(priv->ndev);
607
cb001a1f
JP		 608 if ((rc = bdx_tx_init(priv)) ||
609 (rc = bdx_rx_init(priv)) ||
610 (rc = bdx_fw_load(priv)))
1a348ccc
AG		 611 goto err;
612
613 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
614
cb001a1f
JP		 615 rc = bdx_hw_start(priv);
616 if (rc)
1a348ccc
AG		 617 goto err;
618
619 napi_enable(&priv->napi);
620
621 print_fw_id(priv->nic);
622
623 RET(0);
624
625err:
626 bdx_close(ndev);
627 RET(rc);
628}
629
6131a260
FR		 630static int bdx_range_check(struct bdx_priv *priv, u32 offset)
631{
632 return (offset > (u32) (BDX_REGS_SIZE / priv->nic->port_num)) ?
633 -EINVAL : 0;
634}
635
1a348ccc
AG		 636static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd)
637{
8f15ea42 638 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 639 u32 data[3];
640 int error;
641
642 ENTER;
643
644 DBG("jiffies=%ld cmd=%d\n", jiffies, cmd);
645 if (cmd != SIOCDEVPRIVATE) {
646 error = copy_from_user(data, ifr->ifr_data, sizeof(data));
647 if (error) {
865a21a5 648 pr_err("cant copy from user\n");
1a348ccc
AG		 649 RET(error);
650 }
651 DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]);
652 }
653
62035542 654 if (!capable(CAP_SYS_RAWIO))
f946dffe
JG		 655 return -EPERM;
656
1a348ccc
AG		 657 switch (data[0]) {
658
659 case BDX_OP_READ:
6131a260
FR		 660 error = bdx_range_check(priv, data[1]);
661 if (error < 0)
662 return error;
1a348ccc
AG		 663 data[2] = READ_REG(priv, data[1]);
664 DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2],
665 data[2]);
666 error = copy_to_user(ifr->ifr_data, data, sizeof(data));
667 if (error)
668 RET(error);
669 break;
670
671 case BDX_OP_WRITE:
6131a260
FR		 672 error = bdx_range_check(priv, data[1]);
673 if (error < 0)
674 return error;
1a348ccc
AG		 675 WRITE_REG(priv, data[1], data[2]);
676 DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]);
677 break;
678
679 default:
680 RET(-EOPNOTSUPP);
681 }
682 return 0;
683}
684
685static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
686{
687 ENTER;
688 if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15))
689 RET(bdx_ioctl_priv(ndev, ifr, cmd));
690 else
691 RET(-EOPNOTSUPP);
692}
693
694/*
695 * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid
696 * by passing VLAN filter table to hardware
697 * @ndev network device
698 * @vid VLAN vid
699 * @op add or kill operation
700 */
701static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable)
702{
8f15ea42 703 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 704 u32 reg, bit, val;
705
706 ENTER;
707 DBG2("vid=%d value=%d\n", (int)vid, enable);
708 if (unlikely(vid >= 4096)) {
865a21a5 709 pr_err("invalid VID: %u (> 4096)\n", vid);
1a348ccc
AG		 710 RET();
711 }
712 reg = regVLAN_0 + (vid / 32) * 4;
713 bit = 1 << vid % 32;
714 val = READ_REG(priv, reg);
715 DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit);
716 if (enable)
717 val |= bit;
718 else
719 val &= ~bit;
720 DBG2("new val %x\n", val);
721 WRITE_REG(priv, reg, val);
722 RET();
723}
724
725/*
726 * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table
727 * @ndev network device
728 * @vid VLAN vid to add
729 */
730static void bdx_vlan_rx_add_vid(struct net_device *ndev, uint16_t vid)
731{
732 __bdx_vlan_rx_vid(ndev, vid, 1);
733}
734
735/*
736 * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table
737 * @ndev network device
738 * @vid VLAN vid to kill
739 */
740static void bdx_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid)
741{
742 __bdx_vlan_rx_vid(ndev, vid, 0);
743}
744
745/*
746 * bdx_vlan_rx_register - kernel hook for adding VLAN group
747 * @ndev network device
748 * @grp VLAN group
749 */
750static void
751bdx_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
752{
8f15ea42 753 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 754
755 ENTER;
756 DBG("device='%s', group='%p'\n", ndev->name, grp);
757 priv->vlgrp = grp;
758 RET();
759}
760
761/**
762 * bdx_change_mtu - Change the Maximum Transfer Unit
763 * @netdev: network interface device structure
764 * @new_mtu: new value for maximum frame size
765 *
766 * Returns 0 on success, negative on failure
767 */
768static int bdx_change_mtu(struct net_device *ndev, int new_mtu)
769{
1a348ccc
AG		 770 ENTER;
771
772 if (new_mtu == ndev->mtu)
773 RET(0);
774
775 /* enforce minimum frame size */
776 if (new_mtu < ETH_ZLEN) {
865a21a5
JP		 777 netdev_err(ndev, "mtu %d is less then minimal %d\n",
778 new_mtu, ETH_ZLEN);
1a348ccc
AG		 779 RET(-EINVAL);
780 }
781
782 ndev->mtu = new_mtu;
783 if (netif_running(ndev)) {
784 bdx_close(ndev);
785 bdx_open(ndev);
786 }
787 RET(0);
788}
789
790static void bdx_setmulti(struct net_device *ndev)
791{
8f15ea42 792 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 793
794 u32 rxf_val =
795 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN;
796 int i;
797
798 ENTER;
799 /* IMF - imperfect (hash) rx multicat filter */
800 /* PMF - perfect rx multicat filter */
801
802 /* FIXME: RXE(OFF) */
803 if (ndev->flags & IFF_PROMISC) {
804 rxf_val |= GMAC_RX_FILTER_PRM;
805 } else if (ndev->flags & IFF_ALLMULTI) {
806 /* set IMF to accept all multicast frmaes */
807 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
808 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);
4cd24eaf 809 } else if (!netdev_mc_empty(ndev)) {
1a348ccc
AG		 810 u8 hash;
811 struct dev_mc_list *mclist;
812 u32 reg, val;
813
814 /* set IMF to deny all multicast frames */
815 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
816 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);
817 /* set PMF to deny all multicast frames */
818 for (i = 0; i < MAC_MCST_NUM; i++) {
819 WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);
820 WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);
821 }
822
823 /* use PMF to accept first MAC_MCST_NUM (15) addresses */
824 /* TBD: sort addreses and write them in ascending order
825 * into RX_MAC_MCST regs. we skip this phase now and accept ALL
826 * multicast frames throu IMF */
827 mclist = ndev->mc_list;
828
829 /* accept the rest of addresses throu IMF */
830 for (; mclist; mclist = mclist->next) {
831 hash = 0;
832 for (i = 0; i < ETH_ALEN; i++)
833 hash ^= mclist->dmi_addr[i];
834 reg = regRX_MCST_HASH0 + ((hash >> 5) << 2);
835 val = READ_REG(priv, reg);
836 val |= (1 << (hash % 32));
837 WRITE_REG(priv, reg, val);
838 }
839
840 } else {
4cd24eaf 841 DBG("only own mac %d\n", netdev_mc_count(ndev));
1a348ccc
AG		 842 rxf_val |= GMAC_RX_FILTER_AB;
843 }
844 WRITE_REG(priv, regGMAC_RXF_A, rxf_val);
845 /* enable RX */
846 /* FIXME: RXE(ON) */
847 RET();
848}
849
850static int bdx_set_mac(struct net_device *ndev, void *p)
851{
8f15ea42 852 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 853 struct sockaddr *addr = p;
854
855 ENTER;
856 /*
857 if (netif_running(dev))
858 return -EBUSY
859 */
860 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
861 bdx_restore_mac(ndev, priv);
862 RET(0);
863}
864
865static int bdx_read_mac(struct bdx_priv *priv)
866{
867 u16 macAddress[3], i;
868 ENTER;
869
870 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
871 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
872 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
873 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
874 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
875 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
876 for (i = 0; i < 3; i++) {
877 priv->ndev->dev_addr[i * 2 + 1] = macAddress[i];
878 priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8;
879 }
880 RET(0);
881}
882
883static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg)
884{
885 u64 val;
886
887 val = READ_REG(priv, reg);
888 val |= ((u64) READ_REG(priv, reg + 8)) << 32;
889 return val;
890}
891
892/*Do the statistics-update work*/
893static void bdx_update_stats(struct bdx_priv *priv)
894{
895 struct bdx_stats *stats = &priv->hw_stats;
896 u64 *stats_vector = (u64 *) stats;
897 int i;
898 int addr;
899
900 /*Fill HW structure */
901 addr = 0x7200;
902 /*First 12 statistics - 0x7200 - 0x72B0 */
903 for (i = 0; i < 12; i++) {
904 stats_vector[i] = bdx_read_l2stat(priv, addr);
905 addr += 0x10;
906 }
907 BDX_ASSERT(addr != 0x72C0);
908 /* 0x72C0-0x72E0 RSRV */
909 addr = 0x72F0;
910 for (; i < 16; i++) {
911 stats_vector[i] = bdx_read_l2stat(priv, addr);
912 addr += 0x10;
913 }
914 BDX_ASSERT(addr != 0x7330);
915 /* 0x7330-0x7360 RSRV */
916 addr = 0x7370;
917 for (; i < 19; i++) {
918 stats_vector[i] = bdx_read_l2stat(priv, addr);
919 addr += 0x10;
920 }
921 BDX_ASSERT(addr != 0x73A0);
922 /* 0x73A0-0x73B0 RSRV */
923 addr = 0x73C0;
924 for (; i < 23; i++) {
925 stats_vector[i] = bdx_read_l2stat(priv, addr);
926 addr += 0x10;
927 }
928 BDX_ASSERT(addr != 0x7400);
929 BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i);
930}
931
932static struct net_device_stats *bdx_get_stats(struct net_device *ndev)
933{
8f15ea42 934 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 935 struct net_device_stats *net_stat = &priv->net_stats;
936 return net_stat;
937}
938
939static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
940 u16 rxd_vlan);
941static void print_rxfd(struct rxf_desc *rxfd);
942
943/*************************************************************************
944 * Rx DB *
945 *************************************************************************/
946
947static void bdx_rxdb_destroy(struct rxdb *db)
948{
c0feed87 949 vfree(db);
1a348ccc
AG		 950}
951
952static struct rxdb *bdx_rxdb_create(int nelem)
953{
954 struct rxdb *db;
955 int i;
956
957 db = vmalloc(sizeof(struct rxdb)
958 + (nelem * sizeof(int))
959 + (nelem * sizeof(struct rx_map)));
960 if (likely(db != NULL)) {
961 db->stack = (int *)(db + 1);
962 db->elems = (void *)(db->stack + nelem);
963 db->nelem = nelem;
964 db->top = nelem;
965 for (i = 0; i < nelem; i++)
966 db->stack[i] = nelem - i - 1; /* to make first allocs
967 close to db struct*/
968 }
969
970 return db;
971}
972
973static inline int bdx_rxdb_alloc_elem(struct rxdb *db)
974{
975 BDX_ASSERT(db->top <= 0);
976 return db->stack[--(db->top)];
977}
978
979static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n)
980{
981 BDX_ASSERT((n < 0) || (n >= db->nelem));
982 return db->elems + n;
983}
984
985static inline int bdx_rxdb_available(struct rxdb *db)
986{
987 return db->top;
988}
989
990static inline void bdx_rxdb_free_elem(struct rxdb *db, int n)
991{
992 BDX_ASSERT((n >= db->nelem) || (n < 0));
993 db->stack[(db->top)++] = n;
994}
995
996/*************************************************************************
997 * Rx Init *
998 *************************************************************************/
999
1000/* bdx_rx_init - initialize RX all related HW and SW resources
1001 * @priv - NIC private structure
1002 *
1003 * Returns 0 on success, negative value on failure
1004 *
1005 * It creates rxf and rxd fifos, update relevant HW registers, preallocate
1006 * skb for rx. It assumes that Rx is desabled in HW
1007 * funcs are grouped for better cache usage
1008 *
025dfdaf 1009 * RxD fifo is smaller than RxF fifo by design. Upon high load, RxD will be
1a348ccc
AG		 1010 * filled and packets will be dropped by nic without getting into host or
1011 * cousing interrupt. Anyway, in that condition, host has no chance to proccess
1012 * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
1013 */
1014
1015/* TBD: ensure proper packet size */
1016
1017static int bdx_rx_init(struct bdx_priv *priv)
1018{
1019 ENTER;
ddfce6bb 1020
1a348ccc
AG		 1021 if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size,
1022 regRXD_CFG0_0, regRXD_CFG1_0,
1023 regRXD_RPTR_0, regRXD_WPTR_0))
1024 goto err_mem;
1025 if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size,
1026 regRXF_CFG0_0, regRXF_CFG1_0,
1027 regRXF_RPTR_0, regRXF_WPTR_0))
1028 goto err_mem;
cb001a1f
JP		 1029 priv->rxdb = bdx_rxdb_create(priv->rxf_fifo0.m.memsz /
1030 sizeof(struct rxf_desc));
1031 if (!priv->rxdb)
1a348ccc
AG		 1032 goto err_mem;
1033
1034 priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN;
1035 return 0;
1036
1037err_mem:
865a21a5 1038 netdev_err(priv->ndev, "Rx init failed\n");
1a348ccc
AG		 1039 return -ENOMEM;
1040}
1041
1042/* bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo
1043 * @priv - NIC private structure
1044 * @f - RXF fifo
1045 */
1046static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1047{
1048 struct rx_map *dm;
1049 struct rxdb *db = priv->rxdb;
1050 u16 i;
1051
1052 ENTER;
1053 DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db),
1054 db->nelem - bdx_rxdb_available(db));
1055 while (bdx_rxdb_available(db) > 0) {
1056 i = bdx_rxdb_alloc_elem(db);
1057 dm = bdx_rxdb_addr_elem(db, i);
1058 dm->dma = 0;
1059 }
1060 for (i = 0; i < db->nelem; i++) {
1061 dm = bdx_rxdb_addr_elem(db, i);
1062 if (dm->dma) {
1063 pci_unmap_single(priv->pdev,
1064 dm->dma, f->m.pktsz,
1065 PCI_DMA_FROMDEVICE);
1066 dev_kfree_skb(dm->skb);
1067 }
1068 }
1069}
1070
1071/* bdx_rx_free - release all Rx resources
1072 * @priv - NIC private structure
1073 * It assumes that Rx is desabled in HW
1074 */
1075static void bdx_rx_free(struct bdx_priv *priv)
1076{
1077 ENTER;
1078 if (priv->rxdb) {
1079 bdx_rx_free_skbs(priv, &priv->rxf_fifo0);
1080 bdx_rxdb_destroy(priv->rxdb);
1081 priv->rxdb = NULL;
1082 }
1083 bdx_fifo_free(priv, &priv->rxf_fifo0.m);
1084 bdx_fifo_free(priv, &priv->rxd_fifo0.m);
1085
1086 RET();
1087}
1088
1089/*************************************************************************
1090 * Rx Engine *
1091 *************************************************************************/
1092
1093/* bdx_rx_alloc_skbs - fill rxf fifo with new skbs
1094 * @priv - nic's private structure
1095 * @f - RXF fifo that needs skbs
1096 * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo.
1097 * skb's virtual and physical addresses are stored in skb db.
1098 * To calculate free space, func uses cached values of RPTR and WPTR
1099 * When needed, it also updates RPTR and WPTR.
1100 */
1101
1102/* TBD: do not update WPTR if no desc were written */
1103
1104static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1105{
1106 struct sk_buff *skb;
1107 struct rxf_desc *rxfd;
1108 struct rx_map *dm;
1109 int dno, delta, idx;
1110 struct rxdb *db = priv->rxdb;
1111
1112 ENTER;
1113 dno = bdx_rxdb_available(db) - 1;
1114 while (dno > 0) {
cb001a1f
JP		 1115 skb = dev_alloc_skb(f->m.pktsz + NET_IP_ALIGN);
1116 if (!skb) {
865a21a5 1117 pr_err("NO MEM: dev_alloc_skb failed\n");
1a348ccc
AG		 1118 break;
1119 }
1120 skb->dev = priv->ndev;
1121 skb_reserve(skb, NET_IP_ALIGN);
1122
1123 idx = bdx_rxdb_alloc_elem(db);
1124 dm = bdx_rxdb_addr_elem(db, idx);
1125 dm->dma = pci_map_single(priv->pdev,
1126 skb->data, f->m.pktsz,
1127 PCI_DMA_FROMDEVICE);
1128 dm->skb = skb;
1129 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1130 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1131 rxfd->va_lo = idx;
1132 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1133 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1134 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1135 print_rxfd(rxfd);
1136
1137 f->m.wptr += sizeof(struct rxf_desc);
1138 delta = f->m.wptr - f->m.memsz;
1139 if (unlikely(delta >= 0)) {
1140 f->m.wptr = delta;
1141 if (delta > 0) {
1142 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1143 DBG("wrapped descriptor\n");
1144 }
1145 }
1146 dno--;
1147 }
1148 /*TBD: to do - delayed rxf wptr like in txd */
1149 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1150 RET();
1151}
1152
1153static inline void
1154NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan,
1155 struct sk_buff *skb)
1156{
1157 ENTER;
1158 DBG("rxdd->flags.bits.vtag=%d vlgrp=%p\n", GET_RXD_VTAG(rxd_val1),
1159 priv->vlgrp);
1160 if (priv->vlgrp && GET_RXD_VTAG(rxd_val1)) {
1161 DBG("%s: vlan rcv vlan '%x' vtag '%x', device name '%s'\n",
1162 priv->ndev->name,
1163 GET_RXD_VLAN_ID(rxd_vlan),
1164 GET_RXD_VTAG(rxd_val1),
1165 vlan_group_get_device(priv->vlgrp,
1166 GET_RXD_VLAN_ID(rxd_vlan))->name);
1167 /* NAPI variant of receive functions */
1168 vlan_hwaccel_receive_skb(skb, priv->vlgrp,
38b22195 1169 GET_RXD_VLAN_TCI(rxd_vlan));
1a348ccc
AG		 1170 } else {
1171 netif_receive_skb(skb);
1172 }
1173}
1174
1175static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd)
1176{
1177 struct rxf_desc *rxfd;
1178 struct rx_map *dm;
1179 struct rxf_fifo *f;
1180 struct rxdb *db;
1181 struct sk_buff *skb;
1182 int delta;
1183
1184 ENTER;
1185 DBG("priv=%p rxdd=%p\n", priv, rxdd);
1186 f = &priv->rxf_fifo0;
1187 db = priv->rxdb;
1188 DBG("db=%p f=%p\n", db, f);
1189 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1190 DBG("dm=%p\n", dm);
1191 skb = dm->skb;
1192 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1193 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1194 rxfd->va_lo = rxdd->va_lo;
1195 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1196 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1197 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1198 print_rxfd(rxfd);
1199
1200 f->m.wptr += sizeof(struct rxf_desc);
1201 delta = f->m.wptr - f->m.memsz;
1202 if (unlikely(delta >= 0)) {
1203 f->m.wptr = delta;
1204 if (delta > 0) {
1205 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1206 DBG("wrapped descriptor\n");
1207 }
1208 }
1209 RET();
1210}
1211
1212/* bdx_rx_receive - recieves full packets from RXD fifo and pass them to OS
1213 * NOTE: a special treatment is given to non-continous descriptors
1214 * that start near the end, wraps around and continue at the beginning. a second
1215 * part is copied right after the first, and then descriptor is interpreted as
1216 * normal. fifo has an extra space to allow such operations
1217 * @priv - nic's private structure
1218 * @f - RXF fifo that needs skbs
1219 */
1220
1221/* TBD: replace memcpy func call by explicite inline asm */
1222
1223static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget)
1224{
1225 struct sk_buff *skb, *skb2;
1226 struct rxd_desc *rxdd;
1227 struct rx_map *dm;
1228 struct rxf_fifo *rxf_fifo;
1229 int tmp_len, size;
1230 int done = 0;
1231 int max_done = BDX_MAX_RX_DONE;
1232 struct rxdb *db = NULL;
1233 /* Unmarshalled descriptor - copy of descriptor in host order */
1234 u32 rxd_val1;
1235 u16 len;
1236 u16 rxd_vlan;
1237
1238 ENTER;
1239 max_done = budget;
1240
1a348ccc
AG		 1241 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
1242
1243 size = f->m.wptr - f->m.rptr;
1244 if (size < 0)
1245 size = f->m.memsz + size; /* size is negative :-) */
1246
1247 while (size > 0) {
1248
1249 rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr);
1250 rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1);
1251
1252 len = CPU_CHIP_SWAP16(rxdd->len);
1253
1254 rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan);
1255
1256 print_rxdd(rxdd, rxd_val1, len, rxd_vlan);
1257
1258 tmp_len = GET_RXD_BC(rxd_val1) << 3;
1259 BDX_ASSERT(tmp_len <= 0);
1260 size -= tmp_len;
1261 if (size < 0) /* test for partially arrived descriptor */
1262 break;
1263
1264 f->m.rptr += tmp_len;
1265
1266 tmp_len = f->m.rptr - f->m.memsz;
1267 if (unlikely(tmp_len >= 0)) {
1268 f->m.rptr = tmp_len;
1269 if (tmp_len > 0) {
1270 DBG("wrapped desc rptr=%d tmp_len=%d\n",
1271 f->m.rptr, tmp_len);
1272 memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len);
1273 }
1274 }
1275
1276 if (unlikely(GET_RXD_ERR(rxd_val1))) {
1277 DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1));
1278 priv->net_stats.rx_errors++;
1279 bdx_recycle_skb(priv, rxdd);
1280 continue;
1281 }
1282
1283 rxf_fifo = &priv->rxf_fifo0;
1284 db = priv->rxdb;
1285 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1286 skb = dm->skb;
1287
1288 if (len < BDX_COPYBREAK &&
1289 (skb2 = dev_alloc_skb(len + NET_IP_ALIGN))) {
1290 skb_reserve(skb2, NET_IP_ALIGN);
1291 /*skb_put(skb2, len); */
1292 pci_dma_sync_single_for_cpu(priv->pdev,
1293 dm->dma, rxf_fifo->m.pktsz,
1294 PCI_DMA_FROMDEVICE);
1295 memcpy(skb2->data, skb->data, len);
1296 bdx_recycle_skb(priv, rxdd);
1297 skb = skb2;
1298 } else {
1299 pci_unmap_single(priv->pdev,
1300 dm->dma, rxf_fifo->m.pktsz,
1301 PCI_DMA_FROMDEVICE);
1302 bdx_rxdb_free_elem(db, rxdd->va_lo);
1303 }
1304
1305 priv->net_stats.rx_bytes += len;
1306
1307 skb_put(skb, len);
1308 skb->dev = priv->ndev;
1309 skb->ip_summed = CHECKSUM_UNNECESSARY;
1310 skb->protocol = eth_type_trans(skb, priv->ndev);
1311
1312 /* Non-IP packets aren't checksum-offloaded */
1313 if (GET_RXD_PKT_ID(rxd_val1) == 0)
1314 skb->ip_summed = CHECKSUM_NONE;
1315
1316 NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb);
1317
1318 if (++done >= max_done)
1319 break;
1320 }
1321
1322 priv->net_stats.rx_packets += done;
1323
1324 /* FIXME: do smth to minimize pci accesses */
1325 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1326
1327 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
1328
1329 RET(done);
1330}
1331
1332/*************************************************************************
1333 * Debug / Temprorary Code *
1334 *************************************************************************/
1335static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
1336 u16 rxd_vlan)
1337{
865a21a5 1338 DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d va_lo %d va_hi %d\n",
1a348ccc
AG		 1339 GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1),
1340 GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1),
1341 GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1),
1342 GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan),
1343 GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo,
1344 rxdd->va_hi);
1345}
1346
1347static void print_rxfd(struct rxf_desc *rxfd)
1348{
1349 DBG("=== RxF desc CHIP ORDER/ENDIANESS =============\n"
1350 "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
1351 rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len);
1352}
1353
1354/*
1355 * TX HW/SW interaction overview
1356 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1357 * There are 2 types of TX communication channels betwean driver and NIC.
1358 * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets
1359 * 2) TX Data Fifo - TXD - holds descriptors of full buffers.
1360 *
1361 * Currently NIC supports TSO, checksuming and gather DMA
1362 * UFO and IP fragmentation is on the way
1363 *
1364 * RX SW Data Structures
1365 * ~~~~~~~~~~~~~~~~~~~~~
1366 * txdb - used to keep track of all skbs owned by SW and their dma addresses.
1367 * For TX case, ownership lasts from geting packet via hard_xmit and until HW
1368 * acknowledges sent by TXF descriptors.
1369 * Implemented as cyclic buffer.
1370 * fifo - keeps info about fifo's size and location, relevant HW registers,
1371 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
1372 * Implemented as simple struct.
1373 *
1374 * TX SW Execution Flow
1375 * ~~~~~~~~~~~~~~~~~~~~
1376 * OS calls driver's hard_xmit method with packet to sent.
1377 * Driver creates DMA mappings, builds TXD descriptors and kicks HW
1378 * by updating TXD WPTR.
1379 * When packet is sent, HW write us TXF descriptor and SW frees original skb.
1380 * To prevent TXD fifo overflow without reading HW registers every time,
1381 * SW deploys "tx level" technique.
1382 * Upon strart up, tx level is initialized to TXD fifo length.
1383 * For every sent packet, SW gets its TXD descriptor sizei
1384 * (from precalculated array) and substructs it from tx level.
1385 * The size is also stored in txdb. When TXF ack arrives, SW fetch size of
1386 * original TXD descriptor from txdb and adds it to tx level.
1387 * When Tx level drops under some predefined treshhold, the driver
1388 * stops the TX queue. When TX level rises above that level,
1389 * the tx queue is enabled again.
1390 *
1391 * This technique avoids eccessive reading of RPTR and WPTR registers.
1392 * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput.
1393 */
1394
1395/*************************************************************************
1396 * Tx DB *
1397 *************************************************************************/
1398static inline int bdx_tx_db_size(struct txdb *db)
1399{
1400 int taken = db->wptr - db->rptr;
1401 if (taken < 0)
1402 taken = db->size + 1 + taken; /* (size + 1) equals memsz */
1403
1404 return db->size - taken;
1405}
1406
1407/* __bdx_tx_ptr_next - helper function, increment read/write pointer + wrap
1408 * @d - tx data base
1409 * @ptr - read or write pointer
1410 */
1411static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr)
1412{
1413 BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */
1414
1415 BDX_ASSERT(*pptr != db->rptr && /* expect either read */
1416 *pptr != db->wptr); /* or write pointer */
1417
1418 BDX_ASSERT(*pptr < db->start || /* pointer has to be */
1419 *pptr >= db->end); /* in range */
1420
1421 ++*pptr;
1422 if (unlikely(*pptr == db->end))
1423 *pptr = db->start;
1424}
1425
1426/* bdx_tx_db_inc_rptr - increment read pointer
1427 * @d - tx data base
1428 */
1429static inline void bdx_tx_db_inc_rptr(struct txdb *db)
1430{
1431 BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */
1432 __bdx_tx_db_ptr_next(db, &db->rptr);
1433}
1434
1435/* bdx_tx_db_inc_rptr - increment write pointer
1436 * @d - tx data base
1437 */
1438static inline void bdx_tx_db_inc_wptr(struct txdb *db)
1439{
1440 __bdx_tx_db_ptr_next(db, &db->wptr);
1441 BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as
1442 a result of write */
1443}
1444
1445/* bdx_tx_db_init - creates and initializes tx db
1446 * @d - tx data base
1447 * @sz_type - size of tx fifo
1448 * Returns 0 on success, error code otherwise
1449 */
1450static int bdx_tx_db_init(struct txdb *d, int sz_type)
1451{
1452 int memsz = FIFO_SIZE * (1 << (sz_type + 1));
1453
1454 d->start = vmalloc(memsz);
1455 if (!d->start)
1456 return -ENOMEM;
1457
1458 /*
1459 * In order to differentiate between db is empty and db is full
1460 * states at least one element should always be empty in order to
1461 * avoid rptr == wptr which means db is empty
1462 */
1463 d->size = memsz / sizeof(struct tx_map) - 1;
1464 d->end = d->start + d->size + 1; /* just after last element */
1465
1466 /* all dbs are created equally empty */
1467 d->rptr = d->start;
1468 d->wptr = d->start;
1469
1470 return 0;
1471}
1472
1473/* bdx_tx_db_close - closes tx db and frees all memory
1474 * @d - tx data base
1475 */
1476static void bdx_tx_db_close(struct txdb *d)
1477{
1478 BDX_ASSERT(d == NULL);
1479
c0feed87
F		 1480 vfree(d->start);
1481 d->start = NULL;
1a348ccc
AG		 1482}
1483
1484/*************************************************************************
1485 * Tx Engine *
1486 *************************************************************************/
1487
1488/* sizes of tx desc (including padding if needed) as function
1489 * of skb's frag number */
1490static struct {
1491 u16 bytes;
1492 u16 qwords; /* qword = 64 bit */
1493} txd_sizes[MAX_SKB_FRAGS + 1];
1494
1495/* txdb_map_skb - creates and stores dma mappings for skb's data blocks
1496 * @priv - NIC private structure
1497 * @skb - socket buffer to map
1498 *
1499 * It makes dma mappings for skb's data blocks and writes them to PBL of
1500 * new tx descriptor. It also stores them in the tx db, so they could be
1501 * unmaped after data was sent. It is reponsibility of a caller to make
1502 * sure that there is enough space in the tx db. Last element holds pointer
1503 * to skb itself and marked with zero length
1504 */
1505static inline void
1506bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb,
1507 struct txd_desc *txdd)
1508{
1509 struct txdb *db = &priv->txdb;
1510 struct pbl *pbl = &txdd->pbl[0];
1511 int nr_frags = skb_shinfo(skb)->nr_frags;
1512 int i;
1513
1514 db->wptr->len = skb->len - skb->data_len;
1515 db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data,
1516 db->wptr->len, PCI_DMA_TODEVICE);
1517 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1518 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1519 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1520 DBG("=== pbl len: 0x%x ================\n", pbl->len);
1521 DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo);
1522 DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi);
1523 bdx_tx_db_inc_wptr(db);
1524
1525 for (i = 0; i < nr_frags; i++) {
1526 struct skb_frag_struct *frag;
1527
1528 frag = &skb_shinfo(skb)->frags[i];
1529 db->wptr->len = frag->size;
1530 db->wptr->addr.dma =
1531 pci_map_page(priv->pdev, frag->page, frag->page_offset,
1532 frag->size, PCI_DMA_TODEVICE);
1533
1534 pbl++;
1535 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1536 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1537 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1538 bdx_tx_db_inc_wptr(db);
1539 }
1540
1541 /* add skb clean up info. */
1542 db->wptr->len = -txd_sizes[nr_frags].bytes;
1543 db->wptr->addr.skb = skb;
1544 bdx_tx_db_inc_wptr(db);
1545}
1546
1547/* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags
1548 * number of frags is used as index to fetch correct descriptors size,
1549 * instead of calculating it each time */
1550static void __init init_txd_sizes(void)
1551{
1552 int i, lwords;
1553
1554 /* 7 - is number of lwords in txd with one phys buffer
1555 * 3 - is number of lwords used for every additional phys buffer */
1556 for (i = 0; i < MAX_SKB_FRAGS + 1; i++) {
1557 lwords = 7 + (i * 3);
1558 if (lwords & 1)
1559 lwords++; /* pad it with 1 lword */
1560 txd_sizes[i].qwords = lwords >> 1;
1561 txd_sizes[i].bytes = lwords << 2;
1562 }
1563}
1564
1565/* bdx_tx_init - initialize all Tx related stuff.
1566 * Namely, TXD and TXF fifos, database etc */
1567static int bdx_tx_init(struct bdx_priv *priv)
1568{
1569 if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size,
1570 regTXD_CFG0_0,
1571 regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0))
1572 goto err_mem;
1573 if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size,
1574 regTXF_CFG0_0,
1575 regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0))
1576 goto err_mem;
1577
1578 /* The TX db has to keep mappings for all packets sent (on TxD)
1579 * and not yet reclaimed (on TxF) */
1580 if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size)))
1581 goto err_mem;
1582
1583 priv->tx_level = BDX_MAX_TX_LEVEL;
1584#ifdef BDX_DELAY_WPTR
1585 priv->tx_update_mark = priv->tx_level - 1024;
1586#endif
1587 return 0;
1588
1589err_mem:
865a21a5 1590 netdev_err(priv->ndev, "Tx init failed\n");
1a348ccc
AG		 1591 return -ENOMEM;
1592}
1593
1594/*
1595 * bdx_tx_space - calculates avalable space in TX fifo
1596 * @priv - NIC private structure
1597 * Returns avaliable space in TX fifo in bytes
1598 */
1599static inline int bdx_tx_space(struct bdx_priv *priv)
1600{
1601 struct txd_fifo *f = &priv->txd_fifo0;
1602 int fsize;
1603
1604 f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR;
1605 fsize = f->m.rptr - f->m.wptr;
1606 if (fsize <= 0)
1607 fsize = f->m.memsz + fsize;
249658d5 1608 return fsize;
1a348ccc
AG		 1609}
1610
1611/* bdx_tx_transmit - send packet to NIC
1612 * @skb - packet to send
1613 * ndev - network device assigned to NIC
1614 * Return codes:
1615 * o NETDEV_TX_OK everything ok.
1616 * o NETDEV_TX_BUSY Cannot transmit packet, try later
1617 * Usually a bug, means queue start/stop flow control is broken in
1618 * the driver. Note: the driver must NOT put the skb in its DMA ring.
1619 * o NETDEV_TX_LOCKED Locking failed, please retry quickly.
1620 */
61357325
SH		 1621static netdev_tx_t bdx_tx_transmit(struct sk_buff *skb,
1622 struct net_device *ndev)
1a348ccc 1623{
8f15ea42 1624 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 1625 struct txd_fifo *f = &priv->txd_fifo0;
1626 int txd_checksum = 7; /* full checksum */
1627 int txd_lgsnd = 0;
1628 int txd_vlan_id = 0;
1629 int txd_vtag = 0;
1630 int txd_mss = 0;
1631
1632 int nr_frags = skb_shinfo(skb)->nr_frags;
1633 struct txd_desc *txdd;
1634 int len;
1635 unsigned long flags;
1636
1637 ENTER;
1638 local_irq_save(flags);
1639 if (!spin_trylock(&priv->tx_lock)) {
1640 local_irq_restore(flags);
1641 DBG("%s[%s]: TX locked, returning NETDEV_TX_LOCKED\n",
1642 BDX_DRV_NAME, ndev->name);
1643 return NETDEV_TX_LOCKED;
1644 }
1645
1646 /* build tx descriptor */
1647 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */
1648 txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
1649 if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL))
1650 txd_checksum = 0;
1651
1652 if (skb_shinfo(skb)->gso_size) {
1653 txd_mss = skb_shinfo(skb)->gso_size;
1654 txd_lgsnd = 1;
1655 DBG("skb %p skb len %d gso size = %d\n", skb, skb->len,
1656 txd_mss);
1657 }
1658
1659 if (vlan_tx_tag_present(skb)) {
1660 /*Cut VLAN ID to 12 bits */
1661 txd_vlan_id = vlan_tx_tag_get(skb) & BITS_MASK(12);
1662 txd_vtag = 1;
1663 }
1664
1665 txdd->length = CPU_CHIP_SWAP16(skb->len);
1666 txdd->mss = CPU_CHIP_SWAP16(txd_mss);
1667 txdd->txd_val1 =
1668 CPU_CHIP_SWAP32(TXD_W1_VAL
1669 (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag,
1670 txd_lgsnd, txd_vlan_id));
1671 DBG("=== TxD desc =====================\n");
1672 DBG("=== w1: 0x%x ================\n", txdd->txd_val1);
1673 DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length);
1674
1675 bdx_tx_map_skb(priv, skb, txdd);
1676
1677 /* increment TXD write pointer. In case of
1678 fifo wrapping copy reminder of the descriptor
1679 to the beginning */
1680 f->m.wptr += txd_sizes[nr_frags].bytes;
1681 len = f->m.wptr - f->m.memsz;
1682 if (unlikely(len >= 0)) {
1683 f->m.wptr = len;
1684 if (len > 0) {
1685 BDX_ASSERT(len > f->m.memsz);
1686 memcpy(f->m.va, f->m.va + f->m.memsz, len);
1687 }
1688 }
1689 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */
1690
1691 priv->tx_level -= txd_sizes[nr_frags].bytes;
1692 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1693#ifdef BDX_DELAY_WPTR
1694 if (priv->tx_level > priv->tx_update_mark) {
1695 /* Force memory writes to complete before letting h/w
1696 know there are new descriptors to fetch.
1697 (might be needed on platforms like IA64)
1698 wmb(); */
1699 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1700 } else {
1701 if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) {
1702 priv->tx_noupd = 0;
1703 WRITE_REG(priv, f->m.reg_WPTR,
1704 f->m.wptr & TXF_WPTR_WR_PTR);
1705 }
1706 }
1707#else
1708 /* Force memory writes to complete before letting h/w
1709 know there are new descriptors to fetch.
1710 (might be needed on platforms like IA64)
1711 wmb(); */
1712 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1713
1714#endif
28679751
ED		 1715#ifdef BDX_LLTX
1716 ndev->trans_start = jiffies; /* NETIF_F_LLTX driver :( */
1717#endif
1a348ccc
AG		 1718 priv->net_stats.tx_packets++;
1719 priv->net_stats.tx_bytes += skb->len;
1720
1721 if (priv->tx_level < BDX_MIN_TX_LEVEL) {
1722 DBG("%s: %s: TX Q STOP level %d\n",
1723 BDX_DRV_NAME, ndev->name, priv->tx_level);
1724 netif_stop_queue(ndev);
1725 }
1726
1727 spin_unlock_irqrestore(&priv->tx_lock, flags);
1728 return NETDEV_TX_OK;
1729}
1730
1731/* bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ.
1732 * @priv - bdx adapter
1733 * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS
1734 * that those packets were sent
1735 */
1736static void bdx_tx_cleanup(struct bdx_priv *priv)
1737{
1738 struct txf_fifo *f = &priv->txf_fifo0;
1739 struct txdb *db = &priv->txdb;
1740 int tx_level = 0;
1741
1742 ENTER;
1743 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
1744 BDX_ASSERT(f->m.rptr >= f->m.memsz); /* started with valid rptr */
1745
1746 while (f->m.wptr != f->m.rptr) {
1747 f->m.rptr += BDX_TXF_DESC_SZ;
1748 f->m.rptr &= f->m.size_mask;
1749
1750 /* unmap all the fragments */
1751 /* first has to come tx_maps containing dma */
1752 BDX_ASSERT(db->rptr->len == 0);
1753 do {
1754 BDX_ASSERT(db->rptr->addr.dma == 0);
1755 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1756 db->rptr->len, PCI_DMA_TODEVICE);
1757 bdx_tx_db_inc_rptr(db);
1758 } while (db->rptr->len > 0);
1759 tx_level -= db->rptr->len; /* '-' koz len is negative */
1760
1761 /* now should come skb pointer - free it */
1a348ccc
AG		 1762 dev_kfree_skb_irq(db->rptr->addr.skb);
1763 bdx_tx_db_inc_rptr(db);
1764 }
1765
1766 /* let h/w know which TXF descriptors were cleaned */
1767 BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
1768 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1769
1770 /* We reclaimed resources, so in case the Q is stopped by xmit callback,
1771 * we resume the transmition and use tx_lock to synchronize with xmit.*/
1772 spin_lock(&priv->tx_lock);
1773 priv->tx_level += tx_level;
1774 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1775#ifdef BDX_DELAY_WPTR
1776 if (priv->tx_noupd) {
1777 priv->tx_noupd = 0;
1778 WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,
1779 priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
1780 }
1781#endif
1782
8e95a202
JP		 1783 if (unlikely(netif_queue_stopped(priv->ndev) &&
1784 netif_carrier_ok(priv->ndev) &&
1785 (priv->tx_level >= BDX_MIN_TX_LEVEL))) {
1a348ccc
AG		 1786 DBG("%s: %s: TX Q WAKE level %d\n",
1787 BDX_DRV_NAME, priv->ndev->name, priv->tx_level);
1788 netif_wake_queue(priv->ndev);
1789 }
1790 spin_unlock(&priv->tx_lock);
1791}
1792
1793/* bdx_tx_free_skbs - frees all skbs from TXD fifo.
1794 * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod
1795 */
1796static void bdx_tx_free_skbs(struct bdx_priv *priv)
1797{
1798 struct txdb *db = &priv->txdb;
1799
1800 ENTER;
1801 while (db->rptr != db->wptr) {
1802 if (likely(db->rptr->len))
1803 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1804 db->rptr->len, PCI_DMA_TODEVICE);
1805 else
1806 dev_kfree_skb(db->rptr->addr.skb);
1807 bdx_tx_db_inc_rptr(db);
1808 }
1809 RET();
1810}
1811
1812/* bdx_tx_free - frees all Tx resources */
1813static void bdx_tx_free(struct bdx_priv *priv)
1814{
1815 ENTER;
1816 bdx_tx_free_skbs(priv);
1817 bdx_fifo_free(priv, &priv->txd_fifo0.m);
1818 bdx_fifo_free(priv, &priv->txf_fifo0.m);
1819 bdx_tx_db_close(&priv->txdb);
1820}
1821
1822/* bdx_tx_push_desc - push descriptor to TxD fifo
1823 * @priv - NIC private structure
1824 * @data - desc's data
1825 * @size - desc's size
1826 *
1827 * Pushes desc to TxD fifo and overlaps it if needed.
1828 * NOTE: this func does not check for available space. this is responsibility
025dfdaf 1829 * of the caller. Neither does it check that data size is smaller than
1a348ccc
AG		 1830 * fifo size.
1831 */
1832static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size)
1833{
1834 struct txd_fifo *f = &priv->txd_fifo0;
1835 int i = f->m.memsz - f->m.wptr;
1836
1837 if (size == 0)
1838 return;
1839
1840 if (i > size) {
1841 memcpy(f->m.va + f->m.wptr, data, size);
1842 f->m.wptr += size;
1843 } else {
1844 memcpy(f->m.va + f->m.wptr, data, i);
1845 f->m.wptr = size - i;
1846 memcpy(f->m.va, data + i, f->m.wptr);
1847 }
1848 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1849}
1850
1851/* bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way
1852 * @priv - NIC private structure
1853 * @data - desc's data
1854 * @size - desc's size
1855 *
1856 * NOTE: this func does check for available space and, if neccessary, waits for
1857 * NIC to read existing data before writing new one.
1858 */
1859static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size)
1860{
1861 int timer = 0;
1862 ENTER;
1863
1864 while (size > 0) {
1865 /* we substruct 8 because when fifo is full rptr == wptr
1866 which also means that fifo is empty, we can understand
1867 the difference, but could hw do the same ??? :) */
1868 int avail = bdx_tx_space(priv) - 8;
1869 if (avail <= 0) {
1870 if (timer++ > 300) { /* prevent endless loop */
1871 DBG("timeout while writing desc to TxD fifo\n");
1872 break;
1873 }
1874 udelay(50); /* give hw a chance to clean fifo */
1875 continue;
1876 }
df7641af 1877 avail = min(avail, size);
1a348ccc
AG		 1878 DBG("about to push %d bytes starting %p size %d\n", avail,
1879 data, size);
1880 bdx_tx_push_desc(priv, data, avail);
1881 size -= avail;
1882 data += avail;
1883 }
1884 RET();
1885}
1886
2f30b1f6
SH		 1887static const struct net_device_ops bdx_netdev_ops = {
1888 .ndo_open = bdx_open,
1889 .ndo_stop = bdx_close,
1890 .ndo_start_xmit = bdx_tx_transmit,
1891 .ndo_validate_addr = eth_validate_addr,
1892 .ndo_do_ioctl = bdx_ioctl,
1893 .ndo_set_multicast_list = bdx_setmulti,
1894 .ndo_get_stats = bdx_get_stats,
1895 .ndo_change_mtu = bdx_change_mtu,
1896 .ndo_set_mac_address = bdx_set_mac,
1897 .ndo_vlan_rx_register = bdx_vlan_rx_register,
1898 .ndo_vlan_rx_add_vid = bdx_vlan_rx_add_vid,
1899 .ndo_vlan_rx_kill_vid = bdx_vlan_rx_kill_vid,
1900};
1901
1a348ccc
AG		 1902/**
1903 * bdx_probe - Device Initialization Routine
1904 * @pdev: PCI device information struct
1905 * @ent: entry in bdx_pci_tbl
1906 *
1907 * Returns 0 on success, negative on failure
1908 *
1909 * bdx_probe initializes an adapter identified by a pci_dev structure.
1910 * The OS initialization, configuring of the adapter private structure,
1911 * and a hardware reset occur.
1912 *
1913 * functions and their order used as explained in
1914 * /usr/src/linux/Documentation/DMA-{API,mapping}.txt
1915 *
1916 */
1917
1918/* TBD: netif_msg should be checked and implemented. I disable it for now */
1919static int __devinit
1920bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1921{
1922 struct net_device *ndev;
1923 struct bdx_priv *priv;
1924 int err, pci_using_dac, port;
1925 unsigned long pciaddr;
1926 u32 regionSize;
1927 struct pci_nic *nic;
1928
1929 ENTER;
1930
1931 nic = vmalloc(sizeof(*nic));
1932 if (!nic)
1933 RET(-ENOMEM);
1934
1935 /************** pci *****************/
cb001a1f
JP		 1936 err = pci_enable_device(pdev);
1937 if (err) /* it triggers interrupt, dunno why. */
1938 goto err_pci; /* it's not a problem though */
1a348ccc 1939
6a35528a
YH		 1940 if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) &&
1941 !(err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))) {
1a348ccc
AG		 1942 pci_using_dac = 1;
1943 } else {
284901a9
YH		 1944 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1945 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
865a21a5 1946 pr_err("No usable DMA configuration, aborting\n");
1a348ccc
AG		 1947 goto err_dma;
1948 }
1949 pci_using_dac = 0;
1950 }
1951
cb001a1f
JP		 1952 err = pci_request_regions(pdev, BDX_DRV_NAME);
1953 if (err)
1a348ccc
AG		 1954 goto err_dma;
1955
1956 pci_set_master(pdev);
1957
1958 pciaddr = pci_resource_start(pdev, 0);
1959 if (!pciaddr) {
1960 err = -EIO;
865a21a5 1961 pr_err("no MMIO resource\n");
1a348ccc
AG		 1962 goto err_out_res;
1963 }
cb001a1f
JP		 1964 regionSize = pci_resource_len(pdev, 0);
1965 if (regionSize < BDX_REGS_SIZE) {
1a348ccc 1966 err = -EIO;
865a21a5 1967 pr_err("MMIO resource (%x) too small\n", regionSize);
1a348ccc
AG		 1968 goto err_out_res;
1969 }
1970
1971 nic->regs = ioremap(pciaddr, regionSize);
1972 if (!nic->regs) {
1973 err = -EIO;
865a21a5 1974 pr_err("ioremap failed\n");
1a348ccc
AG		 1975 goto err_out_res;
1976 }
1977
1978 if (pdev->irq < 2) {
1979 err = -EIO;
865a21a5 1980 pr_err("invalid irq (%d)\n", pdev->irq);
1a348ccc
AG		 1981 goto err_out_iomap;
1982 }
1983 pci_set_drvdata(pdev, nic);
1984
1985 if (pdev->device == 0x3014)
1986 nic->port_num = 2;
1987 else
1988 nic->port_num = 1;
1989
1990 print_hw_id(pdev);
1991
1992 bdx_hw_reset_direct(nic->regs);
1993
1994 nic->irq_type = IRQ_INTX;
1995#ifdef BDX_MSI
1996 if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) {
cb001a1f
JP		 1997 err = pci_enable_msi(pdev);
1998 if (err)
865a21a5 1999 pr_err("Can't eneble msi. error is %d\n", err);
1a348ccc
AG		 2000 else
2001 nic->irq_type = IRQ_MSI;
2002 } else
2003 DBG("HW does not support MSI\n");
2004#endif
2005
2006 /************** netdev **************/
2007 for (port = 0; port < nic->port_num; port++) {
cb001a1f
JP		 2008 ndev = alloc_etherdev(sizeof(struct bdx_priv));
2009 if (!ndev) {
1a348ccc 2010 err = -ENOMEM;
865a21a5 2011 pr_err("alloc_etherdev failed\n");
1a348ccc
AG		 2012 goto err_out_iomap;
2013 }
2014
2f30b1f6 2015 ndev->netdev_ops = &bdx_netdev_ops;
1a348ccc 2016 ndev->tx_queue_len = BDX_NDEV_TXQ_LEN;
1a348ccc
AG		 2017
2018 bdx_ethtool_ops(ndev); /* ethtool interface */
2019
2020 /* these fields are used for info purposes only
2021 * so we can have them same for all ports of the board */
2022 ndev->if_port = port;
2023 ndev->base_addr = pciaddr;
2024 ndev->mem_start = pciaddr;
2025 ndev->mem_end = pciaddr + regionSize;
2026 ndev->irq = pdev->irq;
2027 ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO
2028 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
2029 NETIF_F_HW_VLAN_FILTER
2030 /*| NETIF_F_FRAGLIST */
2031 ;
2032
2033 if (pci_using_dac)
2034 ndev->features |= NETIF_F_HIGHDMA;
2035
2036 /************** priv ****************/
8f15ea42 2037 priv = nic->priv[port] = netdev_priv(ndev);
1a348ccc
AG		 2038
2039 memset(priv, 0, sizeof(struct bdx_priv));
2040 priv->pBdxRegs = nic->regs + port * 0x8000;
2041 priv->port = port;
2042 priv->pdev = pdev;
2043 priv->ndev = ndev;
2044 priv->nic = nic;
2045 priv->msg_enable = BDX_DEF_MSG_ENABLE;
2046
2047 netif_napi_add(ndev, &priv->napi, bdx_poll, 64);
2048
2049 if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) {
2050 DBG("HW statistics not supported\n");
2051 priv->stats_flag = 0;
2052 } else {
2053 priv->stats_flag = 1;
2054 }
2055
2056 /* Initialize fifo sizes. */
2057 priv->txd_size = 2;
2058 priv->txf_size = 2;
2059 priv->rxd_size = 2;
2060 priv->rxf_size = 3;
2061
2062 /* Initialize the initial coalescing registers. */
2063 priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12);
2064 priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12);
2065
2066 /* ndev->xmit_lock spinlock is not used.
2067 * Private priv->tx_lock is used for synchronization
2068 * between transmit and TX irq cleanup. In addition
2069 * set multicast list callback has to use priv->tx_lock.
2070 */
2071#ifdef BDX_LLTX
2072 ndev->features |= NETIF_F_LLTX;
2073#endif
2074 spin_lock_init(&priv->tx_lock);
2075
2076 /*bdx_hw_reset(priv); */
2077 if (bdx_read_mac(priv)) {
865a21a5 2078 pr_err("load MAC address failed\n");
1a348ccc
AG		 2079 goto err_out_iomap;
2080 }
2081 SET_NETDEV_DEV(ndev, &pdev->dev);
cb001a1f
JP		 2082 err = register_netdev(ndev);
2083 if (err) {
865a21a5 2084 pr_err("register_netdev failed\n");
1a348ccc
AG		 2085 goto err_out_free;
2086 }
2087 netif_carrier_off(ndev);
2088 netif_stop_queue(ndev);
2089
2090 print_eth_id(ndev);
2091 }
2092 RET(0);
2093
2094err_out_free:
2095 free_netdev(ndev);
2096err_out_iomap:
2097 iounmap(nic->regs);
2098err_out_res:
2099 pci_release_regions(pdev);
2100err_dma:
2101 pci_disable_device(pdev);
bc2618f7 2102err_pci:
1a348ccc
AG		 2103 vfree(nic);
2104
2105 RET(err);
2106}
2107
2108/****************** Ethtool interface *********************/
1a348ccc
AG		 2109/* get strings for statistics counters */
2110static const char
2111 bdx_stat_names[][ETH_GSTRING_LEN] = {
2112 "InUCast", /* 0x7200 */
2113 "InMCast", /* 0x7210 */
2114 "InBCast", /* 0x7220 */
2115 "InPkts", /* 0x7230 */
2116 "InErrors", /* 0x7240 */
2117 "InDropped", /* 0x7250 */
2118 "FrameTooLong", /* 0x7260 */
2119 "FrameSequenceErrors", /* 0x7270 */
2120 "InVLAN", /* 0x7280 */
2121 "InDroppedDFE", /* 0x7290 */
2122 "InDroppedIntFull", /* 0x72A0 */
2123 "InFrameAlignErrors", /* 0x72B0 */
2124
2125 /* 0x72C0-0x72E0 RSRV */
2126
2127 "OutUCast", /* 0x72F0 */
2128 "OutMCast", /* 0x7300 */
2129 "OutBCast", /* 0x7310 */
2130 "OutPkts", /* 0x7320 */
2131
2132 /* 0x7330-0x7360 RSRV */
2133
2134 "OutVLAN", /* 0x7370 */
2135 "InUCastOctects", /* 0x7380 */
2136 "OutUCastOctects", /* 0x7390 */
2137
2138 /* 0x73A0-0x73B0 RSRV */
2139
2140 "InBCastOctects", /* 0x73C0 */
2141 "OutBCastOctects", /* 0x73D0 */
2142 "InOctects", /* 0x73E0 */
2143 "OutOctects", /* 0x73F0 */
2144};
2145
2146/*
2147 * bdx_get_settings - get device-specific settings
2148 * @netdev
2149 * @ecmd
2150 */
2151static int bdx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
2152{
2153 u32 rdintcm;
2154 u32 tdintcm;
8f15ea42 2155 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2156
2157 rdintcm = priv->rdintcm;
2158 tdintcm = priv->tdintcm;
2159
2160 ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
2161 ecmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
2162 ecmd->speed = SPEED_10000;
2163 ecmd->duplex = DUPLEX_FULL;
2164 ecmd->port = PORT_FIBRE;
2165 ecmd->transceiver = XCVR_EXTERNAL; /* what does it mean? */
2166 ecmd->autoneg = AUTONEG_DISABLE;
2167
2168 /* PCK_TH measures in multiples of FIFO bytes
2169 We translate to packets */
2170 ecmd->maxtxpkt =
2171 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2172 ecmd->maxrxpkt =
2173 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2174
2175 return 0;
2176}
2177
2178/*
2179 * bdx_get_drvinfo - report driver information
2180 * @netdev
2181 * @drvinfo
2182 */
2183static void
2184bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
2185{
8f15ea42 2186 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc 2187
072ee3f9
RK		 2188 strlcat(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver));
2189 strlcat(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version));
2190 strlcat(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
2191 strlcat(drvinfo->bus_info, pci_name(priv->pdev),
1a348ccc
AG		 2192 sizeof(drvinfo->bus_info));
2193
4c3616cd 2194 drvinfo->n_stats = ((priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0);
1a348ccc
AG		 2195 drvinfo->testinfo_len = 0;
2196 drvinfo->regdump_len = 0;
2197 drvinfo->eedump_len = 0;
2198}
2199
2200/*
2201 * bdx_get_rx_csum - report whether receive checksums are turned on or off
2202 * @netdev
2203 */
2204static u32 bdx_get_rx_csum(struct net_device *netdev)
2205{
2206 return 1; /* always on */
2207}
2208
2209/*
2210 * bdx_get_tx_csum - report whether transmit checksums are turned on or off
2211 * @netdev
2212 */
2213static u32 bdx_get_tx_csum(struct net_device *netdev)
2214{
2215 return (netdev->features & NETIF_F_IP_CSUM) != 0;
2216}
2217
2218/*
2219 * bdx_get_coalesce - get interrupt coalescing parameters
2220 * @netdev
2221 * @ecoal
2222 */
2223static int
2224bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2225{
2226 u32 rdintcm;
2227 u32 tdintcm;
8f15ea42 2228 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2229
2230 rdintcm = priv->rdintcm;
2231 tdintcm = priv->tdintcm;
2232
2233 /* PCK_TH measures in multiples of FIFO bytes
2234 We translate to packets */
2235 ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT;
2236 ecoal->rx_max_coalesced_frames =
2237 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2238
2239 ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT;
2240 ecoal->tx_max_coalesced_frames =
2241 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2242
2243 /* adaptive parameters ignored */
2244 return 0;
2245}
2246
2247/*
2248 * bdx_set_coalesce - set interrupt coalescing parameters
2249 * @netdev
2250 * @ecoal
2251 */
2252static int
2253bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2254{
2255 u32 rdintcm;
2256 u32 tdintcm;
8f15ea42 2257 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2258 int rx_coal;
2259 int tx_coal;
2260 int rx_max_coal;
2261 int tx_max_coal;
2262
2263 /* Check for valid input */
2264 rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT;
2265 tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT;
2266 rx_max_coal = ecoal->rx_max_coalesced_frames;
2267 tx_max_coal = ecoal->tx_max_coalesced_frames;
2268
2269 /* Translate from packets to multiples of FIFO bytes */
2270 rx_max_coal =
2271 (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1)
2272 / PCK_TH_MULT);
2273 tx_max_coal =
2274 (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1)
2275 / PCK_TH_MULT);
2276
8e95a202
JP		 2277 if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF) ||
2278 (rx_max_coal > 0xF) || (tx_max_coal > 0xF))
1a348ccc
AG		 2279 return -EINVAL;
2280
2281 rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm),
2282 GET_RXF_TH(priv->rdintcm), rx_max_coal);
2283 tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0,
2284 tx_max_coal);
2285
2286 priv->rdintcm = rdintcm;
2287 priv->tdintcm = tdintcm;
2288
2289 WRITE_REG(priv, regRDINTCM0, rdintcm);
2290 WRITE_REG(priv, regTDINTCM0, tdintcm);
2291
2292 return 0;
2293}
2294
2295/* Convert RX fifo size to number of pending packets */
2296static inline int bdx_rx_fifo_size_to_packets(int rx_size)
2297{
249658d5 2298 return (FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc);
1a348ccc
AG		 2299}
2300
2301/* Convert TX fifo size to number of pending packets */
2302static inline int bdx_tx_fifo_size_to_packets(int tx_size)
2303{
249658d5 2304 return (FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ;
1a348ccc
AG		 2305}
2306
2307/*
2308 * bdx_get_ringparam - report ring sizes
2309 * @netdev
2310 * @ring
2311 */
2312static void
2313bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2314{
8f15ea42 2315 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2316
2317 /*max_pending - the maximum-sized FIFO we allow */
2318 ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3);
2319 ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3);
2320 ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size);
2321 ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size);
2322}
2323
2324/*
2325 * bdx_set_ringparam - set ring sizes
2326 * @netdev
2327 * @ring
2328 */
2329static int
2330bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2331{
8f15ea42 2332 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2333 int rx_size = 0;
2334 int tx_size = 0;
2335
2336 for (; rx_size < 4; rx_size++) {
2337 if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending)
2338 break;
2339 }
2340 if (rx_size == 4)
2341 rx_size = 3;
2342
2343 for (; tx_size < 4; tx_size++) {
2344 if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending)
2345 break;
2346 }
2347 if (tx_size == 4)
2348 tx_size = 3;
2349
2350 /*Is there anything to do? */
8e95a202
JP		 2351 if ((rx_size == priv->rxf_size) &&
2352 (tx_size == priv->txd_size))
1a348ccc
AG		 2353 return 0;
2354
2355 priv->rxf_size = rx_size;
2356 if (rx_size > 1)
2357 priv->rxd_size = rx_size - 1;
2358 else
2359 priv->rxd_size = rx_size;
2360
2361 priv->txf_size = priv->txd_size = tx_size;
2362
2363 if (netif_running(netdev)) {
2364 bdx_close(netdev);
2365 bdx_open(netdev);
2366 }
2367 return 0;
2368}
2369
2370/*
2371 * bdx_get_strings - return a set of strings that describe the requested objects
2372 * @netdev
2373 * @data
2374 */
2375static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2376{
2377 switch (stringset) {
1a348ccc
AG		 2378 case ETH_SS_STATS:
2379 memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names));
2380 break;
2381 }
2382}
2383
2384/*
1ddee09f 2385 * bdx_get_sset_count - return number of statistics or tests
1a348ccc
AG		 2386 * @netdev
2387 */
1ddee09f 2388static int bdx_get_sset_count(struct net_device *netdev, int stringset)
1a348ccc 2389{
8f15ea42 2390 struct bdx_priv *priv = netdev_priv(netdev);
1ddee09f
BH		 2391
2392 switch (stringset) {
2393 case ETH_SS_STATS:
2394 BDX_ASSERT(ARRAY_SIZE(bdx_stat_names)
2395 != sizeof(struct bdx_stats) / sizeof(u64));
249658d5 2396 return (priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0;
1ddee09f 2397 }
249658d5
JP		 2398
2399 return -EINVAL;
1a348ccc
AG		 2400}
2401
2402/*
2403 * bdx_get_ethtool_stats - return device's hardware L2 statistics
2404 * @netdev
2405 * @stats
2406 * @data
2407 */
2408static void bdx_get_ethtool_stats(struct net_device *netdev,
2409 struct ethtool_stats *stats, u64 *data)
2410{
8f15ea42 2411 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2412
2413 if (priv->stats_flag) {
2414
2415 /* Update stats from HW */
2416 bdx_update_stats(priv);
2417
2418 /* Copy data to user buffer */
2419 memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats));
2420 }
2421}
2422
2423/*
2424 * bdx_ethtool_ops - ethtool interface implementation
2425 * @netdev
2426 */
2427static void bdx_ethtool_ops(struct net_device *netdev)
2428{
0fc0b732 2429 static const struct ethtool_ops bdx_ethtool_ops = {
1a348ccc
AG		 2430 .get_settings = bdx_get_settings,
2431 .get_drvinfo = bdx_get_drvinfo,
2432 .get_link = ethtool_op_get_link,
2433 .get_coalesce = bdx_get_coalesce,
2434 .set_coalesce = bdx_set_coalesce,
2435 .get_ringparam = bdx_get_ringparam,
2436 .set_ringparam = bdx_set_ringparam,
2437 .get_rx_csum = bdx_get_rx_csum,
2438 .get_tx_csum = bdx_get_tx_csum,
2439 .get_sg = ethtool_op_get_sg,
2440 .get_tso = ethtool_op_get_tso,
2441 .get_strings = bdx_get_strings,
1ddee09f 2442 .get_sset_count = bdx_get_sset_count,
1a348ccc
AG		 2443 .get_ethtool_stats = bdx_get_ethtool_stats,
2444 };
2445
2446 SET_ETHTOOL_OPS(netdev, &bdx_ethtool_ops);
2447}
2448
2449/**
2450 * bdx_remove - Device Removal Routine
2451 * @pdev: PCI device information struct
2452 *
2453 * bdx_remove is called by the PCI subsystem to alert the driver
2454 * that it should release a PCI device. The could be caused by a
2455 * Hot-Plug event, or because the driver is going to be removed from
2456 * memory.
2457 **/
2458static void __devexit bdx_remove(struct pci_dev *pdev)
2459{
2460 struct pci_nic *nic = pci_get_drvdata(pdev);
2461 struct net_device *ndev;
2462 int port;
2463
2464 for (port = 0; port < nic->port_num; port++) {
2465 ndev = nic->priv[port]->ndev;
2466 unregister_netdev(ndev);
2467 free_netdev(ndev);
2468 }
2469
2470 /*bdx_hw_reset_direct(nic->regs); */
2471#ifdef BDX_MSI
2472 if (nic->irq_type == IRQ_MSI)
2473 pci_disable_msi(pdev);
2474#endif
2475
2476 iounmap(nic->regs);
2477 pci_release_regions(pdev);
2478 pci_disable_device(pdev);
2479 pci_set_drvdata(pdev, NULL);
2480 vfree(nic);
2481
2482 RET();
2483}
2484
2485static struct pci_driver bdx_pci_driver = {
2486 .name = BDX_DRV_NAME,
2487 .id_table = bdx_pci_tbl,
2488 .probe = bdx_probe,
2489 .remove = __devexit_p(bdx_remove),
2490};
2491
2492/*
2493 * print_driver_id - print parameters of the driver build
2494 */
2495static void __init print_driver_id(void)
2496{
865a21a5
JP		 2497 pr_info("%s, %s\n", BDX_DRV_DESC, BDX_DRV_VERSION);
2498 pr_info("Options: hw_csum %s\n", BDX_MSI_STRING);
1a348ccc
AG		 2499}
2500
2501static int __init bdx_module_init(void)
2502{
2503 ENTER;
1a348ccc
AG		 2504 init_txd_sizes();
2505 print_driver_id();
2506 RET(pci_register_driver(&bdx_pci_driver));
2507}
2508
2509module_init(bdx_module_init);
2510
2511static void __exit bdx_module_exit(void)
2512{
2513 ENTER;
2514 pci_unregister_driver(&bdx_pci_driver);
2515 RET();
2516}
2517
2518module_exit(bdx_module_exit);
2519
2520MODULE_LICENSE("GPL");
2521MODULE_AUTHOR(DRIVER_AUTHOR);
2522MODULE_DESCRIPTION(BDX_DRV_DESC);
06e1f9ff 2523MODULE_FIRMWARE("tehuti/firmware.bin");
Clone of davem's net-next-2.6 tree