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drivers/net/tehuti.c: Use (pr|netdev|netif)_<levels> macro helpers
[net-next-2.6.git] / drivers / net / tehuti.c
CommitLineData
1a348ccc
AG		 1/*
2 * Tehuti Networks(R) Network Driver
3 * ethtool interface implementation
4 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12/*
13 * RX HW/SW interaction overview
14 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
15 * There are 2 types of RX communication channels betwean driver and NIC.
16 * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
17 * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
18 * info about buffer's location, size and ID. An ID field is used to identify a
19 * buffer when it's returned with data via RXD Fifo (see below)
20 * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
21 * filled by HW and is readen by SW. Each descriptor holds status and ID.
22 * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
23 * via dma moves it into host memory, builds new RXD descriptor with same ID,
24 * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
25 *
26 * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos.
27 * One holds 1.5K packets and another - 26K packets. Depending on incoming
28 * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
29 * filled with data, HW builds new RXD descriptor for it and push it into single
30 * RXD Fifo.
31 *
32 * RX SW Data Structures
33 * ~~~~~~~~~~~~~~~~~~~~~
34 * skb db - used to keep track of all skbs owned by SW and their dma addresses.
35 * For RX case, ownership lasts from allocating new empty skb for RXF until
36 * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own
37 * skb db. Implemented as array with bitmask.
38 * fifo - keeps info about fifo's size and location, relevant HW registers,
39 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
40 * Implemented as simple struct.
41 *
42 * RX SW Execution Flow
43 * ~~~~~~~~~~~~~~~~~~~~
44 * Upon initialization (ifconfig up) driver creates RX fifos and initializes
45 * relevant registers. At the end of init phase, driver enables interrupts.
46 * NIC sees that there is no RXF buffers and raises
47 * RD_INTR interrupt, isr fills skbs and Rx begins.
48 * Driver has two receive operation modes:
49 * NAPI - interrupt-driven mixed with polling
50 * interrupt-driven only
51 *
52 * Interrupt-driven only flow is following. When buffer is ready, HW raises
53 * interrupt and isr is called. isr collects all available packets
54 * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit.
55
56 * Rx buffer allocation note
57 * ~~~~~~~~~~~~~~~~~~~~~~~~~
58 * Driver cares to feed such amount of RxF descriptors that respective amount of
59 * RxD descriptors can not fill entire RxD fifo. The main reason is lack of
60 * overflow check in Bordeaux for RxD fifo free/used size.
61 * FIXME: this is NOT fully implemented, more work should be done
62 *
63 */
64
865a21a5
JP		 65#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
66
1a348ccc 67#include "tehuti.h"
1a348ccc 68
865a21a5 69static struct pci_device_id __devinitdata bdx_pci_tbl[] = {
1a348ccc
AG		 70 {0x1FC9, 0x3009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
71 {0x1FC9, 0x3010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
72 {0x1FC9, 0x3014, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
73 {0}
74};
75
76MODULE_DEVICE_TABLE(pci, bdx_pci_tbl);
77
78/* Definitions needed by ISR or NAPI functions */
79static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f);
80static void bdx_tx_cleanup(struct bdx_priv *priv);
81static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget);
82
83/* Definitions needed by FW loading */
84static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size);
85
86/* Definitions needed by hw_start */
87static int bdx_tx_init(struct bdx_priv *priv);
88static int bdx_rx_init(struct bdx_priv *priv);
89
90/* Definitions needed by bdx_close */
91static void bdx_rx_free(struct bdx_priv *priv);
92static void bdx_tx_free(struct bdx_priv *priv);
93
94/* Definitions needed by bdx_probe */
95static void bdx_ethtool_ops(struct net_device *netdev);
96
97/*************************************************************************
98 * Print Info *
99 *************************************************************************/
100
101static void print_hw_id(struct pci_dev *pdev)
102{
103 struct pci_nic *nic = pci_get_drvdata(pdev);
104 u16 pci_link_status = 0;
105 u16 pci_ctrl = 0;
106
107 pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status);
108 pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl);
109
865a21a5
JP		 110 pr_info("%s%s\n", BDX_NIC_NAME,
111 nic->port_num == 1 ? "" : ", 2-Port");
112 pr_info("srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n",
113 readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF,
114 readl(nic->regs + FPGA_SEED),
115 GET_LINK_STATUS_LANES(pci_link_status),
116 GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl));
1a348ccc
AG		 117}
118
119static void print_fw_id(struct pci_nic *nic)
120{
865a21a5 121 pr_info("fw 0x%x\n", readl(nic->regs + FW_VER));
1a348ccc
AG		 122}
123
124static void print_eth_id(struct net_device *ndev)
125{
865a21a5
JP		 126 netdev_info(ndev, "%s, Port %c\n",
127 BDX_NIC_NAME, (ndev->if_port == 0) ? 'A' : 'B');
1a348ccc
AG		 128
129}
130
131/*************************************************************************
132 * Code *
133 *************************************************************************/
134
135#define bdx_enable_interrupts(priv) \
136 do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
137#define bdx_disable_interrupts(priv) \
138 do { WRITE_REG(priv, regIMR, 0); } while (0)
139
140/* bdx_fifo_init
141 * create TX/RX descriptor fifo for host-NIC communication.
142 * 1K extra space is allocated at the end of the fifo to simplify
143 * processing of descriptors that wraps around fifo's end
144 * @priv - NIC private structure
145 * @f - fifo to initialize
146 * @fsz_type - fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
147 * @reg_XXX - offsets of registers relative to base address
148 *
149 * Returns 0 on success, negative value on failure
150 *
151 */
152static int
153bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type,
154 u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR)
155{
156 u16 memsz = FIFO_SIZE * (1 << fsz_type);
157
158 memset(f, 0, sizeof(struct fifo));
159 /* pci_alloc_consistent gives us 4k-aligned memory */
160 f->va = pci_alloc_consistent(priv->pdev,
161 memsz + FIFO_EXTRA_SPACE, &f->da);
162 if (!f->va) {
865a21a5 163 pr_err("pci_alloc_consistent failed\n");
1a348ccc
AG		 164 RET(-ENOMEM);
165 }
166 f->reg_CFG0 = reg_CFG0;
167 f->reg_CFG1 = reg_CFG1;
168 f->reg_RPTR = reg_RPTR;
169 f->reg_WPTR = reg_WPTR;
170 f->rptr = 0;
171 f->wptr = 0;
172 f->memsz = memsz;
173 f->size_mask = memsz - 1;
174 WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
175 WRITE_REG(priv, reg_CFG1, H32_64(f->da));
176
177 RET(0);
178}
179
180/* bdx_fifo_free - free all resources used by fifo
181 * @priv - NIC private structure
182 * @f - fifo to release
183 */
184static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f)
185{
186 ENTER;
187 if (f->va) {
188 pci_free_consistent(priv->pdev,
189 f->memsz + FIFO_EXTRA_SPACE, f->va, f->da);
190 f->va = NULL;
191 }
192 RET();
193}
194
195/*
196 * bdx_link_changed - notifies OS about hw link state.
197 * @bdx_priv - hw adapter structure
198 */
199static void bdx_link_changed(struct bdx_priv *priv)
200{
201 u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT;
202
203 if (!link) {
204 if (netif_carrier_ok(priv->ndev)) {
205 netif_stop_queue(priv->ndev);
206 netif_carrier_off(priv->ndev);
865a21a5 207 netdev_err(priv->ndev, "Link Down\n");
1a348ccc
AG		 208 }
209 } else {
210 if (!netif_carrier_ok(priv->ndev)) {
211 netif_wake_queue(priv->ndev);
212 netif_carrier_on(priv->ndev);
865a21a5 213 netdev_err(priv->ndev, "Link Up\n");
1a348ccc
AG		 214 }
215 }
216}
217
218static void bdx_isr_extra(struct bdx_priv *priv, u32 isr)
219{
220 if (isr & IR_RX_FREE_0) {
221 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
222 DBG("RX_FREE_0\n");
223 }
224
225 if (isr & IR_LNKCHG0)
226 bdx_link_changed(priv);
227
228 if (isr & IR_PCIE_LINK)
865a21a5 229 netdev_err(priv->ndev, "PCI-E Link Fault\n");
1a348ccc
AG		 230
231 if (isr & IR_PCIE_TOUT)
865a21a5 232 netdev_err(priv->ndev, "PCI-E Time Out\n");
1a348ccc
AG		 233
234}
235
236/* bdx_isr - Interrupt Service Routine for Bordeaux NIC
237 * @irq - interrupt number
238 * @ndev - network device
239 * @regs - CPU registers
240 *
241 * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise
242 *
243 * It reads ISR register to know interrupt reasons, and proceed them one by one.
244 * Reasons of interest are:
245 * RX_DESC - new packet has arrived and RXD fifo holds its descriptor
246 * RX_FREE - number of free Rx buffers in RXF fifo gets low
247 * TX_FREE - packet was transmited and RXF fifo holds its descriptor
248 */
249
250static irqreturn_t bdx_isr_napi(int irq, void *dev)
251{
252 struct net_device *ndev = dev;
8f15ea42 253 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 254 u32 isr;
255
256 ENTER;
257 isr = (READ_REG(priv, regISR) & IR_RUN);
258 if (unlikely(!isr)) {
259 bdx_enable_interrupts(priv);
260 return IRQ_NONE; /* Not our interrupt */
261 }
262
263 if (isr & IR_EXTRA)
264 bdx_isr_extra(priv, isr);
265
266 if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) {
288379f0
BH		 267 if (likely(napi_schedule_prep(&priv->napi))) {
268 __napi_schedule(&priv->napi);
1a348ccc
AG		 269 RET(IRQ_HANDLED);
270 } else {
271 /* NOTE: we get here if intr has slipped into window
272 * between these lines in bdx_poll:
273 * bdx_enable_interrupts(priv);
274 * return 0;
275 * currently intrs are disabled (since we read ISR),
276 * and we have failed to register next poll.
277 * so we read the regs to trigger chip
278 * and allow further interupts. */
279 READ_REG(priv, regTXF_WPTR_0);
280 READ_REG(priv, regRXD_WPTR_0);
281 }
282 }
283
284 bdx_enable_interrupts(priv);
285 RET(IRQ_HANDLED);
286}
287
288static int bdx_poll(struct napi_struct *napi, int budget)
289{
290 struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi);
1a348ccc
AG		 291 int work_done;
292
293 ENTER;
294 bdx_tx_cleanup(priv);
295 work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget);
296 if ((work_done < budget) ||
297 (priv->napi_stop++ >= 30)) {
298 DBG("rx poll is done. backing to isr-driven\n");
299
300 /* from time to time we exit to let NAPI layer release
301 * device lock and allow waiting tasks (eg rmmod) to advance) */
302 priv->napi_stop = 0;
303
288379f0 304 napi_complete(napi);
1a348ccc
AG		 305 bdx_enable_interrupts(priv);
306 }
307 return work_done;
308}
309
310/* bdx_fw_load - loads firmware to NIC
311 * @priv - NIC private structure
312 * Firmware is loaded via TXD fifo, so it must be initialized first.
313 * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC
314 * can have few of them). So all drivers use semaphore register to choose one
315 * that will actually load FW to NIC.
316 */
317
318static int bdx_fw_load(struct bdx_priv *priv)
319{
06e1f9ff 320 const struct firmware *fw = NULL;
1a348ccc 321 int master, i;
06e1f9ff 322 int rc;
1a348ccc
AG		 323
324 ENTER;
325 master = READ_REG(priv, regINIT_SEMAPHORE);
326 if (!READ_REG(priv, regINIT_STATUS) && master) {
06e1f9ff
BH		 327 rc = request_firmware(&fw, "tehuti/firmware.bin", &priv->pdev->dev);
328 if (rc)
329 goto out;
330 bdx_tx_push_desc_safe(priv, (char *)fw->data, fw->size);
1a348ccc
AG		 331 mdelay(100);
332 }
333 for (i = 0; i < 200; i++) {
06e1f9ff
BH		 334 if (READ_REG(priv, regINIT_STATUS)) {
335 rc = 0;
336 goto out;
337 }
1a348ccc
AG		 338 mdelay(2);
339 }
06e1f9ff
BH		 340 rc = -EIO;
341out:
1a348ccc
AG		 342 if (master)
343 WRITE_REG(priv, regINIT_SEMAPHORE, 1);
06e1f9ff
BH		 344 if (fw)
345 release_firmware(fw);
1a348ccc 346
06e1f9ff 347 if (rc) {
865a21a5 348 netdev_err(priv->ndev, "firmware loading failed\n");
06e1f9ff
BH		 349 if (rc == -EIO)
350 DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",
351 READ_REG(priv, regVPC),
352 READ_REG(priv, regVIC),
353 READ_REG(priv, regINIT_STATUS), i);
354 RET(rc);
1a348ccc
AG		 355 } else {
356 DBG("%s: firmware loading success\n", priv->ndev->name);
357 RET(0);
358 }
359}
360
361static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv)
362{
363 u32 val;
364
365 ENTER;
366 DBG("mac0=%x mac1=%x mac2=%x\n",
367 READ_REG(priv, regUNC_MAC0_A),
368 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
369
370 val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);
371 WRITE_REG(priv, regUNC_MAC2_A, val);
372 val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]);
373 WRITE_REG(priv, regUNC_MAC1_A, val);
374 val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]);
375 WRITE_REG(priv, regUNC_MAC0_A, val);
376
377 DBG("mac0=%x mac1=%x mac2=%x\n",
378 READ_REG(priv, regUNC_MAC0_A),
379 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
380 RET();
381}
382
383/* bdx_hw_start - inits registers and starts HW's Rx and Tx engines
384 * @priv - NIC private structure
385 */
386static int bdx_hw_start(struct bdx_priv *priv)
387{
388 int rc = -EIO;
389 struct net_device *ndev = priv->ndev;
390
391 ENTER;
392 bdx_link_changed(priv);
393
394 /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */
395 WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);
396 WRITE_REG(priv, regPAUSE_QUANT, 0x96);
397 WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);
398 WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);
399 WRITE_REG(priv, regRX_FULLNESS, 0);
400 WRITE_REG(priv, regTX_FULLNESS, 0);
401 WRITE_REG(priv, regCTRLST,
402 regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA);
403
404 WRITE_REG(priv, regVGLB, 0);
405 WRITE_REG(priv, regMAX_FRAME_A,
406 priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL);
407
408 DBG("RDINTCM=%08x\n", priv->rdintcm); /*NOTE: test script uses this */
409 WRITE_REG(priv, regRDINTCM0, priv->rdintcm);
410 WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */
411
412 DBG("TDINTCM=%08x\n", priv->tdintcm); /*NOTE: test script uses this */
413 WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */
414
415 /* Enable timer interrupt once in 2 secs. */
416 /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */
417 bdx_restore_mac(priv->ndev, priv);
418
419 WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |
420 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB);
421
422#define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI)?0:IRQF_SHARED)
a0607fd3 423 if ((rc = request_irq(priv->pdev->irq, bdx_isr_napi, BDX_IRQ_TYPE,
1a348ccc
AG		 424 ndev->name, ndev)))
425 goto err_irq;
426 bdx_enable_interrupts(priv);
427
428 RET(0);
429
430err_irq:
431 RET(rc);
432}
433
434static void bdx_hw_stop(struct bdx_priv *priv)
435{
436 ENTER;
437 bdx_disable_interrupts(priv);
438 free_irq(priv->pdev->irq, priv->ndev);
439
440 netif_carrier_off(priv->ndev);
441 netif_stop_queue(priv->ndev);
442
443 RET();
444}
445
446static int bdx_hw_reset_direct(void __iomem *regs)
447{
448 u32 val, i;
449 ENTER;
450
451 /* reset sequences: read, write 1, read, write 0 */
452 val = readl(regs + regCLKPLL);
453 writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);
454 udelay(50);
455 val = readl(regs + regCLKPLL);
456 writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL);
457
458 /* check that the PLLs are locked and reset ended */
459 for (i = 0; i < 70; i++, mdelay(10))
460 if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
461 /* do any PCI-E read transaction */
462 readl(regs + regRXD_CFG0_0);
463 return 0;
464 }
865a21a5 465 pr_err("HW reset failed\n");
1a348ccc
AG		 466 return 1; /* failure */
467}
468
469static int bdx_hw_reset(struct bdx_priv *priv)
470{
471 u32 val, i;
472 ENTER;
473
474 if (priv->port == 0) {
475 /* reset sequences: read, write 1, read, write 0 */
476 val = READ_REG(priv, regCLKPLL);
477 WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);
478 udelay(50);
479 val = READ_REG(priv, regCLKPLL);
480 WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);
481 }
482 /* check that the PLLs are locked and reset ended */
483 for (i = 0; i < 70; i++, mdelay(10))
484 if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
485 /* do any PCI-E read transaction */
486 READ_REG(priv, regRXD_CFG0_0);
487 return 0;
488 }
865a21a5 489 pr_err("HW reset failed\n");
1a348ccc
AG		 490 return 1; /* failure */
491}
492
493static int bdx_sw_reset(struct bdx_priv *priv)
494{
495 int i;
496
497 ENTER;
498 /* 1. load MAC (obsolete) */
499 /* 2. disable Rx (and Tx) */
500 WRITE_REG(priv, regGMAC_RXF_A, 0);
501 mdelay(100);
502 /* 3. disable port */
503 WRITE_REG(priv, regDIS_PORT, 1);
504 /* 4. disable queue */
505 WRITE_REG(priv, regDIS_QU, 1);
506 /* 5. wait until hw is disabled */
507 for (i = 0; i < 50; i++) {
508 if (READ_REG(priv, regRST_PORT) & 1)
509 break;
510 mdelay(10);
511 }
512 if (i == 50)
865a21a5 513 netdev_err(priv->ndev, "SW reset timeout. continuing anyway\n");
1a348ccc
AG		 514
515 /* 6. disable intrs */
516 WRITE_REG(priv, regRDINTCM0, 0);
517 WRITE_REG(priv, regTDINTCM0, 0);
518 WRITE_REG(priv, regIMR, 0);
519 READ_REG(priv, regISR);
520
521 /* 7. reset queue */
522 WRITE_REG(priv, regRST_QU, 1);
523 /* 8. reset port */
524 WRITE_REG(priv, regRST_PORT, 1);
525 /* 9. zero all read and write pointers */
526 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
527 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
528 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
529 WRITE_REG(priv, i, 0);
530 /* 10. unseet port disable */
531 WRITE_REG(priv, regDIS_PORT, 0);
532 /* 11. unset queue disable */
533 WRITE_REG(priv, regDIS_QU, 0);
534 /* 12. unset queue reset */
535 WRITE_REG(priv, regRST_QU, 0);
536 /* 13. unset port reset */
537 WRITE_REG(priv, regRST_PORT, 0);
538 /* 14. enable Rx */
539 /* skiped. will be done later */
540 /* 15. save MAC (obsolete) */
541 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
542 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
543
544 RET(0);
545}
546
547/* bdx_reset - performs right type of reset depending on hw type */
548static int bdx_reset(struct bdx_priv *priv)
549{
550 ENTER;
551 RET((priv->pdev->device == 0x3009)
552 ? bdx_hw_reset(priv)
553 : bdx_sw_reset(priv));
554}
555
556/**
557 * bdx_close - Disables a network interface
558 * @netdev: network interface device structure
559 *
560 * Returns 0, this is not allowed to fail
561 *
562 * The close entry point is called when an interface is de-activated
563 * by the OS. The hardware is still under the drivers control, but
564 * needs to be disabled. A global MAC reset is issued to stop the
565 * hardware, and all transmit and receive resources are freed.
566 **/
567static int bdx_close(struct net_device *ndev)
568{
569 struct bdx_priv *priv = NULL;
570
571 ENTER;
8f15ea42 572 priv = netdev_priv(ndev);
1a348ccc
AG		 573
574 napi_disable(&priv->napi);
575
576 bdx_reset(priv);
577 bdx_hw_stop(priv);
578 bdx_rx_free(priv);
579 bdx_tx_free(priv);
580 RET(0);
581}
582
583/**
584 * bdx_open - Called when a network interface is made active
585 * @netdev: network interface device structure
586 *
587 * Returns 0 on success, negative value on failure
588 *
589 * The open entry point is called when a network interface is made
590 * active by the system (IFF_UP). At this point all resources needed
591 * for transmit and receive operations are allocated, the interrupt
592 * handler is registered with the OS, the watchdog timer is started,
593 * and the stack is notified that the interface is ready.
594 **/
595static int bdx_open(struct net_device *ndev)
596{
597 struct bdx_priv *priv;
598 int rc;
599
600 ENTER;
8f15ea42 601 priv = netdev_priv(ndev);
1a348ccc
AG		 602 bdx_reset(priv);
603 if (netif_running(ndev))
604 netif_stop_queue(priv->ndev);
605
606 if ((rc = bdx_tx_init(priv)))
607 goto err;
608
609 if ((rc = bdx_rx_init(priv)))
610 goto err;
611
612 if ((rc = bdx_fw_load(priv)))
613 goto err;
614
615 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
616
617 if ((rc = bdx_hw_start(priv)))
618 goto err;
619
620 napi_enable(&priv->napi);
621
622 print_fw_id(priv->nic);
623
624 RET(0);
625
626err:
627 bdx_close(ndev);
628 RET(rc);
629}
630
6131a260
FR		 631static int bdx_range_check(struct bdx_priv *priv, u32 offset)
632{
633 return (offset > (u32) (BDX_REGS_SIZE / priv->nic->port_num)) ?
634 -EINVAL : 0;
635}
636
1a348ccc
AG		 637static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd)
638{
8f15ea42 639 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 640 u32 data[3];
641 int error;
642
643 ENTER;
644
645 DBG("jiffies=%ld cmd=%d\n", jiffies, cmd);
646 if (cmd != SIOCDEVPRIVATE) {
647 error = copy_from_user(data, ifr->ifr_data, sizeof(data));
648 if (error) {
865a21a5 649 pr_err("cant copy from user\n");
1a348ccc
AG		 650 RET(error);
651 }
652 DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]);
653 }
654
62035542 655 if (!capable(CAP_SYS_RAWIO))
f946dffe
JG		 656 return -EPERM;
657
1a348ccc
AG		 658 switch (data[0]) {
659
660 case BDX_OP_READ:
6131a260
FR		 661 error = bdx_range_check(priv, data[1]);
662 if (error < 0)
663 return error;
1a348ccc
AG		 664 data[2] = READ_REG(priv, data[1]);
665 DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2],
666 data[2]);
667 error = copy_to_user(ifr->ifr_data, data, sizeof(data));
668 if (error)
669 RET(error);
670 break;
671
672 case BDX_OP_WRITE:
6131a260
FR		 673 error = bdx_range_check(priv, data[1]);
674 if (error < 0)
675 return error;
1a348ccc
AG		 676 WRITE_REG(priv, data[1], data[2]);
677 DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]);
678 break;
679
680 default:
681 RET(-EOPNOTSUPP);
682 }
683 return 0;
684}
685
686static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
687{
688 ENTER;
689 if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15))
690 RET(bdx_ioctl_priv(ndev, ifr, cmd));
691 else
692 RET(-EOPNOTSUPP);
693}
694
695/*
696 * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid
697 * by passing VLAN filter table to hardware
698 * @ndev network device
699 * @vid VLAN vid
700 * @op add or kill operation
701 */
702static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable)
703{
8f15ea42 704 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 705 u32 reg, bit, val;
706
707 ENTER;
708 DBG2("vid=%d value=%d\n", (int)vid, enable);
709 if (unlikely(vid >= 4096)) {
865a21a5 710 pr_err("invalid VID: %u (> 4096)\n", vid);
1a348ccc
AG		 711 RET();
712 }
713 reg = regVLAN_0 + (vid / 32) * 4;
714 bit = 1 << vid % 32;
715 val = READ_REG(priv, reg);
716 DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit);
717 if (enable)
718 val |= bit;
719 else
720 val &= ~bit;
721 DBG2("new val %x\n", val);
722 WRITE_REG(priv, reg, val);
723 RET();
724}
725
726/*
727 * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table
728 * @ndev network device
729 * @vid VLAN vid to add
730 */
731static void bdx_vlan_rx_add_vid(struct net_device *ndev, uint16_t vid)
732{
733 __bdx_vlan_rx_vid(ndev, vid, 1);
734}
735
736/*
737 * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table
738 * @ndev network device
739 * @vid VLAN vid to kill
740 */
741static void bdx_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid)
742{
743 __bdx_vlan_rx_vid(ndev, vid, 0);
744}
745
746/*
747 * bdx_vlan_rx_register - kernel hook for adding VLAN group
748 * @ndev network device
749 * @grp VLAN group
750 */
751static void
752bdx_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
753{
8f15ea42 754 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 755
756 ENTER;
757 DBG("device='%s', group='%p'\n", ndev->name, grp);
758 priv->vlgrp = grp;
759 RET();
760}
761
762/**
763 * bdx_change_mtu - Change the Maximum Transfer Unit
764 * @netdev: network interface device structure
765 * @new_mtu: new value for maximum frame size
766 *
767 * Returns 0 on success, negative on failure
768 */
769static int bdx_change_mtu(struct net_device *ndev, int new_mtu)
770{
1a348ccc
AG		 771 ENTER;
772
773 if (new_mtu == ndev->mtu)
774 RET(0);
775
776 /* enforce minimum frame size */
777 if (new_mtu < ETH_ZLEN) {
865a21a5
JP		 778 netdev_err(ndev, "mtu %d is less then minimal %d\n",
779 new_mtu, ETH_ZLEN);
1a348ccc
AG		 780 RET(-EINVAL);
781 }
782
783 ndev->mtu = new_mtu;
784 if (netif_running(ndev)) {
785 bdx_close(ndev);
786 bdx_open(ndev);
787 }
788 RET(0);
789}
790
791static void bdx_setmulti(struct net_device *ndev)
792{
8f15ea42 793 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 794
795 u32 rxf_val =
796 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN;
797 int i;
798
799 ENTER;
800 /* IMF - imperfect (hash) rx multicat filter */
801 /* PMF - perfect rx multicat filter */
802
803 /* FIXME: RXE(OFF) */
804 if (ndev->flags & IFF_PROMISC) {
805 rxf_val |= GMAC_RX_FILTER_PRM;
806 } else if (ndev->flags & IFF_ALLMULTI) {
807 /* set IMF to accept all multicast frmaes */
808 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
809 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);
4cd24eaf 810 } else if (!netdev_mc_empty(ndev)) {
1a348ccc
AG		 811 u8 hash;
812 struct dev_mc_list *mclist;
813 u32 reg, val;
814
815 /* set IMF to deny all multicast frames */
816 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
817 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);
818 /* set PMF to deny all multicast frames */
819 for (i = 0; i < MAC_MCST_NUM; i++) {
820 WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);
821 WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);
822 }
823
824 /* use PMF to accept first MAC_MCST_NUM (15) addresses */
825 /* TBD: sort addreses and write them in ascending order
826 * into RX_MAC_MCST regs. we skip this phase now and accept ALL
827 * multicast frames throu IMF */
828 mclist = ndev->mc_list;
829
830 /* accept the rest of addresses throu IMF */
831 for (; mclist; mclist = mclist->next) {
832 hash = 0;
833 for (i = 0; i < ETH_ALEN; i++)
834 hash ^= mclist->dmi_addr[i];
835 reg = regRX_MCST_HASH0 + ((hash >> 5) << 2);
836 val = READ_REG(priv, reg);
837 val |= (1 << (hash % 32));
838 WRITE_REG(priv, reg, val);
839 }
840
841 } else {
4cd24eaf 842 DBG("only own mac %d\n", netdev_mc_count(ndev));
1a348ccc
AG		 843 rxf_val |= GMAC_RX_FILTER_AB;
844 }
845 WRITE_REG(priv, regGMAC_RXF_A, rxf_val);
846 /* enable RX */
847 /* FIXME: RXE(ON) */
848 RET();
849}
850
851static int bdx_set_mac(struct net_device *ndev, void *p)
852{
8f15ea42 853 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 854 struct sockaddr *addr = p;
855
856 ENTER;
857 /*
858 if (netif_running(dev))
859 return -EBUSY
860 */
861 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
862 bdx_restore_mac(ndev, priv);
863 RET(0);
864}
865
866static int bdx_read_mac(struct bdx_priv *priv)
867{
868 u16 macAddress[3], i;
869 ENTER;
870
871 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
872 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
873 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
874 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
875 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
876 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
877 for (i = 0; i < 3; i++) {
878 priv->ndev->dev_addr[i * 2 + 1] = macAddress[i];
879 priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8;
880 }
881 RET(0);
882}
883
884static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg)
885{
886 u64 val;
887
888 val = READ_REG(priv, reg);
889 val |= ((u64) READ_REG(priv, reg + 8)) << 32;
890 return val;
891}
892
893/*Do the statistics-update work*/
894static void bdx_update_stats(struct bdx_priv *priv)
895{
896 struct bdx_stats *stats = &priv->hw_stats;
897 u64 *stats_vector = (u64 *) stats;
898 int i;
899 int addr;
900
901 /*Fill HW structure */
902 addr = 0x7200;
903 /*First 12 statistics - 0x7200 - 0x72B0 */
904 for (i = 0; i < 12; i++) {
905 stats_vector[i] = bdx_read_l2stat(priv, addr);
906 addr += 0x10;
907 }
908 BDX_ASSERT(addr != 0x72C0);
909 /* 0x72C0-0x72E0 RSRV */
910 addr = 0x72F0;
911 for (; i < 16; i++) {
912 stats_vector[i] = bdx_read_l2stat(priv, addr);
913 addr += 0x10;
914 }
915 BDX_ASSERT(addr != 0x7330);
916 /* 0x7330-0x7360 RSRV */
917 addr = 0x7370;
918 for (; i < 19; i++) {
919 stats_vector[i] = bdx_read_l2stat(priv, addr);
920 addr += 0x10;
921 }
922 BDX_ASSERT(addr != 0x73A0);
923 /* 0x73A0-0x73B0 RSRV */
924 addr = 0x73C0;
925 for (; i < 23; i++) {
926 stats_vector[i] = bdx_read_l2stat(priv, addr);
927 addr += 0x10;
928 }
929 BDX_ASSERT(addr != 0x7400);
930 BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i);
931}
932
933static struct net_device_stats *bdx_get_stats(struct net_device *ndev)
934{
8f15ea42 935 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 936 struct net_device_stats *net_stat = &priv->net_stats;
937 return net_stat;
938}
939
940static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
941 u16 rxd_vlan);
942static void print_rxfd(struct rxf_desc *rxfd);
943
944/*************************************************************************
945 * Rx DB *
946 *************************************************************************/
947
948static void bdx_rxdb_destroy(struct rxdb *db)
949{
c0feed87 950 vfree(db);
1a348ccc
AG		 951}
952
953static struct rxdb *bdx_rxdb_create(int nelem)
954{
955 struct rxdb *db;
956 int i;
957
958 db = vmalloc(sizeof(struct rxdb)
959 + (nelem * sizeof(int))
960 + (nelem * sizeof(struct rx_map)));
961 if (likely(db != NULL)) {
962 db->stack = (int *)(db + 1);
963 db->elems = (void *)(db->stack + nelem);
964 db->nelem = nelem;
965 db->top = nelem;
966 for (i = 0; i < nelem; i++)
967 db->stack[i] = nelem - i - 1; /* to make first allocs
968 close to db struct*/
969 }
970
971 return db;
972}
973
974static inline int bdx_rxdb_alloc_elem(struct rxdb *db)
975{
976 BDX_ASSERT(db->top <= 0);
977 return db->stack[--(db->top)];
978}
979
980static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n)
981{
982 BDX_ASSERT((n < 0) || (n >= db->nelem));
983 return db->elems + n;
984}
985
986static inline int bdx_rxdb_available(struct rxdb *db)
987{
988 return db->top;
989}
990
991static inline void bdx_rxdb_free_elem(struct rxdb *db, int n)
992{
993 BDX_ASSERT((n >= db->nelem) || (n < 0));
994 db->stack[(db->top)++] = n;
995}
996
997/*************************************************************************
998 * Rx Init *
999 *************************************************************************/
1000
1001/* bdx_rx_init - initialize RX all related HW and SW resources
1002 * @priv - NIC private structure
1003 *
1004 * Returns 0 on success, negative value on failure
1005 *
1006 * It creates rxf and rxd fifos, update relevant HW registers, preallocate
1007 * skb for rx. It assumes that Rx is desabled in HW
1008 * funcs are grouped for better cache usage
1009 *
025dfdaf 1010 * RxD fifo is smaller than RxF fifo by design. Upon high load, RxD will be
1a348ccc
AG		 1011 * filled and packets will be dropped by nic without getting into host or
1012 * cousing interrupt. Anyway, in that condition, host has no chance to proccess
1013 * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
1014 */
1015
1016/* TBD: ensure proper packet size */
1017
1018static int bdx_rx_init(struct bdx_priv *priv)
1019{
1020 ENTER;
ddfce6bb 1021
1a348ccc
AG		 1022 if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size,
1023 regRXD_CFG0_0, regRXD_CFG1_0,
1024 regRXD_RPTR_0, regRXD_WPTR_0))
1025 goto err_mem;
1026 if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size,
1027 regRXF_CFG0_0, regRXF_CFG1_0,
1028 regRXF_RPTR_0, regRXF_WPTR_0))
1029 goto err_mem;
1030 if (!
1031 (priv->rxdb =
1032 bdx_rxdb_create(priv->rxf_fifo0.m.memsz /
1033 sizeof(struct rxf_desc))))
1034 goto err_mem;
1035
1036 priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN;
1037 return 0;
1038
1039err_mem:
865a21a5 1040 netdev_err(priv->ndev, "Rx init failed\n");
1a348ccc
AG		 1041 return -ENOMEM;
1042}
1043
1044/* bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo
1045 * @priv - NIC private structure
1046 * @f - RXF fifo
1047 */
1048static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1049{
1050 struct rx_map *dm;
1051 struct rxdb *db = priv->rxdb;
1052 u16 i;
1053
1054 ENTER;
1055 DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db),
1056 db->nelem - bdx_rxdb_available(db));
1057 while (bdx_rxdb_available(db) > 0) {
1058 i = bdx_rxdb_alloc_elem(db);
1059 dm = bdx_rxdb_addr_elem(db, i);
1060 dm->dma = 0;
1061 }
1062 for (i = 0; i < db->nelem; i++) {
1063 dm = bdx_rxdb_addr_elem(db, i);
1064 if (dm->dma) {
1065 pci_unmap_single(priv->pdev,
1066 dm->dma, f->m.pktsz,
1067 PCI_DMA_FROMDEVICE);
1068 dev_kfree_skb(dm->skb);
1069 }
1070 }
1071}
1072
1073/* bdx_rx_free - release all Rx resources
1074 * @priv - NIC private structure
1075 * It assumes that Rx is desabled in HW
1076 */
1077static void bdx_rx_free(struct bdx_priv *priv)
1078{
1079 ENTER;
1080 if (priv->rxdb) {
1081 bdx_rx_free_skbs(priv, &priv->rxf_fifo0);
1082 bdx_rxdb_destroy(priv->rxdb);
1083 priv->rxdb = NULL;
1084 }
1085 bdx_fifo_free(priv, &priv->rxf_fifo0.m);
1086 bdx_fifo_free(priv, &priv->rxd_fifo0.m);
1087
1088 RET();
1089}
1090
1091/*************************************************************************
1092 * Rx Engine *
1093 *************************************************************************/
1094
1095/* bdx_rx_alloc_skbs - fill rxf fifo with new skbs
1096 * @priv - nic's private structure
1097 * @f - RXF fifo that needs skbs
1098 * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo.
1099 * skb's virtual and physical addresses are stored in skb db.
1100 * To calculate free space, func uses cached values of RPTR and WPTR
1101 * When needed, it also updates RPTR and WPTR.
1102 */
1103
1104/* TBD: do not update WPTR if no desc were written */
1105
1106static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1107{
1108 struct sk_buff *skb;
1109 struct rxf_desc *rxfd;
1110 struct rx_map *dm;
1111 int dno, delta, idx;
1112 struct rxdb *db = priv->rxdb;
1113
1114 ENTER;
1115 dno = bdx_rxdb_available(db) - 1;
1116 while (dno > 0) {
1117 if (!(skb = dev_alloc_skb(f->m.pktsz + NET_IP_ALIGN))) {
865a21a5 1118 pr_err("NO MEM: dev_alloc_skb failed\n");
1a348ccc
AG		 1119 break;
1120 }
1121 skb->dev = priv->ndev;
1122 skb_reserve(skb, NET_IP_ALIGN);
1123
1124 idx = bdx_rxdb_alloc_elem(db);
1125 dm = bdx_rxdb_addr_elem(db, idx);
1126 dm->dma = pci_map_single(priv->pdev,
1127 skb->data, f->m.pktsz,
1128 PCI_DMA_FROMDEVICE);
1129 dm->skb = skb;
1130 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1131 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1132 rxfd->va_lo = idx;
1133 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1134 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1135 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1136 print_rxfd(rxfd);
1137
1138 f->m.wptr += sizeof(struct rxf_desc);
1139 delta = f->m.wptr - f->m.memsz;
1140 if (unlikely(delta >= 0)) {
1141 f->m.wptr = delta;
1142 if (delta > 0) {
1143 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1144 DBG("wrapped descriptor\n");
1145 }
1146 }
1147 dno--;
1148 }
1149 /*TBD: to do - delayed rxf wptr like in txd */
1150 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1151 RET();
1152}
1153
1154static inline void
1155NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan,
1156 struct sk_buff *skb)
1157{
1158 ENTER;
1159 DBG("rxdd->flags.bits.vtag=%d vlgrp=%p\n", GET_RXD_VTAG(rxd_val1),
1160 priv->vlgrp);
1161 if (priv->vlgrp && GET_RXD_VTAG(rxd_val1)) {
1162 DBG("%s: vlan rcv vlan '%x' vtag '%x', device name '%s'\n",
1163 priv->ndev->name,
1164 GET_RXD_VLAN_ID(rxd_vlan),
1165 GET_RXD_VTAG(rxd_val1),
1166 vlan_group_get_device(priv->vlgrp,
1167 GET_RXD_VLAN_ID(rxd_vlan))->name);
1168 /* NAPI variant of receive functions */
1169 vlan_hwaccel_receive_skb(skb, priv->vlgrp,
38b22195 1170 GET_RXD_VLAN_TCI(rxd_vlan));
1a348ccc
AG		 1171 } else {
1172 netif_receive_skb(skb);
1173 }
1174}
1175
1176static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd)
1177{
1178 struct rxf_desc *rxfd;
1179 struct rx_map *dm;
1180 struct rxf_fifo *f;
1181 struct rxdb *db;
1182 struct sk_buff *skb;
1183 int delta;
1184
1185 ENTER;
1186 DBG("priv=%p rxdd=%p\n", priv, rxdd);
1187 f = &priv->rxf_fifo0;
1188 db = priv->rxdb;
1189 DBG("db=%p f=%p\n", db, f);
1190 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1191 DBG("dm=%p\n", dm);
1192 skb = dm->skb;
1193 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1194 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1195 rxfd->va_lo = rxdd->va_lo;
1196 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1197 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1198 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1199 print_rxfd(rxfd);
1200
1201 f->m.wptr += sizeof(struct rxf_desc);
1202 delta = f->m.wptr - f->m.memsz;
1203 if (unlikely(delta >= 0)) {
1204 f->m.wptr = delta;
1205 if (delta > 0) {
1206 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1207 DBG("wrapped descriptor\n");
1208 }
1209 }
1210 RET();
1211}
1212
1213/* bdx_rx_receive - recieves full packets from RXD fifo and pass them to OS
1214 * NOTE: a special treatment is given to non-continous descriptors
1215 * that start near the end, wraps around and continue at the beginning. a second
1216 * part is copied right after the first, and then descriptor is interpreted as
1217 * normal. fifo has an extra space to allow such operations
1218 * @priv - nic's private structure
1219 * @f - RXF fifo that needs skbs
1220 */
1221
1222/* TBD: replace memcpy func call by explicite inline asm */
1223
1224static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget)
1225{
1226 struct sk_buff *skb, *skb2;
1227 struct rxd_desc *rxdd;
1228 struct rx_map *dm;
1229 struct rxf_fifo *rxf_fifo;
1230 int tmp_len, size;
1231 int done = 0;
1232 int max_done = BDX_MAX_RX_DONE;
1233 struct rxdb *db = NULL;
1234 /* Unmarshalled descriptor - copy of descriptor in host order */
1235 u32 rxd_val1;
1236 u16 len;
1237 u16 rxd_vlan;
1238
1239 ENTER;
1240 max_done = budget;
1241
1a348ccc
AG		 1242 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
1243
1244 size = f->m.wptr - f->m.rptr;
1245 if (size < 0)
1246 size = f->m.memsz + size; /* size is negative :-) */
1247
1248 while (size > 0) {
1249
1250 rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr);
1251 rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1);
1252
1253 len = CPU_CHIP_SWAP16(rxdd->len);
1254
1255 rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan);
1256
1257 print_rxdd(rxdd, rxd_val1, len, rxd_vlan);
1258
1259 tmp_len = GET_RXD_BC(rxd_val1) << 3;
1260 BDX_ASSERT(tmp_len <= 0);
1261 size -= tmp_len;
1262 if (size < 0) /* test for partially arrived descriptor */
1263 break;
1264
1265 f->m.rptr += tmp_len;
1266
1267 tmp_len = f->m.rptr - f->m.memsz;
1268 if (unlikely(tmp_len >= 0)) {
1269 f->m.rptr = tmp_len;
1270 if (tmp_len > 0) {
1271 DBG("wrapped desc rptr=%d tmp_len=%d\n",
1272 f->m.rptr, tmp_len);
1273 memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len);
1274 }
1275 }
1276
1277 if (unlikely(GET_RXD_ERR(rxd_val1))) {
1278 DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1));
1279 priv->net_stats.rx_errors++;
1280 bdx_recycle_skb(priv, rxdd);
1281 continue;
1282 }
1283
1284 rxf_fifo = &priv->rxf_fifo0;
1285 db = priv->rxdb;
1286 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1287 skb = dm->skb;
1288
1289 if (len < BDX_COPYBREAK &&
1290 (skb2 = dev_alloc_skb(len + NET_IP_ALIGN))) {
1291 skb_reserve(skb2, NET_IP_ALIGN);
1292 /*skb_put(skb2, len); */
1293 pci_dma_sync_single_for_cpu(priv->pdev,
1294 dm->dma, rxf_fifo->m.pktsz,
1295 PCI_DMA_FROMDEVICE);
1296 memcpy(skb2->data, skb->data, len);
1297 bdx_recycle_skb(priv, rxdd);
1298 skb = skb2;
1299 } else {
1300 pci_unmap_single(priv->pdev,
1301 dm->dma, rxf_fifo->m.pktsz,
1302 PCI_DMA_FROMDEVICE);
1303 bdx_rxdb_free_elem(db, rxdd->va_lo);
1304 }
1305
1306 priv->net_stats.rx_bytes += len;
1307
1308 skb_put(skb, len);
1309 skb->dev = priv->ndev;
1310 skb->ip_summed = CHECKSUM_UNNECESSARY;
1311 skb->protocol = eth_type_trans(skb, priv->ndev);
1312
1313 /* Non-IP packets aren't checksum-offloaded */
1314 if (GET_RXD_PKT_ID(rxd_val1) == 0)
1315 skb->ip_summed = CHECKSUM_NONE;
1316
1317 NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb);
1318
1319 if (++done >= max_done)
1320 break;
1321 }
1322
1323 priv->net_stats.rx_packets += done;
1324
1325 /* FIXME: do smth to minimize pci accesses */
1326 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1327
1328 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
1329
1330 RET(done);
1331}
1332
1333/*************************************************************************
1334 * Debug / Temprorary Code *
1335 *************************************************************************/
1336static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
1337 u16 rxd_vlan)
1338{
865a21a5 1339 DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d va_lo %d va_hi %d\n",
1a348ccc
AG		 1340 GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1),
1341 GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1),
1342 GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1),
1343 GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan),
1344 GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo,
1345 rxdd->va_hi);
1346}
1347
1348static void print_rxfd(struct rxf_desc *rxfd)
1349{
1350 DBG("=== RxF desc CHIP ORDER/ENDIANESS =============\n"
1351 "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
1352 rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len);
1353}
1354
1355/*
1356 * TX HW/SW interaction overview
1357 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1358 * There are 2 types of TX communication channels betwean driver and NIC.
1359 * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets
1360 * 2) TX Data Fifo - TXD - holds descriptors of full buffers.
1361 *
1362 * Currently NIC supports TSO, checksuming and gather DMA
1363 * UFO and IP fragmentation is on the way
1364 *
1365 * RX SW Data Structures
1366 * ~~~~~~~~~~~~~~~~~~~~~
1367 * txdb - used to keep track of all skbs owned by SW and their dma addresses.
1368 * For TX case, ownership lasts from geting packet via hard_xmit and until HW
1369 * acknowledges sent by TXF descriptors.
1370 * Implemented as cyclic buffer.
1371 * fifo - keeps info about fifo's size and location, relevant HW registers,
1372 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
1373 * Implemented as simple struct.
1374 *
1375 * TX SW Execution Flow
1376 * ~~~~~~~~~~~~~~~~~~~~
1377 * OS calls driver's hard_xmit method with packet to sent.
1378 * Driver creates DMA mappings, builds TXD descriptors and kicks HW
1379 * by updating TXD WPTR.
1380 * When packet is sent, HW write us TXF descriptor and SW frees original skb.
1381 * To prevent TXD fifo overflow without reading HW registers every time,
1382 * SW deploys "tx level" technique.
1383 * Upon strart up, tx level is initialized to TXD fifo length.
1384 * For every sent packet, SW gets its TXD descriptor sizei
1385 * (from precalculated array) and substructs it from tx level.
1386 * The size is also stored in txdb. When TXF ack arrives, SW fetch size of
1387 * original TXD descriptor from txdb and adds it to tx level.
1388 * When Tx level drops under some predefined treshhold, the driver
1389 * stops the TX queue. When TX level rises above that level,
1390 * the tx queue is enabled again.
1391 *
1392 * This technique avoids eccessive reading of RPTR and WPTR registers.
1393 * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput.
1394 */
1395
1396/*************************************************************************
1397 * Tx DB *
1398 *************************************************************************/
1399static inline int bdx_tx_db_size(struct txdb *db)
1400{
1401 int taken = db->wptr - db->rptr;
1402 if (taken < 0)
1403 taken = db->size + 1 + taken; /* (size + 1) equals memsz */
1404
1405 return db->size - taken;
1406}
1407
1408/* __bdx_tx_ptr_next - helper function, increment read/write pointer + wrap
1409 * @d - tx data base
1410 * @ptr - read or write pointer
1411 */
1412static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr)
1413{
1414 BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */
1415
1416 BDX_ASSERT(*pptr != db->rptr && /* expect either read */
1417 *pptr != db->wptr); /* or write pointer */
1418
1419 BDX_ASSERT(*pptr < db->start || /* pointer has to be */
1420 *pptr >= db->end); /* in range */
1421
1422 ++*pptr;
1423 if (unlikely(*pptr == db->end))
1424 *pptr = db->start;
1425}
1426
1427/* bdx_tx_db_inc_rptr - increment read pointer
1428 * @d - tx data base
1429 */
1430static inline void bdx_tx_db_inc_rptr(struct txdb *db)
1431{
1432 BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */
1433 __bdx_tx_db_ptr_next(db, &db->rptr);
1434}
1435
1436/* bdx_tx_db_inc_rptr - increment write pointer
1437 * @d - tx data base
1438 */
1439static inline void bdx_tx_db_inc_wptr(struct txdb *db)
1440{
1441 __bdx_tx_db_ptr_next(db, &db->wptr);
1442 BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as
1443 a result of write */
1444}
1445
1446/* bdx_tx_db_init - creates and initializes tx db
1447 * @d - tx data base
1448 * @sz_type - size of tx fifo
1449 * Returns 0 on success, error code otherwise
1450 */
1451static int bdx_tx_db_init(struct txdb *d, int sz_type)
1452{
1453 int memsz = FIFO_SIZE * (1 << (sz_type + 1));
1454
1455 d->start = vmalloc(memsz);
1456 if (!d->start)
1457 return -ENOMEM;
1458
1459 /*
1460 * In order to differentiate between db is empty and db is full
1461 * states at least one element should always be empty in order to
1462 * avoid rptr == wptr which means db is empty
1463 */
1464 d->size = memsz / sizeof(struct tx_map) - 1;
1465 d->end = d->start + d->size + 1; /* just after last element */
1466
1467 /* all dbs are created equally empty */
1468 d->rptr = d->start;
1469 d->wptr = d->start;
1470
1471 return 0;
1472}
1473
1474/* bdx_tx_db_close - closes tx db and frees all memory
1475 * @d - tx data base
1476 */
1477static void bdx_tx_db_close(struct txdb *d)
1478{
1479 BDX_ASSERT(d == NULL);
1480
c0feed87
F		 1481 vfree(d->start);
1482 d->start = NULL;
1a348ccc
AG		 1483}
1484
1485/*************************************************************************
1486 * Tx Engine *
1487 *************************************************************************/
1488
1489/* sizes of tx desc (including padding if needed) as function
1490 * of skb's frag number */
1491static struct {
1492 u16 bytes;
1493 u16 qwords; /* qword = 64 bit */
1494} txd_sizes[MAX_SKB_FRAGS + 1];
1495
1496/* txdb_map_skb - creates and stores dma mappings for skb's data blocks
1497 * @priv - NIC private structure
1498 * @skb - socket buffer to map
1499 *
1500 * It makes dma mappings for skb's data blocks and writes them to PBL of
1501 * new tx descriptor. It also stores them in the tx db, so they could be
1502 * unmaped after data was sent. It is reponsibility of a caller to make
1503 * sure that there is enough space in the tx db. Last element holds pointer
1504 * to skb itself and marked with zero length
1505 */
1506static inline void
1507bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb,
1508 struct txd_desc *txdd)
1509{
1510 struct txdb *db = &priv->txdb;
1511 struct pbl *pbl = &txdd->pbl[0];
1512 int nr_frags = skb_shinfo(skb)->nr_frags;
1513 int i;
1514
1515 db->wptr->len = skb->len - skb->data_len;
1516 db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data,
1517 db->wptr->len, PCI_DMA_TODEVICE);
1518 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1519 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1520 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1521 DBG("=== pbl len: 0x%x ================\n", pbl->len);
1522 DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo);
1523 DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi);
1524 bdx_tx_db_inc_wptr(db);
1525
1526 for (i = 0; i < nr_frags; i++) {
1527 struct skb_frag_struct *frag;
1528
1529 frag = &skb_shinfo(skb)->frags[i];
1530 db->wptr->len = frag->size;
1531 db->wptr->addr.dma =
1532 pci_map_page(priv->pdev, frag->page, frag->page_offset,
1533 frag->size, PCI_DMA_TODEVICE);
1534
1535 pbl++;
1536 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1537 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1538 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1539 bdx_tx_db_inc_wptr(db);
1540 }
1541
1542 /* add skb clean up info. */
1543 db->wptr->len = -txd_sizes[nr_frags].bytes;
1544 db->wptr->addr.skb = skb;
1545 bdx_tx_db_inc_wptr(db);
1546}
1547
1548/* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags
1549 * number of frags is used as index to fetch correct descriptors size,
1550 * instead of calculating it each time */
1551static void __init init_txd_sizes(void)
1552{
1553 int i, lwords;
1554
1555 /* 7 - is number of lwords in txd with one phys buffer
1556 * 3 - is number of lwords used for every additional phys buffer */
1557 for (i = 0; i < MAX_SKB_FRAGS + 1; i++) {
1558 lwords = 7 + (i * 3);
1559 if (lwords & 1)
1560 lwords++; /* pad it with 1 lword */
1561 txd_sizes[i].qwords = lwords >> 1;
1562 txd_sizes[i].bytes = lwords << 2;
1563 }
1564}
1565
1566/* bdx_tx_init - initialize all Tx related stuff.
1567 * Namely, TXD and TXF fifos, database etc */
1568static int bdx_tx_init(struct bdx_priv *priv)
1569{
1570 if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size,
1571 regTXD_CFG0_0,
1572 regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0))
1573 goto err_mem;
1574 if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size,
1575 regTXF_CFG0_0,
1576 regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0))
1577 goto err_mem;
1578
1579 /* The TX db has to keep mappings for all packets sent (on TxD)
1580 * and not yet reclaimed (on TxF) */
1581 if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size)))
1582 goto err_mem;
1583
1584 priv->tx_level = BDX_MAX_TX_LEVEL;
1585#ifdef BDX_DELAY_WPTR
1586 priv->tx_update_mark = priv->tx_level - 1024;
1587#endif
1588 return 0;
1589
1590err_mem:
865a21a5 1591 netdev_err(priv->ndev, "Tx init failed\n");
1a348ccc
AG		 1592 return -ENOMEM;
1593}
1594
1595/*
1596 * bdx_tx_space - calculates avalable space in TX fifo
1597 * @priv - NIC private structure
1598 * Returns avaliable space in TX fifo in bytes
1599 */
1600static inline int bdx_tx_space(struct bdx_priv *priv)
1601{
1602 struct txd_fifo *f = &priv->txd_fifo0;
1603 int fsize;
1604
1605 f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR;
1606 fsize = f->m.rptr - f->m.wptr;
1607 if (fsize <= 0)
1608 fsize = f->m.memsz + fsize;
1609 return (fsize);
1610}
1611
1612/* bdx_tx_transmit - send packet to NIC
1613 * @skb - packet to send
1614 * ndev - network device assigned to NIC
1615 * Return codes:
1616 * o NETDEV_TX_OK everything ok.
1617 * o NETDEV_TX_BUSY Cannot transmit packet, try later
1618 * Usually a bug, means queue start/stop flow control is broken in
1619 * the driver. Note: the driver must NOT put the skb in its DMA ring.
1620 * o NETDEV_TX_LOCKED Locking failed, please retry quickly.
1621 */
61357325
SH		 1622static netdev_tx_t bdx_tx_transmit(struct sk_buff *skb,
1623 struct net_device *ndev)
1a348ccc 1624{
8f15ea42 1625 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 1626 struct txd_fifo *f = &priv->txd_fifo0;
1627 int txd_checksum = 7; /* full checksum */
1628 int txd_lgsnd = 0;
1629 int txd_vlan_id = 0;
1630 int txd_vtag = 0;
1631 int txd_mss = 0;
1632
1633 int nr_frags = skb_shinfo(skb)->nr_frags;
1634 struct txd_desc *txdd;
1635 int len;
1636 unsigned long flags;
1637
1638 ENTER;
1639 local_irq_save(flags);
1640 if (!spin_trylock(&priv->tx_lock)) {
1641 local_irq_restore(flags);
1642 DBG("%s[%s]: TX locked, returning NETDEV_TX_LOCKED\n",
1643 BDX_DRV_NAME, ndev->name);
1644 return NETDEV_TX_LOCKED;
1645 }
1646
1647 /* build tx descriptor */
1648 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */
1649 txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
1650 if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL))
1651 txd_checksum = 0;
1652
1653 if (skb_shinfo(skb)->gso_size) {
1654 txd_mss = skb_shinfo(skb)->gso_size;
1655 txd_lgsnd = 1;
1656 DBG("skb %p skb len %d gso size = %d\n", skb, skb->len,
1657 txd_mss);
1658 }
1659
1660 if (vlan_tx_tag_present(skb)) {
1661 /*Cut VLAN ID to 12 bits */
1662 txd_vlan_id = vlan_tx_tag_get(skb) & BITS_MASK(12);
1663 txd_vtag = 1;
1664 }
1665
1666 txdd->length = CPU_CHIP_SWAP16(skb->len);
1667 txdd->mss = CPU_CHIP_SWAP16(txd_mss);
1668 txdd->txd_val1 =
1669 CPU_CHIP_SWAP32(TXD_W1_VAL
1670 (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag,
1671 txd_lgsnd, txd_vlan_id));
1672 DBG("=== TxD desc =====================\n");
1673 DBG("=== w1: 0x%x ================\n", txdd->txd_val1);
1674 DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length);
1675
1676 bdx_tx_map_skb(priv, skb, txdd);
1677
1678 /* increment TXD write pointer. In case of
1679 fifo wrapping copy reminder of the descriptor
1680 to the beginning */
1681 f->m.wptr += txd_sizes[nr_frags].bytes;
1682 len = f->m.wptr - f->m.memsz;
1683 if (unlikely(len >= 0)) {
1684 f->m.wptr = len;
1685 if (len > 0) {
1686 BDX_ASSERT(len > f->m.memsz);
1687 memcpy(f->m.va, f->m.va + f->m.memsz, len);
1688 }
1689 }
1690 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */
1691
1692 priv->tx_level -= txd_sizes[nr_frags].bytes;
1693 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1694#ifdef BDX_DELAY_WPTR
1695 if (priv->tx_level > priv->tx_update_mark) {
1696 /* Force memory writes to complete before letting h/w
1697 know there are new descriptors to fetch.
1698 (might be needed on platforms like IA64)
1699 wmb(); */
1700 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1701 } else {
1702 if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) {
1703 priv->tx_noupd = 0;
1704 WRITE_REG(priv, f->m.reg_WPTR,
1705 f->m.wptr & TXF_WPTR_WR_PTR);
1706 }
1707 }
1708#else
1709 /* Force memory writes to complete before letting h/w
1710 know there are new descriptors to fetch.
1711 (might be needed on platforms like IA64)
1712 wmb(); */
1713 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1714
1715#endif
28679751
ED		 1716#ifdef BDX_LLTX
1717 ndev->trans_start = jiffies; /* NETIF_F_LLTX driver :( */
1718#endif
1a348ccc
AG		 1719 priv->net_stats.tx_packets++;
1720 priv->net_stats.tx_bytes += skb->len;
1721
1722 if (priv->tx_level < BDX_MIN_TX_LEVEL) {
1723 DBG("%s: %s: TX Q STOP level %d\n",
1724 BDX_DRV_NAME, ndev->name, priv->tx_level);
1725 netif_stop_queue(ndev);
1726 }
1727
1728 spin_unlock_irqrestore(&priv->tx_lock, flags);
1729 return NETDEV_TX_OK;
1730}
1731
1732/* bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ.
1733 * @priv - bdx adapter
1734 * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS
1735 * that those packets were sent
1736 */
1737static void bdx_tx_cleanup(struct bdx_priv *priv)
1738{
1739 struct txf_fifo *f = &priv->txf_fifo0;
1740 struct txdb *db = &priv->txdb;
1741 int tx_level = 0;
1742
1743 ENTER;
1744 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
1745 BDX_ASSERT(f->m.rptr >= f->m.memsz); /* started with valid rptr */
1746
1747 while (f->m.wptr != f->m.rptr) {
1748 f->m.rptr += BDX_TXF_DESC_SZ;
1749 f->m.rptr &= f->m.size_mask;
1750
1751 /* unmap all the fragments */
1752 /* first has to come tx_maps containing dma */
1753 BDX_ASSERT(db->rptr->len == 0);
1754 do {
1755 BDX_ASSERT(db->rptr->addr.dma == 0);
1756 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1757 db->rptr->len, PCI_DMA_TODEVICE);
1758 bdx_tx_db_inc_rptr(db);
1759 } while (db->rptr->len > 0);
1760 tx_level -= db->rptr->len; /* '-' koz len is negative */
1761
1762 /* now should come skb pointer - free it */
1a348ccc
AG		 1763 dev_kfree_skb_irq(db->rptr->addr.skb);
1764 bdx_tx_db_inc_rptr(db);
1765 }
1766
1767 /* let h/w know which TXF descriptors were cleaned */
1768 BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
1769 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1770
1771 /* We reclaimed resources, so in case the Q is stopped by xmit callback,
1772 * we resume the transmition and use tx_lock to synchronize with xmit.*/
1773 spin_lock(&priv->tx_lock);
1774 priv->tx_level += tx_level;
1775 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1776#ifdef BDX_DELAY_WPTR
1777 if (priv->tx_noupd) {
1778 priv->tx_noupd = 0;
1779 WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,
1780 priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
1781 }
1782#endif
1783
8e95a202
JP		 1784 if (unlikely(netif_queue_stopped(priv->ndev) &&
1785 netif_carrier_ok(priv->ndev) &&
1786 (priv->tx_level >= BDX_MIN_TX_LEVEL))) {
1a348ccc
AG		 1787 DBG("%s: %s: TX Q WAKE level %d\n",
1788 BDX_DRV_NAME, priv->ndev->name, priv->tx_level);
1789 netif_wake_queue(priv->ndev);
1790 }
1791 spin_unlock(&priv->tx_lock);
1792}
1793
1794/* bdx_tx_free_skbs - frees all skbs from TXD fifo.
1795 * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod
1796 */
1797static void bdx_tx_free_skbs(struct bdx_priv *priv)
1798{
1799 struct txdb *db = &priv->txdb;
1800
1801 ENTER;
1802 while (db->rptr != db->wptr) {
1803 if (likely(db->rptr->len))
1804 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1805 db->rptr->len, PCI_DMA_TODEVICE);
1806 else
1807 dev_kfree_skb(db->rptr->addr.skb);
1808 bdx_tx_db_inc_rptr(db);
1809 }
1810 RET();
1811}
1812
1813/* bdx_tx_free - frees all Tx resources */
1814static void bdx_tx_free(struct bdx_priv *priv)
1815{
1816 ENTER;
1817 bdx_tx_free_skbs(priv);
1818 bdx_fifo_free(priv, &priv->txd_fifo0.m);
1819 bdx_fifo_free(priv, &priv->txf_fifo0.m);
1820 bdx_tx_db_close(&priv->txdb);
1821}
1822
1823/* bdx_tx_push_desc - push descriptor to TxD fifo
1824 * @priv - NIC private structure
1825 * @data - desc's data
1826 * @size - desc's size
1827 *
1828 * Pushes desc to TxD fifo and overlaps it if needed.
1829 * NOTE: this func does not check for available space. this is responsibility
025dfdaf 1830 * of the caller. Neither does it check that data size is smaller than
1a348ccc
AG		 1831 * fifo size.
1832 */
1833static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size)
1834{
1835 struct txd_fifo *f = &priv->txd_fifo0;
1836 int i = f->m.memsz - f->m.wptr;
1837
1838 if (size == 0)
1839 return;
1840
1841 if (i > size) {
1842 memcpy(f->m.va + f->m.wptr, data, size);
1843 f->m.wptr += size;
1844 } else {
1845 memcpy(f->m.va + f->m.wptr, data, i);
1846 f->m.wptr = size - i;
1847 memcpy(f->m.va, data + i, f->m.wptr);
1848 }
1849 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1850}
1851
1852/* bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way
1853 * @priv - NIC private structure
1854 * @data - desc's data
1855 * @size - desc's size
1856 *
1857 * NOTE: this func does check for available space and, if neccessary, waits for
1858 * NIC to read existing data before writing new one.
1859 */
1860static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size)
1861{
1862 int timer = 0;
1863 ENTER;
1864
1865 while (size > 0) {
1866 /* we substruct 8 because when fifo is full rptr == wptr
1867 which also means that fifo is empty, we can understand
1868 the difference, but could hw do the same ??? :) */
1869 int avail = bdx_tx_space(priv) - 8;
1870 if (avail <= 0) {
1871 if (timer++ > 300) { /* prevent endless loop */
1872 DBG("timeout while writing desc to TxD fifo\n");
1873 break;
1874 }
1875 udelay(50); /* give hw a chance to clean fifo */
1876 continue;
1877 }
df7641af 1878 avail = min(avail, size);
1a348ccc
AG		 1879 DBG("about to push %d bytes starting %p size %d\n", avail,
1880 data, size);
1881 bdx_tx_push_desc(priv, data, avail);
1882 size -= avail;
1883 data += avail;
1884 }
1885 RET();
1886}
1887
2f30b1f6
SH		 1888static const struct net_device_ops bdx_netdev_ops = {
1889 .ndo_open = bdx_open,
1890 .ndo_stop = bdx_close,
1891 .ndo_start_xmit = bdx_tx_transmit,
1892 .ndo_validate_addr = eth_validate_addr,
1893 .ndo_do_ioctl = bdx_ioctl,
1894 .ndo_set_multicast_list = bdx_setmulti,
1895 .ndo_get_stats = bdx_get_stats,
1896 .ndo_change_mtu = bdx_change_mtu,
1897 .ndo_set_mac_address = bdx_set_mac,
1898 .ndo_vlan_rx_register = bdx_vlan_rx_register,
1899 .ndo_vlan_rx_add_vid = bdx_vlan_rx_add_vid,
1900 .ndo_vlan_rx_kill_vid = bdx_vlan_rx_kill_vid,
1901};
1902
1a348ccc
AG		 1903/**
1904 * bdx_probe - Device Initialization Routine
1905 * @pdev: PCI device information struct
1906 * @ent: entry in bdx_pci_tbl
1907 *
1908 * Returns 0 on success, negative on failure
1909 *
1910 * bdx_probe initializes an adapter identified by a pci_dev structure.
1911 * The OS initialization, configuring of the adapter private structure,
1912 * and a hardware reset occur.
1913 *
1914 * functions and their order used as explained in
1915 * /usr/src/linux/Documentation/DMA-{API,mapping}.txt
1916 *
1917 */
1918
1919/* TBD: netif_msg should be checked and implemented. I disable it for now */
1920static int __devinit
1921bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1922{
1923 struct net_device *ndev;
1924 struct bdx_priv *priv;
1925 int err, pci_using_dac, port;
1926 unsigned long pciaddr;
1927 u32 regionSize;
1928 struct pci_nic *nic;
1929
1930 ENTER;
1931
1932 nic = vmalloc(sizeof(*nic));
1933 if (!nic)
1934 RET(-ENOMEM);
1935
1936 /************** pci *****************/
1937 if ((err = pci_enable_device(pdev))) /* it trigers interrupt, dunno why. */
bc2618f7 1938 goto err_pci; /* it's not a problem though */
1a348ccc 1939
6a35528a
YH		 1940 if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) &&
1941 !(err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))) {
1a348ccc
AG		 1942 pci_using_dac = 1;
1943 } else {
284901a9
YH		 1944 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1945 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
865a21a5 1946 pr_err("No usable DMA configuration, aborting\n");
1a348ccc
AG		 1947 goto err_dma;
1948 }
1949 pci_using_dac = 0;
1950 }
1951
1952 if ((err = pci_request_regions(pdev, BDX_DRV_NAME)))
1953 goto err_dma;
1954
1955 pci_set_master(pdev);
1956
1957 pciaddr = pci_resource_start(pdev, 0);
1958 if (!pciaddr) {
1959 err = -EIO;
865a21a5 1960 pr_err("no MMIO resource\n");
1a348ccc
AG		 1961 goto err_out_res;
1962 }
1963 if ((regionSize = pci_resource_len(pdev, 0)) < BDX_REGS_SIZE) {
1964 err = -EIO;
865a21a5 1965 pr_err("MMIO resource (%x) too small\n", regionSize);
1a348ccc
AG		 1966 goto err_out_res;
1967 }
1968
1969 nic->regs = ioremap(pciaddr, regionSize);
1970 if (!nic->regs) {
1971 err = -EIO;
865a21a5 1972 pr_err("ioremap failed\n");
1a348ccc
AG		 1973 goto err_out_res;
1974 }
1975
1976 if (pdev->irq < 2) {
1977 err = -EIO;
865a21a5 1978 pr_err("invalid irq (%d)\n", pdev->irq);
1a348ccc
AG		 1979 goto err_out_iomap;
1980 }
1981 pci_set_drvdata(pdev, nic);
1982
1983 if (pdev->device == 0x3014)
1984 nic->port_num = 2;
1985 else
1986 nic->port_num = 1;
1987
1988 print_hw_id(pdev);
1989
1990 bdx_hw_reset_direct(nic->regs);
1991
1992 nic->irq_type = IRQ_INTX;
1993#ifdef BDX_MSI
1994 if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) {
1995 if ((err = pci_enable_msi(pdev)))
865a21a5 1996 pr_err("Can't eneble msi. error is %d\n", err);
1a348ccc
AG		 1997 else
1998 nic->irq_type = IRQ_MSI;
1999 } else
2000 DBG("HW does not support MSI\n");
2001#endif
2002
2003 /************** netdev **************/
2004 for (port = 0; port < nic->port_num; port++) {
2005 if (!(ndev = alloc_etherdev(sizeof(struct bdx_priv)))) {
2006 err = -ENOMEM;
865a21a5 2007 pr_err("alloc_etherdev failed\n");
1a348ccc
AG		 2008 goto err_out_iomap;
2009 }
2010
2f30b1f6 2011 ndev->netdev_ops = &bdx_netdev_ops;
1a348ccc 2012 ndev->tx_queue_len = BDX_NDEV_TXQ_LEN;
1a348ccc
AG		 2013
2014 bdx_ethtool_ops(ndev); /* ethtool interface */
2015
2016 /* these fields are used for info purposes only
2017 * so we can have them same for all ports of the board */
2018 ndev->if_port = port;
2019 ndev->base_addr = pciaddr;
2020 ndev->mem_start = pciaddr;
2021 ndev->mem_end = pciaddr + regionSize;
2022 ndev->irq = pdev->irq;
2023 ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO
2024 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
2025 NETIF_F_HW_VLAN_FILTER
2026 /*| NETIF_F_FRAGLIST */
2027 ;
2028
2029 if (pci_using_dac)
2030 ndev->features |= NETIF_F_HIGHDMA;
2031
2032 /************** priv ****************/
8f15ea42 2033 priv = nic->priv[port] = netdev_priv(ndev);
1a348ccc
AG		 2034
2035 memset(priv, 0, sizeof(struct bdx_priv));
2036 priv->pBdxRegs = nic->regs + port * 0x8000;
2037 priv->port = port;
2038 priv->pdev = pdev;
2039 priv->ndev = ndev;
2040 priv->nic = nic;
2041 priv->msg_enable = BDX_DEF_MSG_ENABLE;
2042
2043 netif_napi_add(ndev, &priv->napi, bdx_poll, 64);
2044
2045 if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) {
2046 DBG("HW statistics not supported\n");
2047 priv->stats_flag = 0;
2048 } else {
2049 priv->stats_flag = 1;
2050 }
2051
2052 /* Initialize fifo sizes. */
2053 priv->txd_size = 2;
2054 priv->txf_size = 2;
2055 priv->rxd_size = 2;
2056 priv->rxf_size = 3;
2057
2058 /* Initialize the initial coalescing registers. */
2059 priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12);
2060 priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12);
2061
2062 /* ndev->xmit_lock spinlock is not used.
2063 * Private priv->tx_lock is used for synchronization
2064 * between transmit and TX irq cleanup. In addition
2065 * set multicast list callback has to use priv->tx_lock.
2066 */
2067#ifdef BDX_LLTX
2068 ndev->features |= NETIF_F_LLTX;
2069#endif
2070 spin_lock_init(&priv->tx_lock);
2071
2072 /*bdx_hw_reset(priv); */
2073 if (bdx_read_mac(priv)) {
865a21a5 2074 pr_err("load MAC address failed\n");
1a348ccc
AG		 2075 goto err_out_iomap;
2076 }
2077 SET_NETDEV_DEV(ndev, &pdev->dev);
2078 if ((err = register_netdev(ndev))) {
865a21a5 2079 pr_err("register_netdev failed\n");
1a348ccc
AG		 2080 goto err_out_free;
2081 }
2082 netif_carrier_off(ndev);
2083 netif_stop_queue(ndev);
2084
2085 print_eth_id(ndev);
2086 }
2087 RET(0);
2088
2089err_out_free:
2090 free_netdev(ndev);
2091err_out_iomap:
2092 iounmap(nic->regs);
2093err_out_res:
2094 pci_release_regions(pdev);
2095err_dma:
2096 pci_disable_device(pdev);
bc2618f7 2097err_pci:
1a348ccc
AG		 2098 vfree(nic);
2099
2100 RET(err);
2101}
2102
2103/****************** Ethtool interface *********************/
1a348ccc
AG		 2104/* get strings for statistics counters */
2105static const char
2106 bdx_stat_names[][ETH_GSTRING_LEN] = {
2107 "InUCast", /* 0x7200 */
2108 "InMCast", /* 0x7210 */
2109 "InBCast", /* 0x7220 */
2110 "InPkts", /* 0x7230 */
2111 "InErrors", /* 0x7240 */
2112 "InDropped", /* 0x7250 */
2113 "FrameTooLong", /* 0x7260 */
2114 "FrameSequenceErrors", /* 0x7270 */
2115 "InVLAN", /* 0x7280 */
2116 "InDroppedDFE", /* 0x7290 */
2117 "InDroppedIntFull", /* 0x72A0 */
2118 "InFrameAlignErrors", /* 0x72B0 */
2119
2120 /* 0x72C0-0x72E0 RSRV */
2121
2122 "OutUCast", /* 0x72F0 */
2123 "OutMCast", /* 0x7300 */
2124 "OutBCast", /* 0x7310 */
2125 "OutPkts", /* 0x7320 */
2126
2127 /* 0x7330-0x7360 RSRV */
2128
2129 "OutVLAN", /* 0x7370 */
2130 "InUCastOctects", /* 0x7380 */
2131 "OutUCastOctects", /* 0x7390 */
2132
2133 /* 0x73A0-0x73B0 RSRV */
2134
2135 "InBCastOctects", /* 0x73C0 */
2136 "OutBCastOctects", /* 0x73D0 */
2137 "InOctects", /* 0x73E0 */
2138 "OutOctects", /* 0x73F0 */
2139};
2140
2141/*
2142 * bdx_get_settings - get device-specific settings
2143 * @netdev
2144 * @ecmd
2145 */
2146static int bdx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
2147{
2148 u32 rdintcm;
2149 u32 tdintcm;
8f15ea42 2150 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2151
2152 rdintcm = priv->rdintcm;
2153 tdintcm = priv->tdintcm;
2154
2155 ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
2156 ecmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
2157 ecmd->speed = SPEED_10000;
2158 ecmd->duplex = DUPLEX_FULL;
2159 ecmd->port = PORT_FIBRE;
2160 ecmd->transceiver = XCVR_EXTERNAL; /* what does it mean? */
2161 ecmd->autoneg = AUTONEG_DISABLE;
2162
2163 /* PCK_TH measures in multiples of FIFO bytes
2164 We translate to packets */
2165 ecmd->maxtxpkt =
2166 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2167 ecmd->maxrxpkt =
2168 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2169
2170 return 0;
2171}
2172
2173/*
2174 * bdx_get_drvinfo - report driver information
2175 * @netdev
2176 * @drvinfo
2177 */
2178static void
2179bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
2180{
8f15ea42 2181 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc 2182
072ee3f9
RK		 2183 strlcat(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver));
2184 strlcat(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version));
2185 strlcat(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
2186 strlcat(drvinfo->bus_info, pci_name(priv->pdev),
1a348ccc
AG		 2187 sizeof(drvinfo->bus_info));
2188
4c3616cd 2189 drvinfo->n_stats = ((priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0);
1a348ccc
AG		 2190 drvinfo->testinfo_len = 0;
2191 drvinfo->regdump_len = 0;
2192 drvinfo->eedump_len = 0;
2193}
2194
2195/*
2196 * bdx_get_rx_csum - report whether receive checksums are turned on or off
2197 * @netdev
2198 */
2199static u32 bdx_get_rx_csum(struct net_device *netdev)
2200{
2201 return 1; /* always on */
2202}
2203
2204/*
2205 * bdx_get_tx_csum - report whether transmit checksums are turned on or off
2206 * @netdev
2207 */
2208static u32 bdx_get_tx_csum(struct net_device *netdev)
2209{
2210 return (netdev->features & NETIF_F_IP_CSUM) != 0;
2211}
2212
2213/*
2214 * bdx_get_coalesce - get interrupt coalescing parameters
2215 * @netdev
2216 * @ecoal
2217 */
2218static int
2219bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2220{
2221 u32 rdintcm;
2222 u32 tdintcm;
8f15ea42 2223 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2224
2225 rdintcm = priv->rdintcm;
2226 tdintcm = priv->tdintcm;
2227
2228 /* PCK_TH measures in multiples of FIFO bytes
2229 We translate to packets */
2230 ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT;
2231 ecoal->rx_max_coalesced_frames =
2232 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2233
2234 ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT;
2235 ecoal->tx_max_coalesced_frames =
2236 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2237
2238 /* adaptive parameters ignored */
2239 return 0;
2240}
2241
2242/*
2243 * bdx_set_coalesce - set interrupt coalescing parameters
2244 * @netdev
2245 * @ecoal
2246 */
2247static int
2248bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2249{
2250 u32 rdintcm;
2251 u32 tdintcm;
8f15ea42 2252 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2253 int rx_coal;
2254 int tx_coal;
2255 int rx_max_coal;
2256 int tx_max_coal;
2257
2258 /* Check for valid input */
2259 rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT;
2260 tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT;
2261 rx_max_coal = ecoal->rx_max_coalesced_frames;
2262 tx_max_coal = ecoal->tx_max_coalesced_frames;
2263
2264 /* Translate from packets to multiples of FIFO bytes */
2265 rx_max_coal =
2266 (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1)
2267 / PCK_TH_MULT);
2268 tx_max_coal =
2269 (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1)
2270 / PCK_TH_MULT);
2271
8e95a202
JP		 2272 if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF) ||
2273 (rx_max_coal > 0xF) || (tx_max_coal > 0xF))
1a348ccc
AG		 2274 return -EINVAL;
2275
2276 rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm),
2277 GET_RXF_TH(priv->rdintcm), rx_max_coal);
2278 tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0,
2279 tx_max_coal);
2280
2281 priv->rdintcm = rdintcm;
2282 priv->tdintcm = tdintcm;
2283
2284 WRITE_REG(priv, regRDINTCM0, rdintcm);
2285 WRITE_REG(priv, regTDINTCM0, tdintcm);
2286
2287 return 0;
2288}
2289
2290/* Convert RX fifo size to number of pending packets */
2291static inline int bdx_rx_fifo_size_to_packets(int rx_size)
2292{
2293 return ((FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc));
2294}
2295
2296/* Convert TX fifo size to number of pending packets */
2297static inline int bdx_tx_fifo_size_to_packets(int tx_size)
2298{
2299 return ((FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ);
2300}
2301
2302/*
2303 * bdx_get_ringparam - report ring sizes
2304 * @netdev
2305 * @ring
2306 */
2307static void
2308bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2309{
8f15ea42 2310 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2311
2312 /*max_pending - the maximum-sized FIFO we allow */
2313 ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3);
2314 ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3);
2315 ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size);
2316 ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size);
2317}
2318
2319/*
2320 * bdx_set_ringparam - set ring sizes
2321 * @netdev
2322 * @ring
2323 */
2324static int
2325bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2326{
8f15ea42 2327 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2328 int rx_size = 0;
2329 int tx_size = 0;
2330
2331 for (; rx_size < 4; rx_size++) {
2332 if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending)
2333 break;
2334 }
2335 if (rx_size == 4)
2336 rx_size = 3;
2337
2338 for (; tx_size < 4; tx_size++) {
2339 if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending)
2340 break;
2341 }
2342 if (tx_size == 4)
2343 tx_size = 3;
2344
2345 /*Is there anything to do? */
8e95a202
JP		 2346 if ((rx_size == priv->rxf_size) &&
2347 (tx_size == priv->txd_size))
1a348ccc
AG		 2348 return 0;
2349
2350 priv->rxf_size = rx_size;
2351 if (rx_size > 1)
2352 priv->rxd_size = rx_size - 1;
2353 else
2354 priv->rxd_size = rx_size;
2355
2356 priv->txf_size = priv->txd_size = tx_size;
2357
2358 if (netif_running(netdev)) {
2359 bdx_close(netdev);
2360 bdx_open(netdev);
2361 }
2362 return 0;
2363}
2364
2365/*
2366 * bdx_get_strings - return a set of strings that describe the requested objects
2367 * @netdev
2368 * @data
2369 */
2370static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2371{
2372 switch (stringset) {
1a348ccc
AG		 2373 case ETH_SS_STATS:
2374 memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names));
2375 break;
2376 }
2377}
2378
2379/*
1ddee09f 2380 * bdx_get_sset_count - return number of statistics or tests
1a348ccc
AG		 2381 * @netdev
2382 */
1ddee09f 2383static int bdx_get_sset_count(struct net_device *netdev, int stringset)
1a348ccc 2384{
8f15ea42 2385 struct bdx_priv *priv = netdev_priv(netdev);
1ddee09f
BH		 2386
2387 switch (stringset) {
2388 case ETH_SS_STATS:
2389 BDX_ASSERT(ARRAY_SIZE(bdx_stat_names)
2390 != sizeof(struct bdx_stats) / sizeof(u64));
2391 return ((priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0);
2392 default:
2393 return -EINVAL;
2394 }
1a348ccc
AG		 2395}
2396
2397/*
2398 * bdx_get_ethtool_stats - return device's hardware L2 statistics
2399 * @netdev
2400 * @stats
2401 * @data
2402 */
2403static void bdx_get_ethtool_stats(struct net_device *netdev,
2404 struct ethtool_stats *stats, u64 *data)
2405{
8f15ea42 2406 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2407
2408 if (priv->stats_flag) {
2409
2410 /* Update stats from HW */
2411 bdx_update_stats(priv);
2412
2413 /* Copy data to user buffer */
2414 memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats));
2415 }
2416}
2417
2418/*
2419 * bdx_ethtool_ops - ethtool interface implementation
2420 * @netdev
2421 */
2422static void bdx_ethtool_ops(struct net_device *netdev)
2423{
0fc0b732 2424 static const struct ethtool_ops bdx_ethtool_ops = {
1a348ccc
AG		 2425 .get_settings = bdx_get_settings,
2426 .get_drvinfo = bdx_get_drvinfo,
2427 .get_link = ethtool_op_get_link,
2428 .get_coalesce = bdx_get_coalesce,
2429 .set_coalesce = bdx_set_coalesce,
2430 .get_ringparam = bdx_get_ringparam,
2431 .set_ringparam = bdx_set_ringparam,
2432 .get_rx_csum = bdx_get_rx_csum,
2433 .get_tx_csum = bdx_get_tx_csum,
2434 .get_sg = ethtool_op_get_sg,
2435 .get_tso = ethtool_op_get_tso,
2436 .get_strings = bdx_get_strings,
1ddee09f 2437 .get_sset_count = bdx_get_sset_count,
1a348ccc
AG		 2438 .get_ethtool_stats = bdx_get_ethtool_stats,
2439 };
2440
2441 SET_ETHTOOL_OPS(netdev, &bdx_ethtool_ops);
2442}
2443
2444/**
2445 * bdx_remove - Device Removal Routine
2446 * @pdev: PCI device information struct
2447 *
2448 * bdx_remove is called by the PCI subsystem to alert the driver
2449 * that it should release a PCI device. The could be caused by a
2450 * Hot-Plug event, or because the driver is going to be removed from
2451 * memory.
2452 **/
2453static void __devexit bdx_remove(struct pci_dev *pdev)
2454{
2455 struct pci_nic *nic = pci_get_drvdata(pdev);
2456 struct net_device *ndev;
2457 int port;
2458
2459 for (port = 0; port < nic->port_num; port++) {
2460 ndev = nic->priv[port]->ndev;
2461 unregister_netdev(ndev);
2462 free_netdev(ndev);
2463 }
2464
2465 /*bdx_hw_reset_direct(nic->regs); */
2466#ifdef BDX_MSI
2467 if (nic->irq_type == IRQ_MSI)
2468 pci_disable_msi(pdev);
2469#endif
2470
2471 iounmap(nic->regs);
2472 pci_release_regions(pdev);
2473 pci_disable_device(pdev);
2474 pci_set_drvdata(pdev, NULL);
2475 vfree(nic);
2476
2477 RET();
2478}
2479
2480static struct pci_driver bdx_pci_driver = {
2481 .name = BDX_DRV_NAME,
2482 .id_table = bdx_pci_tbl,
2483 .probe = bdx_probe,
2484 .remove = __devexit_p(bdx_remove),
2485};
2486
2487/*
2488 * print_driver_id - print parameters of the driver build
2489 */
2490static void __init print_driver_id(void)
2491{
865a21a5
JP		 2492 pr_info("%s, %s\n", BDX_DRV_DESC, BDX_DRV_VERSION);
2493 pr_info("Options: hw_csum %s\n", BDX_MSI_STRING);
1a348ccc
AG		 2494}
2495
2496static int __init bdx_module_init(void)
2497{
2498 ENTER;
1a348ccc
AG		 2499 init_txd_sizes();
2500 print_driver_id();
2501 RET(pci_register_driver(&bdx_pci_driver));
2502}
2503
2504module_init(bdx_module_init);
2505
2506static void __exit bdx_module_exit(void)
2507{
2508 ENTER;
2509 pci_unregister_driver(&bdx_pci_driver);
2510 RET();
2511}
2512
2513module_exit(bdx_module_exit);
2514
2515MODULE_LICENSE("GPL");
2516MODULE_AUTHOR(DRIVER_AUTHOR);
2517MODULE_DESCRIPTION(BDX_DRV_DESC);
06e1f9ff 2518MODULE_FIRMWARE("tehuti/firmware.bin");
Clone of davem's net-next-2.6 tree