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1a348ccc
AG		 1/*
2 * Tehuti Networks(R) Network Driver
3 * ethtool interface implementation
4 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12/*
13 * RX HW/SW interaction overview
14 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
15 * There are 2 types of RX communication channels betwean driver and NIC.
16 * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
17 * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
18 * info about buffer's location, size and ID. An ID field is used to identify a
19 * buffer when it's returned with data via RXD Fifo (see below)
20 * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
21 * filled by HW and is readen by SW. Each descriptor holds status and ID.
22 * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
23 * via dma moves it into host memory, builds new RXD descriptor with same ID,
24 * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
25 *
26 * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos.
27 * One holds 1.5K packets and another - 26K packets. Depending on incoming
28 * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
29 * filled with data, HW builds new RXD descriptor for it and push it into single
30 * RXD Fifo.
31 *
32 * RX SW Data Structures
33 * ~~~~~~~~~~~~~~~~~~~~~
34 * skb db - used to keep track of all skbs owned by SW and their dma addresses.
35 * For RX case, ownership lasts from allocating new empty skb for RXF until
36 * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own
37 * skb db. Implemented as array with bitmask.
38 * fifo - keeps info about fifo's size and location, relevant HW registers,
39 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
40 * Implemented as simple struct.
41 *
42 * RX SW Execution Flow
43 * ~~~~~~~~~~~~~~~~~~~~
44 * Upon initialization (ifconfig up) driver creates RX fifos and initializes
45 * relevant registers. At the end of init phase, driver enables interrupts.
46 * NIC sees that there is no RXF buffers and raises
47 * RD_INTR interrupt, isr fills skbs and Rx begins.
48 * Driver has two receive operation modes:
49 * NAPI - interrupt-driven mixed with polling
50 * interrupt-driven only
51 *
52 * Interrupt-driven only flow is following. When buffer is ready, HW raises
53 * interrupt and isr is called. isr collects all available packets
54 * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit.
55
56 * Rx buffer allocation note
57 * ~~~~~~~~~~~~~~~~~~~~~~~~~
58 * Driver cares to feed such amount of RxF descriptors that respective amount of
59 * RxD descriptors can not fill entire RxD fifo. The main reason is lack of
60 * overflow check in Bordeaux for RxD fifo free/used size.
61 * FIXME: this is NOT fully implemented, more work should be done
62 *
63 */
64
865a21a5
JP		 65#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
66
1a348ccc 67#include "tehuti.h"
1a348ccc 68
dfa1a041 69static DEFINE_PCI_DEVICE_TABLE(bdx_pci_tbl) = {
1a348ccc
AG		 70 {0x1FC9, 0x3009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
71 {0x1FC9, 0x3010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
72 {0x1FC9, 0x3014, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
73 {0}
74};
75
76MODULE_DEVICE_TABLE(pci, bdx_pci_tbl);
77
78/* Definitions needed by ISR or NAPI functions */
79static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f);
80static void bdx_tx_cleanup(struct bdx_priv *priv);
81static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget);
82
83/* Definitions needed by FW loading */
84static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size);
85
86/* Definitions needed by hw_start */
87static int bdx_tx_init(struct bdx_priv *priv);
88static int bdx_rx_init(struct bdx_priv *priv);
89
90/* Definitions needed by bdx_close */
91static void bdx_rx_free(struct bdx_priv *priv);
92static void bdx_tx_free(struct bdx_priv *priv);
93
94/* Definitions needed by bdx_probe */
95static void bdx_ethtool_ops(struct net_device *netdev);
96
97/*************************************************************************
98 * Print Info *
99 *************************************************************************/
100
101static void print_hw_id(struct pci_dev *pdev)
102{
103 struct pci_nic *nic = pci_get_drvdata(pdev);
104 u16 pci_link_status = 0;
105 u16 pci_ctrl = 0;
106
107 pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status);
108 pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl);
109
865a21a5
JP		 110 pr_info("%s%s\n", BDX_NIC_NAME,
111 nic->port_num == 1 ? "" : ", 2-Port");
112 pr_info("srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n",
113 readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF,
114 readl(nic->regs + FPGA_SEED),
115 GET_LINK_STATUS_LANES(pci_link_status),
116 GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl));
1a348ccc
AG		 117}
118
119static void print_fw_id(struct pci_nic *nic)
120{
865a21a5 121 pr_info("fw 0x%x\n", readl(nic->regs + FW_VER));
1a348ccc
AG		 122}
123
124static void print_eth_id(struct net_device *ndev)
125{
865a21a5
JP		 126 netdev_info(ndev, "%s, Port %c\n",
127 BDX_NIC_NAME, (ndev->if_port == 0) ? 'A' : 'B');
1a348ccc
AG		 128
129}
130
131/*************************************************************************
132 * Code *
133 *************************************************************************/
134
135#define bdx_enable_interrupts(priv) \
136 do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
137#define bdx_disable_interrupts(priv) \
138 do { WRITE_REG(priv, regIMR, 0); } while (0)
139
140/* bdx_fifo_init
141 * create TX/RX descriptor fifo for host-NIC communication.
142 * 1K extra space is allocated at the end of the fifo to simplify
143 * processing of descriptors that wraps around fifo's end
144 * @priv - NIC private structure
145 * @f - fifo to initialize
146 * @fsz_type - fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
147 * @reg_XXX - offsets of registers relative to base address
148 *
149 * Returns 0 on success, negative value on failure
150 *
151 */
152static int
153bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type,
154 u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR)
155{
156 u16 memsz = FIFO_SIZE * (1 << fsz_type);
157
158 memset(f, 0, sizeof(struct fifo));
159 /* pci_alloc_consistent gives us 4k-aligned memory */
160 f->va = pci_alloc_consistent(priv->pdev,
161 memsz + FIFO_EXTRA_SPACE, &f->da);
162 if (!f->va) {
865a21a5 163 pr_err("pci_alloc_consistent failed\n");
1a348ccc
AG		 164 RET(-ENOMEM);
165 }
166 f->reg_CFG0 = reg_CFG0;
167 f->reg_CFG1 = reg_CFG1;
168 f->reg_RPTR = reg_RPTR;
169 f->reg_WPTR = reg_WPTR;
170 f->rptr = 0;
171 f->wptr = 0;
172 f->memsz = memsz;
173 f->size_mask = memsz - 1;
174 WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
175 WRITE_REG(priv, reg_CFG1, H32_64(f->da));
176
177 RET(0);
178}
179
180/* bdx_fifo_free - free all resources used by fifo
181 * @priv - NIC private structure
182 * @f - fifo to release
183 */
184static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f)
185{
186 ENTER;
187 if (f->va) {
188 pci_free_consistent(priv->pdev,
189 f->memsz + FIFO_EXTRA_SPACE, f->va, f->da);
190 f->va = NULL;
191 }
192 RET();
193}
194
195/*
196 * bdx_link_changed - notifies OS about hw link state.
197 * @bdx_priv - hw adapter structure
198 */
199static void bdx_link_changed(struct bdx_priv *priv)
200{
201 u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT;
202
203 if (!link) {
204 if (netif_carrier_ok(priv->ndev)) {
205 netif_stop_queue(priv->ndev);
206 netif_carrier_off(priv->ndev);
865a21a5 207 netdev_err(priv->ndev, "Link Down\n");
1a348ccc
AG		 208 }
209 } else {
210 if (!netif_carrier_ok(priv->ndev)) {
211 netif_wake_queue(priv->ndev);
212 netif_carrier_on(priv->ndev);
865a21a5 213 netdev_err(priv->ndev, "Link Up\n");
1a348ccc
AG		 214 }
215 }
216}
217
218static void bdx_isr_extra(struct bdx_priv *priv, u32 isr)
219{
220 if (isr & IR_RX_FREE_0) {
221 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
222 DBG("RX_FREE_0\n");
223 }
224
225 if (isr & IR_LNKCHG0)
226 bdx_link_changed(priv);
227
228 if (isr & IR_PCIE_LINK)
865a21a5 229 netdev_err(priv->ndev, "PCI-E Link Fault\n");
1a348ccc
AG		 230
231 if (isr & IR_PCIE_TOUT)
865a21a5 232 netdev_err(priv->ndev, "PCI-E Time Out\n");
1a348ccc
AG		 233
234}
235
236/* bdx_isr - Interrupt Service Routine for Bordeaux NIC
237 * @irq - interrupt number
238 * @ndev - network device
239 * @regs - CPU registers
240 *
241 * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise
242 *
243 * It reads ISR register to know interrupt reasons, and proceed them one by one.
244 * Reasons of interest are:
245 * RX_DESC - new packet has arrived and RXD fifo holds its descriptor
246 * RX_FREE - number of free Rx buffers in RXF fifo gets low
247 * TX_FREE - packet was transmited and RXF fifo holds its descriptor
248 */
249
250static irqreturn_t bdx_isr_napi(int irq, void *dev)
251{
252 struct net_device *ndev = dev;
8f15ea42 253 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 254 u32 isr;
255
256 ENTER;
257 isr = (READ_REG(priv, regISR) & IR_RUN);
258 if (unlikely(!isr)) {
259 bdx_enable_interrupts(priv);
260 return IRQ_NONE; /* Not our interrupt */
261 }
262
263 if (isr & IR_EXTRA)
264 bdx_isr_extra(priv, isr);
265
266 if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) {
288379f0
BH		 267 if (likely(napi_schedule_prep(&priv->napi))) {
268 __napi_schedule(&priv->napi);
1a348ccc
AG		 269 RET(IRQ_HANDLED);
270 } else {
271 /* NOTE: we get here if intr has slipped into window
272 * between these lines in bdx_poll:
273 * bdx_enable_interrupts(priv);
274 * return 0;
275 * currently intrs are disabled (since we read ISR),
276 * and we have failed to register next poll.
277 * so we read the regs to trigger chip
278 * and allow further interupts. */
279 READ_REG(priv, regTXF_WPTR_0);
280 READ_REG(priv, regRXD_WPTR_0);
281 }
282 }
283
284 bdx_enable_interrupts(priv);
285 RET(IRQ_HANDLED);
286}
287
288static int bdx_poll(struct napi_struct *napi, int budget)
289{
290 struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi);
1a348ccc
AG		 291 int work_done;
292
293 ENTER;
294 bdx_tx_cleanup(priv);
295 work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget);
296 if ((work_done < budget) ||
297 (priv->napi_stop++ >= 30)) {
298 DBG("rx poll is done. backing to isr-driven\n");
299
300 /* from time to time we exit to let NAPI layer release
301 * device lock and allow waiting tasks (eg rmmod) to advance) */
302 priv->napi_stop = 0;
303
288379f0 304 napi_complete(napi);
1a348ccc
AG		 305 bdx_enable_interrupts(priv);
306 }
307 return work_done;
308}
309
310/* bdx_fw_load - loads firmware to NIC
311 * @priv - NIC private structure
312 * Firmware is loaded via TXD fifo, so it must be initialized first.
313 * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC
314 * can have few of them). So all drivers use semaphore register to choose one
315 * that will actually load FW to NIC.
316 */
317
318static int bdx_fw_load(struct bdx_priv *priv)
319{
06e1f9ff 320 const struct firmware *fw = NULL;
1a348ccc 321 int master, i;
06e1f9ff 322 int rc;
1a348ccc
AG		 323
324 ENTER;
325 master = READ_REG(priv, regINIT_SEMAPHORE);
326 if (!READ_REG(priv, regINIT_STATUS) && master) {
06e1f9ff
BH		 327 rc = request_firmware(&fw, "tehuti/firmware.bin", &priv->pdev->dev);
328 if (rc)
329 goto out;
330 bdx_tx_push_desc_safe(priv, (char *)fw->data, fw->size);
1a348ccc
AG		 331 mdelay(100);
332 }
333 for (i = 0; i < 200; i++) {
06e1f9ff
BH		 334 if (READ_REG(priv, regINIT_STATUS)) {
335 rc = 0;
336 goto out;
337 }
1a348ccc
AG		 338 mdelay(2);
339 }
06e1f9ff
BH		 340 rc = -EIO;
341out:
1a348ccc
AG		 342 if (master)
343 WRITE_REG(priv, regINIT_SEMAPHORE, 1);
06e1f9ff
BH		 344 if (fw)
345 release_firmware(fw);
1a348ccc 346
06e1f9ff 347 if (rc) {
865a21a5 348 netdev_err(priv->ndev, "firmware loading failed\n");
06e1f9ff
BH		 349 if (rc == -EIO)
350 DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",
351 READ_REG(priv, regVPC),
352 READ_REG(priv, regVIC),
353 READ_REG(priv, regINIT_STATUS), i);
354 RET(rc);
1a348ccc
AG		 355 } else {
356 DBG("%s: firmware loading success\n", priv->ndev->name);
357 RET(0);
358 }
359}
360
361static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv)
362{
363 u32 val;
364
365 ENTER;
366 DBG("mac0=%x mac1=%x mac2=%x\n",
367 READ_REG(priv, regUNC_MAC0_A),
368 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
369
370 val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);
371 WRITE_REG(priv, regUNC_MAC2_A, val);
372 val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]);
373 WRITE_REG(priv, regUNC_MAC1_A, val);
374 val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]);
375 WRITE_REG(priv, regUNC_MAC0_A, val);
376
377 DBG("mac0=%x mac1=%x mac2=%x\n",
378 READ_REG(priv, regUNC_MAC0_A),
379 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
380 RET();
381}
382
383/* bdx_hw_start - inits registers and starts HW's Rx and Tx engines
384 * @priv - NIC private structure
385 */
386static int bdx_hw_start(struct bdx_priv *priv)
387{
388 int rc = -EIO;
389 struct net_device *ndev = priv->ndev;
390
391 ENTER;
392 bdx_link_changed(priv);
393
394 /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */
395 WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);
396 WRITE_REG(priv, regPAUSE_QUANT, 0x96);
397 WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);
398 WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);
399 WRITE_REG(priv, regRX_FULLNESS, 0);
400 WRITE_REG(priv, regTX_FULLNESS, 0);
401 WRITE_REG(priv, regCTRLST,
402 regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA);
403
404 WRITE_REG(priv, regVGLB, 0);
405 WRITE_REG(priv, regMAX_FRAME_A,
406 priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL);
407
408 DBG("RDINTCM=%08x\n", priv->rdintcm); /*NOTE: test script uses this */
409 WRITE_REG(priv, regRDINTCM0, priv->rdintcm);
410 WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */
411
412 DBG("TDINTCM=%08x\n", priv->tdintcm); /*NOTE: test script uses this */
413 WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */
414
415 /* Enable timer interrupt once in 2 secs. */
416 /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */
417 bdx_restore_mac(priv->ndev, priv);
418
419 WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |
420 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB);
421
249658d5 422#define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI) ? 0 : IRQF_SHARED)
cb001a1f
JP		 423
424 rc = request_irq(priv->pdev->irq, bdx_isr_napi, BDX_IRQ_TYPE,
425 ndev->name, ndev);
426 if (rc)
1a348ccc
AG		 427 goto err_irq;
428 bdx_enable_interrupts(priv);
429
430 RET(0);
431
432err_irq:
433 RET(rc);
434}
435
436static void bdx_hw_stop(struct bdx_priv *priv)
437{
438 ENTER;
439 bdx_disable_interrupts(priv);
440 free_irq(priv->pdev->irq, priv->ndev);
441
442 netif_carrier_off(priv->ndev);
443 netif_stop_queue(priv->ndev);
444
445 RET();
446}
447
448static int bdx_hw_reset_direct(void __iomem *regs)
449{
450 u32 val, i;
451 ENTER;
452
453 /* reset sequences: read, write 1, read, write 0 */
454 val = readl(regs + regCLKPLL);
455 writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);
456 udelay(50);
457 val = readl(regs + regCLKPLL);
458 writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL);
459
460 /* check that the PLLs are locked and reset ended */
461 for (i = 0; i < 70; i++, mdelay(10))
462 if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
463 /* do any PCI-E read transaction */
464 readl(regs + regRXD_CFG0_0);
465 return 0;
466 }
865a21a5 467 pr_err("HW reset failed\n");
1a348ccc
AG		 468 return 1; /* failure */
469}
470
471static int bdx_hw_reset(struct bdx_priv *priv)
472{
473 u32 val, i;
474 ENTER;
475
476 if (priv->port == 0) {
477 /* reset sequences: read, write 1, read, write 0 */
478 val = READ_REG(priv, regCLKPLL);
479 WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);
480 udelay(50);
481 val = READ_REG(priv, regCLKPLL);
482 WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);
483 }
484 /* check that the PLLs are locked and reset ended */
485 for (i = 0; i < 70; i++, mdelay(10))
486 if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
487 /* do any PCI-E read transaction */
488 READ_REG(priv, regRXD_CFG0_0);
489 return 0;
490 }
865a21a5 491 pr_err("HW reset failed\n");
1a348ccc
AG		 492 return 1; /* failure */
493}
494
495static int bdx_sw_reset(struct bdx_priv *priv)
496{
497 int i;
498
499 ENTER;
500 /* 1. load MAC (obsolete) */
501 /* 2. disable Rx (and Tx) */
502 WRITE_REG(priv, regGMAC_RXF_A, 0);
503 mdelay(100);
504 /* 3. disable port */
505 WRITE_REG(priv, regDIS_PORT, 1);
506 /* 4. disable queue */
507 WRITE_REG(priv, regDIS_QU, 1);
508 /* 5. wait until hw is disabled */
509 for (i = 0; i < 50; i++) {
510 if (READ_REG(priv, regRST_PORT) & 1)
511 break;
512 mdelay(10);
513 }
514 if (i == 50)
865a21a5 515 netdev_err(priv->ndev, "SW reset timeout. continuing anyway\n");
1a348ccc
AG		 516
517 /* 6. disable intrs */
518 WRITE_REG(priv, regRDINTCM0, 0);
519 WRITE_REG(priv, regTDINTCM0, 0);
520 WRITE_REG(priv, regIMR, 0);
521 READ_REG(priv, regISR);
522
523 /* 7. reset queue */
524 WRITE_REG(priv, regRST_QU, 1);
525 /* 8. reset port */
526 WRITE_REG(priv, regRST_PORT, 1);
527 /* 9. zero all read and write pointers */
528 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
529 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
530 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
531 WRITE_REG(priv, i, 0);
532 /* 10. unseet port disable */
533 WRITE_REG(priv, regDIS_PORT, 0);
534 /* 11. unset queue disable */
535 WRITE_REG(priv, regDIS_QU, 0);
536 /* 12. unset queue reset */
537 WRITE_REG(priv, regRST_QU, 0);
538 /* 13. unset port reset */
539 WRITE_REG(priv, regRST_PORT, 0);
540 /* 14. enable Rx */
541 /* skiped. will be done later */
542 /* 15. save MAC (obsolete) */
543 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
544 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
545
546 RET(0);
547}
548
549/* bdx_reset - performs right type of reset depending on hw type */
550static int bdx_reset(struct bdx_priv *priv)
551{
552 ENTER;
553 RET((priv->pdev->device == 0x3009)
554 ? bdx_hw_reset(priv)
555 : bdx_sw_reset(priv));
556}
557
558/**
559 * bdx_close - Disables a network interface
560 * @netdev: network interface device structure
561 *
562 * Returns 0, this is not allowed to fail
563 *
564 * The close entry point is called when an interface is de-activated
565 * by the OS. The hardware is still under the drivers control, but
566 * needs to be disabled. A global MAC reset is issued to stop the
567 * hardware, and all transmit and receive resources are freed.
568 **/
569static int bdx_close(struct net_device *ndev)
570{
571 struct bdx_priv *priv = NULL;
572
573 ENTER;
8f15ea42 574 priv = netdev_priv(ndev);
1a348ccc
AG		 575
576 napi_disable(&priv->napi);
577
578 bdx_reset(priv);
579 bdx_hw_stop(priv);
580 bdx_rx_free(priv);
581 bdx_tx_free(priv);
582 RET(0);
583}
584
585/**
586 * bdx_open - Called when a network interface is made active
587 * @netdev: network interface device structure
588 *
589 * Returns 0 on success, negative value on failure
590 *
591 * The open entry point is called when a network interface is made
592 * active by the system (IFF_UP). At this point all resources needed
593 * for transmit and receive operations are allocated, the interrupt
594 * handler is registered with the OS, the watchdog timer is started,
595 * and the stack is notified that the interface is ready.
596 **/
597static int bdx_open(struct net_device *ndev)
598{
599 struct bdx_priv *priv;
600 int rc;
601
602 ENTER;
8f15ea42 603 priv = netdev_priv(ndev);
1a348ccc
AG		 604 bdx_reset(priv);
605 if (netif_running(ndev))
606 netif_stop_queue(priv->ndev);
607
cb001a1f
JP		 608 if ((rc = bdx_tx_init(priv)) ||
609 (rc = bdx_rx_init(priv)) ||
610 (rc = bdx_fw_load(priv)))
1a348ccc
AG		 611 goto err;
612
613 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
614
cb001a1f
JP		 615 rc = bdx_hw_start(priv);
616 if (rc)
1a348ccc
AG		 617 goto err;
618
619 napi_enable(&priv->napi);
620
621 print_fw_id(priv->nic);
622
623 RET(0);
624
625err:
626 bdx_close(ndev);
627 RET(rc);
628}
629
6131a260
FR		 630static int bdx_range_check(struct bdx_priv *priv, u32 offset)
631{
632 return (offset > (u32) (BDX_REGS_SIZE / priv->nic->port_num)) ?
633 -EINVAL : 0;
634}
635
1a348ccc
AG		 636static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd)
637{
8f15ea42 638 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 639 u32 data[3];
640 int error;
641
642 ENTER;
643
644 DBG("jiffies=%ld cmd=%d\n", jiffies, cmd);
645 if (cmd != SIOCDEVPRIVATE) {
646 error = copy_from_user(data, ifr->ifr_data, sizeof(data));
647 if (error) {
865a21a5 648 pr_err("cant copy from user\n");
1a348ccc
AG		 649 RET(error);
650 }
651 DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]);
652 }
653
62035542 654 if (!capable(CAP_SYS_RAWIO))
f946dffe
JG		 655 return -EPERM;
656
1a348ccc
AG		 657 switch (data[0]) {
658
659 case BDX_OP_READ:
6131a260
FR		 660 error = bdx_range_check(priv, data[1]);
661 if (error < 0)
662 return error;
1a348ccc
AG		 663 data[2] = READ_REG(priv, data[1]);
664 DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2],
665 data[2]);
666 error = copy_to_user(ifr->ifr_data, data, sizeof(data));
667 if (error)
668 RET(error);
669 break;
670
671 case BDX_OP_WRITE:
6131a260
FR		 672 error = bdx_range_check(priv, data[1]);
673 if (error < 0)
674 return error;
1a348ccc
AG		 675 WRITE_REG(priv, data[1], data[2]);
676 DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]);
677 break;
678
679 default:
680 RET(-EOPNOTSUPP);
681 }
682 return 0;
683}
684
685static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
686{
687 ENTER;
688 if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15))
689 RET(bdx_ioctl_priv(ndev, ifr, cmd));
690 else
691 RET(-EOPNOTSUPP);
692}
693
694/*
695 * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid
696 * by passing VLAN filter table to hardware
697 * @ndev network device
698 * @vid VLAN vid
699 * @op add or kill operation
700 */
701static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable)
702{
8f15ea42 703 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 704 u32 reg, bit, val;
705
706 ENTER;
707 DBG2("vid=%d value=%d\n", (int)vid, enable);
708 if (unlikely(vid >= 4096)) {
865a21a5 709 pr_err("invalid VID: %u (> 4096)\n", vid);
1a348ccc
AG		 710 RET();
711 }
712 reg = regVLAN_0 + (vid / 32) * 4;
713 bit = 1 << vid % 32;
714 val = READ_REG(priv, reg);
715 DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit);
716 if (enable)
717 val |= bit;
718 else
719 val &= ~bit;
720 DBG2("new val %x\n", val);
721 WRITE_REG(priv, reg, val);
722 RET();
723}
724
725/*
726 * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table
727 * @ndev network device
728 * @vid VLAN vid to add
729 */
730static void bdx_vlan_rx_add_vid(struct net_device *ndev, uint16_t vid)
731{
732 __bdx_vlan_rx_vid(ndev, vid, 1);
733}
734
735/*
736 * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table
737 * @ndev network device
738 * @vid VLAN vid to kill
739 */
740static void bdx_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid)
741{
742 __bdx_vlan_rx_vid(ndev, vid, 0);
743}
744
745/*
746 * bdx_vlan_rx_register - kernel hook for adding VLAN group
747 * @ndev network device
748 * @grp VLAN group
749 */
750static void
751bdx_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
752{
8f15ea42 753 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 754
755 ENTER;
756 DBG("device='%s', group='%p'\n", ndev->name, grp);
757 priv->vlgrp = grp;
758 RET();
759}
760
761/**
762 * bdx_change_mtu - Change the Maximum Transfer Unit
763 * @netdev: network interface device structure
764 * @new_mtu: new value for maximum frame size
765 *
766 * Returns 0 on success, negative on failure
767 */
768static int bdx_change_mtu(struct net_device *ndev, int new_mtu)
769{
1a348ccc
AG		 770 ENTER;
771
772 if (new_mtu == ndev->mtu)
773 RET(0);
774
775 /* enforce minimum frame size */
776 if (new_mtu < ETH_ZLEN) {
865a21a5
JP		 777 netdev_err(ndev, "mtu %d is less then minimal %d\n",
778 new_mtu, ETH_ZLEN);
1a348ccc
AG		 779 RET(-EINVAL);
780 }
781
782 ndev->mtu = new_mtu;
783 if (netif_running(ndev)) {
784 bdx_close(ndev);
785 bdx_open(ndev);
786 }
787 RET(0);
788}
789
790static void bdx_setmulti(struct net_device *ndev)
791{
8f15ea42 792 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 793
794 u32 rxf_val =
795 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN;
796 int i;
797
798 ENTER;
799 /* IMF - imperfect (hash) rx multicat filter */
800 /* PMF - perfect rx multicat filter */
801
802 /* FIXME: RXE(OFF) */
803 if (ndev->flags & IFF_PROMISC) {
804 rxf_val |= GMAC_RX_FILTER_PRM;
805 } else if (ndev->flags & IFF_ALLMULTI) {
806 /* set IMF to accept all multicast frmaes */
807 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
808 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);
4cd24eaf 809 } else if (!netdev_mc_empty(ndev)) {
1a348ccc 810 u8 hash;
22bedad3 811 struct netdev_hw_addr *ha;
1a348ccc
AG		 812 u32 reg, val;
813
814 /* set IMF to deny all multicast frames */
815 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
816 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);
817 /* set PMF to deny all multicast frames */
818 for (i = 0; i < MAC_MCST_NUM; i++) {
819 WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);
820 WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);
821 }
822
823 /* use PMF to accept first MAC_MCST_NUM (15) addresses */
824 /* TBD: sort addreses and write them in ascending order
825 * into RX_MAC_MCST regs. we skip this phase now and accept ALL
826 * multicast frames throu IMF */
1a348ccc 827 /* accept the rest of addresses throu IMF */
22bedad3 828 netdev_for_each_mc_addr(ha, ndev) {
1a348ccc
AG		 829 hash = 0;
830 for (i = 0; i < ETH_ALEN; i++)
22bedad3 831 hash ^= ha->addr[i];
1a348ccc
AG		 832 reg = regRX_MCST_HASH0 + ((hash >> 5) << 2);
833 val = READ_REG(priv, reg);
834 val |= (1 << (hash % 32));
835 WRITE_REG(priv, reg, val);
836 }
837
838 } else {
4cd24eaf 839 DBG("only own mac %d\n", netdev_mc_count(ndev));
1a348ccc
AG		 840 rxf_val |= GMAC_RX_FILTER_AB;
841 }
842 WRITE_REG(priv, regGMAC_RXF_A, rxf_val);
843 /* enable RX */
844 /* FIXME: RXE(ON) */
845 RET();
846}
847
848static int bdx_set_mac(struct net_device *ndev, void *p)
849{
8f15ea42 850 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 851 struct sockaddr *addr = p;
852
853 ENTER;
854 /*
855 if (netif_running(dev))
856 return -EBUSY
857 */
858 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
859 bdx_restore_mac(ndev, priv);
860 RET(0);
861}
862
863static int bdx_read_mac(struct bdx_priv *priv)
864{
865 u16 macAddress[3], i;
866 ENTER;
867
868 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
869 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
870 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
871 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
872 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
873 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
874 for (i = 0; i < 3; i++) {
875 priv->ndev->dev_addr[i * 2 + 1] = macAddress[i];
876 priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8;
877 }
878 RET(0);
879}
880
881static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg)
882{
883 u64 val;
884
885 val = READ_REG(priv, reg);
886 val |= ((u64) READ_REG(priv, reg + 8)) << 32;
887 return val;
888}
889
890/*Do the statistics-update work*/
891static void bdx_update_stats(struct bdx_priv *priv)
892{
893 struct bdx_stats *stats = &priv->hw_stats;
894 u64 *stats_vector = (u64 *) stats;
895 int i;
896 int addr;
897
898 /*Fill HW structure */
899 addr = 0x7200;
900 /*First 12 statistics - 0x7200 - 0x72B0 */
901 for (i = 0; i < 12; i++) {
902 stats_vector[i] = bdx_read_l2stat(priv, addr);
903 addr += 0x10;
904 }
905 BDX_ASSERT(addr != 0x72C0);
906 /* 0x72C0-0x72E0 RSRV */
907 addr = 0x72F0;
908 for (; i < 16; i++) {
909 stats_vector[i] = bdx_read_l2stat(priv, addr);
910 addr += 0x10;
911 }
912 BDX_ASSERT(addr != 0x7330);
913 /* 0x7330-0x7360 RSRV */
914 addr = 0x7370;
915 for (; i < 19; i++) {
916 stats_vector[i] = bdx_read_l2stat(priv, addr);
917 addr += 0x10;
918 }
919 BDX_ASSERT(addr != 0x73A0);
920 /* 0x73A0-0x73B0 RSRV */
921 addr = 0x73C0;
922 for (; i < 23; i++) {
923 stats_vector[i] = bdx_read_l2stat(priv, addr);
924 addr += 0x10;
925 }
926 BDX_ASSERT(addr != 0x7400);
927 BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i);
928}
929
930static struct net_device_stats *bdx_get_stats(struct net_device *ndev)
931{
8f15ea42 932 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 933 struct net_device_stats *net_stat = &priv->net_stats;
934 return net_stat;
935}
936
937static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
938 u16 rxd_vlan);
939static void print_rxfd(struct rxf_desc *rxfd);
940
941/*************************************************************************
942 * Rx DB *
943 *************************************************************************/
944
945static void bdx_rxdb_destroy(struct rxdb *db)
946{
c0feed87 947 vfree(db);
1a348ccc
AG		 948}
949
950static struct rxdb *bdx_rxdb_create(int nelem)
951{
952 struct rxdb *db;
953 int i;
954
955 db = vmalloc(sizeof(struct rxdb)
956 + (nelem * sizeof(int))
957 + (nelem * sizeof(struct rx_map)));
958 if (likely(db != NULL)) {
959 db->stack = (int *)(db + 1);
960 db->elems = (void *)(db->stack + nelem);
961 db->nelem = nelem;
962 db->top = nelem;
963 for (i = 0; i < nelem; i++)
964 db->stack[i] = nelem - i - 1; /* to make first allocs
965 close to db struct*/
966 }
967
968 return db;
969}
970
971static inline int bdx_rxdb_alloc_elem(struct rxdb *db)
972{
973 BDX_ASSERT(db->top <= 0);
974 return db->stack[--(db->top)];
975}
976
977static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n)
978{
979 BDX_ASSERT((n < 0) || (n >= db->nelem));
980 return db->elems + n;
981}
982
983static inline int bdx_rxdb_available(struct rxdb *db)
984{
985 return db->top;
986}
987
988static inline void bdx_rxdb_free_elem(struct rxdb *db, int n)
989{
990 BDX_ASSERT((n >= db->nelem) || (n < 0));
991 db->stack[(db->top)++] = n;
992}
993
994/*************************************************************************
995 * Rx Init *
996 *************************************************************************/
997
998/* bdx_rx_init - initialize RX all related HW and SW resources
999 * @priv - NIC private structure
1000 *
1001 * Returns 0 on success, negative value on failure
1002 *
1003 * It creates rxf and rxd fifos, update relevant HW registers, preallocate
1004 * skb for rx. It assumes that Rx is desabled in HW
1005 * funcs are grouped for better cache usage
1006 *
025dfdaf 1007 * RxD fifo is smaller than RxF fifo by design. Upon high load, RxD will be
1a348ccc
AG		 1008 * filled and packets will be dropped by nic without getting into host or
1009 * cousing interrupt. Anyway, in that condition, host has no chance to proccess
1010 * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
1011 */
1012
1013/* TBD: ensure proper packet size */
1014
1015static int bdx_rx_init(struct bdx_priv *priv)
1016{
1017 ENTER;
ddfce6bb 1018
1a348ccc
AG		 1019 if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size,
1020 regRXD_CFG0_0, regRXD_CFG1_0,
1021 regRXD_RPTR_0, regRXD_WPTR_0))
1022 goto err_mem;
1023 if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size,
1024 regRXF_CFG0_0, regRXF_CFG1_0,
1025 regRXF_RPTR_0, regRXF_WPTR_0))
1026 goto err_mem;
cb001a1f
JP		 1027 priv->rxdb = bdx_rxdb_create(priv->rxf_fifo0.m.memsz /
1028 sizeof(struct rxf_desc));
1029 if (!priv->rxdb)
1a348ccc
AG		 1030 goto err_mem;
1031
1032 priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN;
1033 return 0;
1034
1035err_mem:
865a21a5 1036 netdev_err(priv->ndev, "Rx init failed\n");
1a348ccc
AG		 1037 return -ENOMEM;
1038}
1039
1040/* bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo
1041 * @priv - NIC private structure
1042 * @f - RXF fifo
1043 */
1044static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1045{
1046 struct rx_map *dm;
1047 struct rxdb *db = priv->rxdb;
1048 u16 i;
1049
1050 ENTER;
1051 DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db),
1052 db->nelem - bdx_rxdb_available(db));
1053 while (bdx_rxdb_available(db) > 0) {
1054 i = bdx_rxdb_alloc_elem(db);
1055 dm = bdx_rxdb_addr_elem(db, i);
1056 dm->dma = 0;
1057 }
1058 for (i = 0; i < db->nelem; i++) {
1059 dm = bdx_rxdb_addr_elem(db, i);
1060 if (dm->dma) {
1061 pci_unmap_single(priv->pdev,
1062 dm->dma, f->m.pktsz,
1063 PCI_DMA_FROMDEVICE);
1064 dev_kfree_skb(dm->skb);
1065 }
1066 }
1067}
1068
1069/* bdx_rx_free - release all Rx resources
1070 * @priv - NIC private structure
1071 * It assumes that Rx is desabled in HW
1072 */
1073static void bdx_rx_free(struct bdx_priv *priv)
1074{
1075 ENTER;
1076 if (priv->rxdb) {
1077 bdx_rx_free_skbs(priv, &priv->rxf_fifo0);
1078 bdx_rxdb_destroy(priv->rxdb);
1079 priv->rxdb = NULL;
1080 }
1081 bdx_fifo_free(priv, &priv->rxf_fifo0.m);
1082 bdx_fifo_free(priv, &priv->rxd_fifo0.m);
1083
1084 RET();
1085}
1086
1087/*************************************************************************
1088 * Rx Engine *
1089 *************************************************************************/
1090
1091/* bdx_rx_alloc_skbs - fill rxf fifo with new skbs
1092 * @priv - nic's private structure
1093 * @f - RXF fifo that needs skbs
1094 * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo.
1095 * skb's virtual and physical addresses are stored in skb db.
1096 * To calculate free space, func uses cached values of RPTR and WPTR
1097 * When needed, it also updates RPTR and WPTR.
1098 */
1099
1100/* TBD: do not update WPTR if no desc were written */
1101
1102static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1103{
1104 struct sk_buff *skb;
1105 struct rxf_desc *rxfd;
1106 struct rx_map *dm;
1107 int dno, delta, idx;
1108 struct rxdb *db = priv->rxdb;
1109
1110 ENTER;
1111 dno = bdx_rxdb_available(db) - 1;
1112 while (dno > 0) {
cb001a1f
JP		 1113 skb = dev_alloc_skb(f->m.pktsz + NET_IP_ALIGN);
1114 if (!skb) {
865a21a5 1115 pr_err("NO MEM: dev_alloc_skb failed\n");
1a348ccc
AG		 1116 break;
1117 }
1118 skb->dev = priv->ndev;
1119 skb_reserve(skb, NET_IP_ALIGN);
1120
1121 idx = bdx_rxdb_alloc_elem(db);
1122 dm = bdx_rxdb_addr_elem(db, idx);
1123 dm->dma = pci_map_single(priv->pdev,
1124 skb->data, f->m.pktsz,
1125 PCI_DMA_FROMDEVICE);
1126 dm->skb = skb;
1127 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1128 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1129 rxfd->va_lo = idx;
1130 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1131 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1132 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1133 print_rxfd(rxfd);
1134
1135 f->m.wptr += sizeof(struct rxf_desc);
1136 delta = f->m.wptr - f->m.memsz;
1137 if (unlikely(delta >= 0)) {
1138 f->m.wptr = delta;
1139 if (delta > 0) {
1140 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1141 DBG("wrapped descriptor\n");
1142 }
1143 }
1144 dno--;
1145 }
1146 /*TBD: to do - delayed rxf wptr like in txd */
1147 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1148 RET();
1149}
1150
1151static inline void
1152NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan,
1153 struct sk_buff *skb)
1154{
1155 ENTER;
1156 DBG("rxdd->flags.bits.vtag=%d vlgrp=%p\n", GET_RXD_VTAG(rxd_val1),
1157 priv->vlgrp);
1158 if (priv->vlgrp && GET_RXD_VTAG(rxd_val1)) {
1159 DBG("%s: vlan rcv vlan '%x' vtag '%x', device name '%s'\n",
1160 priv->ndev->name,
1161 GET_RXD_VLAN_ID(rxd_vlan),
1162 GET_RXD_VTAG(rxd_val1),
1163 vlan_group_get_device(priv->vlgrp,
1164 GET_RXD_VLAN_ID(rxd_vlan))->name);
1165 /* NAPI variant of receive functions */
1166 vlan_hwaccel_receive_skb(skb, priv->vlgrp,
38b22195 1167 GET_RXD_VLAN_TCI(rxd_vlan));
1a348ccc
AG		 1168 } else {
1169 netif_receive_skb(skb);
1170 }
1171}
1172
1173static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd)
1174{
1175 struct rxf_desc *rxfd;
1176 struct rx_map *dm;
1177 struct rxf_fifo *f;
1178 struct rxdb *db;
1179 struct sk_buff *skb;
1180 int delta;
1181
1182 ENTER;
1183 DBG("priv=%p rxdd=%p\n", priv, rxdd);
1184 f = &priv->rxf_fifo0;
1185 db = priv->rxdb;
1186 DBG("db=%p f=%p\n", db, f);
1187 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1188 DBG("dm=%p\n", dm);
1189 skb = dm->skb;
1190 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1191 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1192 rxfd->va_lo = rxdd->va_lo;
1193 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1194 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1195 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1196 print_rxfd(rxfd);
1197
1198 f->m.wptr += sizeof(struct rxf_desc);
1199 delta = f->m.wptr - f->m.memsz;
1200 if (unlikely(delta >= 0)) {
1201 f->m.wptr = delta;
1202 if (delta > 0) {
1203 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1204 DBG("wrapped descriptor\n");
1205 }
1206 }
1207 RET();
1208}
1209
1210/* bdx_rx_receive - recieves full packets from RXD fifo and pass them to OS
1211 * NOTE: a special treatment is given to non-continous descriptors
1212 * that start near the end, wraps around and continue at the beginning. a second
1213 * part is copied right after the first, and then descriptor is interpreted as
1214 * normal. fifo has an extra space to allow such operations
1215 * @priv - nic's private structure
1216 * @f - RXF fifo that needs skbs
1217 */
1218
1219/* TBD: replace memcpy func call by explicite inline asm */
1220
1221static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget)
1222{
1223 struct sk_buff *skb, *skb2;
1224 struct rxd_desc *rxdd;
1225 struct rx_map *dm;
1226 struct rxf_fifo *rxf_fifo;
1227 int tmp_len, size;
1228 int done = 0;
1229 int max_done = BDX_MAX_RX_DONE;
1230 struct rxdb *db = NULL;
1231 /* Unmarshalled descriptor - copy of descriptor in host order */
1232 u32 rxd_val1;
1233 u16 len;
1234 u16 rxd_vlan;
1235
1236 ENTER;
1237 max_done = budget;
1238
1a348ccc
AG		 1239 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
1240
1241 size = f->m.wptr - f->m.rptr;
1242 if (size < 0)
1243 size = f->m.memsz + size; /* size is negative :-) */
1244
1245 while (size > 0) {
1246
1247 rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr);
1248 rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1);
1249
1250 len = CPU_CHIP_SWAP16(rxdd->len);
1251
1252 rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan);
1253
1254 print_rxdd(rxdd, rxd_val1, len, rxd_vlan);
1255
1256 tmp_len = GET_RXD_BC(rxd_val1) << 3;
1257 BDX_ASSERT(tmp_len <= 0);
1258 size -= tmp_len;
1259 if (size < 0) /* test for partially arrived descriptor */
1260 break;
1261
1262 f->m.rptr += tmp_len;
1263
1264 tmp_len = f->m.rptr - f->m.memsz;
1265 if (unlikely(tmp_len >= 0)) {
1266 f->m.rptr = tmp_len;
1267 if (tmp_len > 0) {
1268 DBG("wrapped desc rptr=%d tmp_len=%d\n",
1269 f->m.rptr, tmp_len);
1270 memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len);
1271 }
1272 }
1273
1274 if (unlikely(GET_RXD_ERR(rxd_val1))) {
1275 DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1));
1276 priv->net_stats.rx_errors++;
1277 bdx_recycle_skb(priv, rxdd);
1278 continue;
1279 }
1280
1281 rxf_fifo = &priv->rxf_fifo0;
1282 db = priv->rxdb;
1283 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1284 skb = dm->skb;
1285
1286 if (len < BDX_COPYBREAK &&
1287 (skb2 = dev_alloc_skb(len + NET_IP_ALIGN))) {
1288 skb_reserve(skb2, NET_IP_ALIGN);
1289 /*skb_put(skb2, len); */
1290 pci_dma_sync_single_for_cpu(priv->pdev,
1291 dm->dma, rxf_fifo->m.pktsz,
1292 PCI_DMA_FROMDEVICE);
1293 memcpy(skb2->data, skb->data, len);
1294 bdx_recycle_skb(priv, rxdd);
1295 skb = skb2;
1296 } else {
1297 pci_unmap_single(priv->pdev,
1298 dm->dma, rxf_fifo->m.pktsz,
1299 PCI_DMA_FROMDEVICE);
1300 bdx_rxdb_free_elem(db, rxdd->va_lo);
1301 }
1302
1303 priv->net_stats.rx_bytes += len;
1304
1305 skb_put(skb, len);
1a348ccc
AG		 1306 skb->ip_summed = CHECKSUM_UNNECESSARY;
1307 skb->protocol = eth_type_trans(skb, priv->ndev);
1308
1309 /* Non-IP packets aren't checksum-offloaded */
1310 if (GET_RXD_PKT_ID(rxd_val1) == 0)
1311 skb->ip_summed = CHECKSUM_NONE;
1312
1313 NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb);
1314
1315 if (++done >= max_done)
1316 break;
1317 }
1318
1319 priv->net_stats.rx_packets += done;
1320
1321 /* FIXME: do smth to minimize pci accesses */
1322 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1323
1324 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
1325
1326 RET(done);
1327}
1328
1329/*************************************************************************
1330 * Debug / Temprorary Code *
1331 *************************************************************************/
1332static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
1333 u16 rxd_vlan)
1334{
865a21a5 1335 DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d va_lo %d va_hi %d\n",
1a348ccc
AG		 1336 GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1),
1337 GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1),
1338 GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1),
1339 GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan),
1340 GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo,
1341 rxdd->va_hi);
1342}
1343
1344static void print_rxfd(struct rxf_desc *rxfd)
1345{
1346 DBG("=== RxF desc CHIP ORDER/ENDIANESS =============\n"
1347 "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
1348 rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len);
1349}
1350
1351/*
1352 * TX HW/SW interaction overview
1353 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1354 * There are 2 types of TX communication channels betwean driver and NIC.
1355 * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets
1356 * 2) TX Data Fifo - TXD - holds descriptors of full buffers.
1357 *
1358 * Currently NIC supports TSO, checksuming and gather DMA
1359 * UFO and IP fragmentation is on the way
1360 *
1361 * RX SW Data Structures
1362 * ~~~~~~~~~~~~~~~~~~~~~
1363 * txdb - used to keep track of all skbs owned by SW and their dma addresses.
1364 * For TX case, ownership lasts from geting packet via hard_xmit and until HW
1365 * acknowledges sent by TXF descriptors.
1366 * Implemented as cyclic buffer.
1367 * fifo - keeps info about fifo's size and location, relevant HW registers,
1368 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
1369 * Implemented as simple struct.
1370 *
1371 * TX SW Execution Flow
1372 * ~~~~~~~~~~~~~~~~~~~~
1373 * OS calls driver's hard_xmit method with packet to sent.
1374 * Driver creates DMA mappings, builds TXD descriptors and kicks HW
1375 * by updating TXD WPTR.
1376 * When packet is sent, HW write us TXF descriptor and SW frees original skb.
1377 * To prevent TXD fifo overflow without reading HW registers every time,
1378 * SW deploys "tx level" technique.
1379 * Upon strart up, tx level is initialized to TXD fifo length.
1380 * For every sent packet, SW gets its TXD descriptor sizei
1381 * (from precalculated array) and substructs it from tx level.
1382 * The size is also stored in txdb. When TXF ack arrives, SW fetch size of
1383 * original TXD descriptor from txdb and adds it to tx level.
1384 * When Tx level drops under some predefined treshhold, the driver
1385 * stops the TX queue. When TX level rises above that level,
1386 * the tx queue is enabled again.
1387 *
1388 * This technique avoids eccessive reading of RPTR and WPTR registers.
1389 * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput.
1390 */
1391
1392/*************************************************************************
1393 * Tx DB *
1394 *************************************************************************/
1395static inline int bdx_tx_db_size(struct txdb *db)
1396{
1397 int taken = db->wptr - db->rptr;
1398 if (taken < 0)
1399 taken = db->size + 1 + taken; /* (size + 1) equals memsz */
1400
1401 return db->size - taken;
1402}
1403
1404/* __bdx_tx_ptr_next - helper function, increment read/write pointer + wrap
1405 * @d - tx data base
1406 * @ptr - read or write pointer
1407 */
1408static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr)
1409{
1410 BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */
1411
1412 BDX_ASSERT(*pptr != db->rptr && /* expect either read */
1413 *pptr != db->wptr); /* or write pointer */
1414
1415 BDX_ASSERT(*pptr < db->start || /* pointer has to be */
1416 *pptr >= db->end); /* in range */
1417
1418 ++*pptr;
1419 if (unlikely(*pptr == db->end))
1420 *pptr = db->start;
1421}
1422
1423/* bdx_tx_db_inc_rptr - increment read pointer
1424 * @d - tx data base
1425 */
1426static inline void bdx_tx_db_inc_rptr(struct txdb *db)
1427{
1428 BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */
1429 __bdx_tx_db_ptr_next(db, &db->rptr);
1430}
1431
1432/* bdx_tx_db_inc_rptr - increment write pointer
1433 * @d - tx data base
1434 */
1435static inline void bdx_tx_db_inc_wptr(struct txdb *db)
1436{
1437 __bdx_tx_db_ptr_next(db, &db->wptr);
1438 BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as
1439 a result of write */
1440}
1441
1442/* bdx_tx_db_init - creates and initializes tx db
1443 * @d - tx data base
1444 * @sz_type - size of tx fifo
1445 * Returns 0 on success, error code otherwise
1446 */
1447static int bdx_tx_db_init(struct txdb *d, int sz_type)
1448{
1449 int memsz = FIFO_SIZE * (1 << (sz_type + 1));
1450
1451 d->start = vmalloc(memsz);
1452 if (!d->start)
1453 return -ENOMEM;
1454
1455 /*
1456 * In order to differentiate between db is empty and db is full
1457 * states at least one element should always be empty in order to
1458 * avoid rptr == wptr which means db is empty
1459 */
1460 d->size = memsz / sizeof(struct tx_map) - 1;
1461 d->end = d->start + d->size + 1; /* just after last element */
1462
1463 /* all dbs are created equally empty */
1464 d->rptr = d->start;
1465 d->wptr = d->start;
1466
1467 return 0;
1468}
1469
1470/* bdx_tx_db_close - closes tx db and frees all memory
1471 * @d - tx data base
1472 */
1473static void bdx_tx_db_close(struct txdb *d)
1474{
1475 BDX_ASSERT(d == NULL);
1476
c0feed87
F		 1477 vfree(d->start);
1478 d->start = NULL;
1a348ccc
AG		 1479}
1480
1481/*************************************************************************
1482 * Tx Engine *
1483 *************************************************************************/
1484
1485/* sizes of tx desc (including padding if needed) as function
1486 * of skb's frag number */
1487static struct {
1488 u16 bytes;
1489 u16 qwords; /* qword = 64 bit */
1490} txd_sizes[MAX_SKB_FRAGS + 1];
1491
1492/* txdb_map_skb - creates and stores dma mappings for skb's data blocks
1493 * @priv - NIC private structure
1494 * @skb - socket buffer to map
1495 *
1496 * It makes dma mappings for skb's data blocks and writes them to PBL of
1497 * new tx descriptor. It also stores them in the tx db, so they could be
1498 * unmaped after data was sent. It is reponsibility of a caller to make
1499 * sure that there is enough space in the tx db. Last element holds pointer
1500 * to skb itself and marked with zero length
1501 */
1502static inline void
1503bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb,
1504 struct txd_desc *txdd)
1505{
1506 struct txdb *db = &priv->txdb;
1507 struct pbl *pbl = &txdd->pbl[0];
1508 int nr_frags = skb_shinfo(skb)->nr_frags;
1509 int i;
1510
1511 db->wptr->len = skb->len - skb->data_len;
1512 db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data,
1513 db->wptr->len, PCI_DMA_TODEVICE);
1514 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1515 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1516 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1517 DBG("=== pbl len: 0x%x ================\n", pbl->len);
1518 DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo);
1519 DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi);
1520 bdx_tx_db_inc_wptr(db);
1521
1522 for (i = 0; i < nr_frags; i++) {
1523 struct skb_frag_struct *frag;
1524
1525 frag = &skb_shinfo(skb)->frags[i];
1526 db->wptr->len = frag->size;
1527 db->wptr->addr.dma =
1528 pci_map_page(priv->pdev, frag->page, frag->page_offset,
1529 frag->size, PCI_DMA_TODEVICE);
1530
1531 pbl++;
1532 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1533 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1534 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1535 bdx_tx_db_inc_wptr(db);
1536 }
1537
1538 /* add skb clean up info. */
1539 db->wptr->len = -txd_sizes[nr_frags].bytes;
1540 db->wptr->addr.skb = skb;
1541 bdx_tx_db_inc_wptr(db);
1542}
1543
1544/* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags
1545 * number of frags is used as index to fetch correct descriptors size,
1546 * instead of calculating it each time */
1547static void __init init_txd_sizes(void)
1548{
1549 int i, lwords;
1550
1551 /* 7 - is number of lwords in txd with one phys buffer
1552 * 3 - is number of lwords used for every additional phys buffer */
1553 for (i = 0; i < MAX_SKB_FRAGS + 1; i++) {
1554 lwords = 7 + (i * 3);
1555 if (lwords & 1)
1556 lwords++; /* pad it with 1 lword */
1557 txd_sizes[i].qwords = lwords >> 1;
1558 txd_sizes[i].bytes = lwords << 2;
1559 }
1560}
1561
1562/* bdx_tx_init - initialize all Tx related stuff.
1563 * Namely, TXD and TXF fifos, database etc */
1564static int bdx_tx_init(struct bdx_priv *priv)
1565{
1566 if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size,
1567 regTXD_CFG0_0,
1568 regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0))
1569 goto err_mem;
1570 if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size,
1571 regTXF_CFG0_0,
1572 regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0))
1573 goto err_mem;
1574
1575 /* The TX db has to keep mappings for all packets sent (on TxD)
1576 * and not yet reclaimed (on TxF) */
1577 if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size)))
1578 goto err_mem;
1579
1580 priv->tx_level = BDX_MAX_TX_LEVEL;
1581#ifdef BDX_DELAY_WPTR
1582 priv->tx_update_mark = priv->tx_level - 1024;
1583#endif
1584 return 0;
1585
1586err_mem:
865a21a5 1587 netdev_err(priv->ndev, "Tx init failed\n");
1a348ccc
AG		 1588 return -ENOMEM;
1589}
1590
1591/*
1592 * bdx_tx_space - calculates avalable space in TX fifo
1593 * @priv - NIC private structure
1594 * Returns avaliable space in TX fifo in bytes
1595 */
1596static inline int bdx_tx_space(struct bdx_priv *priv)
1597{
1598 struct txd_fifo *f = &priv->txd_fifo0;
1599 int fsize;
1600
1601 f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR;
1602 fsize = f->m.rptr - f->m.wptr;
1603 if (fsize <= 0)
1604 fsize = f->m.memsz + fsize;
249658d5 1605 return fsize;
1a348ccc
AG		 1606}
1607
1608/* bdx_tx_transmit - send packet to NIC
1609 * @skb - packet to send
1610 * ndev - network device assigned to NIC
1611 * Return codes:
1612 * o NETDEV_TX_OK everything ok.
1613 * o NETDEV_TX_BUSY Cannot transmit packet, try later
1614 * Usually a bug, means queue start/stop flow control is broken in
1615 * the driver. Note: the driver must NOT put the skb in its DMA ring.
1616 * o NETDEV_TX_LOCKED Locking failed, please retry quickly.
1617 */
61357325
SH		 1618static netdev_tx_t bdx_tx_transmit(struct sk_buff *skb,
1619 struct net_device *ndev)
1a348ccc 1620{
8f15ea42 1621 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 1622 struct txd_fifo *f = &priv->txd_fifo0;
1623 int txd_checksum = 7; /* full checksum */
1624 int txd_lgsnd = 0;
1625 int txd_vlan_id = 0;
1626 int txd_vtag = 0;
1627 int txd_mss = 0;
1628
1629 int nr_frags = skb_shinfo(skb)->nr_frags;
1630 struct txd_desc *txdd;
1631 int len;
1632 unsigned long flags;
1633
1634 ENTER;
1635 local_irq_save(flags);
1636 if (!spin_trylock(&priv->tx_lock)) {
1637 local_irq_restore(flags);
1638 DBG("%s[%s]: TX locked, returning NETDEV_TX_LOCKED\n",
1639 BDX_DRV_NAME, ndev->name);
1640 return NETDEV_TX_LOCKED;
1641 }
1642
1643 /* build tx descriptor */
1644 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */
1645 txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
1646 if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL))
1647 txd_checksum = 0;
1648
1649 if (skb_shinfo(skb)->gso_size) {
1650 txd_mss = skb_shinfo(skb)->gso_size;
1651 txd_lgsnd = 1;
1652 DBG("skb %p skb len %d gso size = %d\n", skb, skb->len,
1653 txd_mss);
1654 }
1655
1656 if (vlan_tx_tag_present(skb)) {
1657 /*Cut VLAN ID to 12 bits */
1658 txd_vlan_id = vlan_tx_tag_get(skb) & BITS_MASK(12);
1659 txd_vtag = 1;
1660 }
1661
1662 txdd->length = CPU_CHIP_SWAP16(skb->len);
1663 txdd->mss = CPU_CHIP_SWAP16(txd_mss);
1664 txdd->txd_val1 =
1665 CPU_CHIP_SWAP32(TXD_W1_VAL
1666 (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag,
1667 txd_lgsnd, txd_vlan_id));
1668 DBG("=== TxD desc =====================\n");
1669 DBG("=== w1: 0x%x ================\n", txdd->txd_val1);
1670 DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length);
1671
1672 bdx_tx_map_skb(priv, skb, txdd);
1673
1674 /* increment TXD write pointer. In case of
1675 fifo wrapping copy reminder of the descriptor
1676 to the beginning */
1677 f->m.wptr += txd_sizes[nr_frags].bytes;
1678 len = f->m.wptr - f->m.memsz;
1679 if (unlikely(len >= 0)) {
1680 f->m.wptr = len;
1681 if (len > 0) {
1682 BDX_ASSERT(len > f->m.memsz);
1683 memcpy(f->m.va, f->m.va + f->m.memsz, len);
1684 }
1685 }
1686 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */
1687
1688 priv->tx_level -= txd_sizes[nr_frags].bytes;
1689 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1690#ifdef BDX_DELAY_WPTR
1691 if (priv->tx_level > priv->tx_update_mark) {
1692 /* Force memory writes to complete before letting h/w
1693 know there are new descriptors to fetch.
1694 (might be needed on platforms like IA64)
1695 wmb(); */
1696 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1697 } else {
1698 if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) {
1699 priv->tx_noupd = 0;
1700 WRITE_REG(priv, f->m.reg_WPTR,
1701 f->m.wptr & TXF_WPTR_WR_PTR);
1702 }
1703 }
1704#else
1705 /* Force memory writes to complete before letting h/w
1706 know there are new descriptors to fetch.
1707 (might be needed on platforms like IA64)
1708 wmb(); */
1709 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1710
1711#endif
28679751
ED		 1712#ifdef BDX_LLTX
1713 ndev->trans_start = jiffies; /* NETIF_F_LLTX driver :( */
1714#endif
1a348ccc
AG		 1715 priv->net_stats.tx_packets++;
1716 priv->net_stats.tx_bytes += skb->len;
1717
1718 if (priv->tx_level < BDX_MIN_TX_LEVEL) {
1719 DBG("%s: %s: TX Q STOP level %d\n",
1720 BDX_DRV_NAME, ndev->name, priv->tx_level);
1721 netif_stop_queue(ndev);
1722 }
1723
1724 spin_unlock_irqrestore(&priv->tx_lock, flags);
1725 return NETDEV_TX_OK;
1726}
1727
1728/* bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ.
1729 * @priv - bdx adapter
1730 * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS
1731 * that those packets were sent
1732 */
1733static void bdx_tx_cleanup(struct bdx_priv *priv)
1734{
1735 struct txf_fifo *f = &priv->txf_fifo0;
1736 struct txdb *db = &priv->txdb;
1737 int tx_level = 0;
1738
1739 ENTER;
1740 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
1741 BDX_ASSERT(f->m.rptr >= f->m.memsz); /* started with valid rptr */
1742
1743 while (f->m.wptr != f->m.rptr) {
1744 f->m.rptr += BDX_TXF_DESC_SZ;
1745 f->m.rptr &= f->m.size_mask;
1746
1747 /* unmap all the fragments */
1748 /* first has to come tx_maps containing dma */
1749 BDX_ASSERT(db->rptr->len == 0);
1750 do {
1751 BDX_ASSERT(db->rptr->addr.dma == 0);
1752 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1753 db->rptr->len, PCI_DMA_TODEVICE);
1754 bdx_tx_db_inc_rptr(db);
1755 } while (db->rptr->len > 0);
1756 tx_level -= db->rptr->len; /* '-' koz len is negative */
1757
1758 /* now should come skb pointer - free it */
1a348ccc
AG		 1759 dev_kfree_skb_irq(db->rptr->addr.skb);
1760 bdx_tx_db_inc_rptr(db);
1761 }
1762
1763 /* let h/w know which TXF descriptors were cleaned */
1764 BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
1765 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1766
1767 /* We reclaimed resources, so in case the Q is stopped by xmit callback,
1768 * we resume the transmition and use tx_lock to synchronize with xmit.*/
1769 spin_lock(&priv->tx_lock);
1770 priv->tx_level += tx_level;
1771 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1772#ifdef BDX_DELAY_WPTR
1773 if (priv->tx_noupd) {
1774 priv->tx_noupd = 0;
1775 WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,
1776 priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
1777 }
1778#endif
1779
8e95a202
JP		 1780 if (unlikely(netif_queue_stopped(priv->ndev) &&
1781 netif_carrier_ok(priv->ndev) &&
1782 (priv->tx_level >= BDX_MIN_TX_LEVEL))) {
1a348ccc
AG		 1783 DBG("%s: %s: TX Q WAKE level %d\n",
1784 BDX_DRV_NAME, priv->ndev->name, priv->tx_level);
1785 netif_wake_queue(priv->ndev);
1786 }
1787 spin_unlock(&priv->tx_lock);
1788}
1789
1790/* bdx_tx_free_skbs - frees all skbs from TXD fifo.
1791 * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod
1792 */
1793static void bdx_tx_free_skbs(struct bdx_priv *priv)
1794{
1795 struct txdb *db = &priv->txdb;
1796
1797 ENTER;
1798 while (db->rptr != db->wptr) {
1799 if (likely(db->rptr->len))
1800 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1801 db->rptr->len, PCI_DMA_TODEVICE);
1802 else
1803 dev_kfree_skb(db->rptr->addr.skb);
1804 bdx_tx_db_inc_rptr(db);
1805 }
1806 RET();
1807}
1808
1809/* bdx_tx_free - frees all Tx resources */
1810static void bdx_tx_free(struct bdx_priv *priv)
1811{
1812 ENTER;
1813 bdx_tx_free_skbs(priv);
1814 bdx_fifo_free(priv, &priv->txd_fifo0.m);
1815 bdx_fifo_free(priv, &priv->txf_fifo0.m);
1816 bdx_tx_db_close(&priv->txdb);
1817}
1818
1819/* bdx_tx_push_desc - push descriptor to TxD fifo
1820 * @priv - NIC private structure
1821 * @data - desc's data
1822 * @size - desc's size
1823 *
1824 * Pushes desc to TxD fifo and overlaps it if needed.
1825 * NOTE: this func does not check for available space. this is responsibility
025dfdaf 1826 * of the caller. Neither does it check that data size is smaller than
1a348ccc
AG		 1827 * fifo size.
1828 */
1829static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size)
1830{
1831 struct txd_fifo *f = &priv->txd_fifo0;
1832 int i = f->m.memsz - f->m.wptr;
1833
1834 if (size == 0)
1835 return;
1836
1837 if (i > size) {
1838 memcpy(f->m.va + f->m.wptr, data, size);
1839 f->m.wptr += size;
1840 } else {
1841 memcpy(f->m.va + f->m.wptr, data, i);
1842 f->m.wptr = size - i;
1843 memcpy(f->m.va, data + i, f->m.wptr);
1844 }
1845 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1846}
1847
1848/* bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way
1849 * @priv - NIC private structure
1850 * @data - desc's data
1851 * @size - desc's size
1852 *
3ad2f3fb 1853 * NOTE: this func does check for available space and, if necessary, waits for
1a348ccc
AG		 1854 * NIC to read existing data before writing new one.
1855 */
1856static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size)
1857{
1858 int timer = 0;
1859 ENTER;
1860
1861 while (size > 0) {
1862 /* we substruct 8 because when fifo is full rptr == wptr
1863 which also means that fifo is empty, we can understand
1864 the difference, but could hw do the same ??? :) */
1865 int avail = bdx_tx_space(priv) - 8;
1866 if (avail <= 0) {
1867 if (timer++ > 300) { /* prevent endless loop */
1868 DBG("timeout while writing desc to TxD fifo\n");
1869 break;
1870 }
1871 udelay(50); /* give hw a chance to clean fifo */
1872 continue;
1873 }
df7641af 1874 avail = min(avail, size);
1a348ccc
AG		 1875 DBG("about to push %d bytes starting %p size %d\n", avail,
1876 data, size);
1877 bdx_tx_push_desc(priv, data, avail);
1878 size -= avail;
1879 data += avail;
1880 }
1881 RET();
1882}
1883
2f30b1f6
SH		 1884static const struct net_device_ops bdx_netdev_ops = {
1885 .ndo_open = bdx_open,
1886 .ndo_stop = bdx_close,
1887 .ndo_start_xmit = bdx_tx_transmit,
1888 .ndo_validate_addr = eth_validate_addr,
1889 .ndo_do_ioctl = bdx_ioctl,
1890 .ndo_set_multicast_list = bdx_setmulti,
1891 .ndo_get_stats = bdx_get_stats,
1892 .ndo_change_mtu = bdx_change_mtu,
1893 .ndo_set_mac_address = bdx_set_mac,
1894 .ndo_vlan_rx_register = bdx_vlan_rx_register,
1895 .ndo_vlan_rx_add_vid = bdx_vlan_rx_add_vid,
1896 .ndo_vlan_rx_kill_vid = bdx_vlan_rx_kill_vid,
1897};
1898
1a348ccc
AG		 1899/**
1900 * bdx_probe - Device Initialization Routine
1901 * @pdev: PCI device information struct
1902 * @ent: entry in bdx_pci_tbl
1903 *
1904 * Returns 0 on success, negative on failure
1905 *
1906 * bdx_probe initializes an adapter identified by a pci_dev structure.
1907 * The OS initialization, configuring of the adapter private structure,
1908 * and a hardware reset occur.
1909 *
1910 * functions and their order used as explained in
1911 * /usr/src/linux/Documentation/DMA-{API,mapping}.txt
1912 *
1913 */
1914
1915/* TBD: netif_msg should be checked and implemented. I disable it for now */
1916static int __devinit
1917bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1918{
1919 struct net_device *ndev;
1920 struct bdx_priv *priv;
1921 int err, pci_using_dac, port;
1922 unsigned long pciaddr;
1923 u32 regionSize;
1924 struct pci_nic *nic;
1925
1926 ENTER;
1927
1928 nic = vmalloc(sizeof(*nic));
1929 if (!nic)
1930 RET(-ENOMEM);
1931
1932 /************** pci *****************/
cb001a1f
JP		 1933 err = pci_enable_device(pdev);
1934 if (err) /* it triggers interrupt, dunno why. */
1935 goto err_pci; /* it's not a problem though */
1a348ccc 1936
6a35528a
YH		 1937 if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) &&
1938 !(err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))) {
1a348ccc
AG		 1939 pci_using_dac = 1;
1940 } else {
284901a9
YH		 1941 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1942 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
865a21a5 1943 pr_err("No usable DMA configuration, aborting\n");
1a348ccc
AG		 1944 goto err_dma;
1945 }
1946 pci_using_dac = 0;
1947 }
1948
cb001a1f
JP		 1949 err = pci_request_regions(pdev, BDX_DRV_NAME);
1950 if (err)
1a348ccc
AG		 1951 goto err_dma;
1952
1953 pci_set_master(pdev);
1954
1955 pciaddr = pci_resource_start(pdev, 0);
1956 if (!pciaddr) {
1957 err = -EIO;
865a21a5 1958 pr_err("no MMIO resource\n");
1a348ccc
AG		 1959 goto err_out_res;
1960 }
cb001a1f
JP		 1961 regionSize = pci_resource_len(pdev, 0);
1962 if (regionSize < BDX_REGS_SIZE) {
1a348ccc 1963 err = -EIO;
865a21a5 1964 pr_err("MMIO resource (%x) too small\n", regionSize);
1a348ccc
AG		 1965 goto err_out_res;
1966 }
1967
1968 nic->regs = ioremap(pciaddr, regionSize);
1969 if (!nic->regs) {
1970 err = -EIO;
865a21a5 1971 pr_err("ioremap failed\n");
1a348ccc
AG		 1972 goto err_out_res;
1973 }
1974
1975 if (pdev->irq < 2) {
1976 err = -EIO;
865a21a5 1977 pr_err("invalid irq (%d)\n", pdev->irq);
1a348ccc
AG		 1978 goto err_out_iomap;
1979 }
1980 pci_set_drvdata(pdev, nic);
1981
1982 if (pdev->device == 0x3014)
1983 nic->port_num = 2;
1984 else
1985 nic->port_num = 1;
1986
1987 print_hw_id(pdev);
1988
1989 bdx_hw_reset_direct(nic->regs);
1990
1991 nic->irq_type = IRQ_INTX;
1992#ifdef BDX_MSI
1993 if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) {
cb001a1f
JP		 1994 err = pci_enable_msi(pdev);
1995 if (err)
865a21a5 1996 pr_err("Can't eneble msi. error is %d\n", err);
1a348ccc
AG		 1997 else
1998 nic->irq_type = IRQ_MSI;
1999 } else
2000 DBG("HW does not support MSI\n");
2001#endif
2002
2003 /************** netdev **************/
2004 for (port = 0; port < nic->port_num; port++) {
cb001a1f
JP		 2005 ndev = alloc_etherdev(sizeof(struct bdx_priv));
2006 if (!ndev) {
1a348ccc 2007 err = -ENOMEM;
865a21a5 2008 pr_err("alloc_etherdev failed\n");
1a348ccc
AG		 2009 goto err_out_iomap;
2010 }
2011
2f30b1f6 2012 ndev->netdev_ops = &bdx_netdev_ops;
1a348ccc 2013 ndev->tx_queue_len = BDX_NDEV_TXQ_LEN;
1a348ccc
AG		 2014
2015 bdx_ethtool_ops(ndev); /* ethtool interface */
2016
2017 /* these fields are used for info purposes only
2018 * so we can have them same for all ports of the board */
2019 ndev->if_port = port;
2020 ndev->base_addr = pciaddr;
2021 ndev->mem_start = pciaddr;
2022 ndev->mem_end = pciaddr + regionSize;
2023 ndev->irq = pdev->irq;
2024 ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO
2025 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
2026 NETIF_F_HW_VLAN_FILTER
2027 /*| NETIF_F_FRAGLIST */
2028 ;
2029
2030 if (pci_using_dac)
2031 ndev->features |= NETIF_F_HIGHDMA;
2032
2033 /************** priv ****************/
8f15ea42 2034 priv = nic->priv[port] = netdev_priv(ndev);
1a348ccc
AG		 2035
2036 memset(priv, 0, sizeof(struct bdx_priv));
2037 priv->pBdxRegs = nic->regs + port * 0x8000;
2038 priv->port = port;
2039 priv->pdev = pdev;
2040 priv->ndev = ndev;
2041 priv->nic = nic;
2042 priv->msg_enable = BDX_DEF_MSG_ENABLE;
2043
2044 netif_napi_add(ndev, &priv->napi, bdx_poll, 64);
2045
2046 if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) {
2047 DBG("HW statistics not supported\n");
2048 priv->stats_flag = 0;
2049 } else {
2050 priv->stats_flag = 1;
2051 }
2052
2053 /* Initialize fifo sizes. */
2054 priv->txd_size = 2;
2055 priv->txf_size = 2;
2056 priv->rxd_size = 2;
2057 priv->rxf_size = 3;
2058
2059 /* Initialize the initial coalescing registers. */
2060 priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12);
2061 priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12);
2062
2063 /* ndev->xmit_lock spinlock is not used.
2064 * Private priv->tx_lock is used for synchronization
2065 * between transmit and TX irq cleanup. In addition
2066 * set multicast list callback has to use priv->tx_lock.
2067 */
2068#ifdef BDX_LLTX
2069 ndev->features |= NETIF_F_LLTX;
2070#endif
2071 spin_lock_init(&priv->tx_lock);
2072
2073 /*bdx_hw_reset(priv); */
2074 if (bdx_read_mac(priv)) {
865a21a5 2075 pr_err("load MAC address failed\n");
1a348ccc
AG		 2076 goto err_out_iomap;
2077 }
2078 SET_NETDEV_DEV(ndev, &pdev->dev);
cb001a1f
JP		 2079 err = register_netdev(ndev);
2080 if (err) {
865a21a5 2081 pr_err("register_netdev failed\n");
1a348ccc
AG		 2082 goto err_out_free;
2083 }
2084 netif_carrier_off(ndev);
2085 netif_stop_queue(ndev);
2086
2087 print_eth_id(ndev);
2088 }
2089 RET(0);
2090
2091err_out_free:
2092 free_netdev(ndev);
2093err_out_iomap:
2094 iounmap(nic->regs);
2095err_out_res:
2096 pci_release_regions(pdev);
2097err_dma:
2098 pci_disable_device(pdev);
bc2618f7 2099err_pci:
1a348ccc
AG		 2100 vfree(nic);
2101
2102 RET(err);
2103}
2104
2105/****************** Ethtool interface *********************/
1a348ccc
AG		 2106/* get strings for statistics counters */
2107static const char
2108 bdx_stat_names[][ETH_GSTRING_LEN] = {
2109 "InUCast", /* 0x7200 */
2110 "InMCast", /* 0x7210 */
2111 "InBCast", /* 0x7220 */
2112 "InPkts", /* 0x7230 */
2113 "InErrors", /* 0x7240 */
2114 "InDropped", /* 0x7250 */
2115 "FrameTooLong", /* 0x7260 */
2116 "FrameSequenceErrors", /* 0x7270 */
2117 "InVLAN", /* 0x7280 */
2118 "InDroppedDFE", /* 0x7290 */
2119 "InDroppedIntFull", /* 0x72A0 */
2120 "InFrameAlignErrors", /* 0x72B0 */
2121
2122 /* 0x72C0-0x72E0 RSRV */
2123
2124 "OutUCast", /* 0x72F0 */
2125 "OutMCast", /* 0x7300 */
2126 "OutBCast", /* 0x7310 */
2127 "OutPkts", /* 0x7320 */
2128
2129 /* 0x7330-0x7360 RSRV */
2130
2131 "OutVLAN", /* 0x7370 */
2132 "InUCastOctects", /* 0x7380 */
2133 "OutUCastOctects", /* 0x7390 */
2134
2135 /* 0x73A0-0x73B0 RSRV */
2136
2137 "InBCastOctects", /* 0x73C0 */
2138 "OutBCastOctects", /* 0x73D0 */
2139 "InOctects", /* 0x73E0 */
2140 "OutOctects", /* 0x73F0 */
2141};
2142
2143/*
2144 * bdx_get_settings - get device-specific settings
2145 * @netdev
2146 * @ecmd
2147 */
2148static int bdx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
2149{
2150 u32 rdintcm;
2151 u32 tdintcm;
8f15ea42 2152 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2153
2154 rdintcm = priv->rdintcm;
2155 tdintcm = priv->tdintcm;
2156
2157 ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
2158 ecmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
2159 ecmd->speed = SPEED_10000;
2160 ecmd->duplex = DUPLEX_FULL;
2161 ecmd->port = PORT_FIBRE;
2162 ecmd->transceiver = XCVR_EXTERNAL; /* what does it mean? */
2163 ecmd->autoneg = AUTONEG_DISABLE;
2164
2165 /* PCK_TH measures in multiples of FIFO bytes
2166 We translate to packets */
2167 ecmd->maxtxpkt =
2168 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2169 ecmd->maxrxpkt =
2170 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2171
2172 return 0;
2173}
2174
2175/*
2176 * bdx_get_drvinfo - report driver information
2177 * @netdev
2178 * @drvinfo
2179 */
2180static void
2181bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
2182{
8f15ea42 2183 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc 2184
072ee3f9
RK		 2185 strlcat(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver));
2186 strlcat(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version));
2187 strlcat(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
2188 strlcat(drvinfo->bus_info, pci_name(priv->pdev),
1a348ccc
AG		 2189 sizeof(drvinfo->bus_info));
2190
4c3616cd 2191 drvinfo->n_stats = ((priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0);
1a348ccc
AG		 2192 drvinfo->testinfo_len = 0;
2193 drvinfo->regdump_len = 0;
2194 drvinfo->eedump_len = 0;
2195}
2196
2197/*
2198 * bdx_get_rx_csum - report whether receive checksums are turned on or off
2199 * @netdev
2200 */
2201static u32 bdx_get_rx_csum(struct net_device *netdev)
2202{
2203 return 1; /* always on */
2204}
2205
2206/*
2207 * bdx_get_tx_csum - report whether transmit checksums are turned on or off
2208 * @netdev
2209 */
2210static u32 bdx_get_tx_csum(struct net_device *netdev)
2211{
2212 return (netdev->features & NETIF_F_IP_CSUM) != 0;
2213}
2214
2215/*
2216 * bdx_get_coalesce - get interrupt coalescing parameters
2217 * @netdev
2218 * @ecoal
2219 */
2220static int
2221bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2222{
2223 u32 rdintcm;
2224 u32 tdintcm;
8f15ea42 2225 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2226
2227 rdintcm = priv->rdintcm;
2228 tdintcm = priv->tdintcm;
2229
2230 /* PCK_TH measures in multiples of FIFO bytes
2231 We translate to packets */
2232 ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT;
2233 ecoal->rx_max_coalesced_frames =
2234 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2235
2236 ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT;
2237 ecoal->tx_max_coalesced_frames =
2238 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2239
2240 /* adaptive parameters ignored */
2241 return 0;
2242}
2243
2244/*
2245 * bdx_set_coalesce - set interrupt coalescing parameters
2246 * @netdev
2247 * @ecoal
2248 */
2249static int
2250bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2251{
2252 u32 rdintcm;
2253 u32 tdintcm;
8f15ea42 2254 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2255 int rx_coal;
2256 int tx_coal;
2257 int rx_max_coal;
2258 int tx_max_coal;
2259
2260 /* Check for valid input */
2261 rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT;
2262 tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT;
2263 rx_max_coal = ecoal->rx_max_coalesced_frames;
2264 tx_max_coal = ecoal->tx_max_coalesced_frames;
2265
2266 /* Translate from packets to multiples of FIFO bytes */
2267 rx_max_coal =
2268 (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1)
2269 / PCK_TH_MULT);
2270 tx_max_coal =
2271 (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1)
2272 / PCK_TH_MULT);
2273
8e95a202
JP		 2274 if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF) ||
2275 (rx_max_coal > 0xF) || (tx_max_coal > 0xF))
1a348ccc
AG		 2276 return -EINVAL;
2277
2278 rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm),
2279 GET_RXF_TH(priv->rdintcm), rx_max_coal);
2280 tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0,
2281 tx_max_coal);
2282
2283 priv->rdintcm = rdintcm;
2284 priv->tdintcm = tdintcm;
2285
2286 WRITE_REG(priv, regRDINTCM0, rdintcm);
2287 WRITE_REG(priv, regTDINTCM0, tdintcm);
2288
2289 return 0;
2290}
2291
2292/* Convert RX fifo size to number of pending packets */
2293static inline int bdx_rx_fifo_size_to_packets(int rx_size)
2294{
249658d5 2295 return (FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc);
1a348ccc
AG		 2296}
2297
2298/* Convert TX fifo size to number of pending packets */
2299static inline int bdx_tx_fifo_size_to_packets(int tx_size)
2300{
249658d5 2301 return (FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ;
1a348ccc
AG		 2302}
2303
2304/*
2305 * bdx_get_ringparam - report ring sizes
2306 * @netdev
2307 * @ring
2308 */
2309static void
2310bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2311{
8f15ea42 2312 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2313
2314 /*max_pending - the maximum-sized FIFO we allow */
2315 ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3);
2316 ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3);
2317 ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size);
2318 ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size);
2319}
2320
2321/*
2322 * bdx_set_ringparam - set ring sizes
2323 * @netdev
2324 * @ring
2325 */
2326static int
2327bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2328{
8f15ea42 2329 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2330 int rx_size = 0;
2331 int tx_size = 0;
2332
2333 for (; rx_size < 4; rx_size++) {
2334 if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending)
2335 break;
2336 }
2337 if (rx_size == 4)
2338 rx_size = 3;
2339
2340 for (; tx_size < 4; tx_size++) {
2341 if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending)
2342 break;
2343 }
2344 if (tx_size == 4)
2345 tx_size = 3;
2346
2347 /*Is there anything to do? */
8e95a202
JP		 2348 if ((rx_size == priv->rxf_size) &&
2349 (tx_size == priv->txd_size))
1a348ccc
AG		 2350 return 0;
2351
2352 priv->rxf_size = rx_size;
2353 if (rx_size > 1)
2354 priv->rxd_size = rx_size - 1;
2355 else
2356 priv->rxd_size = rx_size;
2357
2358 priv->txf_size = priv->txd_size = tx_size;
2359
2360 if (netif_running(netdev)) {
2361 bdx_close(netdev);
2362 bdx_open(netdev);
2363 }
2364 return 0;
2365}
2366
2367/*
2368 * bdx_get_strings - return a set of strings that describe the requested objects
2369 * @netdev
2370 * @data
2371 */
2372static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2373{
2374 switch (stringset) {
1a348ccc
AG		 2375 case ETH_SS_STATS:
2376 memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names));
2377 break;
2378 }
2379}
2380
2381/*
1ddee09f 2382 * bdx_get_sset_count - return number of statistics or tests
1a348ccc
AG		 2383 * @netdev
2384 */
1ddee09f 2385static int bdx_get_sset_count(struct net_device *netdev, int stringset)
1a348ccc 2386{
8f15ea42 2387 struct bdx_priv *priv = netdev_priv(netdev);
1ddee09f
BH		 2388
2389 switch (stringset) {
2390 case ETH_SS_STATS:
2391 BDX_ASSERT(ARRAY_SIZE(bdx_stat_names)
2392 != sizeof(struct bdx_stats) / sizeof(u64));
249658d5 2393 return (priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0;
1ddee09f 2394 }
249658d5
JP		 2395
2396 return -EINVAL;
1a348ccc
AG		 2397}
2398
2399/*
2400 * bdx_get_ethtool_stats - return device's hardware L2 statistics
2401 * @netdev
2402 * @stats
2403 * @data
2404 */
2405static void bdx_get_ethtool_stats(struct net_device *netdev,
2406 struct ethtool_stats *stats, u64 *data)
2407{
8f15ea42 2408 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2409
2410 if (priv->stats_flag) {
2411
2412 /* Update stats from HW */
2413 bdx_update_stats(priv);
2414
2415 /* Copy data to user buffer */
2416 memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats));
2417 }
2418}
2419
2420/*
2421 * bdx_ethtool_ops - ethtool interface implementation
2422 * @netdev
2423 */
2424static void bdx_ethtool_ops(struct net_device *netdev)
2425{
0fc0b732 2426 static const struct ethtool_ops bdx_ethtool_ops = {
1a348ccc
AG		 2427 .get_settings = bdx_get_settings,
2428 .get_drvinfo = bdx_get_drvinfo,
2429 .get_link = ethtool_op_get_link,
2430 .get_coalesce = bdx_get_coalesce,
2431 .set_coalesce = bdx_set_coalesce,
2432 .get_ringparam = bdx_get_ringparam,
2433 .set_ringparam = bdx_set_ringparam,
2434 .get_rx_csum = bdx_get_rx_csum,
2435 .get_tx_csum = bdx_get_tx_csum,
2436 .get_sg = ethtool_op_get_sg,
2437 .get_tso = ethtool_op_get_tso,
2438 .get_strings = bdx_get_strings,
1ddee09f 2439 .get_sset_count = bdx_get_sset_count,
1a348ccc
AG		 2440 .get_ethtool_stats = bdx_get_ethtool_stats,
2441 };
2442
2443 SET_ETHTOOL_OPS(netdev, &bdx_ethtool_ops);
2444}
2445
2446/**
2447 * bdx_remove - Device Removal Routine
2448 * @pdev: PCI device information struct
2449 *
2450 * bdx_remove is called by the PCI subsystem to alert the driver
2451 * that it should release a PCI device. The could be caused by a
2452 * Hot-Plug event, or because the driver is going to be removed from
2453 * memory.
2454 **/
2455static void __devexit bdx_remove(struct pci_dev *pdev)
2456{
2457 struct pci_nic *nic = pci_get_drvdata(pdev);
2458 struct net_device *ndev;
2459 int port;
2460
2461 for (port = 0; port < nic->port_num; port++) {
2462 ndev = nic->priv[port]->ndev;
2463 unregister_netdev(ndev);
2464 free_netdev(ndev);
2465 }
2466
2467 /*bdx_hw_reset_direct(nic->regs); */
2468#ifdef BDX_MSI
2469 if (nic->irq_type == IRQ_MSI)
2470 pci_disable_msi(pdev);
2471#endif
2472
2473 iounmap(nic->regs);
2474 pci_release_regions(pdev);
2475 pci_disable_device(pdev);
2476 pci_set_drvdata(pdev, NULL);
2477 vfree(nic);
2478
2479 RET();
2480}
2481
2482static struct pci_driver bdx_pci_driver = {
2483 .name = BDX_DRV_NAME,
2484 .id_table = bdx_pci_tbl,
2485 .probe = bdx_probe,
2486 .remove = __devexit_p(bdx_remove),
2487};
2488
2489/*
2490 * print_driver_id - print parameters of the driver build
2491 */
2492static void __init print_driver_id(void)
2493{
865a21a5
JP		 2494 pr_info("%s, %s\n", BDX_DRV_DESC, BDX_DRV_VERSION);
2495 pr_info("Options: hw_csum %s\n", BDX_MSI_STRING);
1a348ccc
AG		 2496}
2497
2498static int __init bdx_module_init(void)
2499{
2500 ENTER;
1a348ccc
AG		 2501 init_txd_sizes();
2502 print_driver_id();
2503 RET(pci_register_driver(&bdx_pci_driver));
2504}
2505
2506module_init(bdx_module_init);
2507
2508static void __exit bdx_module_exit(void)
2509{
2510 ENTER;
2511 pci_unregister_driver(&bdx_pci_driver);
2512 RET();
2513}
2514
2515module_exit(bdx_module_exit);
2516
2517MODULE_LICENSE("GPL");
2518MODULE_AUTHOR(DRIVER_AUTHOR);
2519MODULE_DESCRIPTION(BDX_DRV_DESC);
06e1f9ff 2520MODULE_FIRMWARE("tehuti/firmware.bin");
Clone of davem's net-next-2.6 tree