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1a348ccc
AG		 1/*
2 * Tehuti Networks(R) Network Driver
3 * ethtool interface implementation
4 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12/*
13 * RX HW/SW interaction overview
14 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
15 * There are 2 types of RX communication channels betwean driver and NIC.
16 * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
17 * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
18 * info about buffer's location, size and ID. An ID field is used to identify a
19 * buffer when it's returned with data via RXD Fifo (see below)
20 * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
21 * filled by HW and is readen by SW. Each descriptor holds status and ID.
22 * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
23 * via dma moves it into host memory, builds new RXD descriptor with same ID,
24 * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
25 *
26 * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos.
27 * One holds 1.5K packets and another - 26K packets. Depending on incoming
28 * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
29 * filled with data, HW builds new RXD descriptor for it and push it into single
30 * RXD Fifo.
31 *
32 * RX SW Data Structures
33 * ~~~~~~~~~~~~~~~~~~~~~
34 * skb db - used to keep track of all skbs owned by SW and their dma addresses.
35 * For RX case, ownership lasts from allocating new empty skb for RXF until
36 * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own
37 * skb db. Implemented as array with bitmask.
38 * fifo - keeps info about fifo's size and location, relevant HW registers,
39 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
40 * Implemented as simple struct.
41 *
42 * RX SW Execution Flow
43 * ~~~~~~~~~~~~~~~~~~~~
44 * Upon initialization (ifconfig up) driver creates RX fifos and initializes
45 * relevant registers. At the end of init phase, driver enables interrupts.
46 * NIC sees that there is no RXF buffers and raises
47 * RD_INTR interrupt, isr fills skbs and Rx begins.
48 * Driver has two receive operation modes:
49 * NAPI - interrupt-driven mixed with polling
50 * interrupt-driven only
51 *
52 * Interrupt-driven only flow is following. When buffer is ready, HW raises
53 * interrupt and isr is called. isr collects all available packets
54 * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit.
55
56 * Rx buffer allocation note
57 * ~~~~~~~~~~~~~~~~~~~~~~~~~
58 * Driver cares to feed such amount of RxF descriptors that respective amount of
59 * RxD descriptors can not fill entire RxD fifo. The main reason is lack of
60 * overflow check in Bordeaux for RxD fifo free/used size.
61 * FIXME: this is NOT fully implemented, more work should be done
62 *
63 */
64
65#include "tehuti.h"
66#include "tehuti_fw.h"
67
68static struct pci_device_id __devinitdata bdx_pci_tbl[] = {
69 {0x1FC9, 0x3009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
70 {0x1FC9, 0x3010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
71 {0x1FC9, 0x3014, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
72 {0}
73};
74
75MODULE_DEVICE_TABLE(pci, bdx_pci_tbl);
76
77/* Definitions needed by ISR or NAPI functions */
78static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f);
79static void bdx_tx_cleanup(struct bdx_priv *priv);
80static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget);
81
82/* Definitions needed by FW loading */
83static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size);
84
85/* Definitions needed by hw_start */
86static int bdx_tx_init(struct bdx_priv *priv);
87static int bdx_rx_init(struct bdx_priv *priv);
88
89/* Definitions needed by bdx_close */
90static void bdx_rx_free(struct bdx_priv *priv);
91static void bdx_tx_free(struct bdx_priv *priv);
92
93/* Definitions needed by bdx_probe */
94static void bdx_ethtool_ops(struct net_device *netdev);
95
96/*************************************************************************
97 * Print Info *
98 *************************************************************************/
99
100static void print_hw_id(struct pci_dev *pdev)
101{
102 struct pci_nic *nic = pci_get_drvdata(pdev);
103 u16 pci_link_status = 0;
104 u16 pci_ctrl = 0;
105
106 pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status);
107 pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl);
108
109 printk(KERN_INFO "tehuti: %s%s\n", BDX_NIC_NAME,
110 nic->port_num == 1 ? "" : ", 2-Port");
111 printk(KERN_INFO
112 "tehuti: srom 0x%x fpga %d build %u lane# %d"
113 " max_pl 0x%x mrrs 0x%x\n",
114 readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF,
115 readl(nic->regs + FPGA_SEED),
116 GET_LINK_STATUS_LANES(pci_link_status),
117 GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl));
118}
119
120static void print_fw_id(struct pci_nic *nic)
121{
122 printk(KERN_INFO "tehuti: fw 0x%x\n", readl(nic->regs + FW_VER));
123}
124
125static void print_eth_id(struct net_device *ndev)
126{
127 printk(KERN_INFO "%s: %s, Port %c\n", ndev->name, BDX_NIC_NAME,
128 (ndev->if_port == 0) ? 'A' : 'B');
129
130}
131
132/*************************************************************************
133 * Code *
134 *************************************************************************/
135
136#define bdx_enable_interrupts(priv) \
137 do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
138#define bdx_disable_interrupts(priv) \
139 do { WRITE_REG(priv, regIMR, 0); } while (0)
140
141/* bdx_fifo_init
142 * create TX/RX descriptor fifo for host-NIC communication.
143 * 1K extra space is allocated at the end of the fifo to simplify
144 * processing of descriptors that wraps around fifo's end
145 * @priv - NIC private structure
146 * @f - fifo to initialize
147 * @fsz_type - fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
148 * @reg_XXX - offsets of registers relative to base address
149 *
150 * Returns 0 on success, negative value on failure
151 *
152 */
153static int
154bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type,
155 u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR)
156{
157 u16 memsz = FIFO_SIZE * (1 << fsz_type);
158
159 memset(f, 0, sizeof(struct fifo));
160 /* pci_alloc_consistent gives us 4k-aligned memory */
161 f->va = pci_alloc_consistent(priv->pdev,
162 memsz + FIFO_EXTRA_SPACE, &f->da);
163 if (!f->va) {
164 ERR("pci_alloc_consistent failed\n");
165 RET(-ENOMEM);
166 }
167 f->reg_CFG0 = reg_CFG0;
168 f->reg_CFG1 = reg_CFG1;
169 f->reg_RPTR = reg_RPTR;
170 f->reg_WPTR = reg_WPTR;
171 f->rptr = 0;
172 f->wptr = 0;
173 f->memsz = memsz;
174 f->size_mask = memsz - 1;
175 WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
176 WRITE_REG(priv, reg_CFG1, H32_64(f->da));
177
178 RET(0);
179}
180
181/* bdx_fifo_free - free all resources used by fifo
182 * @priv - NIC private structure
183 * @f - fifo to release
184 */
185static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f)
186{
187 ENTER;
188 if (f->va) {
189 pci_free_consistent(priv->pdev,
190 f->memsz + FIFO_EXTRA_SPACE, f->va, f->da);
191 f->va = NULL;
192 }
193 RET();
194}
195
196/*
197 * bdx_link_changed - notifies OS about hw link state.
198 * @bdx_priv - hw adapter structure
199 */
200static void bdx_link_changed(struct bdx_priv *priv)
201{
202 u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT;
203
204 if (!link) {
205 if (netif_carrier_ok(priv->ndev)) {
206 netif_stop_queue(priv->ndev);
207 netif_carrier_off(priv->ndev);
208 ERR("%s: Link Down\n", priv->ndev->name);
209 }
210 } else {
211 if (!netif_carrier_ok(priv->ndev)) {
212 netif_wake_queue(priv->ndev);
213 netif_carrier_on(priv->ndev);
214 ERR("%s: Link Up\n", priv->ndev->name);
215 }
216 }
217}
218
219static void bdx_isr_extra(struct bdx_priv *priv, u32 isr)
220{
221 if (isr & IR_RX_FREE_0) {
222 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
223 DBG("RX_FREE_0\n");
224 }
225
226 if (isr & IR_LNKCHG0)
227 bdx_link_changed(priv);
228
229 if (isr & IR_PCIE_LINK)
230 ERR("%s: PCI-E Link Fault\n", priv->ndev->name);
231
232 if (isr & IR_PCIE_TOUT)
233 ERR("%s: PCI-E Time Out\n", priv->ndev->name);
234
235}
236
237/* bdx_isr - Interrupt Service Routine for Bordeaux NIC
238 * @irq - interrupt number
239 * @ndev - network device
240 * @regs - CPU registers
241 *
242 * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise
243 *
244 * It reads ISR register to know interrupt reasons, and proceed them one by one.
245 * Reasons of interest are:
246 * RX_DESC - new packet has arrived and RXD fifo holds its descriptor
247 * RX_FREE - number of free Rx buffers in RXF fifo gets low
248 * TX_FREE - packet was transmited and RXF fifo holds its descriptor
249 */
250
251static irqreturn_t bdx_isr_napi(int irq, void *dev)
252{
253 struct net_device *ndev = dev;
8f15ea42 254 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 255 u32 isr;
256
257 ENTER;
258 isr = (READ_REG(priv, regISR) & IR_RUN);
259 if (unlikely(!isr)) {
260 bdx_enable_interrupts(priv);
261 return IRQ_NONE; /* Not our interrupt */
262 }
263
264 if (isr & IR_EXTRA)
265 bdx_isr_extra(priv, isr);
266
267 if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) {
288379f0
BH		 268 if (likely(napi_schedule_prep(&priv->napi))) {
269 __napi_schedule(&priv->napi);
1a348ccc
AG		 270 RET(IRQ_HANDLED);
271 } else {
272 /* NOTE: we get here if intr has slipped into window
273 * between these lines in bdx_poll:
274 * bdx_enable_interrupts(priv);
275 * return 0;
276 * currently intrs are disabled (since we read ISR),
277 * and we have failed to register next poll.
278 * so we read the regs to trigger chip
279 * and allow further interupts. */
280 READ_REG(priv, regTXF_WPTR_0);
281 READ_REG(priv, regRXD_WPTR_0);
282 }
283 }
284
285 bdx_enable_interrupts(priv);
286 RET(IRQ_HANDLED);
287}
288
289static int bdx_poll(struct napi_struct *napi, int budget)
290{
291 struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi);
1a348ccc
AG		 292 int work_done;
293
294 ENTER;
295 bdx_tx_cleanup(priv);
296 work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget);
297 if ((work_done < budget) ||
298 (priv->napi_stop++ >= 30)) {
299 DBG("rx poll is done. backing to isr-driven\n");
300
301 /* from time to time we exit to let NAPI layer release
302 * device lock and allow waiting tasks (eg rmmod) to advance) */
303 priv->napi_stop = 0;
304
288379f0 305 napi_complete(napi);
1a348ccc
AG		 306 bdx_enable_interrupts(priv);
307 }
308 return work_done;
309}
310
311/* bdx_fw_load - loads firmware to NIC
312 * @priv - NIC private structure
313 * Firmware is loaded via TXD fifo, so it must be initialized first.
314 * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC
315 * can have few of them). So all drivers use semaphore register to choose one
316 * that will actually load FW to NIC.
317 */
318
319static int bdx_fw_load(struct bdx_priv *priv)
320{
321 int master, i;
322
323 ENTER;
324 master = READ_REG(priv, regINIT_SEMAPHORE);
325 if (!READ_REG(priv, regINIT_STATUS) && master) {
326 bdx_tx_push_desc_safe(priv, s_firmLoad, sizeof(s_firmLoad));
327 mdelay(100);
328 }
329 for (i = 0; i < 200; i++) {
330 if (READ_REG(priv, regINIT_STATUS))
331 break;
332 mdelay(2);
333 }
334 if (master)
335 WRITE_REG(priv, regINIT_SEMAPHORE, 1);
336
337 if (i == 200) {
338 ERR("%s: firmware loading failed\n", priv->ndev->name);
339 DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",
340 READ_REG(priv, regVPC),
341 READ_REG(priv, regVIC), READ_REG(priv, regINIT_STATUS), i);
342 RET(-EIO);
343 } else {
344 DBG("%s: firmware loading success\n", priv->ndev->name);
345 RET(0);
346 }
347}
348
349static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv)
350{
351 u32 val;
352
353 ENTER;
354 DBG("mac0=%x mac1=%x mac2=%x\n",
355 READ_REG(priv, regUNC_MAC0_A),
356 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
357
358 val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);
359 WRITE_REG(priv, regUNC_MAC2_A, val);
360 val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]);
361 WRITE_REG(priv, regUNC_MAC1_A, val);
362 val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]);
363 WRITE_REG(priv, regUNC_MAC0_A, val);
364
365 DBG("mac0=%x mac1=%x mac2=%x\n",
366 READ_REG(priv, regUNC_MAC0_A),
367 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
368 RET();
369}
370
371/* bdx_hw_start - inits registers and starts HW's Rx and Tx engines
372 * @priv - NIC private structure
373 */
374static int bdx_hw_start(struct bdx_priv *priv)
375{
376 int rc = -EIO;
377 struct net_device *ndev = priv->ndev;
378
379 ENTER;
380 bdx_link_changed(priv);
381
382 /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */
383 WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);
384 WRITE_REG(priv, regPAUSE_QUANT, 0x96);
385 WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);
386 WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);
387 WRITE_REG(priv, regRX_FULLNESS, 0);
388 WRITE_REG(priv, regTX_FULLNESS, 0);
389 WRITE_REG(priv, regCTRLST,
390 regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA);
391
392 WRITE_REG(priv, regVGLB, 0);
393 WRITE_REG(priv, regMAX_FRAME_A,
394 priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL);
395
396 DBG("RDINTCM=%08x\n", priv->rdintcm); /*NOTE: test script uses this */
397 WRITE_REG(priv, regRDINTCM0, priv->rdintcm);
398 WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */
399
400 DBG("TDINTCM=%08x\n", priv->tdintcm); /*NOTE: test script uses this */
401 WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */
402
403 /* Enable timer interrupt once in 2 secs. */
404 /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */
405 bdx_restore_mac(priv->ndev, priv);
406
407 WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |
408 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB);
409
410#define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI)?0:IRQF_SHARED)
411 if ((rc = request_irq(priv->pdev->irq, &bdx_isr_napi, BDX_IRQ_TYPE,
412 ndev->name, ndev)))
413 goto err_irq;
414 bdx_enable_interrupts(priv);
415
416 RET(0);
417
418err_irq:
419 RET(rc);
420}
421
422static void bdx_hw_stop(struct bdx_priv *priv)
423{
424 ENTER;
425 bdx_disable_interrupts(priv);
426 free_irq(priv->pdev->irq, priv->ndev);
427
428 netif_carrier_off(priv->ndev);
429 netif_stop_queue(priv->ndev);
430
431 RET();
432}
433
434static int bdx_hw_reset_direct(void __iomem *regs)
435{
436 u32 val, i;
437 ENTER;
438
439 /* reset sequences: read, write 1, read, write 0 */
440 val = readl(regs + regCLKPLL);
441 writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);
442 udelay(50);
443 val = readl(regs + regCLKPLL);
444 writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL);
445
446 /* check that the PLLs are locked and reset ended */
447 for (i = 0; i < 70; i++, mdelay(10))
448 if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
449 /* do any PCI-E read transaction */
450 readl(regs + regRXD_CFG0_0);
451 return 0;
452 }
453 ERR("tehuti: HW reset failed\n");
454 return 1; /* failure */
455}
456
457static int bdx_hw_reset(struct bdx_priv *priv)
458{
459 u32 val, i;
460 ENTER;
461
462 if (priv->port == 0) {
463 /* reset sequences: read, write 1, read, write 0 */
464 val = READ_REG(priv, regCLKPLL);
465 WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);
466 udelay(50);
467 val = READ_REG(priv, regCLKPLL);
468 WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);
469 }
470 /* check that the PLLs are locked and reset ended */
471 for (i = 0; i < 70; i++, mdelay(10))
472 if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
473 /* do any PCI-E read transaction */
474 READ_REG(priv, regRXD_CFG0_0);
475 return 0;
476 }
477 ERR("tehuti: HW reset failed\n");
478 return 1; /* failure */
479}
480
481static int bdx_sw_reset(struct bdx_priv *priv)
482{
483 int i;
484
485 ENTER;
486 /* 1. load MAC (obsolete) */
487 /* 2. disable Rx (and Tx) */
488 WRITE_REG(priv, regGMAC_RXF_A, 0);
489 mdelay(100);
490 /* 3. disable port */
491 WRITE_REG(priv, regDIS_PORT, 1);
492 /* 4. disable queue */
493 WRITE_REG(priv, regDIS_QU, 1);
494 /* 5. wait until hw is disabled */
495 for (i = 0; i < 50; i++) {
496 if (READ_REG(priv, regRST_PORT) & 1)
497 break;
498 mdelay(10);
499 }
500 if (i == 50)
501 ERR("%s: SW reset timeout. continuing anyway\n",
502 priv->ndev->name);
503
504 /* 6. disable intrs */
505 WRITE_REG(priv, regRDINTCM0, 0);
506 WRITE_REG(priv, regTDINTCM0, 0);
507 WRITE_REG(priv, regIMR, 0);
508 READ_REG(priv, regISR);
509
510 /* 7. reset queue */
511 WRITE_REG(priv, regRST_QU, 1);
512 /* 8. reset port */
513 WRITE_REG(priv, regRST_PORT, 1);
514 /* 9. zero all read and write pointers */
515 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
516 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
517 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
518 WRITE_REG(priv, i, 0);
519 /* 10. unseet port disable */
520 WRITE_REG(priv, regDIS_PORT, 0);
521 /* 11. unset queue disable */
522 WRITE_REG(priv, regDIS_QU, 0);
523 /* 12. unset queue reset */
524 WRITE_REG(priv, regRST_QU, 0);
525 /* 13. unset port reset */
526 WRITE_REG(priv, regRST_PORT, 0);
527 /* 14. enable Rx */
528 /* skiped. will be done later */
529 /* 15. save MAC (obsolete) */
530 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
531 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
532
533 RET(0);
534}
535
536/* bdx_reset - performs right type of reset depending on hw type */
537static int bdx_reset(struct bdx_priv *priv)
538{
539 ENTER;
540 RET((priv->pdev->device == 0x3009)
541 ? bdx_hw_reset(priv)
542 : bdx_sw_reset(priv));
543}
544
545/**
546 * bdx_close - Disables a network interface
547 * @netdev: network interface device structure
548 *
549 * Returns 0, this is not allowed to fail
550 *
551 * The close entry point is called when an interface is de-activated
552 * by the OS. The hardware is still under the drivers control, but
553 * needs to be disabled. A global MAC reset is issued to stop the
554 * hardware, and all transmit and receive resources are freed.
555 **/
556static int bdx_close(struct net_device *ndev)
557{
558 struct bdx_priv *priv = NULL;
559
560 ENTER;
8f15ea42 561 priv = netdev_priv(ndev);
1a348ccc
AG		 562
563 napi_disable(&priv->napi);
564
565 bdx_reset(priv);
566 bdx_hw_stop(priv);
567 bdx_rx_free(priv);
568 bdx_tx_free(priv);
569 RET(0);
570}
571
572/**
573 * bdx_open - Called when a network interface is made active
574 * @netdev: network interface device structure
575 *
576 * Returns 0 on success, negative value on failure
577 *
578 * The open entry point is called when a network interface is made
579 * active by the system (IFF_UP). At this point all resources needed
580 * for transmit and receive operations are allocated, the interrupt
581 * handler is registered with the OS, the watchdog timer is started,
582 * and the stack is notified that the interface is ready.
583 **/
584static int bdx_open(struct net_device *ndev)
585{
586 struct bdx_priv *priv;
587 int rc;
588
589 ENTER;
8f15ea42 590 priv = netdev_priv(ndev);
1a348ccc
AG		 591 bdx_reset(priv);
592 if (netif_running(ndev))
593 netif_stop_queue(priv->ndev);
594
595 if ((rc = bdx_tx_init(priv)))
596 goto err;
597
598 if ((rc = bdx_rx_init(priv)))
599 goto err;
600
601 if ((rc = bdx_fw_load(priv)))
602 goto err;
603
604 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
605
606 if ((rc = bdx_hw_start(priv)))
607 goto err;
608
609 napi_enable(&priv->napi);
610
611 print_fw_id(priv->nic);
612
613 RET(0);
614
615err:
616 bdx_close(ndev);
617 RET(rc);
618}
619
620static void __init bdx_firmware_endianess(void)
621{
622 int i;
c00acf46 623 for (i = 0; i < ARRAY_SIZE(s_firmLoad); i++)
1a348ccc
AG		 624 s_firmLoad[i] = CPU_CHIP_SWAP32(s_firmLoad[i]);
625}
626
6131a260
FR		 627static int bdx_range_check(struct bdx_priv *priv, u32 offset)
628{
629 return (offset > (u32) (BDX_REGS_SIZE / priv->nic->port_num)) ?
630 -EINVAL : 0;
631}
632
1a348ccc
AG		 633static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd)
634{
8f15ea42 635 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 636 u32 data[3];
637 int error;
638
639 ENTER;
640
641 DBG("jiffies=%ld cmd=%d\n", jiffies, cmd);
642 if (cmd != SIOCDEVPRIVATE) {
643 error = copy_from_user(data, ifr->ifr_data, sizeof(data));
644 if (error) {
645 ERR("cant copy from user\n");
646 RET(error);
647 }
648 DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]);
649 }
650
62035542 651 if (!capable(CAP_SYS_RAWIO))
f946dffe
JG		 652 return -EPERM;
653
1a348ccc
AG		 654 switch (data[0]) {
655
656 case BDX_OP_READ:
6131a260
FR		 657 error = bdx_range_check(priv, data[1]);
658 if (error < 0)
659 return error;
1a348ccc
AG		 660 data[2] = READ_REG(priv, data[1]);
661 DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2],
662 data[2]);
663 error = copy_to_user(ifr->ifr_data, data, sizeof(data));
664 if (error)
665 RET(error);
666 break;
667
668 case BDX_OP_WRITE:
6131a260
FR		 669 error = bdx_range_check(priv, data[1]);
670 if (error < 0)
671 return error;
1a348ccc
AG		 672 WRITE_REG(priv, data[1], data[2]);
673 DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]);
674 break;
675
676 default:
677 RET(-EOPNOTSUPP);
678 }
679 return 0;
680}
681
682static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
683{
684 ENTER;
685 if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15))
686 RET(bdx_ioctl_priv(ndev, ifr, cmd));
687 else
688 RET(-EOPNOTSUPP);
689}
690
691/*
692 * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid
693 * by passing VLAN filter table to hardware
694 * @ndev network device
695 * @vid VLAN vid
696 * @op add or kill operation
697 */
698static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable)
699{
8f15ea42 700 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 701 u32 reg, bit, val;
702
703 ENTER;
704 DBG2("vid=%d value=%d\n", (int)vid, enable);
705 if (unlikely(vid >= 4096)) {
706 ERR("tehuti: invalid VID: %u (> 4096)\n", vid);
707 RET();
708 }
709 reg = regVLAN_0 + (vid / 32) * 4;
710 bit = 1 << vid % 32;
711 val = READ_REG(priv, reg);
712 DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit);
713 if (enable)
714 val |= bit;
715 else
716 val &= ~bit;
717 DBG2("new val %x\n", val);
718 WRITE_REG(priv, reg, val);
719 RET();
720}
721
722/*
723 * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table
724 * @ndev network device
725 * @vid VLAN vid to add
726 */
727static void bdx_vlan_rx_add_vid(struct net_device *ndev, uint16_t vid)
728{
729 __bdx_vlan_rx_vid(ndev, vid, 1);
730}
731
732/*
733 * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table
734 * @ndev network device
735 * @vid VLAN vid to kill
736 */
737static void bdx_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid)
738{
739 __bdx_vlan_rx_vid(ndev, vid, 0);
740}
741
742/*
743 * bdx_vlan_rx_register - kernel hook for adding VLAN group
744 * @ndev network device
745 * @grp VLAN group
746 */
747static void
748bdx_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
749{
8f15ea42 750 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 751
752 ENTER;
753 DBG("device='%s', group='%p'\n", ndev->name, grp);
754 priv->vlgrp = grp;
755 RET();
756}
757
758/**
759 * bdx_change_mtu - Change the Maximum Transfer Unit
760 * @netdev: network interface device structure
761 * @new_mtu: new value for maximum frame size
762 *
763 * Returns 0 on success, negative on failure
764 */
765static int bdx_change_mtu(struct net_device *ndev, int new_mtu)
766{
1a348ccc
AG		 767 ENTER;
768
769 if (new_mtu == ndev->mtu)
770 RET(0);
771
772 /* enforce minimum frame size */
773 if (new_mtu < ETH_ZLEN) {
774 ERR("%s: %s mtu %d is less then minimal %d\n",
775 BDX_DRV_NAME, ndev->name, new_mtu, ETH_ZLEN);
776 RET(-EINVAL);
777 }
778
779 ndev->mtu = new_mtu;
780 if (netif_running(ndev)) {
781 bdx_close(ndev);
782 bdx_open(ndev);
783 }
784 RET(0);
785}
786
787static void bdx_setmulti(struct net_device *ndev)
788{
8f15ea42 789 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 790
791 u32 rxf_val =
792 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN;
793 int i;
794
795 ENTER;
796 /* IMF - imperfect (hash) rx multicat filter */
797 /* PMF - perfect rx multicat filter */
798
799 /* FIXME: RXE(OFF) */
800 if (ndev->flags & IFF_PROMISC) {
801 rxf_val |= GMAC_RX_FILTER_PRM;
802 } else if (ndev->flags & IFF_ALLMULTI) {
803 /* set IMF to accept all multicast frmaes */
804 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
805 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);
806 } else if (ndev->mc_count) {
807 u8 hash;
808 struct dev_mc_list *mclist;
809 u32 reg, val;
810
811 /* set IMF to deny all multicast frames */
812 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
813 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);
814 /* set PMF to deny all multicast frames */
815 for (i = 0; i < MAC_MCST_NUM; i++) {
816 WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);
817 WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);
818 }
819
820 /* use PMF to accept first MAC_MCST_NUM (15) addresses */
821 /* TBD: sort addreses and write them in ascending order
822 * into RX_MAC_MCST regs. we skip this phase now and accept ALL
823 * multicast frames throu IMF */
824 mclist = ndev->mc_list;
825
826 /* accept the rest of addresses throu IMF */
827 for (; mclist; mclist = mclist->next) {
828 hash = 0;
829 for (i = 0; i < ETH_ALEN; i++)
830 hash ^= mclist->dmi_addr[i];
831 reg = regRX_MCST_HASH0 + ((hash >> 5) << 2);
832 val = READ_REG(priv, reg);
833 val |= (1 << (hash % 32));
834 WRITE_REG(priv, reg, val);
835 }
836
837 } else {
838 DBG("only own mac %d\n", ndev->mc_count);
839 rxf_val |= GMAC_RX_FILTER_AB;
840 }
841 WRITE_REG(priv, regGMAC_RXF_A, rxf_val);
842 /* enable RX */
843 /* FIXME: RXE(ON) */
844 RET();
845}
846
847static int bdx_set_mac(struct net_device *ndev, void *p)
848{
8f15ea42 849 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 850 struct sockaddr *addr = p;
851
852 ENTER;
853 /*
854 if (netif_running(dev))
855 return -EBUSY
856 */
857 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
858 bdx_restore_mac(ndev, priv);
859 RET(0);
860}
861
862static int bdx_read_mac(struct bdx_priv *priv)
863{
864 u16 macAddress[3], i;
865 ENTER;
866
867 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
868 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
869 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
870 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
871 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
872 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
873 for (i = 0; i < 3; i++) {
874 priv->ndev->dev_addr[i * 2 + 1] = macAddress[i];
875 priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8;
876 }
877 RET(0);
878}
879
880static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg)
881{
882 u64 val;
883
884 val = READ_REG(priv, reg);
885 val |= ((u64) READ_REG(priv, reg + 8)) << 32;
886 return val;
887}
888
889/*Do the statistics-update work*/
890static void bdx_update_stats(struct bdx_priv *priv)
891{
892 struct bdx_stats *stats = &priv->hw_stats;
893 u64 *stats_vector = (u64 *) stats;
894 int i;
895 int addr;
896
897 /*Fill HW structure */
898 addr = 0x7200;
899 /*First 12 statistics - 0x7200 - 0x72B0 */
900 for (i = 0; i < 12; i++) {
901 stats_vector[i] = bdx_read_l2stat(priv, addr);
902 addr += 0x10;
903 }
904 BDX_ASSERT(addr != 0x72C0);
905 /* 0x72C0-0x72E0 RSRV */
906 addr = 0x72F0;
907 for (; i < 16; i++) {
908 stats_vector[i] = bdx_read_l2stat(priv, addr);
909 addr += 0x10;
910 }
911 BDX_ASSERT(addr != 0x7330);
912 /* 0x7330-0x7360 RSRV */
913 addr = 0x7370;
914 for (; i < 19; i++) {
915 stats_vector[i] = bdx_read_l2stat(priv, addr);
916 addr += 0x10;
917 }
918 BDX_ASSERT(addr != 0x73A0);
919 /* 0x73A0-0x73B0 RSRV */
920 addr = 0x73C0;
921 for (; i < 23; i++) {
922 stats_vector[i] = bdx_read_l2stat(priv, addr);
923 addr += 0x10;
924 }
925 BDX_ASSERT(addr != 0x7400);
926 BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i);
927}
928
929static struct net_device_stats *bdx_get_stats(struct net_device *ndev)
930{
8f15ea42 931 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 932 struct net_device_stats *net_stat = &priv->net_stats;
933 return net_stat;
934}
935
936static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
937 u16 rxd_vlan);
938static void print_rxfd(struct rxf_desc *rxfd);
939
940/*************************************************************************
941 * Rx DB *
942 *************************************************************************/
943
944static void bdx_rxdb_destroy(struct rxdb *db)
945{
946 if (db)
947 vfree(db);
948}
949
950static struct rxdb *bdx_rxdb_create(int nelem)
951{
952 struct rxdb *db;
953 int i;
954
955 db = vmalloc(sizeof(struct rxdb)
956 + (nelem * sizeof(int))
957 + (nelem * sizeof(struct rx_map)));
958 if (likely(db != NULL)) {
959 db->stack = (int *)(db + 1);
960 db->elems = (void *)(db->stack + nelem);
961 db->nelem = nelem;
962 db->top = nelem;
963 for (i = 0; i < nelem; i++)
964 db->stack[i] = nelem - i - 1; /* to make first allocs
965 close to db struct*/
966 }
967
968 return db;
969}
970
971static inline int bdx_rxdb_alloc_elem(struct rxdb *db)
972{
973 BDX_ASSERT(db->top <= 0);
974 return db->stack[--(db->top)];
975}
976
977static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n)
978{
979 BDX_ASSERT((n < 0) || (n >= db->nelem));
980 return db->elems + n;
981}
982
983static inline int bdx_rxdb_available(struct rxdb *db)
984{
985 return db->top;
986}
987
988static inline void bdx_rxdb_free_elem(struct rxdb *db, int n)
989{
990 BDX_ASSERT((n >= db->nelem) || (n < 0));
991 db->stack[(db->top)++] = n;
992}
993
994/*************************************************************************
995 * Rx Init *
996 *************************************************************************/
997
998/* bdx_rx_init - initialize RX all related HW and SW resources
999 * @priv - NIC private structure
1000 *
1001 * Returns 0 on success, negative value on failure
1002 *
1003 * It creates rxf and rxd fifos, update relevant HW registers, preallocate
1004 * skb for rx. It assumes that Rx is desabled in HW
1005 * funcs are grouped for better cache usage
1006 *
025dfdaf 1007 * RxD fifo is smaller than RxF fifo by design. Upon high load, RxD will be
1a348ccc
AG		 1008 * filled and packets will be dropped by nic without getting into host or
1009 * cousing interrupt. Anyway, in that condition, host has no chance to proccess
1010 * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
1011 */
1012
1013/* TBD: ensure proper packet size */
1014
1015static int bdx_rx_init(struct bdx_priv *priv)
1016{
1017 ENTER;
ddfce6bb 1018
1a348ccc
AG		 1019 if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size,
1020 regRXD_CFG0_0, regRXD_CFG1_0,
1021 regRXD_RPTR_0, regRXD_WPTR_0))
1022 goto err_mem;
1023 if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size,
1024 regRXF_CFG0_0, regRXF_CFG1_0,
1025 regRXF_RPTR_0, regRXF_WPTR_0))
1026 goto err_mem;
1027 if (!
1028 (priv->rxdb =
1029 bdx_rxdb_create(priv->rxf_fifo0.m.memsz /
1030 sizeof(struct rxf_desc))))
1031 goto err_mem;
1032
1033 priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN;
1034 return 0;
1035
1036err_mem:
1037 ERR("%s: %s: Rx init failed\n", BDX_DRV_NAME, priv->ndev->name);
1038 return -ENOMEM;
1039}
1040
1041/* bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo
1042 * @priv - NIC private structure
1043 * @f - RXF fifo
1044 */
1045static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1046{
1047 struct rx_map *dm;
1048 struct rxdb *db = priv->rxdb;
1049 u16 i;
1050
1051 ENTER;
1052 DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db),
1053 db->nelem - bdx_rxdb_available(db));
1054 while (bdx_rxdb_available(db) > 0) {
1055 i = bdx_rxdb_alloc_elem(db);
1056 dm = bdx_rxdb_addr_elem(db, i);
1057 dm->dma = 0;
1058 }
1059 for (i = 0; i < db->nelem; i++) {
1060 dm = bdx_rxdb_addr_elem(db, i);
1061 if (dm->dma) {
1062 pci_unmap_single(priv->pdev,
1063 dm->dma, f->m.pktsz,
1064 PCI_DMA_FROMDEVICE);
1065 dev_kfree_skb(dm->skb);
1066 }
1067 }
1068}
1069
1070/* bdx_rx_free - release all Rx resources
1071 * @priv - NIC private structure
1072 * It assumes that Rx is desabled in HW
1073 */
1074static void bdx_rx_free(struct bdx_priv *priv)
1075{
1076 ENTER;
1077 if (priv->rxdb) {
1078 bdx_rx_free_skbs(priv, &priv->rxf_fifo0);
1079 bdx_rxdb_destroy(priv->rxdb);
1080 priv->rxdb = NULL;
1081 }
1082 bdx_fifo_free(priv, &priv->rxf_fifo0.m);
1083 bdx_fifo_free(priv, &priv->rxd_fifo0.m);
1084
1085 RET();
1086}
1087
1088/*************************************************************************
1089 * Rx Engine *
1090 *************************************************************************/
1091
1092/* bdx_rx_alloc_skbs - fill rxf fifo with new skbs
1093 * @priv - nic's private structure
1094 * @f - RXF fifo that needs skbs
1095 * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo.
1096 * skb's virtual and physical addresses are stored in skb db.
1097 * To calculate free space, func uses cached values of RPTR and WPTR
1098 * When needed, it also updates RPTR and WPTR.
1099 */
1100
1101/* TBD: do not update WPTR if no desc were written */
1102
1103static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1104{
1105 struct sk_buff *skb;
1106 struct rxf_desc *rxfd;
1107 struct rx_map *dm;
1108 int dno, delta, idx;
1109 struct rxdb *db = priv->rxdb;
1110
1111 ENTER;
1112 dno = bdx_rxdb_available(db) - 1;
1113 while (dno > 0) {
1114 if (!(skb = dev_alloc_skb(f->m.pktsz + NET_IP_ALIGN))) {
1115 ERR("NO MEM: dev_alloc_skb failed\n");
1116 break;
1117 }
1118 skb->dev = priv->ndev;
1119 skb_reserve(skb, NET_IP_ALIGN);
1120
1121 idx = bdx_rxdb_alloc_elem(db);
1122 dm = bdx_rxdb_addr_elem(db, idx);
1123 dm->dma = pci_map_single(priv->pdev,
1124 skb->data, f->m.pktsz,
1125 PCI_DMA_FROMDEVICE);
1126 dm->skb = skb;
1127 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1128 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1129 rxfd->va_lo = idx;
1130 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1131 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1132 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1133 print_rxfd(rxfd);
1134
1135 f->m.wptr += sizeof(struct rxf_desc);
1136 delta = f->m.wptr - f->m.memsz;
1137 if (unlikely(delta >= 0)) {
1138 f->m.wptr = delta;
1139 if (delta > 0) {
1140 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1141 DBG("wrapped descriptor\n");
1142 }
1143 }
1144 dno--;
1145 }
1146 /*TBD: to do - delayed rxf wptr like in txd */
1147 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1148 RET();
1149}
1150
1151static inline void
1152NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan,
1153 struct sk_buff *skb)
1154{
1155 ENTER;
1156 DBG("rxdd->flags.bits.vtag=%d vlgrp=%p\n", GET_RXD_VTAG(rxd_val1),
1157 priv->vlgrp);
1158 if (priv->vlgrp && GET_RXD_VTAG(rxd_val1)) {
1159 DBG("%s: vlan rcv vlan '%x' vtag '%x', device name '%s'\n",
1160 priv->ndev->name,
1161 GET_RXD_VLAN_ID(rxd_vlan),
1162 GET_RXD_VTAG(rxd_val1),
1163 vlan_group_get_device(priv->vlgrp,
1164 GET_RXD_VLAN_ID(rxd_vlan))->name);
1165 /* NAPI variant of receive functions */
1166 vlan_hwaccel_receive_skb(skb, priv->vlgrp,
38b22195 1167 GET_RXD_VLAN_TCI(rxd_vlan));
1a348ccc
AG		 1168 } else {
1169 netif_receive_skb(skb);
1170 }
1171}
1172
1173static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd)
1174{
1175 struct rxf_desc *rxfd;
1176 struct rx_map *dm;
1177 struct rxf_fifo *f;
1178 struct rxdb *db;
1179 struct sk_buff *skb;
1180 int delta;
1181
1182 ENTER;
1183 DBG("priv=%p rxdd=%p\n", priv, rxdd);
1184 f = &priv->rxf_fifo0;
1185 db = priv->rxdb;
1186 DBG("db=%p f=%p\n", db, f);
1187 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1188 DBG("dm=%p\n", dm);
1189 skb = dm->skb;
1190 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1191 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1192 rxfd->va_lo = rxdd->va_lo;
1193 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1194 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1195 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1196 print_rxfd(rxfd);
1197
1198 f->m.wptr += sizeof(struct rxf_desc);
1199 delta = f->m.wptr - f->m.memsz;
1200 if (unlikely(delta >= 0)) {
1201 f->m.wptr = delta;
1202 if (delta > 0) {
1203 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1204 DBG("wrapped descriptor\n");
1205 }
1206 }
1207 RET();
1208}
1209
1210/* bdx_rx_receive - recieves full packets from RXD fifo and pass them to OS
1211 * NOTE: a special treatment is given to non-continous descriptors
1212 * that start near the end, wraps around and continue at the beginning. a second
1213 * part is copied right after the first, and then descriptor is interpreted as
1214 * normal. fifo has an extra space to allow such operations
1215 * @priv - nic's private structure
1216 * @f - RXF fifo that needs skbs
1217 */
1218
1219/* TBD: replace memcpy func call by explicite inline asm */
1220
1221static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget)
1222{
1223 struct sk_buff *skb, *skb2;
1224 struct rxd_desc *rxdd;
1225 struct rx_map *dm;
1226 struct rxf_fifo *rxf_fifo;
1227 int tmp_len, size;
1228 int done = 0;
1229 int max_done = BDX_MAX_RX_DONE;
1230 struct rxdb *db = NULL;
1231 /* Unmarshalled descriptor - copy of descriptor in host order */
1232 u32 rxd_val1;
1233 u16 len;
1234 u16 rxd_vlan;
1235
1236 ENTER;
1237 max_done = budget;
1238
1a348ccc
AG		 1239 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
1240
1241 size = f->m.wptr - f->m.rptr;
1242 if (size < 0)
1243 size = f->m.memsz + size; /* size is negative :-) */
1244
1245 while (size > 0) {
1246
1247 rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr);
1248 rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1);
1249
1250 len = CPU_CHIP_SWAP16(rxdd->len);
1251
1252 rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan);
1253
1254 print_rxdd(rxdd, rxd_val1, len, rxd_vlan);
1255
1256 tmp_len = GET_RXD_BC(rxd_val1) << 3;
1257 BDX_ASSERT(tmp_len <= 0);
1258 size -= tmp_len;
1259 if (size < 0) /* test for partially arrived descriptor */
1260 break;
1261
1262 f->m.rptr += tmp_len;
1263
1264 tmp_len = f->m.rptr - f->m.memsz;
1265 if (unlikely(tmp_len >= 0)) {
1266 f->m.rptr = tmp_len;
1267 if (tmp_len > 0) {
1268 DBG("wrapped desc rptr=%d tmp_len=%d\n",
1269 f->m.rptr, tmp_len);
1270 memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len);
1271 }
1272 }
1273
1274 if (unlikely(GET_RXD_ERR(rxd_val1))) {
1275 DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1));
1276 priv->net_stats.rx_errors++;
1277 bdx_recycle_skb(priv, rxdd);
1278 continue;
1279 }
1280
1281 rxf_fifo = &priv->rxf_fifo0;
1282 db = priv->rxdb;
1283 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1284 skb = dm->skb;
1285
1286 if (len < BDX_COPYBREAK &&
1287 (skb2 = dev_alloc_skb(len + NET_IP_ALIGN))) {
1288 skb_reserve(skb2, NET_IP_ALIGN);
1289 /*skb_put(skb2, len); */
1290 pci_dma_sync_single_for_cpu(priv->pdev,
1291 dm->dma, rxf_fifo->m.pktsz,
1292 PCI_DMA_FROMDEVICE);
1293 memcpy(skb2->data, skb->data, len);
1294 bdx_recycle_skb(priv, rxdd);
1295 skb = skb2;
1296 } else {
1297 pci_unmap_single(priv->pdev,
1298 dm->dma, rxf_fifo->m.pktsz,
1299 PCI_DMA_FROMDEVICE);
1300 bdx_rxdb_free_elem(db, rxdd->va_lo);
1301 }
1302
1303 priv->net_stats.rx_bytes += len;
1304
1305 skb_put(skb, len);
1306 skb->dev = priv->ndev;
1307 skb->ip_summed = CHECKSUM_UNNECESSARY;
1308 skb->protocol = eth_type_trans(skb, priv->ndev);
1309
1310 /* Non-IP packets aren't checksum-offloaded */
1311 if (GET_RXD_PKT_ID(rxd_val1) == 0)
1312 skb->ip_summed = CHECKSUM_NONE;
1313
1314 NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb);
1315
1316 if (++done >= max_done)
1317 break;
1318 }
1319
1320 priv->net_stats.rx_packets += done;
1321
1322 /* FIXME: do smth to minimize pci accesses */
1323 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1324
1325 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
1326
1327 RET(done);
1328}
1329
1330/*************************************************************************
1331 * Debug / Temprorary Code *
1332 *************************************************************************/
1333static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
1334 u16 rxd_vlan)
1335{
1336 DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d "
1337 "pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d "
1338 "va_lo %d va_hi %d\n",
1339 GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1),
1340 GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1),
1341 GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1),
1342 GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan),
1343 GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo,
1344 rxdd->va_hi);
1345}
1346
1347static void print_rxfd(struct rxf_desc *rxfd)
1348{
1349 DBG("=== RxF desc CHIP ORDER/ENDIANESS =============\n"
1350 "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
1351 rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len);
1352}
1353
1354/*
1355 * TX HW/SW interaction overview
1356 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1357 * There are 2 types of TX communication channels betwean driver and NIC.
1358 * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets
1359 * 2) TX Data Fifo - TXD - holds descriptors of full buffers.
1360 *
1361 * Currently NIC supports TSO, checksuming and gather DMA
1362 * UFO and IP fragmentation is on the way
1363 *
1364 * RX SW Data Structures
1365 * ~~~~~~~~~~~~~~~~~~~~~
1366 * txdb - used to keep track of all skbs owned by SW and their dma addresses.
1367 * For TX case, ownership lasts from geting packet via hard_xmit and until HW
1368 * acknowledges sent by TXF descriptors.
1369 * Implemented as cyclic buffer.
1370 * fifo - keeps info about fifo's size and location, relevant HW registers,
1371 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
1372 * Implemented as simple struct.
1373 *
1374 * TX SW Execution Flow
1375 * ~~~~~~~~~~~~~~~~~~~~
1376 * OS calls driver's hard_xmit method with packet to sent.
1377 * Driver creates DMA mappings, builds TXD descriptors and kicks HW
1378 * by updating TXD WPTR.
1379 * When packet is sent, HW write us TXF descriptor and SW frees original skb.
1380 * To prevent TXD fifo overflow without reading HW registers every time,
1381 * SW deploys "tx level" technique.
1382 * Upon strart up, tx level is initialized to TXD fifo length.
1383 * For every sent packet, SW gets its TXD descriptor sizei
1384 * (from precalculated array) and substructs it from tx level.
1385 * The size is also stored in txdb. When TXF ack arrives, SW fetch size of
1386 * original TXD descriptor from txdb and adds it to tx level.
1387 * When Tx level drops under some predefined treshhold, the driver
1388 * stops the TX queue. When TX level rises above that level,
1389 * the tx queue is enabled again.
1390 *
1391 * This technique avoids eccessive reading of RPTR and WPTR registers.
1392 * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput.
1393 */
1394
1395/*************************************************************************
1396 * Tx DB *
1397 *************************************************************************/
1398static inline int bdx_tx_db_size(struct txdb *db)
1399{
1400 int taken = db->wptr - db->rptr;
1401 if (taken < 0)
1402 taken = db->size + 1 + taken; /* (size + 1) equals memsz */
1403
1404 return db->size - taken;
1405}
1406
1407/* __bdx_tx_ptr_next - helper function, increment read/write pointer + wrap
1408 * @d - tx data base
1409 * @ptr - read or write pointer
1410 */
1411static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr)
1412{
1413 BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */
1414
1415 BDX_ASSERT(*pptr != db->rptr && /* expect either read */
1416 *pptr != db->wptr); /* or write pointer */
1417
1418 BDX_ASSERT(*pptr < db->start || /* pointer has to be */
1419 *pptr >= db->end); /* in range */
1420
1421 ++*pptr;
1422 if (unlikely(*pptr == db->end))
1423 *pptr = db->start;
1424}
1425
1426/* bdx_tx_db_inc_rptr - increment read pointer
1427 * @d - tx data base
1428 */
1429static inline void bdx_tx_db_inc_rptr(struct txdb *db)
1430{
1431 BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */
1432 __bdx_tx_db_ptr_next(db, &db->rptr);
1433}
1434
1435/* bdx_tx_db_inc_rptr - increment write pointer
1436 * @d - tx data base
1437 */
1438static inline void bdx_tx_db_inc_wptr(struct txdb *db)
1439{
1440 __bdx_tx_db_ptr_next(db, &db->wptr);
1441 BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as
1442 a result of write */
1443}
1444
1445/* bdx_tx_db_init - creates and initializes tx db
1446 * @d - tx data base
1447 * @sz_type - size of tx fifo
1448 * Returns 0 on success, error code otherwise
1449 */
1450static int bdx_tx_db_init(struct txdb *d, int sz_type)
1451{
1452 int memsz = FIFO_SIZE * (1 << (sz_type + 1));
1453
1454 d->start = vmalloc(memsz);
1455 if (!d->start)
1456 return -ENOMEM;
1457
1458 /*
1459 * In order to differentiate between db is empty and db is full
1460 * states at least one element should always be empty in order to
1461 * avoid rptr == wptr which means db is empty
1462 */
1463 d->size = memsz / sizeof(struct tx_map) - 1;
1464 d->end = d->start + d->size + 1; /* just after last element */
1465
1466 /* all dbs are created equally empty */
1467 d->rptr = d->start;
1468 d->wptr = d->start;
1469
1470 return 0;
1471}
1472
1473/* bdx_tx_db_close - closes tx db and frees all memory
1474 * @d - tx data base
1475 */
1476static void bdx_tx_db_close(struct txdb *d)
1477{
1478 BDX_ASSERT(d == NULL);
1479
1480 if (d->start) {
1481 vfree(d->start);
1482 d->start = NULL;
1483 }
1484}
1485
1486/*************************************************************************
1487 * Tx Engine *
1488 *************************************************************************/
1489
1490/* sizes of tx desc (including padding if needed) as function
1491 * of skb's frag number */
1492static struct {
1493 u16 bytes;
1494 u16 qwords; /* qword = 64 bit */
1495} txd_sizes[MAX_SKB_FRAGS + 1];
1496
1497/* txdb_map_skb - creates and stores dma mappings for skb's data blocks
1498 * @priv - NIC private structure
1499 * @skb - socket buffer to map
1500 *
1501 * It makes dma mappings for skb's data blocks and writes them to PBL of
1502 * new tx descriptor. It also stores them in the tx db, so they could be
1503 * unmaped after data was sent. It is reponsibility of a caller to make
1504 * sure that there is enough space in the tx db. Last element holds pointer
1505 * to skb itself and marked with zero length
1506 */
1507static inline void
1508bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb,
1509 struct txd_desc *txdd)
1510{
1511 struct txdb *db = &priv->txdb;
1512 struct pbl *pbl = &txdd->pbl[0];
1513 int nr_frags = skb_shinfo(skb)->nr_frags;
1514 int i;
1515
1516 db->wptr->len = skb->len - skb->data_len;
1517 db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data,
1518 db->wptr->len, PCI_DMA_TODEVICE);
1519 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1520 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1521 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1522 DBG("=== pbl len: 0x%x ================\n", pbl->len);
1523 DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo);
1524 DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi);
1525 bdx_tx_db_inc_wptr(db);
1526
1527 for (i = 0; i < nr_frags; i++) {
1528 struct skb_frag_struct *frag;
1529
1530 frag = &skb_shinfo(skb)->frags[i];
1531 db->wptr->len = frag->size;
1532 db->wptr->addr.dma =
1533 pci_map_page(priv->pdev, frag->page, frag->page_offset,
1534 frag->size, PCI_DMA_TODEVICE);
1535
1536 pbl++;
1537 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1538 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1539 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1540 bdx_tx_db_inc_wptr(db);
1541 }
1542
1543 /* add skb clean up info. */
1544 db->wptr->len = -txd_sizes[nr_frags].bytes;
1545 db->wptr->addr.skb = skb;
1546 bdx_tx_db_inc_wptr(db);
1547}
1548
1549/* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags
1550 * number of frags is used as index to fetch correct descriptors size,
1551 * instead of calculating it each time */
1552static void __init init_txd_sizes(void)
1553{
1554 int i, lwords;
1555
1556 /* 7 - is number of lwords in txd with one phys buffer
1557 * 3 - is number of lwords used for every additional phys buffer */
1558 for (i = 0; i < MAX_SKB_FRAGS + 1; i++) {
1559 lwords = 7 + (i * 3);
1560 if (lwords & 1)
1561 lwords++; /* pad it with 1 lword */
1562 txd_sizes[i].qwords = lwords >> 1;
1563 txd_sizes[i].bytes = lwords << 2;
1564 }
1565}
1566
1567/* bdx_tx_init - initialize all Tx related stuff.
1568 * Namely, TXD and TXF fifos, database etc */
1569static int bdx_tx_init(struct bdx_priv *priv)
1570{
1571 if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size,
1572 regTXD_CFG0_0,
1573 regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0))
1574 goto err_mem;
1575 if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size,
1576 regTXF_CFG0_0,
1577 regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0))
1578 goto err_mem;
1579
1580 /* The TX db has to keep mappings for all packets sent (on TxD)
1581 * and not yet reclaimed (on TxF) */
1582 if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size)))
1583 goto err_mem;
1584
1585 priv->tx_level = BDX_MAX_TX_LEVEL;
1586#ifdef BDX_DELAY_WPTR
1587 priv->tx_update_mark = priv->tx_level - 1024;
1588#endif
1589 return 0;
1590
1591err_mem:
1592 ERR("tehuti: %s: Tx init failed\n", priv->ndev->name);
1593 return -ENOMEM;
1594}
1595
1596/*
1597 * bdx_tx_space - calculates avalable space in TX fifo
1598 * @priv - NIC private structure
1599 * Returns avaliable space in TX fifo in bytes
1600 */
1601static inline int bdx_tx_space(struct bdx_priv *priv)
1602{
1603 struct txd_fifo *f = &priv->txd_fifo0;
1604 int fsize;
1605
1606 f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR;
1607 fsize = f->m.rptr - f->m.wptr;
1608 if (fsize <= 0)
1609 fsize = f->m.memsz + fsize;
1610 return (fsize);
1611}
1612
1613/* bdx_tx_transmit - send packet to NIC
1614 * @skb - packet to send
1615 * ndev - network device assigned to NIC
1616 * Return codes:
1617 * o NETDEV_TX_OK everything ok.
1618 * o NETDEV_TX_BUSY Cannot transmit packet, try later
1619 * Usually a bug, means queue start/stop flow control is broken in
1620 * the driver. Note: the driver must NOT put the skb in its DMA ring.
1621 * o NETDEV_TX_LOCKED Locking failed, please retry quickly.
1622 */
1623static int bdx_tx_transmit(struct sk_buff *skb, struct net_device *ndev)
1624{
8f15ea42 1625 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 1626 struct txd_fifo *f = &priv->txd_fifo0;
1627 int txd_checksum = 7; /* full checksum */
1628 int txd_lgsnd = 0;
1629 int txd_vlan_id = 0;
1630 int txd_vtag = 0;
1631 int txd_mss = 0;
1632
1633 int nr_frags = skb_shinfo(skb)->nr_frags;
1634 struct txd_desc *txdd;
1635 int len;
1636 unsigned long flags;
1637
1638 ENTER;
1639 local_irq_save(flags);
1640 if (!spin_trylock(&priv->tx_lock)) {
1641 local_irq_restore(flags);
1642 DBG("%s[%s]: TX locked, returning NETDEV_TX_LOCKED\n",
1643 BDX_DRV_NAME, ndev->name);
1644 return NETDEV_TX_LOCKED;
1645 }
1646
1647 /* build tx descriptor */
1648 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */
1649 txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
1650 if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL))
1651 txd_checksum = 0;
1652
1653 if (skb_shinfo(skb)->gso_size) {
1654 txd_mss = skb_shinfo(skb)->gso_size;
1655 txd_lgsnd = 1;
1656 DBG("skb %p skb len %d gso size = %d\n", skb, skb->len,
1657 txd_mss);
1658 }
1659
1660 if (vlan_tx_tag_present(skb)) {
1661 /*Cut VLAN ID to 12 bits */
1662 txd_vlan_id = vlan_tx_tag_get(skb) & BITS_MASK(12);
1663 txd_vtag = 1;
1664 }
1665
1666 txdd->length = CPU_CHIP_SWAP16(skb->len);
1667 txdd->mss = CPU_CHIP_SWAP16(txd_mss);
1668 txdd->txd_val1 =
1669 CPU_CHIP_SWAP32(TXD_W1_VAL
1670 (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag,
1671 txd_lgsnd, txd_vlan_id));
1672 DBG("=== TxD desc =====================\n");
1673 DBG("=== w1: 0x%x ================\n", txdd->txd_val1);
1674 DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length);
1675
1676 bdx_tx_map_skb(priv, skb, txdd);
1677
1678 /* increment TXD write pointer. In case of
1679 fifo wrapping copy reminder of the descriptor
1680 to the beginning */
1681 f->m.wptr += txd_sizes[nr_frags].bytes;
1682 len = f->m.wptr - f->m.memsz;
1683 if (unlikely(len >= 0)) {
1684 f->m.wptr = len;
1685 if (len > 0) {
1686 BDX_ASSERT(len > f->m.memsz);
1687 memcpy(f->m.va, f->m.va + f->m.memsz, len);
1688 }
1689 }
1690 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */
1691
1692 priv->tx_level -= txd_sizes[nr_frags].bytes;
1693 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1694#ifdef BDX_DELAY_WPTR
1695 if (priv->tx_level > priv->tx_update_mark) {
1696 /* Force memory writes to complete before letting h/w
1697 know there are new descriptors to fetch.
1698 (might be needed on platforms like IA64)
1699 wmb(); */
1700 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1701 } else {
1702 if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) {
1703 priv->tx_noupd = 0;
1704 WRITE_REG(priv, f->m.reg_WPTR,
1705 f->m.wptr & TXF_WPTR_WR_PTR);
1706 }
1707 }
1708#else
1709 /* Force memory writes to complete before letting h/w
1710 know there are new descriptors to fetch.
1711 (might be needed on platforms like IA64)
1712 wmb(); */
1713 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1714
1715#endif
1716 ndev->trans_start = jiffies;
1717
1718 priv->net_stats.tx_packets++;
1719 priv->net_stats.tx_bytes += skb->len;
1720
1721 if (priv->tx_level < BDX_MIN_TX_LEVEL) {
1722 DBG("%s: %s: TX Q STOP level %d\n",
1723 BDX_DRV_NAME, ndev->name, priv->tx_level);
1724 netif_stop_queue(ndev);
1725 }
1726
1727 spin_unlock_irqrestore(&priv->tx_lock, flags);
1728 return NETDEV_TX_OK;
1729}
1730
1731/* bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ.
1732 * @priv - bdx adapter
1733 * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS
1734 * that those packets were sent
1735 */
1736static void bdx_tx_cleanup(struct bdx_priv *priv)
1737{
1738 struct txf_fifo *f = &priv->txf_fifo0;
1739 struct txdb *db = &priv->txdb;
1740 int tx_level = 0;
1741
1742 ENTER;
1743 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
1744 BDX_ASSERT(f->m.rptr >= f->m.memsz); /* started with valid rptr */
1745
1746 while (f->m.wptr != f->m.rptr) {
1747 f->m.rptr += BDX_TXF_DESC_SZ;
1748 f->m.rptr &= f->m.size_mask;
1749
1750 /* unmap all the fragments */
1751 /* first has to come tx_maps containing dma */
1752 BDX_ASSERT(db->rptr->len == 0);
1753 do {
1754 BDX_ASSERT(db->rptr->addr.dma == 0);
1755 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1756 db->rptr->len, PCI_DMA_TODEVICE);
1757 bdx_tx_db_inc_rptr(db);
1758 } while (db->rptr->len > 0);
1759 tx_level -= db->rptr->len; /* '-' koz len is negative */
1760
1761 /* now should come skb pointer - free it */
1a348ccc
AG		 1762 dev_kfree_skb_irq(db->rptr->addr.skb);
1763 bdx_tx_db_inc_rptr(db);
1764 }
1765
1766 /* let h/w know which TXF descriptors were cleaned */
1767 BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
1768 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1769
1770 /* We reclaimed resources, so in case the Q is stopped by xmit callback,
1771 * we resume the transmition and use tx_lock to synchronize with xmit.*/
1772 spin_lock(&priv->tx_lock);
1773 priv->tx_level += tx_level;
1774 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1775#ifdef BDX_DELAY_WPTR
1776 if (priv->tx_noupd) {
1777 priv->tx_noupd = 0;
1778 WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,
1779 priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
1780 }
1781#endif
1782
1783 if (unlikely(netif_queue_stopped(priv->ndev)
1784 && netif_carrier_ok(priv->ndev)
1785 && (priv->tx_level >= BDX_MIN_TX_LEVEL))) {
1786 DBG("%s: %s: TX Q WAKE level %d\n",
1787 BDX_DRV_NAME, priv->ndev->name, priv->tx_level);
1788 netif_wake_queue(priv->ndev);
1789 }
1790 spin_unlock(&priv->tx_lock);
1791}
1792
1793/* bdx_tx_free_skbs - frees all skbs from TXD fifo.
1794 * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod
1795 */
1796static void bdx_tx_free_skbs(struct bdx_priv *priv)
1797{
1798 struct txdb *db = &priv->txdb;
1799
1800 ENTER;
1801 while (db->rptr != db->wptr) {
1802 if (likely(db->rptr->len))
1803 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1804 db->rptr->len, PCI_DMA_TODEVICE);
1805 else
1806 dev_kfree_skb(db->rptr->addr.skb);
1807 bdx_tx_db_inc_rptr(db);
1808 }
1809 RET();
1810}
1811
1812/* bdx_tx_free - frees all Tx resources */
1813static void bdx_tx_free(struct bdx_priv *priv)
1814{
1815 ENTER;
1816 bdx_tx_free_skbs(priv);
1817 bdx_fifo_free(priv, &priv->txd_fifo0.m);
1818 bdx_fifo_free(priv, &priv->txf_fifo0.m);
1819 bdx_tx_db_close(&priv->txdb);
1820}
1821
1822/* bdx_tx_push_desc - push descriptor to TxD fifo
1823 * @priv - NIC private structure
1824 * @data - desc's data
1825 * @size - desc's size
1826 *
1827 * Pushes desc to TxD fifo and overlaps it if needed.
1828 * NOTE: this func does not check for available space. this is responsibility
025dfdaf 1829 * of the caller. Neither does it check that data size is smaller than
1a348ccc
AG		 1830 * fifo size.
1831 */
1832static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size)
1833{
1834 struct txd_fifo *f = &priv->txd_fifo0;
1835 int i = f->m.memsz - f->m.wptr;
1836
1837 if (size == 0)
1838 return;
1839
1840 if (i > size) {
1841 memcpy(f->m.va + f->m.wptr, data, size);
1842 f->m.wptr += size;
1843 } else {
1844 memcpy(f->m.va + f->m.wptr, data, i);
1845 f->m.wptr = size - i;
1846 memcpy(f->m.va, data + i, f->m.wptr);
1847 }
1848 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1849}
1850
1851/* bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way
1852 * @priv - NIC private structure
1853 * @data - desc's data
1854 * @size - desc's size
1855 *
1856 * NOTE: this func does check for available space and, if neccessary, waits for
1857 * NIC to read existing data before writing new one.
1858 */
1859static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size)
1860{
1861 int timer = 0;
1862 ENTER;
1863
1864 while (size > 0) {
1865 /* we substruct 8 because when fifo is full rptr == wptr
1866 which also means that fifo is empty, we can understand
1867 the difference, but could hw do the same ??? :) */
1868 int avail = bdx_tx_space(priv) - 8;
1869 if (avail <= 0) {
1870 if (timer++ > 300) { /* prevent endless loop */
1871 DBG("timeout while writing desc to TxD fifo\n");
1872 break;
1873 }
1874 udelay(50); /* give hw a chance to clean fifo */
1875 continue;
1876 }
1877 avail = MIN(avail, size);
1878 DBG("about to push %d bytes starting %p size %d\n", avail,
1879 data, size);
1880 bdx_tx_push_desc(priv, data, avail);
1881 size -= avail;
1882 data += avail;
1883 }
1884 RET();
1885}
1886
2f30b1f6
SH		 1887static const struct net_device_ops bdx_netdev_ops = {
1888 .ndo_open = bdx_open,
1889 .ndo_stop = bdx_close,
1890 .ndo_start_xmit = bdx_tx_transmit,
1891 .ndo_validate_addr = eth_validate_addr,
1892 .ndo_do_ioctl = bdx_ioctl,
1893 .ndo_set_multicast_list = bdx_setmulti,
1894 .ndo_get_stats = bdx_get_stats,
1895 .ndo_change_mtu = bdx_change_mtu,
1896 .ndo_set_mac_address = bdx_set_mac,
1897 .ndo_vlan_rx_register = bdx_vlan_rx_register,
1898 .ndo_vlan_rx_add_vid = bdx_vlan_rx_add_vid,
1899 .ndo_vlan_rx_kill_vid = bdx_vlan_rx_kill_vid,
1900};
1901
1a348ccc
AG		 1902/**
1903 * bdx_probe - Device Initialization Routine
1904 * @pdev: PCI device information struct
1905 * @ent: entry in bdx_pci_tbl
1906 *
1907 * Returns 0 on success, negative on failure
1908 *
1909 * bdx_probe initializes an adapter identified by a pci_dev structure.
1910 * The OS initialization, configuring of the adapter private structure,
1911 * and a hardware reset occur.
1912 *
1913 * functions and their order used as explained in
1914 * /usr/src/linux/Documentation/DMA-{API,mapping}.txt
1915 *
1916 */
1917
1918/* TBD: netif_msg should be checked and implemented. I disable it for now */
1919static int __devinit
1920bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1921{
1922 struct net_device *ndev;
1923 struct bdx_priv *priv;
1924 int err, pci_using_dac, port;
1925 unsigned long pciaddr;
1926 u32 regionSize;
1927 struct pci_nic *nic;
1928
1929 ENTER;
1930
1931 nic = vmalloc(sizeof(*nic));
1932 if (!nic)
1933 RET(-ENOMEM);
1934
1935 /************** pci *****************/
1936 if ((err = pci_enable_device(pdev))) /* it trigers interrupt, dunno why. */
bc2618f7 1937 goto err_pci; /* it's not a problem though */
1a348ccc
AG		 1938
1939 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
1940 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
1941 pci_using_dac = 1;
1942 } else {
1943 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) ||
1944 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
1945 printk(KERN_ERR "tehuti: No usable DMA configuration"
1946 ", aborting\n");
1947 goto err_dma;
1948 }
1949 pci_using_dac = 0;
1950 }
1951
1952 if ((err = pci_request_regions(pdev, BDX_DRV_NAME)))
1953 goto err_dma;
1954
1955 pci_set_master(pdev);
1956
1957 pciaddr = pci_resource_start(pdev, 0);
1958 if (!pciaddr) {
1959 err = -EIO;
1960 ERR("tehuti: no MMIO resource\n");
1961 goto err_out_res;
1962 }
1963 if ((regionSize = pci_resource_len(pdev, 0)) < BDX_REGS_SIZE) {
1964 err = -EIO;
1965 ERR("tehuti: MMIO resource (%x) too small\n", regionSize);
1966 goto err_out_res;
1967 }
1968
1969 nic->regs = ioremap(pciaddr, regionSize);
1970 if (!nic->regs) {
1971 err = -EIO;
1972 ERR("tehuti: ioremap failed\n");
1973 goto err_out_res;
1974 }
1975
1976 if (pdev->irq < 2) {
1977 err = -EIO;
1978 ERR("tehuti: invalid irq (%d)\n", pdev->irq);
1979 goto err_out_iomap;
1980 }
1981 pci_set_drvdata(pdev, nic);
1982
1983 if (pdev->device == 0x3014)
1984 nic->port_num = 2;
1985 else
1986 nic->port_num = 1;
1987
1988 print_hw_id(pdev);
1989
1990 bdx_hw_reset_direct(nic->regs);
1991
1992 nic->irq_type = IRQ_INTX;
1993#ifdef BDX_MSI
1994 if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) {
1995 if ((err = pci_enable_msi(pdev)))
1996 ERR("Tehuti: Can't eneble msi. error is %d\n", err);
1997 else
1998 nic->irq_type = IRQ_MSI;
1999 } else
2000 DBG("HW does not support MSI\n");
2001#endif
2002
2003 /************** netdev **************/
2004 for (port = 0; port < nic->port_num; port++) {
2005 if (!(ndev = alloc_etherdev(sizeof(struct bdx_priv)))) {
2006 err = -ENOMEM;
2007 printk(KERN_ERR "tehuti: alloc_etherdev failed\n");
2008 goto err_out_iomap;
2009 }
2010
2f30b1f6 2011 ndev->netdev_ops = &bdx_netdev_ops;
1a348ccc 2012 ndev->tx_queue_len = BDX_NDEV_TXQ_LEN;
1a348ccc
AG		 2013
2014 bdx_ethtool_ops(ndev); /* ethtool interface */
2015
2016 /* these fields are used for info purposes only
2017 * so we can have them same for all ports of the board */
2018 ndev->if_port = port;
2019 ndev->base_addr = pciaddr;
2020 ndev->mem_start = pciaddr;
2021 ndev->mem_end = pciaddr + regionSize;
2022 ndev->irq = pdev->irq;
2023 ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO
2024 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
2025 NETIF_F_HW_VLAN_FILTER
2026 /*| NETIF_F_FRAGLIST */
2027 ;
2028
2029 if (pci_using_dac)
2030 ndev->features |= NETIF_F_HIGHDMA;
2031
2032 /************** priv ****************/
8f15ea42 2033 priv = nic->priv[port] = netdev_priv(ndev);
1a348ccc
AG		 2034
2035 memset(priv, 0, sizeof(struct bdx_priv));
2036 priv->pBdxRegs = nic->regs + port * 0x8000;
2037 priv->port = port;
2038 priv->pdev = pdev;
2039 priv->ndev = ndev;
2040 priv->nic = nic;
2041 priv->msg_enable = BDX_DEF_MSG_ENABLE;
2042
2043 netif_napi_add(ndev, &priv->napi, bdx_poll, 64);
2044
2045 if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) {
2046 DBG("HW statistics not supported\n");
2047 priv->stats_flag = 0;
2048 } else {
2049 priv->stats_flag = 1;
2050 }
2051
2052 /* Initialize fifo sizes. */
2053 priv->txd_size = 2;
2054 priv->txf_size = 2;
2055 priv->rxd_size = 2;
2056 priv->rxf_size = 3;
2057
2058 /* Initialize the initial coalescing registers. */
2059 priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12);
2060 priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12);
2061
2062 /* ndev->xmit_lock spinlock is not used.
2063 * Private priv->tx_lock is used for synchronization
2064 * between transmit and TX irq cleanup. In addition
2065 * set multicast list callback has to use priv->tx_lock.
2066 */
2067#ifdef BDX_LLTX
2068 ndev->features |= NETIF_F_LLTX;
2069#endif
2070 spin_lock_init(&priv->tx_lock);
2071
2072 /*bdx_hw_reset(priv); */
2073 if (bdx_read_mac(priv)) {
2074 printk(KERN_ERR "tehuti: load MAC address failed\n");
2075 goto err_out_iomap;
2076 }
2077 SET_NETDEV_DEV(ndev, &pdev->dev);
2078 if ((err = register_netdev(ndev))) {
2079 printk(KERN_ERR "tehuti: register_netdev failed\n");
2080 goto err_out_free;
2081 }
2082 netif_carrier_off(ndev);
2083 netif_stop_queue(ndev);
2084
2085 print_eth_id(ndev);
2086 }
2087 RET(0);
2088
2089err_out_free:
2090 free_netdev(ndev);
2091err_out_iomap:
2092 iounmap(nic->regs);
2093err_out_res:
2094 pci_release_regions(pdev);
2095err_dma:
2096 pci_disable_device(pdev);
bc2618f7 2097err_pci:
1a348ccc
AG		 2098 vfree(nic);
2099
2100 RET(err);
2101}
2102
2103/****************** Ethtool interface *********************/
2104/* get strings for tests */
2105static const char
2106 bdx_test_names[][ETH_GSTRING_LEN] = {
2107 "No tests defined"
2108};
2109
2110/* get strings for statistics counters */
2111static const char
2112 bdx_stat_names[][ETH_GSTRING_LEN] = {
2113 "InUCast", /* 0x7200 */
2114 "InMCast", /* 0x7210 */
2115 "InBCast", /* 0x7220 */
2116 "InPkts", /* 0x7230 */
2117 "InErrors", /* 0x7240 */
2118 "InDropped", /* 0x7250 */
2119 "FrameTooLong", /* 0x7260 */
2120 "FrameSequenceErrors", /* 0x7270 */
2121 "InVLAN", /* 0x7280 */
2122 "InDroppedDFE", /* 0x7290 */
2123 "InDroppedIntFull", /* 0x72A0 */
2124 "InFrameAlignErrors", /* 0x72B0 */
2125
2126 /* 0x72C0-0x72E0 RSRV */
2127
2128 "OutUCast", /* 0x72F0 */
2129 "OutMCast", /* 0x7300 */
2130 "OutBCast", /* 0x7310 */
2131 "OutPkts", /* 0x7320 */
2132
2133 /* 0x7330-0x7360 RSRV */
2134
2135 "OutVLAN", /* 0x7370 */
2136 "InUCastOctects", /* 0x7380 */
2137 "OutUCastOctects", /* 0x7390 */
2138
2139 /* 0x73A0-0x73B0 RSRV */
2140
2141 "InBCastOctects", /* 0x73C0 */
2142 "OutBCastOctects", /* 0x73D0 */
2143 "InOctects", /* 0x73E0 */
2144 "OutOctects", /* 0x73F0 */
2145};
2146
2147/*
2148 * bdx_get_settings - get device-specific settings
2149 * @netdev
2150 * @ecmd
2151 */
2152static int bdx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
2153{
2154 u32 rdintcm;
2155 u32 tdintcm;
8f15ea42 2156 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2157
2158 rdintcm = priv->rdintcm;
2159 tdintcm = priv->tdintcm;
2160
2161 ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
2162 ecmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
2163 ecmd->speed = SPEED_10000;
2164 ecmd->duplex = DUPLEX_FULL;
2165 ecmd->port = PORT_FIBRE;
2166 ecmd->transceiver = XCVR_EXTERNAL; /* what does it mean? */
2167 ecmd->autoneg = AUTONEG_DISABLE;
2168
2169 /* PCK_TH measures in multiples of FIFO bytes
2170 We translate to packets */
2171 ecmd->maxtxpkt =
2172 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2173 ecmd->maxrxpkt =
2174 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2175
2176 return 0;
2177}
2178
2179/*
2180 * bdx_get_drvinfo - report driver information
2181 * @netdev
2182 * @drvinfo
2183 */
2184static void
2185bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
2186{
8f15ea42 2187 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc 2188
072ee3f9
RK		 2189 strlcat(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver));
2190 strlcat(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version));
2191 strlcat(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
2192 strlcat(drvinfo->bus_info, pci_name(priv->pdev),
1a348ccc
AG		 2193 sizeof(drvinfo->bus_info));
2194
4c3616cd 2195 drvinfo->n_stats = ((priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0);
1a348ccc
AG		 2196 drvinfo->testinfo_len = 0;
2197 drvinfo->regdump_len = 0;
2198 drvinfo->eedump_len = 0;
2199}
2200
2201/*
2202 * bdx_get_rx_csum - report whether receive checksums are turned on or off
2203 * @netdev
2204 */
2205static u32 bdx_get_rx_csum(struct net_device *netdev)
2206{
2207 return 1; /* always on */
2208}
2209
2210/*
2211 * bdx_get_tx_csum - report whether transmit checksums are turned on or off
2212 * @netdev
2213 */
2214static u32 bdx_get_tx_csum(struct net_device *netdev)
2215{
2216 return (netdev->features & NETIF_F_IP_CSUM) != 0;
2217}
2218
2219/*
2220 * bdx_get_coalesce - get interrupt coalescing parameters
2221 * @netdev
2222 * @ecoal
2223 */
2224static int
2225bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2226{
2227 u32 rdintcm;
2228 u32 tdintcm;
8f15ea42 2229 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2230
2231 rdintcm = priv->rdintcm;
2232 tdintcm = priv->tdintcm;
2233
2234 /* PCK_TH measures in multiples of FIFO bytes
2235 We translate to packets */
2236 ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT;
2237 ecoal->rx_max_coalesced_frames =
2238 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2239
2240 ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT;
2241 ecoal->tx_max_coalesced_frames =
2242 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2243
2244 /* adaptive parameters ignored */
2245 return 0;
2246}
2247
2248/*
2249 * bdx_set_coalesce - set interrupt coalescing parameters
2250 * @netdev
2251 * @ecoal
2252 */
2253static int
2254bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2255{
2256 u32 rdintcm;
2257 u32 tdintcm;
8f15ea42 2258 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2259 int rx_coal;
2260 int tx_coal;
2261 int rx_max_coal;
2262 int tx_max_coal;
2263
2264 /* Check for valid input */
2265 rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT;
2266 tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT;
2267 rx_max_coal = ecoal->rx_max_coalesced_frames;
2268 tx_max_coal = ecoal->tx_max_coalesced_frames;
2269
2270 /* Translate from packets to multiples of FIFO bytes */
2271 rx_max_coal =
2272 (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1)
2273 / PCK_TH_MULT);
2274 tx_max_coal =
2275 (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1)
2276 / PCK_TH_MULT);
2277
2278 if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF)
2279 || (rx_max_coal > 0xF) || (tx_max_coal > 0xF))
2280 return -EINVAL;
2281
2282 rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm),
2283 GET_RXF_TH(priv->rdintcm), rx_max_coal);
2284 tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0,
2285 tx_max_coal);
2286
2287 priv->rdintcm = rdintcm;
2288 priv->tdintcm = tdintcm;
2289
2290 WRITE_REG(priv, regRDINTCM0, rdintcm);
2291 WRITE_REG(priv, regTDINTCM0, tdintcm);
2292
2293 return 0;
2294}
2295
2296/* Convert RX fifo size to number of pending packets */
2297static inline int bdx_rx_fifo_size_to_packets(int rx_size)
2298{
2299 return ((FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc));
2300}
2301
2302/* Convert TX fifo size to number of pending packets */
2303static inline int bdx_tx_fifo_size_to_packets(int tx_size)
2304{
2305 return ((FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ);
2306}
2307
2308/*
2309 * bdx_get_ringparam - report ring sizes
2310 * @netdev
2311 * @ring
2312 */
2313static void
2314bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2315{
8f15ea42 2316 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2317
2318 /*max_pending - the maximum-sized FIFO we allow */
2319 ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3);
2320 ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3);
2321 ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size);
2322 ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size);
2323}
2324
2325/*
2326 * bdx_set_ringparam - set ring sizes
2327 * @netdev
2328 * @ring
2329 */
2330static int
2331bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2332{
8f15ea42 2333 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2334 int rx_size = 0;
2335 int tx_size = 0;
2336
2337 for (; rx_size < 4; rx_size++) {
2338 if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending)
2339 break;
2340 }
2341 if (rx_size == 4)
2342 rx_size = 3;
2343
2344 for (; tx_size < 4; tx_size++) {
2345 if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending)
2346 break;
2347 }
2348 if (tx_size == 4)
2349 tx_size = 3;
2350
2351 /*Is there anything to do? */
2352 if ((rx_size == priv->rxf_size)
2353 && (tx_size == priv->txd_size))
2354 return 0;
2355
2356 priv->rxf_size = rx_size;
2357 if (rx_size > 1)
2358 priv->rxd_size = rx_size - 1;
2359 else
2360 priv->rxd_size = rx_size;
2361
2362 priv->txf_size = priv->txd_size = tx_size;
2363
2364 if (netif_running(netdev)) {
2365 bdx_close(netdev);
2366 bdx_open(netdev);
2367 }
2368 return 0;
2369}
2370
2371/*
2372 * bdx_get_strings - return a set of strings that describe the requested objects
2373 * @netdev
2374 * @data
2375 */
2376static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2377{
2378 switch (stringset) {
2379 case ETH_SS_TEST:
2380 memcpy(data, *bdx_test_names, sizeof(bdx_test_names));
2381 break;
2382 case ETH_SS_STATS:
2383 memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names));
2384 break;
2385 }
2386}
2387
2388/*
2389 * bdx_get_stats_count - return number of 64bit statistics counters
2390 * @netdev
2391 */
2392static int bdx_get_stats_count(struct net_device *netdev)
2393{
8f15ea42 2394 struct bdx_priv *priv = netdev_priv(netdev);
4c3616cd 2395 BDX_ASSERT(ARRAY_SIZE(bdx_stat_names)
1a348ccc 2396 != sizeof(struct bdx_stats) / sizeof(u64));
4c3616cd 2397 return ((priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0);
1a348ccc
AG		 2398}
2399
2400/*
2401 * bdx_get_ethtool_stats - return device's hardware L2 statistics
2402 * @netdev
2403 * @stats
2404 * @data
2405 */
2406static void bdx_get_ethtool_stats(struct net_device *netdev,
2407 struct ethtool_stats *stats, u64 *data)
2408{
8f15ea42 2409 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2410
2411 if (priv->stats_flag) {
2412
2413 /* Update stats from HW */
2414 bdx_update_stats(priv);
2415
2416 /* Copy data to user buffer */
2417 memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats));
2418 }
2419}
2420
2421/*
2422 * bdx_ethtool_ops - ethtool interface implementation
2423 * @netdev
2424 */
2425static void bdx_ethtool_ops(struct net_device *netdev)
2426{
2427 static struct ethtool_ops bdx_ethtool_ops = {
2428 .get_settings = bdx_get_settings,
2429 .get_drvinfo = bdx_get_drvinfo,
2430 .get_link = ethtool_op_get_link,
2431 .get_coalesce = bdx_get_coalesce,
2432 .set_coalesce = bdx_set_coalesce,
2433 .get_ringparam = bdx_get_ringparam,
2434 .set_ringparam = bdx_set_ringparam,
2435 .get_rx_csum = bdx_get_rx_csum,
2436 .get_tx_csum = bdx_get_tx_csum,
2437 .get_sg = ethtool_op_get_sg,
2438 .get_tso = ethtool_op_get_tso,
2439 .get_strings = bdx_get_strings,
2440 .get_stats_count = bdx_get_stats_count,
2441 .get_ethtool_stats = bdx_get_ethtool_stats,
2442 };
2443
2444 SET_ETHTOOL_OPS(netdev, &bdx_ethtool_ops);
2445}
2446
2447/**
2448 * bdx_remove - Device Removal Routine
2449 * @pdev: PCI device information struct
2450 *
2451 * bdx_remove is called by the PCI subsystem to alert the driver
2452 * that it should release a PCI device. The could be caused by a
2453 * Hot-Plug event, or because the driver is going to be removed from
2454 * memory.
2455 **/
2456static void __devexit bdx_remove(struct pci_dev *pdev)
2457{
2458 struct pci_nic *nic = pci_get_drvdata(pdev);
2459 struct net_device *ndev;
2460 int port;
2461
2462 for (port = 0; port < nic->port_num; port++) {
2463 ndev = nic->priv[port]->ndev;
2464 unregister_netdev(ndev);
2465 free_netdev(ndev);
2466 }
2467
2468 /*bdx_hw_reset_direct(nic->regs); */
2469#ifdef BDX_MSI
2470 if (nic->irq_type == IRQ_MSI)
2471 pci_disable_msi(pdev);
2472#endif
2473
2474 iounmap(nic->regs);
2475 pci_release_regions(pdev);
2476 pci_disable_device(pdev);
2477 pci_set_drvdata(pdev, NULL);
2478 vfree(nic);
2479
2480 RET();
2481}
2482
2483static struct pci_driver bdx_pci_driver = {
2484 .name = BDX_DRV_NAME,
2485 .id_table = bdx_pci_tbl,
2486 .probe = bdx_probe,
2487 .remove = __devexit_p(bdx_remove),
2488};
2489
2490/*
2491 * print_driver_id - print parameters of the driver build
2492 */
2493static void __init print_driver_id(void)
2494{
2495 printk(KERN_INFO "%s: %s, %s\n", BDX_DRV_NAME, BDX_DRV_DESC,
2496 BDX_DRV_VERSION);
2497 printk(KERN_INFO "%s: Options: hw_csum %s\n", BDX_DRV_NAME,
2498 BDX_MSI_STRING);
2499}
2500
2501static int __init bdx_module_init(void)
2502{
2503 ENTER;
2504 bdx_firmware_endianess();
2505 init_txd_sizes();
2506 print_driver_id();
2507 RET(pci_register_driver(&bdx_pci_driver));
2508}
2509
2510module_init(bdx_module_init);
2511
2512static void __exit bdx_module_exit(void)
2513{
2514 ENTER;
2515 pci_unregister_driver(&bdx_pci_driver);
2516 RET();
2517}
2518
2519module_exit(bdx_module_exit);
2520
2521MODULE_LICENSE("GPL");
2522MODULE_AUTHOR(DRIVER_AUTHOR);
2523MODULE_DESCRIPTION(BDX_DRV_DESC);
Clone of davem's net-next-2.6 tree