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1da177e4
LT		 1/* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
6aa20a22 5 *
1da177e4
LT		 6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
9 *
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
6aa20a22
JG		 12 *
13 * TODO:
1da177e4
LT		 14 * - Now that the driver was significantly simplified, I need to rework
15 * the locking. I'm sure we don't need _2_ spinlocks, and we probably
16 * can avoid taking most of them for so long period of time (and schedule
17 * instead). The main issues at this point are caused by the netdev layer
18 * though:
6aa20a22 19 *
1da177e4
LT		 20 * gem_change_mtu() and gem_set_multicast() are called with a read_lock()
21 * help by net/core/dev.c, thus they can't schedule. That means they can't
bea3348e 22 * call napi_disable() neither, thus force gem_poll() to keep a spinlock
1da177e4
LT		 23 * where it could have been dropped. change_mtu especially would love also to
24 * be able to msleep instead of horrid locked delays when resetting the HW,
25 * but that read_lock() makes it impossible, unless I defer it's action to
26 * the reset task, which means it'll be asynchronous (won't take effect until
27 * the system schedules a bit).
28 *
29 * Also, it would probably be possible to also remove most of the long-life
30 * locking in open/resume code path (gem_reinit_chip) by beeing more careful
31 * about when we can start taking interrupts or get xmit() called...
32 */
33
34#include <linux/module.h>
35#include <linux/kernel.h>
36#include <linux/types.h>
37#include <linux/fcntl.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/in.h>
41#include <linux/slab.h>
42#include <linux/string.h>
43#include <linux/delay.h>
44#include <linux/init.h>
45#include <linux/errno.h>
46#include <linux/pci.h>
1e7f0bd8 47#include <linux/dma-mapping.h>
1da177e4
LT		 48#include <linux/netdevice.h>
49#include <linux/etherdevice.h>
50#include <linux/skbuff.h>
51#include <linux/mii.h>
52#include <linux/ethtool.h>
53#include <linux/crc32.h>
54#include <linux/random.h>
55#include <linux/workqueue.h>
56#include <linux/if_vlan.h>
57#include <linux/bitops.h>
e3968fc0 58#include <linux/mutex.h>
d7fe0f24 59#include <linux/mm.h>
1da177e4
LT		 60
61#include <asm/system.h>
62#include <asm/io.h>
63#include <asm/byteorder.h>
64#include <asm/uaccess.h>
65#include <asm/irq.h>
66
dadb830d 67#ifdef CONFIG_SPARC
1da177e4 68#include <asm/idprom.h>
457e1a8a 69#include <asm/prom.h>
1da177e4
LT		 70#endif
71
72#ifdef CONFIG_PPC_PMAC
73#include <asm/pci-bridge.h>
74#include <asm/prom.h>
75#include <asm/machdep.h>
76#include <asm/pmac_feature.h>
77#endif
78
79#include "sungem_phy.h"
80#include "sungem.h"
81
82/* Stripping FCS is causing problems, disabled for now */
83#undef STRIP_FCS
84
85#define DEFAULT_MSG (NETIF_MSG_DRV | \
86 NETIF_MSG_PROBE | \
87 NETIF_MSG_LINK)
88
89#define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
90 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
63ea998a
BH		 91 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
92 SUPPORTED_Pause | SUPPORTED_Autoneg)
1da177e4
LT		 93
94#define DRV_NAME "sungem"
95#define DRV_VERSION "0.98"
96#define DRV_RELDATE "8/24/03"
97#define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
98
99static char version[] __devinitdata =
100 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
101
102MODULE_AUTHOR(DRV_AUTHOR);
103MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
104MODULE_LICENSE("GPL");
105
106#define GEM_MODULE_NAME "gem"
107#define PFX GEM_MODULE_NAME ": "
108
109static struct pci_device_id gem_pci_tbl[] = {
110 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
112
113 /* These models only differ from the original GEM in
114 * that their tx/rx fifos are of a different size and
115 * they only support 10/100 speeds. -DaveM
6aa20a22 116 *
1da177e4
LT		 117 * Apple's GMAC does support gigabit on machines with
118 * the BCM54xx PHYs. -BenH
119 */
120 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
122 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
124 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
126 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
128 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
130 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7fce260a
OJ		 132 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 134 {0, }
135};
136
137MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
138
139static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
140{
141 u32 cmd;
142 int limit = 10000;
143
144 cmd = (1 << 30);
145 cmd |= (2 << 28);
146 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
147 cmd |= (reg << 18) & MIF_FRAME_REGAD;
148 cmd |= (MIF_FRAME_TAMSB);
149 writel(cmd, gp->regs + MIF_FRAME);
150
151 while (limit--) {
152 cmd = readl(gp->regs + MIF_FRAME);
153 if (cmd & MIF_FRAME_TALSB)
154 break;
155
156 udelay(10);
157 }
158
159 if (!limit)
160 cmd = 0xffff;
161
162 return cmd & MIF_FRAME_DATA;
163}
164
165static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
166{
167 struct gem *gp = dev->priv;
168 return __phy_read(gp, mii_id, reg);
169}
170
171static inline u16 phy_read(struct gem *gp, int reg)
172{
173 return __phy_read(gp, gp->mii_phy_addr, reg);
174}
175
176static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
177{
178 u32 cmd;
179 int limit = 10000;
180
181 cmd = (1 << 30);
182 cmd |= (1 << 28);
183 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
184 cmd |= (reg << 18) & MIF_FRAME_REGAD;
185 cmd |= (MIF_FRAME_TAMSB);
186 cmd |= (val & MIF_FRAME_DATA);
187 writel(cmd, gp->regs + MIF_FRAME);
188
189 while (limit--) {
190 cmd = readl(gp->regs + MIF_FRAME);
191 if (cmd & MIF_FRAME_TALSB)
192 break;
193
194 udelay(10);
195 }
196}
197
198static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
199{
200 struct gem *gp = dev->priv;
201 __phy_write(gp, mii_id, reg, val & 0xffff);
202}
203
204static inline void phy_write(struct gem *gp, int reg, u16 val)
205{
206 __phy_write(gp, gp->mii_phy_addr, reg, val);
207}
208
209static inline void gem_enable_ints(struct gem *gp)
210{
211 /* Enable all interrupts but TXDONE */
212 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
213}
214
215static inline void gem_disable_ints(struct gem *gp)
216{
217 /* Disable all interrupts, including TXDONE */
218 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
219}
220
221static void gem_get_cell(struct gem *gp)
222{
223 BUG_ON(gp->cell_enabled < 0);
224 gp->cell_enabled++;
225#ifdef CONFIG_PPC_PMAC
226 if (gp->cell_enabled == 1) {
227 mb();
228 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
229 udelay(10);
230 }
231#endif /* CONFIG_PPC_PMAC */
232}
233
234/* Turn off the chip's clock */
235static void gem_put_cell(struct gem *gp)
236{
237 BUG_ON(gp->cell_enabled <= 0);
238 gp->cell_enabled--;
239#ifdef CONFIG_PPC_PMAC
240 if (gp->cell_enabled == 0) {
241 mb();
242 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
243 udelay(10);
244 }
245#endif /* CONFIG_PPC_PMAC */
246}
247
248static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
249{
250 if (netif_msg_intr(gp))
251 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
252}
253
254static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
255{
256 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
257 u32 pcs_miistat;
258
259 if (netif_msg_intr(gp))
260 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
261 gp->dev->name, pcs_istat);
262
263 if (!(pcs_istat & PCS_ISTAT_LSC)) {
264 printk(KERN_ERR "%s: PCS irq but no link status change???\n",
265 dev->name);
266 return 0;
267 }
268
269 /* The link status bit latches on zero, so you must
270 * read it twice in such a case to see a transition
271 * to the link being up.
272 */
273 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
274 if (!(pcs_miistat & PCS_MIISTAT_LS))
275 pcs_miistat |=
276 (readl(gp->regs + PCS_MIISTAT) &
277 PCS_MIISTAT_LS);
278
279 if (pcs_miistat & PCS_MIISTAT_ANC) {
280 /* The remote-fault indication is only valid
281 * when autoneg has completed.
282 */
283 if (pcs_miistat & PCS_MIISTAT_RF)
284 printk(KERN_INFO "%s: PCS AutoNEG complete, "
285 "RemoteFault\n", dev->name);
286 else
287 printk(KERN_INFO "%s: PCS AutoNEG complete.\n",
288 dev->name);
289 }
290
291 if (pcs_miistat & PCS_MIISTAT_LS) {
292 printk(KERN_INFO "%s: PCS link is now up.\n",
293 dev->name);
294 netif_carrier_on(gp->dev);
295 } else {
296 printk(KERN_INFO "%s: PCS link is now down.\n",
297 dev->name);
298 netif_carrier_off(gp->dev);
299 /* If this happens and the link timer is not running,
300 * reset so we re-negotiate.
301 */
302 if (!timer_pending(&gp->link_timer))
303 return 1;
304 }
305
306 return 0;
307}
308
309static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
310{
311 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
312
313 if (netif_msg_intr(gp))
314 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
315 gp->dev->name, txmac_stat);
316
317 /* Defer timer expiration is quite normal,
318 * don't even log the event.
319 */
320 if ((txmac_stat & MAC_TXSTAT_DTE) &&
321 !(txmac_stat & ~MAC_TXSTAT_DTE))
322 return 0;
323
324 if (txmac_stat & MAC_TXSTAT_URUN) {
325 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
326 dev->name);
327 gp->net_stats.tx_fifo_errors++;
328 }
329
330 if (txmac_stat & MAC_TXSTAT_MPE) {
331 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
332 dev->name);
333 gp->net_stats.tx_errors++;
334 }
335
336 /* The rest are all cases of one of the 16-bit TX
337 * counters expiring.
338 */
339 if (txmac_stat & MAC_TXSTAT_NCE)
340 gp->net_stats.collisions += 0x10000;
341
342 if (txmac_stat & MAC_TXSTAT_ECE) {
343 gp->net_stats.tx_aborted_errors += 0x10000;
344 gp->net_stats.collisions += 0x10000;
345 }
346
347 if (txmac_stat & MAC_TXSTAT_LCE) {
348 gp->net_stats.tx_aborted_errors += 0x10000;
349 gp->net_stats.collisions += 0x10000;
350 }
351
352 /* We do not keep track of MAC_TXSTAT_FCE and
353 * MAC_TXSTAT_PCE events.
354 */
355 return 0;
356}
357
358/* When we get a RX fifo overflow, the RX unit in GEM is probably hung
359 * so we do the following.
360 *
361 * If any part of the reset goes wrong, we return 1 and that causes the
362 * whole chip to be reset.
363 */
364static int gem_rxmac_reset(struct gem *gp)
365{
366 struct net_device *dev = gp->dev;
367 int limit, i;
368 u64 desc_dma;
369 u32 val;
370
371 /* First, reset & disable MAC RX. */
372 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
373 for (limit = 0; limit < 5000; limit++) {
374 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
375 break;
376 udelay(10);
377 }
378 if (limit == 5000) {
379 printk(KERN_ERR "%s: RX MAC will not reset, resetting whole "
380 "chip.\n", dev->name);
381 return 1;
382 }
383
384 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
385 gp->regs + MAC_RXCFG);
386 for (limit = 0; limit < 5000; limit++) {
387 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
388 break;
389 udelay(10);
390 }
391 if (limit == 5000) {
392 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
393 "chip.\n", dev->name);
394 return 1;
395 }
396
397 /* Second, disable RX DMA. */
398 writel(0, gp->regs + RXDMA_CFG);
399 for (limit = 0; limit < 5000; limit++) {
400 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
401 break;
402 udelay(10);
403 }
404 if (limit == 5000) {
405 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
406 "chip.\n", dev->name);
407 return 1;
408 }
409
410 udelay(5000);
411
412 /* Execute RX reset command. */
413 writel(gp->swrst_base | GREG_SWRST_RXRST,
414 gp->regs + GREG_SWRST);
415 for (limit = 0; limit < 5000; limit++) {
416 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
417 break;
418 udelay(10);
419 }
420 if (limit == 5000) {
421 printk(KERN_ERR "%s: RX reset command will not execute, resetting "
422 "whole chip.\n", dev->name);
423 return 1;
424 }
425
426 /* Refresh the RX ring. */
427 for (i = 0; i < RX_RING_SIZE; i++) {
428 struct gem_rxd *rxd = &gp->init_block->rxd[i];
429
430 if (gp->rx_skbs[i] == NULL) {
431 printk(KERN_ERR "%s: Parts of RX ring empty, resetting "
432 "whole chip.\n", dev->name);
433 return 1;
434 }
435
436 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
437 }
438 gp->rx_new = gp->rx_old = 0;
439
440 /* Now we must reprogram the rest of RX unit. */
441 desc_dma = (u64) gp->gblock_dvma;
442 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
443 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
444 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
445 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
446 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
447 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
448 writel(val, gp->regs + RXDMA_CFG);
449 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
450 writel(((5 & RXDMA_BLANK_IPKTS) |
451 ((8 << 12) & RXDMA_BLANK_ITIME)),
452 gp->regs + RXDMA_BLANK);
453 else
454 writel(((5 & RXDMA_BLANK_IPKTS) |
455 ((4 << 12) & RXDMA_BLANK_ITIME)),
456 gp->regs + RXDMA_BLANK);
457 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
458 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
459 writel(val, gp->regs + RXDMA_PTHRESH);
460 val = readl(gp->regs + RXDMA_CFG);
461 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
462 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
463 val = readl(gp->regs + MAC_RXCFG);
464 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
465
466 return 0;
467}
468
469static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
470{
471 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
472 int ret = 0;
473
474 if (netif_msg_intr(gp))
475 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
476 gp->dev->name, rxmac_stat);
477
478 if (rxmac_stat & MAC_RXSTAT_OFLW) {
479 u32 smac = readl(gp->regs + MAC_SMACHINE);
480
481 printk(KERN_ERR "%s: RX MAC fifo overflow smac[%08x].\n",
482 dev->name, smac);
483 gp->net_stats.rx_over_errors++;
484 gp->net_stats.rx_fifo_errors++;
485
486 ret = gem_rxmac_reset(gp);
487 }
488
489 if (rxmac_stat & MAC_RXSTAT_ACE)
490 gp->net_stats.rx_frame_errors += 0x10000;
491
492 if (rxmac_stat & MAC_RXSTAT_CCE)
493 gp->net_stats.rx_crc_errors += 0x10000;
494
495 if (rxmac_stat & MAC_RXSTAT_LCE)
496 gp->net_stats.rx_length_errors += 0x10000;
497
498 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
499 * events.
500 */
501 return ret;
502}
503
504static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
505{
506 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
507
508 if (netif_msg_intr(gp))
509 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
510 gp->dev->name, mac_cstat);
511
512 /* This interrupt is just for pause frame and pause
513 * tracking. It is useful for diagnostics and debug
514 * but probably by default we will mask these events.
515 */
516 if (mac_cstat & MAC_CSTAT_PS)
517 gp->pause_entered++;
518
519 if (mac_cstat & MAC_CSTAT_PRCV)
520 gp->pause_last_time_recvd = (mac_cstat >> 16);
521
522 return 0;
523}
524
525static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
526{
527 u32 mif_status = readl(gp->regs + MIF_STATUS);
528 u32 reg_val, changed_bits;
529
530 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
531 changed_bits = (mif_status & MIF_STATUS_STAT);
532
533 gem_handle_mif_event(gp, reg_val, changed_bits);
534
535 return 0;
536}
537
538static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
539{
540 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
541
542 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
543 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
544 printk(KERN_ERR "%s: PCI error [%04x] ",
545 dev->name, pci_estat);
546
547 if (pci_estat & GREG_PCIESTAT_BADACK)
548 printk("<No ACK64# during ABS64 cycle> ");
549 if (pci_estat & GREG_PCIESTAT_DTRTO)
550 printk("<Delayed transaction timeout> ");
551 if (pci_estat & GREG_PCIESTAT_OTHER)
552 printk("<other>");
553 printk("\n");
554 } else {
555 pci_estat |= GREG_PCIESTAT_OTHER;
556 printk(KERN_ERR "%s: PCI error\n", dev->name);
557 }
558
559 if (pci_estat & GREG_PCIESTAT_OTHER) {
560 u16 pci_cfg_stat;
561
562 /* Interrogate PCI config space for the
563 * true cause.
564 */
565 pci_read_config_word(gp->pdev, PCI_STATUS,
566 &pci_cfg_stat);
567 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
568 dev->name, pci_cfg_stat);
569 if (pci_cfg_stat & PCI_STATUS_PARITY)
570 printk(KERN_ERR "%s: PCI parity error detected.\n",
571 dev->name);
572 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
573 printk(KERN_ERR "%s: PCI target abort.\n",
574 dev->name);
575 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
576 printk(KERN_ERR "%s: PCI master acks target abort.\n",
577 dev->name);
578 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
579 printk(KERN_ERR "%s: PCI master abort.\n",
580 dev->name);
581 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
582 printk(KERN_ERR "%s: PCI system error SERR#.\n",
583 dev->name);
584 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
585 printk(KERN_ERR "%s: PCI parity error.\n",
586 dev->name);
587
588 /* Write the error bits back to clear them. */
589 pci_cfg_stat &= (PCI_STATUS_PARITY |
590 PCI_STATUS_SIG_TARGET_ABORT |
591 PCI_STATUS_REC_TARGET_ABORT |
592 PCI_STATUS_REC_MASTER_ABORT |
593 PCI_STATUS_SIG_SYSTEM_ERROR |
594 PCI_STATUS_DETECTED_PARITY);
595 pci_write_config_word(gp->pdev,
596 PCI_STATUS, pci_cfg_stat);
597 }
598
599 /* For all PCI errors, we should reset the chip. */
600 return 1;
601}
602
603/* All non-normal interrupt conditions get serviced here.
604 * Returns non-zero if we should just exit the interrupt
605 * handler right now (ie. if we reset the card which invalidates
606 * all of the other original irq status bits).
607 */
608static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
609{
610 if (gem_status & GREG_STAT_RXNOBUF) {
611 /* Frame arrived, no free RX buffers available. */
612 if (netif_msg_rx_err(gp))
613 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
614 gp->dev->name);
615 gp->net_stats.rx_dropped++;
616 }
617
618 if (gem_status & GREG_STAT_RXTAGERR) {
619 /* corrupt RX tag framing */
620 if (netif_msg_rx_err(gp))
621 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
622 gp->dev->name);
623 gp->net_stats.rx_errors++;
624
625 goto do_reset;
626 }
627
628 if (gem_status & GREG_STAT_PCS) {
629 if (gem_pcs_interrupt(dev, gp, gem_status))
630 goto do_reset;
631 }
632
633 if (gem_status & GREG_STAT_TXMAC) {
634 if (gem_txmac_interrupt(dev, gp, gem_status))
635 goto do_reset;
636 }
637
638 if (gem_status & GREG_STAT_RXMAC) {
639 if (gem_rxmac_interrupt(dev, gp, gem_status))
640 goto do_reset;
641 }
642
643 if (gem_status & GREG_STAT_MAC) {
644 if (gem_mac_interrupt(dev, gp, gem_status))
645 goto do_reset;
646 }
647
648 if (gem_status & GREG_STAT_MIF) {
649 if (gem_mif_interrupt(dev, gp, gem_status))
650 goto do_reset;
651 }
652
653 if (gem_status & GREG_STAT_PCIERR) {
654 if (gem_pci_interrupt(dev, gp, gem_status))
655 goto do_reset;
656 }
657
658 return 0;
659
660do_reset:
661 gp->reset_task_pending = 1;
662 schedule_work(&gp->reset_task);
663
664 return 1;
665}
666
667static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
668{
669 int entry, limit;
670
671 if (netif_msg_intr(gp))
672 printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n",
673 gp->dev->name, gem_status);
674
675 entry = gp->tx_old;
676 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
677 while (entry != limit) {
678 struct sk_buff *skb;
679 struct gem_txd *txd;
680 dma_addr_t dma_addr;
681 u32 dma_len;
682 int frag;
683
684 if (netif_msg_tx_done(gp))
685 printk(KERN_DEBUG "%s: tx done, slot %d\n",
686 gp->dev->name, entry);
687 skb = gp->tx_skbs[entry];
688 if (skb_shinfo(skb)->nr_frags) {
689 int last = entry + skb_shinfo(skb)->nr_frags;
690 int walk = entry;
691 int incomplete = 0;
692
693 last &= (TX_RING_SIZE - 1);
694 for (;;) {
695 walk = NEXT_TX(walk);
696 if (walk == limit)
697 incomplete = 1;
698 if (walk == last)
699 break;
700 }
701 if (incomplete)
702 break;
703 }
704 gp->tx_skbs[entry] = NULL;
705 gp->net_stats.tx_bytes += skb->len;
706
707 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
708 txd = &gp->init_block->txd[entry];
709
710 dma_addr = le64_to_cpu(txd->buffer);
711 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
712
713 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
714 entry = NEXT_TX(entry);
715 }
716
717 gp->net_stats.tx_packets++;
718 dev_kfree_skb_irq(skb);
719 }
720 gp->tx_old = entry;
721
722 if (netif_queue_stopped(dev) &&
723 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
724 netif_wake_queue(dev);
725}
726
727static __inline__ void gem_post_rxds(struct gem *gp, int limit)
728{
729 int cluster_start, curr, count, kick;
730
731 cluster_start = curr = (gp->rx_new & ~(4 - 1));
732 count = 0;
733 kick = -1;
734 wmb();
735 while (curr != limit) {
736 curr = NEXT_RX(curr);
737 if (++count == 4) {
738 struct gem_rxd *rxd =
739 &gp->init_block->rxd[cluster_start];
740 for (;;) {
741 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
742 rxd++;
743 cluster_start = NEXT_RX(cluster_start);
744 if (cluster_start == curr)
745 break;
746 }
747 kick = curr;
748 count = 0;
749 }
750 }
751 if (kick >= 0) {
752 mb();
753 writel(kick, gp->regs + RXDMA_KICK);
754 }
755}
756
757static int gem_rx(struct gem *gp, int work_to_do)
758{
759 int entry, drops, work_done = 0;
760 u32 done;
761
762 if (netif_msg_rx_status(gp))
763 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
764 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
765
766 entry = gp->rx_new;
767 drops = 0;
768 done = readl(gp->regs + RXDMA_DONE);
769 for (;;) {
770 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
771 struct sk_buff *skb;
772 u64 status = cpu_to_le64(rxd->status_word);
773 dma_addr_t dma_addr;
774 int len;
775
776 if ((status & RXDCTRL_OWN) != 0)
777 break;
778
779 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
780 break;
781
782 /* When writing back RX descriptor, GEM writes status
783 * then buffer address, possibly in seperate transactions.
784 * If we don't wait for the chip to write both, we could
785 * post a new buffer to this descriptor then have GEM spam
786 * on the buffer address. We sync on the RX completion
787 * register to prevent this from happening.
788 */
789 if (entry == done) {
790 done = readl(gp->regs + RXDMA_DONE);
791 if (entry == done)
792 break;
793 }
794
795 /* We can now account for the work we're about to do */
796 work_done++;
797
798 skb = gp->rx_skbs[entry];
799
800 len = (status & RXDCTRL_BUFSZ) >> 16;
801 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
802 gp->net_stats.rx_errors++;
803 if (len < ETH_ZLEN)
804 gp->net_stats.rx_length_errors++;
805 if (len & RXDCTRL_BAD)
806 gp->net_stats.rx_crc_errors++;
807
808 /* We'll just return it to GEM. */
809 drop_it:
810 gp->net_stats.rx_dropped++;
811 goto next;
812 }
813
814 dma_addr = cpu_to_le64(rxd->buffer);
815 if (len > RX_COPY_THRESHOLD) {
816 struct sk_buff *new_skb;
817
818 new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
819 if (new_skb == NULL) {
820 drops++;
821 goto drop_it;
822 }
823 pci_unmap_page(gp->pdev, dma_addr,
824 RX_BUF_ALLOC_SIZE(gp),
825 PCI_DMA_FROMDEVICE);
826 gp->rx_skbs[entry] = new_skb;
827 new_skb->dev = gp->dev;
828 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
829 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
830 virt_to_page(new_skb->data),
831 offset_in_page(new_skb->data),
832 RX_BUF_ALLOC_SIZE(gp),
833 PCI_DMA_FROMDEVICE));
834 skb_reserve(new_skb, RX_OFFSET);
835
836 /* Trim the original skb for the netif. */
837 skb_trim(skb, len);
838 } else {
839 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
840
841 if (copy_skb == NULL) {
842 drops++;
843 goto drop_it;
844 }
845
1da177e4
LT		 846 skb_reserve(copy_skb, 2);
847 skb_put(copy_skb, len);
848 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 849 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 850 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
851
852 /* We'll reuse the original ring buffer. */
853 skb = copy_skb;
854 }
855
856 skb->csum = ntohs((status & RXDCTRL_TCPCSUM) ^ 0xffff);
84fa7933 857 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 858 skb->protocol = eth_type_trans(skb, gp->dev);
859
860 netif_receive_skb(skb);
861
862 gp->net_stats.rx_packets++;
863 gp->net_stats.rx_bytes += len;
864 gp->dev->last_rx = jiffies;
865
866 next:
867 entry = NEXT_RX(entry);
868 }
869
870 gem_post_rxds(gp, entry);
871
872 gp->rx_new = entry;
873
874 if (drops)
875 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
876 gp->dev->name);
877
878 return work_done;
879}
880
bea3348e 881static int gem_poll(struct napi_struct *napi, int budget)
1da177e4 882{
bea3348e
SH		 883 struct gem *gp = container_of(napi, struct gem, napi);
884 struct net_device *dev = gp->dev;
1da177e4 885 unsigned long flags;
bea3348e 886 int work_done;
1da177e4
LT		 887
888 /*
6aa20a22 889 * NAPI locking nightmare: See comment at head of driver
1da177e4
LT		 890 */
891 spin_lock_irqsave(&gp->lock, flags);
892
bea3348e 893 work_done = 0;
1da177e4 894 do {
1da177e4
LT		 895 /* Handle anomalies */
896 if (gp->status & GREG_STAT_ABNORMAL) {
897 if (gem_abnormal_irq(dev, gp, gp->status))
898 break;
899 }
900
901 /* Run TX completion thread */
902 spin_lock(&gp->tx_lock);
903 gem_tx(dev, gp, gp->status);
904 spin_unlock(&gp->tx_lock);
905
906 spin_unlock_irqrestore(&gp->lock, flags);
907
6aa20a22
JG		 908 /* Run RX thread. We don't use any locking here,
909 * code willing to do bad things - like cleaning the
bea3348e 910 * rx ring - must call napi_disable(), which
1da177e4
LT		 911 * schedule_timeout()'s if polling is already disabled.
912 */
bea3348e 913 work_done += gem_rx(gp, budget);
1da177e4 914
bea3348e
SH		 915 if (work_done >= budget)
916 return work_done;
1da177e4
LT		 917
918 spin_lock_irqsave(&gp->lock, flags);
6aa20a22 919
1da177e4
LT		 920 gp->status = readl(gp->regs + GREG_STAT);
921 } while (gp->status & GREG_STAT_NAPI);
922
bea3348e 923 __netif_rx_complete(dev, napi);
1da177e4
LT		 924 gem_enable_ints(gp);
925
926 spin_unlock_irqrestore(&gp->lock, flags);
bea3348e
SH		 927
928 return work_done;
1da177e4
LT		 929}
930
7d12e780 931static irqreturn_t gem_interrupt(int irq, void *dev_id)
1da177e4
LT		 932{
933 struct net_device *dev = dev_id;
934 struct gem *gp = dev->priv;
935 unsigned long flags;
936
937 /* Swallow interrupts when shutting the chip down, though
938 * that shouldn't happen, we should have done free_irq() at
939 * this point...
940 */
941 if (!gp->running)
942 return IRQ_HANDLED;
943
944 spin_lock_irqsave(&gp->lock, flags);
6aa20a22 945
bea3348e 946 if (netif_rx_schedule_prep(dev, &gp->napi)) {
1da177e4
LT		 947 u32 gem_status = readl(gp->regs + GREG_STAT);
948
949 if (gem_status == 0) {
bea3348e 950 napi_enable(&gp->napi);
1da177e4
LT		 951 spin_unlock_irqrestore(&gp->lock, flags);
952 return IRQ_NONE;
953 }
954 gp->status = gem_status;
955 gem_disable_ints(gp);
bea3348e 956 __netif_rx_schedule(dev, &gp->napi);
1da177e4
LT		 957 }
958
959 spin_unlock_irqrestore(&gp->lock, flags);
6aa20a22 960
1da177e4 961 /* If polling was disabled at the time we received that
6aa20a22 962 * interrupt, we may return IRQ_HANDLED here while we
1da177e4
LT		 963 * should return IRQ_NONE. No big deal...
964 */
965 return IRQ_HANDLED;
966}
967
968#ifdef CONFIG_NET_POLL_CONTROLLER
969static void gem_poll_controller(struct net_device *dev)
970{
971 /* gem_interrupt is safe to reentrance so no need
972 * to disable_irq here.
973 */
7d12e780 974 gem_interrupt(dev->irq, dev);
1da177e4
LT		 975}
976#endif
977
978static void gem_tx_timeout(struct net_device *dev)
979{
980 struct gem *gp = dev->priv;
981
982 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
983 if (!gp->running) {
984 printk("%s: hrm.. hw not running !\n", dev->name);
985 return;
986 }
987 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x]\n",
988 dev->name,
989 readl(gp->regs + TXDMA_CFG),
990 readl(gp->regs + MAC_TXSTAT),
991 readl(gp->regs + MAC_TXCFG));
992 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
993 dev->name,
994 readl(gp->regs + RXDMA_CFG),
995 readl(gp->regs + MAC_RXSTAT),
996 readl(gp->regs + MAC_RXCFG));
997
998 spin_lock_irq(&gp->lock);
999 spin_lock(&gp->tx_lock);
1000
1001 gp->reset_task_pending = 1;
1002 schedule_work(&gp->reset_task);
1003
1004 spin_unlock(&gp->tx_lock);
1005 spin_unlock_irq(&gp->lock);
1006}
1007
1008static __inline__ int gem_intme(int entry)
1009{
1010 /* Algorithm: IRQ every 1/2 of descriptors. */
1011 if (!(entry & ((TX_RING_SIZE>>1)-1)))
1012 return 1;
1013
1014 return 0;
1015}
1016
1017static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
1018{
1019 struct gem *gp = dev->priv;
1020 int entry;
1021 u64 ctrl;
1022 unsigned long flags;
1023
1024 ctrl = 0;
84fa7933 1025 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d
ACM		 1026 const u64 csum_start_off = skb_transport_offset(skb);
1027 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
1da177e4
LT		 1028
1029 ctrl = (TXDCTRL_CENAB |
1030 (csum_start_off << 15) |
1031 (csum_stuff_off << 21));
1032 }
1033
1034 local_irq_save(flags);
1035 if (!spin_trylock(&gp->tx_lock)) {
1036 /* Tell upper layer to requeue */
1037 local_irq_restore(flags);
1038 return NETDEV_TX_LOCKED;
1039 }
1040 /* We raced with gem_do_stop() */
1041 if (!gp->running) {
1042 spin_unlock_irqrestore(&gp->tx_lock, flags);
1043 return NETDEV_TX_BUSY;
1044 }
1045
1046 /* This is a hard error, log it. */
1047 if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
1048 netif_stop_queue(dev);
1049 spin_unlock_irqrestore(&gp->tx_lock, flags);
1050 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
1051 dev->name);
1052 return NETDEV_TX_BUSY;
1053 }
1054
1055 entry = gp->tx_new;
1056 gp->tx_skbs[entry] = skb;
1057
1058 if (skb_shinfo(skb)->nr_frags == 0) {
1059 struct gem_txd *txd = &gp->init_block->txd[entry];
1060 dma_addr_t mapping;
1061 u32 len;
1062
1063 len = skb->len;
1064 mapping = pci_map_page(gp->pdev,
1065 virt_to_page(skb->data),
1066 offset_in_page(skb->data),
1067 len, PCI_DMA_TODEVICE);
1068 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1069 if (gem_intme(entry))
1070 ctrl |= TXDCTRL_INTME;
1071 txd->buffer = cpu_to_le64(mapping);
1072 wmb();
1073 txd->control_word = cpu_to_le64(ctrl);
1074 entry = NEXT_TX(entry);
1075 } else {
1076 struct gem_txd *txd;
1077 u32 first_len;
1078 u64 intme;
1079 dma_addr_t first_mapping;
1080 int frag, first_entry = entry;
1081
1082 intme = 0;
1083 if (gem_intme(entry))
1084 intme |= TXDCTRL_INTME;
1085
1086 /* We must give this initial chunk to the device last.
1087 * Otherwise we could race with the device.
1088 */
1089 first_len = skb_headlen(skb);
1090 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1091 offset_in_page(skb->data),
1092 first_len, PCI_DMA_TODEVICE);
1093 entry = NEXT_TX(entry);
1094
1095 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1096 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1097 u32 len;
1098 dma_addr_t mapping;
1099 u64 this_ctrl;
1100
1101 len = this_frag->size;
1102 mapping = pci_map_page(gp->pdev,
1103 this_frag->page,
1104 this_frag->page_offset,
1105 len, PCI_DMA_TODEVICE);
1106 this_ctrl = ctrl;
1107 if (frag == skb_shinfo(skb)->nr_frags - 1)
1108 this_ctrl |= TXDCTRL_EOF;
6aa20a22 1109
1da177e4
LT		 1110 txd = &gp->init_block->txd[entry];
1111 txd->buffer = cpu_to_le64(mapping);
1112 wmb();
1113 txd->control_word = cpu_to_le64(this_ctrl | len);
1114
1115 if (gem_intme(entry))
1116 intme |= TXDCTRL_INTME;
1117
1118 entry = NEXT_TX(entry);
1119 }
1120 txd = &gp->init_block->txd[first_entry];
1121 txd->buffer = cpu_to_le64(first_mapping);
1122 wmb();
1123 txd->control_word =
1124 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1125 }
1126
1127 gp->tx_new = entry;
1128 if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))
1129 netif_stop_queue(dev);
1130
1131 if (netif_msg_tx_queued(gp))
1132 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1133 dev->name, entry, skb->len);
1134 mb();
1135 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1136 spin_unlock_irqrestore(&gp->tx_lock, flags);
1137
1138 dev->trans_start = jiffies;
1139
1140 return NETDEV_TX_OK;
1141}
1142
1143#define STOP_TRIES 32
1144
1145/* Must be invoked under gp->lock and gp->tx_lock. */
1146static void gem_reset(struct gem *gp)
1147{
1148 int limit;
1149 u32 val;
1150
1151 /* Make sure we won't get any more interrupts */
1152 writel(0xffffffff, gp->regs + GREG_IMASK);
1153
1154 /* Reset the chip */
1155 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1156 gp->regs + GREG_SWRST);
1157
1158 limit = STOP_TRIES;
1159
1160 do {
1161 udelay(20);
1162 val = readl(gp->regs + GREG_SWRST);
1163 if (limit-- <= 0)
1164 break;
1165 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1166
1167 if (limit <= 0)
1168 printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name);
1169}
1170
1171/* Must be invoked under gp->lock and gp->tx_lock. */
1172static void gem_start_dma(struct gem *gp)
1173{
1174 u32 val;
6aa20a22 1175
1da177e4
LT		 1176 /* We are ready to rock, turn everything on. */
1177 val = readl(gp->regs + TXDMA_CFG);
1178 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1179 val = readl(gp->regs + RXDMA_CFG);
1180 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1181 val = readl(gp->regs + MAC_TXCFG);
1182 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1183 val = readl(gp->regs + MAC_RXCFG);
1184 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1185
1186 (void) readl(gp->regs + MAC_RXCFG);
1187 udelay(100);
1188
1189 gem_enable_ints(gp);
1190
1191 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1192}
1193
1194/* Must be invoked under gp->lock and gp->tx_lock. DMA won't be
1195 * actually stopped before about 4ms tho ...
1196 */
1197static void gem_stop_dma(struct gem *gp)
1198{
1199 u32 val;
1200
1201 /* We are done rocking, turn everything off. */
1202 val = readl(gp->regs + TXDMA_CFG);
1203 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1204 val = readl(gp->regs + RXDMA_CFG);
1205 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1206 val = readl(gp->regs + MAC_TXCFG);
1207 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1208 val = readl(gp->regs + MAC_RXCFG);
1209 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1210
1211 (void) readl(gp->regs + MAC_RXCFG);
1212
1213 /* Need to wait a bit ... done by the caller */
1214}
1215
1216
1217/* Must be invoked under gp->lock and gp->tx_lock. */
1218// XXX dbl check what that function should do when called on PCS PHY
1219static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1220{
1221 u32 advertise, features;
1222 int autoneg;
1223 int speed;
1224 int duplex;
1225
1226 if (gp->phy_type != phy_mii_mdio0 &&
1227 gp->phy_type != phy_mii_mdio1)
1228 goto non_mii;
1229
1230 /* Setup advertise */
1231 if (found_mii_phy(gp))
1232 features = gp->phy_mii.def->features;
1233 else
1234 features = 0;
1235
1236 advertise = features & ADVERTISE_MASK;
1237 if (gp->phy_mii.advertising != 0)
1238 advertise &= gp->phy_mii.advertising;
1239
1240 autoneg = gp->want_autoneg;
1241 speed = gp->phy_mii.speed;
1242 duplex = gp->phy_mii.duplex;
6aa20a22 1243
1da177e4
LT		 1244 /* Setup link parameters */
1245 if (!ep)
1246 goto start_aneg;
1247 if (ep->autoneg == AUTONEG_ENABLE) {
1248 advertise = ep->advertising;
1249 autoneg = 1;
1250 } else {
1251 autoneg = 0;
1252 speed = ep->speed;
1253 duplex = ep->duplex;
1254 }
1255
1256start_aneg:
1257 /* Sanitize settings based on PHY capabilities */
1258 if ((features & SUPPORTED_Autoneg) == 0)
1259 autoneg = 0;
1260 if (speed == SPEED_1000 &&
1261 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1262 speed = SPEED_100;
1263 if (speed == SPEED_100 &&
1264 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1265 speed = SPEED_10;
1266 if (duplex == DUPLEX_FULL &&
1267 !(features & (SUPPORTED_1000baseT_Full |
1268 SUPPORTED_100baseT_Full |
1269 SUPPORTED_10baseT_Full)))
1270 duplex = DUPLEX_HALF;
1271 if (speed == 0)
1272 speed = SPEED_10;
6aa20a22 1273
1da177e4
LT		 1274 /* If we are asleep, we don't try to actually setup the PHY, we
1275 * just store the settings
1276 */
1277 if (gp->asleep) {
1278 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1279 gp->phy_mii.speed = speed;
1280 gp->phy_mii.duplex = duplex;
1281 return;
1282 }
1283
1284 /* Configure PHY & start aneg */
1285 gp->want_autoneg = autoneg;
1286 if (autoneg) {
1287 if (found_mii_phy(gp))
1288 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1289 gp->lstate = link_aneg;
1290 } else {
1291 if (found_mii_phy(gp))
1292 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1293 gp->lstate = link_force_ok;
1294 }
1295
1296non_mii:
1297 gp->timer_ticks = 0;
1298 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1299}
1300
1301/* A link-up condition has occurred, initialize and enable the
1302 * rest of the chip.
1303 *
1304 * Must be invoked under gp->lock and gp->tx_lock.
1305 */
1306static int gem_set_link_modes(struct gem *gp)
1307{
1308 u32 val;
1309 int full_duplex, speed, pause;
1310
1311 full_duplex = 0;
1312 speed = SPEED_10;
1313 pause = 0;
1314
1315 if (found_mii_phy(gp)) {
1316 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1317 return 1;
1318 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1319 speed = gp->phy_mii.speed;
1320 pause = gp->phy_mii.pause;
1321 } else if (gp->phy_type == phy_serialink ||
1322 gp->phy_type == phy_serdes) {
1323 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1324
1325 if (pcs_lpa & PCS_MIIADV_FD)
1326 full_duplex = 1;
1327 speed = SPEED_1000;
1328 }
1329
1330 if (netif_msg_link(gp))
1331 printk(KERN_INFO "%s: Link is up at %d Mbps, %s-duplex.\n",
1332 gp->dev->name, speed, (full_duplex ? "full" : "half"));
1333
1334 if (!gp->running)
1335 return 0;
1336
1337 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1338 if (full_duplex) {
1339 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1340 } else {
1341 /* MAC_TXCFG_NBO must be zero. */
6aa20a22 1342 }
1da177e4
LT		 1343 writel(val, gp->regs + MAC_TXCFG);
1344
1345 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1346 if (!full_duplex &&
1347 (gp->phy_type == phy_mii_mdio0 ||
1348 gp->phy_type == phy_mii_mdio1)) {
1349 val |= MAC_XIFCFG_DISE;
1350 } else if (full_duplex) {
1351 val |= MAC_XIFCFG_FLED;
1352 }
1353
1354 if (speed == SPEED_1000)
1355 val |= (MAC_XIFCFG_GMII);
1356
1357 writel(val, gp->regs + MAC_XIFCFG);
1358
1359 /* If gigabit and half-duplex, enable carrier extension
1360 * mode. Else, disable it.
1361 */
1362 if (speed == SPEED_1000 && !full_duplex) {
1363 val = readl(gp->regs + MAC_TXCFG);
1364 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1365
1366 val = readl(gp->regs + MAC_RXCFG);
1367 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1368 } else {
1369 val = readl(gp->regs + MAC_TXCFG);
1370 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1371
1372 val = readl(gp->regs + MAC_RXCFG);
1373 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1374 }
1375
1376 if (gp->phy_type == phy_serialink ||
1377 gp->phy_type == phy_serdes) {
1378 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1379
1380 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1381 pause = 1;
1382 }
1383
1384 if (netif_msg_link(gp)) {
1385 if (pause) {
1386 printk(KERN_INFO "%s: Pause is enabled "
1387 "(rxfifo: %d off: %d on: %d)\n",
1388 gp->dev->name,
1389 gp->rx_fifo_sz,
1390 gp->rx_pause_off,
1391 gp->rx_pause_on);
1392 } else {
1393 printk(KERN_INFO "%s: Pause is disabled\n",
1394 gp->dev->name);
1395 }
1396 }
1397
1398 if (!full_duplex)
1399 writel(512, gp->regs + MAC_STIME);
1400 else
1401 writel(64, gp->regs + MAC_STIME);
1402 val = readl(gp->regs + MAC_MCCFG);
1403 if (pause)
1404 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1405 else
1406 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1407 writel(val, gp->regs + MAC_MCCFG);
1408
1409 gem_start_dma(gp);
1410
1411 return 0;
1412}
1413
1414/* Must be invoked under gp->lock and gp->tx_lock. */
1415static int gem_mdio_link_not_up(struct gem *gp)
1416{
1417 switch (gp->lstate) {
1418 case link_force_ret:
1419 if (netif_msg_link(gp))
1420 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1421 " forced mode\n", gp->dev->name);
1422 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1423 gp->last_forced_speed, DUPLEX_HALF);
1424 gp->timer_ticks = 5;
1425 gp->lstate = link_force_ok;
1426 return 0;
1427 case link_aneg:
1428 /* We try forced modes after a failed aneg only on PHYs that don't
1429 * have "magic_aneg" bit set, which means they internally do the
1430 * while forced-mode thingy. On these, we just restart aneg
1431 */
1432 if (gp->phy_mii.def->magic_aneg)
1433 return 1;
1434 if (netif_msg_link(gp))
1435 printk(KERN_INFO "%s: switching to forced 100bt\n",
1436 gp->dev->name);
1437 /* Try forced modes. */
1438 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1439 DUPLEX_HALF);
1440 gp->timer_ticks = 5;
1441 gp->lstate = link_force_try;
1442 return 0;
1443 case link_force_try:
1444 /* Downgrade from 100 to 10 Mbps if necessary.
1445 * If already at 10Mbps, warn user about the
1446 * situation every 10 ticks.
1447 */
1448 if (gp->phy_mii.speed == SPEED_100) {
1449 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1450 DUPLEX_HALF);
1451 gp->timer_ticks = 5;
1452 if (netif_msg_link(gp))
1453 printk(KERN_INFO "%s: switching to forced 10bt\n",
1454 gp->dev->name);
1455 return 0;
1456 } else
1457 return 1;
1458 default:
1459 return 0;
1460 }
1461}
1462
1463static void gem_link_timer(unsigned long data)
1464{
1465 struct gem *gp = (struct gem *) data;
1466 int restart_aneg = 0;
6aa20a22 1467
1da177e4
LT		 1468 if (gp->asleep)
1469 return;
1470
1471 spin_lock_irq(&gp->lock);
1472 spin_lock(&gp->tx_lock);
1473 gem_get_cell(gp);
1474
1475 /* If the reset task is still pending, we just
1476 * reschedule the link timer
1477 */
1478 if (gp->reset_task_pending)
1479 goto restart;
6aa20a22 1480
1da177e4
LT		 1481 if (gp->phy_type == phy_serialink ||
1482 gp->phy_type == phy_serdes) {
1483 u32 val = readl(gp->regs + PCS_MIISTAT);
1484
1485 if (!(val & PCS_MIISTAT_LS))
1486 val = readl(gp->regs + PCS_MIISTAT);
1487
1488 if ((val & PCS_MIISTAT_LS) != 0) {
1489 gp->lstate = link_up;
1490 netif_carrier_on(gp->dev);
1491 (void)gem_set_link_modes(gp);
1492 }
1493 goto restart;
1494 }
1495 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1496 /* Ok, here we got a link. If we had it due to a forced
1497 * fallback, and we were configured for autoneg, we do
1498 * retry a short autoneg pass. If you know your hub is
1499 * broken, use ethtool ;)
1500 */
1501 if (gp->lstate == link_force_try && gp->want_autoneg) {
1502 gp->lstate = link_force_ret;
1503 gp->last_forced_speed = gp->phy_mii.speed;
1504 gp->timer_ticks = 5;
1505 if (netif_msg_link(gp))
1506 printk(KERN_INFO "%s: Got link after fallback, retrying"
1507 " autoneg once...\n", gp->dev->name);
1508 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1509 } else if (gp->lstate != link_up) {
1510 gp->lstate = link_up;
1511 netif_carrier_on(gp->dev);
1512 if (gem_set_link_modes(gp))
1513 restart_aneg = 1;
1514 }
1515 } else {
1516 /* If the link was previously up, we restart the
1517 * whole process
1518 */
1519 if (gp->lstate == link_up) {
1520 gp->lstate = link_down;
1521 if (netif_msg_link(gp))
1522 printk(KERN_INFO "%s: Link down\n",
1523 gp->dev->name);
1524 netif_carrier_off(gp->dev);
1525 gp->reset_task_pending = 1;
1526 schedule_work(&gp->reset_task);
1527 restart_aneg = 1;
1528 } else if (++gp->timer_ticks > 10) {
1529 if (found_mii_phy(gp))
1530 restart_aneg = gem_mdio_link_not_up(gp);
1531 else
1532 restart_aneg = 1;
1533 }
1534 }
1535 if (restart_aneg) {
1536 gem_begin_auto_negotiation(gp, NULL);
1537 goto out_unlock;
1538 }
1539restart:
1540 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1541out_unlock:
1542 gem_put_cell(gp);
1543 spin_unlock(&gp->tx_lock);
1544 spin_unlock_irq(&gp->lock);
1545}
1546
1547/* Must be invoked under gp->lock and gp->tx_lock. */
1548static void gem_clean_rings(struct gem *gp)
1549{
1550 struct gem_init_block *gb = gp->init_block;
1551 struct sk_buff *skb;
1552 int i;
1553 dma_addr_t dma_addr;
1554
1555 for (i = 0; i < RX_RING_SIZE; i++) {
1556 struct gem_rxd *rxd;
1557
1558 rxd = &gb->rxd[i];
1559 if (gp->rx_skbs[i] != NULL) {
1560 skb = gp->rx_skbs[i];
1561 dma_addr = le64_to_cpu(rxd->buffer);
1562 pci_unmap_page(gp->pdev, dma_addr,
1563 RX_BUF_ALLOC_SIZE(gp),
1564 PCI_DMA_FROMDEVICE);
1565 dev_kfree_skb_any(skb);
1566 gp->rx_skbs[i] = NULL;
1567 }
1568 rxd->status_word = 0;
1569 wmb();
1570 rxd->buffer = 0;
1571 }
1572
1573 for (i = 0; i < TX_RING_SIZE; i++) {
1574 if (gp->tx_skbs[i] != NULL) {
1575 struct gem_txd *txd;
1576 int frag;
1577
1578 skb = gp->tx_skbs[i];
1579 gp->tx_skbs[i] = NULL;
1580
1581 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1582 int ent = i & (TX_RING_SIZE - 1);
1583
1584 txd = &gb->txd[ent];
1585 dma_addr = le64_to_cpu(txd->buffer);
1586 pci_unmap_page(gp->pdev, dma_addr,
1587 le64_to_cpu(txd->control_word) &
1588 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1589
1590 if (frag != skb_shinfo(skb)->nr_frags)
1591 i++;
1592 }
1593 dev_kfree_skb_any(skb);
1594 }
1595 }
1596}
1597
1598/* Must be invoked under gp->lock and gp->tx_lock. */
1599static void gem_init_rings(struct gem *gp)
1600{
1601 struct gem_init_block *gb = gp->init_block;
1602 struct net_device *dev = gp->dev;
1603 int i;
1604 dma_addr_t dma_addr;
1605
1606 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1607
1608 gem_clean_rings(gp);
1609
1610 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1611 (unsigned)VLAN_ETH_FRAME_LEN);
1612
1613 for (i = 0; i < RX_RING_SIZE; i++) {
1614 struct sk_buff *skb;
1615 struct gem_rxd *rxd = &gb->rxd[i];
1616
1617 skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
1618 if (!skb) {
1619 rxd->buffer = 0;
1620 rxd->status_word = 0;
1621 continue;
1622 }
1623
1624 gp->rx_skbs[i] = skb;
1625 skb->dev = dev;
1626 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1627 dma_addr = pci_map_page(gp->pdev,
1628 virt_to_page(skb->data),
1629 offset_in_page(skb->data),
1630 RX_BUF_ALLOC_SIZE(gp),
1631 PCI_DMA_FROMDEVICE);
1632 rxd->buffer = cpu_to_le64(dma_addr);
1633 wmb();
1634 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1635 skb_reserve(skb, RX_OFFSET);
1636 }
1637
1638 for (i = 0; i < TX_RING_SIZE; i++) {
1639 struct gem_txd *txd = &gb->txd[i];
1640
1641 txd->control_word = 0;
1642 wmb();
1643 txd->buffer = 0;
1644 }
1645 wmb();
1646}
1647
1648/* Init PHY interface and start link poll state machine */
1649static void gem_init_phy(struct gem *gp)
1650{
7fb76aa0 1651 u32 mifcfg;
1da177e4
LT		 1652
1653 /* Revert MIF CFG setting done on stop_phy */
7fb76aa0
DM		 1654 mifcfg = readl(gp->regs + MIF_CFG);
1655 mifcfg &= ~MIF_CFG_BBMODE;
1656 writel(mifcfg, gp->regs + MIF_CFG);
6aa20a22 1657
1da177e4
LT		 1658 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1659 int i;
1660
7fb76aa0
DM		 1661 /* Those delay sucks, the HW seem to love them though, I'll
1662 * serisouly consider breaking some locks here to be able
1663 * to schedule instead
1664 */
1665 for (i = 0; i < 3; i++) {
1da177e4 1666#ifdef CONFIG_PPC_PMAC
7fb76aa0
DM		 1667 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1668 msleep(20);
1da177e4 1669#endif
7fb76aa0
DM		 1670 /* Some PHYs used by apple have problem getting back to us,
1671 * we do an additional reset here
1672 */
1673 phy_write(gp, MII_BMCR, BMCR_RESET);
1674 msleep(20);
1675 if (phy_read(gp, MII_BMCR) != 0xffff)
1da177e4 1676 break;
7fb76aa0
DM		 1677 if (i == 2)
1678 printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
1679 gp->dev->name);
1da177e4
LT		 1680 }
1681 }
1682
1683 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1684 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1685 u32 val;
1686
1687 /* Init datapath mode register. */
1688 if (gp->phy_type == phy_mii_mdio0 ||
1689 gp->phy_type == phy_mii_mdio1) {
1690 val = PCS_DMODE_MGM;
1691 } else if (gp->phy_type == phy_serialink) {
1692 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1693 } else {
1694 val = PCS_DMODE_ESM;
1695 }
1696
1697 writel(val, gp->regs + PCS_DMODE);
1698 }
1699
1700 if (gp->phy_type == phy_mii_mdio0 ||
1701 gp->phy_type == phy_mii_mdio1) {
1702 // XXX check for errors
1703 mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1704
1705 /* Init PHY */
1706 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1707 gp->phy_mii.def->ops->init(&gp->phy_mii);
1708 } else {
1709 u32 val;
1710 int limit;
1711
1712 /* Reset PCS unit. */
1713 val = readl(gp->regs + PCS_MIICTRL);
1714 val |= PCS_MIICTRL_RST;
1715 writeb(val, gp->regs + PCS_MIICTRL);
1716
1717 limit = 32;
1718 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1719 udelay(100);
1720 if (limit-- <= 0)
1721 break;
1722 }
1723 if (limit <= 0)
1724 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1725 gp->dev->name);
1726
1727 /* Make sure PCS is disabled while changing advertisement
1728 * configuration.
1729 */
1730 val = readl(gp->regs + PCS_CFG);
1731 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1732 writel(val, gp->regs + PCS_CFG);
1733
1734 /* Advertise all capabilities except assymetric
1735 * pause.
1736 */
1737 val = readl(gp->regs + PCS_MIIADV);
1738 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1739 PCS_MIIADV_SP | PCS_MIIADV_AP);
1740 writel(val, gp->regs + PCS_MIIADV);
1741
1742 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1743 * and re-enable PCS.
1744 */
1745 val = readl(gp->regs + PCS_MIICTRL);
1746 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1747 val &= ~PCS_MIICTRL_WB;
1748 writel(val, gp->regs + PCS_MIICTRL);
1749
1750 val = readl(gp->regs + PCS_CFG);
1751 val |= PCS_CFG_ENABLE;
1752 writel(val, gp->regs + PCS_CFG);
1753
1754 /* Make sure serialink loopback is off. The meaning
1755 * of this bit is logically inverted based upon whether
1756 * you are in Serialink or SERDES mode.
1757 */
1758 val = readl(gp->regs + PCS_SCTRL);
1759 if (gp->phy_type == phy_serialink)
1760 val &= ~PCS_SCTRL_LOOP;
1761 else
1762 val |= PCS_SCTRL_LOOP;
1763 writel(val, gp->regs + PCS_SCTRL);
1764 }
1765
1766 /* Default aneg parameters */
1767 gp->timer_ticks = 0;
1768 gp->lstate = link_down;
1769 netif_carrier_off(gp->dev);
1770
1771 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
1772 spin_lock_irq(&gp->lock);
1773 gem_begin_auto_negotiation(gp, NULL);
1774 spin_unlock_irq(&gp->lock);
1775}
1776
1777/* Must be invoked under gp->lock and gp->tx_lock. */
1778static void gem_init_dma(struct gem *gp)
1779{
1780 u64 desc_dma = (u64) gp->gblock_dvma;
1781 u32 val;
1782
1783 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1784 writel(val, gp->regs + TXDMA_CFG);
1785
1786 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1787 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1788 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1789
1790 writel(0, gp->regs + TXDMA_KICK);
1791
1792 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1793 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1794 writel(val, gp->regs + RXDMA_CFG);
1795
1796 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1797 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1798
1799 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1800
1801 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1802 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1803 writel(val, gp->regs + RXDMA_PTHRESH);
1804
1805 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1806 writel(((5 & RXDMA_BLANK_IPKTS) |
1807 ((8 << 12) & RXDMA_BLANK_ITIME)),
1808 gp->regs + RXDMA_BLANK);
1809 else
1810 writel(((5 & RXDMA_BLANK_IPKTS) |
1811 ((4 << 12) & RXDMA_BLANK_ITIME)),
1812 gp->regs + RXDMA_BLANK);
1813}
1814
1815/* Must be invoked under gp->lock and gp->tx_lock. */
1816static u32 gem_setup_multicast(struct gem *gp)
1817{
1818 u32 rxcfg = 0;
1819 int i;
6aa20a22 1820
1da177e4
LT		 1821 if ((gp->dev->flags & IFF_ALLMULTI) ||
1822 (gp->dev->mc_count > 256)) {
1823 for (i=0; i<16; i++)
1824 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1825 rxcfg |= MAC_RXCFG_HFE;
1826 } else if (gp->dev->flags & IFF_PROMISC) {
1827 rxcfg |= MAC_RXCFG_PROM;
1828 } else {
1829 u16 hash_table[16];
1830 u32 crc;
1831 struct dev_mc_list *dmi = gp->dev->mc_list;
1832 int i;
1833
1834 for (i = 0; i < 16; i++)
1835 hash_table[i] = 0;
1836
1837 for (i = 0; i < gp->dev->mc_count; i++) {
1838 char *addrs = dmi->dmi_addr;
1839
1840 dmi = dmi->next;
1841
1842 if (!(*addrs & 1))
1843 continue;
1844
1845 crc = ether_crc_le(6, addrs);
1846 crc >>= 24;
1847 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1848 }
1849 for (i=0; i<16; i++)
1850 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1851 rxcfg |= MAC_RXCFG_HFE;
1852 }
1853
1854 return rxcfg;
1855}
1856
1857/* Must be invoked under gp->lock and gp->tx_lock. */
1858static void gem_init_mac(struct gem *gp)
1859{
1860 unsigned char *e = &gp->dev->dev_addr[0];
1861
1862 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1863
1864 writel(0x00, gp->regs + MAC_IPG0);
1865 writel(0x08, gp->regs + MAC_IPG1);
1866 writel(0x04, gp->regs + MAC_IPG2);
1867 writel(0x40, gp->regs + MAC_STIME);
1868 writel(0x40, gp->regs + MAC_MINFSZ);
1869
1870 /* Ethernet payload + header + FCS + optional VLAN tag. */
1871 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1872
1873 writel(0x07, gp->regs + MAC_PASIZE);
1874 writel(0x04, gp->regs + MAC_JAMSIZE);
1875 writel(0x10, gp->regs + MAC_ATTLIM);
1876 writel(0x8808, gp->regs + MAC_MCTYPE);
1877
1878 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1879
1880 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1881 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1882 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1883
1884 writel(0, gp->regs + MAC_ADDR3);
1885 writel(0, gp->regs + MAC_ADDR4);
1886 writel(0, gp->regs + MAC_ADDR5);
1887
1888 writel(0x0001, gp->regs + MAC_ADDR6);
1889 writel(0xc200, gp->regs + MAC_ADDR7);
1890 writel(0x0180, gp->regs + MAC_ADDR8);
1891
1892 writel(0, gp->regs + MAC_AFILT0);
1893 writel(0, gp->regs + MAC_AFILT1);
1894 writel(0, gp->regs + MAC_AFILT2);
1895 writel(0, gp->regs + MAC_AF21MSK);
1896 writel(0, gp->regs + MAC_AF0MSK);
1897
1898 gp->mac_rx_cfg = gem_setup_multicast(gp);
1899#ifdef STRIP_FCS
1900 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1901#endif
1902 writel(0, gp->regs + MAC_NCOLL);
1903 writel(0, gp->regs + MAC_FASUCC);
1904 writel(0, gp->regs + MAC_ECOLL);
1905 writel(0, gp->regs + MAC_LCOLL);
1906 writel(0, gp->regs + MAC_DTIMER);
1907 writel(0, gp->regs + MAC_PATMPS);
1908 writel(0, gp->regs + MAC_RFCTR);
1909 writel(0, gp->regs + MAC_LERR);
1910 writel(0, gp->regs + MAC_AERR);
1911 writel(0, gp->regs + MAC_FCSERR);
1912 writel(0, gp->regs + MAC_RXCVERR);
1913
1914 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1915 * them once a link is established.
1916 */
1917 writel(0, gp->regs + MAC_TXCFG);
1918 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1919 writel(0, gp->regs + MAC_MCCFG);
1920 writel(0, gp->regs + MAC_XIFCFG);
1921
1922 /* Setup MAC interrupts. We want to get all of the interesting
1923 * counter expiration events, but we do not want to hear about
1924 * normal rx/tx as the DMA engine tells us that.
1925 */
1926 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1927 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1928
1929 /* Don't enable even the PAUSE interrupts for now, we
1930 * make no use of those events other than to record them.
1931 */
1932 writel(0xffffffff, gp->regs + MAC_MCMASK);
1933
1934 /* Don't enable GEM's WOL in normal operations
1935 */
1936 if (gp->has_wol)
1937 writel(0, gp->regs + WOL_WAKECSR);
1938}
1939
1940/* Must be invoked under gp->lock and gp->tx_lock. */
1941static void gem_init_pause_thresholds(struct gem *gp)
1942{
1943 u32 cfg;
1944
1945 /* Calculate pause thresholds. Setting the OFF threshold to the
1946 * full RX fifo size effectively disables PAUSE generation which
1947 * is what we do for 10/100 only GEMs which have FIFOs too small
1948 * to make real gains from PAUSE.
1949 */
1950 if (gp->rx_fifo_sz <= (2 * 1024)) {
1951 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1952 } else {
1953 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1954 int off = (gp->rx_fifo_sz - (max_frame * 2));
1955 int on = off - max_frame;
1956
1957 gp->rx_pause_off = off;
1958 gp->rx_pause_on = on;
1959 }
1960
1961
1962 /* Configure the chip "burst" DMA mode & enable some
1963 * HW bug fixes on Apple version
1964 */
1965 cfg = 0;
1966 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1967 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1968#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1969 cfg |= GREG_CFG_IBURST;
1970#endif
1971 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1972 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1973 writel(cfg, gp->regs + GREG_CFG);
1974
1975 /* If Infinite Burst didn't stick, then use different
1976 * thresholds (and Apple bug fixes don't exist)
1977 */
1978 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1979 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1980 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1981 writel(cfg, gp->regs + GREG_CFG);
6aa20a22 1982 }
1da177e4
LT		 1983}
1984
1985static int gem_check_invariants(struct gem *gp)
1986{
1987 struct pci_dev *pdev = gp->pdev;
1988 u32 mif_cfg;
1989
1990 /* On Apple's sungem, we can't rely on registers as the chip
1991 * was been powered down by the firmware. The PHY is looked
1992 * up later on.
1993 */
1994 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1995 gp->phy_type = phy_mii_mdio0;
1996 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1997 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1998 gp->swrst_base = 0;
1999
2000 mif_cfg = readl(gp->regs + MIF_CFG);
2001 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
2002 mif_cfg |= MIF_CFG_MDI0;
2003 writel(mif_cfg, gp->regs + MIF_CFG);
2004 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
2005 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
2006
2007 /* We hard-code the PHY address so we can properly bring it out of
2008 * reset later on, we can't really probe it at this point, though
2009 * that isn't an issue.
2010 */
2011 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
2012 gp->mii_phy_addr = 1;
2013 else
2014 gp->mii_phy_addr = 0;
2015
2016 return 0;
2017 }
2018
2019 mif_cfg = readl(gp->regs + MIF_CFG);
2020
2021 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2022 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
2023 /* One of the MII PHYs _must_ be present
2024 * as this chip has no gigabit PHY.
2025 */
2026 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
2027 printk(KERN_ERR PFX "RIO GEM lacks MII phy, mif_cfg[%08x]\n",
2028 mif_cfg);
2029 return -1;
2030 }
2031 }
2032
2033 /* Determine initial PHY interface type guess. MDIO1 is the
2034 * external PHY and thus takes precedence over MDIO0.
2035 */
6aa20a22 2036
1da177e4
LT		 2037 if (mif_cfg & MIF_CFG_MDI1) {
2038 gp->phy_type = phy_mii_mdio1;
2039 mif_cfg |= MIF_CFG_PSELECT;
2040 writel(mif_cfg, gp->regs + MIF_CFG);
2041 } else if (mif_cfg & MIF_CFG_MDI0) {
2042 gp->phy_type = phy_mii_mdio0;
2043 mif_cfg &= ~MIF_CFG_PSELECT;
2044 writel(mif_cfg, gp->regs + MIF_CFG);
2045 } else {
2046 gp->phy_type = phy_serialink;
2047 }
2048 if (gp->phy_type == phy_mii_mdio1 ||
2049 gp->phy_type == phy_mii_mdio0) {
2050 int i;
2051
2052 for (i = 0; i < 32; i++) {
2053 gp->mii_phy_addr = i;
2054 if (phy_read(gp, MII_BMCR) != 0xffff)
2055 break;
2056 }
2057 if (i == 32) {
2058 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2059 printk(KERN_ERR PFX "RIO MII phy will not respond.\n");
2060 return -1;
2061 }
2062 gp->phy_type = phy_serdes;
2063 }
2064 }
2065
2066 /* Fetch the FIFO configurations now too. */
2067 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2068 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2069
2070 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2071 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2072 if (gp->tx_fifo_sz != (9 * 1024) ||
2073 gp->rx_fifo_sz != (20 * 1024)) {
2074 printk(KERN_ERR PFX "GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2075 gp->tx_fifo_sz, gp->rx_fifo_sz);
2076 return -1;
2077 }
2078 gp->swrst_base = 0;
2079 } else {
2080 if (gp->tx_fifo_sz != (2 * 1024) ||
2081 gp->rx_fifo_sz != (2 * 1024)) {
2082 printk(KERN_ERR PFX "RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2083 gp->tx_fifo_sz, gp->rx_fifo_sz);
2084 return -1;
2085 }
2086 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2087 }
2088 }
2089
2090 return 0;
2091}
2092
2093/* Must be invoked under gp->lock and gp->tx_lock. */
2094static void gem_reinit_chip(struct gem *gp)
2095{
2096 /* Reset the chip */
2097 gem_reset(gp);
2098
2099 /* Make sure ints are disabled */
2100 gem_disable_ints(gp);
2101
2102 /* Allocate & setup ring buffers */
2103 gem_init_rings(gp);
2104
2105 /* Configure pause thresholds */
2106 gem_init_pause_thresholds(gp);
2107
2108 /* Init DMA & MAC engines */
2109 gem_init_dma(gp);
2110 gem_init_mac(gp);
2111}
2112
2113
2114/* Must be invoked with no lock held. */
2115static void gem_stop_phy(struct gem *gp, int wol)
2116{
7fb76aa0 2117 u32 mifcfg;
1da177e4
LT		 2118 unsigned long flags;
2119
2120 /* Let the chip settle down a bit, it seems that helps
2121 * for sleep mode on some models
2122 */
2123 msleep(10);
2124
2125 /* Make sure we aren't polling PHY status change. We
2126 * don't currently use that feature though
2127 */
7fb76aa0
DM		 2128 mifcfg = readl(gp->regs + MIF_CFG);
2129 mifcfg &= ~MIF_CFG_POLL;
2130 writel(mifcfg, gp->regs + MIF_CFG);
1da177e4
LT		 2131
2132 if (wol && gp->has_wol) {
2133 unsigned char *e = &gp->dev->dev_addr[0];
2134 u32 csr;
2135
2136 /* Setup wake-on-lan for MAGIC packet */
2137 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
6aa20a22 2138 gp->regs + MAC_RXCFG);
1da177e4
LT		 2139 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2140 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2141 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2142
2143 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2144 csr = WOL_WAKECSR_ENABLE;
2145 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2146 csr |= WOL_WAKECSR_MII;
2147 writel(csr, gp->regs + WOL_WAKECSR);
2148 } else {
2149 writel(0, gp->regs + MAC_RXCFG);
2150 (void)readl(gp->regs + MAC_RXCFG);
2151 /* Machine sleep will die in strange ways if we
2152 * dont wait a bit here, looks like the chip takes
2153 * some time to really shut down
2154 */
2155 msleep(10);
2156 }
2157
2158 writel(0, gp->regs + MAC_TXCFG);
2159 writel(0, gp->regs + MAC_XIFCFG);
2160 writel(0, gp->regs + TXDMA_CFG);
2161 writel(0, gp->regs + RXDMA_CFG);
2162
2163 if (!wol) {
2164 spin_lock_irqsave(&gp->lock, flags);
2165 spin_lock(&gp->tx_lock);
2166 gem_reset(gp);
2167 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2168 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2169 spin_unlock(&gp->tx_lock);
2170 spin_unlock_irqrestore(&gp->lock, flags);
2171
2172 /* No need to take the lock here */
2173
2174 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2175 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2176
2177 /* According to Apple, we must set the MDIO pins to this begnign
2178 * state or we may 1) eat more current, 2) damage some PHYs
2179 */
7fb76aa0 2180 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
1da177e4
LT		 2181 writel(0, gp->regs + MIF_BBCLK);
2182 writel(0, gp->regs + MIF_BBDATA);
2183 writel(0, gp->regs + MIF_BBOENAB);
2184 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2185 (void) readl(gp->regs + MAC_XIFCFG);
2186 }
2187}
2188
2189
2190static int gem_do_start(struct net_device *dev)
2191{
2192 struct gem *gp = dev->priv;
2193 unsigned long flags;
2194
2195 spin_lock_irqsave(&gp->lock, flags);
2196 spin_lock(&gp->tx_lock);
2197
2198 /* Enable the cell */
2199 gem_get_cell(gp);
2200
2201 /* Init & setup chip hardware */
2202 gem_reinit_chip(gp);
2203
2204 gp->running = 1;
2205
2206 if (gp->lstate == link_up) {
2207 netif_carrier_on(gp->dev);
2208 gem_set_link_modes(gp);
2209 }
2210
2211 netif_wake_queue(gp->dev);
2212
2213 spin_unlock(&gp->tx_lock);
2214 spin_unlock_irqrestore(&gp->lock, flags);
2215
2216 if (request_irq(gp->pdev->irq, gem_interrupt,
1fb9df5d 2217 IRQF_SHARED, dev->name, (void *)dev)) {
1da177e4
LT		 2218 printk(KERN_ERR "%s: failed to request irq !\n", gp->dev->name);
2219
2220 spin_lock_irqsave(&gp->lock, flags);
2221 spin_lock(&gp->tx_lock);
2222
2223 gp->running = 0;
2224 gem_reset(gp);
2225 gem_clean_rings(gp);
2226 gem_put_cell(gp);
6aa20a22 2227
1da177e4
LT		 2228 spin_unlock(&gp->tx_lock);
2229 spin_unlock_irqrestore(&gp->lock, flags);
2230
2231 return -EAGAIN;
2232 }
2233
2234 return 0;
2235}
2236
2237static void gem_do_stop(struct net_device *dev, int wol)
2238{
2239 struct gem *gp = dev->priv;
2240 unsigned long flags;
2241
2242 spin_lock_irqsave(&gp->lock, flags);
2243 spin_lock(&gp->tx_lock);
2244
2245 gp->running = 0;
2246
2247 /* Stop netif queue */
2248 netif_stop_queue(dev);
2249
2250 /* Make sure ints are disabled */
2251 gem_disable_ints(gp);
2252
2253 /* We can drop the lock now */
2254 spin_unlock(&gp->tx_lock);
2255 spin_unlock_irqrestore(&gp->lock, flags);
2256
2257 /* If we are going to sleep with WOL */
2258 gem_stop_dma(gp);
2259 msleep(10);
2260 if (!wol)
2261 gem_reset(gp);
2262 msleep(10);
2263
2264 /* Get rid of rings */
2265 gem_clean_rings(gp);
2266
2267 /* No irq needed anymore */
2268 free_irq(gp->pdev->irq, (void *) dev);
2269
2270 /* Cell not needed neither if no WOL */
2271 if (!wol) {
2272 spin_lock_irqsave(&gp->lock, flags);
2273 gem_put_cell(gp);
2274 spin_unlock_irqrestore(&gp->lock, flags);
2275 }
2276}
2277
c4028958 2278static void gem_reset_task(struct work_struct *work)
1da177e4 2279{
c4028958 2280 struct gem *gp = container_of(work, struct gem, reset_task);
1da177e4 2281
e3968fc0 2282 mutex_lock(&gp->pm_mutex);
1da177e4 2283
dde655c9
JB		 2284 if (gp->opened)
2285 napi_disable(&gp->napi);
1da177e4
LT		 2286
2287 spin_lock_irq(&gp->lock);
2288 spin_lock(&gp->tx_lock);
2289
1da177e4
LT		 2290 if (gp->running) {
2291 netif_stop_queue(gp->dev);
2292
2293 /* Reset the chip & rings */
2294 gem_reinit_chip(gp);
2295 if (gp->lstate == link_up)
2296 gem_set_link_modes(gp);
2297 netif_wake_queue(gp->dev);
2298 }
dde655c9 2299
1da177e4
LT		 2300 gp->reset_task_pending = 0;
2301
2302 spin_unlock(&gp->tx_lock);
2303 spin_unlock_irq(&gp->lock);
2304
dde655c9
JB		 2305 if (gp->opened)
2306 napi_enable(&gp->napi);
1da177e4 2307
e3968fc0 2308 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2309}
2310
2311
2312static int gem_open(struct net_device *dev)
2313{
2314 struct gem *gp = dev->priv;
2315 int rc = 0;
2316
e3968fc0 2317 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2318
2319 /* We need the cell enabled */
2320 if (!gp->asleep)
2321 rc = gem_do_start(dev);
2322 gp->opened = (rc == 0);
bea3348e
SH		 2323 if (gp->opened)
2324 napi_enable(&gp->napi);
1da177e4 2325
e3968fc0 2326 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2327
2328 return rc;
2329}
2330
2331static int gem_close(struct net_device *dev)
2332{
2333 struct gem *gp = dev->priv;
2334
e3968fc0 2335 mutex_lock(&gp->pm_mutex);
1da177e4 2336
62768e28
JB		 2337 napi_disable(&gp->napi);
2338
6aa20a22 2339 gp->opened = 0;
1da177e4
LT		 2340 if (!gp->asleep)
2341 gem_do_stop(dev, 0);
2342
e3968fc0 2343 mutex_unlock(&gp->pm_mutex);
6aa20a22 2344
1da177e4
LT		 2345 return 0;
2346}
2347
2348#ifdef CONFIG_PM
2349static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2350{
2351 struct net_device *dev = pci_get_drvdata(pdev);
2352 struct gem *gp = dev->priv;
2353 unsigned long flags;
2354
e3968fc0 2355 mutex_lock(&gp->pm_mutex);
1da177e4 2356
1da177e4
LT		 2357 printk(KERN_INFO "%s: suspending, WakeOnLan %s\n",
2358 dev->name,
2359 (gp->wake_on_lan && gp->opened) ? "enabled" : "disabled");
6aa20a22 2360
1da177e4
LT		 2361 /* Keep the cell enabled during the entire operation */
2362 spin_lock_irqsave(&gp->lock, flags);
2363 spin_lock(&gp->tx_lock);
2364 gem_get_cell(gp);
2365 spin_unlock(&gp->tx_lock);
2366 spin_unlock_irqrestore(&gp->lock, flags);
2367
2368 /* If the driver is opened, we stop the MAC */
2369 if (gp->opened) {
62768e28
JB		 2370 napi_disable(&gp->napi);
2371
1da177e4
LT		 2372 /* Stop traffic, mark us closed */
2373 netif_device_detach(dev);
2374
2375 /* Switch off MAC, remember WOL setting */
2376 gp->asleep_wol = gp->wake_on_lan;
2377 gem_do_stop(dev, gp->asleep_wol);
2378 } else
2379 gp->asleep_wol = 0;
2380
2381 /* Mark us asleep */
2382 gp->asleep = 1;
2383 wmb();
2384
2385 /* Stop the link timer */
2386 del_timer_sync(&gp->link_timer);
2387
e3968fc0 2388 /* Now we release the mutex to not block the reset task who
1da177e4
LT		 2389 * can take it too. We are marked asleep, so there will be no
2390 * conflict here
2391 */
e3968fc0 2392 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2393
2394 /* Wait for a pending reset task to complete */
2395 while (gp->reset_task_pending)
2396 yield();
2397 flush_scheduled_work();
2398
2399 /* Shut the PHY down eventually and setup WOL */
2400 gem_stop_phy(gp, gp->asleep_wol);
2401
2402 /* Make sure bus master is disabled */
2403 pci_disable_device(gp->pdev);
2404
2405 /* Release the cell, no need to take a lock at this point since
2406 * nothing else can happen now
2407 */
2408 gem_put_cell(gp);
2409
2410 return 0;
2411}
2412
2413static int gem_resume(struct pci_dev *pdev)
2414{
2415 struct net_device *dev = pci_get_drvdata(pdev);
2416 struct gem *gp = dev->priv;
2417 unsigned long flags;
2418
2419 printk(KERN_INFO "%s: resuming\n", dev->name);
2420
e3968fc0 2421 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2422
2423 /* Keep the cell enabled during the entire operation, no need to
2424 * take a lock here tho since nothing else can happen while we are
2425 * marked asleep
2426 */
2427 gem_get_cell(gp);
2428
2429 /* Make sure PCI access and bus master are enabled */
2430 if (pci_enable_device(gp->pdev)) {
2431 printk(KERN_ERR "%s: Can't re-enable chip !\n",
2432 dev->name);
2433 /* Put cell and forget it for now, it will be considered as
2434 * still asleep, a new sleep cycle may bring it back
2435 */
2436 gem_put_cell(gp);
e3968fc0 2437 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2438 return 0;
2439 }
2440 pci_set_master(gp->pdev);
2441
2442 /* Reset everything */
2443 gem_reset(gp);
2444
2445 /* Mark us woken up */
2446 gp->asleep = 0;
2447 wmb();
2448
2449 /* Bring the PHY back. Again, lock is useless at this point as
2450 * nothing can be happening until we restart the whole thing
2451 */
2452 gem_init_phy(gp);
2453
2454 /* If we were opened, bring everything back */
2455 if (gp->opened) {
2456 /* Restart MAC */
2457 gem_do_start(dev);
2458
2459 /* Re-attach net device */
2460 netif_device_attach(dev);
2461
62768e28 2462 napi_enable(&gp->napi);
1da177e4
LT		 2463 }
2464
2465 spin_lock_irqsave(&gp->lock, flags);
2466 spin_lock(&gp->tx_lock);
2467
2468 /* If we had WOL enabled, the cell clock was never turned off during
2469 * sleep, so we end up beeing unbalanced. Fix that here
2470 */
2471 if (gp->asleep_wol)
2472 gem_put_cell(gp);
2473
2474 /* This function doesn't need to hold the cell, it will be held if the
2475 * driver is open by gem_do_start().
2476 */
2477 gem_put_cell(gp);
2478
2479 spin_unlock(&gp->tx_lock);
2480 spin_unlock_irqrestore(&gp->lock, flags);
2481
e3968fc0 2482 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2483
2484 return 0;
2485}
2486#endif /* CONFIG_PM */
2487
2488static struct net_device_stats *gem_get_stats(struct net_device *dev)
2489{
2490 struct gem *gp = dev->priv;
2491 struct net_device_stats *stats = &gp->net_stats;
2492
2493 spin_lock_irq(&gp->lock);
2494 spin_lock(&gp->tx_lock);
2495
2496 /* I have seen this being called while the PM was in progress,
2497 * so we shield against this
2498 */
2499 if (gp->running) {
2500 stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2501 writel(0, gp->regs + MAC_FCSERR);
2502
2503 stats->rx_frame_errors += readl(gp->regs + MAC_AERR);
2504 writel(0, gp->regs + MAC_AERR);
2505
2506 stats->rx_length_errors += readl(gp->regs + MAC_LERR);
2507 writel(0, gp->regs + MAC_LERR);
2508
2509 stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2510 stats->collisions +=
2511 (readl(gp->regs + MAC_ECOLL) +
2512 readl(gp->regs + MAC_LCOLL));
2513 writel(0, gp->regs + MAC_ECOLL);
2514 writel(0, gp->regs + MAC_LCOLL);
2515 }
2516
2517 spin_unlock(&gp->tx_lock);
2518 spin_unlock_irq(&gp->lock);
2519
2520 return &gp->net_stats;
2521}
2522
09c72ec8
RV		 2523static int gem_set_mac_address(struct net_device *dev, void *addr)
2524{
2525 struct sockaddr *macaddr = (struct sockaddr *) addr;
2526 struct gem *gp = dev->priv;
2527 unsigned char *e = &dev->dev_addr[0];
2528
2529 if (!is_valid_ether_addr(macaddr->sa_data))
2530 return -EADDRNOTAVAIL;
2531
2532 if (!netif_running(dev) || !netif_device_present(dev)) {
2533 /* We'll just catch it later when the
2534 * device is up'd or resumed.
2535 */
2536 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2537 return 0;
2538 }
2539
2540 mutex_lock(&gp->pm_mutex);
2541 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2542 if (gp->running) {
2543 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2544 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2545 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2546 }
2547 mutex_unlock(&gp->pm_mutex);
2548
2549 return 0;
2550}
2551
1da177e4
LT		 2552static void gem_set_multicast(struct net_device *dev)
2553{
2554 struct gem *gp = dev->priv;
2555 u32 rxcfg, rxcfg_new;
2556 int limit = 10000;
6aa20a22 2557
1da177e4
LT		 2558
2559 spin_lock_irq(&gp->lock);
2560 spin_lock(&gp->tx_lock);
2561
2562 if (!gp->running)
2563 goto bail;
2564
2565 netif_stop_queue(dev);
2566
2567 rxcfg = readl(gp->regs + MAC_RXCFG);
2568 rxcfg_new = gem_setup_multicast(gp);
2569#ifdef STRIP_FCS
2570 rxcfg_new |= MAC_RXCFG_SFCS;
2571#endif
2572 gp->mac_rx_cfg = rxcfg_new;
6aa20a22 2573
1da177e4
LT		 2574 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2575 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2576 if (!limit--)
2577 break;
2578 udelay(10);
2579 }
2580
2581 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2582 rxcfg |= rxcfg_new;
2583
2584 writel(rxcfg, gp->regs + MAC_RXCFG);
2585
2586 netif_wake_queue(dev);
2587
2588 bail:
2589 spin_unlock(&gp->tx_lock);
2590 spin_unlock_irq(&gp->lock);
2591}
2592
2593/* Jumbo-grams don't seem to work :-( */
2594#define GEM_MIN_MTU 68
2595#if 1
2596#define GEM_MAX_MTU 1500
2597#else
2598#define GEM_MAX_MTU 9000
2599#endif
2600
2601static int gem_change_mtu(struct net_device *dev, int new_mtu)
2602{
2603 struct gem *gp = dev->priv;
2604
2605 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
2606 return -EINVAL;
2607
2608 if (!netif_running(dev) || !netif_device_present(dev)) {
2609 /* We'll just catch it later when the
2610 * device is up'd or resumed.
2611 */
2612 dev->mtu = new_mtu;
2613 return 0;
2614 }
2615
e3968fc0 2616 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2617 spin_lock_irq(&gp->lock);
2618 spin_lock(&gp->tx_lock);
2619 dev->mtu = new_mtu;
2620 if (gp->running) {
2621 gem_reinit_chip(gp);
2622 if (gp->lstate == link_up)
2623 gem_set_link_modes(gp);
2624 }
2625 spin_unlock(&gp->tx_lock);
2626 spin_unlock_irq(&gp->lock);
e3968fc0 2627 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2628
2629 return 0;
2630}
2631
2632static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2633{
2634 struct gem *gp = dev->priv;
6aa20a22 2635
1da177e4
LT		 2636 strcpy(info->driver, DRV_NAME);
2637 strcpy(info->version, DRV_VERSION);
2638 strcpy(info->bus_info, pci_name(gp->pdev));
2639}
6aa20a22 2640
1da177e4
LT		 2641static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2642{
2643 struct gem *gp = dev->priv;
2644
2645 if (gp->phy_type == phy_mii_mdio0 ||
2646 gp->phy_type == phy_mii_mdio1) {
2647 if (gp->phy_mii.def)
2648 cmd->supported = gp->phy_mii.def->features;
2649 else
2650 cmd->supported = (SUPPORTED_10baseT_Half |
2651 SUPPORTED_10baseT_Full);
2652
2653 /* XXX hardcoded stuff for now */
2654 cmd->port = PORT_MII;
2655 cmd->transceiver = XCVR_EXTERNAL;
2656 cmd->phy_address = 0; /* XXX fixed PHYAD */
2657
2658 /* Return current PHY settings */
2659 spin_lock_irq(&gp->lock);
2660 cmd->autoneg = gp->want_autoneg;
2661 cmd->speed = gp->phy_mii.speed;
6aa20a22 2662 cmd->duplex = gp->phy_mii.duplex;
1da177e4
LT		 2663 cmd->advertising = gp->phy_mii.advertising;
2664
2665 /* If we started with a forced mode, we don't have a default
2666 * advertise set, we need to return something sensible so
2667 * userland can re-enable autoneg properly.
2668 */
2669 if (cmd->advertising == 0)
2670 cmd->advertising = cmd->supported;
2671 spin_unlock_irq(&gp->lock);
2672 } else { // XXX PCS ?
2673 cmd->supported =
2674 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2675 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2676 SUPPORTED_Autoneg);
2677 cmd->advertising = cmd->supported;
2678 cmd->speed = 0;
2679 cmd->duplex = cmd->port = cmd->phy_address =
2680 cmd->transceiver = cmd->autoneg = 0;
2681 }
2682 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2683
2684 return 0;
2685}
2686
2687static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2688{
2689 struct gem *gp = dev->priv;
2690
2691 /* Verify the settings we care about. */
2692 if (cmd->autoneg != AUTONEG_ENABLE &&
2693 cmd->autoneg != AUTONEG_DISABLE)
2694 return -EINVAL;
2695
2696 if (cmd->autoneg == AUTONEG_ENABLE &&
2697 cmd->advertising == 0)
2698 return -EINVAL;
2699
2700 if (cmd->autoneg == AUTONEG_DISABLE &&
2701 ((cmd->speed != SPEED_1000 &&
2702 cmd->speed != SPEED_100 &&
2703 cmd->speed != SPEED_10) ||
2704 (cmd->duplex != DUPLEX_HALF &&
2705 cmd->duplex != DUPLEX_FULL)))
2706 return -EINVAL;
6aa20a22 2707
1da177e4
LT		 2708 /* Apply settings and restart link process. */
2709 spin_lock_irq(&gp->lock);
2710 gem_get_cell(gp);
2711 gem_begin_auto_negotiation(gp, cmd);
2712 gem_put_cell(gp);
2713 spin_unlock_irq(&gp->lock);
2714
2715 return 0;
2716}
2717
2718static int gem_nway_reset(struct net_device *dev)
2719{
2720 struct gem *gp = dev->priv;
2721
2722 if (!gp->want_autoneg)
2723 return -EINVAL;
2724
2725 /* Restart link process. */
2726 spin_lock_irq(&gp->lock);
2727 gem_get_cell(gp);
2728 gem_begin_auto_negotiation(gp, NULL);
2729 gem_put_cell(gp);
2730 spin_unlock_irq(&gp->lock);
2731
2732 return 0;
2733}
2734
2735static u32 gem_get_msglevel(struct net_device *dev)
2736{
2737 struct gem *gp = dev->priv;
2738 return gp->msg_enable;
2739}
6aa20a22 2740
1da177e4
LT		 2741static void gem_set_msglevel(struct net_device *dev, u32 value)
2742{
2743 struct gem *gp = dev->priv;
2744 gp->msg_enable = value;
2745}
2746
2747
2748/* Add more when I understand how to program the chip */
2749/* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2750
2751#define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2752
2753static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2754{
2755 struct gem *gp = dev->priv;
2756
2757 /* Add more when I understand how to program the chip */
2758 if (gp->has_wol) {
2759 wol->supported = WOL_SUPPORTED_MASK;
2760 wol->wolopts = gp->wake_on_lan;
2761 } else {
2762 wol->supported = 0;
2763 wol->wolopts = 0;
2764 }
2765}
2766
2767static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2768{
2769 struct gem *gp = dev->priv;
2770
2771 if (!gp->has_wol)
2772 return -EOPNOTSUPP;
2773 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2774 return 0;
2775}
2776
7282d491 2777static const struct ethtool_ops gem_ethtool_ops = {
1da177e4
LT		 2778 .get_drvinfo = gem_get_drvinfo,
2779 .get_link = ethtool_op_get_link,
2780 .get_settings = gem_get_settings,
2781 .set_settings = gem_set_settings,
2782 .nway_reset = gem_nway_reset,
2783 .get_msglevel = gem_get_msglevel,
2784 .set_msglevel = gem_set_msglevel,
2785 .get_wol = gem_get_wol,
2786 .set_wol = gem_set_wol,
2787};
2788
2789static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2790{
2791 struct gem *gp = dev->priv;
2792 struct mii_ioctl_data *data = if_mii(ifr);
2793 int rc = -EOPNOTSUPP;
2794 unsigned long flags;
2795
e3968fc0 2796 /* Hold the PM mutex while doing ioctl's or we may collide
1da177e4
LT		 2797 * with power management.
2798 */
e3968fc0 2799 mutex_lock(&gp->pm_mutex);
6aa20a22 2800
1da177e4
LT		 2801 spin_lock_irqsave(&gp->lock, flags);
2802 gem_get_cell(gp);
2803 spin_unlock_irqrestore(&gp->lock, flags);
2804
2805 switch (cmd) {
2806 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2807 data->phy_id = gp->mii_phy_addr;
2808 /* Fallthrough... */
2809
2810 case SIOCGMIIREG: /* Read MII PHY register. */
2811 if (!gp->running)
2812 rc = -EAGAIN;
2813 else {
2814 data->val_out = __phy_read(gp, data->phy_id & 0x1f,
2815 data->reg_num & 0x1f);
2816 rc = 0;
2817 }
2818 break;
2819
2820 case SIOCSMIIREG: /* Write MII PHY register. */
2821 if (!capable(CAP_NET_ADMIN))
2822 rc = -EPERM;
2823 else if (!gp->running)
2824 rc = -EAGAIN;
2825 else {
2826 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2827 data->val_in);
2828 rc = 0;
2829 }
2830 break;
2831 };
6aa20a22 2832
1da177e4
LT		 2833 spin_lock_irqsave(&gp->lock, flags);
2834 gem_put_cell(gp);
2835 spin_unlock_irqrestore(&gp->lock, flags);
2836
e3968fc0 2837 mutex_unlock(&gp->pm_mutex);
6aa20a22 2838
1da177e4
LT		 2839 return rc;
2840}
2841
dadb830d 2842#if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
1da177e4 2843/* Fetch MAC address from vital product data of PCI ROM. */
4120b028 2844static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
1da177e4
LT		 2845{
2846 int this_offset;
2847
2848 for (this_offset = 0x20; this_offset < len; this_offset++) {
2849 void __iomem *p = rom_base + this_offset;
2850 int i;
2851
2852 if (readb(p + 0) != 0x90 ||
2853 readb(p + 1) != 0x00 ||
2854 readb(p + 2) != 0x09 ||
2855 readb(p + 3) != 0x4e ||
2856 readb(p + 4) != 0x41 ||
2857 readb(p + 5) != 0x06)
2858 continue;
2859
2860 this_offset += 6;
2861 p += 6;
2862
2863 for (i = 0; i < 6; i++)
2864 dev_addr[i] = readb(p + i);
4120b028 2865 return 1;
1da177e4 2866 }
4120b028 2867 return 0;
1da177e4
LT		 2868}
2869
2870static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2871{
4120b028
LT		 2872 size_t size;
2873 void __iomem *p = pci_map_rom(pdev, &size);
1da177e4 2874
4120b028
LT		 2875 if (p) {
2876 int found;
1da177e4 2877
4120b028
LT		 2878 found = readb(p) == 0x55 &&
2879 readb(p + 1) == 0xaa &&
2880 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2881 pci_unmap_rom(pdev, p);
2882 if (found)
2883 return;
2884 }
1da177e4 2885
1da177e4
LT		 2886 /* Sun MAC prefix then 3 random bytes. */
2887 dev_addr[0] = 0x08;
2888 dev_addr[1] = 0x00;
2889 dev_addr[2] = 0x20;
2890 get_random_bytes(dev_addr + 3, 3);
2891 return;
2892}
2893#endif /* not Sparc and not PPC */
2894
2895static int __devinit gem_get_device_address(struct gem *gp)
2896{
dadb830d 2897#if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
1da177e4 2898 struct net_device *dev = gp->dev;
1a2509c9 2899 const unsigned char *addr;
1da177e4 2900
40cd3a45 2901 addr = of_get_property(gp->of_node, "local-mac-address", NULL);
1da177e4 2902 if (addr == NULL) {
457e1a8a
DM		 2903#ifdef CONFIG_SPARC
2904 addr = idprom->id_ethaddr;
2905#else
1da177e4
LT		 2906 printk("\n");
2907 printk(KERN_ERR "%s: can't get mac-address\n", dev->name);
2908 return -1;
457e1a8a 2909#endif
1da177e4
LT		 2910 }
2911 memcpy(dev->dev_addr, addr, 6);
2912#else
2913 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2914#endif
2915 return 0;
2916}
2917
14904398 2918static void gem_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2919{
2920 struct net_device *dev = pci_get_drvdata(pdev);
2921
2922 if (dev) {
2923 struct gem *gp = dev->priv;
2924
2925 unregister_netdev(dev);
2926
2927 /* Stop the link timer */
2928 del_timer_sync(&gp->link_timer);
2929
2930 /* We shouldn't need any locking here */
2931 gem_get_cell(gp);
2932
2933 /* Wait for a pending reset task to complete */
2934 while (gp->reset_task_pending)
2935 yield();
2936 flush_scheduled_work();
2937
2938 /* Shut the PHY down */
2939 gem_stop_phy(gp, 0);
2940
2941 gem_put_cell(gp);
2942
2943 /* Make sure bus master is disabled */
2944 pci_disable_device(gp->pdev);
2945
2946 /* Free resources */
2947 pci_free_consistent(pdev,
2948 sizeof(struct gem_init_block),
2949 gp->init_block,
2950 gp->gblock_dvma);
2951 iounmap(gp->regs);
2952 pci_release_regions(pdev);
2953 free_netdev(dev);
2954
2955 pci_set_drvdata(pdev, NULL);
2956 }
2957}
2958
2959static int __devinit gem_init_one(struct pci_dev *pdev,
2960 const struct pci_device_id *ent)
2961{
2962 static int gem_version_printed = 0;
2963 unsigned long gemreg_base, gemreg_len;
2964 struct net_device *dev;
2965 struct gem *gp;
0795af57
JP		 2966 int err, pci_using_dac;
2967 DECLARE_MAC_BUF(mac);
1da177e4
LT		 2968
2969 if (gem_version_printed++ == 0)
2970 printk(KERN_INFO "%s", version);
2971
2972 /* Apple gmac note: during probe, the chip is powered up by
2973 * the arch code to allow the code below to work (and to let
2974 * the chip be probed on the config space. It won't stay powered
2975 * up until the interface is brought up however, so we can't rely
2976 * on register configuration done at this point.
2977 */
2978 err = pci_enable_device(pdev);
2979 if (err) {
2980 printk(KERN_ERR PFX "Cannot enable MMIO operation, "
2981 "aborting.\n");
2982 return err;
2983 }
2984 pci_set_master(pdev);
2985
2986 /* Configure DMA attributes. */
2987
2988 /* All of the GEM documentation states that 64-bit DMA addressing
2989 * is fully supported and should work just fine. However the
2990 * front end for RIO based GEMs is different and only supports
2991 * 32-bit addressing.
2992 *
2993 * For now we assume the various PPC GEMs are 32-bit only as well.
2994 */
2995 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2996 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
1e7f0bd8 2997 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 2998 pci_using_dac = 1;
2999 } else {
1e7f0bd8 3000 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4
LT		 3001 if (err) {
3002 printk(KERN_ERR PFX "No usable DMA configuration, "
3003 "aborting.\n");
3004 goto err_disable_device;
3005 }
3006 pci_using_dac = 0;
3007 }
6aa20a22 3008
1da177e4
LT		 3009 gemreg_base = pci_resource_start(pdev, 0);
3010 gemreg_len = pci_resource_len(pdev, 0);
3011
3012 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3013 printk(KERN_ERR PFX "Cannot find proper PCI device "
3014 "base address, aborting.\n");
3015 err = -ENODEV;
3016 goto err_disable_device;
3017 }
3018
3019 dev = alloc_etherdev(sizeof(*gp));
3020 if (!dev) {
3021 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
3022 err = -ENOMEM;
3023 goto err_disable_device;
3024 }
1da177e4
LT		 3025 SET_NETDEV_DEV(dev, &pdev->dev);
3026
3027 gp = dev->priv;
3028
3029 err = pci_request_regions(pdev, DRV_NAME);
3030 if (err) {
3031 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
3032 "aborting.\n");
3033 goto err_out_free_netdev;
3034 }
3035
3036 gp->pdev = pdev;
3037 dev->base_addr = (long) pdev;
3038 gp->dev = dev;
3039
3040 gp->msg_enable = DEFAULT_MSG;
3041
3042 spin_lock_init(&gp->lock);
3043 spin_lock_init(&gp->tx_lock);
e3968fc0 3044 mutex_init(&gp->pm_mutex);
1da177e4
LT		 3045
3046 init_timer(&gp->link_timer);
3047 gp->link_timer.function = gem_link_timer;
3048 gp->link_timer.data = (unsigned long) gp;
3049
c4028958 3050 INIT_WORK(&gp->reset_task, gem_reset_task);
6aa20a22 3051
1da177e4
LT		 3052 gp->lstate = link_down;
3053 gp->timer_ticks = 0;
3054 netif_carrier_off(dev);
3055
3056 gp->regs = ioremap(gemreg_base, gemreg_len);
3057 if (gp->regs == 0UL) {
3058 printk(KERN_ERR PFX "Cannot map device registers, "
3059 "aborting.\n");
3060 err = -EIO;
3061 goto err_out_free_res;
3062 }
3063
3064 /* On Apple, we want a reference to the Open Firmware device-tree
3065 * node. We use it for clock control.
3066 */
457e1a8a 3067#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
1da177e4
LT		 3068 gp->of_node = pci_device_to_OF_node(pdev);
3069#endif
3070
3071 /* Only Apple version supports WOL afaik */
3072 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
3073 gp->has_wol = 1;
3074
3075 /* Make sure cell is enabled */
3076 gem_get_cell(gp);
3077
3078 /* Make sure everything is stopped and in init state */
3079 gem_reset(gp);
3080
3081 /* Fill up the mii_phy structure (even if we won't use it) */
3082 gp->phy_mii.dev = dev;
3083 gp->phy_mii.mdio_read = _phy_read;
3084 gp->phy_mii.mdio_write = _phy_write;
3c326fe9
BH		 3085#ifdef CONFIG_PPC_PMAC
3086 gp->phy_mii.platform_data = gp->of_node;
3087#endif
1da177e4
LT		 3088 /* By default, we start with autoneg */
3089 gp->want_autoneg = 1;
3090
3091 /* Check fifo sizes, PHY type, etc... */
3092 if (gem_check_invariants(gp)) {
3093 err = -ENODEV;
3094 goto err_out_iounmap;
3095 }
3096
3097 /* It is guaranteed that the returned buffer will be at least
3098 * PAGE_SIZE aligned.
3099 */
3100 gp->init_block = (struct gem_init_block *)
3101 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
3102 &gp->gblock_dvma);
3103 if (!gp->init_block) {
3104 printk(KERN_ERR PFX "Cannot allocate init block, "
3105 "aborting.\n");
3106 err = -ENOMEM;
3107 goto err_out_iounmap;
3108 }
3109
3110 if (gem_get_device_address(gp))
3111 goto err_out_free_consistent;
3112
3113 dev->open = gem_open;
3114 dev->stop = gem_close;
3115 dev->hard_start_xmit = gem_start_xmit;
3116 dev->get_stats = gem_get_stats;
3117 dev->set_multicast_list = gem_set_multicast;
3118 dev->do_ioctl = gem_ioctl;
bea3348e 3119 netif_napi_add(dev, &gp->napi, gem_poll, 64);
1da177e4
LT		 3120 dev->ethtool_ops = &gem_ethtool_ops;
3121 dev->tx_timeout = gem_tx_timeout;
3122 dev->watchdog_timeo = 5 * HZ;
3123 dev->change_mtu = gem_change_mtu;
3124 dev->irq = pdev->irq;
3125 dev->dma = 0;
09c72ec8 3126 dev->set_mac_address = gem_set_mac_address;
1da177e4
LT		 3127#ifdef CONFIG_NET_POLL_CONTROLLER
3128 dev->poll_controller = gem_poll_controller;
3129#endif
3130
3131 /* Set that now, in case PM kicks in now */
3132 pci_set_drvdata(pdev, dev);
3133
3134 /* Detect & init PHY, start autoneg, we release the cell now
3135 * too, it will be managed by whoever needs it
3136 */
3137 gem_init_phy(gp);
3138
3139 spin_lock_irq(&gp->lock);
3140 gem_put_cell(gp);
3141 spin_unlock_irq(&gp->lock);
3142
3143 /* Register with kernel */
3144 if (register_netdev(dev)) {
3145 printk(KERN_ERR PFX "Cannot register net device, "
3146 "aborting.\n");
3147 err = -ENOMEM;
3148 goto err_out_free_consistent;
3149 }
3150
0795af57
JP		 3151 printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet "
3152 "%s\n",
3153 dev->name, print_mac(mac, dev->dev_addr));
1da177e4
LT		 3154
3155 if (gp->phy_type == phy_mii_mdio0 ||
3156 gp->phy_type == phy_mii_mdio1)
6aa20a22 3157 printk(KERN_INFO "%s: Found %s PHY\n", dev->name,
1da177e4
LT		 3158 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
3159
3160 /* GEM can do it all... */
3161 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_LLTX;
3162 if (pci_using_dac)
3163 dev->features |= NETIF_F_HIGHDMA;
3164
3165 return 0;
3166
3167err_out_free_consistent:
3168 gem_remove_one(pdev);
3169err_out_iounmap:
3170 gem_put_cell(gp);
3171 iounmap(gp->regs);
3172
3173err_out_free_res:
3174 pci_release_regions(pdev);
3175
3176err_out_free_netdev:
3177 free_netdev(dev);
3178err_disable_device:
3179 pci_disable_device(pdev);
3180 return err;
3181
3182}
3183
3184
3185static struct pci_driver gem_driver = {
3186 .name = GEM_MODULE_NAME,
3187 .id_table = gem_pci_tbl,
3188 .probe = gem_init_one,
14904398 3189 .remove = gem_remove_one,
1da177e4
LT		 3190#ifdef CONFIG_PM
3191 .suspend = gem_suspend,
3192 .resume = gem_resume,
3193#endif /* CONFIG_PM */
3194};
3195
3196static int __init gem_init(void)
3197{
29917620 3198 return pci_register_driver(&gem_driver);
1da177e4
LT		 3199}
3200
3201static void __exit gem_cleanup(void)
3202{
3203 pci_unregister_driver(&gem_driver);
3204}
3205
3206module_init(gem_init);
3207module_exit(gem_cleanup);
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