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1da177e4
LT		 1/* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
6aa20a22 5 *
1da177e4
LT		 6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
9 *
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
6aa20a22
JG		 12 *
13 * TODO:
1da177e4
LT		 14 * - Now that the driver was significantly simplified, I need to rework
15 * the locking. I'm sure we don't need _2_ spinlocks, and we probably
16 * can avoid taking most of them for so long period of time (and schedule
17 * instead). The main issues at this point are caused by the netdev layer
18 * though:
6aa20a22 19 *
1da177e4
LT		 20 * gem_change_mtu() and gem_set_multicast() are called with a read_lock()
21 * help by net/core/dev.c, thus they can't schedule. That means they can't
bea3348e 22 * call napi_disable() neither, thus force gem_poll() to keep a spinlock
1da177e4
LT		 23 * where it could have been dropped. change_mtu especially would love also to
24 * be able to msleep instead of horrid locked delays when resetting the HW,
25 * but that read_lock() makes it impossible, unless I defer it's action to
26 * the reset task, which means it'll be asynchronous (won't take effect until
27 * the system schedules a bit).
28 *
29 * Also, it would probably be possible to also remove most of the long-life
30 * locking in open/resume code path (gem_reinit_chip) by beeing more careful
31 * about when we can start taking interrupts or get xmit() called...
32 */
33
c6c75988
JP		 34#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
35
1da177e4
LT		 36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/types.h>
39#include <linux/fcntl.h>
40#include <linux/interrupt.h>
41#include <linux/ioport.h>
42#include <linux/in.h>
d43c36dc 43#include <linux/sched.h>
1da177e4
LT		 44#include <linux/string.h>
45#include <linux/delay.h>
46#include <linux/init.h>
47#include <linux/errno.h>
48#include <linux/pci.h>
1e7f0bd8 49#include <linux/dma-mapping.h>
1da177e4
LT		 50#include <linux/netdevice.h>
51#include <linux/etherdevice.h>
52#include <linux/skbuff.h>
53#include <linux/mii.h>
54#include <linux/ethtool.h>
55#include <linux/crc32.h>
56#include <linux/random.h>
57#include <linux/workqueue.h>
58#include <linux/if_vlan.h>
59#include <linux/bitops.h>
e3968fc0 60#include <linux/mutex.h>
d7fe0f24 61#include <linux/mm.h>
5a0e3ad6 62#include <linux/gfp.h>
1da177e4
LT		 63
64#include <asm/system.h>
65#include <asm/io.h>
66#include <asm/byteorder.h>
67#include <asm/uaccess.h>
68#include <asm/irq.h>
69
dadb830d 70#ifdef CONFIG_SPARC
1da177e4 71#include <asm/idprom.h>
457e1a8a 72#include <asm/prom.h>
1da177e4
LT		 73#endif
74
75#ifdef CONFIG_PPC_PMAC
76#include <asm/pci-bridge.h>
77#include <asm/prom.h>
78#include <asm/machdep.h>
79#include <asm/pmac_feature.h>
80#endif
81
82#include "sungem_phy.h"
83#include "sungem.h"
84
85/* Stripping FCS is causing problems, disabled for now */
86#undef STRIP_FCS
87
88#define DEFAULT_MSG (NETIF_MSG_DRV | \
89 NETIF_MSG_PROBE | \
90 NETIF_MSG_LINK)
91
92#define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
93 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
63ea998a
BH		 94 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
95 SUPPORTED_Pause | SUPPORTED_Autoneg)
1da177e4
LT		 96
97#define DRV_NAME "sungem"
98#define DRV_VERSION "0.98"
99#define DRV_RELDATE "8/24/03"
100#define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
101
102static char version[] __devinitdata =
103 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
104
105MODULE_AUTHOR(DRV_AUTHOR);
106MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
107MODULE_LICENSE("GPL");
108
109#define GEM_MODULE_NAME "gem"
1da177e4 110
a3aa1884 111static DEFINE_PCI_DEVICE_TABLE(gem_pci_tbl) = {
1da177e4
LT		 112 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
114
115 /* These models only differ from the original GEM in
116 * that their tx/rx fifos are of a different size and
117 * they only support 10/100 speeds. -DaveM
6aa20a22 118 *
1da177e4
LT		 119 * Apple's GMAC does support gigabit on machines with
120 * the BCM54xx PHYs. -BenH
121 */
122 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
124 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
126 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
128 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
130 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
132 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7fce260a
OJ		 134 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 136 {0, }
137};
138
139MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
140
141static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
142{
143 u32 cmd;
144 int limit = 10000;
145
146 cmd = (1 << 30);
147 cmd |= (2 << 28);
148 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
149 cmd |= (reg << 18) & MIF_FRAME_REGAD;
150 cmd |= (MIF_FRAME_TAMSB);
151 writel(cmd, gp->regs + MIF_FRAME);
152
46578a69 153 while (--limit) {
1da177e4
LT		 154 cmd = readl(gp->regs + MIF_FRAME);
155 if (cmd & MIF_FRAME_TALSB)
156 break;
157
158 udelay(10);
159 }
160
161 if (!limit)
162 cmd = 0xffff;
163
164 return cmd & MIF_FRAME_DATA;
165}
166
167static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
168{
8f15ea42 169 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 170 return __phy_read(gp, mii_id, reg);
171}
172
173static inline u16 phy_read(struct gem *gp, int reg)
174{
175 return __phy_read(gp, gp->mii_phy_addr, reg);
176}
177
178static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
179{
180 u32 cmd;
181 int limit = 10000;
182
183 cmd = (1 << 30);
184 cmd |= (1 << 28);
185 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
186 cmd |= (reg << 18) & MIF_FRAME_REGAD;
187 cmd |= (MIF_FRAME_TAMSB);
188 cmd |= (val & MIF_FRAME_DATA);
189 writel(cmd, gp->regs + MIF_FRAME);
190
191 while (limit--) {
192 cmd = readl(gp->regs + MIF_FRAME);
193 if (cmd & MIF_FRAME_TALSB)
194 break;
195
196 udelay(10);
197 }
198}
199
200static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
201{
8f15ea42 202 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 203 __phy_write(gp, mii_id, reg, val & 0xffff);
204}
205
206static inline void phy_write(struct gem *gp, int reg, u16 val)
207{
208 __phy_write(gp, gp->mii_phy_addr, reg, val);
209}
210
211static inline void gem_enable_ints(struct gem *gp)
212{
213 /* Enable all interrupts but TXDONE */
214 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
215}
216
217static inline void gem_disable_ints(struct gem *gp)
218{
219 /* Disable all interrupts, including TXDONE */
220 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
221}
222
223static void gem_get_cell(struct gem *gp)
224{
225 BUG_ON(gp->cell_enabled < 0);
226 gp->cell_enabled++;
227#ifdef CONFIG_PPC_PMAC
228 if (gp->cell_enabled == 1) {
229 mb();
230 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
231 udelay(10);
232 }
233#endif /* CONFIG_PPC_PMAC */
234}
235
236/* Turn off the chip's clock */
237static void gem_put_cell(struct gem *gp)
238{
239 BUG_ON(gp->cell_enabled <= 0);
240 gp->cell_enabled--;
241#ifdef CONFIG_PPC_PMAC
242 if (gp->cell_enabled == 0) {
243 mb();
244 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
245 udelay(10);
246 }
247#endif /* CONFIG_PPC_PMAC */
248}
249
250static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
251{
252 if (netif_msg_intr(gp))
253 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
254}
255
256static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
257{
258 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
259 u32 pcs_miistat;
260
261 if (netif_msg_intr(gp))
262 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
263 gp->dev->name, pcs_istat);
264
265 if (!(pcs_istat & PCS_ISTAT_LSC)) {
c6c75988 266 netdev_err(dev, "PCS irq but no link status change???\n");
1da177e4
LT		 267 return 0;
268 }
269
270 /* The link status bit latches on zero, so you must
271 * read it twice in such a case to see a transition
272 * to the link being up.
273 */
274 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
275 if (!(pcs_miistat & PCS_MIISTAT_LS))
276 pcs_miistat |=
277 (readl(gp->regs + PCS_MIISTAT) &
278 PCS_MIISTAT_LS);
279
280 if (pcs_miistat & PCS_MIISTAT_ANC) {
281 /* The remote-fault indication is only valid
282 * when autoneg has completed.
283 */
284 if (pcs_miistat & PCS_MIISTAT_RF)
c6c75988 285 netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n");
1da177e4 286 else
c6c75988 287 netdev_info(dev, "PCS AutoNEG complete\n");
1da177e4
LT		 288 }
289
290 if (pcs_miistat & PCS_MIISTAT_LS) {
c6c75988 291 netdev_info(dev, "PCS link is now up\n");
1da177e4
LT		 292 netif_carrier_on(gp->dev);
293 } else {
c6c75988 294 netdev_info(dev, "PCS link is now down\n");
1da177e4
LT		 295 netif_carrier_off(gp->dev);
296 /* If this happens and the link timer is not running,
297 * reset so we re-negotiate.
298 */
299 if (!timer_pending(&gp->link_timer))
300 return 1;
301 }
302
303 return 0;
304}
305
306static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
307{
308 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
309
310 if (netif_msg_intr(gp))
311 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
312 gp->dev->name, txmac_stat);
313
314 /* Defer timer expiration is quite normal,
315 * don't even log the event.
316 */
317 if ((txmac_stat & MAC_TXSTAT_DTE) &&
318 !(txmac_stat & ~MAC_TXSTAT_DTE))
319 return 0;
320
321 if (txmac_stat & MAC_TXSTAT_URUN) {
c6c75988 322 netdev_err(dev, "TX MAC xmit underrun\n");
1da177e4
LT		 323 gp->net_stats.tx_fifo_errors++;
324 }
325
326 if (txmac_stat & MAC_TXSTAT_MPE) {
c6c75988 327 netdev_err(dev, "TX MAC max packet size error\n");
1da177e4
LT		 328 gp->net_stats.tx_errors++;
329 }
330
331 /* The rest are all cases of one of the 16-bit TX
332 * counters expiring.
333 */
334 if (txmac_stat & MAC_TXSTAT_NCE)
335 gp->net_stats.collisions += 0x10000;
336
337 if (txmac_stat & MAC_TXSTAT_ECE) {
338 gp->net_stats.tx_aborted_errors += 0x10000;
339 gp->net_stats.collisions += 0x10000;
340 }
341
342 if (txmac_stat & MAC_TXSTAT_LCE) {
343 gp->net_stats.tx_aborted_errors += 0x10000;
344 gp->net_stats.collisions += 0x10000;
345 }
346
347 /* We do not keep track of MAC_TXSTAT_FCE and
348 * MAC_TXSTAT_PCE events.
349 */
350 return 0;
351}
352
353/* When we get a RX fifo overflow, the RX unit in GEM is probably hung
354 * so we do the following.
355 *
356 * If any part of the reset goes wrong, we return 1 and that causes the
357 * whole chip to be reset.
358 */
359static int gem_rxmac_reset(struct gem *gp)
360{
361 struct net_device *dev = gp->dev;
362 int limit, i;
363 u64 desc_dma;
364 u32 val;
365
366 /* First, reset & disable MAC RX. */
367 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
368 for (limit = 0; limit < 5000; limit++) {
369 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
370 break;
371 udelay(10);
372 }
373 if (limit == 5000) {
c6c75988 374 netdev_err(dev, "RX MAC will not reset, resetting whole chip\n");
1da177e4
LT		 375 return 1;
376 }
377
378 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
379 gp->regs + MAC_RXCFG);
380 for (limit = 0; limit < 5000; limit++) {
381 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
382 break;
383 udelay(10);
384 }
385 if (limit == 5000) {
c6c75988 386 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
1da177e4
LT		 387 return 1;
388 }
389
390 /* Second, disable RX DMA. */
391 writel(0, gp->regs + RXDMA_CFG);
392 for (limit = 0; limit < 5000; limit++) {
393 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
394 break;
395 udelay(10);
396 }
397 if (limit == 5000) {
c6c75988 398 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
1da177e4
LT		 399 return 1;
400 }
401
402 udelay(5000);
403
404 /* Execute RX reset command. */
405 writel(gp->swrst_base | GREG_SWRST_RXRST,
406 gp->regs + GREG_SWRST);
407 for (limit = 0; limit < 5000; limit++) {
408 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
409 break;
410 udelay(10);
411 }
412 if (limit == 5000) {
c6c75988 413 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
1da177e4
LT		 414 return 1;
415 }
416
417 /* Refresh the RX ring. */
418 for (i = 0; i < RX_RING_SIZE; i++) {
419 struct gem_rxd *rxd = &gp->init_block->rxd[i];
420
421 if (gp->rx_skbs[i] == NULL) {
c6c75988 422 netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n");
1da177e4
LT		 423 return 1;
424 }
425
426 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
427 }
428 gp->rx_new = gp->rx_old = 0;
429
430 /* Now we must reprogram the rest of RX unit. */
431 desc_dma = (u64) gp->gblock_dvma;
432 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
433 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
434 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
435 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
436 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
437 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
438 writel(val, gp->regs + RXDMA_CFG);
439 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
440 writel(((5 & RXDMA_BLANK_IPKTS) |
441 ((8 << 12) & RXDMA_BLANK_ITIME)),
442 gp->regs + RXDMA_BLANK);
443 else
444 writel(((5 & RXDMA_BLANK_IPKTS) |
445 ((4 << 12) & RXDMA_BLANK_ITIME)),
446 gp->regs + RXDMA_BLANK);
447 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
448 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
449 writel(val, gp->regs + RXDMA_PTHRESH);
450 val = readl(gp->regs + RXDMA_CFG);
451 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
452 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
453 val = readl(gp->regs + MAC_RXCFG);
454 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
455
456 return 0;
457}
458
459static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
460{
461 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
462 int ret = 0;
463
464 if (netif_msg_intr(gp))
465 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
466 gp->dev->name, rxmac_stat);
467
468 if (rxmac_stat & MAC_RXSTAT_OFLW) {
469 u32 smac = readl(gp->regs + MAC_SMACHINE);
470
c6c75988 471 netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac);
1da177e4
LT		 472 gp->net_stats.rx_over_errors++;
473 gp->net_stats.rx_fifo_errors++;
474
475 ret = gem_rxmac_reset(gp);
476 }
477
478 if (rxmac_stat & MAC_RXSTAT_ACE)
479 gp->net_stats.rx_frame_errors += 0x10000;
480
481 if (rxmac_stat & MAC_RXSTAT_CCE)
482 gp->net_stats.rx_crc_errors += 0x10000;
483
484 if (rxmac_stat & MAC_RXSTAT_LCE)
485 gp->net_stats.rx_length_errors += 0x10000;
486
487 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
488 * events.
489 */
490 return ret;
491}
492
493static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
494{
495 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
496
497 if (netif_msg_intr(gp))
498 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
499 gp->dev->name, mac_cstat);
500
501 /* This interrupt is just for pause frame and pause
502 * tracking. It is useful for diagnostics and debug
503 * but probably by default we will mask these events.
504 */
505 if (mac_cstat & MAC_CSTAT_PS)
506 gp->pause_entered++;
507
508 if (mac_cstat & MAC_CSTAT_PRCV)
509 gp->pause_last_time_recvd = (mac_cstat >> 16);
510
511 return 0;
512}
513
514static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
515{
516 u32 mif_status = readl(gp->regs + MIF_STATUS);
517 u32 reg_val, changed_bits;
518
519 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
520 changed_bits = (mif_status & MIF_STATUS_STAT);
521
522 gem_handle_mif_event(gp, reg_val, changed_bits);
523
524 return 0;
525}
526
527static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
528{
529 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
530
531 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
532 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
c6c75988 533 netdev_err(dev, "PCI error [%04x]", pci_estat);
1da177e4
LT		 534
535 if (pci_estat & GREG_PCIESTAT_BADACK)
c6c75988 536 pr_cont(" <No ACK64# during ABS64 cycle>");
1da177e4 537 if (pci_estat & GREG_PCIESTAT_DTRTO)
c6c75988 538 pr_cont(" <Delayed transaction timeout>");
1da177e4 539 if (pci_estat & GREG_PCIESTAT_OTHER)
c6c75988
JP		 540 pr_cont(" <other>");
541 pr_cont("\n");
1da177e4
LT		 542 } else {
543 pci_estat |= GREG_PCIESTAT_OTHER;
c6c75988 544 netdev_err(dev, "PCI error\n");
1da177e4
LT		 545 }
546
547 if (pci_estat & GREG_PCIESTAT_OTHER) {
548 u16 pci_cfg_stat;
549
550 /* Interrogate PCI config space for the
551 * true cause.
552 */
553 pci_read_config_word(gp->pdev, PCI_STATUS,
554 &pci_cfg_stat);
c6c75988
JP		 555 netdev_err(dev, "Read PCI cfg space status [%04x]\n",
556 pci_cfg_stat);
1da177e4 557 if (pci_cfg_stat & PCI_STATUS_PARITY)
c6c75988 558 netdev_err(dev, "PCI parity error detected\n");
1da177e4 559 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
c6c75988 560 netdev_err(dev, "PCI target abort\n");
1da177e4 561 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
c6c75988 562 netdev_err(dev, "PCI master acks target abort\n");
1da177e4 563 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
c6c75988 564 netdev_err(dev, "PCI master abort\n");
1da177e4 565 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
c6c75988 566 netdev_err(dev, "PCI system error SERR#\n");
1da177e4 567 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
c6c75988 568 netdev_err(dev, "PCI parity error\n");
1da177e4
LT		 569
570 /* Write the error bits back to clear them. */
571 pci_cfg_stat &= (PCI_STATUS_PARITY |
572 PCI_STATUS_SIG_TARGET_ABORT |
573 PCI_STATUS_REC_TARGET_ABORT |
574 PCI_STATUS_REC_MASTER_ABORT |
575 PCI_STATUS_SIG_SYSTEM_ERROR |
576 PCI_STATUS_DETECTED_PARITY);
577 pci_write_config_word(gp->pdev,
578 PCI_STATUS, pci_cfg_stat);
579 }
580
581 /* For all PCI errors, we should reset the chip. */
582 return 1;
583}
584
585/* All non-normal interrupt conditions get serviced here.
586 * Returns non-zero if we should just exit the interrupt
587 * handler right now (ie. if we reset the card which invalidates
588 * all of the other original irq status bits).
589 */
590static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
591{
592 if (gem_status & GREG_STAT_RXNOBUF) {
593 /* Frame arrived, no free RX buffers available. */
594 if (netif_msg_rx_err(gp))
595 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
596 gp->dev->name);
597 gp->net_stats.rx_dropped++;
598 }
599
600 if (gem_status & GREG_STAT_RXTAGERR) {
601 /* corrupt RX tag framing */
602 if (netif_msg_rx_err(gp))
603 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
604 gp->dev->name);
605 gp->net_stats.rx_errors++;
606
607 goto do_reset;
608 }
609
610 if (gem_status & GREG_STAT_PCS) {
611 if (gem_pcs_interrupt(dev, gp, gem_status))
612 goto do_reset;
613 }
614
615 if (gem_status & GREG_STAT_TXMAC) {
616 if (gem_txmac_interrupt(dev, gp, gem_status))
617 goto do_reset;
618 }
619
620 if (gem_status & GREG_STAT_RXMAC) {
621 if (gem_rxmac_interrupt(dev, gp, gem_status))
622 goto do_reset;
623 }
624
625 if (gem_status & GREG_STAT_MAC) {
626 if (gem_mac_interrupt(dev, gp, gem_status))
627 goto do_reset;
628 }
629
630 if (gem_status & GREG_STAT_MIF) {
631 if (gem_mif_interrupt(dev, gp, gem_status))
632 goto do_reset;
633 }
634
635 if (gem_status & GREG_STAT_PCIERR) {
636 if (gem_pci_interrupt(dev, gp, gem_status))
637 goto do_reset;
638 }
639
640 return 0;
641
642do_reset:
643 gp->reset_task_pending = 1;
644 schedule_work(&gp->reset_task);
645
646 return 1;
647}
648
649static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
650{
651 int entry, limit;
652
653 if (netif_msg_intr(gp))
654 printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n",
655 gp->dev->name, gem_status);
656
657 entry = gp->tx_old;
658 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
659 while (entry != limit) {
660 struct sk_buff *skb;
661 struct gem_txd *txd;
662 dma_addr_t dma_addr;
663 u32 dma_len;
664 int frag;
665
666 if (netif_msg_tx_done(gp))
667 printk(KERN_DEBUG "%s: tx done, slot %d\n",
668 gp->dev->name, entry);
669 skb = gp->tx_skbs[entry];
670 if (skb_shinfo(skb)->nr_frags) {
671 int last = entry + skb_shinfo(skb)->nr_frags;
672 int walk = entry;
673 int incomplete = 0;
674
675 last &= (TX_RING_SIZE - 1);
676 for (;;) {
677 walk = NEXT_TX(walk);
678 if (walk == limit)
679 incomplete = 1;
680 if (walk == last)
681 break;
682 }
683 if (incomplete)
684 break;
685 }
686 gp->tx_skbs[entry] = NULL;
687 gp->net_stats.tx_bytes += skb->len;
688
689 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
690 txd = &gp->init_block->txd[entry];
691
692 dma_addr = le64_to_cpu(txd->buffer);
693 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
694
695 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
696 entry = NEXT_TX(entry);
697 }
698
699 gp->net_stats.tx_packets++;
700 dev_kfree_skb_irq(skb);
701 }
702 gp->tx_old = entry;
703
704 if (netif_queue_stopped(dev) &&
705 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
706 netif_wake_queue(dev);
707}
708
709static __inline__ void gem_post_rxds(struct gem *gp, int limit)
710{
711 int cluster_start, curr, count, kick;
712
713 cluster_start = curr = (gp->rx_new & ~(4 - 1));
714 count = 0;
715 kick = -1;
716 wmb();
717 while (curr != limit) {
718 curr = NEXT_RX(curr);
719 if (++count == 4) {
720 struct gem_rxd *rxd =
721 &gp->init_block->rxd[cluster_start];
722 for (;;) {
723 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
724 rxd++;
725 cluster_start = NEXT_RX(cluster_start);
726 if (cluster_start == curr)
727 break;
728 }
729 kick = curr;
730 count = 0;
731 }
732 }
733 if (kick >= 0) {
734 mb();
735 writel(kick, gp->regs + RXDMA_KICK);
736 }
737}
738
739static int gem_rx(struct gem *gp, int work_to_do)
740{
741 int entry, drops, work_done = 0;
742 u32 done;
439104b3 743 __sum16 csum;
1da177e4
LT		 744
745 if (netif_msg_rx_status(gp))
746 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
747 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
748
749 entry = gp->rx_new;
750 drops = 0;
751 done = readl(gp->regs + RXDMA_DONE);
752 for (;;) {
753 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
754 struct sk_buff *skb;
439104b3 755 u64 status = le64_to_cpu(rxd->status_word);
1da177e4
LT		 756 dma_addr_t dma_addr;
757 int len;
758
759 if ((status & RXDCTRL_OWN) != 0)
760 break;
761
762 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
763 break;
764
765 /* When writing back RX descriptor, GEM writes status
3ad2f3fb 766 * then buffer address, possibly in separate transactions.
1da177e4
LT		 767 * If we don't wait for the chip to write both, we could
768 * post a new buffer to this descriptor then have GEM spam
769 * on the buffer address. We sync on the RX completion
770 * register to prevent this from happening.
771 */
772 if (entry == done) {
773 done = readl(gp->regs + RXDMA_DONE);
774 if (entry == done)
775 break;
776 }
777
778 /* We can now account for the work we're about to do */
779 work_done++;
780
781 skb = gp->rx_skbs[entry];
782
783 len = (status & RXDCTRL_BUFSZ) >> 16;
784 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
785 gp->net_stats.rx_errors++;
786 if (len < ETH_ZLEN)
787 gp->net_stats.rx_length_errors++;
788 if (len & RXDCTRL_BAD)
789 gp->net_stats.rx_crc_errors++;
790
791 /* We'll just return it to GEM. */
792 drop_it:
793 gp->net_stats.rx_dropped++;
794 goto next;
795 }
796
439104b3 797 dma_addr = le64_to_cpu(rxd->buffer);
1da177e4
LT		 798 if (len > RX_COPY_THRESHOLD) {
799 struct sk_buff *new_skb;
800
801 new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
802 if (new_skb == NULL) {
803 drops++;
804 goto drop_it;
805 }
806 pci_unmap_page(gp->pdev, dma_addr,
807 RX_BUF_ALLOC_SIZE(gp),
808 PCI_DMA_FROMDEVICE);
809 gp->rx_skbs[entry] = new_skb;
810 new_skb->dev = gp->dev;
811 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
812 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
813 virt_to_page(new_skb->data),
814 offset_in_page(new_skb->data),
815 RX_BUF_ALLOC_SIZE(gp),
816 PCI_DMA_FROMDEVICE));
817 skb_reserve(new_skb, RX_OFFSET);
818
819 /* Trim the original skb for the netif. */
820 skb_trim(skb, len);
821 } else {
822 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
823
824 if (copy_skb == NULL) {
825 drops++;
826 goto drop_it;
827 }
828
1da177e4
LT		 829 skb_reserve(copy_skb, 2);
830 skb_put(copy_skb, len);
831 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 832 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 833 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
834
835 /* We'll reuse the original ring buffer. */
836 skb = copy_skb;
837 }
838
439104b3
AV		 839 csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
840 skb->csum = csum_unfold(csum);
84fa7933 841 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 842 skb->protocol = eth_type_trans(skb, gp->dev);
843
844 netif_receive_skb(skb);
845
846 gp->net_stats.rx_packets++;
847 gp->net_stats.rx_bytes += len;
1da177e4
LT		 848
849 next:
850 entry = NEXT_RX(entry);
851 }
852
853 gem_post_rxds(gp, entry);
854
855 gp->rx_new = entry;
856
857 if (drops)
c6c75988 858 netdev_info(gp->dev, "Memory squeeze, deferring packet\n");
1da177e4
LT		 859
860 return work_done;
861}
862
bea3348e 863static int gem_poll(struct napi_struct *napi, int budget)
1da177e4 864{
bea3348e
SH		 865 struct gem *gp = container_of(napi, struct gem, napi);
866 struct net_device *dev = gp->dev;
1da177e4 867 unsigned long flags;
bea3348e 868 int work_done;
1da177e4
LT		 869
870 /*
6aa20a22 871 * NAPI locking nightmare: See comment at head of driver
1da177e4
LT		 872 */
873 spin_lock_irqsave(&gp->lock, flags);
874
bea3348e 875 work_done = 0;
1da177e4 876 do {
1da177e4
LT		 877 /* Handle anomalies */
878 if (gp->status & GREG_STAT_ABNORMAL) {
879 if (gem_abnormal_irq(dev, gp, gp->status))
880 break;
881 }
882
883 /* Run TX completion thread */
884 spin_lock(&gp->tx_lock);
885 gem_tx(dev, gp, gp->status);
886 spin_unlock(&gp->tx_lock);
887
888 spin_unlock_irqrestore(&gp->lock, flags);
889
6aa20a22
JG		 890 /* Run RX thread. We don't use any locking here,
891 * code willing to do bad things - like cleaning the
bea3348e 892 * rx ring - must call napi_disable(), which
1da177e4
LT		 893 * schedule_timeout()'s if polling is already disabled.
894 */
da990a24 895 work_done += gem_rx(gp, budget - work_done);
1da177e4 896
bea3348e
SH		 897 if (work_done >= budget)
898 return work_done;
1da177e4
LT		 899
900 spin_lock_irqsave(&gp->lock, flags);
6aa20a22 901
1da177e4
LT		 902 gp->status = readl(gp->regs + GREG_STAT);
903 } while (gp->status & GREG_STAT_NAPI);
904
288379f0 905 __napi_complete(napi);
1da177e4
LT		 906 gem_enable_ints(gp);
907
908 spin_unlock_irqrestore(&gp->lock, flags);
bea3348e
SH		 909
910 return work_done;
1da177e4
LT		 911}
912
7d12e780 913static irqreturn_t gem_interrupt(int irq, void *dev_id)
1da177e4
LT		 914{
915 struct net_device *dev = dev_id;
8f15ea42 916 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 917 unsigned long flags;
918
919 /* Swallow interrupts when shutting the chip down, though
920 * that shouldn't happen, we should have done free_irq() at
921 * this point...
922 */
923 if (!gp->running)
924 return IRQ_HANDLED;
925
926 spin_lock_irqsave(&gp->lock, flags);
6aa20a22 927
288379f0 928 if (napi_schedule_prep(&gp->napi)) {
1da177e4
LT		 929 u32 gem_status = readl(gp->regs + GREG_STAT);
930
931 if (gem_status == 0) {
bea3348e 932 napi_enable(&gp->napi);
1da177e4
LT		 933 spin_unlock_irqrestore(&gp->lock, flags);
934 return IRQ_NONE;
935 }
936 gp->status = gem_status;
937 gem_disable_ints(gp);
288379f0 938 __napi_schedule(&gp->napi);
1da177e4
LT		 939 }
940
941 spin_unlock_irqrestore(&gp->lock, flags);
6aa20a22 942
1da177e4 943 /* If polling was disabled at the time we received that
6aa20a22 944 * interrupt, we may return IRQ_HANDLED here while we
1da177e4
LT		 945 * should return IRQ_NONE. No big deal...
946 */
947 return IRQ_HANDLED;
948}
949
950#ifdef CONFIG_NET_POLL_CONTROLLER
951static void gem_poll_controller(struct net_device *dev)
952{
953 /* gem_interrupt is safe to reentrance so no need
954 * to disable_irq here.
955 */
7d12e780 956 gem_interrupt(dev->irq, dev);
1da177e4
LT		 957}
958#endif
959
960static void gem_tx_timeout(struct net_device *dev)
961{
8f15ea42 962 struct gem *gp = netdev_priv(dev);
1da177e4 963
c6c75988 964 netdev_err(dev, "transmit timed out, resetting\n");
1da177e4 965 if (!gp->running) {
c6c75988 966 netdev_err(dev, "hrm.. hw not running !\n");
1da177e4
LT		 967 return;
968 }
c6c75988
JP		 969 netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n",
970 readl(gp->regs + TXDMA_CFG),
971 readl(gp->regs + MAC_TXSTAT),
972 readl(gp->regs + MAC_TXCFG));
973 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
974 readl(gp->regs + RXDMA_CFG),
975 readl(gp->regs + MAC_RXSTAT),
976 readl(gp->regs + MAC_RXCFG));
1da177e4
LT		 977
978 spin_lock_irq(&gp->lock);
979 spin_lock(&gp->tx_lock);
980
981 gp->reset_task_pending = 1;
982 schedule_work(&gp->reset_task);
983
984 spin_unlock(&gp->tx_lock);
985 spin_unlock_irq(&gp->lock);
986}
987
988static __inline__ int gem_intme(int entry)
989{
990 /* Algorithm: IRQ every 1/2 of descriptors. */
991 if (!(entry & ((TX_RING_SIZE>>1)-1)))
992 return 1;
993
994 return 0;
995}
996
61357325
SH		 997static netdev_tx_t gem_start_xmit(struct sk_buff *skb,
998 struct net_device *dev)
1da177e4 999{
8f15ea42 1000 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 1001 int entry;
1002 u64 ctrl;
1003 unsigned long flags;
1004
1005 ctrl = 0;
84fa7933 1006 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d
ACM		 1007 const u64 csum_start_off = skb_transport_offset(skb);
1008 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
1da177e4
LT		 1009
1010 ctrl = (TXDCTRL_CENAB |
1011 (csum_start_off << 15) |
1012 (csum_stuff_off << 21));
1013 }
1014
b8883a65 1015 if (!spin_trylock_irqsave(&gp->tx_lock, flags)) {
1da177e4 1016 /* Tell upper layer to requeue */
1da177e4
LT		 1017 return NETDEV_TX_LOCKED;
1018 }
1019 /* We raced with gem_do_stop() */
1020 if (!gp->running) {
1021 spin_unlock_irqrestore(&gp->tx_lock, flags);
1022 return NETDEV_TX_BUSY;
1023 }
1024
1025 /* This is a hard error, log it. */
1026 if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
1027 netif_stop_queue(dev);
1028 spin_unlock_irqrestore(&gp->tx_lock, flags);
c6c75988 1029 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
1da177e4
LT		 1030 return NETDEV_TX_BUSY;
1031 }
1032
1033 entry = gp->tx_new;
1034 gp->tx_skbs[entry] = skb;
1035
1036 if (skb_shinfo(skb)->nr_frags == 0) {
1037 struct gem_txd *txd = &gp->init_block->txd[entry];
1038 dma_addr_t mapping;
1039 u32 len;
1040
1041 len = skb->len;
1042 mapping = pci_map_page(gp->pdev,
1043 virt_to_page(skb->data),
1044 offset_in_page(skb->data),
1045 len, PCI_DMA_TODEVICE);
1046 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1047 if (gem_intme(entry))
1048 ctrl |= TXDCTRL_INTME;
1049 txd->buffer = cpu_to_le64(mapping);
1050 wmb();
1051 txd->control_word = cpu_to_le64(ctrl);
1052 entry = NEXT_TX(entry);
1053 } else {
1054 struct gem_txd *txd;
1055 u32 first_len;
1056 u64 intme;
1057 dma_addr_t first_mapping;
1058 int frag, first_entry = entry;
1059
1060 intme = 0;
1061 if (gem_intme(entry))
1062 intme |= TXDCTRL_INTME;
1063
1064 /* We must give this initial chunk to the device last.
1065 * Otherwise we could race with the device.
1066 */
1067 first_len = skb_headlen(skb);
1068 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1069 offset_in_page(skb->data),
1070 first_len, PCI_DMA_TODEVICE);
1071 entry = NEXT_TX(entry);
1072
1073 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1074 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1075 u32 len;
1076 dma_addr_t mapping;
1077 u64 this_ctrl;
1078
1079 len = this_frag->size;
1080 mapping = pci_map_page(gp->pdev,
1081 this_frag->page,
1082 this_frag->page_offset,
1083 len, PCI_DMA_TODEVICE);
1084 this_ctrl = ctrl;
1085 if (frag == skb_shinfo(skb)->nr_frags - 1)
1086 this_ctrl |= TXDCTRL_EOF;
6aa20a22 1087
1da177e4
LT		 1088 txd = &gp->init_block->txd[entry];
1089 txd->buffer = cpu_to_le64(mapping);
1090 wmb();
1091 txd->control_word = cpu_to_le64(this_ctrl | len);
1092
1093 if (gem_intme(entry))
1094 intme |= TXDCTRL_INTME;
1095
1096 entry = NEXT_TX(entry);
1097 }
1098 txd = &gp->init_block->txd[first_entry];
1099 txd->buffer = cpu_to_le64(first_mapping);
1100 wmb();
1101 txd->control_word =
1102 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1103 }
1104
1105 gp->tx_new = entry;
1106 if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))
1107 netif_stop_queue(dev);
1108
1109 if (netif_msg_tx_queued(gp))
1110 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1111 dev->name, entry, skb->len);
1112 mb();
1113 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1114 spin_unlock_irqrestore(&gp->tx_lock, flags);
1115
1ae5dc34 1116 dev->trans_start = jiffies; /* NETIF_F_LLTX driver :( */
1da177e4
LT		 1117
1118 return NETDEV_TX_OK;
1119}
1120
8c83f80b
DM		 1121static void gem_pcs_reset(struct gem *gp)
1122{
1123 int limit;
1124 u32 val;
1125
1126 /* Reset PCS unit. */
1127 val = readl(gp->regs + PCS_MIICTRL);
1128 val |= PCS_MIICTRL_RST;
1129 writel(val, gp->regs + PCS_MIICTRL);
1130
1131 limit = 32;
1132 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1133 udelay(100);
1134 if (limit-- <= 0)
1135 break;
1136 }
d13c11f6 1137 if (limit < 0)
c6c75988 1138 netdev_warn(gp->dev, "PCS reset bit would not clear\n");
8c83f80b
DM		 1139}
1140
1141static void gem_pcs_reinit_adv(struct gem *gp)
1142{
1143 u32 val;
1144
1145 /* Make sure PCS is disabled while changing advertisement
1146 * configuration.
1147 */
1148 val = readl(gp->regs + PCS_CFG);
1149 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1150 writel(val, gp->regs + PCS_CFG);
1151
1152 /* Advertise all capabilities except assymetric
1153 * pause.
1154 */
1155 val = readl(gp->regs + PCS_MIIADV);
1156 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1157 PCS_MIIADV_SP | PCS_MIIADV_AP);
1158 writel(val, gp->regs + PCS_MIIADV);
1159
1160 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1161 * and re-enable PCS.
1162 */
1163 val = readl(gp->regs + PCS_MIICTRL);
1164 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1165 val &= ~PCS_MIICTRL_WB;
1166 writel(val, gp->regs + PCS_MIICTRL);
1167
1168 val = readl(gp->regs + PCS_CFG);
1169 val |= PCS_CFG_ENABLE;
1170 writel(val, gp->regs + PCS_CFG);
1171
1172 /* Make sure serialink loopback is off. The meaning
1173 * of this bit is logically inverted based upon whether
1174 * you are in Serialink or SERDES mode.
1175 */
1176 val = readl(gp->regs + PCS_SCTRL);
1177 if (gp->phy_type == phy_serialink)
1178 val &= ~PCS_SCTRL_LOOP;
1179 else
1180 val |= PCS_SCTRL_LOOP;
1181 writel(val, gp->regs + PCS_SCTRL);
1182}
1183
1da177e4
LT		 1184#define STOP_TRIES 32
1185
1186/* Must be invoked under gp->lock and gp->tx_lock. */
1187static void gem_reset(struct gem *gp)
1188{
1189 int limit;
1190 u32 val;
1191
1192 /* Make sure we won't get any more interrupts */
1193 writel(0xffffffff, gp->regs + GREG_IMASK);
1194
1195 /* Reset the chip */
1196 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1197 gp->regs + GREG_SWRST);
1198
1199 limit = STOP_TRIES;
1200
1201 do {
1202 udelay(20);
1203 val = readl(gp->regs + GREG_SWRST);
1204 if (limit-- <= 0)
1205 break;
1206 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1207
4a8fd2cf 1208 if (limit < 0)
c6c75988 1209 netdev_err(gp->dev, "SW reset is ghetto\n");
8c83f80b
DM		 1210
1211 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
1212 gem_pcs_reinit_adv(gp);
1da177e4
LT		 1213}
1214
1215/* Must be invoked under gp->lock and gp->tx_lock. */
1216static void gem_start_dma(struct gem *gp)
1217{
1218 u32 val;
6aa20a22 1219
1da177e4
LT		 1220 /* We are ready to rock, turn everything on. */
1221 val = readl(gp->regs + TXDMA_CFG);
1222 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1223 val = readl(gp->regs + RXDMA_CFG);
1224 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1225 val = readl(gp->regs + MAC_TXCFG);
1226 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1227 val = readl(gp->regs + MAC_RXCFG);
1228 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1229
1230 (void) readl(gp->regs + MAC_RXCFG);
1231 udelay(100);
1232
1233 gem_enable_ints(gp);
1234
1235 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1236}
1237
1238/* Must be invoked under gp->lock and gp->tx_lock. DMA won't be
1239 * actually stopped before about 4ms tho ...
1240 */
1241static void gem_stop_dma(struct gem *gp)
1242{
1243 u32 val;
1244
1245 /* We are done rocking, turn everything off. */
1246 val = readl(gp->regs + TXDMA_CFG);
1247 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1248 val = readl(gp->regs + RXDMA_CFG);
1249 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1250 val = readl(gp->regs + MAC_TXCFG);
1251 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1252 val = readl(gp->regs + MAC_RXCFG);
1253 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1254
1255 (void) readl(gp->regs + MAC_RXCFG);
1256
1257 /* Need to wait a bit ... done by the caller */
1258}
1259
1260
1261/* Must be invoked under gp->lock and gp->tx_lock. */
1262// XXX dbl check what that function should do when called on PCS PHY
1263static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1264{
1265 u32 advertise, features;
1266 int autoneg;
1267 int speed;
1268 int duplex;
1269
1270 if (gp->phy_type != phy_mii_mdio0 &&
1271 gp->phy_type != phy_mii_mdio1)
1272 goto non_mii;
1273
1274 /* Setup advertise */
1275 if (found_mii_phy(gp))
1276 features = gp->phy_mii.def->features;
1277 else
1278 features = 0;
1279
1280 advertise = features & ADVERTISE_MASK;
1281 if (gp->phy_mii.advertising != 0)
1282 advertise &= gp->phy_mii.advertising;
1283
1284 autoneg = gp->want_autoneg;
1285 speed = gp->phy_mii.speed;
1286 duplex = gp->phy_mii.duplex;
6aa20a22 1287
1da177e4
LT		 1288 /* Setup link parameters */
1289 if (!ep)
1290 goto start_aneg;
1291 if (ep->autoneg == AUTONEG_ENABLE) {
1292 advertise = ep->advertising;
1293 autoneg = 1;
1294 } else {
1295 autoneg = 0;
1296 speed = ep->speed;
1297 duplex = ep->duplex;
1298 }
1299
1300start_aneg:
1301 /* Sanitize settings based on PHY capabilities */
1302 if ((features & SUPPORTED_Autoneg) == 0)
1303 autoneg = 0;
1304 if (speed == SPEED_1000 &&
1305 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1306 speed = SPEED_100;
1307 if (speed == SPEED_100 &&
1308 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1309 speed = SPEED_10;
1310 if (duplex == DUPLEX_FULL &&
1311 !(features & (SUPPORTED_1000baseT_Full |
1312 SUPPORTED_100baseT_Full |
1313 SUPPORTED_10baseT_Full)))
1314 duplex = DUPLEX_HALF;
1315 if (speed == 0)
1316 speed = SPEED_10;
6aa20a22 1317
1da177e4
LT		 1318 /* If we are asleep, we don't try to actually setup the PHY, we
1319 * just store the settings
1320 */
1321 if (gp->asleep) {
1322 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1323 gp->phy_mii.speed = speed;
1324 gp->phy_mii.duplex = duplex;
1325 return;
1326 }
1327
1328 /* Configure PHY & start aneg */
1329 gp->want_autoneg = autoneg;
1330 if (autoneg) {
1331 if (found_mii_phy(gp))
1332 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1333 gp->lstate = link_aneg;
1334 } else {
1335 if (found_mii_phy(gp))
1336 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1337 gp->lstate = link_force_ok;
1338 }
1339
1340non_mii:
1341 gp->timer_ticks = 0;
1342 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1343}
1344
1345/* A link-up condition has occurred, initialize and enable the
1346 * rest of the chip.
1347 *
1348 * Must be invoked under gp->lock and gp->tx_lock.
1349 */
1350static int gem_set_link_modes(struct gem *gp)
1351{
1352 u32 val;
1353 int full_duplex, speed, pause;
1354
1355 full_duplex = 0;
1356 speed = SPEED_10;
1357 pause = 0;
1358
1359 if (found_mii_phy(gp)) {
1360 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1361 return 1;
1362 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1363 speed = gp->phy_mii.speed;
1364 pause = gp->phy_mii.pause;
1365 } else if (gp->phy_type == phy_serialink ||
1366 gp->phy_type == phy_serdes) {
1367 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1368
8c83f80b 1369 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
1da177e4
LT		 1370 full_duplex = 1;
1371 speed = SPEED_1000;
1372 }
1373
c6c75988
JP		 1374 netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n",
1375 speed, (full_duplex ? "full" : "half"));
1da177e4
LT		 1376
1377 if (!gp->running)
1378 return 0;
1379
1380 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1381 if (full_duplex) {
1382 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1383 } else {
1384 /* MAC_TXCFG_NBO must be zero. */
6aa20a22 1385 }
1da177e4
LT		 1386 writel(val, gp->regs + MAC_TXCFG);
1387
1388 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1389 if (!full_duplex &&
1390 (gp->phy_type == phy_mii_mdio0 ||
1391 gp->phy_type == phy_mii_mdio1)) {
1392 val |= MAC_XIFCFG_DISE;
1393 } else if (full_duplex) {
1394 val |= MAC_XIFCFG_FLED;
1395 }
1396
1397 if (speed == SPEED_1000)
1398 val |= (MAC_XIFCFG_GMII);
1399
1400 writel(val, gp->regs + MAC_XIFCFG);
1401
1402 /* If gigabit and half-duplex, enable carrier extension
1403 * mode. Else, disable it.
1404 */
1405 if (speed == SPEED_1000 && !full_duplex) {
1406 val = readl(gp->regs + MAC_TXCFG);
1407 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1408
1409 val = readl(gp->regs + MAC_RXCFG);
1410 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1411 } else {
1412 val = readl(gp->regs + MAC_TXCFG);
1413 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1414
1415 val = readl(gp->regs + MAC_RXCFG);
1416 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1417 }
1418
1419 if (gp->phy_type == phy_serialink ||
1420 gp->phy_type == phy_serdes) {
1421 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1422
1423 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1424 pause = 1;
1425 }
1426
1427 if (netif_msg_link(gp)) {
1428 if (pause) {
c6c75988
JP		 1429 netdev_info(gp->dev,
1430 "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
1431 gp->rx_fifo_sz,
1432 gp->rx_pause_off,
1433 gp->rx_pause_on);
1da177e4 1434 } else {
c6c75988 1435 netdev_info(gp->dev, "Pause is disabled\n");
1da177e4
LT		 1436 }
1437 }
1438
1439 if (!full_duplex)
1440 writel(512, gp->regs + MAC_STIME);
1441 else
1442 writel(64, gp->regs + MAC_STIME);
1443 val = readl(gp->regs + MAC_MCCFG);
1444 if (pause)
1445 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1446 else
1447 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1448 writel(val, gp->regs + MAC_MCCFG);
1449
1450 gem_start_dma(gp);
1451
1452 return 0;
1453}
1454
1455/* Must be invoked under gp->lock and gp->tx_lock. */
1456static int gem_mdio_link_not_up(struct gem *gp)
1457{
1458 switch (gp->lstate) {
1459 case link_force_ret:
c6c75988
JP		 1460 netif_info(gp, link, gp->dev,
1461 "Autoneg failed again, keeping forced mode\n");
1da177e4
LT		 1462 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1463 gp->last_forced_speed, DUPLEX_HALF);
1464 gp->timer_ticks = 5;
1465 gp->lstate = link_force_ok;
1466 return 0;
1467 case link_aneg:
1468 /* We try forced modes after a failed aneg only on PHYs that don't
1469 * have "magic_aneg" bit set, which means they internally do the
1470 * while forced-mode thingy. On these, we just restart aneg
1471 */
1472 if (gp->phy_mii.def->magic_aneg)
1473 return 1;
c6c75988 1474 netif_info(gp, link, gp->dev, "switching to forced 100bt\n");
1da177e4
LT		 1475 /* Try forced modes. */
1476 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1477 DUPLEX_HALF);
1478 gp->timer_ticks = 5;
1479 gp->lstate = link_force_try;
1480 return 0;
1481 case link_force_try:
1482 /* Downgrade from 100 to 10 Mbps if necessary.
1483 * If already at 10Mbps, warn user about the
1484 * situation every 10 ticks.
1485 */
1486 if (gp->phy_mii.speed == SPEED_100) {
1487 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1488 DUPLEX_HALF);
1489 gp->timer_ticks = 5;
c6c75988
JP		 1490 netif_info(gp, link, gp->dev,
1491 "switching to forced 10bt\n");
1da177e4
LT		 1492 return 0;
1493 } else
1494 return 1;
1495 default:
1496 return 0;
1497 }
1498}
1499
1500static void gem_link_timer(unsigned long data)
1501{
1502 struct gem *gp = (struct gem *) data;
1503 int restart_aneg = 0;
6aa20a22 1504
1da177e4
LT		 1505 if (gp->asleep)
1506 return;
1507
1508 spin_lock_irq(&gp->lock);
1509 spin_lock(&gp->tx_lock);
1510 gem_get_cell(gp);
1511
1512 /* If the reset task is still pending, we just
1513 * reschedule the link timer
1514 */
1515 if (gp->reset_task_pending)
1516 goto restart;
6aa20a22 1517
1da177e4
LT		 1518 if (gp->phy_type == phy_serialink ||
1519 gp->phy_type == phy_serdes) {
1520 u32 val = readl(gp->regs + PCS_MIISTAT);
1521
1522 if (!(val & PCS_MIISTAT_LS))
1523 val = readl(gp->regs + PCS_MIISTAT);
1524
1525 if ((val & PCS_MIISTAT_LS) != 0) {
8c83f80b
DM		 1526 if (gp->lstate == link_up)
1527 goto restart;
1528
1da177e4
LT		 1529 gp->lstate = link_up;
1530 netif_carrier_on(gp->dev);
1531 (void)gem_set_link_modes(gp);
1532 }
1533 goto restart;
1534 }
1535 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1536 /* Ok, here we got a link. If we had it due to a forced
1537 * fallback, and we were configured for autoneg, we do
1538 * retry a short autoneg pass. If you know your hub is
1539 * broken, use ethtool ;)
1540 */
1541 if (gp->lstate == link_force_try && gp->want_autoneg) {
1542 gp->lstate = link_force_ret;
1543 gp->last_forced_speed = gp->phy_mii.speed;
1544 gp->timer_ticks = 5;
1545 if (netif_msg_link(gp))
c6c75988
JP		 1546 netdev_info(gp->dev,
1547 "Got link after fallback, retrying autoneg once...\n");
1da177e4
LT		 1548 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1549 } else if (gp->lstate != link_up) {
1550 gp->lstate = link_up;
1551 netif_carrier_on(gp->dev);
1552 if (gem_set_link_modes(gp))
1553 restart_aneg = 1;
1554 }
1555 } else {
1556 /* If the link was previously up, we restart the
1557 * whole process
1558 */
1559 if (gp->lstate == link_up) {
1560 gp->lstate = link_down;
c6c75988 1561 netif_info(gp, link, gp->dev, "Link down\n");
1da177e4
LT		 1562 netif_carrier_off(gp->dev);
1563 gp->reset_task_pending = 1;
1564 schedule_work(&gp->reset_task);
1565 restart_aneg = 1;
1566 } else if (++gp->timer_ticks > 10) {
1567 if (found_mii_phy(gp))
1568 restart_aneg = gem_mdio_link_not_up(gp);
1569 else
1570 restart_aneg = 1;
1571 }
1572 }
1573 if (restart_aneg) {
1574 gem_begin_auto_negotiation(gp, NULL);
1575 goto out_unlock;
1576 }
1577restart:
1578 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1579out_unlock:
1580 gem_put_cell(gp);
1581 spin_unlock(&gp->tx_lock);
1582 spin_unlock_irq(&gp->lock);
1583}
1584
1585/* Must be invoked under gp->lock and gp->tx_lock. */
1586static void gem_clean_rings(struct gem *gp)
1587{
1588 struct gem_init_block *gb = gp->init_block;
1589 struct sk_buff *skb;
1590 int i;
1591 dma_addr_t dma_addr;
1592
1593 for (i = 0; i < RX_RING_SIZE; i++) {
1594 struct gem_rxd *rxd;
1595
1596 rxd = &gb->rxd[i];
1597 if (gp->rx_skbs[i] != NULL) {
1598 skb = gp->rx_skbs[i];
1599 dma_addr = le64_to_cpu(rxd->buffer);
1600 pci_unmap_page(gp->pdev, dma_addr,
1601 RX_BUF_ALLOC_SIZE(gp),
1602 PCI_DMA_FROMDEVICE);
1603 dev_kfree_skb_any(skb);
1604 gp->rx_skbs[i] = NULL;
1605 }
1606 rxd->status_word = 0;
1607 wmb();
1608 rxd->buffer = 0;
1609 }
1610
1611 for (i = 0; i < TX_RING_SIZE; i++) {
1612 if (gp->tx_skbs[i] != NULL) {
1613 struct gem_txd *txd;
1614 int frag;
1615
1616 skb = gp->tx_skbs[i];
1617 gp->tx_skbs[i] = NULL;
1618
1619 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1620 int ent = i & (TX_RING_SIZE - 1);
1621
1622 txd = &gb->txd[ent];
1623 dma_addr = le64_to_cpu(txd->buffer);
1624 pci_unmap_page(gp->pdev, dma_addr,
1625 le64_to_cpu(txd->control_word) &
1626 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1627
1628 if (frag != skb_shinfo(skb)->nr_frags)
1629 i++;
1630 }
1631 dev_kfree_skb_any(skb);
1632 }
1633 }
1634}
1635
1636/* Must be invoked under gp->lock and gp->tx_lock. */
1637static void gem_init_rings(struct gem *gp)
1638{
1639 struct gem_init_block *gb = gp->init_block;
1640 struct net_device *dev = gp->dev;
1641 int i;
1642 dma_addr_t dma_addr;
1643
1644 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1645
1646 gem_clean_rings(gp);
1647
1648 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1649 (unsigned)VLAN_ETH_FRAME_LEN);
1650
1651 for (i = 0; i < RX_RING_SIZE; i++) {
1652 struct sk_buff *skb;
1653 struct gem_rxd *rxd = &gb->rxd[i];
1654
1655 skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
1656 if (!skb) {
1657 rxd->buffer = 0;
1658 rxd->status_word = 0;
1659 continue;
1660 }
1661
1662 gp->rx_skbs[i] = skb;
1663 skb->dev = dev;
1664 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1665 dma_addr = pci_map_page(gp->pdev,
1666 virt_to_page(skb->data),
1667 offset_in_page(skb->data),
1668 RX_BUF_ALLOC_SIZE(gp),
1669 PCI_DMA_FROMDEVICE);
1670 rxd->buffer = cpu_to_le64(dma_addr);
1671 wmb();
1672 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1673 skb_reserve(skb, RX_OFFSET);
1674 }
1675
1676 for (i = 0; i < TX_RING_SIZE; i++) {
1677 struct gem_txd *txd = &gb->txd[i];
1678
1679 txd->control_word = 0;
1680 wmb();
1681 txd->buffer = 0;
1682 }
1683 wmb();
1684}
1685
1686/* Init PHY interface and start link poll state machine */
1687static void gem_init_phy(struct gem *gp)
1688{
7fb76aa0 1689 u32 mifcfg;
1da177e4
LT		 1690
1691 /* Revert MIF CFG setting done on stop_phy */
7fb76aa0
DM		 1692 mifcfg = readl(gp->regs + MIF_CFG);
1693 mifcfg &= ~MIF_CFG_BBMODE;
1694 writel(mifcfg, gp->regs + MIF_CFG);
6aa20a22 1695
1da177e4
LT		 1696 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1697 int i;
1698
7fb76aa0
DM		 1699 /* Those delay sucks, the HW seem to love them though, I'll
1700 * serisouly consider breaking some locks here to be able
1701 * to schedule instead
1702 */
1703 for (i = 0; i < 3; i++) {
1da177e4 1704#ifdef CONFIG_PPC_PMAC
7fb76aa0
DM		 1705 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1706 msleep(20);
1da177e4 1707#endif
7fb76aa0
DM		 1708 /* Some PHYs used by apple have problem getting back to us,
1709 * we do an additional reset here
1710 */
1711 phy_write(gp, MII_BMCR, BMCR_RESET);
1712 msleep(20);
1713 if (phy_read(gp, MII_BMCR) != 0xffff)
1da177e4 1714 break;
7fb76aa0 1715 if (i == 2)
c6c75988 1716 netdev_warn(gp->dev, "GMAC PHY not responding !\n");
1da177e4
LT		 1717 }
1718 }
1719
1720 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1721 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1722 u32 val;
1723
1724 /* Init datapath mode register. */
1725 if (gp->phy_type == phy_mii_mdio0 ||
1726 gp->phy_type == phy_mii_mdio1) {
1727 val = PCS_DMODE_MGM;
1728 } else if (gp->phy_type == phy_serialink) {
1729 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1730 } else {
1731 val = PCS_DMODE_ESM;
1732 }
1733
1734 writel(val, gp->regs + PCS_DMODE);
1735 }
1736
1737 if (gp->phy_type == phy_mii_mdio0 ||
1738 gp->phy_type == phy_mii_mdio1) {
1739 // XXX check for errors
1740 mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1741
1742 /* Init PHY */
1743 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1744 gp->phy_mii.def->ops->init(&gp->phy_mii);
1745 } else {
8c83f80b
DM		 1746 gem_pcs_reset(gp);
1747 gem_pcs_reinit_adv(gp);
1da177e4
LT		 1748 }
1749
1750 /* Default aneg parameters */
1751 gp->timer_ticks = 0;
1752 gp->lstate = link_down;
1753 netif_carrier_off(gp->dev);
1754
1755 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
1756 spin_lock_irq(&gp->lock);
1757 gem_begin_auto_negotiation(gp, NULL);
1758 spin_unlock_irq(&gp->lock);
1759}
1760
1761/* Must be invoked under gp->lock and gp->tx_lock. */
1762static void gem_init_dma(struct gem *gp)
1763{
1764 u64 desc_dma = (u64) gp->gblock_dvma;
1765 u32 val;
1766
1767 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1768 writel(val, gp->regs + TXDMA_CFG);
1769
1770 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1771 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1772 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1773
1774 writel(0, gp->regs + TXDMA_KICK);
1775
1776 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1777 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1778 writel(val, gp->regs + RXDMA_CFG);
1779
1780 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1781 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1782
1783 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1784
1785 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1786 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1787 writel(val, gp->regs + RXDMA_PTHRESH);
1788
1789 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1790 writel(((5 & RXDMA_BLANK_IPKTS) |
1791 ((8 << 12) & RXDMA_BLANK_ITIME)),
1792 gp->regs + RXDMA_BLANK);
1793 else
1794 writel(((5 & RXDMA_BLANK_IPKTS) |
1795 ((4 << 12) & RXDMA_BLANK_ITIME)),
1796 gp->regs + RXDMA_BLANK);
1797}
1798
1799/* Must be invoked under gp->lock and gp->tx_lock. */
1800static u32 gem_setup_multicast(struct gem *gp)
1801{
1802 u32 rxcfg = 0;
1803 int i;
6aa20a22 1804
1da177e4 1805 if ((gp->dev->flags & IFF_ALLMULTI) ||
4cd24eaf 1806 (netdev_mc_count(gp->dev) > 256)) {
1da177e4
LT		 1807 for (i=0; i<16; i++)
1808 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1809 rxcfg |= MAC_RXCFG_HFE;
1810 } else if (gp->dev->flags & IFF_PROMISC) {
1811 rxcfg |= MAC_RXCFG_PROM;
1812 } else {
1813 u16 hash_table[16];
1814 u32 crc;
22bedad3 1815 struct netdev_hw_addr *ha;
1da177e4
LT		 1816 int i;
1817
5508590c 1818 memset(hash_table, 0, sizeof(hash_table));
22bedad3
JP		 1819 netdev_for_each_mc_addr(ha, gp->dev) {
1820 char *addrs = ha->addr;
1da177e4 1821
1da177e4
LT		 1822 if (!(*addrs & 1))
1823 continue;
1824
1825 crc = ether_crc_le(6, addrs);
1826 crc >>= 24;
1827 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1828 }
1829 for (i=0; i<16; i++)
1830 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1831 rxcfg |= MAC_RXCFG_HFE;
1832 }
1833
1834 return rxcfg;
1835}
1836
1837/* Must be invoked under gp->lock and gp->tx_lock. */
1838static void gem_init_mac(struct gem *gp)
1839{
1840 unsigned char *e = &gp->dev->dev_addr[0];
1841
1842 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1843
1844 writel(0x00, gp->regs + MAC_IPG0);
1845 writel(0x08, gp->regs + MAC_IPG1);
1846 writel(0x04, gp->regs + MAC_IPG2);
1847 writel(0x40, gp->regs + MAC_STIME);
1848 writel(0x40, gp->regs + MAC_MINFSZ);
1849
1850 /* Ethernet payload + header + FCS + optional VLAN tag. */
1851 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1852
1853 writel(0x07, gp->regs + MAC_PASIZE);
1854 writel(0x04, gp->regs + MAC_JAMSIZE);
1855 writel(0x10, gp->regs + MAC_ATTLIM);
1856 writel(0x8808, gp->regs + MAC_MCTYPE);
1857
1858 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1859
1860 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1861 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1862 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1863
1864 writel(0, gp->regs + MAC_ADDR3);
1865 writel(0, gp->regs + MAC_ADDR4);
1866 writel(0, gp->regs + MAC_ADDR5);
1867
1868 writel(0x0001, gp->regs + MAC_ADDR6);
1869 writel(0xc200, gp->regs + MAC_ADDR7);
1870 writel(0x0180, gp->regs + MAC_ADDR8);
1871
1872 writel(0, gp->regs + MAC_AFILT0);
1873 writel(0, gp->regs + MAC_AFILT1);
1874 writel(0, gp->regs + MAC_AFILT2);
1875 writel(0, gp->regs + MAC_AF21MSK);
1876 writel(0, gp->regs + MAC_AF0MSK);
1877
1878 gp->mac_rx_cfg = gem_setup_multicast(gp);
1879#ifdef STRIP_FCS
1880 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1881#endif
1882 writel(0, gp->regs + MAC_NCOLL);
1883 writel(0, gp->regs + MAC_FASUCC);
1884 writel(0, gp->regs + MAC_ECOLL);
1885 writel(0, gp->regs + MAC_LCOLL);
1886 writel(0, gp->regs + MAC_DTIMER);
1887 writel(0, gp->regs + MAC_PATMPS);
1888 writel(0, gp->regs + MAC_RFCTR);
1889 writel(0, gp->regs + MAC_LERR);
1890 writel(0, gp->regs + MAC_AERR);
1891 writel(0, gp->regs + MAC_FCSERR);
1892 writel(0, gp->regs + MAC_RXCVERR);
1893
1894 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1895 * them once a link is established.
1896 */
1897 writel(0, gp->regs + MAC_TXCFG);
1898 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1899 writel(0, gp->regs + MAC_MCCFG);
1900 writel(0, gp->regs + MAC_XIFCFG);
1901
1902 /* Setup MAC interrupts. We want to get all of the interesting
1903 * counter expiration events, but we do not want to hear about
1904 * normal rx/tx as the DMA engine tells us that.
1905 */
1906 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1907 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1908
1909 /* Don't enable even the PAUSE interrupts for now, we
1910 * make no use of those events other than to record them.
1911 */
1912 writel(0xffffffff, gp->regs + MAC_MCMASK);
1913
1914 /* Don't enable GEM's WOL in normal operations
1915 */
1916 if (gp->has_wol)
1917 writel(0, gp->regs + WOL_WAKECSR);
1918}
1919
1920/* Must be invoked under gp->lock and gp->tx_lock. */
1921static void gem_init_pause_thresholds(struct gem *gp)
1922{
1923 u32 cfg;
1924
1925 /* Calculate pause thresholds. Setting the OFF threshold to the
1926 * full RX fifo size effectively disables PAUSE generation which
1927 * is what we do for 10/100 only GEMs which have FIFOs too small
1928 * to make real gains from PAUSE.
1929 */
1930 if (gp->rx_fifo_sz <= (2 * 1024)) {
1931 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1932 } else {
1933 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1934 int off = (gp->rx_fifo_sz - (max_frame * 2));
1935 int on = off - max_frame;
1936
1937 gp->rx_pause_off = off;
1938 gp->rx_pause_on = on;
1939 }
1940
1941
1942 /* Configure the chip "burst" DMA mode & enable some
1943 * HW bug fixes on Apple version
1944 */
1945 cfg = 0;
1946 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1947 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1948#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1949 cfg |= GREG_CFG_IBURST;
1950#endif
1951 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1952 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1953 writel(cfg, gp->regs + GREG_CFG);
1954
1955 /* If Infinite Burst didn't stick, then use different
1956 * thresholds (and Apple bug fixes don't exist)
1957 */
1958 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1959 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1960 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1961 writel(cfg, gp->regs + GREG_CFG);
6aa20a22 1962 }
1da177e4
LT		 1963}
1964
1965static int gem_check_invariants(struct gem *gp)
1966{
1967 struct pci_dev *pdev = gp->pdev;
1968 u32 mif_cfg;
1969
1970 /* On Apple's sungem, we can't rely on registers as the chip
1971 * was been powered down by the firmware. The PHY is looked
1972 * up later on.
1973 */
1974 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1975 gp->phy_type = phy_mii_mdio0;
1976 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1977 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1978 gp->swrst_base = 0;
1979
1980 mif_cfg = readl(gp->regs + MIF_CFG);
1981 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
1982 mif_cfg |= MIF_CFG_MDI0;
1983 writel(mif_cfg, gp->regs + MIF_CFG);
1984 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
1985 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
1986
1987 /* We hard-code the PHY address so we can properly bring it out of
1988 * reset later on, we can't really probe it at this point, though
1989 * that isn't an issue.
1990 */
1991 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
1992 gp->mii_phy_addr = 1;
1993 else
1994 gp->mii_phy_addr = 0;
1995
1996 return 0;
1997 }
1998
1999 mif_cfg = readl(gp->regs + MIF_CFG);
2000
2001 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2002 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
2003 /* One of the MII PHYs _must_ be present
2004 * as this chip has no gigabit PHY.
2005 */
2006 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
c6c75988 2007 pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1da177e4
LT		 2008 mif_cfg);
2009 return -1;
2010 }
2011 }
2012
2013 /* Determine initial PHY interface type guess. MDIO1 is the
2014 * external PHY and thus takes precedence over MDIO0.
2015 */
6aa20a22 2016
1da177e4
LT		 2017 if (mif_cfg & MIF_CFG_MDI1) {
2018 gp->phy_type = phy_mii_mdio1;
2019 mif_cfg |= MIF_CFG_PSELECT;
2020 writel(mif_cfg, gp->regs + MIF_CFG);
2021 } else if (mif_cfg & MIF_CFG_MDI0) {
2022 gp->phy_type = phy_mii_mdio0;
2023 mif_cfg &= ~MIF_CFG_PSELECT;
2024 writel(mif_cfg, gp->regs + MIF_CFG);
2025 } else {
e54d5512
DM		 2026#ifdef CONFIG_SPARC
2027 const char *p;
2028
2029 p = of_get_property(gp->of_node, "shared-pins", NULL);
2030 if (p && !strcmp(p, "serdes"))
2031 gp->phy_type = phy_serdes;
2032 else
2033#endif
2034 gp->phy_type = phy_serialink;
1da177e4
LT		 2035 }
2036 if (gp->phy_type == phy_mii_mdio1 ||
2037 gp->phy_type == phy_mii_mdio0) {
2038 int i;
2039
2040 for (i = 0; i < 32; i++) {
2041 gp->mii_phy_addr = i;
2042 if (phy_read(gp, MII_BMCR) != 0xffff)
2043 break;
2044 }
2045 if (i == 32) {
2046 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
c6c75988 2047 pr_err("RIO MII phy will not respond\n");
1da177e4
LT		 2048 return -1;
2049 }
2050 gp->phy_type = phy_serdes;
2051 }
2052 }
2053
2054 /* Fetch the FIFO configurations now too. */
2055 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2056 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2057
2058 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2059 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2060 if (gp->tx_fifo_sz != (9 * 1024) ||
2061 gp->rx_fifo_sz != (20 * 1024)) {
c6c75988 2062 pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",
1da177e4
LT		 2063 gp->tx_fifo_sz, gp->rx_fifo_sz);
2064 return -1;
2065 }
2066 gp->swrst_base = 0;
2067 } else {
2068 if (gp->tx_fifo_sz != (2 * 1024) ||
2069 gp->rx_fifo_sz != (2 * 1024)) {
c6c75988 2070 pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
1da177e4
LT		 2071 gp->tx_fifo_sz, gp->rx_fifo_sz);
2072 return -1;
2073 }
2074 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2075 }
2076 }
2077
2078 return 0;
2079}
2080
2081/* Must be invoked under gp->lock and gp->tx_lock. */
2082static void gem_reinit_chip(struct gem *gp)
2083{
2084 /* Reset the chip */
2085 gem_reset(gp);
2086
2087 /* Make sure ints are disabled */
2088 gem_disable_ints(gp);
2089
2090 /* Allocate & setup ring buffers */
2091 gem_init_rings(gp);
2092
2093 /* Configure pause thresholds */
2094 gem_init_pause_thresholds(gp);
2095
2096 /* Init DMA & MAC engines */
2097 gem_init_dma(gp);
2098 gem_init_mac(gp);
2099}
2100
2101
2102/* Must be invoked with no lock held. */
2103static void gem_stop_phy(struct gem *gp, int wol)
2104{
7fb76aa0 2105 u32 mifcfg;
1da177e4
LT		 2106 unsigned long flags;
2107
2108 /* Let the chip settle down a bit, it seems that helps
2109 * for sleep mode on some models
2110 */
2111 msleep(10);
2112
2113 /* Make sure we aren't polling PHY status change. We
2114 * don't currently use that feature though
2115 */
7fb76aa0
DM		 2116 mifcfg = readl(gp->regs + MIF_CFG);
2117 mifcfg &= ~MIF_CFG_POLL;
2118 writel(mifcfg, gp->regs + MIF_CFG);
1da177e4
LT		 2119
2120 if (wol && gp->has_wol) {
2121 unsigned char *e = &gp->dev->dev_addr[0];
2122 u32 csr;
2123
2124 /* Setup wake-on-lan for MAGIC packet */
2125 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
6aa20a22 2126 gp->regs + MAC_RXCFG);
1da177e4
LT		 2127 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2128 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2129 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2130
2131 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2132 csr = WOL_WAKECSR_ENABLE;
2133 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2134 csr |= WOL_WAKECSR_MII;
2135 writel(csr, gp->regs + WOL_WAKECSR);
2136 } else {
2137 writel(0, gp->regs + MAC_RXCFG);
2138 (void)readl(gp->regs + MAC_RXCFG);
2139 /* Machine sleep will die in strange ways if we
2140 * dont wait a bit here, looks like the chip takes
2141 * some time to really shut down
2142 */
2143 msleep(10);
2144 }
2145
2146 writel(0, gp->regs + MAC_TXCFG);
2147 writel(0, gp->regs + MAC_XIFCFG);
2148 writel(0, gp->regs + TXDMA_CFG);
2149 writel(0, gp->regs + RXDMA_CFG);
2150
2151 if (!wol) {
2152 spin_lock_irqsave(&gp->lock, flags);
2153 spin_lock(&gp->tx_lock);
2154 gem_reset(gp);
2155 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2156 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2157 spin_unlock(&gp->tx_lock);
2158 spin_unlock_irqrestore(&gp->lock, flags);
2159
2160 /* No need to take the lock here */
2161
2162 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2163 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2164
2165 /* According to Apple, we must set the MDIO pins to this begnign
2166 * state or we may 1) eat more current, 2) damage some PHYs
2167 */
7fb76aa0 2168 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
1da177e4
LT		 2169 writel(0, gp->regs + MIF_BBCLK);
2170 writel(0, gp->regs + MIF_BBDATA);
2171 writel(0, gp->regs + MIF_BBOENAB);
2172 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2173 (void) readl(gp->regs + MAC_XIFCFG);
2174 }
2175}
2176
2177
2178static int gem_do_start(struct net_device *dev)
2179{
8f15ea42 2180 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2181 unsigned long flags;
2182
2183 spin_lock_irqsave(&gp->lock, flags);
2184 spin_lock(&gp->tx_lock);
2185
2186 /* Enable the cell */
2187 gem_get_cell(gp);
2188
2189 /* Init & setup chip hardware */
2190 gem_reinit_chip(gp);
2191
2192 gp->running = 1;
2193
71822faa
IV		 2194 napi_enable(&gp->napi);
2195
1da177e4
LT		 2196 if (gp->lstate == link_up) {
2197 netif_carrier_on(gp->dev);
2198 gem_set_link_modes(gp);
2199 }
2200
2201 netif_wake_queue(gp->dev);
2202
2203 spin_unlock(&gp->tx_lock);
2204 spin_unlock_irqrestore(&gp->lock, flags);
2205
2206 if (request_irq(gp->pdev->irq, gem_interrupt,
1fb9df5d 2207 IRQF_SHARED, dev->name, (void *)dev)) {
c6c75988 2208 netdev_err(dev, "failed to request irq !\n");
1da177e4
LT		 2209
2210 spin_lock_irqsave(&gp->lock, flags);
2211 spin_lock(&gp->tx_lock);
2212
71822faa
IV		 2213 napi_disable(&gp->napi);
2214
1da177e4
LT		 2215 gp->running = 0;
2216 gem_reset(gp);
2217 gem_clean_rings(gp);
2218 gem_put_cell(gp);
6aa20a22 2219
1da177e4
LT		 2220 spin_unlock(&gp->tx_lock);
2221 spin_unlock_irqrestore(&gp->lock, flags);
2222
2223 return -EAGAIN;
2224 }
2225
2226 return 0;
2227}
2228
2229static void gem_do_stop(struct net_device *dev, int wol)
2230{
8f15ea42 2231 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2232 unsigned long flags;
2233
2234 spin_lock_irqsave(&gp->lock, flags);
2235 spin_lock(&gp->tx_lock);
2236
2237 gp->running = 0;
2238
2239 /* Stop netif queue */
2240 netif_stop_queue(dev);
2241
2242 /* Make sure ints are disabled */
2243 gem_disable_ints(gp);
2244
2245 /* We can drop the lock now */
2246 spin_unlock(&gp->tx_lock);
2247 spin_unlock_irqrestore(&gp->lock, flags);
2248
2249 /* If we are going to sleep with WOL */
2250 gem_stop_dma(gp);
2251 msleep(10);
2252 if (!wol)
2253 gem_reset(gp);
2254 msleep(10);
2255
2256 /* Get rid of rings */
2257 gem_clean_rings(gp);
2258
2259 /* No irq needed anymore */
2260 free_irq(gp->pdev->irq, (void *) dev);
2261
2262 /* Cell not needed neither if no WOL */
2263 if (!wol) {
2264 spin_lock_irqsave(&gp->lock, flags);
2265 gem_put_cell(gp);
2266 spin_unlock_irqrestore(&gp->lock, flags);
2267 }
2268}
2269
c4028958 2270static void gem_reset_task(struct work_struct *work)
1da177e4 2271{
c4028958 2272 struct gem *gp = container_of(work, struct gem, reset_task);
1da177e4 2273
e3968fc0 2274 mutex_lock(&gp->pm_mutex);
1da177e4 2275
dde655c9
JB		 2276 if (gp->opened)
2277 napi_disable(&gp->napi);
1da177e4
LT		 2278
2279 spin_lock_irq(&gp->lock);
2280 spin_lock(&gp->tx_lock);
2281
1da177e4
LT		 2282 if (gp->running) {
2283 netif_stop_queue(gp->dev);
2284
2285 /* Reset the chip & rings */
2286 gem_reinit_chip(gp);
2287 if (gp->lstate == link_up)
2288 gem_set_link_modes(gp);
2289 netif_wake_queue(gp->dev);
2290 }
dde655c9 2291
1da177e4
LT		 2292 gp->reset_task_pending = 0;
2293
2294 spin_unlock(&gp->tx_lock);
2295 spin_unlock_irq(&gp->lock);
2296
dde655c9
JB		 2297 if (gp->opened)
2298 napi_enable(&gp->napi);
1da177e4 2299
e3968fc0 2300 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2301}
2302
2303
2304static int gem_open(struct net_device *dev)
2305{
8f15ea42 2306 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2307 int rc = 0;
2308
e3968fc0 2309 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2310
2311 /* We need the cell enabled */
2312 if (!gp->asleep)
2313 rc = gem_do_start(dev);
2314 gp->opened = (rc == 0);
2315
e3968fc0 2316 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2317
2318 return rc;
2319}
2320
2321static int gem_close(struct net_device *dev)
2322{
8f15ea42 2323 struct gem *gp = netdev_priv(dev);
1da177e4 2324
e3968fc0 2325 mutex_lock(&gp->pm_mutex);
1da177e4 2326
62768e28
JB		 2327 napi_disable(&gp->napi);
2328
6aa20a22 2329 gp->opened = 0;
1da177e4
LT		 2330 if (!gp->asleep)
2331 gem_do_stop(dev, 0);
2332
e3968fc0 2333 mutex_unlock(&gp->pm_mutex);
6aa20a22 2334
1da177e4
LT		 2335 return 0;
2336}
2337
2338#ifdef CONFIG_PM
2339static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2340{
2341 struct net_device *dev = pci_get_drvdata(pdev);
8f15ea42 2342 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2343 unsigned long flags;
2344
e3968fc0 2345 mutex_lock(&gp->pm_mutex);
1da177e4 2346
c6c75988
JP		 2347 netdev_info(dev, "suspending, WakeOnLan %s\n",
2348 (gp->wake_on_lan && gp->opened) ? "enabled" : "disabled");
6aa20a22 2349
1da177e4
LT		 2350 /* Keep the cell enabled during the entire operation */
2351 spin_lock_irqsave(&gp->lock, flags);
2352 spin_lock(&gp->tx_lock);
2353 gem_get_cell(gp);
2354 spin_unlock(&gp->tx_lock);
2355 spin_unlock_irqrestore(&gp->lock, flags);
2356
2357 /* If the driver is opened, we stop the MAC */
2358 if (gp->opened) {
62768e28
JB		 2359 napi_disable(&gp->napi);
2360
1da177e4
LT		 2361 /* Stop traffic, mark us closed */
2362 netif_device_detach(dev);
2363
2364 /* Switch off MAC, remember WOL setting */
2365 gp->asleep_wol = gp->wake_on_lan;
2366 gem_do_stop(dev, gp->asleep_wol);
2367 } else
2368 gp->asleep_wol = 0;
2369
2370 /* Mark us asleep */
2371 gp->asleep = 1;
2372 wmb();
2373
2374 /* Stop the link timer */
2375 del_timer_sync(&gp->link_timer);
2376
e3968fc0 2377 /* Now we release the mutex to not block the reset task who
1da177e4
LT		 2378 * can take it too. We are marked asleep, so there will be no
2379 * conflict here
2380 */
e3968fc0 2381 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2382
2383 /* Wait for a pending reset task to complete */
2384 while (gp->reset_task_pending)
2385 yield();
2386 flush_scheduled_work();
2387
2388 /* Shut the PHY down eventually and setup WOL */
2389 gem_stop_phy(gp, gp->asleep_wol);
2390
2391 /* Make sure bus master is disabled */
2392 pci_disable_device(gp->pdev);
2393
2394 /* Release the cell, no need to take a lock at this point since
2395 * nothing else can happen now
2396 */
2397 gem_put_cell(gp);
2398
2399 return 0;
2400}
2401
2402static int gem_resume(struct pci_dev *pdev)
2403{
2404 struct net_device *dev = pci_get_drvdata(pdev);
8f15ea42 2405 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2406 unsigned long flags;
2407
c6c75988 2408 netdev_info(dev, "resuming\n");
1da177e4 2409
e3968fc0 2410 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2411
2412 /* Keep the cell enabled during the entire operation, no need to
2413 * take a lock here tho since nothing else can happen while we are
2414 * marked asleep
2415 */
2416 gem_get_cell(gp);
2417
2418 /* Make sure PCI access and bus master are enabled */
2419 if (pci_enable_device(gp->pdev)) {
c6c75988 2420 netdev_err(dev, "Can't re-enable chip !\n");
1da177e4
LT		 2421 /* Put cell and forget it for now, it will be considered as
2422 * still asleep, a new sleep cycle may bring it back
2423 */
2424 gem_put_cell(gp);
e3968fc0 2425 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2426 return 0;
2427 }
2428 pci_set_master(gp->pdev);
2429
2430 /* Reset everything */
2431 gem_reset(gp);
2432
2433 /* Mark us woken up */
2434 gp->asleep = 0;
2435 wmb();
2436
2437 /* Bring the PHY back. Again, lock is useless at this point as
2438 * nothing can be happening until we restart the whole thing
2439 */
2440 gem_init_phy(gp);
2441
2442 /* If we were opened, bring everything back */
2443 if (gp->opened) {
2444 /* Restart MAC */
2445 gem_do_start(dev);
2446
2447 /* Re-attach net device */
2448 netif_device_attach(dev);
1da177e4
LT		 2449 }
2450
2451 spin_lock_irqsave(&gp->lock, flags);
2452 spin_lock(&gp->tx_lock);
2453
2454 /* If we had WOL enabled, the cell clock was never turned off during
2455 * sleep, so we end up beeing unbalanced. Fix that here
2456 */
2457 if (gp->asleep_wol)
2458 gem_put_cell(gp);
2459
2460 /* This function doesn't need to hold the cell, it will be held if the
2461 * driver is open by gem_do_start().
2462 */
2463 gem_put_cell(gp);
2464
2465 spin_unlock(&gp->tx_lock);
2466 spin_unlock_irqrestore(&gp->lock, flags);
2467
e3968fc0 2468 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2469
2470 return 0;
2471}
2472#endif /* CONFIG_PM */
2473
2474static struct net_device_stats *gem_get_stats(struct net_device *dev)
2475{
8f15ea42 2476 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2477 struct net_device_stats *stats = &gp->net_stats;
2478
2479 spin_lock_irq(&gp->lock);
2480 spin_lock(&gp->tx_lock);
2481
2482 /* I have seen this being called while the PM was in progress,
2483 * so we shield against this
2484 */
2485 if (gp->running) {
2486 stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2487 writel(0, gp->regs + MAC_FCSERR);
2488
2489 stats->rx_frame_errors += readl(gp->regs + MAC_AERR);
2490 writel(0, gp->regs + MAC_AERR);
2491
2492 stats->rx_length_errors += readl(gp->regs + MAC_LERR);
2493 writel(0, gp->regs + MAC_LERR);
2494
2495 stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2496 stats->collisions +=
2497 (readl(gp->regs + MAC_ECOLL) +
2498 readl(gp->regs + MAC_LCOLL));
2499 writel(0, gp->regs + MAC_ECOLL);
2500 writel(0, gp->regs + MAC_LCOLL);
2501 }
2502
2503 spin_unlock(&gp->tx_lock);
2504 spin_unlock_irq(&gp->lock);
2505
2506 return &gp->net_stats;
2507}
2508
09c72ec8
RV		 2509static int gem_set_mac_address(struct net_device *dev, void *addr)
2510{
2511 struct sockaddr *macaddr = (struct sockaddr *) addr;
8f15ea42 2512 struct gem *gp = netdev_priv(dev);
09c72ec8
RV		 2513 unsigned char *e = &dev->dev_addr[0];
2514
2515 if (!is_valid_ether_addr(macaddr->sa_data))
2516 return -EADDRNOTAVAIL;
2517
2518 if (!netif_running(dev) || !netif_device_present(dev)) {
2519 /* We'll just catch it later when the
2520 * device is up'd or resumed.
2521 */
2522 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2523 return 0;
2524 }
2525
2526 mutex_lock(&gp->pm_mutex);
2527 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2528 if (gp->running) {
2529 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2530 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2531 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2532 }
2533 mutex_unlock(&gp->pm_mutex);
2534
2535 return 0;
2536}
2537
1da177e4
LT		 2538static void gem_set_multicast(struct net_device *dev)
2539{
8f15ea42 2540 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2541 u32 rxcfg, rxcfg_new;
2542 int limit = 10000;
6aa20a22 2543
1da177e4
LT		 2544
2545 spin_lock_irq(&gp->lock);
2546 spin_lock(&gp->tx_lock);
2547
2548 if (!gp->running)
2549 goto bail;
2550
2551 netif_stop_queue(dev);
2552
2553 rxcfg = readl(gp->regs + MAC_RXCFG);
2554 rxcfg_new = gem_setup_multicast(gp);
2555#ifdef STRIP_FCS
2556 rxcfg_new |= MAC_RXCFG_SFCS;
2557#endif
2558 gp->mac_rx_cfg = rxcfg_new;
6aa20a22 2559
1da177e4
LT		 2560 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2561 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2562 if (!limit--)
2563 break;
2564 udelay(10);
2565 }
2566
2567 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2568 rxcfg |= rxcfg_new;
2569
2570 writel(rxcfg, gp->regs + MAC_RXCFG);
2571
2572 netif_wake_queue(dev);
2573
2574 bail:
2575 spin_unlock(&gp->tx_lock);
2576 spin_unlock_irq(&gp->lock);
2577}
2578
2579/* Jumbo-grams don't seem to work :-( */
2580#define GEM_MIN_MTU 68
2581#if 1
2582#define GEM_MAX_MTU 1500
2583#else
2584#define GEM_MAX_MTU 9000
2585#endif
2586
2587static int gem_change_mtu(struct net_device *dev, int new_mtu)
2588{
8f15ea42 2589 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2590
2591 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
2592 return -EINVAL;
2593
2594 if (!netif_running(dev) || !netif_device_present(dev)) {
2595 /* We'll just catch it later when the
2596 * device is up'd or resumed.
2597 */
2598 dev->mtu = new_mtu;
2599 return 0;
2600 }
2601
e3968fc0 2602 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2603 spin_lock_irq(&gp->lock);
2604 spin_lock(&gp->tx_lock);
2605 dev->mtu = new_mtu;
2606 if (gp->running) {
2607 gem_reinit_chip(gp);
2608 if (gp->lstate == link_up)
2609 gem_set_link_modes(gp);
2610 }
2611 spin_unlock(&gp->tx_lock);
2612 spin_unlock_irq(&gp->lock);
e3968fc0 2613 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2614
2615 return 0;
2616}
2617
2618static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2619{
8f15ea42 2620 struct gem *gp = netdev_priv(dev);
6aa20a22 2621
1da177e4
LT		 2622 strcpy(info->driver, DRV_NAME);
2623 strcpy(info->version, DRV_VERSION);
2624 strcpy(info->bus_info, pci_name(gp->pdev));
2625}
6aa20a22 2626
1da177e4
LT		 2627static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2628{
8f15ea42 2629 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2630
2631 if (gp->phy_type == phy_mii_mdio0 ||
2632 gp->phy_type == phy_mii_mdio1) {
2633 if (gp->phy_mii.def)
2634 cmd->supported = gp->phy_mii.def->features;
2635 else
2636 cmd->supported = (SUPPORTED_10baseT_Half |
2637 SUPPORTED_10baseT_Full);
2638
2639 /* XXX hardcoded stuff for now */
2640 cmd->port = PORT_MII;
2641 cmd->transceiver = XCVR_EXTERNAL;
2642 cmd->phy_address = 0; /* XXX fixed PHYAD */
2643
2644 /* Return current PHY settings */
2645 spin_lock_irq(&gp->lock);
2646 cmd->autoneg = gp->want_autoneg;
2647 cmd->speed = gp->phy_mii.speed;
6aa20a22 2648 cmd->duplex = gp->phy_mii.duplex;
1da177e4
LT		 2649 cmd->advertising = gp->phy_mii.advertising;
2650
2651 /* If we started with a forced mode, we don't have a default
2652 * advertise set, we need to return something sensible so
2653 * userland can re-enable autoneg properly.
2654 */
2655 if (cmd->advertising == 0)
2656 cmd->advertising = cmd->supported;
2657 spin_unlock_irq(&gp->lock);
2658 } else { // XXX PCS ?
2659 cmd->supported =
2660 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2661 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2662 SUPPORTED_Autoneg);
2663 cmd->advertising = cmd->supported;
2664 cmd->speed = 0;
2665 cmd->duplex = cmd->port = cmd->phy_address =
2666 cmd->transceiver = cmd->autoneg = 0;
fbf0229e
HL		 2667
2668 /* serdes means usually a Fibre connector, with most fixed */
2669 if (gp->phy_type == phy_serdes) {
2670 cmd->port = PORT_FIBRE;
2671 cmd->supported = (SUPPORTED_1000baseT_Half |
2672 SUPPORTED_1000baseT_Full |
2673 SUPPORTED_FIBRE | SUPPORTED_Autoneg |
2674 SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2675 cmd->advertising = cmd->supported;
2676 cmd->transceiver = XCVR_INTERNAL;
2677 if (gp->lstate == link_up)
2678 cmd->speed = SPEED_1000;
2679 cmd->duplex = DUPLEX_FULL;
2680 cmd->autoneg = 1;
2681 }
1da177e4
LT		 2682 }
2683 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2684
2685 return 0;
2686}
2687
2688static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2689{
8f15ea42 2690 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2691
2692 /* Verify the settings we care about. */
2693 if (cmd->autoneg != AUTONEG_ENABLE &&
2694 cmd->autoneg != AUTONEG_DISABLE)
2695 return -EINVAL;
2696
2697 if (cmd->autoneg == AUTONEG_ENABLE &&
2698 cmd->advertising == 0)
2699 return -EINVAL;
2700
2701 if (cmd->autoneg == AUTONEG_DISABLE &&
2702 ((cmd->speed != SPEED_1000 &&
2703 cmd->speed != SPEED_100 &&
2704 cmd->speed != SPEED_10) ||
2705 (cmd->duplex != DUPLEX_HALF &&
2706 cmd->duplex != DUPLEX_FULL)))
2707 return -EINVAL;
6aa20a22 2708
1da177e4
LT		 2709 /* Apply settings and restart link process. */
2710 spin_lock_irq(&gp->lock);
2711 gem_get_cell(gp);
2712 gem_begin_auto_negotiation(gp, cmd);
2713 gem_put_cell(gp);
2714 spin_unlock_irq(&gp->lock);
2715
2716 return 0;
2717}
2718
2719static int gem_nway_reset(struct net_device *dev)
2720{
8f15ea42 2721 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2722
2723 if (!gp->want_autoneg)
2724 return -EINVAL;
2725
2726 /* Restart link process. */
2727 spin_lock_irq(&gp->lock);
2728 gem_get_cell(gp);
2729 gem_begin_auto_negotiation(gp, NULL);
2730 gem_put_cell(gp);
2731 spin_unlock_irq(&gp->lock);
2732
2733 return 0;
2734}
2735
2736static u32 gem_get_msglevel(struct net_device *dev)
2737{
8f15ea42 2738 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2739 return gp->msg_enable;
2740}
6aa20a22 2741
1da177e4
LT		 2742static void gem_set_msglevel(struct net_device *dev, u32 value)
2743{
8f15ea42 2744 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2745 gp->msg_enable = value;
2746}
2747
2748
2749/* Add more when I understand how to program the chip */
2750/* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2751
2752#define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2753
2754static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2755{
8f15ea42 2756 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2757
2758 /* Add more when I understand how to program the chip */
2759 if (gp->has_wol) {
2760 wol->supported = WOL_SUPPORTED_MASK;
2761 wol->wolopts = gp->wake_on_lan;
2762 } else {
2763 wol->supported = 0;
2764 wol->wolopts = 0;
2765 }
2766}
2767
2768static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2769{
8f15ea42 2770 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2771
2772 if (!gp->has_wol)
2773 return -EOPNOTSUPP;
2774 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2775 return 0;
2776}
2777
7282d491 2778static const struct ethtool_ops gem_ethtool_ops = {
1da177e4
LT		 2779 .get_drvinfo = gem_get_drvinfo,
2780 .get_link = ethtool_op_get_link,
2781 .get_settings = gem_get_settings,
2782 .set_settings = gem_set_settings,
2783 .nway_reset = gem_nway_reset,
2784 .get_msglevel = gem_get_msglevel,
2785 .set_msglevel = gem_set_msglevel,
2786 .get_wol = gem_get_wol,
2787 .set_wol = gem_set_wol,
2788};
2789
2790static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2791{
8f15ea42 2792 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2793 struct mii_ioctl_data *data = if_mii(ifr);
2794 int rc = -EOPNOTSUPP;
2795 unsigned long flags;
2796
e3968fc0 2797 /* Hold the PM mutex while doing ioctl's or we may collide
1da177e4
LT		 2798 * with power management.
2799 */
e3968fc0 2800 mutex_lock(&gp->pm_mutex);
6aa20a22 2801
1da177e4
LT		 2802 spin_lock_irqsave(&gp->lock, flags);
2803 gem_get_cell(gp);
2804 spin_unlock_irqrestore(&gp->lock, flags);
2805
2806 switch (cmd) {
2807 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2808 data->phy_id = gp->mii_phy_addr;
2809 /* Fallthrough... */
2810
2811 case SIOCGMIIREG: /* Read MII PHY register. */
2812 if (!gp->running)
2813 rc = -EAGAIN;
2814 else {
2815 data->val_out = __phy_read(gp, data->phy_id & 0x1f,
2816 data->reg_num & 0x1f);
2817 rc = 0;
2818 }
2819 break;
2820
2821 case SIOCSMIIREG: /* Write MII PHY register. */
7ab0f273 2822 if (!gp->running)
1da177e4
LT		 2823 rc = -EAGAIN;
2824 else {
2825 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2826 data->val_in);
2827 rc = 0;
2828 }
2829 break;
2830 };
6aa20a22 2831
1da177e4
LT		 2832 spin_lock_irqsave(&gp->lock, flags);
2833 gem_put_cell(gp);
2834 spin_unlock_irqrestore(&gp->lock, flags);
2835
e3968fc0 2836 mutex_unlock(&gp->pm_mutex);
6aa20a22 2837
1da177e4
LT		 2838 return rc;
2839}
2840
dadb830d 2841#if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
1da177e4 2842/* Fetch MAC address from vital product data of PCI ROM. */
4120b028 2843static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
1da177e4
LT		 2844{
2845 int this_offset;
2846
2847 for (this_offset = 0x20; this_offset < len; this_offset++) {
2848 void __iomem *p = rom_base + this_offset;
2849 int i;
2850
2851 if (readb(p + 0) != 0x90 ||
2852 readb(p + 1) != 0x00 ||
2853 readb(p + 2) != 0x09 ||
2854 readb(p + 3) != 0x4e ||
2855 readb(p + 4) != 0x41 ||
2856 readb(p + 5) != 0x06)
2857 continue;
2858
2859 this_offset += 6;
2860 p += 6;
2861
2862 for (i = 0; i < 6; i++)
2863 dev_addr[i] = readb(p + i);
4120b028 2864 return 1;
1da177e4 2865 }
4120b028 2866 return 0;
1da177e4
LT		 2867}
2868
2869static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2870{
4120b028
LT		 2871 size_t size;
2872 void __iomem *p = pci_map_rom(pdev, &size);
1da177e4 2873
4120b028
LT		 2874 if (p) {
2875 int found;
1da177e4 2876
4120b028
LT		 2877 found = readb(p) == 0x55 &&
2878 readb(p + 1) == 0xaa &&
2879 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2880 pci_unmap_rom(pdev, p);
2881 if (found)
2882 return;
2883 }
1da177e4 2884
1da177e4
LT		 2885 /* Sun MAC prefix then 3 random bytes. */
2886 dev_addr[0] = 0x08;
2887 dev_addr[1] = 0x00;
2888 dev_addr[2] = 0x20;
2889 get_random_bytes(dev_addr + 3, 3);
1da177e4
LT		 2890}
2891#endif /* not Sparc and not PPC */
2892
2893static int __devinit gem_get_device_address(struct gem *gp)
2894{
dadb830d 2895#if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
1da177e4 2896 struct net_device *dev = gp->dev;
1a2509c9 2897 const unsigned char *addr;
1da177e4 2898
40cd3a45 2899 addr = of_get_property(gp->of_node, "local-mac-address", NULL);
1da177e4 2900 if (addr == NULL) {
457e1a8a
DM		 2901#ifdef CONFIG_SPARC
2902 addr = idprom->id_ethaddr;
2903#else
1da177e4 2904 printk("\n");
c6c75988 2905 pr_err("%s: can't get mac-address\n", dev->name);
1da177e4 2906 return -1;
457e1a8a 2907#endif
1da177e4
LT		 2908 }
2909 memcpy(dev->dev_addr, addr, 6);
2910#else
2911 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2912#endif
2913 return 0;
2914}
2915
14904398 2916static void gem_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2917{
2918 struct net_device *dev = pci_get_drvdata(pdev);
2919
2920 if (dev) {
8f15ea42 2921 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2922
2923 unregister_netdev(dev);
2924
2925 /* Stop the link timer */
2926 del_timer_sync(&gp->link_timer);
2927
2928 /* We shouldn't need any locking here */
2929 gem_get_cell(gp);
2930
2931 /* Wait for a pending reset task to complete */
2932 while (gp->reset_task_pending)
2933 yield();
2934 flush_scheduled_work();
2935
2936 /* Shut the PHY down */
2937 gem_stop_phy(gp, 0);
2938
2939 gem_put_cell(gp);
2940
2941 /* Make sure bus master is disabled */
2942 pci_disable_device(gp->pdev);
2943
2944 /* Free resources */
2945 pci_free_consistent(pdev,
2946 sizeof(struct gem_init_block),
2947 gp->init_block,
2948 gp->gblock_dvma);
2949 iounmap(gp->regs);
2950 pci_release_regions(pdev);
2951 free_netdev(dev);
2952
2953 pci_set_drvdata(pdev, NULL);
2954 }
2955}
2956
d9a811d5
SH		 2957static const struct net_device_ops gem_netdev_ops = {
2958 .ndo_open = gem_open,
2959 .ndo_stop = gem_close,
2960 .ndo_start_xmit = gem_start_xmit,
2961 .ndo_get_stats = gem_get_stats,
2962 .ndo_set_multicast_list = gem_set_multicast,
2963 .ndo_do_ioctl = gem_ioctl,
2964 .ndo_tx_timeout = gem_tx_timeout,
2965 .ndo_change_mtu = gem_change_mtu,
d9a811d5 2966 .ndo_validate_addr = eth_validate_addr,
5ed0102f
SH		 2967 .ndo_set_mac_address = gem_set_mac_address,
2968#ifdef CONFIG_NET_POLL_CONTROLLER
2969 .ndo_poll_controller = gem_poll_controller,
2970#endif
d9a811d5
SH		 2971};
2972
1da177e4
LT		 2973static int __devinit gem_init_one(struct pci_dev *pdev,
2974 const struct pci_device_id *ent)
2975{
1da177e4
LT		 2976 unsigned long gemreg_base, gemreg_len;
2977 struct net_device *dev;
2978 struct gem *gp;
0795af57 2979 int err, pci_using_dac;
1da177e4 2980
c6c75988 2981 printk_once(KERN_INFO "%s", version);
1da177e4
LT		 2982
2983 /* Apple gmac note: during probe, the chip is powered up by
2984 * the arch code to allow the code below to work (and to let
2985 * the chip be probed on the config space. It won't stay powered
2986 * up until the interface is brought up however, so we can't rely
2987 * on register configuration done at this point.
2988 */
2989 err = pci_enable_device(pdev);
2990 if (err) {
c6c75988 2991 pr_err("Cannot enable MMIO operation, aborting\n");
1da177e4
LT		 2992 return err;
2993 }
2994 pci_set_master(pdev);
2995
2996 /* Configure DMA attributes. */
2997
2998 /* All of the GEM documentation states that 64-bit DMA addressing
2999 * is fully supported and should work just fine. However the
3000 * front end for RIO based GEMs is different and only supports
3001 * 32-bit addressing.
3002 *
3003 * For now we assume the various PPC GEMs are 32-bit only as well.
3004 */
3005 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
3006 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
6a35528a 3007 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4
LT		 3008 pci_using_dac = 1;
3009 } else {
284901a9 3010 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3011 if (err) {
c6c75988 3012 pr_err("No usable DMA configuration, aborting\n");
1da177e4
LT		 3013 goto err_disable_device;
3014 }
3015 pci_using_dac = 0;
3016 }
6aa20a22 3017
1da177e4
LT		 3018 gemreg_base = pci_resource_start(pdev, 0);
3019 gemreg_len = pci_resource_len(pdev, 0);
3020
3021 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
c6c75988 3022 pr_err("Cannot find proper PCI device base address, aborting\n");
1da177e4
LT		 3023 err = -ENODEV;
3024 goto err_disable_device;
3025 }
3026
3027 dev = alloc_etherdev(sizeof(*gp));
3028 if (!dev) {
c6c75988 3029 pr_err("Etherdev alloc failed, aborting\n");
1da177e4
LT		 3030 err = -ENOMEM;
3031 goto err_disable_device;
3032 }
1da177e4
LT		 3033 SET_NETDEV_DEV(dev, &pdev->dev);
3034
8f15ea42 3035 gp = netdev_priv(dev);
1da177e4
LT		 3036
3037 err = pci_request_regions(pdev, DRV_NAME);
3038 if (err) {
c6c75988 3039 pr_err("Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 3040 goto err_out_free_netdev;
3041 }
3042
3043 gp->pdev = pdev;
3044 dev->base_addr = (long) pdev;
3045 gp->dev = dev;
3046
3047 gp->msg_enable = DEFAULT_MSG;
3048
3049 spin_lock_init(&gp->lock);
3050 spin_lock_init(&gp->tx_lock);
e3968fc0 3051 mutex_init(&gp->pm_mutex);
1da177e4
LT		 3052
3053 init_timer(&gp->link_timer);
3054 gp->link_timer.function = gem_link_timer;
3055 gp->link_timer.data = (unsigned long) gp;
3056
c4028958 3057 INIT_WORK(&gp->reset_task, gem_reset_task);
6aa20a22 3058
1da177e4
LT		 3059 gp->lstate = link_down;
3060 gp->timer_ticks = 0;
3061 netif_carrier_off(dev);
3062
3063 gp->regs = ioremap(gemreg_base, gemreg_len);
79ea13ce 3064 if (!gp->regs) {
c6c75988 3065 pr_err("Cannot map device registers, aborting\n");
1da177e4
LT		 3066 err = -EIO;
3067 goto err_out_free_res;
3068 }
3069
3070 /* On Apple, we want a reference to the Open Firmware device-tree
3071 * node. We use it for clock control.
3072 */
457e1a8a 3073#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
1da177e4
LT		 3074 gp->of_node = pci_device_to_OF_node(pdev);
3075#endif
3076
3077 /* Only Apple version supports WOL afaik */
3078 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
3079 gp->has_wol = 1;
3080
3081 /* Make sure cell is enabled */
3082 gem_get_cell(gp);
3083
3084 /* Make sure everything is stopped and in init state */
3085 gem_reset(gp);
3086
3087 /* Fill up the mii_phy structure (even if we won't use it) */
3088 gp->phy_mii.dev = dev;
3089 gp->phy_mii.mdio_read = _phy_read;
3090 gp->phy_mii.mdio_write = _phy_write;
3c326fe9
BH		 3091#ifdef CONFIG_PPC_PMAC
3092 gp->phy_mii.platform_data = gp->of_node;
3093#endif
1da177e4
LT		 3094 /* By default, we start with autoneg */
3095 gp->want_autoneg = 1;
3096
3097 /* Check fifo sizes, PHY type, etc... */
3098 if (gem_check_invariants(gp)) {
3099 err = -ENODEV;
3100 goto err_out_iounmap;
3101 }
3102
3103 /* It is guaranteed that the returned buffer will be at least
3104 * PAGE_SIZE aligned.
3105 */
3106 gp->init_block = (struct gem_init_block *)
3107 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
3108 &gp->gblock_dvma);
3109 if (!gp->init_block) {
c6c75988 3110 pr_err("Cannot allocate init block, aborting\n");
1da177e4
LT		 3111 err = -ENOMEM;
3112 goto err_out_iounmap;
3113 }
3114
3115 if (gem_get_device_address(gp))
3116 goto err_out_free_consistent;
3117
d9a811d5 3118 dev->netdev_ops = &gem_netdev_ops;
bea3348e 3119 netif_napi_add(dev, &gp->napi, gem_poll, 64);
1da177e4 3120 dev->ethtool_ops = &gem_ethtool_ops;
1da177e4 3121 dev->watchdog_timeo = 5 * HZ;
1da177e4
LT		 3122 dev->irq = pdev->irq;
3123 dev->dma = 0;
1da177e4
LT		 3124
3125 /* Set that now, in case PM kicks in now */
3126 pci_set_drvdata(pdev, dev);
3127
3128 /* Detect & init PHY, start autoneg, we release the cell now
3129 * too, it will be managed by whoever needs it
3130 */
3131 gem_init_phy(gp);
3132
3133 spin_lock_irq(&gp->lock);
3134 gem_put_cell(gp);
3135 spin_unlock_irq(&gp->lock);
3136
3137 /* Register with kernel */
3138 if (register_netdev(dev)) {
c6c75988 3139 pr_err("Cannot register net device, aborting\n");
1da177e4
LT		 3140 err = -ENOMEM;
3141 goto err_out_free_consistent;
3142 }
3143
c6c75988
JP		 3144 netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
3145 dev->dev_addr);
1da177e4
LT		 3146
3147 if (gp->phy_type == phy_mii_mdio0 ||
3148 gp->phy_type == phy_mii_mdio1)
c6c75988
JP		 3149 netdev_info(dev, "Found %s PHY\n",
3150 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
1da177e4
LT		 3151
3152 /* GEM can do it all... */
3153 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_LLTX;
3154 if (pci_using_dac)
3155 dev->features |= NETIF_F_HIGHDMA;
3156
3157 return 0;
3158
3159err_out_free_consistent:
3160 gem_remove_one(pdev);
3161err_out_iounmap:
3162 gem_put_cell(gp);
3163 iounmap(gp->regs);
3164
3165err_out_free_res:
3166 pci_release_regions(pdev);
3167
3168err_out_free_netdev:
3169 free_netdev(dev);
3170err_disable_device:
3171 pci_disable_device(pdev);
3172 return err;
3173
3174}
3175
3176
3177static struct pci_driver gem_driver = {
3178 .name = GEM_MODULE_NAME,
3179 .id_table = gem_pci_tbl,
3180 .probe = gem_init_one,
14904398 3181 .remove = gem_remove_one,
1da177e4
LT		 3182#ifdef CONFIG_PM
3183 .suspend = gem_suspend,
3184 .resume = gem_resume,
3185#endif /* CONFIG_PM */
3186};
3187
3188static int __init gem_init(void)
3189{
29917620 3190 return pci_register_driver(&gem_driver);
1da177e4
LT		 3191}
3192
3193static void __exit gem_cleanup(void)
3194{
3195 pci_unregister_driver(&gem_driver);
3196}
3197
3198module_init(gem_init);
3199module_exit(gem_cleanup);
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