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atm nicstar: Removal of debug code containing deprecated calls to cli()/sti()
[net-next-2.6.git] / drivers / net / sungem.c
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1da177e4
LT		 1/* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
6aa20a22 5 *
1da177e4
LT		 6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
9 *
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
6aa20a22
JG		 12 *
13 * TODO:
1da177e4
LT		 14 * - Now that the driver was significantly simplified, I need to rework
15 * the locking. I'm sure we don't need _2_ spinlocks, and we probably
16 * can avoid taking most of them for so long period of time (and schedule
17 * instead). The main issues at this point are caused by the netdev layer
18 * though:
6aa20a22 19 *
1da177e4
LT		 20 * gem_change_mtu() and gem_set_multicast() are called with a read_lock()
21 * help by net/core/dev.c, thus they can't schedule. That means they can't
bea3348e 22 * call napi_disable() neither, thus force gem_poll() to keep a spinlock
1da177e4
LT		 23 * where it could have been dropped. change_mtu especially would love also to
24 * be able to msleep instead of horrid locked delays when resetting the HW,
25 * but that read_lock() makes it impossible, unless I defer it's action to
26 * the reset task, which means it'll be asynchronous (won't take effect until
27 * the system schedules a bit).
28 *
29 * Also, it would probably be possible to also remove most of the long-life
30 * locking in open/resume code path (gem_reinit_chip) by beeing more careful
31 * about when we can start taking interrupts or get xmit() called...
32 */
33
34#include <linux/module.h>
35#include <linux/kernel.h>
36#include <linux/types.h>
37#include <linux/fcntl.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/in.h>
41#include <linux/slab.h>
42#include <linux/string.h>
43#include <linux/delay.h>
44#include <linux/init.h>
45#include <linux/errno.h>
46#include <linux/pci.h>
1e7f0bd8 47#include <linux/dma-mapping.h>
1da177e4
LT		 48#include <linux/netdevice.h>
49#include <linux/etherdevice.h>
50#include <linux/skbuff.h>
51#include <linux/mii.h>
52#include <linux/ethtool.h>
53#include <linux/crc32.h>
54#include <linux/random.h>
55#include <linux/workqueue.h>
56#include <linux/if_vlan.h>
57#include <linux/bitops.h>
e3968fc0 58#include <linux/mutex.h>
d7fe0f24 59#include <linux/mm.h>
1da177e4
LT		 60
61#include <asm/system.h>
62#include <asm/io.h>
63#include <asm/byteorder.h>
64#include <asm/uaccess.h>
65#include <asm/irq.h>
66
dadb830d 67#ifdef CONFIG_SPARC
1da177e4 68#include <asm/idprom.h>
457e1a8a 69#include <asm/prom.h>
1da177e4
LT		 70#endif
71
72#ifdef CONFIG_PPC_PMAC
73#include <asm/pci-bridge.h>
74#include <asm/prom.h>
75#include <asm/machdep.h>
76#include <asm/pmac_feature.h>
77#endif
78
79#include "sungem_phy.h"
80#include "sungem.h"
81
82/* Stripping FCS is causing problems, disabled for now */
83#undef STRIP_FCS
84
85#define DEFAULT_MSG (NETIF_MSG_DRV | \
86 NETIF_MSG_PROBE | \
87 NETIF_MSG_LINK)
88
89#define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
90 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
63ea998a
BH		 91 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
92 SUPPORTED_Pause | SUPPORTED_Autoneg)
1da177e4
LT		 93
94#define DRV_NAME "sungem"
95#define DRV_VERSION "0.98"
96#define DRV_RELDATE "8/24/03"
97#define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
98
99static char version[] __devinitdata =
100 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
101
102MODULE_AUTHOR(DRV_AUTHOR);
103MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
104MODULE_LICENSE("GPL");
105
106#define GEM_MODULE_NAME "gem"
107#define PFX GEM_MODULE_NAME ": "
108
109static struct pci_device_id gem_pci_tbl[] = {
110 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
112
113 /* These models only differ from the original GEM in
114 * that their tx/rx fifos are of a different size and
115 * they only support 10/100 speeds. -DaveM
6aa20a22 116 *
1da177e4
LT		 117 * Apple's GMAC does support gigabit on machines with
118 * the BCM54xx PHYs. -BenH
119 */
120 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
122 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
124 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
126 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
128 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
130 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7fce260a
OJ		 132 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 134 {0, }
135};
136
137MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
138
139static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
140{
141 u32 cmd;
142 int limit = 10000;
143
144 cmd = (1 << 30);
145 cmd |= (2 << 28);
146 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
147 cmd |= (reg << 18) & MIF_FRAME_REGAD;
148 cmd |= (MIF_FRAME_TAMSB);
149 writel(cmd, gp->regs + MIF_FRAME);
150
151 while (limit--) {
152 cmd = readl(gp->regs + MIF_FRAME);
153 if (cmd & MIF_FRAME_TALSB)
154 break;
155
156 udelay(10);
157 }
158
159 if (!limit)
160 cmd = 0xffff;
161
162 return cmd & MIF_FRAME_DATA;
163}
164
165static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
166{
167 struct gem *gp = dev->priv;
168 return __phy_read(gp, mii_id, reg);
169}
170
171static inline u16 phy_read(struct gem *gp, int reg)
172{
173 return __phy_read(gp, gp->mii_phy_addr, reg);
174}
175
176static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
177{
178 u32 cmd;
179 int limit = 10000;
180
181 cmd = (1 << 30);
182 cmd |= (1 << 28);
183 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
184 cmd |= (reg << 18) & MIF_FRAME_REGAD;
185 cmd |= (MIF_FRAME_TAMSB);
186 cmd |= (val & MIF_FRAME_DATA);
187 writel(cmd, gp->regs + MIF_FRAME);
188
189 while (limit--) {
190 cmd = readl(gp->regs + MIF_FRAME);
191 if (cmd & MIF_FRAME_TALSB)
192 break;
193
194 udelay(10);
195 }
196}
197
198static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
199{
200 struct gem *gp = dev->priv;
201 __phy_write(gp, mii_id, reg, val & 0xffff);
202}
203
204static inline void phy_write(struct gem *gp, int reg, u16 val)
205{
206 __phy_write(gp, gp->mii_phy_addr, reg, val);
207}
208
209static inline void gem_enable_ints(struct gem *gp)
210{
211 /* Enable all interrupts but TXDONE */
212 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
213}
214
215static inline void gem_disable_ints(struct gem *gp)
216{
217 /* Disable all interrupts, including TXDONE */
218 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
219}
220
221static void gem_get_cell(struct gem *gp)
222{
223 BUG_ON(gp->cell_enabled < 0);
224 gp->cell_enabled++;
225#ifdef CONFIG_PPC_PMAC
226 if (gp->cell_enabled == 1) {
227 mb();
228 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
229 udelay(10);
230 }
231#endif /* CONFIG_PPC_PMAC */
232}
233
234/* Turn off the chip's clock */
235static void gem_put_cell(struct gem *gp)
236{
237 BUG_ON(gp->cell_enabled <= 0);
238 gp->cell_enabled--;
239#ifdef CONFIG_PPC_PMAC
240 if (gp->cell_enabled == 0) {
241 mb();
242 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
243 udelay(10);
244 }
245#endif /* CONFIG_PPC_PMAC */
246}
247
248static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
249{
250 if (netif_msg_intr(gp))
251 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
252}
253
254static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
255{
256 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
257 u32 pcs_miistat;
258
259 if (netif_msg_intr(gp))
260 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
261 gp->dev->name, pcs_istat);
262
263 if (!(pcs_istat & PCS_ISTAT_LSC)) {
264 printk(KERN_ERR "%s: PCS irq but no link status change???\n",
265 dev->name);
266 return 0;
267 }
268
269 /* The link status bit latches on zero, so you must
270 * read it twice in such a case to see a transition
271 * to the link being up.
272 */
273 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
274 if (!(pcs_miistat & PCS_MIISTAT_LS))
275 pcs_miistat |=
276 (readl(gp->regs + PCS_MIISTAT) &
277 PCS_MIISTAT_LS);
278
279 if (pcs_miistat & PCS_MIISTAT_ANC) {
280 /* The remote-fault indication is only valid
281 * when autoneg has completed.
282 */
283 if (pcs_miistat & PCS_MIISTAT_RF)
284 printk(KERN_INFO "%s: PCS AutoNEG complete, "
285 "RemoteFault\n", dev->name);
286 else
287 printk(KERN_INFO "%s: PCS AutoNEG complete.\n",
288 dev->name);
289 }
290
291 if (pcs_miistat & PCS_MIISTAT_LS) {
292 printk(KERN_INFO "%s: PCS link is now up.\n",
293 dev->name);
294 netif_carrier_on(gp->dev);
295 } else {
296 printk(KERN_INFO "%s: PCS link is now down.\n",
297 dev->name);
298 netif_carrier_off(gp->dev);
299 /* If this happens and the link timer is not running,
300 * reset so we re-negotiate.
301 */
302 if (!timer_pending(&gp->link_timer))
303 return 1;
304 }
305
306 return 0;
307}
308
309static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
310{
311 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
312
313 if (netif_msg_intr(gp))
314 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
315 gp->dev->name, txmac_stat);
316
317 /* Defer timer expiration is quite normal,
318 * don't even log the event.
319 */
320 if ((txmac_stat & MAC_TXSTAT_DTE) &&
321 !(txmac_stat & ~MAC_TXSTAT_DTE))
322 return 0;
323
324 if (txmac_stat & MAC_TXSTAT_URUN) {
325 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
326 dev->name);
327 gp->net_stats.tx_fifo_errors++;
328 }
329
330 if (txmac_stat & MAC_TXSTAT_MPE) {
331 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
332 dev->name);
333 gp->net_stats.tx_errors++;
334 }
335
336 /* The rest are all cases of one of the 16-bit TX
337 * counters expiring.
338 */
339 if (txmac_stat & MAC_TXSTAT_NCE)
340 gp->net_stats.collisions += 0x10000;
341
342 if (txmac_stat & MAC_TXSTAT_ECE) {
343 gp->net_stats.tx_aborted_errors += 0x10000;
344 gp->net_stats.collisions += 0x10000;
345 }
346
347 if (txmac_stat & MAC_TXSTAT_LCE) {
348 gp->net_stats.tx_aborted_errors += 0x10000;
349 gp->net_stats.collisions += 0x10000;
350 }
351
352 /* We do not keep track of MAC_TXSTAT_FCE and
353 * MAC_TXSTAT_PCE events.
354 */
355 return 0;
356}
357
358/* When we get a RX fifo overflow, the RX unit in GEM is probably hung
359 * so we do the following.
360 *
361 * If any part of the reset goes wrong, we return 1 and that causes the
362 * whole chip to be reset.
363 */
364static int gem_rxmac_reset(struct gem *gp)
365{
366 struct net_device *dev = gp->dev;
367 int limit, i;
368 u64 desc_dma;
369 u32 val;
370
371 /* First, reset & disable MAC RX. */
372 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
373 for (limit = 0; limit < 5000; limit++) {
374 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
375 break;
376 udelay(10);
377 }
378 if (limit == 5000) {
379 printk(KERN_ERR "%s: RX MAC will not reset, resetting whole "
380 "chip.\n", dev->name);
381 return 1;
382 }
383
384 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
385 gp->regs + MAC_RXCFG);
386 for (limit = 0; limit < 5000; limit++) {
387 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
388 break;
389 udelay(10);
390 }
391 if (limit == 5000) {
392 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
393 "chip.\n", dev->name);
394 return 1;
395 }
396
397 /* Second, disable RX DMA. */
398 writel(0, gp->regs + RXDMA_CFG);
399 for (limit = 0; limit < 5000; limit++) {
400 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
401 break;
402 udelay(10);
403 }
404 if (limit == 5000) {
405 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
406 "chip.\n", dev->name);
407 return 1;
408 }
409
410 udelay(5000);
411
412 /* Execute RX reset command. */
413 writel(gp->swrst_base | GREG_SWRST_RXRST,
414 gp->regs + GREG_SWRST);
415 for (limit = 0; limit < 5000; limit++) {
416 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
417 break;
418 udelay(10);
419 }
420 if (limit == 5000) {
421 printk(KERN_ERR "%s: RX reset command will not execute, resetting "
422 "whole chip.\n", dev->name);
423 return 1;
424 }
425
426 /* Refresh the RX ring. */
427 for (i = 0; i < RX_RING_SIZE; i++) {
428 struct gem_rxd *rxd = &gp->init_block->rxd[i];
429
430 if (gp->rx_skbs[i] == NULL) {
431 printk(KERN_ERR "%s: Parts of RX ring empty, resetting "
432 "whole chip.\n", dev->name);
433 return 1;
434 }
435
436 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
437 }
438 gp->rx_new = gp->rx_old = 0;
439
440 /* Now we must reprogram the rest of RX unit. */
441 desc_dma = (u64) gp->gblock_dvma;
442 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
443 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
444 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
445 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
446 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
447 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
448 writel(val, gp->regs + RXDMA_CFG);
449 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
450 writel(((5 & RXDMA_BLANK_IPKTS) |
451 ((8 << 12) & RXDMA_BLANK_ITIME)),
452 gp->regs + RXDMA_BLANK);
453 else
454 writel(((5 & RXDMA_BLANK_IPKTS) |
455 ((4 << 12) & RXDMA_BLANK_ITIME)),
456 gp->regs + RXDMA_BLANK);
457 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
458 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
459 writel(val, gp->regs + RXDMA_PTHRESH);
460 val = readl(gp->regs + RXDMA_CFG);
461 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
462 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
463 val = readl(gp->regs + MAC_RXCFG);
464 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
465
466 return 0;
467}
468
469static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
470{
471 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
472 int ret = 0;
473
474 if (netif_msg_intr(gp))
475 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
476 gp->dev->name, rxmac_stat);
477
478 if (rxmac_stat & MAC_RXSTAT_OFLW) {
479 u32 smac = readl(gp->regs + MAC_SMACHINE);
480
481 printk(KERN_ERR "%s: RX MAC fifo overflow smac[%08x].\n",
482 dev->name, smac);
483 gp->net_stats.rx_over_errors++;
484 gp->net_stats.rx_fifo_errors++;
485
486 ret = gem_rxmac_reset(gp);
487 }
488
489 if (rxmac_stat & MAC_RXSTAT_ACE)
490 gp->net_stats.rx_frame_errors += 0x10000;
491
492 if (rxmac_stat & MAC_RXSTAT_CCE)
493 gp->net_stats.rx_crc_errors += 0x10000;
494
495 if (rxmac_stat & MAC_RXSTAT_LCE)
496 gp->net_stats.rx_length_errors += 0x10000;
497
498 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
499 * events.
500 */
501 return ret;
502}
503
504static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
505{
506 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
507
508 if (netif_msg_intr(gp))
509 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
510 gp->dev->name, mac_cstat);
511
512 /* This interrupt is just for pause frame and pause
513 * tracking. It is useful for diagnostics and debug
514 * but probably by default we will mask these events.
515 */
516 if (mac_cstat & MAC_CSTAT_PS)
517 gp->pause_entered++;
518
519 if (mac_cstat & MAC_CSTAT_PRCV)
520 gp->pause_last_time_recvd = (mac_cstat >> 16);
521
522 return 0;
523}
524
525static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
526{
527 u32 mif_status = readl(gp->regs + MIF_STATUS);
528 u32 reg_val, changed_bits;
529
530 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
531 changed_bits = (mif_status & MIF_STATUS_STAT);
532
533 gem_handle_mif_event(gp, reg_val, changed_bits);
534
535 return 0;
536}
537
538static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
539{
540 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
541
542 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
543 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
544 printk(KERN_ERR "%s: PCI error [%04x] ",
545 dev->name, pci_estat);
546
547 if (pci_estat & GREG_PCIESTAT_BADACK)
548 printk("<No ACK64# during ABS64 cycle> ");
549 if (pci_estat & GREG_PCIESTAT_DTRTO)
550 printk("<Delayed transaction timeout> ");
551 if (pci_estat & GREG_PCIESTAT_OTHER)
552 printk("<other>");
553 printk("\n");
554 } else {
555 pci_estat |= GREG_PCIESTAT_OTHER;
556 printk(KERN_ERR "%s: PCI error\n", dev->name);
557 }
558
559 if (pci_estat & GREG_PCIESTAT_OTHER) {
560 u16 pci_cfg_stat;
561
562 /* Interrogate PCI config space for the
563 * true cause.
564 */
565 pci_read_config_word(gp->pdev, PCI_STATUS,
566 &pci_cfg_stat);
567 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
568 dev->name, pci_cfg_stat);
569 if (pci_cfg_stat & PCI_STATUS_PARITY)
570 printk(KERN_ERR "%s: PCI parity error detected.\n",
571 dev->name);
572 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
573 printk(KERN_ERR "%s: PCI target abort.\n",
574 dev->name);
575 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
576 printk(KERN_ERR "%s: PCI master acks target abort.\n",
577 dev->name);
578 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
579 printk(KERN_ERR "%s: PCI master abort.\n",
580 dev->name);
581 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
582 printk(KERN_ERR "%s: PCI system error SERR#.\n",
583 dev->name);
584 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
585 printk(KERN_ERR "%s: PCI parity error.\n",
586 dev->name);
587
588 /* Write the error bits back to clear them. */
589 pci_cfg_stat &= (PCI_STATUS_PARITY |
590 PCI_STATUS_SIG_TARGET_ABORT |
591 PCI_STATUS_REC_TARGET_ABORT |
592 PCI_STATUS_REC_MASTER_ABORT |
593 PCI_STATUS_SIG_SYSTEM_ERROR |
594 PCI_STATUS_DETECTED_PARITY);
595 pci_write_config_word(gp->pdev,
596 PCI_STATUS, pci_cfg_stat);
597 }
598
599 /* For all PCI errors, we should reset the chip. */
600 return 1;
601}
602
603/* All non-normal interrupt conditions get serviced here.
604 * Returns non-zero if we should just exit the interrupt
605 * handler right now (ie. if we reset the card which invalidates
606 * all of the other original irq status bits).
607 */
608static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
609{
610 if (gem_status & GREG_STAT_RXNOBUF) {
611 /* Frame arrived, no free RX buffers available. */
612 if (netif_msg_rx_err(gp))
613 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
614 gp->dev->name);
615 gp->net_stats.rx_dropped++;
616 }
617
618 if (gem_status & GREG_STAT_RXTAGERR) {
619 /* corrupt RX tag framing */
620 if (netif_msg_rx_err(gp))
621 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
622 gp->dev->name);
623 gp->net_stats.rx_errors++;
624
625 goto do_reset;
626 }
627
628 if (gem_status & GREG_STAT_PCS) {
629 if (gem_pcs_interrupt(dev, gp, gem_status))
630 goto do_reset;
631 }
632
633 if (gem_status & GREG_STAT_TXMAC) {
634 if (gem_txmac_interrupt(dev, gp, gem_status))
635 goto do_reset;
636 }
637
638 if (gem_status & GREG_STAT_RXMAC) {
639 if (gem_rxmac_interrupt(dev, gp, gem_status))
640 goto do_reset;
641 }
642
643 if (gem_status & GREG_STAT_MAC) {
644 if (gem_mac_interrupt(dev, gp, gem_status))
645 goto do_reset;
646 }
647
648 if (gem_status & GREG_STAT_MIF) {
649 if (gem_mif_interrupt(dev, gp, gem_status))
650 goto do_reset;
651 }
652
653 if (gem_status & GREG_STAT_PCIERR) {
654 if (gem_pci_interrupt(dev, gp, gem_status))
655 goto do_reset;
656 }
657
658 return 0;
659
660do_reset:
661 gp->reset_task_pending = 1;
662 schedule_work(&gp->reset_task);
663
664 return 1;
665}
666
667static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
668{
669 int entry, limit;
670
671 if (netif_msg_intr(gp))
672 printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n",
673 gp->dev->name, gem_status);
674
675 entry = gp->tx_old;
676 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
677 while (entry != limit) {
678 struct sk_buff *skb;
679 struct gem_txd *txd;
680 dma_addr_t dma_addr;
681 u32 dma_len;
682 int frag;
683
684 if (netif_msg_tx_done(gp))
685 printk(KERN_DEBUG "%s: tx done, slot %d\n",
686 gp->dev->name, entry);
687 skb = gp->tx_skbs[entry];
688 if (skb_shinfo(skb)->nr_frags) {
689 int last = entry + skb_shinfo(skb)->nr_frags;
690 int walk = entry;
691 int incomplete = 0;
692
693 last &= (TX_RING_SIZE - 1);
694 for (;;) {
695 walk = NEXT_TX(walk);
696 if (walk == limit)
697 incomplete = 1;
698 if (walk == last)
699 break;
700 }
701 if (incomplete)
702 break;
703 }
704 gp->tx_skbs[entry] = NULL;
705 gp->net_stats.tx_bytes += skb->len;
706
707 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
708 txd = &gp->init_block->txd[entry];
709
710 dma_addr = le64_to_cpu(txd->buffer);
711 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
712
713 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
714 entry = NEXT_TX(entry);
715 }
716
717 gp->net_stats.tx_packets++;
718 dev_kfree_skb_irq(skb);
719 }
720 gp->tx_old = entry;
721
722 if (netif_queue_stopped(dev) &&
723 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
724 netif_wake_queue(dev);
725}
726
727static __inline__ void gem_post_rxds(struct gem *gp, int limit)
728{
729 int cluster_start, curr, count, kick;
730
731 cluster_start = curr = (gp->rx_new & ~(4 - 1));
732 count = 0;
733 kick = -1;
734 wmb();
735 while (curr != limit) {
736 curr = NEXT_RX(curr);
737 if (++count == 4) {
738 struct gem_rxd *rxd =
739 &gp->init_block->rxd[cluster_start];
740 for (;;) {
741 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
742 rxd++;
743 cluster_start = NEXT_RX(cluster_start);
744 if (cluster_start == curr)
745 break;
746 }
747 kick = curr;
748 count = 0;
749 }
750 }
751 if (kick >= 0) {
752 mb();
753 writel(kick, gp->regs + RXDMA_KICK);
754 }
755}
756
757static int gem_rx(struct gem *gp, int work_to_do)
758{
759 int entry, drops, work_done = 0;
760 u32 done;
439104b3 761 __sum16 csum;
1da177e4
LT		 762
763 if (netif_msg_rx_status(gp))
764 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
765 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
766
767 entry = gp->rx_new;
768 drops = 0;
769 done = readl(gp->regs + RXDMA_DONE);
770 for (;;) {
771 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
772 struct sk_buff *skb;
439104b3 773 u64 status = le64_to_cpu(rxd->status_word);
1da177e4
LT		 774 dma_addr_t dma_addr;
775 int len;
776
777 if ((status & RXDCTRL_OWN) != 0)
778 break;
779
780 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
781 break;
782
783 /* When writing back RX descriptor, GEM writes status
784 * then buffer address, possibly in seperate transactions.
785 * If we don't wait for the chip to write both, we could
786 * post a new buffer to this descriptor then have GEM spam
787 * on the buffer address. We sync on the RX completion
788 * register to prevent this from happening.
789 */
790 if (entry == done) {
791 done = readl(gp->regs + RXDMA_DONE);
792 if (entry == done)
793 break;
794 }
795
796 /* We can now account for the work we're about to do */
797 work_done++;
798
799 skb = gp->rx_skbs[entry];
800
801 len = (status & RXDCTRL_BUFSZ) >> 16;
802 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
803 gp->net_stats.rx_errors++;
804 if (len < ETH_ZLEN)
805 gp->net_stats.rx_length_errors++;
806 if (len & RXDCTRL_BAD)
807 gp->net_stats.rx_crc_errors++;
808
809 /* We'll just return it to GEM. */
810 drop_it:
811 gp->net_stats.rx_dropped++;
812 goto next;
813 }
814
439104b3 815 dma_addr = le64_to_cpu(rxd->buffer);
1da177e4
LT		 816 if (len > RX_COPY_THRESHOLD) {
817 struct sk_buff *new_skb;
818
819 new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
820 if (new_skb == NULL) {
821 drops++;
822 goto drop_it;
823 }
824 pci_unmap_page(gp->pdev, dma_addr,
825 RX_BUF_ALLOC_SIZE(gp),
826 PCI_DMA_FROMDEVICE);
827 gp->rx_skbs[entry] = new_skb;
828 new_skb->dev = gp->dev;
829 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
830 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
831 virt_to_page(new_skb->data),
832 offset_in_page(new_skb->data),
833 RX_BUF_ALLOC_SIZE(gp),
834 PCI_DMA_FROMDEVICE));
835 skb_reserve(new_skb, RX_OFFSET);
836
837 /* Trim the original skb for the netif. */
838 skb_trim(skb, len);
839 } else {
840 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
841
842 if (copy_skb == NULL) {
843 drops++;
844 goto drop_it;
845 }
846
1da177e4
LT		 847 skb_reserve(copy_skb, 2);
848 skb_put(copy_skb, len);
849 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 850 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 851 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
852
853 /* We'll reuse the original ring buffer. */
854 skb = copy_skb;
855 }
856
439104b3
AV		 857 csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
858 skb->csum = csum_unfold(csum);
84fa7933 859 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 860 skb->protocol = eth_type_trans(skb, gp->dev);
861
862 netif_receive_skb(skb);
863
864 gp->net_stats.rx_packets++;
865 gp->net_stats.rx_bytes += len;
866 gp->dev->last_rx = jiffies;
867
868 next:
869 entry = NEXT_RX(entry);
870 }
871
872 gem_post_rxds(gp, entry);
873
874 gp->rx_new = entry;
875
876 if (drops)
877 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
878 gp->dev->name);
879
880 return work_done;
881}
882
bea3348e 883static int gem_poll(struct napi_struct *napi, int budget)
1da177e4 884{
bea3348e
SH		 885 struct gem *gp = container_of(napi, struct gem, napi);
886 struct net_device *dev = gp->dev;
1da177e4 887 unsigned long flags;
bea3348e 888 int work_done;
1da177e4
LT		 889
890 /*
6aa20a22 891 * NAPI locking nightmare: See comment at head of driver
1da177e4
LT		 892 */
893 spin_lock_irqsave(&gp->lock, flags);
894
bea3348e 895 work_done = 0;
1da177e4 896 do {
1da177e4
LT		 897 /* Handle anomalies */
898 if (gp->status & GREG_STAT_ABNORMAL) {
899 if (gem_abnormal_irq(dev, gp, gp->status))
900 break;
901 }
902
903 /* Run TX completion thread */
904 spin_lock(&gp->tx_lock);
905 gem_tx(dev, gp, gp->status);
906 spin_unlock(&gp->tx_lock);
907
908 spin_unlock_irqrestore(&gp->lock, flags);
909
6aa20a22
JG		 910 /* Run RX thread. We don't use any locking here,
911 * code willing to do bad things - like cleaning the
bea3348e 912 * rx ring - must call napi_disable(), which
1da177e4
LT		 913 * schedule_timeout()'s if polling is already disabled.
914 */
da990a24 915 work_done += gem_rx(gp, budget - work_done);
1da177e4 916
bea3348e
SH		 917 if (work_done >= budget)
918 return work_done;
1da177e4
LT		 919
920 spin_lock_irqsave(&gp->lock, flags);
6aa20a22 921
1da177e4
LT		 922 gp->status = readl(gp->regs + GREG_STAT);
923 } while (gp->status & GREG_STAT_NAPI);
924
bea3348e 925 __netif_rx_complete(dev, napi);
1da177e4
LT		 926 gem_enable_ints(gp);
927
928 spin_unlock_irqrestore(&gp->lock, flags);
bea3348e
SH		 929
930 return work_done;
1da177e4
LT		 931}
932
7d12e780 933static irqreturn_t gem_interrupt(int irq, void *dev_id)
1da177e4
LT		 934{
935 struct net_device *dev = dev_id;
936 struct gem *gp = dev->priv;
937 unsigned long flags;
938
939 /* Swallow interrupts when shutting the chip down, though
940 * that shouldn't happen, we should have done free_irq() at
941 * this point...
942 */
943 if (!gp->running)
944 return IRQ_HANDLED;
945
946 spin_lock_irqsave(&gp->lock, flags);
6aa20a22 947
bea3348e 948 if (netif_rx_schedule_prep(dev, &gp->napi)) {
1da177e4
LT		 949 u32 gem_status = readl(gp->regs + GREG_STAT);
950
951 if (gem_status == 0) {
bea3348e 952 napi_enable(&gp->napi);
1da177e4
LT		 953 spin_unlock_irqrestore(&gp->lock, flags);
954 return IRQ_NONE;
955 }
956 gp->status = gem_status;
957 gem_disable_ints(gp);
bea3348e 958 __netif_rx_schedule(dev, &gp->napi);
1da177e4
LT		 959 }
960
961 spin_unlock_irqrestore(&gp->lock, flags);
6aa20a22 962
1da177e4 963 /* If polling was disabled at the time we received that
6aa20a22 964 * interrupt, we may return IRQ_HANDLED here while we
1da177e4
LT		 965 * should return IRQ_NONE. No big deal...
966 */
967 return IRQ_HANDLED;
968}
969
970#ifdef CONFIG_NET_POLL_CONTROLLER
971static void gem_poll_controller(struct net_device *dev)
972{
973 /* gem_interrupt is safe to reentrance so no need
974 * to disable_irq here.
975 */
7d12e780 976 gem_interrupt(dev->irq, dev);
1da177e4
LT		 977}
978#endif
979
980static void gem_tx_timeout(struct net_device *dev)
981{
982 struct gem *gp = dev->priv;
983
984 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
985 if (!gp->running) {
986 printk("%s: hrm.. hw not running !\n", dev->name);
987 return;
988 }
989 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x]\n",
990 dev->name,
991 readl(gp->regs + TXDMA_CFG),
992 readl(gp->regs + MAC_TXSTAT),
993 readl(gp->regs + MAC_TXCFG));
994 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
995 dev->name,
996 readl(gp->regs + RXDMA_CFG),
997 readl(gp->regs + MAC_RXSTAT),
998 readl(gp->regs + MAC_RXCFG));
999
1000 spin_lock_irq(&gp->lock);
1001 spin_lock(&gp->tx_lock);
1002
1003 gp->reset_task_pending = 1;
1004 schedule_work(&gp->reset_task);
1005
1006 spin_unlock(&gp->tx_lock);
1007 spin_unlock_irq(&gp->lock);
1008}
1009
1010static __inline__ int gem_intme(int entry)
1011{
1012 /* Algorithm: IRQ every 1/2 of descriptors. */
1013 if (!(entry & ((TX_RING_SIZE>>1)-1)))
1014 return 1;
1015
1016 return 0;
1017}
1018
1019static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
1020{
1021 struct gem *gp = dev->priv;
1022 int entry;
1023 u64 ctrl;
1024 unsigned long flags;
1025
1026 ctrl = 0;
84fa7933 1027 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d
ACM		 1028 const u64 csum_start_off = skb_transport_offset(skb);
1029 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
1da177e4
LT		 1030
1031 ctrl = (TXDCTRL_CENAB |
1032 (csum_start_off << 15) |
1033 (csum_stuff_off << 21));
1034 }
1035
1036 local_irq_save(flags);
1037 if (!spin_trylock(&gp->tx_lock)) {
1038 /* Tell upper layer to requeue */
1039 local_irq_restore(flags);
1040 return NETDEV_TX_LOCKED;
1041 }
1042 /* We raced with gem_do_stop() */
1043 if (!gp->running) {
1044 spin_unlock_irqrestore(&gp->tx_lock, flags);
1045 return NETDEV_TX_BUSY;
1046 }
1047
1048 /* This is a hard error, log it. */
1049 if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
1050 netif_stop_queue(dev);
1051 spin_unlock_irqrestore(&gp->tx_lock, flags);
1052 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
1053 dev->name);
1054 return NETDEV_TX_BUSY;
1055 }
1056
1057 entry = gp->tx_new;
1058 gp->tx_skbs[entry] = skb;
1059
1060 if (skb_shinfo(skb)->nr_frags == 0) {
1061 struct gem_txd *txd = &gp->init_block->txd[entry];
1062 dma_addr_t mapping;
1063 u32 len;
1064
1065 len = skb->len;
1066 mapping = pci_map_page(gp->pdev,
1067 virt_to_page(skb->data),
1068 offset_in_page(skb->data),
1069 len, PCI_DMA_TODEVICE);
1070 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1071 if (gem_intme(entry))
1072 ctrl |= TXDCTRL_INTME;
1073 txd->buffer = cpu_to_le64(mapping);
1074 wmb();
1075 txd->control_word = cpu_to_le64(ctrl);
1076 entry = NEXT_TX(entry);
1077 } else {
1078 struct gem_txd *txd;
1079 u32 first_len;
1080 u64 intme;
1081 dma_addr_t first_mapping;
1082 int frag, first_entry = entry;
1083
1084 intme = 0;
1085 if (gem_intme(entry))
1086 intme |= TXDCTRL_INTME;
1087
1088 /* We must give this initial chunk to the device last.
1089 * Otherwise we could race with the device.
1090 */
1091 first_len = skb_headlen(skb);
1092 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1093 offset_in_page(skb->data),
1094 first_len, PCI_DMA_TODEVICE);
1095 entry = NEXT_TX(entry);
1096
1097 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1098 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1099 u32 len;
1100 dma_addr_t mapping;
1101 u64 this_ctrl;
1102
1103 len = this_frag->size;
1104 mapping = pci_map_page(gp->pdev,
1105 this_frag->page,
1106 this_frag->page_offset,
1107 len, PCI_DMA_TODEVICE);
1108 this_ctrl = ctrl;
1109 if (frag == skb_shinfo(skb)->nr_frags - 1)
1110 this_ctrl |= TXDCTRL_EOF;
6aa20a22 1111
1da177e4
LT		 1112 txd = &gp->init_block->txd[entry];
1113 txd->buffer = cpu_to_le64(mapping);
1114 wmb();
1115 txd->control_word = cpu_to_le64(this_ctrl | len);
1116
1117 if (gem_intme(entry))
1118 intme |= TXDCTRL_INTME;
1119
1120 entry = NEXT_TX(entry);
1121 }
1122 txd = &gp->init_block->txd[first_entry];
1123 txd->buffer = cpu_to_le64(first_mapping);
1124 wmb();
1125 txd->control_word =
1126 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1127 }
1128
1129 gp->tx_new = entry;
1130 if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))
1131 netif_stop_queue(dev);
1132
1133 if (netif_msg_tx_queued(gp))
1134 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1135 dev->name, entry, skb->len);
1136 mb();
1137 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1138 spin_unlock_irqrestore(&gp->tx_lock, flags);
1139
1140 dev->trans_start = jiffies;
1141
1142 return NETDEV_TX_OK;
1143}
1144
1145#define STOP_TRIES 32
1146
1147/* Must be invoked under gp->lock and gp->tx_lock. */
1148static void gem_reset(struct gem *gp)
1149{
1150 int limit;
1151 u32 val;
1152
1153 /* Make sure we won't get any more interrupts */
1154 writel(0xffffffff, gp->regs + GREG_IMASK);
1155
1156 /* Reset the chip */
1157 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1158 gp->regs + GREG_SWRST);
1159
1160 limit = STOP_TRIES;
1161
1162 do {
1163 udelay(20);
1164 val = readl(gp->regs + GREG_SWRST);
1165 if (limit-- <= 0)
1166 break;
1167 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1168
1169 if (limit <= 0)
1170 printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name);
1171}
1172
1173/* Must be invoked under gp->lock and gp->tx_lock. */
1174static void gem_start_dma(struct gem *gp)
1175{
1176 u32 val;
6aa20a22 1177
1da177e4
LT		 1178 /* We are ready to rock, turn everything on. */
1179 val = readl(gp->regs + TXDMA_CFG);
1180 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1181 val = readl(gp->regs + RXDMA_CFG);
1182 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1183 val = readl(gp->regs + MAC_TXCFG);
1184 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1185 val = readl(gp->regs + MAC_RXCFG);
1186 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1187
1188 (void) readl(gp->regs + MAC_RXCFG);
1189 udelay(100);
1190
1191 gem_enable_ints(gp);
1192
1193 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1194}
1195
1196/* Must be invoked under gp->lock and gp->tx_lock. DMA won't be
1197 * actually stopped before about 4ms tho ...
1198 */
1199static void gem_stop_dma(struct gem *gp)
1200{
1201 u32 val;
1202
1203 /* We are done rocking, turn everything off. */
1204 val = readl(gp->regs + TXDMA_CFG);
1205 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1206 val = readl(gp->regs + RXDMA_CFG);
1207 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1208 val = readl(gp->regs + MAC_TXCFG);
1209 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1210 val = readl(gp->regs + MAC_RXCFG);
1211 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1212
1213 (void) readl(gp->regs + MAC_RXCFG);
1214
1215 /* Need to wait a bit ... done by the caller */
1216}
1217
1218
1219/* Must be invoked under gp->lock and gp->tx_lock. */
1220// XXX dbl check what that function should do when called on PCS PHY
1221static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1222{
1223 u32 advertise, features;
1224 int autoneg;
1225 int speed;
1226 int duplex;
1227
1228 if (gp->phy_type != phy_mii_mdio0 &&
1229 gp->phy_type != phy_mii_mdio1)
1230 goto non_mii;
1231
1232 /* Setup advertise */
1233 if (found_mii_phy(gp))
1234 features = gp->phy_mii.def->features;
1235 else
1236 features = 0;
1237
1238 advertise = features & ADVERTISE_MASK;
1239 if (gp->phy_mii.advertising != 0)
1240 advertise &= gp->phy_mii.advertising;
1241
1242 autoneg = gp->want_autoneg;
1243 speed = gp->phy_mii.speed;
1244 duplex = gp->phy_mii.duplex;
6aa20a22 1245
1da177e4
LT		 1246 /* Setup link parameters */
1247 if (!ep)
1248 goto start_aneg;
1249 if (ep->autoneg == AUTONEG_ENABLE) {
1250 advertise = ep->advertising;
1251 autoneg = 1;
1252 } else {
1253 autoneg = 0;
1254 speed = ep->speed;
1255 duplex = ep->duplex;
1256 }
1257
1258start_aneg:
1259 /* Sanitize settings based on PHY capabilities */
1260 if ((features & SUPPORTED_Autoneg) == 0)
1261 autoneg = 0;
1262 if (speed == SPEED_1000 &&
1263 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1264 speed = SPEED_100;
1265 if (speed == SPEED_100 &&
1266 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1267 speed = SPEED_10;
1268 if (duplex == DUPLEX_FULL &&
1269 !(features & (SUPPORTED_1000baseT_Full |
1270 SUPPORTED_100baseT_Full |
1271 SUPPORTED_10baseT_Full)))
1272 duplex = DUPLEX_HALF;
1273 if (speed == 0)
1274 speed = SPEED_10;
6aa20a22 1275
1da177e4
LT		 1276 /* If we are asleep, we don't try to actually setup the PHY, we
1277 * just store the settings
1278 */
1279 if (gp->asleep) {
1280 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1281 gp->phy_mii.speed = speed;
1282 gp->phy_mii.duplex = duplex;
1283 return;
1284 }
1285
1286 /* Configure PHY & start aneg */
1287 gp->want_autoneg = autoneg;
1288 if (autoneg) {
1289 if (found_mii_phy(gp))
1290 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1291 gp->lstate = link_aneg;
1292 } else {
1293 if (found_mii_phy(gp))
1294 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1295 gp->lstate = link_force_ok;
1296 }
1297
1298non_mii:
1299 gp->timer_ticks = 0;
1300 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1301}
1302
1303/* A link-up condition has occurred, initialize and enable the
1304 * rest of the chip.
1305 *
1306 * Must be invoked under gp->lock and gp->tx_lock.
1307 */
1308static int gem_set_link_modes(struct gem *gp)
1309{
1310 u32 val;
1311 int full_duplex, speed, pause;
1312
1313 full_duplex = 0;
1314 speed = SPEED_10;
1315 pause = 0;
1316
1317 if (found_mii_phy(gp)) {
1318 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1319 return 1;
1320 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1321 speed = gp->phy_mii.speed;
1322 pause = gp->phy_mii.pause;
1323 } else if (gp->phy_type == phy_serialink ||
1324 gp->phy_type == phy_serdes) {
1325 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1326
1327 if (pcs_lpa & PCS_MIIADV_FD)
1328 full_duplex = 1;
1329 speed = SPEED_1000;
1330 }
1331
1332 if (netif_msg_link(gp))
1333 printk(KERN_INFO "%s: Link is up at %d Mbps, %s-duplex.\n",
1334 gp->dev->name, speed, (full_duplex ? "full" : "half"));
1335
1336 if (!gp->running)
1337 return 0;
1338
1339 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1340 if (full_duplex) {
1341 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1342 } else {
1343 /* MAC_TXCFG_NBO must be zero. */
6aa20a22 1344 }
1da177e4
LT		 1345 writel(val, gp->regs + MAC_TXCFG);
1346
1347 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1348 if (!full_duplex &&
1349 (gp->phy_type == phy_mii_mdio0 ||
1350 gp->phy_type == phy_mii_mdio1)) {
1351 val |= MAC_XIFCFG_DISE;
1352 } else if (full_duplex) {
1353 val |= MAC_XIFCFG_FLED;
1354 }
1355
1356 if (speed == SPEED_1000)
1357 val |= (MAC_XIFCFG_GMII);
1358
1359 writel(val, gp->regs + MAC_XIFCFG);
1360
1361 /* If gigabit and half-duplex, enable carrier extension
1362 * mode. Else, disable it.
1363 */
1364 if (speed == SPEED_1000 && !full_duplex) {
1365 val = readl(gp->regs + MAC_TXCFG);
1366 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1367
1368 val = readl(gp->regs + MAC_RXCFG);
1369 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1370 } else {
1371 val = readl(gp->regs + MAC_TXCFG);
1372 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1373
1374 val = readl(gp->regs + MAC_RXCFG);
1375 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1376 }
1377
1378 if (gp->phy_type == phy_serialink ||
1379 gp->phy_type == phy_serdes) {
1380 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1381
1382 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1383 pause = 1;
1384 }
1385
1386 if (netif_msg_link(gp)) {
1387 if (pause) {
1388 printk(KERN_INFO "%s: Pause is enabled "
1389 "(rxfifo: %d off: %d on: %d)\n",
1390 gp->dev->name,
1391 gp->rx_fifo_sz,
1392 gp->rx_pause_off,
1393 gp->rx_pause_on);
1394 } else {
1395 printk(KERN_INFO "%s: Pause is disabled\n",
1396 gp->dev->name);
1397 }
1398 }
1399
1400 if (!full_duplex)
1401 writel(512, gp->regs + MAC_STIME);
1402 else
1403 writel(64, gp->regs + MAC_STIME);
1404 val = readl(gp->regs + MAC_MCCFG);
1405 if (pause)
1406 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1407 else
1408 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1409 writel(val, gp->regs + MAC_MCCFG);
1410
1411 gem_start_dma(gp);
1412
1413 return 0;
1414}
1415
1416/* Must be invoked under gp->lock and gp->tx_lock. */
1417static int gem_mdio_link_not_up(struct gem *gp)
1418{
1419 switch (gp->lstate) {
1420 case link_force_ret:
1421 if (netif_msg_link(gp))
1422 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1423 " forced mode\n", gp->dev->name);
1424 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1425 gp->last_forced_speed, DUPLEX_HALF);
1426 gp->timer_ticks = 5;
1427 gp->lstate = link_force_ok;
1428 return 0;
1429 case link_aneg:
1430 /* We try forced modes after a failed aneg only on PHYs that don't
1431 * have "magic_aneg" bit set, which means they internally do the
1432 * while forced-mode thingy. On these, we just restart aneg
1433 */
1434 if (gp->phy_mii.def->magic_aneg)
1435 return 1;
1436 if (netif_msg_link(gp))
1437 printk(KERN_INFO "%s: switching to forced 100bt\n",
1438 gp->dev->name);
1439 /* Try forced modes. */
1440 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1441 DUPLEX_HALF);
1442 gp->timer_ticks = 5;
1443 gp->lstate = link_force_try;
1444 return 0;
1445 case link_force_try:
1446 /* Downgrade from 100 to 10 Mbps if necessary.
1447 * If already at 10Mbps, warn user about the
1448 * situation every 10 ticks.
1449 */
1450 if (gp->phy_mii.speed == SPEED_100) {
1451 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1452 DUPLEX_HALF);
1453 gp->timer_ticks = 5;
1454 if (netif_msg_link(gp))
1455 printk(KERN_INFO "%s: switching to forced 10bt\n",
1456 gp->dev->name);
1457 return 0;
1458 } else
1459 return 1;
1460 default:
1461 return 0;
1462 }
1463}
1464
1465static void gem_link_timer(unsigned long data)
1466{
1467 struct gem *gp = (struct gem *) data;
1468 int restart_aneg = 0;
6aa20a22 1469
1da177e4
LT		 1470 if (gp->asleep)
1471 return;
1472
1473 spin_lock_irq(&gp->lock);
1474 spin_lock(&gp->tx_lock);
1475 gem_get_cell(gp);
1476
1477 /* If the reset task is still pending, we just
1478 * reschedule the link timer
1479 */
1480 if (gp->reset_task_pending)
1481 goto restart;
6aa20a22 1482
1da177e4
LT		 1483 if (gp->phy_type == phy_serialink ||
1484 gp->phy_type == phy_serdes) {
1485 u32 val = readl(gp->regs + PCS_MIISTAT);
1486
1487 if (!(val & PCS_MIISTAT_LS))
1488 val = readl(gp->regs + PCS_MIISTAT);
1489
1490 if ((val & PCS_MIISTAT_LS) != 0) {
1491 gp->lstate = link_up;
1492 netif_carrier_on(gp->dev);
1493 (void)gem_set_link_modes(gp);
1494 }
1495 goto restart;
1496 }
1497 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1498 /* Ok, here we got a link. If we had it due to a forced
1499 * fallback, and we were configured for autoneg, we do
1500 * retry a short autoneg pass. If you know your hub is
1501 * broken, use ethtool ;)
1502 */
1503 if (gp->lstate == link_force_try && gp->want_autoneg) {
1504 gp->lstate = link_force_ret;
1505 gp->last_forced_speed = gp->phy_mii.speed;
1506 gp->timer_ticks = 5;
1507 if (netif_msg_link(gp))
1508 printk(KERN_INFO "%s: Got link after fallback, retrying"
1509 " autoneg once...\n", gp->dev->name);
1510 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1511 } else if (gp->lstate != link_up) {
1512 gp->lstate = link_up;
1513 netif_carrier_on(gp->dev);
1514 if (gem_set_link_modes(gp))
1515 restart_aneg = 1;
1516 }
1517 } else {
1518 /* If the link was previously up, we restart the
1519 * whole process
1520 */
1521 if (gp->lstate == link_up) {
1522 gp->lstate = link_down;
1523 if (netif_msg_link(gp))
1524 printk(KERN_INFO "%s: Link down\n",
1525 gp->dev->name);
1526 netif_carrier_off(gp->dev);
1527 gp->reset_task_pending = 1;
1528 schedule_work(&gp->reset_task);
1529 restart_aneg = 1;
1530 } else if (++gp->timer_ticks > 10) {
1531 if (found_mii_phy(gp))
1532 restart_aneg = gem_mdio_link_not_up(gp);
1533 else
1534 restart_aneg = 1;
1535 }
1536 }
1537 if (restart_aneg) {
1538 gem_begin_auto_negotiation(gp, NULL);
1539 goto out_unlock;
1540 }
1541restart:
1542 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1543out_unlock:
1544 gem_put_cell(gp);
1545 spin_unlock(&gp->tx_lock);
1546 spin_unlock_irq(&gp->lock);
1547}
1548
1549/* Must be invoked under gp->lock and gp->tx_lock. */
1550static void gem_clean_rings(struct gem *gp)
1551{
1552 struct gem_init_block *gb = gp->init_block;
1553 struct sk_buff *skb;
1554 int i;
1555 dma_addr_t dma_addr;
1556
1557 for (i = 0; i < RX_RING_SIZE; i++) {
1558 struct gem_rxd *rxd;
1559
1560 rxd = &gb->rxd[i];
1561 if (gp->rx_skbs[i] != NULL) {
1562 skb = gp->rx_skbs[i];
1563 dma_addr = le64_to_cpu(rxd->buffer);
1564 pci_unmap_page(gp->pdev, dma_addr,
1565 RX_BUF_ALLOC_SIZE(gp),
1566 PCI_DMA_FROMDEVICE);
1567 dev_kfree_skb_any(skb);
1568 gp->rx_skbs[i] = NULL;
1569 }
1570 rxd->status_word = 0;
1571 wmb();
1572 rxd->buffer = 0;
1573 }
1574
1575 for (i = 0; i < TX_RING_SIZE; i++) {
1576 if (gp->tx_skbs[i] != NULL) {
1577 struct gem_txd *txd;
1578 int frag;
1579
1580 skb = gp->tx_skbs[i];
1581 gp->tx_skbs[i] = NULL;
1582
1583 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1584 int ent = i & (TX_RING_SIZE - 1);
1585
1586 txd = &gb->txd[ent];
1587 dma_addr = le64_to_cpu(txd->buffer);
1588 pci_unmap_page(gp->pdev, dma_addr,
1589 le64_to_cpu(txd->control_word) &
1590 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1591
1592 if (frag != skb_shinfo(skb)->nr_frags)
1593 i++;
1594 }
1595 dev_kfree_skb_any(skb);
1596 }
1597 }
1598}
1599
1600/* Must be invoked under gp->lock and gp->tx_lock. */
1601static void gem_init_rings(struct gem *gp)
1602{
1603 struct gem_init_block *gb = gp->init_block;
1604 struct net_device *dev = gp->dev;
1605 int i;
1606 dma_addr_t dma_addr;
1607
1608 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1609
1610 gem_clean_rings(gp);
1611
1612 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1613 (unsigned)VLAN_ETH_FRAME_LEN);
1614
1615 for (i = 0; i < RX_RING_SIZE; i++) {
1616 struct sk_buff *skb;
1617 struct gem_rxd *rxd = &gb->rxd[i];
1618
1619 skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
1620 if (!skb) {
1621 rxd->buffer = 0;
1622 rxd->status_word = 0;
1623 continue;
1624 }
1625
1626 gp->rx_skbs[i] = skb;
1627 skb->dev = dev;
1628 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1629 dma_addr = pci_map_page(gp->pdev,
1630 virt_to_page(skb->data),
1631 offset_in_page(skb->data),
1632 RX_BUF_ALLOC_SIZE(gp),
1633 PCI_DMA_FROMDEVICE);
1634 rxd->buffer = cpu_to_le64(dma_addr);
1635 wmb();
1636 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1637 skb_reserve(skb, RX_OFFSET);
1638 }
1639
1640 for (i = 0; i < TX_RING_SIZE; i++) {
1641 struct gem_txd *txd = &gb->txd[i];
1642
1643 txd->control_word = 0;
1644 wmb();
1645 txd->buffer = 0;
1646 }
1647 wmb();
1648}
1649
1650/* Init PHY interface and start link poll state machine */
1651static void gem_init_phy(struct gem *gp)
1652{
7fb76aa0 1653 u32 mifcfg;
1da177e4
LT		 1654
1655 /* Revert MIF CFG setting done on stop_phy */
7fb76aa0
DM		 1656 mifcfg = readl(gp->regs + MIF_CFG);
1657 mifcfg &= ~MIF_CFG_BBMODE;
1658 writel(mifcfg, gp->regs + MIF_CFG);
6aa20a22 1659
1da177e4
LT		 1660 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1661 int i;
1662
7fb76aa0
DM		 1663 /* Those delay sucks, the HW seem to love them though, I'll
1664 * serisouly consider breaking some locks here to be able
1665 * to schedule instead
1666 */
1667 for (i = 0; i < 3; i++) {
1da177e4 1668#ifdef CONFIG_PPC_PMAC
7fb76aa0
DM		 1669 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1670 msleep(20);
1da177e4 1671#endif
7fb76aa0
DM		 1672 /* Some PHYs used by apple have problem getting back to us,
1673 * we do an additional reset here
1674 */
1675 phy_write(gp, MII_BMCR, BMCR_RESET);
1676 msleep(20);
1677 if (phy_read(gp, MII_BMCR) != 0xffff)
1da177e4 1678 break;
7fb76aa0
DM		 1679 if (i == 2)
1680 printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
1681 gp->dev->name);
1da177e4
LT		 1682 }
1683 }
1684
1685 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1686 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1687 u32 val;
1688
1689 /* Init datapath mode register. */
1690 if (gp->phy_type == phy_mii_mdio0 ||
1691 gp->phy_type == phy_mii_mdio1) {
1692 val = PCS_DMODE_MGM;
1693 } else if (gp->phy_type == phy_serialink) {
1694 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1695 } else {
1696 val = PCS_DMODE_ESM;
1697 }
1698
1699 writel(val, gp->regs + PCS_DMODE);
1700 }
1701
1702 if (gp->phy_type == phy_mii_mdio0 ||
1703 gp->phy_type == phy_mii_mdio1) {
1704 // XXX check for errors
1705 mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1706
1707 /* Init PHY */
1708 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1709 gp->phy_mii.def->ops->init(&gp->phy_mii);
1710 } else {
1711 u32 val;
1712 int limit;
1713
1714 /* Reset PCS unit. */
1715 val = readl(gp->regs + PCS_MIICTRL);
1716 val |= PCS_MIICTRL_RST;
1717 writeb(val, gp->regs + PCS_MIICTRL);
1718
1719 limit = 32;
1720 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1721 udelay(100);
1722 if (limit-- <= 0)
1723 break;
1724 }
1725 if (limit <= 0)
1726 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1727 gp->dev->name);
1728
1729 /* Make sure PCS is disabled while changing advertisement
1730 * configuration.
1731 */
1732 val = readl(gp->regs + PCS_CFG);
1733 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1734 writel(val, gp->regs + PCS_CFG);
1735
1736 /* Advertise all capabilities except assymetric
1737 * pause.
1738 */
1739 val = readl(gp->regs + PCS_MIIADV);
1740 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1741 PCS_MIIADV_SP | PCS_MIIADV_AP);
1742 writel(val, gp->regs + PCS_MIIADV);
1743
1744 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1745 * and re-enable PCS.
1746 */
1747 val = readl(gp->regs + PCS_MIICTRL);
1748 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1749 val &= ~PCS_MIICTRL_WB;
1750 writel(val, gp->regs + PCS_MIICTRL);
1751
1752 val = readl(gp->regs + PCS_CFG);
1753 val |= PCS_CFG_ENABLE;
1754 writel(val, gp->regs + PCS_CFG);
1755
1756 /* Make sure serialink loopback is off. The meaning
1757 * of this bit is logically inverted based upon whether
1758 * you are in Serialink or SERDES mode.
1759 */
1760 val = readl(gp->regs + PCS_SCTRL);
1761 if (gp->phy_type == phy_serialink)
1762 val &= ~PCS_SCTRL_LOOP;
1763 else
1764 val |= PCS_SCTRL_LOOP;
1765 writel(val, gp->regs + PCS_SCTRL);
1766 }
1767
1768 /* Default aneg parameters */
1769 gp->timer_ticks = 0;
1770 gp->lstate = link_down;
1771 netif_carrier_off(gp->dev);
1772
1773 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
1774 spin_lock_irq(&gp->lock);
1775 gem_begin_auto_negotiation(gp, NULL);
1776 spin_unlock_irq(&gp->lock);
1777}
1778
1779/* Must be invoked under gp->lock and gp->tx_lock. */
1780static void gem_init_dma(struct gem *gp)
1781{
1782 u64 desc_dma = (u64) gp->gblock_dvma;
1783 u32 val;
1784
1785 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1786 writel(val, gp->regs + TXDMA_CFG);
1787
1788 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1789 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1790 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1791
1792 writel(0, gp->regs + TXDMA_KICK);
1793
1794 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1795 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1796 writel(val, gp->regs + RXDMA_CFG);
1797
1798 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1799 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1800
1801 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1802
1803 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1804 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1805 writel(val, gp->regs + RXDMA_PTHRESH);
1806
1807 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1808 writel(((5 & RXDMA_BLANK_IPKTS) |
1809 ((8 << 12) & RXDMA_BLANK_ITIME)),
1810 gp->regs + RXDMA_BLANK);
1811 else
1812 writel(((5 & RXDMA_BLANK_IPKTS) |
1813 ((4 << 12) & RXDMA_BLANK_ITIME)),
1814 gp->regs + RXDMA_BLANK);
1815}
1816
1817/* Must be invoked under gp->lock and gp->tx_lock. */
1818static u32 gem_setup_multicast(struct gem *gp)
1819{
1820 u32 rxcfg = 0;
1821 int i;
6aa20a22 1822
1da177e4
LT		 1823 if ((gp->dev->flags & IFF_ALLMULTI) ||
1824 (gp->dev->mc_count > 256)) {
1825 for (i=0; i<16; i++)
1826 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1827 rxcfg |= MAC_RXCFG_HFE;
1828 } else if (gp->dev->flags & IFF_PROMISC) {
1829 rxcfg |= MAC_RXCFG_PROM;
1830 } else {
1831 u16 hash_table[16];
1832 u32 crc;
1833 struct dev_mc_list *dmi = gp->dev->mc_list;
1834 int i;
1835
1836 for (i = 0; i < 16; i++)
1837 hash_table[i] = 0;
1838
1839 for (i = 0; i < gp->dev->mc_count; i++) {
1840 char *addrs = dmi->dmi_addr;
1841
1842 dmi = dmi->next;
1843
1844 if (!(*addrs & 1))
1845 continue;
1846
1847 crc = ether_crc_le(6, addrs);
1848 crc >>= 24;
1849 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1850 }
1851 for (i=0; i<16; i++)
1852 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1853 rxcfg |= MAC_RXCFG_HFE;
1854 }
1855
1856 return rxcfg;
1857}
1858
1859/* Must be invoked under gp->lock and gp->tx_lock. */
1860static void gem_init_mac(struct gem *gp)
1861{
1862 unsigned char *e = &gp->dev->dev_addr[0];
1863
1864 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1865
1866 writel(0x00, gp->regs + MAC_IPG0);
1867 writel(0x08, gp->regs + MAC_IPG1);
1868 writel(0x04, gp->regs + MAC_IPG2);
1869 writel(0x40, gp->regs + MAC_STIME);
1870 writel(0x40, gp->regs + MAC_MINFSZ);
1871
1872 /* Ethernet payload + header + FCS + optional VLAN tag. */
1873 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1874
1875 writel(0x07, gp->regs + MAC_PASIZE);
1876 writel(0x04, gp->regs + MAC_JAMSIZE);
1877 writel(0x10, gp->regs + MAC_ATTLIM);
1878 writel(0x8808, gp->regs + MAC_MCTYPE);
1879
1880 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1881
1882 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1883 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1884 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1885
1886 writel(0, gp->regs + MAC_ADDR3);
1887 writel(0, gp->regs + MAC_ADDR4);
1888 writel(0, gp->regs + MAC_ADDR5);
1889
1890 writel(0x0001, gp->regs + MAC_ADDR6);
1891 writel(0xc200, gp->regs + MAC_ADDR7);
1892 writel(0x0180, gp->regs + MAC_ADDR8);
1893
1894 writel(0, gp->regs + MAC_AFILT0);
1895 writel(0, gp->regs + MAC_AFILT1);
1896 writel(0, gp->regs + MAC_AFILT2);
1897 writel(0, gp->regs + MAC_AF21MSK);
1898 writel(0, gp->regs + MAC_AF0MSK);
1899
1900 gp->mac_rx_cfg = gem_setup_multicast(gp);
1901#ifdef STRIP_FCS
1902 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1903#endif
1904 writel(0, gp->regs + MAC_NCOLL);
1905 writel(0, gp->regs + MAC_FASUCC);
1906 writel(0, gp->regs + MAC_ECOLL);
1907 writel(0, gp->regs + MAC_LCOLL);
1908 writel(0, gp->regs + MAC_DTIMER);
1909 writel(0, gp->regs + MAC_PATMPS);
1910 writel(0, gp->regs + MAC_RFCTR);
1911 writel(0, gp->regs + MAC_LERR);
1912 writel(0, gp->regs + MAC_AERR);
1913 writel(0, gp->regs + MAC_FCSERR);
1914 writel(0, gp->regs + MAC_RXCVERR);
1915
1916 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1917 * them once a link is established.
1918 */
1919 writel(0, gp->regs + MAC_TXCFG);
1920 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1921 writel(0, gp->regs + MAC_MCCFG);
1922 writel(0, gp->regs + MAC_XIFCFG);
1923
1924 /* Setup MAC interrupts. We want to get all of the interesting
1925 * counter expiration events, but we do not want to hear about
1926 * normal rx/tx as the DMA engine tells us that.
1927 */
1928 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1929 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1930
1931 /* Don't enable even the PAUSE interrupts for now, we
1932 * make no use of those events other than to record them.
1933 */
1934 writel(0xffffffff, gp->regs + MAC_MCMASK);
1935
1936 /* Don't enable GEM's WOL in normal operations
1937 */
1938 if (gp->has_wol)
1939 writel(0, gp->regs + WOL_WAKECSR);
1940}
1941
1942/* Must be invoked under gp->lock and gp->tx_lock. */
1943static void gem_init_pause_thresholds(struct gem *gp)
1944{
1945 u32 cfg;
1946
1947 /* Calculate pause thresholds. Setting the OFF threshold to the
1948 * full RX fifo size effectively disables PAUSE generation which
1949 * is what we do for 10/100 only GEMs which have FIFOs too small
1950 * to make real gains from PAUSE.
1951 */
1952 if (gp->rx_fifo_sz <= (2 * 1024)) {
1953 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1954 } else {
1955 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1956 int off = (gp->rx_fifo_sz - (max_frame * 2));
1957 int on = off - max_frame;
1958
1959 gp->rx_pause_off = off;
1960 gp->rx_pause_on = on;
1961 }
1962
1963
1964 /* Configure the chip "burst" DMA mode & enable some
1965 * HW bug fixes on Apple version
1966 */
1967 cfg = 0;
1968 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1969 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1970#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1971 cfg |= GREG_CFG_IBURST;
1972#endif
1973 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1974 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1975 writel(cfg, gp->regs + GREG_CFG);
1976
1977 /* If Infinite Burst didn't stick, then use different
1978 * thresholds (and Apple bug fixes don't exist)
1979 */
1980 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1981 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1982 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1983 writel(cfg, gp->regs + GREG_CFG);
6aa20a22 1984 }
1da177e4
LT		 1985}
1986
1987static int gem_check_invariants(struct gem *gp)
1988{
1989 struct pci_dev *pdev = gp->pdev;
1990 u32 mif_cfg;
1991
1992 /* On Apple's sungem, we can't rely on registers as the chip
1993 * was been powered down by the firmware. The PHY is looked
1994 * up later on.
1995 */
1996 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1997 gp->phy_type = phy_mii_mdio0;
1998 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1999 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2000 gp->swrst_base = 0;
2001
2002 mif_cfg = readl(gp->regs + MIF_CFG);
2003 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
2004 mif_cfg |= MIF_CFG_MDI0;
2005 writel(mif_cfg, gp->regs + MIF_CFG);
2006 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
2007 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
2008
2009 /* We hard-code the PHY address so we can properly bring it out of
2010 * reset later on, we can't really probe it at this point, though
2011 * that isn't an issue.
2012 */
2013 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
2014 gp->mii_phy_addr = 1;
2015 else
2016 gp->mii_phy_addr = 0;
2017
2018 return 0;
2019 }
2020
2021 mif_cfg = readl(gp->regs + MIF_CFG);
2022
2023 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2024 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
2025 /* One of the MII PHYs _must_ be present
2026 * as this chip has no gigabit PHY.
2027 */
2028 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
2029 printk(KERN_ERR PFX "RIO GEM lacks MII phy, mif_cfg[%08x]\n",
2030 mif_cfg);
2031 return -1;
2032 }
2033 }
2034
2035 /* Determine initial PHY interface type guess. MDIO1 is the
2036 * external PHY and thus takes precedence over MDIO0.
2037 */
6aa20a22 2038
1da177e4
LT		 2039 if (mif_cfg & MIF_CFG_MDI1) {
2040 gp->phy_type = phy_mii_mdio1;
2041 mif_cfg |= MIF_CFG_PSELECT;
2042 writel(mif_cfg, gp->regs + MIF_CFG);
2043 } else if (mif_cfg & MIF_CFG_MDI0) {
2044 gp->phy_type = phy_mii_mdio0;
2045 mif_cfg &= ~MIF_CFG_PSELECT;
2046 writel(mif_cfg, gp->regs + MIF_CFG);
2047 } else {
2048 gp->phy_type = phy_serialink;
2049 }
2050 if (gp->phy_type == phy_mii_mdio1 ||
2051 gp->phy_type == phy_mii_mdio0) {
2052 int i;
2053
2054 for (i = 0; i < 32; i++) {
2055 gp->mii_phy_addr = i;
2056 if (phy_read(gp, MII_BMCR) != 0xffff)
2057 break;
2058 }
2059 if (i == 32) {
2060 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2061 printk(KERN_ERR PFX "RIO MII phy will not respond.\n");
2062 return -1;
2063 }
2064 gp->phy_type = phy_serdes;
2065 }
2066 }
2067
2068 /* Fetch the FIFO configurations now too. */
2069 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2070 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2071
2072 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2073 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2074 if (gp->tx_fifo_sz != (9 * 1024) ||
2075 gp->rx_fifo_sz != (20 * 1024)) {
2076 printk(KERN_ERR PFX "GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2077 gp->tx_fifo_sz, gp->rx_fifo_sz);
2078 return -1;
2079 }
2080 gp->swrst_base = 0;
2081 } else {
2082 if (gp->tx_fifo_sz != (2 * 1024) ||
2083 gp->rx_fifo_sz != (2 * 1024)) {
2084 printk(KERN_ERR PFX "RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2085 gp->tx_fifo_sz, gp->rx_fifo_sz);
2086 return -1;
2087 }
2088 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2089 }
2090 }
2091
2092 return 0;
2093}
2094
2095/* Must be invoked under gp->lock and gp->tx_lock. */
2096static void gem_reinit_chip(struct gem *gp)
2097{
2098 /* Reset the chip */
2099 gem_reset(gp);
2100
2101 /* Make sure ints are disabled */
2102 gem_disable_ints(gp);
2103
2104 /* Allocate & setup ring buffers */
2105 gem_init_rings(gp);
2106
2107 /* Configure pause thresholds */
2108 gem_init_pause_thresholds(gp);
2109
2110 /* Init DMA & MAC engines */
2111 gem_init_dma(gp);
2112 gem_init_mac(gp);
2113}
2114
2115
2116/* Must be invoked with no lock held. */
2117static void gem_stop_phy(struct gem *gp, int wol)
2118{
7fb76aa0 2119 u32 mifcfg;
1da177e4
LT		 2120 unsigned long flags;
2121
2122 /* Let the chip settle down a bit, it seems that helps
2123 * for sleep mode on some models
2124 */
2125 msleep(10);
2126
2127 /* Make sure we aren't polling PHY status change. We
2128 * don't currently use that feature though
2129 */
7fb76aa0
DM		 2130 mifcfg = readl(gp->regs + MIF_CFG);
2131 mifcfg &= ~MIF_CFG_POLL;
2132 writel(mifcfg, gp->regs + MIF_CFG);
1da177e4
LT		 2133
2134 if (wol && gp->has_wol) {
2135 unsigned char *e = &gp->dev->dev_addr[0];
2136 u32 csr;
2137
2138 /* Setup wake-on-lan for MAGIC packet */
2139 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
6aa20a22 2140 gp->regs + MAC_RXCFG);
1da177e4
LT		 2141 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2142 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2143 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2144
2145 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2146 csr = WOL_WAKECSR_ENABLE;
2147 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2148 csr |= WOL_WAKECSR_MII;
2149 writel(csr, gp->regs + WOL_WAKECSR);
2150 } else {
2151 writel(0, gp->regs + MAC_RXCFG);
2152 (void)readl(gp->regs + MAC_RXCFG);
2153 /* Machine sleep will die in strange ways if we
2154 * dont wait a bit here, looks like the chip takes
2155 * some time to really shut down
2156 */
2157 msleep(10);
2158 }
2159
2160 writel(0, gp->regs + MAC_TXCFG);
2161 writel(0, gp->regs + MAC_XIFCFG);
2162 writel(0, gp->regs + TXDMA_CFG);
2163 writel(0, gp->regs + RXDMA_CFG);
2164
2165 if (!wol) {
2166 spin_lock_irqsave(&gp->lock, flags);
2167 spin_lock(&gp->tx_lock);
2168 gem_reset(gp);
2169 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2170 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2171 spin_unlock(&gp->tx_lock);
2172 spin_unlock_irqrestore(&gp->lock, flags);
2173
2174 /* No need to take the lock here */
2175
2176 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2177 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2178
2179 /* According to Apple, we must set the MDIO pins to this begnign
2180 * state or we may 1) eat more current, 2) damage some PHYs
2181 */
7fb76aa0 2182 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
1da177e4
LT		 2183 writel(0, gp->regs + MIF_BBCLK);
2184 writel(0, gp->regs + MIF_BBDATA);
2185 writel(0, gp->regs + MIF_BBOENAB);
2186 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2187 (void) readl(gp->regs + MAC_XIFCFG);
2188 }
2189}
2190
2191
2192static int gem_do_start(struct net_device *dev)
2193{
2194 struct gem *gp = dev->priv;
2195 unsigned long flags;
2196
2197 spin_lock_irqsave(&gp->lock, flags);
2198 spin_lock(&gp->tx_lock);
2199
2200 /* Enable the cell */
2201 gem_get_cell(gp);
2202
2203 /* Init & setup chip hardware */
2204 gem_reinit_chip(gp);
2205
2206 gp->running = 1;
2207
2208 if (gp->lstate == link_up) {
2209 netif_carrier_on(gp->dev);
2210 gem_set_link_modes(gp);
2211 }
2212
2213 netif_wake_queue(gp->dev);
2214
2215 spin_unlock(&gp->tx_lock);
2216 spin_unlock_irqrestore(&gp->lock, flags);
2217
2218 if (request_irq(gp->pdev->irq, gem_interrupt,
1fb9df5d 2219 IRQF_SHARED, dev->name, (void *)dev)) {
1da177e4
LT		 2220 printk(KERN_ERR "%s: failed to request irq !\n", gp->dev->name);
2221
2222 spin_lock_irqsave(&gp->lock, flags);
2223 spin_lock(&gp->tx_lock);
2224
2225 gp->running = 0;
2226 gem_reset(gp);
2227 gem_clean_rings(gp);
2228 gem_put_cell(gp);
6aa20a22 2229
1da177e4
LT		 2230 spin_unlock(&gp->tx_lock);
2231 spin_unlock_irqrestore(&gp->lock, flags);
2232
2233 return -EAGAIN;
2234 }
2235
2236 return 0;
2237}
2238
2239static void gem_do_stop(struct net_device *dev, int wol)
2240{
2241 struct gem *gp = dev->priv;
2242 unsigned long flags;
2243
2244 spin_lock_irqsave(&gp->lock, flags);
2245 spin_lock(&gp->tx_lock);
2246
2247 gp->running = 0;
2248
2249 /* Stop netif queue */
2250 netif_stop_queue(dev);
2251
2252 /* Make sure ints are disabled */
2253 gem_disable_ints(gp);
2254
2255 /* We can drop the lock now */
2256 spin_unlock(&gp->tx_lock);
2257 spin_unlock_irqrestore(&gp->lock, flags);
2258
2259 /* If we are going to sleep with WOL */
2260 gem_stop_dma(gp);
2261 msleep(10);
2262 if (!wol)
2263 gem_reset(gp);
2264 msleep(10);
2265
2266 /* Get rid of rings */
2267 gem_clean_rings(gp);
2268
2269 /* No irq needed anymore */
2270 free_irq(gp->pdev->irq, (void *) dev);
2271
2272 /* Cell not needed neither if no WOL */
2273 if (!wol) {
2274 spin_lock_irqsave(&gp->lock, flags);
2275 gem_put_cell(gp);
2276 spin_unlock_irqrestore(&gp->lock, flags);
2277 }
2278}
2279
c4028958 2280static void gem_reset_task(struct work_struct *work)
1da177e4 2281{
c4028958 2282 struct gem *gp = container_of(work, struct gem, reset_task);
1da177e4 2283
e3968fc0 2284 mutex_lock(&gp->pm_mutex);
1da177e4 2285
dde655c9
JB		 2286 if (gp->opened)
2287 napi_disable(&gp->napi);
1da177e4
LT		 2288
2289 spin_lock_irq(&gp->lock);
2290 spin_lock(&gp->tx_lock);
2291
1da177e4
LT		 2292 if (gp->running) {
2293 netif_stop_queue(gp->dev);
2294
2295 /* Reset the chip & rings */
2296 gem_reinit_chip(gp);
2297 if (gp->lstate == link_up)
2298 gem_set_link_modes(gp);
2299 netif_wake_queue(gp->dev);
2300 }
dde655c9 2301
1da177e4
LT		 2302 gp->reset_task_pending = 0;
2303
2304 spin_unlock(&gp->tx_lock);
2305 spin_unlock_irq(&gp->lock);
2306
dde655c9
JB		 2307 if (gp->opened)
2308 napi_enable(&gp->napi);
1da177e4 2309
e3968fc0 2310 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2311}
2312
2313
2314static int gem_open(struct net_device *dev)
2315{
2316 struct gem *gp = dev->priv;
2317 int rc = 0;
2318
e3968fc0 2319 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2320
2321 /* We need the cell enabled */
2322 if (!gp->asleep)
2323 rc = gem_do_start(dev);
2324 gp->opened = (rc == 0);
bea3348e
SH		 2325 if (gp->opened)
2326 napi_enable(&gp->napi);
1da177e4 2327
e3968fc0 2328 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2329
2330 return rc;
2331}
2332
2333static int gem_close(struct net_device *dev)
2334{
2335 struct gem *gp = dev->priv;
2336
e3968fc0 2337 mutex_lock(&gp->pm_mutex);
1da177e4 2338
62768e28
JB		 2339 napi_disable(&gp->napi);
2340
6aa20a22 2341 gp->opened = 0;
1da177e4
LT		 2342 if (!gp->asleep)
2343 gem_do_stop(dev, 0);
2344
e3968fc0 2345 mutex_unlock(&gp->pm_mutex);
6aa20a22 2346
1da177e4
LT		 2347 return 0;
2348}
2349
2350#ifdef CONFIG_PM
2351static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2352{
2353 struct net_device *dev = pci_get_drvdata(pdev);
2354 struct gem *gp = dev->priv;
2355 unsigned long flags;
2356
e3968fc0 2357 mutex_lock(&gp->pm_mutex);
1da177e4 2358
1da177e4
LT		 2359 printk(KERN_INFO "%s: suspending, WakeOnLan %s\n",
2360 dev->name,
2361 (gp->wake_on_lan && gp->opened) ? "enabled" : "disabled");
6aa20a22 2362
1da177e4
LT		 2363 /* Keep the cell enabled during the entire operation */
2364 spin_lock_irqsave(&gp->lock, flags);
2365 spin_lock(&gp->tx_lock);
2366 gem_get_cell(gp);
2367 spin_unlock(&gp->tx_lock);
2368 spin_unlock_irqrestore(&gp->lock, flags);
2369
2370 /* If the driver is opened, we stop the MAC */
2371 if (gp->opened) {
62768e28
JB		 2372 napi_disable(&gp->napi);
2373
1da177e4
LT		 2374 /* Stop traffic, mark us closed */
2375 netif_device_detach(dev);
2376
2377 /* Switch off MAC, remember WOL setting */
2378 gp->asleep_wol = gp->wake_on_lan;
2379 gem_do_stop(dev, gp->asleep_wol);
2380 } else
2381 gp->asleep_wol = 0;
2382
2383 /* Mark us asleep */
2384 gp->asleep = 1;
2385 wmb();
2386
2387 /* Stop the link timer */
2388 del_timer_sync(&gp->link_timer);
2389
e3968fc0 2390 /* Now we release the mutex to not block the reset task who
1da177e4
LT		 2391 * can take it too. We are marked asleep, so there will be no
2392 * conflict here
2393 */
e3968fc0 2394 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2395
2396 /* Wait for a pending reset task to complete */
2397 while (gp->reset_task_pending)
2398 yield();
2399 flush_scheduled_work();
2400
2401 /* Shut the PHY down eventually and setup WOL */
2402 gem_stop_phy(gp, gp->asleep_wol);
2403
2404 /* Make sure bus master is disabled */
2405 pci_disable_device(gp->pdev);
2406
2407 /* Release the cell, no need to take a lock at this point since
2408 * nothing else can happen now
2409 */
2410 gem_put_cell(gp);
2411
2412 return 0;
2413}
2414
2415static int gem_resume(struct pci_dev *pdev)
2416{
2417 struct net_device *dev = pci_get_drvdata(pdev);
2418 struct gem *gp = dev->priv;
2419 unsigned long flags;
2420
2421 printk(KERN_INFO "%s: resuming\n", dev->name);
2422
e3968fc0 2423 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2424
2425 /* Keep the cell enabled during the entire operation, no need to
2426 * take a lock here tho since nothing else can happen while we are
2427 * marked asleep
2428 */
2429 gem_get_cell(gp);
2430
2431 /* Make sure PCI access and bus master are enabled */
2432 if (pci_enable_device(gp->pdev)) {
2433 printk(KERN_ERR "%s: Can't re-enable chip !\n",
2434 dev->name);
2435 /* Put cell and forget it for now, it will be considered as
2436 * still asleep, a new sleep cycle may bring it back
2437 */
2438 gem_put_cell(gp);
e3968fc0 2439 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2440 return 0;
2441 }
2442 pci_set_master(gp->pdev);
2443
2444 /* Reset everything */
2445 gem_reset(gp);
2446
2447 /* Mark us woken up */
2448 gp->asleep = 0;
2449 wmb();
2450
2451 /* Bring the PHY back. Again, lock is useless at this point as
2452 * nothing can be happening until we restart the whole thing
2453 */
2454 gem_init_phy(gp);
2455
2456 /* If we were opened, bring everything back */
2457 if (gp->opened) {
2458 /* Restart MAC */
2459 gem_do_start(dev);
2460
2461 /* Re-attach net device */
2462 netif_device_attach(dev);
2463
62768e28 2464 napi_enable(&gp->napi);
1da177e4
LT		 2465 }
2466
2467 spin_lock_irqsave(&gp->lock, flags);
2468 spin_lock(&gp->tx_lock);
2469
2470 /* If we had WOL enabled, the cell clock was never turned off during
2471 * sleep, so we end up beeing unbalanced. Fix that here
2472 */
2473 if (gp->asleep_wol)
2474 gem_put_cell(gp);
2475
2476 /* This function doesn't need to hold the cell, it will be held if the
2477 * driver is open by gem_do_start().
2478 */
2479 gem_put_cell(gp);
2480
2481 spin_unlock(&gp->tx_lock);
2482 spin_unlock_irqrestore(&gp->lock, flags);
2483
e3968fc0 2484 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2485
2486 return 0;
2487}
2488#endif /* CONFIG_PM */
2489
2490static struct net_device_stats *gem_get_stats(struct net_device *dev)
2491{
2492 struct gem *gp = dev->priv;
2493 struct net_device_stats *stats = &gp->net_stats;
2494
2495 spin_lock_irq(&gp->lock);
2496 spin_lock(&gp->tx_lock);
2497
2498 /* I have seen this being called while the PM was in progress,
2499 * so we shield against this
2500 */
2501 if (gp->running) {
2502 stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2503 writel(0, gp->regs + MAC_FCSERR);
2504
2505 stats->rx_frame_errors += readl(gp->regs + MAC_AERR);
2506 writel(0, gp->regs + MAC_AERR);
2507
2508 stats->rx_length_errors += readl(gp->regs + MAC_LERR);
2509 writel(0, gp->regs + MAC_LERR);
2510
2511 stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2512 stats->collisions +=
2513 (readl(gp->regs + MAC_ECOLL) +
2514 readl(gp->regs + MAC_LCOLL));
2515 writel(0, gp->regs + MAC_ECOLL);
2516 writel(0, gp->regs + MAC_LCOLL);
2517 }
2518
2519 spin_unlock(&gp->tx_lock);
2520 spin_unlock_irq(&gp->lock);
2521
2522 return &gp->net_stats;
2523}
2524
09c72ec8
RV		 2525static int gem_set_mac_address(struct net_device *dev, void *addr)
2526{
2527 struct sockaddr *macaddr = (struct sockaddr *) addr;
2528 struct gem *gp = dev->priv;
2529 unsigned char *e = &dev->dev_addr[0];
2530
2531 if (!is_valid_ether_addr(macaddr->sa_data))
2532 return -EADDRNOTAVAIL;
2533
2534 if (!netif_running(dev) || !netif_device_present(dev)) {
2535 /* We'll just catch it later when the
2536 * device is up'd or resumed.
2537 */
2538 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2539 return 0;
2540 }
2541
2542 mutex_lock(&gp->pm_mutex);
2543 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2544 if (gp->running) {
2545 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2546 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2547 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2548 }
2549 mutex_unlock(&gp->pm_mutex);
2550
2551 return 0;
2552}
2553
1da177e4
LT		 2554static void gem_set_multicast(struct net_device *dev)
2555{
2556 struct gem *gp = dev->priv;
2557 u32 rxcfg, rxcfg_new;
2558 int limit = 10000;
6aa20a22 2559
1da177e4
LT		 2560
2561 spin_lock_irq(&gp->lock);
2562 spin_lock(&gp->tx_lock);
2563
2564 if (!gp->running)
2565 goto bail;
2566
2567 netif_stop_queue(dev);
2568
2569 rxcfg = readl(gp->regs + MAC_RXCFG);
2570 rxcfg_new = gem_setup_multicast(gp);
2571#ifdef STRIP_FCS
2572 rxcfg_new |= MAC_RXCFG_SFCS;
2573#endif
2574 gp->mac_rx_cfg = rxcfg_new;
6aa20a22 2575
1da177e4
LT		 2576 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2577 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2578 if (!limit--)
2579 break;
2580 udelay(10);
2581 }
2582
2583 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2584 rxcfg |= rxcfg_new;
2585
2586 writel(rxcfg, gp->regs + MAC_RXCFG);
2587
2588 netif_wake_queue(dev);
2589
2590 bail:
2591 spin_unlock(&gp->tx_lock);
2592 spin_unlock_irq(&gp->lock);
2593}
2594
2595/* Jumbo-grams don't seem to work :-( */
2596#define GEM_MIN_MTU 68
2597#if 1
2598#define GEM_MAX_MTU 1500
2599#else
2600#define GEM_MAX_MTU 9000
2601#endif
2602
2603static int gem_change_mtu(struct net_device *dev, int new_mtu)
2604{
2605 struct gem *gp = dev->priv;
2606
2607 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
2608 return -EINVAL;
2609
2610 if (!netif_running(dev) || !netif_device_present(dev)) {
2611 /* We'll just catch it later when the
2612 * device is up'd or resumed.
2613 */
2614 dev->mtu = new_mtu;
2615 return 0;
2616 }
2617
e3968fc0 2618 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2619 spin_lock_irq(&gp->lock);
2620 spin_lock(&gp->tx_lock);
2621 dev->mtu = new_mtu;
2622 if (gp->running) {
2623 gem_reinit_chip(gp);
2624 if (gp->lstate == link_up)
2625 gem_set_link_modes(gp);
2626 }
2627 spin_unlock(&gp->tx_lock);
2628 spin_unlock_irq(&gp->lock);
e3968fc0 2629 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2630
2631 return 0;
2632}
2633
2634static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2635{
2636 struct gem *gp = dev->priv;
6aa20a22 2637
1da177e4
LT		 2638 strcpy(info->driver, DRV_NAME);
2639 strcpy(info->version, DRV_VERSION);
2640 strcpy(info->bus_info, pci_name(gp->pdev));
2641}
6aa20a22 2642
1da177e4
LT		 2643static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2644{
2645 struct gem *gp = dev->priv;
2646
2647 if (gp->phy_type == phy_mii_mdio0 ||
2648 gp->phy_type == phy_mii_mdio1) {
2649 if (gp->phy_mii.def)
2650 cmd->supported = gp->phy_mii.def->features;
2651 else
2652 cmd->supported = (SUPPORTED_10baseT_Half |
2653 SUPPORTED_10baseT_Full);
2654
2655 /* XXX hardcoded stuff for now */
2656 cmd->port = PORT_MII;
2657 cmd->transceiver = XCVR_EXTERNAL;
2658 cmd->phy_address = 0; /* XXX fixed PHYAD */
2659
2660 /* Return current PHY settings */
2661 spin_lock_irq(&gp->lock);
2662 cmd->autoneg = gp->want_autoneg;
2663 cmd->speed = gp->phy_mii.speed;
6aa20a22 2664 cmd->duplex = gp->phy_mii.duplex;
1da177e4
LT		 2665 cmd->advertising = gp->phy_mii.advertising;
2666
2667 /* If we started with a forced mode, we don't have a default
2668 * advertise set, we need to return something sensible so
2669 * userland can re-enable autoneg properly.
2670 */
2671 if (cmd->advertising == 0)
2672 cmd->advertising = cmd->supported;
2673 spin_unlock_irq(&gp->lock);
2674 } else { // XXX PCS ?
2675 cmd->supported =
2676 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2677 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2678 SUPPORTED_Autoneg);
2679 cmd->advertising = cmd->supported;
2680 cmd->speed = 0;
2681 cmd->duplex = cmd->port = cmd->phy_address =
2682 cmd->transceiver = cmd->autoneg = 0;
2683 }
2684 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2685
2686 return 0;
2687}
2688
2689static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2690{
2691 struct gem *gp = dev->priv;
2692
2693 /* Verify the settings we care about. */
2694 if (cmd->autoneg != AUTONEG_ENABLE &&
2695 cmd->autoneg != AUTONEG_DISABLE)
2696 return -EINVAL;
2697
2698 if (cmd->autoneg == AUTONEG_ENABLE &&
2699 cmd->advertising == 0)
2700 return -EINVAL;
2701
2702 if (cmd->autoneg == AUTONEG_DISABLE &&
2703 ((cmd->speed != SPEED_1000 &&
2704 cmd->speed != SPEED_100 &&
2705 cmd->speed != SPEED_10) ||
2706 (cmd->duplex != DUPLEX_HALF &&
2707 cmd->duplex != DUPLEX_FULL)))
2708 return -EINVAL;
6aa20a22 2709
1da177e4
LT		 2710 /* Apply settings and restart link process. */
2711 spin_lock_irq(&gp->lock);
2712 gem_get_cell(gp);
2713 gem_begin_auto_negotiation(gp, cmd);
2714 gem_put_cell(gp);
2715 spin_unlock_irq(&gp->lock);
2716
2717 return 0;
2718}
2719
2720static int gem_nway_reset(struct net_device *dev)
2721{
2722 struct gem *gp = dev->priv;
2723
2724 if (!gp->want_autoneg)
2725 return -EINVAL;
2726
2727 /* Restart link process. */
2728 spin_lock_irq(&gp->lock);
2729 gem_get_cell(gp);
2730 gem_begin_auto_negotiation(gp, NULL);
2731 gem_put_cell(gp);
2732 spin_unlock_irq(&gp->lock);
2733
2734 return 0;
2735}
2736
2737static u32 gem_get_msglevel(struct net_device *dev)
2738{
2739 struct gem *gp = dev->priv;
2740 return gp->msg_enable;
2741}
6aa20a22 2742
1da177e4
LT		 2743static void gem_set_msglevel(struct net_device *dev, u32 value)
2744{
2745 struct gem *gp = dev->priv;
2746 gp->msg_enable = value;
2747}
2748
2749
2750/* Add more when I understand how to program the chip */
2751/* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2752
2753#define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2754
2755static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2756{
2757 struct gem *gp = dev->priv;
2758
2759 /* Add more when I understand how to program the chip */
2760 if (gp->has_wol) {
2761 wol->supported = WOL_SUPPORTED_MASK;
2762 wol->wolopts = gp->wake_on_lan;
2763 } else {
2764 wol->supported = 0;
2765 wol->wolopts = 0;
2766 }
2767}
2768
2769static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2770{
2771 struct gem *gp = dev->priv;
2772
2773 if (!gp->has_wol)
2774 return -EOPNOTSUPP;
2775 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2776 return 0;
2777}
2778
7282d491 2779static const struct ethtool_ops gem_ethtool_ops = {
1da177e4
LT		 2780 .get_drvinfo = gem_get_drvinfo,
2781 .get_link = ethtool_op_get_link,
2782 .get_settings = gem_get_settings,
2783 .set_settings = gem_set_settings,
2784 .nway_reset = gem_nway_reset,
2785 .get_msglevel = gem_get_msglevel,
2786 .set_msglevel = gem_set_msglevel,
2787 .get_wol = gem_get_wol,
2788 .set_wol = gem_set_wol,
2789};
2790
2791static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2792{
2793 struct gem *gp = dev->priv;
2794 struct mii_ioctl_data *data = if_mii(ifr);
2795 int rc = -EOPNOTSUPP;
2796 unsigned long flags;
2797
e3968fc0 2798 /* Hold the PM mutex while doing ioctl's or we may collide
1da177e4
LT		 2799 * with power management.
2800 */
e3968fc0 2801 mutex_lock(&gp->pm_mutex);
6aa20a22 2802
1da177e4
LT		 2803 spin_lock_irqsave(&gp->lock, flags);
2804 gem_get_cell(gp);
2805 spin_unlock_irqrestore(&gp->lock, flags);
2806
2807 switch (cmd) {
2808 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2809 data->phy_id = gp->mii_phy_addr;
2810 /* Fallthrough... */
2811
2812 case SIOCGMIIREG: /* Read MII PHY register. */
2813 if (!gp->running)
2814 rc = -EAGAIN;
2815 else {
2816 data->val_out = __phy_read(gp, data->phy_id & 0x1f,
2817 data->reg_num & 0x1f);
2818 rc = 0;
2819 }
2820 break;
2821
2822 case SIOCSMIIREG: /* Write MII PHY register. */
2823 if (!capable(CAP_NET_ADMIN))
2824 rc = -EPERM;
2825 else if (!gp->running)
2826 rc = -EAGAIN;
2827 else {
2828 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2829 data->val_in);
2830 rc = 0;
2831 }
2832 break;
2833 };
6aa20a22 2834
1da177e4
LT		 2835 spin_lock_irqsave(&gp->lock, flags);
2836 gem_put_cell(gp);
2837 spin_unlock_irqrestore(&gp->lock, flags);
2838
e3968fc0 2839 mutex_unlock(&gp->pm_mutex);
6aa20a22 2840
1da177e4
LT		 2841 return rc;
2842}
2843
dadb830d 2844#if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
1da177e4 2845/* Fetch MAC address from vital product data of PCI ROM. */
4120b028 2846static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
1da177e4
LT		 2847{
2848 int this_offset;
2849
2850 for (this_offset = 0x20; this_offset < len; this_offset++) {
2851 void __iomem *p = rom_base + this_offset;
2852 int i;
2853
2854 if (readb(p + 0) != 0x90 ||
2855 readb(p + 1) != 0x00 ||
2856 readb(p + 2) != 0x09 ||
2857 readb(p + 3) != 0x4e ||
2858 readb(p + 4) != 0x41 ||
2859 readb(p + 5) != 0x06)
2860 continue;
2861
2862 this_offset += 6;
2863 p += 6;
2864
2865 for (i = 0; i < 6; i++)
2866 dev_addr[i] = readb(p + i);
4120b028 2867 return 1;
1da177e4 2868 }
4120b028 2869 return 0;
1da177e4
LT		 2870}
2871
2872static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2873{
4120b028
LT		 2874 size_t size;
2875 void __iomem *p = pci_map_rom(pdev, &size);
1da177e4 2876
4120b028
LT		 2877 if (p) {
2878 int found;
1da177e4 2879
4120b028
LT		 2880 found = readb(p) == 0x55 &&
2881 readb(p + 1) == 0xaa &&
2882 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2883 pci_unmap_rom(pdev, p);
2884 if (found)
2885 return;
2886 }
1da177e4 2887
1da177e4
LT		 2888 /* Sun MAC prefix then 3 random bytes. */
2889 dev_addr[0] = 0x08;
2890 dev_addr[1] = 0x00;
2891 dev_addr[2] = 0x20;
2892 get_random_bytes(dev_addr + 3, 3);
2893 return;
2894}
2895#endif /* not Sparc and not PPC */
2896
2897static int __devinit gem_get_device_address(struct gem *gp)
2898{
dadb830d 2899#if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
1da177e4 2900 struct net_device *dev = gp->dev;
1a2509c9 2901 const unsigned char *addr;
1da177e4 2902
40cd3a45 2903 addr = of_get_property(gp->of_node, "local-mac-address", NULL);
1da177e4 2904 if (addr == NULL) {
457e1a8a
DM		 2905#ifdef CONFIG_SPARC
2906 addr = idprom->id_ethaddr;
2907#else
1da177e4
LT		 2908 printk("\n");
2909 printk(KERN_ERR "%s: can't get mac-address\n", dev->name);
2910 return -1;
457e1a8a 2911#endif
1da177e4
LT		 2912 }
2913 memcpy(dev->dev_addr, addr, 6);
2914#else
2915 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2916#endif
2917 return 0;
2918}
2919
14904398 2920static void gem_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2921{
2922 struct net_device *dev = pci_get_drvdata(pdev);
2923
2924 if (dev) {
2925 struct gem *gp = dev->priv;
2926
2927 unregister_netdev(dev);
2928
2929 /* Stop the link timer */
2930 del_timer_sync(&gp->link_timer);
2931
2932 /* We shouldn't need any locking here */
2933 gem_get_cell(gp);
2934
2935 /* Wait for a pending reset task to complete */
2936 while (gp->reset_task_pending)
2937 yield();
2938 flush_scheduled_work();
2939
2940 /* Shut the PHY down */
2941 gem_stop_phy(gp, 0);
2942
2943 gem_put_cell(gp);
2944
2945 /* Make sure bus master is disabled */
2946 pci_disable_device(gp->pdev);
2947
2948 /* Free resources */
2949 pci_free_consistent(pdev,
2950 sizeof(struct gem_init_block),
2951 gp->init_block,
2952 gp->gblock_dvma);
2953 iounmap(gp->regs);
2954 pci_release_regions(pdev);
2955 free_netdev(dev);
2956
2957 pci_set_drvdata(pdev, NULL);
2958 }
2959}
2960
2961static int __devinit gem_init_one(struct pci_dev *pdev,
2962 const struct pci_device_id *ent)
2963{
2964 static int gem_version_printed = 0;
2965 unsigned long gemreg_base, gemreg_len;
2966 struct net_device *dev;
2967 struct gem *gp;
0795af57
JP		 2968 int err, pci_using_dac;
2969 DECLARE_MAC_BUF(mac);
1da177e4
LT		 2970
2971 if (gem_version_printed++ == 0)
2972 printk(KERN_INFO "%s", version);
2973
2974 /* Apple gmac note: during probe, the chip is powered up by
2975 * the arch code to allow the code below to work (and to let
2976 * the chip be probed on the config space. It won't stay powered
2977 * up until the interface is brought up however, so we can't rely
2978 * on register configuration done at this point.
2979 */
2980 err = pci_enable_device(pdev);
2981 if (err) {
2982 printk(KERN_ERR PFX "Cannot enable MMIO operation, "
2983 "aborting.\n");
2984 return err;
2985 }
2986 pci_set_master(pdev);
2987
2988 /* Configure DMA attributes. */
2989
2990 /* All of the GEM documentation states that 64-bit DMA addressing
2991 * is fully supported and should work just fine. However the
2992 * front end for RIO based GEMs is different and only supports
2993 * 32-bit addressing.
2994 *
2995 * For now we assume the various PPC GEMs are 32-bit only as well.
2996 */
2997 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2998 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
1e7f0bd8 2999 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 3000 pci_using_dac = 1;
3001 } else {
1e7f0bd8 3002 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4
LT		 3003 if (err) {
3004 printk(KERN_ERR PFX "No usable DMA configuration, "
3005 "aborting.\n");
3006 goto err_disable_device;
3007 }
3008 pci_using_dac = 0;
3009 }
6aa20a22 3010
1da177e4
LT		 3011 gemreg_base = pci_resource_start(pdev, 0);
3012 gemreg_len = pci_resource_len(pdev, 0);
3013
3014 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3015 printk(KERN_ERR PFX "Cannot find proper PCI device "
3016 "base address, aborting.\n");
3017 err = -ENODEV;
3018 goto err_disable_device;
3019 }
3020
3021 dev = alloc_etherdev(sizeof(*gp));
3022 if (!dev) {
3023 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
3024 err = -ENOMEM;
3025 goto err_disable_device;
3026 }
1da177e4
LT		 3027 SET_NETDEV_DEV(dev, &pdev->dev);
3028
3029 gp = dev->priv;
3030
3031 err = pci_request_regions(pdev, DRV_NAME);
3032 if (err) {
3033 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
3034 "aborting.\n");
3035 goto err_out_free_netdev;
3036 }
3037
3038 gp->pdev = pdev;
3039 dev->base_addr = (long) pdev;
3040 gp->dev = dev;
3041
3042 gp->msg_enable = DEFAULT_MSG;
3043
3044 spin_lock_init(&gp->lock);
3045 spin_lock_init(&gp->tx_lock);
e3968fc0 3046 mutex_init(&gp->pm_mutex);
1da177e4
LT		 3047
3048 init_timer(&gp->link_timer);
3049 gp->link_timer.function = gem_link_timer;
3050 gp->link_timer.data = (unsigned long) gp;
3051
c4028958 3052 INIT_WORK(&gp->reset_task, gem_reset_task);
6aa20a22 3053
1da177e4
LT		 3054 gp->lstate = link_down;
3055 gp->timer_ticks = 0;
3056 netif_carrier_off(dev);
3057
3058 gp->regs = ioremap(gemreg_base, gemreg_len);
79ea13ce 3059 if (!gp->regs) {
1da177e4
LT		 3060 printk(KERN_ERR PFX "Cannot map device registers, "
3061 "aborting.\n");
3062 err = -EIO;
3063 goto err_out_free_res;
3064 }
3065
3066 /* On Apple, we want a reference to the Open Firmware device-tree
3067 * node. We use it for clock control.
3068 */
457e1a8a 3069#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
1da177e4
LT		 3070 gp->of_node = pci_device_to_OF_node(pdev);
3071#endif
3072
3073 /* Only Apple version supports WOL afaik */
3074 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
3075 gp->has_wol = 1;
3076
3077 /* Make sure cell is enabled */
3078 gem_get_cell(gp);
3079
3080 /* Make sure everything is stopped and in init state */
3081 gem_reset(gp);
3082
3083 /* Fill up the mii_phy structure (even if we won't use it) */
3084 gp->phy_mii.dev = dev;
3085 gp->phy_mii.mdio_read = _phy_read;
3086 gp->phy_mii.mdio_write = _phy_write;
3c326fe9
BH		 3087#ifdef CONFIG_PPC_PMAC
3088 gp->phy_mii.platform_data = gp->of_node;
3089#endif
1da177e4
LT		 3090 /* By default, we start with autoneg */
3091 gp->want_autoneg = 1;
3092
3093 /* Check fifo sizes, PHY type, etc... */
3094 if (gem_check_invariants(gp)) {
3095 err = -ENODEV;
3096 goto err_out_iounmap;
3097 }
3098
3099 /* It is guaranteed that the returned buffer will be at least
3100 * PAGE_SIZE aligned.
3101 */
3102 gp->init_block = (struct gem_init_block *)
3103 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
3104 &gp->gblock_dvma);
3105 if (!gp->init_block) {
3106 printk(KERN_ERR PFX "Cannot allocate init block, "
3107 "aborting.\n");
3108 err = -ENOMEM;
3109 goto err_out_iounmap;
3110 }
3111
3112 if (gem_get_device_address(gp))
3113 goto err_out_free_consistent;
3114
3115 dev->open = gem_open;
3116 dev->stop = gem_close;
3117 dev->hard_start_xmit = gem_start_xmit;
3118 dev->get_stats = gem_get_stats;
3119 dev->set_multicast_list = gem_set_multicast;
3120 dev->do_ioctl = gem_ioctl;
bea3348e 3121 netif_napi_add(dev, &gp->napi, gem_poll, 64);
1da177e4
LT		 3122 dev->ethtool_ops = &gem_ethtool_ops;
3123 dev->tx_timeout = gem_tx_timeout;
3124 dev->watchdog_timeo = 5 * HZ;
3125 dev->change_mtu = gem_change_mtu;
3126 dev->irq = pdev->irq;
3127 dev->dma = 0;
09c72ec8 3128 dev->set_mac_address = gem_set_mac_address;
1da177e4
LT		 3129#ifdef CONFIG_NET_POLL_CONTROLLER
3130 dev->poll_controller = gem_poll_controller;
3131#endif
3132
3133 /* Set that now, in case PM kicks in now */
3134 pci_set_drvdata(pdev, dev);
3135
3136 /* Detect & init PHY, start autoneg, we release the cell now
3137 * too, it will be managed by whoever needs it
3138 */
3139 gem_init_phy(gp);
3140
3141 spin_lock_irq(&gp->lock);
3142 gem_put_cell(gp);
3143 spin_unlock_irq(&gp->lock);
3144
3145 /* Register with kernel */
3146 if (register_netdev(dev)) {
3147 printk(KERN_ERR PFX "Cannot register net device, "
3148 "aborting.\n");
3149 err = -ENOMEM;
3150 goto err_out_free_consistent;
3151 }
3152
0795af57
JP		 3153 printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet "
3154 "%s\n",
3155 dev->name, print_mac(mac, dev->dev_addr));
1da177e4
LT		 3156
3157 if (gp->phy_type == phy_mii_mdio0 ||
3158 gp->phy_type == phy_mii_mdio1)
6aa20a22 3159 printk(KERN_INFO "%s: Found %s PHY\n", dev->name,
1da177e4
LT		 3160 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
3161
3162 /* GEM can do it all... */
3163 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_LLTX;
3164 if (pci_using_dac)
3165 dev->features |= NETIF_F_HIGHDMA;
3166
3167 return 0;
3168
3169err_out_free_consistent:
3170 gem_remove_one(pdev);
3171err_out_iounmap:
3172 gem_put_cell(gp);
3173 iounmap(gp->regs);
3174
3175err_out_free_res:
3176 pci_release_regions(pdev);
3177
3178err_out_free_netdev:
3179 free_netdev(dev);
3180err_disable_device:
3181 pci_disable_device(pdev);
3182 return err;
3183
3184}
3185
3186
3187static struct pci_driver gem_driver = {
3188 .name = GEM_MODULE_NAME,
3189 .id_table = gem_pci_tbl,
3190 .probe = gem_init_one,
14904398 3191 .remove = gem_remove_one,
1da177e4
LT		 3192#ifdef CONFIG_PM
3193 .suspend = gem_suspend,
3194 .resume = gem_resume,
3195#endif /* CONFIG_PM */
3196};
3197
3198static int __init gem_init(void)
3199{
29917620 3200 return pci_register_driver(&gem_driver);
1da177e4
LT		 3201}
3202
3203static void __exit gem_cleanup(void)
3204{
3205 pci_unregister_driver(&gem_driver);
3206}
3207
3208module_init(gem_init);
3209module_exit(gem_cleanup);
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