[net-next-2.6.git] / drivers / net / stmmac / dwmac100_dma.c

/*******************************************************************************
  This is the driver for the MAC 10/100 on-chip Ethernet controller
  currently tested on all the ST boards based on STb7109 and stx7200 SoCs.

  DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
  this code.

  This contains the functions to handle the dma.

  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#include "dwmac100.h"
#include "dwmac_dma.h"

static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx,
			     u32 dma_rx)
{
	u32 value = readl(ioaddr + DMA_BUS_MODE);
	int limit;

	/* DMA SW reset */
	value |= DMA_BUS_MODE_SFT_RESET;
	writel(value, ioaddr + DMA_BUS_MODE);
	limit = 15000;
	while (limit--) {
		if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
			break;
	}
	if (limit < 0)
		return -EBUSY;

	/* Enable Application Access by writing to DMA CSR0 */
	writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT),
	       ioaddr + DMA_BUS_MODE);

	/* Mask interrupts by writing to CSR7 */
	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);

	/* The base address of the RX/TX descriptor lists must be written into
	 * DMA CSR3 and CSR4, respectively. */
	writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
	writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);

	return 0;
}

/* Store and Forward capability is not used at all..
 * The transmit threshold can be programmed by
 * setting the TTC bits in the DMA control register.*/
static void dwmac100_dma_operation_mode(void __iomem *ioaddr, int txmode,
					int rxmode)
{
	u32 csr6 = readl(ioaddr + DMA_CONTROL);

	if (txmode <= 32)
		csr6 |= DMA_CONTROL_TTC_32;
	else if (txmode <= 64)
		csr6 |= DMA_CONTROL_TTC_64;
	else
		csr6 |= DMA_CONTROL_TTC_128;

	writel(csr6, ioaddr + DMA_CONTROL);
}

static void dwmac100_dump_dma_regs(void __iomem *ioaddr)
{
	int i;

	CHIP_DBG(KERN_DEBUG "DWMAC 100 DMA CSR\n");
	for (i = 0; i < 9; i++)
		pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i,
		       (DMA_BUS_MODE + i * 4),
		       readl(ioaddr + DMA_BUS_MODE + i * 4));
	CHIP_DBG(KERN_DEBUG "\t CSR20 (offset 0x%x): 0x%08x\n",
	    DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR));
	CHIP_DBG(KERN_DEBUG "\t CSR21 (offset 0x%x): 0x%08x\n",
	    DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR));
}

/* DMA controller has two counters to track the number of
 * the receive missed frames. */
static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x,
				       void __iomem *ioaddr)
{
	struct net_device_stats *stats = (struct net_device_stats *)data;
	u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR);

	if (unlikely(csr8)) {
		if (csr8 & DMA_MISSED_FRAME_OVE) {
			stats->rx_over_errors += 0x800;
			x->rx_overflow_cntr += 0x800;
		} else {
			unsigned int ove_cntr;
			ove_cntr = ((csr8 & DMA_MISSED_FRAME_OVE_CNTR) >> 17);
			stats->rx_over_errors += ove_cntr;
			x->rx_overflow_cntr += ove_cntr;
		}

		if (csr8 & DMA_MISSED_FRAME_OVE_M) {
			stats->rx_missed_errors += 0xffff;
			x->rx_missed_cntr += 0xffff;
		} else {
			unsigned int miss_f = (csr8 & DMA_MISSED_FRAME_M_CNTR);
			stats->rx_missed_errors += miss_f;
			x->rx_missed_cntr += miss_f;
		}
	}
}

const struct stmmac_dma_ops dwmac100_dma_ops = {
	.init = dwmac100_dma_init,
	.dump_regs = dwmac100_dump_dma_regs,
	.dma_mode = dwmac100_dma_operation_mode,
	.dma_diagnostic_fr = dwmac100_dma_diagnostic_fr,
	.enable_dma_transmission = dwmac_enable_dma_transmission,
	.enable_dma_irq = dwmac_enable_dma_irq,
	.disable_dma_irq = dwmac_disable_dma_irq,
	.start_tx = dwmac_dma_start_tx,
	.stop_tx = dwmac_dma_stop_tx,
	.start_rx = dwmac_dma_start_rx,
	.stop_rx = dwmac_dma_stop_rx,
	.dma_interrupt = dwmac_dma_interrupt,
};
Commit	Line	Data
47dd7a54 GC	1	/*******************************************************************************
	2	This is the driver for the MAC 10/100 on-chip Ethernet controller
	3	currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
	4
	5	DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
	6	this code.
	7
56b106ae	8	This contains the functions to handle the dma.
3c32be63	9
47dd7a54 GC	10	Copyright (C) 2007-2009 STMicroelectronics Ltd
	11
	12	This program is free software; you can redistribute it and/or modify it
	13	under the terms and conditions of the GNU General Public License,
	14	version 2, as published by the Free Software Foundation.
	15
	16	This program is distributed in the hope it will be useful, but WITHOUT
	17	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	18	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	19	more details.
	20
	21	You should have received a copy of the GNU General Public License along with
	22	this program; if not, write to the Free Software Foundation, Inc.,
	23	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	24
	25	The full GNU General Public License is included in this distribution in
	26	the file called "COPYING".
	27
	28	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	29	*******************************************************************************/
	30
7e848ae1	31	#include "dwmac100.h"
aec7ff27	32	#include "dwmac_dma.h"
47dd7a54	33
ad01b7d4	34	static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx,
3c32be63	35	u32 dma_rx)
47dd7a54 GC	36	{
47dd7a54 GC	37	u32 value = readl(ioaddr + DMA_BUS_MODE);
c629882a GC	38	int limit;
c629882a GC	39
47dd7a54 GC	40	/* DMA SW reset */
	41	value \|= DMA_BUS_MODE_SFT_RESET;
	42	writel(value, ioaddr + DMA_BUS_MODE);
c629882a GC	43	limit = 15000;
	44	while (limit--) {
	45	if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
	46	break;
	47	}
	48	if (limit < 0)
	49	return -EBUSY;
47dd7a54 GC	50
	51	/* Enable Application Access by writing to DMA CSR0 */
	52	writel(DMA_BUS_MODE_DEFAULT \| (pbl << DMA_BUS_MODE_PBL_SHIFT),
	53	ioaddr + DMA_BUS_MODE);
	54
	55	/* Mask interrupts by writing to CSR7 */
	56	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
	57
	58	/* The base address of the RX/TX descriptor lists must be written into
	59	* DMA CSR3 and CSR4, respectively. */
	60	writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
	61	writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
	62
	63	return 0;
	64	}
	65
	66	/* Store and Forward capability is not used at all..
	67	* The transmit threshold can be programmed by
	68	* setting the TTC bits in the DMA control register.*/
ad01b7d4	69	static void dwmac100_dma_operation_mode(void __iomem *ioaddr, int txmode,
3c32be63	70	int rxmode)
47dd7a54 GC	71	{
	72	u32 csr6 = readl(ioaddr + DMA_CONTROL);
	73
	74	if (txmode <= 32)
	75	csr6 \|= DMA_CONTROL_TTC_32;
	76	else if (txmode <= 64)
	77	csr6 \|= DMA_CONTROL_TTC_64;
	78	else
	79	csr6 \|= DMA_CONTROL_TTC_128;
	80
	81	writel(csr6, ioaddr + DMA_CONTROL);
47dd7a54 GC	82	}
47dd7a54 GC	83
ad01b7d4	84	static void dwmac100_dump_dma_regs(void __iomem *ioaddr)
47dd7a54 GC	85	{
	86	int i;
	87
56b106ae	88	CHIP_DBG(KERN_DEBUG "DWMAC 100 DMA CSR\n");
47dd7a54 GC	89	for (i = 0; i < 9; i++)
	90	pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i,
	91	(DMA_BUS_MODE + i * 4),
	92	readl(ioaddr + DMA_BUS_MODE + i * 4));
56b106ae	93	CHIP_DBG(KERN_DEBUG "\t CSR20 (offset 0x%x): 0x%08x\n",
47dd7a54	94	DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR));
56b106ae	95	CHIP_DBG(KERN_DEBUG "\t CSR21 (offset 0x%x): 0x%08x\n",
47dd7a54	96	DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR));
47dd7a54 GC	97	}
	98
	99	/* DMA controller has two counters to track the number of
7e848ae1	100	* the receive missed frames. */
3c32be63	101	static void dwmac100_dma_diagnostic_fr(void data, struct stmmac_extra_stats x,
ad01b7d4	102	void __iomem *ioaddr)
47dd7a54 GC	103	{
	104	struct net_device_stats stats = (struct net_device_stats )data;
	105	u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR);
	106
	107	if (unlikely(csr8)) {
	108	if (csr8 & DMA_MISSED_FRAME_OVE) {
	109	stats->rx_over_errors += 0x800;
	110	x->rx_overflow_cntr += 0x800;
	111	} else {
	112	unsigned int ove_cntr;
	113	ove_cntr = ((csr8 & DMA_MISSED_FRAME_OVE_CNTR) >> 17);
	114	stats->rx_over_errors += ove_cntr;
	115	x->rx_overflow_cntr += ove_cntr;
	116	}
	117
	118	if (csr8 & DMA_MISSED_FRAME_OVE_M) {
	119	stats->rx_missed_errors += 0xffff;
	120	x->rx_missed_cntr += 0xffff;
	121	} else {
	122	unsigned int miss_f = (csr8 & DMA_MISSED_FRAME_M_CNTR);
	123	stats->rx_missed_errors += miss_f;
	124	x->rx_missed_cntr += miss_f;
	125	}
	126	}
47dd7a54 GC	127	}
47dd7a54 GC	128
cadb7924	129	const struct stmmac_dma_ops dwmac100_dma_ops = {
7e848ae1 GC	130	.init = dwmac100_dma_init,
	131	.dump_regs = dwmac100_dump_dma_regs,
	132	.dma_mode = dwmac100_dma_operation_mode,
	133	.dma_diagnostic_fr = dwmac100_dma_diagnostic_fr,
aec7ff27 GC	134	.enable_dma_transmission = dwmac_enable_dma_transmission,
	135	.enable_dma_irq = dwmac_enable_dma_irq,
	136	.disable_dma_irq = dwmac_disable_dma_irq,
	137	.start_tx = dwmac_dma_start_tx,
	138	.stop_tx = dwmac_dma_stop_tx,
	139	.start_rx = dwmac_dma_start_rx,
	140	.stop_rx = dwmac_dma_stop_rx,
	141	.dma_interrupt = dwmac_dma_interrupt,
db98a0b0	142	};