[net-next-2.6.git] / drivers / net / stmmac / common.h

/*******************************************************************************
  STMMAC Common Header File

  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#include <linux/netdevice.h>
#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
#define STMMAC_VLAN_TAG_USED
#include <linux/if_vlan.h>
#endif

#include "descs.h"

#undef CHIP_DEBUG_PRINT
/* Turn-on extra printk debug for MAC core, dma and descriptors */
/* #define CHIP_DEBUG_PRINT */

#ifdef CHIP_DEBUG_PRINT
#define CHIP_DBG(fmt, args...)  printk(fmt, ## args)
#else
#define CHIP_DBG(fmt, args...)  do { } while (0)
#endif

#undef FRAME_FILTER_DEBUG
/* #define FRAME_FILTER_DEBUG */

struct stmmac_extra_stats {
	/* Transmit errors */
	unsigned long tx_underflow ____cacheline_aligned;
	unsigned long tx_carrier;
	unsigned long tx_losscarrier;
	unsigned long tx_heartbeat;
	unsigned long tx_deferred;
	unsigned long tx_vlan;
	unsigned long tx_jabber;
	unsigned long tx_frame_flushed;
	unsigned long tx_payload_error;
	unsigned long tx_ip_header_error;
	/* Receive errors */
	unsigned long rx_desc;
	unsigned long rx_partial;
	unsigned long rx_runt;
	unsigned long rx_toolong;
	unsigned long rx_collision;
	unsigned long rx_crc;
	unsigned long rx_length;
	unsigned long rx_mii;
	unsigned long rx_multicast;
	unsigned long rx_gmac_overflow;
	unsigned long rx_watchdog;
	unsigned long da_rx_filter_fail;
	unsigned long sa_rx_filter_fail;
	unsigned long rx_missed_cntr;
	unsigned long rx_overflow_cntr;
	unsigned long rx_vlan;
	/* Tx/Rx IRQ errors */
	unsigned long tx_undeflow_irq;
	unsigned long tx_process_stopped_irq;
	unsigned long tx_jabber_irq;
	unsigned long rx_overflow_irq;
	unsigned long rx_buf_unav_irq;
	unsigned long rx_process_stopped_irq;
	unsigned long rx_watchdog_irq;
	unsigned long tx_early_irq;
	unsigned long fatal_bus_error_irq;
	/* Extra info */
	unsigned long threshold;
	unsigned long tx_pkt_n;
	unsigned long rx_pkt_n;
	unsigned long poll_n;
	unsigned long sched_timer_n;
	unsigned long normal_irq_n;
};

#define HASH_TABLE_SIZE 64
#define PAUSE_TIME 0x200

/* Flow Control defines */
#define FLOW_OFF	0
#define FLOW_RX		1
#define FLOW_TX		2
#define FLOW_AUTO	(FLOW_TX | FLOW_RX)

#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */

enum rx_frame_status { /* IPC status */
	good_frame = 0,
	discard_frame = 1,
	csum_none = 2,
	llc_snap = 4,
};

enum tx_dma_irq_status {
	tx_hard_error = 1,
	tx_hard_error_bump_tc = 2,
	handle_tx_rx = 3,
};

/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
#define BUF_SIZE_16KiB 16384
#define BUF_SIZE_8KiB 8192
#define BUF_SIZE_4KiB 4096
#define BUF_SIZE_2KiB 2048

/* Power Down and WOL */
#define PMT_NOT_SUPPORTED 0
#define PMT_SUPPORTED 1

/* Common MAC defines */
#define MAC_CTRL_REG		0x00000000	/* MAC Control */
#define MAC_ENABLE_TX		0x00000008	/* Transmitter Enable */
#define MAC_RNABLE_RX		0x00000004	/* Receiver Enable */

/* MAC Management Counters register */
#define MMC_CONTROL		0x00000100	/* MMC Control */
#define MMC_HIGH_INTR		0x00000104	/* MMC High Interrupt */
#define MMC_LOW_INTR		0x00000108	/* MMC Low Interrupt */
#define MMC_HIGH_INTR_MASK	0x0000010c	/* MMC High Interrupt Mask */
#define MMC_LOW_INTR_MASK	0x00000110	/* MMC Low Interrupt Mask */

#define MMC_CONTROL_MAX_FRM_MASK	0x0003ff8	/* Maximum Frame Size */
#define MMC_CONTROL_MAX_FRM_SHIFT	3
#define MMC_CONTROL_MAX_FRAME		0x7FF

struct stmmac_desc_ops {
	/* DMA RX descriptor ring initialization */
	void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
			      int disable_rx_ic);
	/* DMA TX descriptor ring initialization */
	void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);

	/* Invoked by the xmit function to prepare the tx descriptor */
	void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
				 int csum_flag);
	/* Set/get the owner of the descriptor */
	void (*set_tx_owner) (struct dma_desc *p);
	int (*get_tx_owner) (struct dma_desc *p);
	/* Invoked by the xmit function to close the tx descriptor */
	void (*close_tx_desc) (struct dma_desc *p);
	/* Clean the tx descriptor as soon as the tx irq is received */
	void (*release_tx_desc) (struct dma_desc *p);
	/* Clear interrupt on tx frame completion. When this bit is
	 * set an interrupt happens as soon as the frame is transmitted */
	void (*clear_tx_ic) (struct dma_desc *p);
	/* Last tx segment reports the transmit status */
	int (*get_tx_ls) (struct dma_desc *p);
	/* Return the transmit status looking at the TDES1 */
	int (*tx_status) (void *data, struct stmmac_extra_stats *x,
			  struct dma_desc *p, void __iomem *ioaddr);
	/* Get the buffer size from the descriptor */
	int (*get_tx_len) (struct dma_desc *p);
	/* Handle extra events on specific interrupts hw dependent */
	int (*get_rx_owner) (struct dma_desc *p);
	void (*set_rx_owner) (struct dma_desc *p);
	/* Get the receive frame size */
	int (*get_rx_frame_len) (struct dma_desc *p);
	/* Return the reception status looking at the RDES1 */
	int (*rx_status) (void *data, struct stmmac_extra_stats *x,
			  struct dma_desc *p);
};

struct stmmac_dma_ops {
	/* DMA core initialization */
	int (*init) (void __iomem *ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
	/* Dump DMA registers */
	void (*dump_regs) (void __iomem *ioaddr);
	/* Set tx/rx threshold in the csr6 register
	 * An invalid value enables the store-and-forward mode */
	void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
	/* To track extra statistic (if supported) */
	void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
				   void __iomem *ioaddr);
	void (*enable_dma_transmission) (void __iomem *ioaddr);
	void (*enable_dma_irq) (void __iomem *ioaddr);
	void (*disable_dma_irq) (void __iomem *ioaddr);
	void (*start_tx) (void __iomem *ioaddr);
	void (*stop_tx) (void __iomem *ioaddr);
	void (*start_rx) (void __iomem *ioaddr);
	void (*stop_rx) (void __iomem *ioaddr);
	int (*dma_interrupt) (void __iomem *ioaddr,
			      struct stmmac_extra_stats *x);
};

struct stmmac_ops {
	/* MAC core initialization */
	void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned;
	/* Support checksum offload engine */
	int  (*rx_coe) (void __iomem *ioaddr);
	/* Dump MAC registers */
	void (*dump_regs) (void __iomem *ioaddr);
	/* Handle extra events on specific interrupts hw dependent */
	void (*host_irq_status) (void __iomem *ioaddr);
	/* Multicast filter setting */
	void (*set_filter) (struct net_device *dev);
	/* Flow control setting */
	void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
			   unsigned int fc, unsigned int pause_time);
	/* Set power management mode (e.g. magic frame) */
	void (*pmt) (void __iomem *ioaddr, unsigned long mode);
	/* Set/Get Unicast MAC addresses */
	void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
			       unsigned int reg_n);
	void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
			       unsigned int reg_n);
};

struct mac_link {
	int port;
	int duplex;
	int speed;
};

struct mii_regs {
	unsigned int addr;	/* MII Address */
	unsigned int data;	/* MII Data */
};

struct mac_device_info {
	struct stmmac_ops	*mac;
	struct stmmac_desc_ops	*desc;
	struct stmmac_dma_ops	*dma;
	struct mii_regs mii;	/* MII register Addresses */
	struct mac_link link;
};

struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);

extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
				unsigned int high, unsigned int low);
extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
				unsigned int high, unsigned int low);
extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
Commit	Line	Data
47dd7a54 GC	1	/*******************************************************************************
	2	STMMAC Common Header File
	3
	4	Copyright (C) 2007-2009 STMicroelectronics Ltd
	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	23	*******************************************************************************/
	24
5e33c791	25	#include <linux/netdevice.h>
8f617541 GC	26	#if defined(CONFIG_VLAN_8021Q) \|\| defined(CONFIG_VLAN_8021Q_MODULE)
	27	#define STMMAC_VLAN_TAG_USED
	28	#include <linux/if_vlan.h>
	29	#endif
	30
56b106ae GC	31	#include "descs.h"
	32
	33	#undef CHIP_DEBUG_PRINT
	34	/* Turn-on extra printk debug for MAC core, dma and descriptors */
	35	/* #define CHIP_DEBUG_PRINT */
	36
	37	#ifdef CHIP_DEBUG_PRINT
	38	#define CHIP_DBG(fmt, args...) printk(fmt, ## args)
	39	#else
	40	#define CHIP_DBG(fmt, args...) do { } while (0)
	41	#endif
	42
	43	#undef FRAME_FILTER_DEBUG
	44	/* #define FRAME_FILTER_DEBUG */
47dd7a54	45
47dd7a54 GC	46	struct stmmac_extra_stats {
	47	/* Transmit errors */
	48	unsigned long tx_underflow ____cacheline_aligned;
	49	unsigned long tx_carrier;
	50	unsigned long tx_losscarrier;
	51	unsigned long tx_heartbeat;
	52	unsigned long tx_deferred;
	53	unsigned long tx_vlan;
	54	unsigned long tx_jabber;
	55	unsigned long tx_frame_flushed;
	56	unsigned long tx_payload_error;
	57	unsigned long tx_ip_header_error;
	58	/* Receive errors */
	59	unsigned long rx_desc;
	60	unsigned long rx_partial;
	61	unsigned long rx_runt;
	62	unsigned long rx_toolong;
	63	unsigned long rx_collision;
	64	unsigned long rx_crc;
1b924032	65	unsigned long rx_length;
47dd7a54 GC	66	unsigned long rx_mii;
	67	unsigned long rx_multicast;
	68	unsigned long rx_gmac_overflow;
	69	unsigned long rx_watchdog;
	70	unsigned long da_rx_filter_fail;
	71	unsigned long sa_rx_filter_fail;
	72	unsigned long rx_missed_cntr;
	73	unsigned long rx_overflow_cntr;
	74	unsigned long rx_vlan;
	75	/* Tx/Rx IRQ errors */
	76	unsigned long tx_undeflow_irq;
	77	unsigned long tx_process_stopped_irq;
	78	unsigned long tx_jabber_irq;
	79	unsigned long rx_overflow_irq;
	80	unsigned long rx_buf_unav_irq;
	81	unsigned long rx_process_stopped_irq;
	82	unsigned long rx_watchdog_irq;
	83	unsigned long tx_early_irq;
	84	unsigned long fatal_bus_error_irq;
	85	/* Extra info */
	86	unsigned long threshold;
	87	unsigned long tx_pkt_n;
	88	unsigned long rx_pkt_n;
	89	unsigned long poll_n;
	90	unsigned long sched_timer_n;
	91	unsigned long normal_irq_n;
	92	};
	93
aec7ff27 GC	94	#define HASH_TABLE_SIZE 64
	95	#define PAUSE_TIME 0x200
	96
	97	/* Flow Control defines */
	98	#define FLOW_OFF 0
	99	#define FLOW_RX 1
	100	#define FLOW_TX 2
	101	#define FLOW_AUTO (FLOW_TX \| FLOW_RX)
	102
	103	#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
	104
aec7ff27	105	enum rx_frame_status { /* IPC status */
47dd7a54 GC	106	good_frame = 0,
	107	discard_frame = 1,
	108	csum_none = 2,
3eeb2997	109	llc_snap = 4,
47dd7a54 GC	110	};
47dd7a54 GC	111
aec7ff27 GC	112	enum tx_dma_irq_status {
	113	tx_hard_error = 1,
	114	tx_hard_error_bump_tc = 2,
	115	handle_tx_rx = 3,
	116	};
47dd7a54	117
aec7ff27 GC	118	/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
	119	#define BUF_SIZE_16KiB 16384
	120	#define BUF_SIZE_8KiB 8192
	121	#define BUF_SIZE_4KiB 4096
	122	#define BUF_SIZE_2KiB 2048
47dd7a54	123
aec7ff27 GC	124	/* Power Down and WOL */
	125	#define PMT_NOT_SUPPORTED 0
	126	#define PMT_SUPPORTED 1
47dd7a54	127
aec7ff27 GC	128	/* Common MAC defines */
	129	#define MAC_CTRL_REG 0x00000000 /* MAC Control */
	130	#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
	131	#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
47dd7a54	132
aec7ff27 GC	133	/* MAC Management Counters register */
	134	#define MMC_CONTROL 0x00000100 /* MMC Control */
	135	#define MMC_HIGH_INTR 0x00000104 /* MMC High Interrupt */
	136	#define MMC_LOW_INTR 0x00000108 /* MMC Low Interrupt */
	137	#define MMC_HIGH_INTR_MASK 0x0000010c /* MMC High Interrupt Mask */
	138	#define MMC_LOW_INTR_MASK 0x00000110 /* MMC Low Interrupt Mask */
47dd7a54	139
aec7ff27 GC	140	#define MMC_CONTROL_MAX_FRM_MASK 0x0003ff8 /* Maximum Frame Size */
	141	#define MMC_CONTROL_MAX_FRM_SHIFT 3
	142	#define MMC_CONTROL_MAX_FRAME 0x7FF
47dd7a54	143
db98a0b0 GC	144	struct stmmac_desc_ops {
db98a0b0 GC	145	/* DMA RX descriptor ring initialization */
47dd7a54	146	void (init_rx_desc) (struct dma_desc p, unsigned int ring_size,
db98a0b0 GC	147	int disable_rx_ic);
db98a0b0 GC	148	/* DMA TX descriptor ring initialization */
47dd7a54 GC	149	void (init_tx_desc) (struct dma_desc p, unsigned int ring_size);
	150
	151	/* Invoked by the xmit function to prepare the tx descriptor */
	152	void (prepare_tx_desc) (struct dma_desc p, int is_fs, int len,
	153	int csum_flag);
	154	/* Set/get the owner of the descriptor */
	155	void (set_tx_owner) (struct dma_desc p);
	156	int (get_tx_owner) (struct dma_desc p);
	157	/* Invoked by the xmit function to close the tx descriptor */
	158	void (close_tx_desc) (struct dma_desc p);
	159	/* Clean the tx descriptor as soon as the tx irq is received */
	160	void (release_tx_desc) (struct dma_desc p);
	161	/* Clear interrupt on tx frame completion. When this bit is
	162	* set an interrupt happens as soon as the frame is transmitted */
	163	void (clear_tx_ic) (struct dma_desc p);
	164	/* Last tx segment reports the transmit status */
	165	int (get_tx_ls) (struct dma_desc p);
	166	/* Return the transmit status looking at the TDES1 */
	167	int (tx_status) (void data, struct stmmac_extra_stats *x,
ad01b7d4	168	struct dma_desc p, void __iomem ioaddr);
47dd7a54 GC	169	/* Get the buffer size from the descriptor */
	170	int (get_tx_len) (struct dma_desc p);
	171	/* Handle extra events on specific interrupts hw dependent */
47dd7a54 GC	172	int (get_rx_owner) (struct dma_desc p);
	173	void (set_rx_owner) (struct dma_desc p);
	174	/* Get the receive frame size */
	175	int (get_rx_frame_len) (struct dma_desc p);
	176	/* Return the reception status looking at the RDES1 */
	177	int (rx_status) (void data, struct stmmac_extra_stats *x,
	178	struct dma_desc *p);
db98a0b0 GC	179	};
	180
	181	struct stmmac_dma_ops {
	182	/* DMA core initialization */
ad01b7d4	183	int (init) (void __iomem ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
db98a0b0	184	/* Dump DMA registers */
ad01b7d4	185	void (dump_regs) (void __iomem ioaddr);
db98a0b0 GC	186	/* Set tx/rx threshold in the csr6 register
db98a0b0 GC	187	* An invalid value enables the store-and-forward mode */
ad01b7d4	188	void (dma_mode) (void __iomem ioaddr, int txmode, int rxmode);
db98a0b0 GC	189	/* To track extra statistic (if supported) */
db98a0b0 GC	190	void (dma_diagnostic_fr) (void data, struct stmmac_extra_stats *x,
ad01b7d4 GC	191	void __iomem *ioaddr);
	192	void (enable_dma_transmission) (void __iomem ioaddr);
	193	void (enable_dma_irq) (void __iomem ioaddr);
	194	void (disable_dma_irq) (void __iomem ioaddr);
	195	void (start_tx) (void __iomem ioaddr);
	196	void (stop_tx) (void __iomem ioaddr);
	197	void (start_rx) (void __iomem ioaddr);
	198	void (stop_rx) (void __iomem ioaddr);
	199	int (dma_interrupt) (void __iomem ioaddr,
aec7ff27	200	struct stmmac_extra_stats *x);
db98a0b0 GC	201	};
	202
	203	struct stmmac_ops {
	204	/* MAC core initialization */
ad01b7d4	205	void (core_init) (void __iomem ioaddr) ____cacheline_aligned;
ebbb293f GC	206	/* Support checksum offload engine */
ebbb293f GC	207	int (rx_coe) (void __iomem ioaddr);
db98a0b0	208	/* Dump MAC registers */
ad01b7d4	209	void (dump_regs) (void __iomem ioaddr);
db98a0b0	210	/* Handle extra events on specific interrupts hw dependent */
ad01b7d4	211	void (host_irq_status) (void __iomem ioaddr);
47dd7a54 GC	212	/* Multicast filter setting */
	213	void (set_filter) (struct net_device dev);
	214	/* Flow control setting */
ad01b7d4	215	void (flow_ctrl) (void __iomem ioaddr, unsigned int duplex,
47dd7a54 GC	216	unsigned int fc, unsigned int pause_time);
47dd7a54 GC	217	/* Set power management mode (e.g. magic frame) */
ad01b7d4	218	void (pmt) (void __iomem ioaddr, unsigned long mode);
47dd7a54	219	/* Set/Get Unicast MAC addresses */
ad01b7d4	220	void (set_umac_addr) (void __iomem ioaddr, unsigned char *addr,
db98a0b0	221	unsigned int reg_n);
ad01b7d4	222	void (get_umac_addr) (void __iomem ioaddr, unsigned char *addr,
db98a0b0	223	unsigned int reg_n);
47dd7a54 GC	224	};
	225
	226	struct mac_link {
	227	int port;
	228	int duplex;
	229	int speed;
	230	};
	231
	232	struct mii_regs {
	233	unsigned int addr; /* MII Address */
	234	unsigned int data; /* MII Data */
	235	};
	236
47dd7a54	237	struct mac_device_info {
db98a0b0 GC	238	struct stmmac_ops *mac;
	239	struct stmmac_desc_ops *desc;
	240	struct stmmac_dma_ops *dma;
db98a0b0 GC	241	struct mii_regs mii; /* MII register Addresses */
db98a0b0 GC	242	struct mac_link link;
47dd7a54 GC	243	};
47dd7a54 GC	244
ad01b7d4 GC	245	struct mac_device_info dwmac1000_setup(void __iomem ioaddr);
ad01b7d4 GC	246	struct mac_device_info dwmac100_setup(void __iomem ioaddr);
aec7ff27	247
ad01b7d4	248	extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
aec7ff27	249	unsigned int high, unsigned int low);
ad01b7d4	250	extern void stmmac_get_mac_addr(void __iomem ioaddr, unsigned char addr,
aec7ff27	251	unsigned int high, unsigned int low);
ad01b7d4	252	extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);