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Merge branch 'ebt_config_compat_v4' of git://git.breakpoint.cc/fw/nf-next-2.6
[net-next-2.6.git] / drivers / net / smsc9420.c
CommitLineData
2cb37728
SG		 1 /***************************************************************************
2 *
3 * Copyright (C) 2007,2008 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 ***************************************************************************
20 */
21
22#include <linux/kernel.h>
23#include <linux/netdevice.h>
24#include <linux/phy.h>
25#include <linux/pci.h>
26#include <linux/if_vlan.h>
27#include <linux/dma-mapping.h>
28#include <linux/crc32.h>
29#include <asm/unaligned.h>
30#include "smsc9420.h"
31
32#define DRV_NAME "smsc9420"
33#define PFX DRV_NAME ": "
34#define DRV_MDIONAME "smsc9420-mdio"
35#define DRV_DESCRIPTION "SMSC LAN9420 driver"
36#define DRV_VERSION "1.01"
37
38MODULE_LICENSE("GPL");
39MODULE_VERSION(DRV_VERSION);
40
41struct smsc9420_dma_desc {
42 u32 status;
43 u32 length;
44 u32 buffer1;
45 u32 buffer2;
46};
47
48struct smsc9420_ring_info {
49 struct sk_buff *skb;
50 dma_addr_t mapping;
51};
52
53struct smsc9420_pdata {
54 void __iomem *base_addr;
55 struct pci_dev *pdev;
56 struct net_device *dev;
57
58 struct smsc9420_dma_desc *rx_ring;
59 struct smsc9420_dma_desc *tx_ring;
60 struct smsc9420_ring_info *tx_buffers;
61 struct smsc9420_ring_info *rx_buffers;
62 dma_addr_t rx_dma_addr;
63 dma_addr_t tx_dma_addr;
64 int tx_ring_head, tx_ring_tail;
65 int rx_ring_head, rx_ring_tail;
66
67 spinlock_t int_lock;
68 spinlock_t phy_lock;
69
70 struct napi_struct napi;
71
72 bool software_irq_signal;
73 bool rx_csum;
74 u32 msg_enable;
75
76 struct phy_device *phy_dev;
77 struct mii_bus *mii_bus;
78 int phy_irq[PHY_MAX_ADDR];
79 int last_duplex;
80 int last_carrier;
81};
82
a3aa1884 83static DEFINE_PCI_DEVICE_TABLE(smsc9420_id_table) = {
2cb37728
SG		 84 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
85 { 0, }
86};
87
88MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
89
90#define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
91
92static uint smsc_debug;
93static uint debug = -1;
94module_param(debug, uint, 0);
95MODULE_PARM_DESC(debug, "debug level");
96
97#define smsc_dbg(TYPE, f, a...) \
98do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
99 printk(KERN_DEBUG PFX f "\n", ## a); \
100} while (0)
101
102#define smsc_info(TYPE, f, a...) \
103do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
104 printk(KERN_INFO PFX f "\n", ## a); \
105} while (0)
106
107#define smsc_warn(TYPE, f, a...) \
108do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
109 printk(KERN_WARNING PFX f "\n", ## a); \
110} while (0)
111
112static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
113{
114 return ioread32(pd->base_addr + offset);
115}
116
117static inline void
118smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
119{
120 iowrite32(value, pd->base_addr + offset);
121}
122
123static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
124{
125 /* to ensure PCI write completion, we must perform a PCI read */
126 smsc9420_reg_read(pd, ID_REV);
127}
128
129static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
130{
131 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
132 unsigned long flags;
133 u32 addr;
134 int i, reg = -EIO;
135
136 spin_lock_irqsave(&pd->phy_lock, flags);
137
138 /* confirm MII not busy */
139 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
140 smsc_warn(DRV, "MII is busy???");
141 goto out;
142 }
143
144 /* set the address, index & direction (read from PHY) */
145 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
146 MII_ACCESS_MII_READ_;
147 smsc9420_reg_write(pd, MII_ACCESS, addr);
148
149 /* wait for read to complete with 50us timeout */
150 for (i = 0; i < 5; i++) {
151 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
152 MII_ACCESS_MII_BUSY_)) {
153 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
154 goto out;
155 }
156 udelay(10);
157 }
158
159 smsc_warn(DRV, "MII busy timeout!");
160
161out:
162 spin_unlock_irqrestore(&pd->phy_lock, flags);
163 return reg;
164}
165
166static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
167 u16 val)
168{
169 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
170 unsigned long flags;
171 u32 addr;
172 int i, reg = -EIO;
173
174 spin_lock_irqsave(&pd->phy_lock, flags);
175
176 /* confirm MII not busy */
177 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
178 smsc_warn(DRV, "MII is busy???");
179 goto out;
180 }
181
182 /* put the data to write in the MAC */
183 smsc9420_reg_write(pd, MII_DATA, (u32)val);
184
185 /* set the address, index & direction (write to PHY) */
186 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
187 MII_ACCESS_MII_WRITE_;
188 smsc9420_reg_write(pd, MII_ACCESS, addr);
189
190 /* wait for write to complete with 50us timeout */
191 for (i = 0; i < 5; i++) {
192 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
193 MII_ACCESS_MII_BUSY_)) {
194 reg = 0;
195 goto out;
196 }
197 udelay(10);
198 }
199
200 smsc_warn(DRV, "MII busy timeout!");
201
202out:
203 spin_unlock_irqrestore(&pd->phy_lock, flags);
204 return reg;
205}
206
207/* Returns hash bit number for given MAC address
208 * Example:
209 * 01 00 5E 00 00 01 -> returns bit number 31 */
210static u32 smsc9420_hash(u8 addr[ETH_ALEN])
211{
212 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
213}
214
215static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
216{
217 int timeout = 100000;
218
219 BUG_ON(!pd);
220
221 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
222 smsc_dbg(DRV, "smsc9420_eeprom_reload: Eeprom busy");
223 return -EIO;
224 }
225
226 smsc9420_reg_write(pd, E2P_CMD,
227 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
228
229 do {
230 udelay(10);
231 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
232 return 0;
233 } while (timeout--);
234
235 smsc_warn(DRV, "smsc9420_eeprom_reload: Eeprom timed out");
236 return -EIO;
237}
238
239/* Standard ioctls for mii-tool */
240static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
241{
242 struct smsc9420_pdata *pd = netdev_priv(dev);
243
244 if (!netif_running(dev) || !pd->phy_dev)
245 return -EINVAL;
246
247 return phy_mii_ioctl(pd->phy_dev, if_mii(ifr), cmd);
248}
249
250static int smsc9420_ethtool_get_settings(struct net_device *dev,
251 struct ethtool_cmd *cmd)
252{
253 struct smsc9420_pdata *pd = netdev_priv(dev);
254
6c53b1b1
SG		 255 if (!pd->phy_dev)
256 return -ENODEV;
257
2cb37728
SG		 258 cmd->maxtxpkt = 1;
259 cmd->maxrxpkt = 1;
260 return phy_ethtool_gset(pd->phy_dev, cmd);
261}
262
263static int smsc9420_ethtool_set_settings(struct net_device *dev,
264 struct ethtool_cmd *cmd)
265{
266 struct smsc9420_pdata *pd = netdev_priv(dev);
267
6c53b1b1
SG		 268 if (!pd->phy_dev)
269 return -ENODEV;
270
2cb37728
SG		 271 return phy_ethtool_sset(pd->phy_dev, cmd);
272}
273
274static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
275 struct ethtool_drvinfo *drvinfo)
276{
277 struct smsc9420_pdata *pd = netdev_priv(netdev);
278
279 strcpy(drvinfo->driver, DRV_NAME);
280 strcpy(drvinfo->bus_info, pci_name(pd->pdev));
281 strcpy(drvinfo->version, DRV_VERSION);
282}
283
284static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
285{
286 struct smsc9420_pdata *pd = netdev_priv(netdev);
287 return pd->msg_enable;
288}
289
290static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
291{
292 struct smsc9420_pdata *pd = netdev_priv(netdev);
293 pd->msg_enable = data;
294}
295
296static int smsc9420_ethtool_nway_reset(struct net_device *netdev)
297{
298 struct smsc9420_pdata *pd = netdev_priv(netdev);
6c53b1b1
SG		 299
300 if (!pd->phy_dev)
301 return -ENODEV;
302
2cb37728
SG		 303 return phy_start_aneg(pd->phy_dev);
304}
305
a7276db6
SG		 306static int smsc9420_ethtool_getregslen(struct net_device *dev)
307{
308 /* all smsc9420 registers plus all phy registers */
309 return 0x100 + (32 * sizeof(u32));
310}
311
312static void
313smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
314 void *buf)
315{
316 struct smsc9420_pdata *pd = netdev_priv(dev);
317 struct phy_device *phy_dev = pd->phy_dev;
318 unsigned int i, j = 0;
319 u32 *data = buf;
320
321 regs->version = smsc9420_reg_read(pd, ID_REV);
322 for (i = 0; i < 0x100; i += (sizeof(u32)))
323 data[j++] = smsc9420_reg_read(pd, i);
324
6c53b1b1
SG		 325 // cannot read phy registers if the net device is down
326 if (!phy_dev)
327 return;
328
a7276db6
SG		 329 for (i = 0; i <= 31; i++)
330 data[j++] = smsc9420_mii_read(phy_dev->bus, phy_dev->addr, i);
331}
332
012b215c
SG		 333static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
334{
335 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
336 temp &= ~GPIO_CFG_EEPR_EN_;
337 smsc9420_reg_write(pd, GPIO_CFG, temp);
338 msleep(1);
339}
340
341static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
342{
343 int timeout = 100;
344 u32 e2cmd;
345
346 smsc_dbg(HW, "op 0x%08x", op);
347 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
348 smsc_warn(HW, "Busy at start");
349 return -EBUSY;
350 }
351
352 e2cmd = op | E2P_CMD_EPC_BUSY_;
353 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
354
355 do {
356 msleep(1);
357 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
9df8f4e3 358 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
012b215c
SG		 359
360 if (!timeout) {
361 smsc_info(HW, "TIMED OUT");
362 return -EAGAIN;
363 }
364
365 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
366 smsc_info(HW, "Error occured during eeprom operation");
367 return -EINVAL;
368 }
369
370 return 0;
371}
372
373static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
374 u8 address, u8 *data)
375{
376 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
377 int ret;
378
379 smsc_dbg(HW, "address 0x%x", address);
380 ret = smsc9420_eeprom_send_cmd(pd, op);
381
382 if (!ret)
383 data[address] = smsc9420_reg_read(pd, E2P_DATA);
384
385 return ret;
386}
387
388static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
389 u8 address, u8 data)
390{
391 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
392 int ret;
393
394 smsc_dbg(HW, "address 0x%x, data 0x%x", address, data);
395 ret = smsc9420_eeprom_send_cmd(pd, op);
396
397 if (!ret) {
398 op = E2P_CMD_EPC_CMD_WRITE_ | address;
399 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
400 ret = smsc9420_eeprom_send_cmd(pd, op);
401 }
402
403 return ret;
404}
405
406static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)
407{
408 return SMSC9420_EEPROM_SIZE;
409}
410
411static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
412 struct ethtool_eeprom *eeprom, u8 *data)
413{
414 struct smsc9420_pdata *pd = netdev_priv(dev);
415 u8 eeprom_data[SMSC9420_EEPROM_SIZE];
416 int len, i;
417
418 smsc9420_eeprom_enable_access(pd);
419
420 len = min(eeprom->len, SMSC9420_EEPROM_SIZE);
421 for (i = 0; i < len; i++) {
422 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
423 if (ret < 0) {
424 eeprom->len = 0;
425 return ret;
426 }
427 }
428
429 memcpy(data, &eeprom_data[eeprom->offset], len);
196b7e1b 430 eeprom->magic = SMSC9420_EEPROM_MAGIC;
012b215c
SG		 431 eeprom->len = len;
432 return 0;
433}
434
435static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
436 struct ethtool_eeprom *eeprom, u8 *data)
437{
438 struct smsc9420_pdata *pd = netdev_priv(dev);
439 int ret;
440
196b7e1b
SG		 441 if (eeprom->magic != SMSC9420_EEPROM_MAGIC)
442 return -EINVAL;
443
012b215c
SG		 444 smsc9420_eeprom_enable_access(pd);
445 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
446 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
447 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
448
449 /* Single byte write, according to man page */
450 eeprom->len = 1;
451
452 return ret;
453}
454
2cb37728
SG		 455static const struct ethtool_ops smsc9420_ethtool_ops = {
456 .get_settings = smsc9420_ethtool_get_settings,
457 .set_settings = smsc9420_ethtool_set_settings,
458 .get_drvinfo = smsc9420_ethtool_get_drvinfo,
459 .get_msglevel = smsc9420_ethtool_get_msglevel,
460 .set_msglevel = smsc9420_ethtool_set_msglevel,
461 .nway_reset = smsc9420_ethtool_nway_reset,
462 .get_link = ethtool_op_get_link,
012b215c
SG		 463 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len,
464 .get_eeprom = smsc9420_ethtool_get_eeprom,
465 .set_eeprom = smsc9420_ethtool_set_eeprom,
a7276db6
SG		 466 .get_regs_len = smsc9420_ethtool_getregslen,
467 .get_regs = smsc9420_ethtool_getregs,
2cb37728
SG		 468};
469
470/* Sets the device MAC address to dev_addr */
471static void smsc9420_set_mac_address(struct net_device *dev)
472{
473 struct smsc9420_pdata *pd = netdev_priv(dev);
474 u8 *dev_addr = dev->dev_addr;
475 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
476 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
477 (dev_addr[1] << 8) | dev_addr[0];
478
479 smsc9420_reg_write(pd, ADDRH, mac_high16);
480 smsc9420_reg_write(pd, ADDRL, mac_low32);
481}
482
483static void smsc9420_check_mac_address(struct net_device *dev)
484{
485 struct smsc9420_pdata *pd = netdev_priv(dev);
486
487 /* Check if mac address has been specified when bringing interface up */
488 if (is_valid_ether_addr(dev->dev_addr)) {
489 smsc9420_set_mac_address(dev);
490 smsc_dbg(PROBE, "MAC Address is specified by configuration");
491 } else {
492 /* Try reading mac address from device. if EEPROM is present
493 * it will already have been set */
494 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
495 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
496 dev->dev_addr[0] = (u8)(mac_low32);
497 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
498 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
499 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
500 dev->dev_addr[4] = (u8)(mac_high16);
501 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
502
503 if (is_valid_ether_addr(dev->dev_addr)) {
504 /* eeprom values are valid so use them */
505 smsc_dbg(PROBE, "Mac Address is read from EEPROM");
506 } else {
507 /* eeprom values are invalid, generate random MAC */
508 random_ether_addr(dev->dev_addr);
509 smsc9420_set_mac_address(dev);
510 smsc_dbg(PROBE,
511 "MAC Address is set to random_ether_addr");
512 }
513 }
514}
515
516static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
517{
518 u32 dmac_control, mac_cr, dma_intr_ena;
46578a69 519 int timeout = 1000;
2cb37728
SG		 520
521 /* disable TX DMAC */
522 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
523 dmac_control &= (~DMAC_CONTROL_ST_);
524 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
525
526 /* Wait max 10ms for transmit process to stop */
46578a69 527 while (--timeout) {
2cb37728
SG		 528 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
529 break;
530 udelay(10);
531 }
532
46578a69 533 if (!timeout)
2cb37728
SG		 534 smsc_warn(IFDOWN, "TX DMAC failed to stop");
535
536 /* ACK Tx DMAC stop bit */
537 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
538
539 /* mask TX DMAC interrupts */
540 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
541 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
542 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
543 smsc9420_pci_flush_write(pd);
544
545 /* stop MAC TX */
546 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
547 smsc9420_reg_write(pd, MAC_CR, mac_cr);
548 smsc9420_pci_flush_write(pd);
549}
550
551static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
552{
553 int i;
554
555 BUG_ON(!pd->tx_ring);
556
557 if (!pd->tx_buffers)
558 return;
559
560 for (i = 0; i < TX_RING_SIZE; i++) {
561 struct sk_buff *skb = pd->tx_buffers[i].skb;
562
563 if (skb) {
564 BUG_ON(!pd->tx_buffers[i].mapping);
565 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping,
566 skb->len, PCI_DMA_TODEVICE);
567 dev_kfree_skb_any(skb);
568 }
569
570 pd->tx_ring[i].status = 0;
571 pd->tx_ring[i].length = 0;
572 pd->tx_ring[i].buffer1 = 0;
573 pd->tx_ring[i].buffer2 = 0;
574 }
575 wmb();
576
577 kfree(pd->tx_buffers);
578 pd->tx_buffers = NULL;
579
580 pd->tx_ring_head = 0;
581 pd->tx_ring_tail = 0;
582}
583
584static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
585{
586 int i;
587
588 BUG_ON(!pd->rx_ring);
589
590 if (!pd->rx_buffers)
591 return;
592
593 for (i = 0; i < RX_RING_SIZE; i++) {
594 if (pd->rx_buffers[i].skb)
595 dev_kfree_skb_any(pd->rx_buffers[i].skb);
596
597 if (pd->rx_buffers[i].mapping)
598 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping,
599 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
600
601 pd->rx_ring[i].status = 0;
602 pd->rx_ring[i].length = 0;
603 pd->rx_ring[i].buffer1 = 0;
604 pd->rx_ring[i].buffer2 = 0;
605 }
606 wmb();
607
608 kfree(pd->rx_buffers);
609 pd->rx_buffers = NULL;
610
611 pd->rx_ring_head = 0;
612 pd->rx_ring_tail = 0;
613}
614
615static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
616{
46578a69 617 int timeout = 1000;
2cb37728
SG		 618 u32 mac_cr, dmac_control, dma_intr_ena;
619
620 /* mask RX DMAC interrupts */
621 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
622 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
623 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
624 smsc9420_pci_flush_write(pd);
625
626 /* stop RX MAC prior to stoping DMA */
627 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
628 smsc9420_reg_write(pd, MAC_CR, mac_cr);
629 smsc9420_pci_flush_write(pd);
630
631 /* stop RX DMAC */
632 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
633 dmac_control &= (~DMAC_CONTROL_SR_);
634 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
635 smsc9420_pci_flush_write(pd);
636
637 /* wait up to 10ms for receive to stop */
46578a69 638 while (--timeout) {
2cb37728
SG		 639 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
640 break;
641 udelay(10);
642 }
643
46578a69 644 if (!timeout)
2cb37728
SG		 645 smsc_warn(IFDOWN, "RX DMAC did not stop! timeout.");
646
647 /* ACK the Rx DMAC stop bit */
648 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
649}
650
651static irqreturn_t smsc9420_isr(int irq, void *dev_id)
652{
653 struct smsc9420_pdata *pd = dev_id;
654 u32 int_cfg, int_sts, int_ctl;
655 irqreturn_t ret = IRQ_NONE;
656 ulong flags;
657
658 BUG_ON(!pd);
659 BUG_ON(!pd->base_addr);
660
661 int_cfg = smsc9420_reg_read(pd, INT_CFG);
662
663 /* check if it's our interrupt */
664 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
665 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
666 return IRQ_NONE;
667
668 int_sts = smsc9420_reg_read(pd, INT_STAT);
669
670 if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
671 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
672 u32 ints_to_clear = 0;
673
674 if (status & DMAC_STS_TX_) {
675 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
676 netif_wake_queue(pd->dev);
677 }
678
679 if (status & DMAC_STS_RX_) {
680 /* mask RX DMAC interrupts */
681 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
682 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
683 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
684 smsc9420_pci_flush_write(pd);
685
686 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
288379f0 687 napi_schedule(&pd->napi);
2cb37728
SG		 688 }
689
690 if (ints_to_clear)
691 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
692
693 ret = IRQ_HANDLED;
694 }
695
696 if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
697 /* mask software interrupt */
698 spin_lock_irqsave(&pd->int_lock, flags);
699 int_ctl = smsc9420_reg_read(pd, INT_CTL);
700 int_ctl &= (~INT_CTL_SW_INT_EN_);
701 smsc9420_reg_write(pd, INT_CTL, int_ctl);
702 spin_unlock_irqrestore(&pd->int_lock, flags);
703
704 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
705 pd->software_irq_signal = true;
706 smp_wmb();
707
708 ret = IRQ_HANDLED;
709 }
710
711 /* to ensure PCI write completion, we must perform a PCI read */
712 smsc9420_pci_flush_write(pd);
713
714 return ret;
715}
716
e312674f
SG		 717#ifdef CONFIG_NET_POLL_CONTROLLER
718static void smsc9420_poll_controller(struct net_device *dev)
719{
720 disable_irq(dev->irq);
721 smsc9420_isr(0, dev);
722 enable_irq(dev->irq);
723}
724#endif /* CONFIG_NET_POLL_CONTROLLER */
725
2cb37728
SG		 726static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
727{
728 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
729 smsc9420_reg_read(pd, BUS_MODE);
730 udelay(2);
731 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
732 smsc_warn(DRV, "Software reset not cleared");
733}
734
735static int smsc9420_stop(struct net_device *dev)
736{
737 struct smsc9420_pdata *pd = netdev_priv(dev);
738 u32 int_cfg;
739 ulong flags;
740
741 BUG_ON(!pd);
742 BUG_ON(!pd->phy_dev);
743
744 /* disable master interrupt */
745 spin_lock_irqsave(&pd->int_lock, flags);
746 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
747 smsc9420_reg_write(pd, INT_CFG, int_cfg);
748 spin_unlock_irqrestore(&pd->int_lock, flags);
749
750 netif_tx_disable(dev);
751 napi_disable(&pd->napi);
752
753 smsc9420_stop_tx(pd);
754 smsc9420_free_tx_ring(pd);
755
756 smsc9420_stop_rx(pd);
757 smsc9420_free_rx_ring(pd);
758
759 free_irq(dev->irq, pd);
760
761 smsc9420_dmac_soft_reset(pd);
762
763 phy_stop(pd->phy_dev);
764
765 phy_disconnect(pd->phy_dev);
766 pd->phy_dev = NULL;
767 mdiobus_unregister(pd->mii_bus);
768 mdiobus_free(pd->mii_bus);
769
770 return 0;
771}
772
773static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
774{
775 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
776 dev->stats.rx_errors++;
777 if (desc_status & RDES0_DESCRIPTOR_ERROR_)
778 dev->stats.rx_over_errors++;
779 else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
780 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
781 dev->stats.rx_frame_errors++;
782 else if (desc_status & RDES0_CRC_ERROR_)
783 dev->stats.rx_crc_errors++;
784 }
785
786 if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
787 dev->stats.rx_length_errors++;
788
789 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
790 (desc_status & RDES0_FIRST_DESCRIPTOR_))))
791 dev->stats.rx_length_errors++;
792
793 if (desc_status & RDES0_MULTICAST_FRAME_)
794 dev->stats.multicast++;
795}
796
797static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
798 const u32 status)
799{
800 struct net_device *dev = pd->dev;
801 struct sk_buff *skb;
802 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
803 >> RDES0_FRAME_LENGTH_SHFT_;
804
805 /* remove crc from packet lendth */
806 packet_length -= 4;
807
808 if (pd->rx_csum)
809 packet_length -= 2;
810
811 dev->stats.rx_packets++;
812 dev->stats.rx_bytes += packet_length;
813
814 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping,
815 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
816 pd->rx_buffers[index].mapping = 0;
817
818 skb = pd->rx_buffers[index].skb;
819 pd->rx_buffers[index].skb = NULL;
820
821 if (pd->rx_csum) {
822 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
823 NET_IP_ALIGN + packet_length + 4);
cd7a3b75 824 put_unaligned_le16(hw_csum, &skb->csum);
2cb37728
SG		 825 skb->ip_summed = CHECKSUM_COMPLETE;
826 }
827
828 skb_reserve(skb, NET_IP_ALIGN);
829 skb_put(skb, packet_length);
830
831 skb->protocol = eth_type_trans(skb, dev);
832
833 netif_receive_skb(skb);
2cb37728
SG		 834}
835
836static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
837{
838 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
839 dma_addr_t mapping;
840
841 BUG_ON(pd->rx_buffers[index].skb);
842 BUG_ON(pd->rx_buffers[index].mapping);
843
844 if (unlikely(!skb)) {
845 smsc_warn(RX_ERR, "Failed to allocate new skb!");
846 return -ENOMEM;
847 }
848
849 skb->dev = pd->dev;
850
851 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb),
852 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
853 if (pci_dma_mapping_error(pd->pdev, mapping)) {
854 dev_kfree_skb_any(skb);
855 smsc_warn(RX_ERR, "pci_map_single failed!");
856 return -ENOMEM;
857 }
858
859 pd->rx_buffers[index].skb = skb;
860 pd->rx_buffers[index].mapping = mapping;
861 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
862 pd->rx_ring[index].status = RDES0_OWN_;
863 wmb();
864
865 return 0;
866}
867
868static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
869{
870 while (pd->rx_ring_tail != pd->rx_ring_head) {
871 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
872 break;
873
874 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
875 }
876}
877
878static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
879{
880 struct smsc9420_pdata *pd =
881 container_of(napi, struct smsc9420_pdata, napi);
882 struct net_device *dev = pd->dev;
883 u32 drop_frame_cnt, dma_intr_ena, status;
884 int work_done;
885
886 for (work_done = 0; work_done < budget; work_done++) {
887 rmb();
888 status = pd->rx_ring[pd->rx_ring_head].status;
889
890 /* stop if DMAC owns this dma descriptor */
891 if (status & RDES0_OWN_)
892 break;
893
894 smsc9420_rx_count_stats(dev, status);
895 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
896 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
897 smsc9420_alloc_new_rx_buffers(pd);
898 }
899
900 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
901 dev->stats.rx_dropped +=
902 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
903
904 /* Kick RXDMA */
905 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
906 smsc9420_pci_flush_write(pd);
907
908 if (work_done < budget) {
288379f0 909 napi_complete(&pd->napi);
2cb37728
SG		 910
911 /* re-enable RX DMA interrupts */
912 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
913 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
914 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
915 smsc9420_pci_flush_write(pd);
916 }
917 return work_done;
918}
919
920static void
921smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
922{
923 if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
924 dev->stats.tx_errors++;
925 if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
926 TDES0_EXCESSIVE_COLLISIONS_))
927 dev->stats.tx_aborted_errors++;
928
929 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
930 dev->stats.tx_carrier_errors++;
931 } else {
932 dev->stats.tx_packets++;
933 dev->stats.tx_bytes += (length & 0x7FF);
934 }
935
936 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
937 dev->stats.collisions += 16;
938 } else {
939 dev->stats.collisions +=
940 (status & TDES0_COLLISION_COUNT_MASK_) >>
941 TDES0_COLLISION_COUNT_SHFT_;
942 }
943
944 if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
945 dev->stats.tx_heartbeat_errors++;
946}
947
948/* Check for completed dma transfers, update stats and free skbs */
949static void smsc9420_complete_tx(struct net_device *dev)
950{
951 struct smsc9420_pdata *pd = netdev_priv(dev);
952
953 while (pd->tx_ring_tail != pd->tx_ring_head) {
954 int index = pd->tx_ring_tail;
955 u32 status, length;
956
957 rmb();
958 status = pd->tx_ring[index].status;
959 length = pd->tx_ring[index].length;
960
961 /* Check if DMA still owns this descriptor */
962 if (unlikely(TDES0_OWN_ & status))
963 break;
964
965 smsc9420_tx_update_stats(dev, status, length);
966
967 BUG_ON(!pd->tx_buffers[index].skb);
968 BUG_ON(!pd->tx_buffers[index].mapping);
969
970 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping,
971 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE);
972 pd->tx_buffers[index].mapping = 0;
973
974 dev_kfree_skb_any(pd->tx_buffers[index].skb);
975 pd->tx_buffers[index].skb = NULL;
976
977 pd->tx_ring[index].buffer1 = 0;
978 wmb();
979
980 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
981 }
982}
983
61357325
SH		 984static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb,
985 struct net_device *dev)
2cb37728
SG		 986{
987 struct smsc9420_pdata *pd = netdev_priv(dev);
988 dma_addr_t mapping;
989 int index = pd->tx_ring_head;
990 u32 tmp_desc1;
991 bool about_to_take_last_desc =
992 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
993
994 smsc9420_complete_tx(dev);
995
996 rmb();
997 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
998 BUG_ON(pd->tx_buffers[index].skb);
999 BUG_ON(pd->tx_buffers[index].mapping);
1000
1001 mapping = pci_map_single(pd->pdev, skb->data,
1002 skb->len, PCI_DMA_TODEVICE);
1003 if (pci_dma_mapping_error(pd->pdev, mapping)) {
1004 smsc_warn(TX_ERR, "pci_map_single failed, dropping packet");
1005 return NETDEV_TX_BUSY;
1006 }
1007
1008 pd->tx_buffers[index].skb = skb;
1009 pd->tx_buffers[index].mapping = mapping;
1010
1011 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
1012 if (unlikely(about_to_take_last_desc)) {
1013 tmp_desc1 |= TDES1_IC_;
1014 netif_stop_queue(pd->dev);
1015 }
1016
1017 /* check if we are at the last descriptor and need to set EOR */
1018 if (unlikely(index == (TX_RING_SIZE - 1)))
1019 tmp_desc1 |= TDES1_TER_;
1020
1021 pd->tx_ring[index].buffer1 = mapping;
1022 pd->tx_ring[index].length = tmp_desc1;
1023 wmb();
1024
1025 /* increment head */
1026 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
1027
1028 /* assign ownership to DMAC */
1029 pd->tx_ring[index].status = TDES0_OWN_;
1030 wmb();
1031
1032 /* kick the DMA */
1033 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
1034 smsc9420_pci_flush_write(pd);
1035
1036 dev->trans_start = jiffies;
1037
1038 return NETDEV_TX_OK;
1039}
1040
1041static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
1042{
1043 struct smsc9420_pdata *pd = netdev_priv(dev);
1044 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
1045 dev->stats.rx_dropped +=
1046 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
1047 return &dev->stats;
1048}
1049
1050static void smsc9420_set_multicast_list(struct net_device *dev)
1051{
1052 struct smsc9420_pdata *pd = netdev_priv(dev);
1053 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1054
1055 if (dev->flags & IFF_PROMISC) {
1056 smsc_dbg(HW, "Promiscuous Mode Enabled");
1057 mac_cr |= MAC_CR_PRMS_;
1058 mac_cr &= (~MAC_CR_MCPAS_);
1059 mac_cr &= (~MAC_CR_HPFILT_);
1060 } else if (dev->flags & IFF_ALLMULTI) {
1061 smsc_dbg(HW, "Receive all Multicast Enabled");
1062 mac_cr &= (~MAC_CR_PRMS_);
1063 mac_cr |= MAC_CR_MCPAS_;
1064 mac_cr &= (~MAC_CR_HPFILT_);
4cd24eaf 1065 } else if (!netdev_mc_empty(dev)) {
2cb37728
SG		 1066 struct dev_mc_list *mc_list = dev->mc_list;
1067 u32 hash_lo = 0, hash_hi = 0;
1068
1069 smsc_dbg(HW, "Multicast filter enabled");
1070 while (mc_list) {
1071 u32 bit_num = smsc9420_hash(mc_list->dmi_addr);
1072 u32 mask = 1 << (bit_num & 0x1F);
1073
1074 if (bit_num & 0x20)
1075 hash_hi |= mask;
1076 else
1077 hash_lo |= mask;
1078
1079 mc_list = mc_list->next;
1080 }
1081 smsc9420_reg_write(pd, HASHH, hash_hi);
1082 smsc9420_reg_write(pd, HASHL, hash_lo);
1083
1084 mac_cr &= (~MAC_CR_PRMS_);
1085 mac_cr &= (~MAC_CR_MCPAS_);
1086 mac_cr |= MAC_CR_HPFILT_;
1087 } else {
1088 smsc_dbg(HW, "Receive own packets only.");
1089 smsc9420_reg_write(pd, HASHH, 0);
1090 smsc9420_reg_write(pd, HASHL, 0);
1091
1092 mac_cr &= (~MAC_CR_PRMS_);
1093 mac_cr &= (~MAC_CR_MCPAS_);
1094 mac_cr &= (~MAC_CR_HPFILT_);
1095 }
1096
1097 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1098 smsc9420_pci_flush_write(pd);
1099}
1100
2cb37728
SG		 1101static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1102{
1103 struct phy_device *phy_dev = pd->phy_dev;
1104 u32 flow;
1105
1106 if (phy_dev->duplex == DUPLEX_FULL) {
1107 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
1108 u16 rmtadv = phy_read(phy_dev, MII_LPA);
bc02ff95 1109 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
2cb37728
SG		 1110
1111 if (cap & FLOW_CTRL_RX)
1112 flow = 0xFFFF0002;
1113 else
1114 flow = 0;
1115
1116 smsc_info(LINK, "rx pause %s, tx pause %s",
1117 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
1118 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
1119 } else {
1120 smsc_info(LINK, "half duplex");
1121 flow = 0;
1122 }
1123
1124 smsc9420_reg_write(pd, FLOW, flow);
1125}
1126
1127/* Update link mode if anything has changed. Called periodically when the
1128 * PHY is in polling mode, even if nothing has changed. */
1129static void smsc9420_phy_adjust_link(struct net_device *dev)
1130{
1131 struct smsc9420_pdata *pd = netdev_priv(dev);
1132 struct phy_device *phy_dev = pd->phy_dev;
1133 int carrier;
1134
1135 if (phy_dev->duplex != pd->last_duplex) {
1136 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1137 if (phy_dev->duplex) {
1138 smsc_dbg(LINK, "full duplex mode");
1139 mac_cr |= MAC_CR_FDPX_;
1140 } else {
1141 smsc_dbg(LINK, "half duplex mode");
1142 mac_cr &= ~MAC_CR_FDPX_;
1143 }
1144 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1145
1146 smsc9420_phy_update_flowcontrol(pd);
1147 pd->last_duplex = phy_dev->duplex;
1148 }
1149
1150 carrier = netif_carrier_ok(dev);
1151 if (carrier != pd->last_carrier) {
1152 if (carrier)
1153 smsc_dbg(LINK, "carrier OK");
1154 else
1155 smsc_dbg(LINK, "no carrier");
1156 pd->last_carrier = carrier;
1157 }
1158}
1159
1160static int smsc9420_mii_probe(struct net_device *dev)
1161{
1162 struct smsc9420_pdata *pd = netdev_priv(dev);
1163 struct phy_device *phydev = NULL;
1164
1165 BUG_ON(pd->phy_dev);
1166
1167 /* Device only supports internal PHY at address 1 */
1168 if (!pd->mii_bus->phy_map[1]) {
1169 pr_err("%s: no PHY found at address 1\n", dev->name);
1170 return -ENODEV;
1171 }
1172
1173 phydev = pd->mii_bus->phy_map[1];
1174 smsc_info(PROBE, "PHY addr %d, phy_id 0x%08X", phydev->addr,
1175 phydev->phy_id);
1176
db1d7bf7 1177 phydev = phy_connect(dev, dev_name(&phydev->dev),
a974a679 1178 smsc9420_phy_adjust_link, 0, PHY_INTERFACE_MODE_MII);
2cb37728
SG		 1179
1180 if (IS_ERR(phydev)) {
1181 pr_err("%s: Could not attach to PHY\n", dev->name);
1182 return PTR_ERR(phydev);
1183 }
1184
1185 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
db1d7bf7 1186 dev->name, phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
2cb37728
SG		 1187
1188 /* mask with MAC supported features */
1189 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
1190 SUPPORTED_Asym_Pause);
1191 phydev->advertising = phydev->supported;
1192
1193 pd->phy_dev = phydev;
1194 pd->last_duplex = -1;
1195 pd->last_carrier = -1;
1196
1197 return 0;
1198}
1199
1200static int smsc9420_mii_init(struct net_device *dev)
1201{
1202 struct smsc9420_pdata *pd = netdev_priv(dev);
1203 int err = -ENXIO, i;
1204
1205 pd->mii_bus = mdiobus_alloc();
1206 if (!pd->mii_bus) {
1207 err = -ENOMEM;
1208 goto err_out_1;
1209 }
1210 pd->mii_bus->name = DRV_MDIONAME;
1211 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1212 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1213 pd->mii_bus->priv = pd;
1214 pd->mii_bus->read = smsc9420_mii_read;
1215 pd->mii_bus->write = smsc9420_mii_write;
1216 pd->mii_bus->irq = pd->phy_irq;
1217 for (i = 0; i < PHY_MAX_ADDR; ++i)
1218 pd->mii_bus->irq[i] = PHY_POLL;
1219
1220 /* Mask all PHYs except ID 1 (internal) */
1221 pd->mii_bus->phy_mask = ~(1 << 1);
1222
1223 if (mdiobus_register(pd->mii_bus)) {
1224 smsc_warn(PROBE, "Error registering mii bus");
1225 goto err_out_free_bus_2;
1226 }
1227
1228 if (smsc9420_mii_probe(dev) < 0) {
1229 smsc_warn(PROBE, "Error probing mii bus");
1230 goto err_out_unregister_bus_3;
1231 }
1232
1233 return 0;
1234
1235err_out_unregister_bus_3:
1236 mdiobus_unregister(pd->mii_bus);
1237err_out_free_bus_2:
1238 mdiobus_free(pd->mii_bus);
1239err_out_1:
1240 return err;
1241}
1242
1243static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1244{
1245 int i;
1246
1247 BUG_ON(!pd->tx_ring);
1248
1249 pd->tx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1250 TX_RING_SIZE), GFP_KERNEL);
1251 if (!pd->tx_buffers) {
1252 smsc_warn(IFUP, "Failed to allocated tx_buffers");
1253 return -ENOMEM;
1254 }
1255
1256 /* Initialize the TX Ring */
1257 for (i = 0; i < TX_RING_SIZE; i++) {
1258 pd->tx_buffers[i].skb = NULL;
1259 pd->tx_buffers[i].mapping = 0;
1260 pd->tx_ring[i].status = 0;
1261 pd->tx_ring[i].length = 0;
1262 pd->tx_ring[i].buffer1 = 0;
1263 pd->tx_ring[i].buffer2 = 0;
1264 }
1265 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1266 wmb();
1267
1268 pd->tx_ring_head = 0;
1269 pd->tx_ring_tail = 0;
1270
1271 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1272 smsc9420_pci_flush_write(pd);
1273
1274 return 0;
1275}
1276
1277static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1278{
1279 int i;
1280
1281 BUG_ON(!pd->rx_ring);
1282
1283 pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1284 RX_RING_SIZE), GFP_KERNEL);
1285 if (pd->rx_buffers == NULL) {
1286 smsc_warn(IFUP, "Failed to allocated rx_buffers");
1287 goto out;
1288 }
1289
1290 /* initialize the rx ring */
1291 for (i = 0; i < RX_RING_SIZE; i++) {
1292 pd->rx_ring[i].status = 0;
1293 pd->rx_ring[i].length = PKT_BUF_SZ;
1294 pd->rx_ring[i].buffer2 = 0;
1295 pd->rx_buffers[i].skb = NULL;
1296 pd->rx_buffers[i].mapping = 0;
1297 }
1298 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1299
1300 /* now allocate the entire ring of skbs */
1301 for (i = 0; i < RX_RING_SIZE; i++) {
1302 if (smsc9420_alloc_rx_buffer(pd, i)) {
1303 smsc_warn(IFUP, "failed to allocate rx skb %d", i);
1304 goto out_free_rx_skbs;
1305 }
1306 }
1307
1308 pd->rx_ring_head = 0;
1309 pd->rx_ring_tail = 0;
1310
1311 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1312 smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1));
1313
1314 if (pd->rx_csum) {
1315 /* Enable RX COE */
1316 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1317 smsc9420_reg_write(pd, COE_CR, coe);
1318 smsc_dbg(IFUP, "COE_CR = 0x%08x", coe);
1319 }
1320
1321 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1322 smsc9420_pci_flush_write(pd);
1323
1324 return 0;
1325
1326out_free_rx_skbs:
1327 smsc9420_free_rx_ring(pd);
1328out:
1329 return -ENOMEM;
1330}
1331
1332static int smsc9420_open(struct net_device *dev)
1333{
1334 struct smsc9420_pdata *pd;
1335 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
1336 unsigned long flags;
1337 int result = 0, timeout;
1338
1339 BUG_ON(!dev);
1340 pd = netdev_priv(dev);
1341 BUG_ON(!pd);
1342
1343 if (!is_valid_ether_addr(dev->dev_addr)) {
1344 smsc_warn(IFUP, "dev_addr is not a valid MAC address");
1345 result = -EADDRNOTAVAIL;
1346 goto out_0;
1347 }
1348
1349 netif_carrier_off(dev);
1350
1351 /* disable, mask and acknowlege all interrupts */
1352 spin_lock_irqsave(&pd->int_lock, flags);
1353 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1354 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1355 smsc9420_reg_write(pd, INT_CTL, 0);
1356 spin_unlock_irqrestore(&pd->int_lock, flags);
1357 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1358 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1359 smsc9420_pci_flush_write(pd);
1360
1361 if (request_irq(dev->irq, smsc9420_isr, IRQF_SHARED | IRQF_DISABLED,
1362 DRV_NAME, pd)) {
1363 smsc_warn(IFUP, "Unable to use IRQ = %d", dev->irq);
1364 result = -ENODEV;
1365 goto out_0;
1366 }
1367
1368 smsc9420_dmac_soft_reset(pd);
1369
1370 /* make sure MAC_CR is sane */
1371 smsc9420_reg_write(pd, MAC_CR, 0);
1372
1373 smsc9420_set_mac_address(dev);
1374
1375 /* Configure GPIO pins to drive LEDs */
1376 smsc9420_reg_write(pd, GPIO_CFG,
1377 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1378
1379 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1380
1381#ifdef __BIG_ENDIAN
1382 bus_mode |= BUS_MODE_DBO_;
1383#endif
1384
1385 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1386
1387 smsc9420_pci_flush_write(pd);
1388
1389 /* set bus master bridge arbitration priority for Rx and TX DMA */
1390 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1391
1392 smsc9420_reg_write(pd, DMAC_CONTROL,
1393 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1394
1395 smsc9420_pci_flush_write(pd);
1396
1397 /* test the IRQ connection to the ISR */
1398 smsc_dbg(IFUP, "Testing ISR using IRQ %d", dev->irq);
16095595 1399 pd->software_irq_signal = false;
2cb37728
SG		 1400
1401 spin_lock_irqsave(&pd->int_lock, flags);
1402 /* configure interrupt deassertion timer and enable interrupts */
1403 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1404 int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1405 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1406 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1407
1408 /* unmask software interrupt */
1409 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1410 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1411 spin_unlock_irqrestore(&pd->int_lock, flags);
1412 smsc9420_pci_flush_write(pd);
1413
1414 timeout = 1000;
2cb37728
SG		 1415 while (timeout--) {
1416 if (pd->software_irq_signal)
1417 break;
1418 msleep(1);
1419 }
1420
1421 /* disable interrupts */
1422 spin_lock_irqsave(&pd->int_lock, flags);
1423 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1424 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1425 spin_unlock_irqrestore(&pd->int_lock, flags);
1426
1427 if (!pd->software_irq_signal) {
1428 smsc_warn(IFUP, "ISR failed signaling test");
1429 result = -ENODEV;
1430 goto out_free_irq_1;
1431 }
1432
1433 smsc_dbg(IFUP, "ISR passed test using IRQ %d", dev->irq);
1434
1435 result = smsc9420_alloc_tx_ring(pd);
1436 if (result) {
1437 smsc_warn(IFUP, "Failed to Initialize tx dma ring");
1438 result = -ENOMEM;
1439 goto out_free_irq_1;
1440 }
1441
1442 result = smsc9420_alloc_rx_ring(pd);
1443 if (result) {
1444 smsc_warn(IFUP, "Failed to Initialize rx dma ring");
1445 result = -ENOMEM;
1446 goto out_free_tx_ring_2;
1447 }
1448
1449 result = smsc9420_mii_init(dev);
1450 if (result) {
1451 smsc_warn(IFUP, "Failed to initialize Phy");
1452 result = -ENODEV;
1453 goto out_free_rx_ring_3;
1454 }
1455
1456 /* Bring the PHY up */
1457 phy_start(pd->phy_dev);
1458
1459 napi_enable(&pd->napi);
1460
1461 /* start tx and rx */
1462 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1463 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1464
1465 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1466 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1467 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1468 smsc9420_pci_flush_write(pd);
1469
1470 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1471 dma_intr_ena |=
1472 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1473 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1474 smsc9420_pci_flush_write(pd);
1475
1476 netif_wake_queue(dev);
1477
1478 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1479
1480 /* enable interrupts */
1481 spin_lock_irqsave(&pd->int_lock, flags);
1482 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1483 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1484 spin_unlock_irqrestore(&pd->int_lock, flags);
1485
1486 return 0;
1487
1488out_free_rx_ring_3:
1489 smsc9420_free_rx_ring(pd);
1490out_free_tx_ring_2:
1491 smsc9420_free_tx_ring(pd);
1492out_free_irq_1:
1493 free_irq(dev->irq, pd);
1494out_0:
1495 return result;
1496}
1497
1498#ifdef CONFIG_PM
1499
1500static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state)
1501{
1502 struct net_device *dev = pci_get_drvdata(pdev);
1503 struct smsc9420_pdata *pd = netdev_priv(dev);
1504 u32 int_cfg;
1505 ulong flags;
1506
1507 /* disable interrupts */
1508 spin_lock_irqsave(&pd->int_lock, flags);
1509 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1510 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1511 spin_unlock_irqrestore(&pd->int_lock, flags);
1512
1513 if (netif_running(dev)) {
1514 netif_tx_disable(dev);
1515 smsc9420_stop_tx(pd);
1516 smsc9420_free_tx_ring(pd);
1517
1518 napi_disable(&pd->napi);
1519 smsc9420_stop_rx(pd);
1520 smsc9420_free_rx_ring(pd);
1521
1522 free_irq(dev->irq, pd);
1523
1524 netif_device_detach(dev);
1525 }
1526
1527 pci_save_state(pdev);
1528 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1529 pci_disable_device(pdev);
1530 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1531
1532 return 0;
1533}
1534
1535static int smsc9420_resume(struct pci_dev *pdev)
1536{
1537 struct net_device *dev = pci_get_drvdata(pdev);
1538 struct smsc9420_pdata *pd = netdev_priv(dev);
1539 int err;
1540
1541 pci_set_power_state(pdev, PCI_D0);
1542 pci_restore_state(pdev);
1543
1544 err = pci_enable_device(pdev);
1545 if (err)
1546 return err;
1547
1548 pci_set_master(pdev);
1549
1550 err = pci_enable_wake(pdev, 0, 0);
1551 if (err)
1552 smsc_warn(IFUP, "pci_enable_wake failed: %d", err);
1553
1554 if (netif_running(dev)) {
1555 err = smsc9420_open(dev);
1556 netif_device_attach(dev);
1557 }
1558 return err;
1559}
1560
1561#endif /* CONFIG_PM */
1562
1563static const struct net_device_ops smsc9420_netdev_ops = {
1564 .ndo_open = smsc9420_open,
1565 .ndo_stop = smsc9420_stop,
1566 .ndo_start_xmit = smsc9420_hard_start_xmit,
1567 .ndo_get_stats = smsc9420_get_stats,
1568 .ndo_set_multicast_list = smsc9420_set_multicast_list,
1569 .ndo_do_ioctl = smsc9420_do_ioctl,
1570 .ndo_validate_addr = eth_validate_addr,
fe96aaa1 1571 .ndo_set_mac_address = eth_mac_addr,
e312674f
SG		 1572#ifdef CONFIG_NET_POLL_CONTROLLER
1573 .ndo_poll_controller = smsc9420_poll_controller,
1574#endif /* CONFIG_NET_POLL_CONTROLLER */
2cb37728
SG		 1575};
1576
1577static int __devinit
1578smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1579{
1580 struct net_device *dev;
1581 struct smsc9420_pdata *pd;
1582 void __iomem *virt_addr;
1583 int result = 0;
1584 u32 id_rev;
1585
1586 printk(KERN_INFO DRV_DESCRIPTION " version " DRV_VERSION "\n");
1587
1588 /* First do the PCI initialisation */
1589 result = pci_enable_device(pdev);
1590 if (unlikely(result)) {
1591 printk(KERN_ERR "Cannot enable smsc9420\n");
1592 goto out_0;
1593 }
1594
1595 pci_set_master(pdev);
1596
1597 dev = alloc_etherdev(sizeof(*pd));
1598 if (!dev) {
1599 printk(KERN_ERR "ether device alloc failed\n");
1600 goto out_disable_pci_device_1;
1601 }
1602
1603 SET_NETDEV_DEV(dev, &pdev->dev);
1604
1605 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
1606 printk(KERN_ERR "Cannot find PCI device base address\n");
1607 goto out_free_netdev_2;
1608 }
1609
1610 if ((pci_request_regions(pdev, DRV_NAME))) {
1611 printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n");
1612 goto out_free_netdev_2;
1613 }
1614
284901a9 1615 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2cb37728
SG		 1616 printk(KERN_ERR "No usable DMA configuration, aborting.\n");
1617 goto out_free_regions_3;
1618 }
1619
1620 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1621 pci_resource_len(pdev, SMSC_BAR));
1622 if (!virt_addr) {
1623 printk(KERN_ERR "Cannot map device registers, aborting.\n");
1624 goto out_free_regions_3;
1625 }
1626
1627 /* registers are double mapped with 0 offset for LE and 0x200 for BE */
1628 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1629
1630 dev->base_addr = (ulong)virt_addr;
1631
1632 pd = netdev_priv(dev);
1633
1634 /* pci descriptors are created in the PCI consistent area */
1635 pd->rx_ring = pci_alloc_consistent(pdev,
1636 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE +
1637 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE,
1638 &pd->rx_dma_addr);
1639
1640 if (!pd->rx_ring)
1641 goto out_free_io_4;
1642
1643 /* descriptors are aligned due to the nature of pci_alloc_consistent */
1644 pd->tx_ring = (struct smsc9420_dma_desc *)
1645 (pd->rx_ring + RX_RING_SIZE);
1646 pd->tx_dma_addr = pd->rx_dma_addr +
1647 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1648
1649 pd->pdev = pdev;
1650 pd->dev = dev;
1651 pd->base_addr = virt_addr;
1652 pd->msg_enable = smsc_debug;
1653 pd->rx_csum = true;
1654
1655 smsc_dbg(PROBE, "lan_base=0x%08lx", (ulong)virt_addr);
1656
1657 id_rev = smsc9420_reg_read(pd, ID_REV);
1658 switch (id_rev & 0xFFFF0000) {
1659 case 0x94200000:
1660 smsc_info(PROBE, "LAN9420 identified, ID_REV=0x%08X", id_rev);
1661 break;
1662 default:
1663 smsc_warn(PROBE, "LAN9420 NOT identified");
1664 smsc_warn(PROBE, "ID_REV=0x%08X", id_rev);
1665 goto out_free_dmadesc_5;
1666 }
1667
1668 smsc9420_dmac_soft_reset(pd);
1669 smsc9420_eeprom_reload(pd);
1670 smsc9420_check_mac_address(dev);
1671
1672 dev->netdev_ops = &smsc9420_netdev_ops;
1673 dev->ethtool_ops = &smsc9420_ethtool_ops;
1674 dev->irq = pdev->irq;
1675
1676 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1677
1678 result = register_netdev(dev);
1679 if (result) {
1680 smsc_warn(PROBE, "error %i registering device", result);
1681 goto out_free_dmadesc_5;
1682 }
1683
1684 pci_set_drvdata(pdev, dev);
1685
1686 spin_lock_init(&pd->int_lock);
1687 spin_lock_init(&pd->phy_lock);
1688
1689 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1690
1691 return 0;
1692
1693out_free_dmadesc_5:
1694 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1695 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1696out_free_io_4:
1697 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1698out_free_regions_3:
1699 pci_release_regions(pdev);
1700out_free_netdev_2:
1701 free_netdev(dev);
1702out_disable_pci_device_1:
1703 pci_disable_device(pdev);
1704out_0:
1705 return -ENODEV;
1706}
1707
1708static void __devexit smsc9420_remove(struct pci_dev *pdev)
1709{
1710 struct net_device *dev;
1711 struct smsc9420_pdata *pd;
1712
1713 dev = pci_get_drvdata(pdev);
1714 if (!dev)
1715 return;
1716
1717 pci_set_drvdata(pdev, NULL);
1718
1719 pd = netdev_priv(dev);
1720 unregister_netdev(dev);
1721
1722 /* tx_buffers and rx_buffers are freed in stop */
1723 BUG_ON(pd->tx_buffers);
1724 BUG_ON(pd->rx_buffers);
1725
1726 BUG_ON(!pd->tx_ring);
1727 BUG_ON(!pd->rx_ring);
1728
1729 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1730 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1731
1732 iounmap(pd->base_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1733 pci_release_regions(pdev);
1734 free_netdev(dev);
1735 pci_disable_device(pdev);
1736}
1737
1738static struct pci_driver smsc9420_driver = {
1739 .name = DRV_NAME,
1740 .id_table = smsc9420_id_table,
1741 .probe = smsc9420_probe,
1742 .remove = __devexit_p(smsc9420_remove),
1743#ifdef CONFIG_PM
1744 .suspend = smsc9420_suspend,
1745 .resume = smsc9420_resume,
1746#endif /* CONFIG_PM */
1747};
1748
1749static int __init smsc9420_init_module(void)
1750{
1751 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1752
1753 return pci_register_driver(&smsc9420_driver);
1754}
1755
1756static void __exit smsc9420_exit_module(void)
1757{
1758 pci_unregister_driver(&smsc9420_driver);
1759}
1760
1761module_init(smsc9420_init_module);
1762module_exit(smsc9420_exit_module);
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