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net: preserve ifreq parameter when calling generic phy_mii_ioctl().
[net-next-2.6.git] / drivers / net / smsc9420.c
CommitLineData
2cb37728
SG		 1 /***************************************************************************
2 *
3 * Copyright (C) 2007,2008 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 ***************************************************************************
20 */
21
22#include <linux/kernel.h>
23#include <linux/netdevice.h>
24#include <linux/phy.h>
25#include <linux/pci.h>
26#include <linux/if_vlan.h>
27#include <linux/dma-mapping.h>
28#include <linux/crc32.h>
5a0e3ad6 29#include <linux/slab.h>
2cb37728
SG		 30#include <asm/unaligned.h>
31#include "smsc9420.h"
32
33#define DRV_NAME "smsc9420"
34#define PFX DRV_NAME ": "
35#define DRV_MDIONAME "smsc9420-mdio"
36#define DRV_DESCRIPTION "SMSC LAN9420 driver"
37#define DRV_VERSION "1.01"
38
39MODULE_LICENSE("GPL");
40MODULE_VERSION(DRV_VERSION);
41
42struct smsc9420_dma_desc {
43 u32 status;
44 u32 length;
45 u32 buffer1;
46 u32 buffer2;
47};
48
49struct smsc9420_ring_info {
50 struct sk_buff *skb;
51 dma_addr_t mapping;
52};
53
54struct smsc9420_pdata {
55 void __iomem *base_addr;
56 struct pci_dev *pdev;
57 struct net_device *dev;
58
59 struct smsc9420_dma_desc *rx_ring;
60 struct smsc9420_dma_desc *tx_ring;
61 struct smsc9420_ring_info *tx_buffers;
62 struct smsc9420_ring_info *rx_buffers;
63 dma_addr_t rx_dma_addr;
64 dma_addr_t tx_dma_addr;
65 int tx_ring_head, tx_ring_tail;
66 int rx_ring_head, rx_ring_tail;
67
68 spinlock_t int_lock;
69 spinlock_t phy_lock;
70
71 struct napi_struct napi;
72
73 bool software_irq_signal;
74 bool rx_csum;
75 u32 msg_enable;
76
77 struct phy_device *phy_dev;
78 struct mii_bus *mii_bus;
79 int phy_irq[PHY_MAX_ADDR];
80 int last_duplex;
81 int last_carrier;
82};
83
a3aa1884 84static DEFINE_PCI_DEVICE_TABLE(smsc9420_id_table) = {
2cb37728
SG		 85 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
86 { 0, }
87};
88
89MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
90
91#define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
92
93static uint smsc_debug;
94static uint debug = -1;
95module_param(debug, uint, 0);
96MODULE_PARM_DESC(debug, "debug level");
97
98#define smsc_dbg(TYPE, f, a...) \
99do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
100 printk(KERN_DEBUG PFX f "\n", ## a); \
101} while (0)
102
103#define smsc_info(TYPE, f, a...) \
104do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
105 printk(KERN_INFO PFX f "\n", ## a); \
106} while (0)
107
108#define smsc_warn(TYPE, f, a...) \
109do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
110 printk(KERN_WARNING PFX f "\n", ## a); \
111} while (0)
112
113static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
114{
115 return ioread32(pd->base_addr + offset);
116}
117
118static inline void
119smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
120{
121 iowrite32(value, pd->base_addr + offset);
122}
123
124static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
125{
126 /* to ensure PCI write completion, we must perform a PCI read */
127 smsc9420_reg_read(pd, ID_REV);
128}
129
130static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
131{
132 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
133 unsigned long flags;
134 u32 addr;
135 int i, reg = -EIO;
136
137 spin_lock_irqsave(&pd->phy_lock, flags);
138
139 /* confirm MII not busy */
140 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
141 smsc_warn(DRV, "MII is busy???");
142 goto out;
143 }
144
145 /* set the address, index & direction (read from PHY) */
146 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
147 MII_ACCESS_MII_READ_;
148 smsc9420_reg_write(pd, MII_ACCESS, addr);
149
150 /* wait for read to complete with 50us timeout */
151 for (i = 0; i < 5; i++) {
152 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
153 MII_ACCESS_MII_BUSY_)) {
154 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
155 goto out;
156 }
157 udelay(10);
158 }
159
160 smsc_warn(DRV, "MII busy timeout!");
161
162out:
163 spin_unlock_irqrestore(&pd->phy_lock, flags);
164 return reg;
165}
166
167static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
168 u16 val)
169{
170 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
171 unsigned long flags;
172 u32 addr;
173 int i, reg = -EIO;
174
175 spin_lock_irqsave(&pd->phy_lock, flags);
176
177 /* confirm MII not busy */
178 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
179 smsc_warn(DRV, "MII is busy???");
180 goto out;
181 }
182
183 /* put the data to write in the MAC */
184 smsc9420_reg_write(pd, MII_DATA, (u32)val);
185
186 /* set the address, index & direction (write to PHY) */
187 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
188 MII_ACCESS_MII_WRITE_;
189 smsc9420_reg_write(pd, MII_ACCESS, addr);
190
191 /* wait for write to complete with 50us timeout */
192 for (i = 0; i < 5; i++) {
193 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
194 MII_ACCESS_MII_BUSY_)) {
195 reg = 0;
196 goto out;
197 }
198 udelay(10);
199 }
200
201 smsc_warn(DRV, "MII busy timeout!");
202
203out:
204 spin_unlock_irqrestore(&pd->phy_lock, flags);
205 return reg;
206}
207
208/* Returns hash bit number for given MAC address
209 * Example:
210 * 01 00 5E 00 00 01 -> returns bit number 31 */
211static u32 smsc9420_hash(u8 addr[ETH_ALEN])
212{
213 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
214}
215
216static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
217{
218 int timeout = 100000;
219
220 BUG_ON(!pd);
221
222 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
223 smsc_dbg(DRV, "smsc9420_eeprom_reload: Eeprom busy");
224 return -EIO;
225 }
226
227 smsc9420_reg_write(pd, E2P_CMD,
228 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
229
230 do {
231 udelay(10);
232 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
233 return 0;
234 } while (timeout--);
235
236 smsc_warn(DRV, "smsc9420_eeprom_reload: Eeprom timed out");
237 return -EIO;
238}
239
240/* Standard ioctls for mii-tool */
241static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
242{
243 struct smsc9420_pdata *pd = netdev_priv(dev);
244
245 if (!netif_running(dev) || !pd->phy_dev)
246 return -EINVAL;
247
28b04113 248 return phy_mii_ioctl(pd->phy_dev, ifr, cmd);
2cb37728
SG		 249}
250
251static int smsc9420_ethtool_get_settings(struct net_device *dev,
252 struct ethtool_cmd *cmd)
253{
254 struct smsc9420_pdata *pd = netdev_priv(dev);
255
6c53b1b1
SG		 256 if (!pd->phy_dev)
257 return -ENODEV;
258
2cb37728
SG		 259 cmd->maxtxpkt = 1;
260 cmd->maxrxpkt = 1;
261 return phy_ethtool_gset(pd->phy_dev, cmd);
262}
263
264static int smsc9420_ethtool_set_settings(struct net_device *dev,
265 struct ethtool_cmd *cmd)
266{
267 struct smsc9420_pdata *pd = netdev_priv(dev);
268
6c53b1b1
SG		 269 if (!pd->phy_dev)
270 return -ENODEV;
271
2cb37728
SG		 272 return phy_ethtool_sset(pd->phy_dev, cmd);
273}
274
275static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
276 struct ethtool_drvinfo *drvinfo)
277{
278 struct smsc9420_pdata *pd = netdev_priv(netdev);
279
280 strcpy(drvinfo->driver, DRV_NAME);
281 strcpy(drvinfo->bus_info, pci_name(pd->pdev));
282 strcpy(drvinfo->version, DRV_VERSION);
283}
284
285static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
286{
287 struct smsc9420_pdata *pd = netdev_priv(netdev);
288 return pd->msg_enable;
289}
290
291static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
292{
293 struct smsc9420_pdata *pd = netdev_priv(netdev);
294 pd->msg_enable = data;
295}
296
297static int smsc9420_ethtool_nway_reset(struct net_device *netdev)
298{
299 struct smsc9420_pdata *pd = netdev_priv(netdev);
6c53b1b1
SG		 300
301 if (!pd->phy_dev)
302 return -ENODEV;
303
2cb37728
SG		 304 return phy_start_aneg(pd->phy_dev);
305}
306
a7276db6
SG		 307static int smsc9420_ethtool_getregslen(struct net_device *dev)
308{
309 /* all smsc9420 registers plus all phy registers */
310 return 0x100 + (32 * sizeof(u32));
311}
312
313static void
314smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
315 void *buf)
316{
317 struct smsc9420_pdata *pd = netdev_priv(dev);
318 struct phy_device *phy_dev = pd->phy_dev;
319 unsigned int i, j = 0;
320 u32 *data = buf;
321
322 regs->version = smsc9420_reg_read(pd, ID_REV);
323 for (i = 0; i < 0x100; i += (sizeof(u32)))
324 data[j++] = smsc9420_reg_read(pd, i);
325
6c53b1b1
SG		 326 // cannot read phy registers if the net device is down
327 if (!phy_dev)
328 return;
329
a7276db6
SG		 330 for (i = 0; i <= 31; i++)
331 data[j++] = smsc9420_mii_read(phy_dev->bus, phy_dev->addr, i);
332}
333
012b215c
SG		 334static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
335{
336 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
337 temp &= ~GPIO_CFG_EEPR_EN_;
338 smsc9420_reg_write(pd, GPIO_CFG, temp);
339 msleep(1);
340}
341
342static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
343{
344 int timeout = 100;
345 u32 e2cmd;
346
347 smsc_dbg(HW, "op 0x%08x", op);
348 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
349 smsc_warn(HW, "Busy at start");
350 return -EBUSY;
351 }
352
353 e2cmd = op | E2P_CMD_EPC_BUSY_;
354 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
355
356 do {
357 msleep(1);
358 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
9df8f4e3 359 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
012b215c
SG		 360
361 if (!timeout) {
362 smsc_info(HW, "TIMED OUT");
363 return -EAGAIN;
364 }
365
366 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
367 smsc_info(HW, "Error occured during eeprom operation");
368 return -EINVAL;
369 }
370
371 return 0;
372}
373
374static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
375 u8 address, u8 *data)
376{
377 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
378 int ret;
379
380 smsc_dbg(HW, "address 0x%x", address);
381 ret = smsc9420_eeprom_send_cmd(pd, op);
382
383 if (!ret)
384 data[address] = smsc9420_reg_read(pd, E2P_DATA);
385
386 return ret;
387}
388
389static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
390 u8 address, u8 data)
391{
392 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
393 int ret;
394
395 smsc_dbg(HW, "address 0x%x, data 0x%x", address, data);
396 ret = smsc9420_eeprom_send_cmd(pd, op);
397
398 if (!ret) {
399 op = E2P_CMD_EPC_CMD_WRITE_ | address;
400 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
401 ret = smsc9420_eeprom_send_cmd(pd, op);
402 }
403
404 return ret;
405}
406
407static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)
408{
409 return SMSC9420_EEPROM_SIZE;
410}
411
412static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
413 struct ethtool_eeprom *eeprom, u8 *data)
414{
415 struct smsc9420_pdata *pd = netdev_priv(dev);
416 u8 eeprom_data[SMSC9420_EEPROM_SIZE];
417 int len, i;
418
419 smsc9420_eeprom_enable_access(pd);
420
421 len = min(eeprom->len, SMSC9420_EEPROM_SIZE);
422 for (i = 0; i < len; i++) {
423 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
424 if (ret < 0) {
425 eeprom->len = 0;
426 return ret;
427 }
428 }
429
430 memcpy(data, &eeprom_data[eeprom->offset], len);
196b7e1b 431 eeprom->magic = SMSC9420_EEPROM_MAGIC;
012b215c
SG		 432 eeprom->len = len;
433 return 0;
434}
435
436static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
437 struct ethtool_eeprom *eeprom, u8 *data)
438{
439 struct smsc9420_pdata *pd = netdev_priv(dev);
440 int ret;
441
196b7e1b
SG		 442 if (eeprom->magic != SMSC9420_EEPROM_MAGIC)
443 return -EINVAL;
444
012b215c
SG		 445 smsc9420_eeprom_enable_access(pd);
446 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
447 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
448 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
449
450 /* Single byte write, according to man page */
451 eeprom->len = 1;
452
453 return ret;
454}
455
2cb37728
SG		 456static const struct ethtool_ops smsc9420_ethtool_ops = {
457 .get_settings = smsc9420_ethtool_get_settings,
458 .set_settings = smsc9420_ethtool_set_settings,
459 .get_drvinfo = smsc9420_ethtool_get_drvinfo,
460 .get_msglevel = smsc9420_ethtool_get_msglevel,
461 .set_msglevel = smsc9420_ethtool_set_msglevel,
462 .nway_reset = smsc9420_ethtool_nway_reset,
463 .get_link = ethtool_op_get_link,
012b215c
SG		 464 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len,
465 .get_eeprom = smsc9420_ethtool_get_eeprom,
466 .set_eeprom = smsc9420_ethtool_set_eeprom,
a7276db6
SG		 467 .get_regs_len = smsc9420_ethtool_getregslen,
468 .get_regs = smsc9420_ethtool_getregs,
2cb37728
SG		 469};
470
471/* Sets the device MAC address to dev_addr */
472static void smsc9420_set_mac_address(struct net_device *dev)
473{
474 struct smsc9420_pdata *pd = netdev_priv(dev);
475 u8 *dev_addr = dev->dev_addr;
476 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
477 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
478 (dev_addr[1] << 8) | dev_addr[0];
479
480 smsc9420_reg_write(pd, ADDRH, mac_high16);
481 smsc9420_reg_write(pd, ADDRL, mac_low32);
482}
483
484static void smsc9420_check_mac_address(struct net_device *dev)
485{
486 struct smsc9420_pdata *pd = netdev_priv(dev);
487
488 /* Check if mac address has been specified when bringing interface up */
489 if (is_valid_ether_addr(dev->dev_addr)) {
490 smsc9420_set_mac_address(dev);
491 smsc_dbg(PROBE, "MAC Address is specified by configuration");
492 } else {
493 /* Try reading mac address from device. if EEPROM is present
494 * it will already have been set */
495 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
496 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
497 dev->dev_addr[0] = (u8)(mac_low32);
498 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
499 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
500 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
501 dev->dev_addr[4] = (u8)(mac_high16);
502 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
503
504 if (is_valid_ether_addr(dev->dev_addr)) {
505 /* eeprom values are valid so use them */
506 smsc_dbg(PROBE, "Mac Address is read from EEPROM");
507 } else {
508 /* eeprom values are invalid, generate random MAC */
509 random_ether_addr(dev->dev_addr);
510 smsc9420_set_mac_address(dev);
511 smsc_dbg(PROBE,
512 "MAC Address is set to random_ether_addr");
513 }
514 }
515}
516
517static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
518{
519 u32 dmac_control, mac_cr, dma_intr_ena;
46578a69 520 int timeout = 1000;
2cb37728
SG		 521
522 /* disable TX DMAC */
523 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
524 dmac_control &= (~DMAC_CONTROL_ST_);
525 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
526
527 /* Wait max 10ms for transmit process to stop */
46578a69 528 while (--timeout) {
2cb37728
SG		 529 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
530 break;
531 udelay(10);
532 }
533
46578a69 534 if (!timeout)
2cb37728
SG		 535 smsc_warn(IFDOWN, "TX DMAC failed to stop");
536
537 /* ACK Tx DMAC stop bit */
538 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
539
540 /* mask TX DMAC interrupts */
541 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
542 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
543 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
544 smsc9420_pci_flush_write(pd);
545
546 /* stop MAC TX */
547 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
548 smsc9420_reg_write(pd, MAC_CR, mac_cr);
549 smsc9420_pci_flush_write(pd);
550}
551
552static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
553{
554 int i;
555
556 BUG_ON(!pd->tx_ring);
557
558 if (!pd->tx_buffers)
559 return;
560
561 for (i = 0; i < TX_RING_SIZE; i++) {
562 struct sk_buff *skb = pd->tx_buffers[i].skb;
563
564 if (skb) {
565 BUG_ON(!pd->tx_buffers[i].mapping);
566 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping,
567 skb->len, PCI_DMA_TODEVICE);
568 dev_kfree_skb_any(skb);
569 }
570
571 pd->tx_ring[i].status = 0;
572 pd->tx_ring[i].length = 0;
573 pd->tx_ring[i].buffer1 = 0;
574 pd->tx_ring[i].buffer2 = 0;
575 }
576 wmb();
577
578 kfree(pd->tx_buffers);
579 pd->tx_buffers = NULL;
580
581 pd->tx_ring_head = 0;
582 pd->tx_ring_tail = 0;
583}
584
585static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
586{
587 int i;
588
589 BUG_ON(!pd->rx_ring);
590
591 if (!pd->rx_buffers)
592 return;
593
594 for (i = 0; i < RX_RING_SIZE; i++) {
595 if (pd->rx_buffers[i].skb)
596 dev_kfree_skb_any(pd->rx_buffers[i].skb);
597
598 if (pd->rx_buffers[i].mapping)
599 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping,
600 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
601
602 pd->rx_ring[i].status = 0;
603 pd->rx_ring[i].length = 0;
604 pd->rx_ring[i].buffer1 = 0;
605 pd->rx_ring[i].buffer2 = 0;
606 }
607 wmb();
608
609 kfree(pd->rx_buffers);
610 pd->rx_buffers = NULL;
611
612 pd->rx_ring_head = 0;
613 pd->rx_ring_tail = 0;
614}
615
616static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
617{
46578a69 618 int timeout = 1000;
2cb37728
SG		 619 u32 mac_cr, dmac_control, dma_intr_ena;
620
621 /* mask RX DMAC interrupts */
622 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
623 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
624 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
625 smsc9420_pci_flush_write(pd);
626
627 /* stop RX MAC prior to stoping DMA */
628 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
629 smsc9420_reg_write(pd, MAC_CR, mac_cr);
630 smsc9420_pci_flush_write(pd);
631
632 /* stop RX DMAC */
633 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
634 dmac_control &= (~DMAC_CONTROL_SR_);
635 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
636 smsc9420_pci_flush_write(pd);
637
638 /* wait up to 10ms for receive to stop */
46578a69 639 while (--timeout) {
2cb37728
SG		 640 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
641 break;
642 udelay(10);
643 }
644
46578a69 645 if (!timeout)
2cb37728
SG		 646 smsc_warn(IFDOWN, "RX DMAC did not stop! timeout.");
647
648 /* ACK the Rx DMAC stop bit */
649 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
650}
651
652static irqreturn_t smsc9420_isr(int irq, void *dev_id)
653{
654 struct smsc9420_pdata *pd = dev_id;
655 u32 int_cfg, int_sts, int_ctl;
656 irqreturn_t ret = IRQ_NONE;
657 ulong flags;
658
659 BUG_ON(!pd);
660 BUG_ON(!pd->base_addr);
661
662 int_cfg = smsc9420_reg_read(pd, INT_CFG);
663
664 /* check if it's our interrupt */
665 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
666 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
667 return IRQ_NONE;
668
669 int_sts = smsc9420_reg_read(pd, INT_STAT);
670
671 if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
672 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
673 u32 ints_to_clear = 0;
674
675 if (status & DMAC_STS_TX_) {
676 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
677 netif_wake_queue(pd->dev);
678 }
679
680 if (status & DMAC_STS_RX_) {
681 /* mask RX DMAC interrupts */
682 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
683 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
684 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
685 smsc9420_pci_flush_write(pd);
686
687 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
288379f0 688 napi_schedule(&pd->napi);
2cb37728
SG		 689 }
690
691 if (ints_to_clear)
692 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
693
694 ret = IRQ_HANDLED;
695 }
696
697 if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
698 /* mask software interrupt */
699 spin_lock_irqsave(&pd->int_lock, flags);
700 int_ctl = smsc9420_reg_read(pd, INT_CTL);
701 int_ctl &= (~INT_CTL_SW_INT_EN_);
702 smsc9420_reg_write(pd, INT_CTL, int_ctl);
703 spin_unlock_irqrestore(&pd->int_lock, flags);
704
705 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
706 pd->software_irq_signal = true;
707 smp_wmb();
708
709 ret = IRQ_HANDLED;
710 }
711
712 /* to ensure PCI write completion, we must perform a PCI read */
713 smsc9420_pci_flush_write(pd);
714
715 return ret;
716}
717
e312674f
SG		 718#ifdef CONFIG_NET_POLL_CONTROLLER
719static void smsc9420_poll_controller(struct net_device *dev)
720{
721 disable_irq(dev->irq);
722 smsc9420_isr(0, dev);
723 enable_irq(dev->irq);
724}
725#endif /* CONFIG_NET_POLL_CONTROLLER */
726
2cb37728
SG		 727static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
728{
729 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
730 smsc9420_reg_read(pd, BUS_MODE);
731 udelay(2);
732 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
733 smsc_warn(DRV, "Software reset not cleared");
734}
735
736static int smsc9420_stop(struct net_device *dev)
737{
738 struct smsc9420_pdata *pd = netdev_priv(dev);
739 u32 int_cfg;
740 ulong flags;
741
742 BUG_ON(!pd);
743 BUG_ON(!pd->phy_dev);
744
745 /* disable master interrupt */
746 spin_lock_irqsave(&pd->int_lock, flags);
747 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
748 smsc9420_reg_write(pd, INT_CFG, int_cfg);
749 spin_unlock_irqrestore(&pd->int_lock, flags);
750
751 netif_tx_disable(dev);
752 napi_disable(&pd->napi);
753
754 smsc9420_stop_tx(pd);
755 smsc9420_free_tx_ring(pd);
756
757 smsc9420_stop_rx(pd);
758 smsc9420_free_rx_ring(pd);
759
760 free_irq(dev->irq, pd);
761
762 smsc9420_dmac_soft_reset(pd);
763
764 phy_stop(pd->phy_dev);
765
766 phy_disconnect(pd->phy_dev);
767 pd->phy_dev = NULL;
768 mdiobus_unregister(pd->mii_bus);
769 mdiobus_free(pd->mii_bus);
770
771 return 0;
772}
773
774static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
775{
776 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
777 dev->stats.rx_errors++;
778 if (desc_status & RDES0_DESCRIPTOR_ERROR_)
779 dev->stats.rx_over_errors++;
780 else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
781 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
782 dev->stats.rx_frame_errors++;
783 else if (desc_status & RDES0_CRC_ERROR_)
784 dev->stats.rx_crc_errors++;
785 }
786
787 if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
788 dev->stats.rx_length_errors++;
789
790 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
791 (desc_status & RDES0_FIRST_DESCRIPTOR_))))
792 dev->stats.rx_length_errors++;
793
794 if (desc_status & RDES0_MULTICAST_FRAME_)
795 dev->stats.multicast++;
796}
797
798static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
799 const u32 status)
800{
801 struct net_device *dev = pd->dev;
802 struct sk_buff *skb;
803 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
804 >> RDES0_FRAME_LENGTH_SHFT_;
805
806 /* remove crc from packet lendth */
807 packet_length -= 4;
808
809 if (pd->rx_csum)
810 packet_length -= 2;
811
812 dev->stats.rx_packets++;
813 dev->stats.rx_bytes += packet_length;
814
815 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping,
816 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
817 pd->rx_buffers[index].mapping = 0;
818
819 skb = pd->rx_buffers[index].skb;
820 pd->rx_buffers[index].skb = NULL;
821
822 if (pd->rx_csum) {
823 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
824 NET_IP_ALIGN + packet_length + 4);
cd7a3b75 825 put_unaligned_le16(hw_csum, &skb->csum);
2cb37728
SG		 826 skb->ip_summed = CHECKSUM_COMPLETE;
827 }
828
829 skb_reserve(skb, NET_IP_ALIGN);
830 skb_put(skb, packet_length);
831
832 skb->protocol = eth_type_trans(skb, dev);
833
834 netif_receive_skb(skb);
2cb37728
SG		 835}
836
837static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
838{
839 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
840 dma_addr_t mapping;
841
842 BUG_ON(pd->rx_buffers[index].skb);
843 BUG_ON(pd->rx_buffers[index].mapping);
844
845 if (unlikely(!skb)) {
846 smsc_warn(RX_ERR, "Failed to allocate new skb!");
847 return -ENOMEM;
848 }
849
850 skb->dev = pd->dev;
851
852 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb),
853 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
854 if (pci_dma_mapping_error(pd->pdev, mapping)) {
855 dev_kfree_skb_any(skb);
856 smsc_warn(RX_ERR, "pci_map_single failed!");
857 return -ENOMEM;
858 }
859
860 pd->rx_buffers[index].skb = skb;
861 pd->rx_buffers[index].mapping = mapping;
862 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
863 pd->rx_ring[index].status = RDES0_OWN_;
864 wmb();
865
866 return 0;
867}
868
869static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
870{
871 while (pd->rx_ring_tail != pd->rx_ring_head) {
872 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
873 break;
874
875 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
876 }
877}
878
879static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
880{
881 struct smsc9420_pdata *pd =
882 container_of(napi, struct smsc9420_pdata, napi);
883 struct net_device *dev = pd->dev;
884 u32 drop_frame_cnt, dma_intr_ena, status;
885 int work_done;
886
887 for (work_done = 0; work_done < budget; work_done++) {
888 rmb();
889 status = pd->rx_ring[pd->rx_ring_head].status;
890
891 /* stop if DMAC owns this dma descriptor */
892 if (status & RDES0_OWN_)
893 break;
894
895 smsc9420_rx_count_stats(dev, status);
896 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
897 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
898 smsc9420_alloc_new_rx_buffers(pd);
899 }
900
901 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
902 dev->stats.rx_dropped +=
903 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
904
905 /* Kick RXDMA */
906 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
907 smsc9420_pci_flush_write(pd);
908
909 if (work_done < budget) {
288379f0 910 napi_complete(&pd->napi);
2cb37728
SG		 911
912 /* re-enable RX DMA interrupts */
913 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
914 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
915 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
916 smsc9420_pci_flush_write(pd);
917 }
918 return work_done;
919}
920
921static void
922smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
923{
924 if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
925 dev->stats.tx_errors++;
926 if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
927 TDES0_EXCESSIVE_COLLISIONS_))
928 dev->stats.tx_aborted_errors++;
929
930 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
931 dev->stats.tx_carrier_errors++;
932 } else {
933 dev->stats.tx_packets++;
934 dev->stats.tx_bytes += (length & 0x7FF);
935 }
936
937 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
938 dev->stats.collisions += 16;
939 } else {
940 dev->stats.collisions +=
941 (status & TDES0_COLLISION_COUNT_MASK_) >>
942 TDES0_COLLISION_COUNT_SHFT_;
943 }
944
945 if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
946 dev->stats.tx_heartbeat_errors++;
947}
948
949/* Check for completed dma transfers, update stats and free skbs */
950static void smsc9420_complete_tx(struct net_device *dev)
951{
952 struct smsc9420_pdata *pd = netdev_priv(dev);
953
954 while (pd->tx_ring_tail != pd->tx_ring_head) {
955 int index = pd->tx_ring_tail;
956 u32 status, length;
957
958 rmb();
959 status = pd->tx_ring[index].status;
960 length = pd->tx_ring[index].length;
961
962 /* Check if DMA still owns this descriptor */
963 if (unlikely(TDES0_OWN_ & status))
964 break;
965
966 smsc9420_tx_update_stats(dev, status, length);
967
968 BUG_ON(!pd->tx_buffers[index].skb);
969 BUG_ON(!pd->tx_buffers[index].mapping);
970
971 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping,
972 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE);
973 pd->tx_buffers[index].mapping = 0;
974
975 dev_kfree_skb_any(pd->tx_buffers[index].skb);
976 pd->tx_buffers[index].skb = NULL;
977
978 pd->tx_ring[index].buffer1 = 0;
979 wmb();
980
981 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
982 }
983}
984
61357325
SH		 985static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb,
986 struct net_device *dev)
2cb37728
SG		 987{
988 struct smsc9420_pdata *pd = netdev_priv(dev);
989 dma_addr_t mapping;
990 int index = pd->tx_ring_head;
991 u32 tmp_desc1;
992 bool about_to_take_last_desc =
993 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
994
995 smsc9420_complete_tx(dev);
996
997 rmb();
998 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
999 BUG_ON(pd->tx_buffers[index].skb);
1000 BUG_ON(pd->tx_buffers[index].mapping);
1001
1002 mapping = pci_map_single(pd->pdev, skb->data,
1003 skb->len, PCI_DMA_TODEVICE);
1004 if (pci_dma_mapping_error(pd->pdev, mapping)) {
1005 smsc_warn(TX_ERR, "pci_map_single failed, dropping packet");
1006 return NETDEV_TX_BUSY;
1007 }
1008
1009 pd->tx_buffers[index].skb = skb;
1010 pd->tx_buffers[index].mapping = mapping;
1011
1012 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
1013 if (unlikely(about_to_take_last_desc)) {
1014 tmp_desc1 |= TDES1_IC_;
1015 netif_stop_queue(pd->dev);
1016 }
1017
1018 /* check if we are at the last descriptor and need to set EOR */
1019 if (unlikely(index == (TX_RING_SIZE - 1)))
1020 tmp_desc1 |= TDES1_TER_;
1021
1022 pd->tx_ring[index].buffer1 = mapping;
1023 pd->tx_ring[index].length = tmp_desc1;
1024 wmb();
1025
1026 /* increment head */
1027 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
1028
1029 /* assign ownership to DMAC */
1030 pd->tx_ring[index].status = TDES0_OWN_;
1031 wmb();
1032
1033 /* kick the DMA */
1034 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
1035 smsc9420_pci_flush_write(pd);
1036
2cb37728
SG		 1037 return NETDEV_TX_OK;
1038}
1039
1040static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
1041{
1042 struct smsc9420_pdata *pd = netdev_priv(dev);
1043 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
1044 dev->stats.rx_dropped +=
1045 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
1046 return &dev->stats;
1047}
1048
1049static void smsc9420_set_multicast_list(struct net_device *dev)
1050{
1051 struct smsc9420_pdata *pd = netdev_priv(dev);
1052 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1053
1054 if (dev->flags & IFF_PROMISC) {
1055 smsc_dbg(HW, "Promiscuous Mode Enabled");
1056 mac_cr |= MAC_CR_PRMS_;
1057 mac_cr &= (~MAC_CR_MCPAS_);
1058 mac_cr &= (~MAC_CR_HPFILT_);
1059 } else if (dev->flags & IFF_ALLMULTI) {
1060 smsc_dbg(HW, "Receive all Multicast Enabled");
1061 mac_cr &= (~MAC_CR_PRMS_);
1062 mac_cr |= MAC_CR_MCPAS_;
1063 mac_cr &= (~MAC_CR_HPFILT_);
4cd24eaf 1064 } else if (!netdev_mc_empty(dev)) {
22bedad3 1065 struct netdev_hw_addr *ha;
2cb37728
SG		 1066 u32 hash_lo = 0, hash_hi = 0;
1067
1068 smsc_dbg(HW, "Multicast filter enabled");
22bedad3
JP		 1069 netdev_for_each_mc_addr(ha, dev) {
1070 u32 bit_num = smsc9420_hash(ha->addr);
2cb37728
SG		 1071 u32 mask = 1 << (bit_num & 0x1F);
1072
1073 if (bit_num & 0x20)
1074 hash_hi |= mask;
1075 else
1076 hash_lo |= mask;
1077
2cb37728
SG		 1078 }
1079 smsc9420_reg_write(pd, HASHH, hash_hi);
1080 smsc9420_reg_write(pd, HASHL, hash_lo);
1081
1082 mac_cr &= (~MAC_CR_PRMS_);
1083 mac_cr &= (~MAC_CR_MCPAS_);
1084 mac_cr |= MAC_CR_HPFILT_;
1085 } else {
1086 smsc_dbg(HW, "Receive own packets only.");
1087 smsc9420_reg_write(pd, HASHH, 0);
1088 smsc9420_reg_write(pd, HASHL, 0);
1089
1090 mac_cr &= (~MAC_CR_PRMS_);
1091 mac_cr &= (~MAC_CR_MCPAS_);
1092 mac_cr &= (~MAC_CR_HPFILT_);
1093 }
1094
1095 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1096 smsc9420_pci_flush_write(pd);
1097}
1098
2cb37728
SG		 1099static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1100{
1101 struct phy_device *phy_dev = pd->phy_dev;
1102 u32 flow;
1103
1104 if (phy_dev->duplex == DUPLEX_FULL) {
1105 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
1106 u16 rmtadv = phy_read(phy_dev, MII_LPA);
bc02ff95 1107 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
2cb37728
SG		 1108
1109 if (cap & FLOW_CTRL_RX)
1110 flow = 0xFFFF0002;
1111 else
1112 flow = 0;
1113
1114 smsc_info(LINK, "rx pause %s, tx pause %s",
1115 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
1116 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
1117 } else {
1118 smsc_info(LINK, "half duplex");
1119 flow = 0;
1120 }
1121
1122 smsc9420_reg_write(pd, FLOW, flow);
1123}
1124
1125/* Update link mode if anything has changed. Called periodically when the
1126 * PHY is in polling mode, even if nothing has changed. */
1127static void smsc9420_phy_adjust_link(struct net_device *dev)
1128{
1129 struct smsc9420_pdata *pd = netdev_priv(dev);
1130 struct phy_device *phy_dev = pd->phy_dev;
1131 int carrier;
1132
1133 if (phy_dev->duplex != pd->last_duplex) {
1134 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1135 if (phy_dev->duplex) {
1136 smsc_dbg(LINK, "full duplex mode");
1137 mac_cr |= MAC_CR_FDPX_;
1138 } else {
1139 smsc_dbg(LINK, "half duplex mode");
1140 mac_cr &= ~MAC_CR_FDPX_;
1141 }
1142 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1143
1144 smsc9420_phy_update_flowcontrol(pd);
1145 pd->last_duplex = phy_dev->duplex;
1146 }
1147
1148 carrier = netif_carrier_ok(dev);
1149 if (carrier != pd->last_carrier) {
1150 if (carrier)
1151 smsc_dbg(LINK, "carrier OK");
1152 else
1153 smsc_dbg(LINK, "no carrier");
1154 pd->last_carrier = carrier;
1155 }
1156}
1157
1158static int smsc9420_mii_probe(struct net_device *dev)
1159{
1160 struct smsc9420_pdata *pd = netdev_priv(dev);
1161 struct phy_device *phydev = NULL;
1162
1163 BUG_ON(pd->phy_dev);
1164
1165 /* Device only supports internal PHY at address 1 */
1166 if (!pd->mii_bus->phy_map[1]) {
1167 pr_err("%s: no PHY found at address 1\n", dev->name);
1168 return -ENODEV;
1169 }
1170
1171 phydev = pd->mii_bus->phy_map[1];
1172 smsc_info(PROBE, "PHY addr %d, phy_id 0x%08X", phydev->addr,
1173 phydev->phy_id);
1174
db1d7bf7 1175 phydev = phy_connect(dev, dev_name(&phydev->dev),
a974a679 1176 smsc9420_phy_adjust_link, 0, PHY_INTERFACE_MODE_MII);
2cb37728
SG		 1177
1178 if (IS_ERR(phydev)) {
1179 pr_err("%s: Could not attach to PHY\n", dev->name);
1180 return PTR_ERR(phydev);
1181 }
1182
1183 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
db1d7bf7 1184 dev->name, phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
2cb37728
SG		 1185
1186 /* mask with MAC supported features */
1187 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
1188 SUPPORTED_Asym_Pause);
1189 phydev->advertising = phydev->supported;
1190
1191 pd->phy_dev = phydev;
1192 pd->last_duplex = -1;
1193 pd->last_carrier = -1;
1194
1195 return 0;
1196}
1197
1198static int smsc9420_mii_init(struct net_device *dev)
1199{
1200 struct smsc9420_pdata *pd = netdev_priv(dev);
1201 int err = -ENXIO, i;
1202
1203 pd->mii_bus = mdiobus_alloc();
1204 if (!pd->mii_bus) {
1205 err = -ENOMEM;
1206 goto err_out_1;
1207 }
1208 pd->mii_bus->name = DRV_MDIONAME;
1209 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1210 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1211 pd->mii_bus->priv = pd;
1212 pd->mii_bus->read = smsc9420_mii_read;
1213 pd->mii_bus->write = smsc9420_mii_write;
1214 pd->mii_bus->irq = pd->phy_irq;
1215 for (i = 0; i < PHY_MAX_ADDR; ++i)
1216 pd->mii_bus->irq[i] = PHY_POLL;
1217
1218 /* Mask all PHYs except ID 1 (internal) */
1219 pd->mii_bus->phy_mask = ~(1 << 1);
1220
1221 if (mdiobus_register(pd->mii_bus)) {
1222 smsc_warn(PROBE, "Error registering mii bus");
1223 goto err_out_free_bus_2;
1224 }
1225
1226 if (smsc9420_mii_probe(dev) < 0) {
1227 smsc_warn(PROBE, "Error probing mii bus");
1228 goto err_out_unregister_bus_3;
1229 }
1230
1231 return 0;
1232
1233err_out_unregister_bus_3:
1234 mdiobus_unregister(pd->mii_bus);
1235err_out_free_bus_2:
1236 mdiobus_free(pd->mii_bus);
1237err_out_1:
1238 return err;
1239}
1240
1241static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1242{
1243 int i;
1244
1245 BUG_ON(!pd->tx_ring);
1246
1247 pd->tx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1248 TX_RING_SIZE), GFP_KERNEL);
1249 if (!pd->tx_buffers) {
1250 smsc_warn(IFUP, "Failed to allocated tx_buffers");
1251 return -ENOMEM;
1252 }
1253
1254 /* Initialize the TX Ring */
1255 for (i = 0; i < TX_RING_SIZE; i++) {
1256 pd->tx_buffers[i].skb = NULL;
1257 pd->tx_buffers[i].mapping = 0;
1258 pd->tx_ring[i].status = 0;
1259 pd->tx_ring[i].length = 0;
1260 pd->tx_ring[i].buffer1 = 0;
1261 pd->tx_ring[i].buffer2 = 0;
1262 }
1263 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1264 wmb();
1265
1266 pd->tx_ring_head = 0;
1267 pd->tx_ring_tail = 0;
1268
1269 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1270 smsc9420_pci_flush_write(pd);
1271
1272 return 0;
1273}
1274
1275static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1276{
1277 int i;
1278
1279 BUG_ON(!pd->rx_ring);
1280
1281 pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1282 RX_RING_SIZE), GFP_KERNEL);
1283 if (pd->rx_buffers == NULL) {
1284 smsc_warn(IFUP, "Failed to allocated rx_buffers");
1285 goto out;
1286 }
1287
1288 /* initialize the rx ring */
1289 for (i = 0; i < RX_RING_SIZE; i++) {
1290 pd->rx_ring[i].status = 0;
1291 pd->rx_ring[i].length = PKT_BUF_SZ;
1292 pd->rx_ring[i].buffer2 = 0;
1293 pd->rx_buffers[i].skb = NULL;
1294 pd->rx_buffers[i].mapping = 0;
1295 }
1296 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1297
1298 /* now allocate the entire ring of skbs */
1299 for (i = 0; i < RX_RING_SIZE; i++) {
1300 if (smsc9420_alloc_rx_buffer(pd, i)) {
1301 smsc_warn(IFUP, "failed to allocate rx skb %d", i);
1302 goto out_free_rx_skbs;
1303 }
1304 }
1305
1306 pd->rx_ring_head = 0;
1307 pd->rx_ring_tail = 0;
1308
1309 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1310 smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1));
1311
1312 if (pd->rx_csum) {
1313 /* Enable RX COE */
1314 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1315 smsc9420_reg_write(pd, COE_CR, coe);
1316 smsc_dbg(IFUP, "COE_CR = 0x%08x", coe);
1317 }
1318
1319 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1320 smsc9420_pci_flush_write(pd);
1321
1322 return 0;
1323
1324out_free_rx_skbs:
1325 smsc9420_free_rx_ring(pd);
1326out:
1327 return -ENOMEM;
1328}
1329
1330static int smsc9420_open(struct net_device *dev)
1331{
1332 struct smsc9420_pdata *pd;
1333 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
1334 unsigned long flags;
1335 int result = 0, timeout;
1336
1337 BUG_ON(!dev);
1338 pd = netdev_priv(dev);
1339 BUG_ON(!pd);
1340
1341 if (!is_valid_ether_addr(dev->dev_addr)) {
1342 smsc_warn(IFUP, "dev_addr is not a valid MAC address");
1343 result = -EADDRNOTAVAIL;
1344 goto out_0;
1345 }
1346
1347 netif_carrier_off(dev);
1348
3ad2f3fb 1349 /* disable, mask and acknowledge all interrupts */
2cb37728
SG		 1350 spin_lock_irqsave(&pd->int_lock, flags);
1351 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1352 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1353 smsc9420_reg_write(pd, INT_CTL, 0);
1354 spin_unlock_irqrestore(&pd->int_lock, flags);
1355 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1356 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1357 smsc9420_pci_flush_write(pd);
1358
1359 if (request_irq(dev->irq, smsc9420_isr, IRQF_SHARED | IRQF_DISABLED,
1360 DRV_NAME, pd)) {
1361 smsc_warn(IFUP, "Unable to use IRQ = %d", dev->irq);
1362 result = -ENODEV;
1363 goto out_0;
1364 }
1365
1366 smsc9420_dmac_soft_reset(pd);
1367
1368 /* make sure MAC_CR is sane */
1369 smsc9420_reg_write(pd, MAC_CR, 0);
1370
1371 smsc9420_set_mac_address(dev);
1372
1373 /* Configure GPIO pins to drive LEDs */
1374 smsc9420_reg_write(pd, GPIO_CFG,
1375 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1376
1377 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1378
1379#ifdef __BIG_ENDIAN
1380 bus_mode |= BUS_MODE_DBO_;
1381#endif
1382
1383 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1384
1385 smsc9420_pci_flush_write(pd);
1386
1387 /* set bus master bridge arbitration priority for Rx and TX DMA */
1388 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1389
1390 smsc9420_reg_write(pd, DMAC_CONTROL,
1391 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1392
1393 smsc9420_pci_flush_write(pd);
1394
1395 /* test the IRQ connection to the ISR */
1396 smsc_dbg(IFUP, "Testing ISR using IRQ %d", dev->irq);
16095595 1397 pd->software_irq_signal = false;
2cb37728
SG		 1398
1399 spin_lock_irqsave(&pd->int_lock, flags);
1400 /* configure interrupt deassertion timer and enable interrupts */
1401 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1402 int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1403 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1404 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1405
1406 /* unmask software interrupt */
1407 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1408 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1409 spin_unlock_irqrestore(&pd->int_lock, flags);
1410 smsc9420_pci_flush_write(pd);
1411
1412 timeout = 1000;
2cb37728
SG		 1413 while (timeout--) {
1414 if (pd->software_irq_signal)
1415 break;
1416 msleep(1);
1417 }
1418
1419 /* disable interrupts */
1420 spin_lock_irqsave(&pd->int_lock, flags);
1421 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1422 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1423 spin_unlock_irqrestore(&pd->int_lock, flags);
1424
1425 if (!pd->software_irq_signal) {
1426 smsc_warn(IFUP, "ISR failed signaling test");
1427 result = -ENODEV;
1428 goto out_free_irq_1;
1429 }
1430
1431 smsc_dbg(IFUP, "ISR passed test using IRQ %d", dev->irq);
1432
1433 result = smsc9420_alloc_tx_ring(pd);
1434 if (result) {
1435 smsc_warn(IFUP, "Failed to Initialize tx dma ring");
1436 result = -ENOMEM;
1437 goto out_free_irq_1;
1438 }
1439
1440 result = smsc9420_alloc_rx_ring(pd);
1441 if (result) {
1442 smsc_warn(IFUP, "Failed to Initialize rx dma ring");
1443 result = -ENOMEM;
1444 goto out_free_tx_ring_2;
1445 }
1446
1447 result = smsc9420_mii_init(dev);
1448 if (result) {
1449 smsc_warn(IFUP, "Failed to initialize Phy");
1450 result = -ENODEV;
1451 goto out_free_rx_ring_3;
1452 }
1453
1454 /* Bring the PHY up */
1455 phy_start(pd->phy_dev);
1456
1457 napi_enable(&pd->napi);
1458
1459 /* start tx and rx */
1460 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1461 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1462
1463 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1464 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1465 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1466 smsc9420_pci_flush_write(pd);
1467
1468 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1469 dma_intr_ena |=
1470 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1471 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1472 smsc9420_pci_flush_write(pd);
1473
1474 netif_wake_queue(dev);
1475
1476 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1477
1478 /* enable interrupts */
1479 spin_lock_irqsave(&pd->int_lock, flags);
1480 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1481 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1482 spin_unlock_irqrestore(&pd->int_lock, flags);
1483
1484 return 0;
1485
1486out_free_rx_ring_3:
1487 smsc9420_free_rx_ring(pd);
1488out_free_tx_ring_2:
1489 smsc9420_free_tx_ring(pd);
1490out_free_irq_1:
1491 free_irq(dev->irq, pd);
1492out_0:
1493 return result;
1494}
1495
1496#ifdef CONFIG_PM
1497
1498static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state)
1499{
1500 struct net_device *dev = pci_get_drvdata(pdev);
1501 struct smsc9420_pdata *pd = netdev_priv(dev);
1502 u32 int_cfg;
1503 ulong flags;
1504
1505 /* disable interrupts */
1506 spin_lock_irqsave(&pd->int_lock, flags);
1507 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1508 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1509 spin_unlock_irqrestore(&pd->int_lock, flags);
1510
1511 if (netif_running(dev)) {
1512 netif_tx_disable(dev);
1513 smsc9420_stop_tx(pd);
1514 smsc9420_free_tx_ring(pd);
1515
1516 napi_disable(&pd->napi);
1517 smsc9420_stop_rx(pd);
1518 smsc9420_free_rx_ring(pd);
1519
1520 free_irq(dev->irq, pd);
1521
1522 netif_device_detach(dev);
1523 }
1524
1525 pci_save_state(pdev);
1526 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1527 pci_disable_device(pdev);
1528 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1529
1530 return 0;
1531}
1532
1533static int smsc9420_resume(struct pci_dev *pdev)
1534{
1535 struct net_device *dev = pci_get_drvdata(pdev);
1536 struct smsc9420_pdata *pd = netdev_priv(dev);
1537 int err;
1538
1539 pci_set_power_state(pdev, PCI_D0);
1540 pci_restore_state(pdev);
1541
1542 err = pci_enable_device(pdev);
1543 if (err)
1544 return err;
1545
1546 pci_set_master(pdev);
1547
1548 err = pci_enable_wake(pdev, 0, 0);
1549 if (err)
1550 smsc_warn(IFUP, "pci_enable_wake failed: %d", err);
1551
1552 if (netif_running(dev)) {
1553 err = smsc9420_open(dev);
1554 netif_device_attach(dev);
1555 }
1556 return err;
1557}
1558
1559#endif /* CONFIG_PM */
1560
1561static const struct net_device_ops smsc9420_netdev_ops = {
1562 .ndo_open = smsc9420_open,
1563 .ndo_stop = smsc9420_stop,
1564 .ndo_start_xmit = smsc9420_hard_start_xmit,
1565 .ndo_get_stats = smsc9420_get_stats,
1566 .ndo_set_multicast_list = smsc9420_set_multicast_list,
1567 .ndo_do_ioctl = smsc9420_do_ioctl,
1568 .ndo_validate_addr = eth_validate_addr,
fe96aaa1 1569 .ndo_set_mac_address = eth_mac_addr,
e312674f
SG		 1570#ifdef CONFIG_NET_POLL_CONTROLLER
1571 .ndo_poll_controller = smsc9420_poll_controller,
1572#endif /* CONFIG_NET_POLL_CONTROLLER */
2cb37728
SG		 1573};
1574
1575static int __devinit
1576smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1577{
1578 struct net_device *dev;
1579 struct smsc9420_pdata *pd;
1580 void __iomem *virt_addr;
1581 int result = 0;
1582 u32 id_rev;
1583
1584 printk(KERN_INFO DRV_DESCRIPTION " version " DRV_VERSION "\n");
1585
1586 /* First do the PCI initialisation */
1587 result = pci_enable_device(pdev);
1588 if (unlikely(result)) {
1589 printk(KERN_ERR "Cannot enable smsc9420\n");
1590 goto out_0;
1591 }
1592
1593 pci_set_master(pdev);
1594
1595 dev = alloc_etherdev(sizeof(*pd));
1596 if (!dev) {
1597 printk(KERN_ERR "ether device alloc failed\n");
1598 goto out_disable_pci_device_1;
1599 }
1600
1601 SET_NETDEV_DEV(dev, &pdev->dev);
1602
1603 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
1604 printk(KERN_ERR "Cannot find PCI device base address\n");
1605 goto out_free_netdev_2;
1606 }
1607
1608 if ((pci_request_regions(pdev, DRV_NAME))) {
1609 printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n");
1610 goto out_free_netdev_2;
1611 }
1612
284901a9 1613 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2cb37728
SG		 1614 printk(KERN_ERR "No usable DMA configuration, aborting.\n");
1615 goto out_free_regions_3;
1616 }
1617
1618 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1619 pci_resource_len(pdev, SMSC_BAR));
1620 if (!virt_addr) {
1621 printk(KERN_ERR "Cannot map device registers, aborting.\n");
1622 goto out_free_regions_3;
1623 }
1624
1625 /* registers are double mapped with 0 offset for LE and 0x200 for BE */
1626 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1627
1628 dev->base_addr = (ulong)virt_addr;
1629
1630 pd = netdev_priv(dev);
1631
1632 /* pci descriptors are created in the PCI consistent area */
1633 pd->rx_ring = pci_alloc_consistent(pdev,
1634 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE +
1635 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE,
1636 &pd->rx_dma_addr);
1637
1638 if (!pd->rx_ring)
1639 goto out_free_io_4;
1640
1641 /* descriptors are aligned due to the nature of pci_alloc_consistent */
1642 pd->tx_ring = (struct smsc9420_dma_desc *)
1643 (pd->rx_ring + RX_RING_SIZE);
1644 pd->tx_dma_addr = pd->rx_dma_addr +
1645 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1646
1647 pd->pdev = pdev;
1648 pd->dev = dev;
1649 pd->base_addr = virt_addr;
1650 pd->msg_enable = smsc_debug;
1651 pd->rx_csum = true;
1652
1653 smsc_dbg(PROBE, "lan_base=0x%08lx", (ulong)virt_addr);
1654
1655 id_rev = smsc9420_reg_read(pd, ID_REV);
1656 switch (id_rev & 0xFFFF0000) {
1657 case 0x94200000:
1658 smsc_info(PROBE, "LAN9420 identified, ID_REV=0x%08X", id_rev);
1659 break;
1660 default:
1661 smsc_warn(PROBE, "LAN9420 NOT identified");
1662 smsc_warn(PROBE, "ID_REV=0x%08X", id_rev);
1663 goto out_free_dmadesc_5;
1664 }
1665
1666 smsc9420_dmac_soft_reset(pd);
1667 smsc9420_eeprom_reload(pd);
1668 smsc9420_check_mac_address(dev);
1669
1670 dev->netdev_ops = &smsc9420_netdev_ops;
1671 dev->ethtool_ops = &smsc9420_ethtool_ops;
1672 dev->irq = pdev->irq;
1673
1674 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1675
1676 result = register_netdev(dev);
1677 if (result) {
1678 smsc_warn(PROBE, "error %i registering device", result);
1679 goto out_free_dmadesc_5;
1680 }
1681
1682 pci_set_drvdata(pdev, dev);
1683
1684 spin_lock_init(&pd->int_lock);
1685 spin_lock_init(&pd->phy_lock);
1686
1687 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1688
1689 return 0;
1690
1691out_free_dmadesc_5:
1692 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1693 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1694out_free_io_4:
1695 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1696out_free_regions_3:
1697 pci_release_regions(pdev);
1698out_free_netdev_2:
1699 free_netdev(dev);
1700out_disable_pci_device_1:
1701 pci_disable_device(pdev);
1702out_0:
1703 return -ENODEV;
1704}
1705
1706static void __devexit smsc9420_remove(struct pci_dev *pdev)
1707{
1708 struct net_device *dev;
1709 struct smsc9420_pdata *pd;
1710
1711 dev = pci_get_drvdata(pdev);
1712 if (!dev)
1713 return;
1714
1715 pci_set_drvdata(pdev, NULL);
1716
1717 pd = netdev_priv(dev);
1718 unregister_netdev(dev);
1719
1720 /* tx_buffers and rx_buffers are freed in stop */
1721 BUG_ON(pd->tx_buffers);
1722 BUG_ON(pd->rx_buffers);
1723
1724 BUG_ON(!pd->tx_ring);
1725 BUG_ON(!pd->rx_ring);
1726
1727 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1728 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1729
1730 iounmap(pd->base_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1731 pci_release_regions(pdev);
1732 free_netdev(dev);
1733 pci_disable_device(pdev);
1734}
1735
1736static struct pci_driver smsc9420_driver = {
1737 .name = DRV_NAME,
1738 .id_table = smsc9420_id_table,
1739 .probe = smsc9420_probe,
1740 .remove = __devexit_p(smsc9420_remove),
1741#ifdef CONFIG_PM
1742 .suspend = smsc9420_suspend,
1743 .resume = smsc9420_resume,
1744#endif /* CONFIG_PM */
1745};
1746
1747static int __init smsc9420_init_module(void)
1748{
1749 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1750
1751 return pci_register_driver(&smsc9420_driver);
1752}
1753
1754static void __exit smsc9420_exit_module(void)
1755{
1756 pci_unregister_driver(&smsc9420_driver);
1757}
1758
1759module_init(smsc9420_init_module);
1760module_exit(smsc9420_exit_module);
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