]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/smsc911x.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drivers/net: avoid some skb->ip_summed initializations
[net-next-2.6.git] / drivers / net / smsc911x.c
CommitLineData
fd9abb3d
SG		 1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************
21 * Rewritten, heavily based on smsc911x simple driver by SMSC.
22 * Partly uses io macros from smc91x.c by Nicolas Pitre
23 *
24 * Supported devices:
25 * LAN9115, LAN9116, LAN9117, LAN9118
26 * LAN9215, LAN9216, LAN9217, LAN9218
27 * LAN9210, LAN9211
28 * LAN9220, LAN9221
29 *
30 */
31
32#include <linux/crc32.h>
33#include <linux/delay.h>
34#include <linux/errno.h>
35#include <linux/etherdevice.h>
36#include <linux/ethtool.h>
37#include <linux/init.h>
38#include <linux/ioport.h>
39#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/netdevice.h>
42#include <linux/platform_device.h>
43#include <linux/sched.h>
fd9abb3d 44#include <linux/timer.h>
fd9abb3d
SG		 45#include <linux/bug.h>
46#include <linux/bitops.h>
47#include <linux/irq.h>
48#include <linux/io.h>
833cc67c 49#include <linux/swab.h>
fd9abb3d
SG		 50#include <linux/phy.h>
51#include <linux/smsc911x.h>
6cb87823 52#include <linux/device.h>
fd9abb3d
SG		 53#include "smsc911x.h"
54
55#define SMSC_CHIPNAME "smsc911x"
56#define SMSC_MDIONAME "smsc911x-mdio"
57#define SMSC_DRV_VERSION "2008-10-21"
58
59MODULE_LICENSE("GPL");
60MODULE_VERSION(SMSC_DRV_VERSION);
61
62#if USE_DEBUG > 0
63static int debug = 16;
64#else
65static int debug = 3;
66#endif
67
68module_param(debug, int, 0);
69MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
70
71struct smsc911x_data {
72 void __iomem *ioaddr;
73
74 unsigned int idrev;
75
76 /* used to decide which workarounds apply */
77 unsigned int generation;
78
79 /* device configuration (copied from platform_data during probe) */
2107fb8b 80 struct smsc911x_platform_config config;
fd9abb3d
SG		 81
82 /* This needs to be acquired before calling any of below:
83 * smsc911x_mac_read(), smsc911x_mac_write()
84 */
85 spinlock_t mac_lock;
86
492c5d94 87 /* spinlock to ensure register accesses are serialised */
fd9abb3d 88 spinlock_t dev_lock;
fd9abb3d
SG		 89
90 struct phy_device *phy_dev;
91 struct mii_bus *mii_bus;
92 int phy_irq[PHY_MAX_ADDR];
93 unsigned int using_extphy;
94 int last_duplex;
95 int last_carrier;
96
97 u32 msg_enable;
98 unsigned int gpio_setting;
99 unsigned int gpio_orig_setting;
100 struct net_device *dev;
101 struct napi_struct napi;
102
103 unsigned int software_irq_signal;
104
105#ifdef USE_PHY_WORK_AROUND
106#define MIN_PACKET_SIZE (64)
107 char loopback_tx_pkt[MIN_PACKET_SIZE];
108 char loopback_rx_pkt[MIN_PACKET_SIZE];
109 unsigned int resetcount;
110#endif
111
112 /* Members for Multicast filter workaround */
113 unsigned int multicast_update_pending;
114 unsigned int set_bits_mask;
115 unsigned int clear_bits_mask;
116 unsigned int hashhi;
117 unsigned int hashlo;
118};
119
492c5d94 120static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
fd9abb3d 121{
2107fb8b
SG		 122 if (pdata->config.flags & SMSC911X_USE_32BIT)
123 return readl(pdata->ioaddr + reg);
124
492c5d94
CM		 125 if (pdata->config.flags & SMSC911X_USE_16BIT)
126 return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
2107fb8b 127 ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
fd9abb3d 128
2107fb8b 129 BUG();
702403af 130 return 0;
fd9abb3d
SG		 131}
132
492c5d94
CM		 133static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
134{
135 u32 data;
136 unsigned long flags;
137
138 spin_lock_irqsave(&pdata->dev_lock, flags);
139 data = __smsc911x_reg_read(pdata, reg);
140 spin_unlock_irqrestore(&pdata->dev_lock, flags);
141
142 return data;
143}
144
145static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
146 u32 val)
fd9abb3d 147{
2107fb8b
SG		 148 if (pdata->config.flags & SMSC911X_USE_32BIT) {
149 writel(val, pdata->ioaddr + reg);
150 return;
151 }
152
153 if (pdata->config.flags & SMSC911X_USE_16BIT) {
2107fb8b
SG		 154 writew(val & 0xFFFF, pdata->ioaddr + reg);
155 writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
2107fb8b
SG		 156 return;
157 }
fd9abb3d 158
2107fb8b 159 BUG();
fd9abb3d
SG		 160}
161
492c5d94
CM		 162static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
163 u32 val)
164{
165 unsigned long flags;
166
167 spin_lock_irqsave(&pdata->dev_lock, flags);
168 __smsc911x_reg_write(pdata, reg, val);
169 spin_unlock_irqrestore(&pdata->dev_lock, flags);
170}
171
fd9abb3d
SG		 172/* Writes a packet to the TX_DATA_FIFO */
173static inline void
174smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
175 unsigned int wordcount)
176{
492c5d94
CM		 177 unsigned long flags;
178
179 spin_lock_irqsave(&pdata->dev_lock, flags);
180
833cc67c
MD		 181 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
182 while (wordcount--)
492c5d94
CM		 183 __smsc911x_reg_write(pdata, TX_DATA_FIFO,
184 swab32(*buf++));
185 goto out;
833cc67c
MD		 186 }
187
2107fb8b
SG		 188 if (pdata->config.flags & SMSC911X_USE_32BIT) {
189 writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
492c5d94 190 goto out;
2107fb8b
SG		 191 }
192
193 if (pdata->config.flags & SMSC911X_USE_16BIT) {
194 while (wordcount--)
492c5d94
CM		 195 __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
196 goto out;
2107fb8b
SG		 197 }
198
199 BUG();
492c5d94
CM		 200out:
201 spin_unlock_irqrestore(&pdata->dev_lock, flags);
fd9abb3d
SG		 202}
203
204/* Reads a packet out of the RX_DATA_FIFO */
205static inline void
206smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
207 unsigned int wordcount)
208{
492c5d94
CM		 209 unsigned long flags;
210
211 spin_lock_irqsave(&pdata->dev_lock, flags);
212
833cc67c
MD		 213 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
214 while (wordcount--)
492c5d94
CM		 215 *buf++ = swab32(__smsc911x_reg_read(pdata,
216 RX_DATA_FIFO));
217 goto out;
833cc67c
MD		 218 }
219
2107fb8b
SG		 220 if (pdata->config.flags & SMSC911X_USE_32BIT) {
221 readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
492c5d94 222 goto out;
2107fb8b 223 }
fd9abb3d 224
2107fb8b
SG		 225 if (pdata->config.flags & SMSC911X_USE_16BIT) {
226 while (wordcount--)
492c5d94
CM		 227 *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
228 goto out;
2107fb8b
SG		 229 }
230
231 BUG();
492c5d94
CM		 232out:
233 spin_unlock_irqrestore(&pdata->dev_lock, flags);
2107fb8b 234}
fd9abb3d
SG		 235
236/* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
237 * and smsc911x_mac_write, so assumes mac_lock is held */
238static int smsc911x_mac_complete(struct smsc911x_data *pdata)
239{
240 int i;
241 u32 val;
242
243 SMSC_ASSERT_MAC_LOCK(pdata);
244
245 for (i = 0; i < 40; i++) {
246 val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
247 if (!(val & MAC_CSR_CMD_CSR_BUSY_))
248 return 0;
249 }
250 SMSC_WARNING(HW, "Timed out waiting for MAC not BUSY. "
251 "MAC_CSR_CMD: 0x%08X", val);
252 return -EIO;
253}
254
255/* Fetches a MAC register value. Assumes mac_lock is acquired */
256static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
257{
258 unsigned int temp;
259
260 SMSC_ASSERT_MAC_LOCK(pdata);
261
262 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
263 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
264 SMSC_WARNING(HW, "MAC busy at entry");
265 return 0xFFFFFFFF;
266 }
267
268 /* Send the MAC cmd */
269 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
270 MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
271
272 /* Workaround for hardware read-after-write restriction */
273 temp = smsc911x_reg_read(pdata, BYTE_TEST);
274
275 /* Wait for the read to complete */
276 if (likely(smsc911x_mac_complete(pdata) == 0))
277 return smsc911x_reg_read(pdata, MAC_CSR_DATA);
278
279 SMSC_WARNING(HW, "MAC busy after read");
280 return 0xFFFFFFFF;
281}
282
283/* Set a mac register, mac_lock must be acquired before calling */
284static void smsc911x_mac_write(struct smsc911x_data *pdata,
285 unsigned int offset, u32 val)
286{
287 unsigned int temp;
288
289 SMSC_ASSERT_MAC_LOCK(pdata);
290
291 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
292 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
293 SMSC_WARNING(HW,
294 "smsc911x_mac_write failed, MAC busy at entry");
295 return;
296 }
297
298 /* Send data to write */
299 smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
300
301 /* Write the actual data */
302 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
303 MAC_CSR_CMD_CSR_BUSY_));
304
305 /* Workaround for hardware read-after-write restriction */
306 temp = smsc911x_reg_read(pdata, BYTE_TEST);
307
308 /* Wait for the write to complete */
309 if (likely(smsc911x_mac_complete(pdata) == 0))
310 return;
311
312 SMSC_WARNING(HW,
313 "smsc911x_mac_write failed, MAC busy after write");
314}
315
316/* Get a phy register */
317static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
318{
319 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
320 unsigned long flags;
321 unsigned int addr;
322 int i, reg;
323
324 spin_lock_irqsave(&pdata->mac_lock, flags);
325
326 /* Confirm MII not busy */
327 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
328 SMSC_WARNING(HW,
329 "MII is busy in smsc911x_mii_read???");
330 reg = -EIO;
331 goto out;
332 }
333
334 /* Set the address, index & direction (read from PHY) */
335 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
336 smsc911x_mac_write(pdata, MII_ACC, addr);
337
338 /* Wait for read to complete w/ timeout */
339 for (i = 0; i < 100; i++)
340 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
341 reg = smsc911x_mac_read(pdata, MII_DATA);
342 goto out;
343 }
344
150899d2 345 SMSC_WARNING(HW, "Timed out waiting for MII read to finish");
fd9abb3d
SG		 346 reg = -EIO;
347
348out:
349 spin_unlock_irqrestore(&pdata->mac_lock, flags);
350 return reg;
351}
352
353/* Set a phy register */
354static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
355 u16 val)
356{
357 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
358 unsigned long flags;
359 unsigned int addr;
360 int i, reg;
361
362 spin_lock_irqsave(&pdata->mac_lock, flags);
363
364 /* Confirm MII not busy */
365 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
366 SMSC_WARNING(HW,
367 "MII is busy in smsc911x_mii_write???");
368 reg = -EIO;
369 goto out;
370 }
371
372 /* Put the data to write in the MAC */
373 smsc911x_mac_write(pdata, MII_DATA, val);
374
375 /* Set the address, index & direction (write to PHY) */
376 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
377 MII_ACC_MII_WRITE_;
378 smsc911x_mac_write(pdata, MII_ACC, addr);
379
380 /* Wait for write to complete w/ timeout */
381 for (i = 0; i < 100; i++)
382 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
383 reg = 0;
384 goto out;
385 }
386
387 SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
388 reg = -EIO;
389
390out:
391 spin_unlock_irqrestore(&pdata->mac_lock, flags);
392 return reg;
393}
394
d23f028a
SG		 395/* Switch to external phy. Assumes tx and rx are stopped. */
396static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
fd9abb3d
SG		 397{
398 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
399
d23f028a
SG		 400 /* Disable phy clocks to the MAC */
401 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
402 hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
403 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
404 udelay(10); /* Enough time for clocks to stop */
fd9abb3d 405
d23f028a
SG		 406 /* Switch to external phy */
407 hwcfg |= HW_CFG_EXT_PHY_EN_;
408 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
fd9abb3d 409
d23f028a
SG		 410 /* Enable phy clocks to the MAC */
411 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
412 hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
413 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
414 udelay(10); /* Enough time for clocks to restart */
fd9abb3d 415
d23f028a
SG		 416 hwcfg |= HW_CFG_SMI_SEL_;
417 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
418}
fd9abb3d 419
d23f028a
SG		 420/* Autodetects and enables external phy if present on supported chips.
421 * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
422 * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
423static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
424{
425 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
fd9abb3d 426
d23f028a
SG		 427 if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
428 SMSC_TRACE(HW, "Forcing internal PHY");
429 pdata->using_extphy = 0;
430 } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
431 SMSC_TRACE(HW, "Forcing external PHY");
432 smsc911x_phy_enable_external(pdata);
433 pdata->using_extphy = 1;
434 } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
435 SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET set, using external PHY");
436 smsc911x_phy_enable_external(pdata);
fd9abb3d
SG		 437 pdata->using_extphy = 1;
438 } else {
d23f028a
SG		 439 SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET clear, using internal PHY");
440 pdata->using_extphy = 0;
fd9abb3d 441 }
fd9abb3d
SG		 442}
443
444/* Fetches a tx status out of the status fifo */
445static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
446{
447 unsigned int result =
448 smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
449
450 if (result != 0)
451 result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
452
453 return result;
454}
455
456/* Fetches the next rx status */
457static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
458{
459 unsigned int result =
460 smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
461
462 if (result != 0)
463 result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
464
465 return result;
466}
467
468#ifdef USE_PHY_WORK_AROUND
469static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
470{
471 unsigned int tries;
472 u32 wrsz;
473 u32 rdsz;
474 ulong bufp;
475
476 for (tries = 0; tries < 10; tries++) {
477 unsigned int txcmd_a;
478 unsigned int txcmd_b;
479 unsigned int status;
480 unsigned int pktlength;
481 unsigned int i;
482
483 /* Zero-out rx packet memory */
484 memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
485
486 /* Write tx packet to 118 */
487 txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
488 txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
489 txcmd_a |= MIN_PACKET_SIZE;
490
491 txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
492
493 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
494 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
495
496 bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
497 wrsz = MIN_PACKET_SIZE + 3;
498 wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
499 wrsz >>= 2;
500
501 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
502
503 /* Wait till transmit is done */
504 i = 60;
505 do {
506 udelay(5);
507 status = smsc911x_tx_get_txstatus(pdata);
508 } while ((i--) && (!status));
509
510 if (!status) {
511 SMSC_WARNING(HW, "Failed to transmit "
512 "during loopback test");
513 continue;
514 }
515 if (status & TX_STS_ES_) {
516 SMSC_WARNING(HW, "Transmit encountered "
517 "errors during loopback test");
518 continue;
519 }
520
521 /* Wait till receive is done */
522 i = 60;
523 do {
524 udelay(5);
525 status = smsc911x_rx_get_rxstatus(pdata);
526 } while ((i--) && (!status));
527
528 if (!status) {
529 SMSC_WARNING(HW,
530 "Failed to receive during loopback test");
531 continue;
532 }
533 if (status & RX_STS_ES_) {
534 SMSC_WARNING(HW, "Receive encountered "
535 "errors during loopback test");
536 continue;
537 }
538
539 pktlength = ((status & 0x3FFF0000UL) >> 16);
540 bufp = (ulong)pdata->loopback_rx_pkt;
541 rdsz = pktlength + 3;
542 rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
543 rdsz >>= 2;
544
545 smsc911x_rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
546
547 if (pktlength != (MIN_PACKET_SIZE + 4)) {
548 SMSC_WARNING(HW, "Unexpected packet size "
549 "during loop back test, size=%d, will retry",
550 pktlength);
551 } else {
552 unsigned int j;
553 int mismatch = 0;
554 for (j = 0; j < MIN_PACKET_SIZE; j++) {
555 if (pdata->loopback_tx_pkt[j]
556 != pdata->loopback_rx_pkt[j]) {
557 mismatch = 1;
558 break;
559 }
560 }
561 if (!mismatch) {
562 SMSC_TRACE(HW, "Successfully verified "
563 "loopback packet");
564 return 0;
565 } else {
566 SMSC_WARNING(HW, "Data mismatch "
567 "during loop back test, will retry");
568 }
569 }
570 }
571
572 return -EIO;
573}
574
575static int smsc911x_phy_reset(struct smsc911x_data *pdata)
576{
577 struct phy_device *phy_dev = pdata->phy_dev;
578 unsigned int temp;
579 unsigned int i = 100000;
580
581 BUG_ON(!phy_dev);
582 BUG_ON(!phy_dev->bus);
583
584 SMSC_TRACE(HW, "Performing PHY BCR Reset");
585 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
586 do {
587 msleep(1);
588 temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
589 MII_BMCR);
590 } while ((i--) && (temp & BMCR_RESET));
591
592 if (temp & BMCR_RESET) {
593 SMSC_WARNING(HW, "PHY reset failed to complete.");
594 return -EIO;
595 }
596 /* Extra delay required because the phy may not be completed with
597 * its reset when BMCR_RESET is cleared. Specs say 256 uS is
598 * enough delay but using 1ms here to be safe */
599 msleep(1);
600
601 return 0;
602}
603
604static int smsc911x_phy_loopbacktest(struct net_device *dev)
605{
606 struct smsc911x_data *pdata = netdev_priv(dev);
607 struct phy_device *phy_dev = pdata->phy_dev;
608 int result = -EIO;
609 unsigned int i, val;
610 unsigned long flags;
611
612 /* Initialise tx packet using broadcast destination address */
613 memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
614
615 /* Use incrementing source address */
616 for (i = 6; i < 12; i++)
617 pdata->loopback_tx_pkt[i] = (char)i;
618
619 /* Set length type field */
620 pdata->loopback_tx_pkt[12] = 0x00;
621 pdata->loopback_tx_pkt[13] = 0x00;
622
623 for (i = 14; i < MIN_PACKET_SIZE; i++)
624 pdata->loopback_tx_pkt[i] = (char)i;
625
626 val = smsc911x_reg_read(pdata, HW_CFG);
627 val &= HW_CFG_TX_FIF_SZ_;
628 val |= HW_CFG_SF_;
629 smsc911x_reg_write(pdata, HW_CFG, val);
630
631 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
632 smsc911x_reg_write(pdata, RX_CFG,
633 (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
634
635 for (i = 0; i < 10; i++) {
636 /* Set PHY to 10/FD, no ANEG, and loopback mode */
637 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
638 BMCR_LOOPBACK | BMCR_FULLDPLX);
639
640 /* Enable MAC tx/rx, FD */
641 spin_lock_irqsave(&pdata->mac_lock, flags);
642 smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
643 | MAC_CR_TXEN_ | MAC_CR_RXEN_);
644 spin_unlock_irqrestore(&pdata->mac_lock, flags);
645
646 if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
647 result = 0;
648 break;
649 }
650 pdata->resetcount++;
651
652 /* Disable MAC rx */
653 spin_lock_irqsave(&pdata->mac_lock, flags);
654 smsc911x_mac_write(pdata, MAC_CR, 0);
655 spin_unlock_irqrestore(&pdata->mac_lock, flags);
656
657 smsc911x_phy_reset(pdata);
658 }
659
660 /* Disable MAC */
661 spin_lock_irqsave(&pdata->mac_lock, flags);
662 smsc911x_mac_write(pdata, MAC_CR, 0);
663 spin_unlock_irqrestore(&pdata->mac_lock, flags);
664
665 /* Cancel PHY loopback mode */
666 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
667
668 smsc911x_reg_write(pdata, TX_CFG, 0);
669 smsc911x_reg_write(pdata, RX_CFG, 0);
670
671 return result;
672}
673#endif /* USE_PHY_WORK_AROUND */
674
fd9abb3d
SG		 675static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
676{
677 struct phy_device *phy_dev = pdata->phy_dev;
678 u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
679 u32 flow;
680 unsigned long flags;
681
682 if (phy_dev->duplex == DUPLEX_FULL) {
683 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
684 u16 rmtadv = phy_read(phy_dev, MII_LPA);
bc02ff95 685 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
fd9abb3d
SG		 686
687 if (cap & FLOW_CTRL_RX)
688 flow = 0xFFFF0002;
689 else
690 flow = 0;
691
692 if (cap & FLOW_CTRL_TX)
693 afc |= 0xF;
694 else
695 afc &= ~0xF;
696
697 SMSC_TRACE(HW, "rx pause %s, tx pause %s",
698 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
699 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
700 } else {
701 SMSC_TRACE(HW, "half duplex");
702 flow = 0;
703 afc |= 0xF;
704 }
705
706 spin_lock_irqsave(&pdata->mac_lock, flags);
707 smsc911x_mac_write(pdata, FLOW, flow);
708 spin_unlock_irqrestore(&pdata->mac_lock, flags);
709
710 smsc911x_reg_write(pdata, AFC_CFG, afc);
711}
712
713/* Update link mode if anything has changed. Called periodically when the
714 * PHY is in polling mode, even if nothing has changed. */
715static void smsc911x_phy_adjust_link(struct net_device *dev)
716{
717 struct smsc911x_data *pdata = netdev_priv(dev);
718 struct phy_device *phy_dev = pdata->phy_dev;
719 unsigned long flags;
720 int carrier;
721
722 if (phy_dev->duplex != pdata->last_duplex) {
723 unsigned int mac_cr;
724 SMSC_TRACE(HW, "duplex state has changed");
725
726 spin_lock_irqsave(&pdata->mac_lock, flags);
727 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
728 if (phy_dev->duplex) {
729 SMSC_TRACE(HW,
730 "configuring for full duplex mode");
731 mac_cr |= MAC_CR_FDPX_;
732 } else {
733 SMSC_TRACE(HW,
734 "configuring for half duplex mode");
735 mac_cr &= ~MAC_CR_FDPX_;
736 }
737 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
738 spin_unlock_irqrestore(&pdata->mac_lock, flags);
739
740 smsc911x_phy_update_flowcontrol(pdata);
741 pdata->last_duplex = phy_dev->duplex;
742 }
743
744 carrier = netif_carrier_ok(dev);
745 if (carrier != pdata->last_carrier) {
746 SMSC_TRACE(HW, "carrier state has changed");
747 if (carrier) {
748 SMSC_TRACE(HW, "configuring for carrier OK");
749 if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
750 (!pdata->using_extphy)) {
88393161 751 /* Restore original GPIO configuration */
fd9abb3d
SG		 752 pdata->gpio_setting = pdata->gpio_orig_setting;
753 smsc911x_reg_write(pdata, GPIO_CFG,
754 pdata->gpio_setting);
755 }
756 } else {
757 SMSC_TRACE(HW, "configuring for no carrier");
758 /* Check global setting that LED1
759 * usage is 10/100 indicator */
760 pdata->gpio_setting = smsc911x_reg_read(pdata,
761 GPIO_CFG);
8e95a202
JP		 762 if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
763 (!pdata->using_extphy)) {
fd9abb3d 764 /* Force 10/100 LED off, after saving
88393161 765 * original GPIO configuration */
fd9abb3d
SG		 766 pdata->gpio_orig_setting = pdata->gpio_setting;
767
768 pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
769 pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
770 | GPIO_CFG_GPIODIR0_
771 | GPIO_CFG_GPIOD0_);
772 smsc911x_reg_write(pdata, GPIO_CFG,
773 pdata->gpio_setting);
774 }
775 }
776 pdata->last_carrier = carrier;
777 }
778}
779
780static int smsc911x_mii_probe(struct net_device *dev)
781{
782 struct smsc911x_data *pdata = netdev_priv(dev);
783 struct phy_device *phydev = NULL;
e4a474f8 784 int ret;
fd9abb3d
SG		 785
786 /* find the first phy */
e4a474f8 787 phydev = phy_find_first(pdata->mii_bus);
fd9abb3d
SG		 788 if (!phydev) {
789 pr_err("%s: no PHY found\n", dev->name);
790 return -ENODEV;
791 }
792
e4a474f8 793 SMSC_TRACE(PROBE, "PHY %d: addr %d, phy_id 0x%08X",
794 phy_addr, phydev->addr, phydev->phy_id);
795
796 ret = phy_connect_direct(dev, phydev,
797 &smsc911x_phy_adjust_link, 0,
798 pdata->config.phy_interface);
fd9abb3d 799
e4a474f8 800 if (ret) {
fd9abb3d 801 pr_err("%s: Could not attach to PHY\n", dev->name);
e4a474f8 802 return ret;
fd9abb3d
SG		 803 }
804
805 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
db1d7bf7
KS		 806 dev->name, phydev->drv->name,
807 dev_name(&phydev->dev), phydev->irq);
fd9abb3d
SG		 808
809 /* mask with MAC supported features */
810 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
811 SUPPORTED_Asym_Pause);
812 phydev->advertising = phydev->supported;
813
814 pdata->phy_dev = phydev;
815 pdata->last_duplex = -1;
816 pdata->last_carrier = -1;
817
818#ifdef USE_PHY_WORK_AROUND
819 if (smsc911x_phy_loopbacktest(dev) < 0) {
820 SMSC_WARNING(HW, "Failed Loop Back Test");
821 return -ENODEV;
822 }
823 SMSC_TRACE(HW, "Passed Loop Back Test");
824#endif /* USE_PHY_WORK_AROUND */
825
af901ca1 826 SMSC_TRACE(HW, "phy initialised successfully");
fd9abb3d
SG		 827 return 0;
828}
829
830static int __devinit smsc911x_mii_init(struct platform_device *pdev,
831 struct net_device *dev)
832{
833 struct smsc911x_data *pdata = netdev_priv(dev);
834 int err = -ENXIO, i;
835
836 pdata->mii_bus = mdiobus_alloc();
837 if (!pdata->mii_bus) {
838 err = -ENOMEM;
839 goto err_out_1;
840 }
841
842 pdata->mii_bus->name = SMSC_MDIONAME;
843 snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
844 pdata->mii_bus->priv = pdata;
845 pdata->mii_bus->read = smsc911x_mii_read;
846 pdata->mii_bus->write = smsc911x_mii_write;
847 pdata->mii_bus->irq = pdata->phy_irq;
848 for (i = 0; i < PHY_MAX_ADDR; ++i)
849 pdata->mii_bus->irq[i] = PHY_POLL;
850
851 pdata->mii_bus->parent = &pdev->dev;
fd9abb3d 852
fd9abb3d
SG		 853 switch (pdata->idrev & 0xFFFF0000) {
854 case 0x01170000:
855 case 0x01150000:
856 case 0x117A0000:
857 case 0x115A0000:
858 /* External PHY supported, try to autodetect */
d23f028a 859 smsc911x_phy_initialise_external(pdata);
fd9abb3d
SG		 860 break;
861 default:
862 SMSC_TRACE(HW, "External PHY is not supported, "
863 "using internal PHY");
d23f028a 864 pdata->using_extphy = 0;
fd9abb3d
SG		 865 break;
866 }
867
868 if (!pdata->using_extphy) {
869 /* Mask all PHYs except ID 1 (internal) */
870 pdata->mii_bus->phy_mask = ~(1 << 1);
871 }
872
873 if (mdiobus_register(pdata->mii_bus)) {
874 SMSC_WARNING(PROBE, "Error registering mii bus");
875 goto err_out_free_bus_2;
876 }
877
878 if (smsc911x_mii_probe(dev) < 0) {
879 SMSC_WARNING(PROBE, "Error registering mii bus");
880 goto err_out_unregister_bus_3;
881 }
882
883 return 0;
884
885err_out_unregister_bus_3:
886 mdiobus_unregister(pdata->mii_bus);
887err_out_free_bus_2:
888 mdiobus_free(pdata->mii_bus);
889err_out_1:
890 return err;
891}
892
893/* Gets the number of tx statuses in the fifo */
894static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
895{
896 return (smsc911x_reg_read(pdata, TX_FIFO_INF)
897 & TX_FIFO_INF_TSUSED_) >> 16;
898}
899
900/* Reads tx statuses and increments counters where necessary */
901static void smsc911x_tx_update_txcounters(struct net_device *dev)
902{
903 struct smsc911x_data *pdata = netdev_priv(dev);
904 unsigned int tx_stat;
905
906 while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
907 if (unlikely(tx_stat & 0x80000000)) {
908 /* In this driver the packet tag is used as the packet
909 * length. Since a packet length can never reach the
910 * size of 0x8000, this bit is reserved. It is worth
911 * noting that the "reserved bit" in the warning above
912 * does not reference a hardware defined reserved bit
913 * but rather a driver defined one.
914 */
915 SMSC_WARNING(HW,
916 "Packet tag reserved bit is high");
917 } else {
785b6f97 918 if (unlikely(tx_stat & TX_STS_ES_)) {
fd9abb3d
SG		 919 dev->stats.tx_errors++;
920 } else {
921 dev->stats.tx_packets++;
922 dev->stats.tx_bytes += (tx_stat >> 16);
923 }
785b6f97 924 if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
fd9abb3d
SG		 925 dev->stats.collisions += 16;
926 dev->stats.tx_aborted_errors += 1;
927 } else {
928 dev->stats.collisions +=
929 ((tx_stat >> 3) & 0xF);
930 }
785b6f97 931 if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
fd9abb3d 932 dev->stats.tx_carrier_errors += 1;
785b6f97 933 if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
fd9abb3d
SG		 934 dev->stats.collisions++;
935 dev->stats.tx_aborted_errors++;
936 }
937 }
938 }
939}
940
941/* Increments the Rx error counters */
942static void
943smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
944{
945 int crc_err = 0;
946
785b6f97 947 if (unlikely(rxstat & RX_STS_ES_)) {
fd9abb3d 948 dev->stats.rx_errors++;
785b6f97 949 if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
fd9abb3d
SG		 950 dev->stats.rx_crc_errors++;
951 crc_err = 1;
952 }
953 }
954 if (likely(!crc_err)) {
785b6f97
SG		 955 if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
956 (rxstat & RX_STS_LENGTH_ERR_)))
fd9abb3d 957 dev->stats.rx_length_errors++;
fd9abb3d
SG		 958 if (rxstat & RX_STS_MCAST_)
959 dev->stats.multicast++;
960 }
961}
962
963/* Quickly dumps bad packets */
964static void
965smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
966{
967 unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
968
969 if (likely(pktwords >= 4)) {
970 unsigned int timeout = 500;
971 unsigned int val;
972 smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
973 do {
974 udelay(1);
975 val = smsc911x_reg_read(pdata, RX_DP_CTRL);
8dacd548 976 } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
fd9abb3d
SG		 977
978 if (unlikely(timeout == 0))
979 SMSC_WARNING(HW, "Timed out waiting for "
980 "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
981 } else {
982 unsigned int temp;
983 while (pktwords--)
984 temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
985 }
986}
987
988/* NAPI poll function */
989static int smsc911x_poll(struct napi_struct *napi, int budget)
990{
991 struct smsc911x_data *pdata =
992 container_of(napi, struct smsc911x_data, napi);
993 struct net_device *dev = pdata->dev;
994 int npackets = 0;
995
f88c5b98 996 while (npackets < budget) {
fd9abb3d
SG		 997 unsigned int pktlength;
998 unsigned int pktwords;
999 struct sk_buff *skb;
1000 unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
1001
1002 if (!rxstat) {
1003 unsigned int temp;
1004 /* We processed all packets available. Tell NAPI it can
1005 * stop polling then re-enable rx interrupts */
1006 smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
288379f0 1007 napi_complete(napi);
fd9abb3d
SG		 1008 temp = smsc911x_reg_read(pdata, INT_EN);
1009 temp |= INT_EN_RSFL_EN_;
1010 smsc911x_reg_write(pdata, INT_EN, temp);
1011 break;
1012 }
1013
1014 /* Count packet for NAPI scheduling, even if it has an error.
1015 * Error packets still require cycles to discard */
1016 npackets++;
1017
1018 pktlength = ((rxstat & 0x3FFF0000) >> 16);
1019 pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
1020 smsc911x_rx_counterrors(dev, rxstat);
1021
1022 if (unlikely(rxstat & RX_STS_ES_)) {
1023 SMSC_WARNING(RX_ERR,
1024 "Discarding packet with error bit set");
1025 /* Packet has an error, discard it and continue with
1026 * the next */
1027 smsc911x_rx_fastforward(pdata, pktwords);
1028 dev->stats.rx_dropped++;
1029 continue;
1030 }
1031
1032 skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
1033 if (unlikely(!skb)) {
1034 SMSC_WARNING(RX_ERR,
1035 "Unable to allocate skb for rx packet");
1036 /* Drop the packet and stop this polling iteration */
1037 smsc911x_rx_fastforward(pdata, pktwords);
1038 dev->stats.rx_dropped++;
1039 break;
1040 }
1041
1042 skb->data = skb->head;
1043 skb_reset_tail_pointer(skb);
1044
1045 /* Align IP on 16B boundary */
1046 skb_reserve(skb, NET_IP_ALIGN);
1047 skb_put(skb, pktlength - 4);
1048 smsc911x_rx_readfifo(pdata, (unsigned int *)skb->head,
1049 pktwords);
1050 skb->protocol = eth_type_trans(skb, dev);
bc8acf2c 1051 skb_checksum_none_assert(skb);
fd9abb3d
SG		 1052 netif_receive_skb(skb);
1053
1054 /* Update counters */
1055 dev->stats.rx_packets++;
1056 dev->stats.rx_bytes += (pktlength - 4);
fd9abb3d
SG		 1057 }
1058
1059 /* Return total received packets */
1060 return npackets;
1061}
1062
1063/* Returns hash bit number for given MAC address
1064 * Example:
1065 * 01 00 5E 00 00 01 -> returns bit number 31 */
1066static unsigned int smsc911x_hash(char addr[ETH_ALEN])
1067{
1068 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
1069}
1070
1071static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
1072{
1073 /* Performs the multicast & mac_cr update. This is called when
1074 * safe on the current hardware, and with the mac_lock held */
1075 unsigned int mac_cr;
1076
1077 SMSC_ASSERT_MAC_LOCK(pdata);
1078
1079 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1080 mac_cr |= pdata->set_bits_mask;
1081 mac_cr &= ~(pdata->clear_bits_mask);
1082 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1083 smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
1084 smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
1085 SMSC_TRACE(HW, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
1086 mac_cr, pdata->hashhi, pdata->hashlo);
1087}
1088
1089static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
1090{
1091 unsigned int mac_cr;
1092
1093 /* This function is only called for older LAN911x devices
1094 * (revA or revB), where MAC_CR, HASHH and HASHL should not
1095 * be modified during Rx - newer devices immediately update the
1096 * registers.
1097 *
1098 * This is called from interrupt context */
1099
1100 spin_lock(&pdata->mac_lock);
1101
1102 /* Check Rx has stopped */
1103 if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
1104 SMSC_WARNING(DRV, "Rx not stopped");
1105
1106 /* Perform the update - safe to do now Rx has stopped */
1107 smsc911x_rx_multicast_update(pdata);
1108
1109 /* Re-enable Rx */
1110 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1111 mac_cr |= MAC_CR_RXEN_;
1112 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1113
1114 pdata->multicast_update_pending = 0;
1115
1116 spin_unlock(&pdata->mac_lock);
1117}
1118
1119static int smsc911x_soft_reset(struct smsc911x_data *pdata)
1120{
1121 unsigned int timeout;
1122 unsigned int temp;
1123
1124 /* Reset the LAN911x */
1125 smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
1126 timeout = 10;
1127 do {
1128 udelay(10);
1129 temp = smsc911x_reg_read(pdata, HW_CFG);
1130 } while ((--timeout) && (temp & HW_CFG_SRST_));
1131
1132 if (unlikely(temp & HW_CFG_SRST_)) {
1133 SMSC_WARNING(DRV, "Failed to complete reset");
1134 return -EIO;
1135 }
1136 return 0;
1137}
1138
1139/* Sets the device MAC address to dev_addr, called with mac_lock held */
1140static void
225ddf49 1141smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
fd9abb3d
SG		 1142{
1143 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
1144 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
1145 (dev_addr[1] << 8) | dev_addr[0];
1146
1147 SMSC_ASSERT_MAC_LOCK(pdata);
1148
1149 smsc911x_mac_write(pdata, ADDRH, mac_high16);
1150 smsc911x_mac_write(pdata, ADDRL, mac_low32);
1151}
1152
1153static int smsc911x_open(struct net_device *dev)
1154{
1155 struct smsc911x_data *pdata = netdev_priv(dev);
1156 unsigned int timeout;
1157 unsigned int temp;
1158 unsigned int intcfg;
1159
1160 /* if the phy is not yet registered, retry later*/
1161 if (!pdata->phy_dev) {
1162 SMSC_WARNING(HW, "phy_dev is NULL");
1163 return -EAGAIN;
1164 }
1165
1166 if (!is_valid_ether_addr(dev->dev_addr)) {
1167 SMSC_WARNING(HW, "dev_addr is not a valid MAC address");
1168 return -EADDRNOTAVAIL;
1169 }
1170
1171 /* Reset the LAN911x */
1172 if (smsc911x_soft_reset(pdata)) {
1173 SMSC_WARNING(HW, "soft reset failed");
1174 return -EIO;
1175 }
1176
1177 smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
1178 smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
1179
1180 /* Make sure EEPROM has finished loading before setting GPIO_CFG */
1181 timeout = 50;
f7efb6cc
SG		 1182 while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
1183 --timeout) {
fd9abb3d
SG		 1184 udelay(10);
1185 }
1186
1187 if (unlikely(timeout == 0))
1188 SMSC_WARNING(IFUP,
1189 "Timed out waiting for EEPROM busy bit to clear");
1190
1191 smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
1192
1193 /* The soft reset above cleared the device's MAC address,
1194 * restore it from local copy (set in probe) */
1195 spin_lock_irq(&pdata->mac_lock);
225ddf49 1196 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 1197 spin_unlock_irq(&pdata->mac_lock);
1198
1199 /* Initialise irqs, but leave all sources disabled */
1200 smsc911x_reg_write(pdata, INT_EN, 0);
1201 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
1202
1203 /* Set interrupt deassertion to 100uS */
1204 intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
1205
2107fb8b 1206 if (pdata->config.irq_polarity) {
fd9abb3d
SG		 1207 SMSC_TRACE(IFUP, "irq polarity: active high");
1208 intcfg |= INT_CFG_IRQ_POL_;
1209 } else {
1210 SMSC_TRACE(IFUP, "irq polarity: active low");
1211 }
1212
2107fb8b 1213 if (pdata->config.irq_type) {
fd9abb3d
SG		 1214 SMSC_TRACE(IFUP, "irq type: push-pull");
1215 intcfg |= INT_CFG_IRQ_TYPE_;
1216 } else {
1217 SMSC_TRACE(IFUP, "irq type: open drain");
1218 }
1219
1220 smsc911x_reg_write(pdata, INT_CFG, intcfg);
1221
1222 SMSC_TRACE(IFUP, "Testing irq handler using IRQ %d", dev->irq);
1223 pdata->software_irq_signal = 0;
1224 smp_wmb();
1225
1226 temp = smsc911x_reg_read(pdata, INT_EN);
1227 temp |= INT_EN_SW_INT_EN_;
1228 smsc911x_reg_write(pdata, INT_EN, temp);
1229
1230 timeout = 1000;
1231 while (timeout--) {
1232 if (pdata->software_irq_signal)
1233 break;
1234 msleep(1);
1235 }
1236
1237 if (!pdata->software_irq_signal) {
1238 dev_warn(&dev->dev, "ISR failed signaling test (IRQ %d)\n",
1239 dev->irq);
1240 return -ENODEV;
1241 }
1242 SMSC_TRACE(IFUP, "IRQ handler passed test using IRQ %d", dev->irq);
1243
1244 dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
1245 (unsigned long)pdata->ioaddr, dev->irq);
1246
44c1d6f9
SG		 1247 /* Reset the last known duplex and carrier */
1248 pdata->last_duplex = -1;
1249 pdata->last_carrier = -1;
1250
fd9abb3d
SG		 1251 /* Bring the PHY up */
1252 phy_start(pdata->phy_dev);
1253
1254 temp = smsc911x_reg_read(pdata, HW_CFG);
1255 /* Preserve TX FIFO size and external PHY configuration */
1256 temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
1257 temp |= HW_CFG_SF_;
1258 smsc911x_reg_write(pdata, HW_CFG, temp);
1259
1260 temp = smsc911x_reg_read(pdata, FIFO_INT);
1261 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1262 temp &= ~(FIFO_INT_RX_STS_LEVEL_);
1263 smsc911x_reg_write(pdata, FIFO_INT, temp);
1264
1265 /* set RX Data offset to 2 bytes for alignment */
1266 smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
1267
1268 /* enable NAPI polling before enabling RX interrupts */
1269 napi_enable(&pdata->napi);
1270
1271 temp = smsc911x_reg_read(pdata, INT_EN);
1373c0fd 1272 temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
fd9abb3d
SG		 1273 smsc911x_reg_write(pdata, INT_EN, temp);
1274
1275 spin_lock_irq(&pdata->mac_lock);
1276 temp = smsc911x_mac_read(pdata, MAC_CR);
1277 temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
1278 smsc911x_mac_write(pdata, MAC_CR, temp);
1279 spin_unlock_irq(&pdata->mac_lock);
1280
1281 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
1282
1283 netif_start_queue(dev);
1284 return 0;
1285}
1286
1287/* Entry point for stopping the interface */
1288static int smsc911x_stop(struct net_device *dev)
1289{
1290 struct smsc911x_data *pdata = netdev_priv(dev);
1291 unsigned int temp;
1292
fd9abb3d
SG		 1293 /* Disable all device interrupts */
1294 temp = smsc911x_reg_read(pdata, INT_CFG);
1295 temp &= ~INT_CFG_IRQ_EN_;
1296 smsc911x_reg_write(pdata, INT_CFG, temp);
1297
1298 /* Stop Tx and Rx polling */
1299 netif_stop_queue(dev);
1300 napi_disable(&pdata->napi);
1301
1302 /* At this point all Rx and Tx activity is stopped */
1303 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1304 smsc911x_tx_update_txcounters(dev);
1305
1306 /* Bring the PHY down */
dd045193
SG		 1307 if (pdata->phy_dev)
1308 phy_stop(pdata->phy_dev);
fd9abb3d
SG		 1309
1310 SMSC_TRACE(IFDOWN, "Interface stopped");
1311 return 0;
1312}
1313
1314/* Entry point for transmitting a packet */
1315static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1316{
1317 struct smsc911x_data *pdata = netdev_priv(dev);
1318 unsigned int freespace;
1319 unsigned int tx_cmd_a;
1320 unsigned int tx_cmd_b;
1321 unsigned int temp;
1322 u32 wrsz;
1323 ulong bufp;
1324
1325 freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
1326
1327 if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
1328 SMSC_WARNING(TX_ERR,
1329 "Tx data fifo low, space available: %d", freespace);
1330
1331 /* Word alignment adjustment */
1332 tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
1333 tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
1334 tx_cmd_a |= (unsigned int)skb->len;
1335
1336 tx_cmd_b = ((unsigned int)skb->len) << 16;
1337 tx_cmd_b |= (unsigned int)skb->len;
1338
1339 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
1340 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
1341
1342 bufp = (ulong)skb->data & (~0x3);
1343 wrsz = (u32)skb->len + 3;
1344 wrsz += (u32)((ulong)skb->data & 0x3);
1345 wrsz >>= 2;
1346
1347 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
1348 freespace -= (skb->len + 32);
1349 dev_kfree_skb(skb);
fd9abb3d
SG		 1350
1351 if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
1352 smsc911x_tx_update_txcounters(dev);
1353
1354 if (freespace < TX_FIFO_LOW_THRESHOLD) {
1355 netif_stop_queue(dev);
1356 temp = smsc911x_reg_read(pdata, FIFO_INT);
1357 temp &= 0x00FFFFFF;
1358 temp |= 0x32000000;
1359 smsc911x_reg_write(pdata, FIFO_INT, temp);
1360 }
1361
1362 return NETDEV_TX_OK;
1363}
1364
1365/* Entry point for getting status counters */
1366static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
1367{
1368 struct smsc911x_data *pdata = netdev_priv(dev);
1369 smsc911x_tx_update_txcounters(dev);
1370 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1371 return &dev->stats;
1372}
1373
1374/* Entry point for setting addressing modes */
1375static void smsc911x_set_multicast_list(struct net_device *dev)
1376{
1377 struct smsc911x_data *pdata = netdev_priv(dev);
1378 unsigned long flags;
1379
1380 if (dev->flags & IFF_PROMISC) {
1381 /* Enabling promiscuous mode */
1382 pdata->set_bits_mask = MAC_CR_PRMS_;
1383 pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1384 pdata->hashhi = 0;
1385 pdata->hashlo = 0;
1386 } else if (dev->flags & IFF_ALLMULTI) {
1387 /* Enabling all multicast mode */
1388 pdata->set_bits_mask = MAC_CR_MCPAS_;
1389 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
1390 pdata->hashhi = 0;
1391 pdata->hashlo = 0;
4cd24eaf 1392 } else if (!netdev_mc_empty(dev)) {
fd9abb3d
SG		 1393 /* Enabling specific multicast addresses */
1394 unsigned int hash_high = 0;
1395 unsigned int hash_low = 0;
22bedad3 1396 struct netdev_hw_addr *ha;
fd9abb3d
SG		 1397
1398 pdata->set_bits_mask = MAC_CR_HPFILT_;
1399 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1400
22bedad3
JP		 1401 netdev_for_each_mc_addr(ha, dev) {
1402 unsigned int bitnum = smsc911x_hash(ha->addr);
2a0d18f9
JP		 1403 unsigned int mask = 0x01 << (bitnum & 0x1F);
1404
1405 if (bitnum & 0x20)
1406 hash_high |= mask;
1407 else
1408 hash_low |= mask;
fd9abb3d 1409 }
fd9abb3d
SG		 1410
1411 pdata->hashhi = hash_high;
1412 pdata->hashlo = hash_low;
1413 } else {
1414 /* Enabling local MAC address only */
1415 pdata->set_bits_mask = 0;
1416 pdata->clear_bits_mask =
1417 (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1418 pdata->hashhi = 0;
1419 pdata->hashlo = 0;
1420 }
1421
1422 spin_lock_irqsave(&pdata->mac_lock, flags);
1423
1424 if (pdata->generation <= 1) {
1425 /* Older hardware revision - cannot change these flags while
1426 * receiving data */
1427 if (!pdata->multicast_update_pending) {
1428 unsigned int temp;
1429 SMSC_TRACE(HW, "scheduling mcast update");
1430 pdata->multicast_update_pending = 1;
1431
1432 /* Request the hardware to stop, then perform the
1433 * update when we get an RX_STOP interrupt */
fd9abb3d
SG		 1434 temp = smsc911x_mac_read(pdata, MAC_CR);
1435 temp &= ~(MAC_CR_RXEN_);
1436 smsc911x_mac_write(pdata, MAC_CR, temp);
1437 } else {
1438 /* There is another update pending, this should now
1439 * use the newer values */
1440 }
1441 } else {
1442 /* Newer hardware revision - can write immediately */
1443 smsc911x_rx_multicast_update(pdata);
1444 }
1445
1446 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1447}
1448
1449static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
1450{
1451 struct net_device *dev = dev_id;
1452 struct smsc911x_data *pdata = netdev_priv(dev);
1453 u32 intsts = smsc911x_reg_read(pdata, INT_STS);
1454 u32 inten = smsc911x_reg_read(pdata, INT_EN);
1455 int serviced = IRQ_NONE;
1456 u32 temp;
1457
1458 if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
1459 temp = smsc911x_reg_read(pdata, INT_EN);
1460 temp &= (~INT_EN_SW_INT_EN_);
1461 smsc911x_reg_write(pdata, INT_EN, temp);
1462 smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
1463 pdata->software_irq_signal = 1;
1464 smp_wmb();
1465 serviced = IRQ_HANDLED;
1466 }
1467
1468 if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
1469 /* Called when there is a multicast update scheduled and
1470 * it is now safe to complete the update */
1471 SMSC_TRACE(INTR, "RX Stop interrupt");
fd9abb3d 1472 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
1373c0fd
SG		 1473 if (pdata->multicast_update_pending)
1474 smsc911x_rx_multicast_update_workaround(pdata);
fd9abb3d
SG		 1475 serviced = IRQ_HANDLED;
1476 }
1477
1478 if (intsts & inten & INT_STS_TDFA_) {
1479 temp = smsc911x_reg_read(pdata, FIFO_INT);
1480 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1481 smsc911x_reg_write(pdata, FIFO_INT, temp);
1482 smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
1483 netif_wake_queue(dev);
1484 serviced = IRQ_HANDLED;
1485 }
1486
1487 if (unlikely(intsts & inten & INT_STS_RXE_)) {
1488 SMSC_TRACE(INTR, "RX Error interrupt");
1489 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
1490 serviced = IRQ_HANDLED;
1491 }
1492
1493 if (likely(intsts & inten & INT_STS_RSFL_)) {
288379f0 1494 if (likely(napi_schedule_prep(&pdata->napi))) {
fd9abb3d
SG		 1495 /* Disable Rx interrupts */
1496 temp = smsc911x_reg_read(pdata, INT_EN);
1497 temp &= (~INT_EN_RSFL_EN_);
1498 smsc911x_reg_write(pdata, INT_EN, temp);
1499 /* Schedule a NAPI poll */
288379f0 1500 __napi_schedule(&pdata->napi);
fd9abb3d
SG		 1501 } else {
1502 SMSC_WARNING(RX_ERR,
288379f0 1503 "napi_schedule_prep failed");
fd9abb3d
SG		 1504 }
1505 serviced = IRQ_HANDLED;
1506 }
1507
1508 return serviced;
1509}
1510
1511#ifdef CONFIG_NET_POLL_CONTROLLER
1757ab2f 1512static void smsc911x_poll_controller(struct net_device *dev)
fd9abb3d
SG		 1513{
1514 disable_irq(dev->irq);
1515 smsc911x_irqhandler(0, dev);
1516 enable_irq(dev->irq);
1517}
1518#endif /* CONFIG_NET_POLL_CONTROLLER */
1519
225ddf49
SG		 1520static int smsc911x_set_mac_address(struct net_device *dev, void *p)
1521{
1522 struct smsc911x_data *pdata = netdev_priv(dev);
1523 struct sockaddr *addr = p;
1524
1525 /* On older hardware revisions we cannot change the mac address
1526 * registers while receiving data. Newer devices can safely change
1527 * this at any time. */
1528 if (pdata->generation <= 1 && netif_running(dev))
1529 return -EBUSY;
1530
1531 if (!is_valid_ether_addr(addr->sa_data))
1532 return -EADDRNOTAVAIL;
1533
1534 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1535
1536 spin_lock_irq(&pdata->mac_lock);
1537 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
1538 spin_unlock_irq(&pdata->mac_lock);
1539
1540 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1541
1542 return 0;
1543}
1544
fd9abb3d
SG		 1545/* Standard ioctls for mii-tool */
1546static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1547{
1548 struct smsc911x_data *pdata = netdev_priv(dev);
1549
1550 if (!netif_running(dev) || !pdata->phy_dev)
1551 return -EINVAL;
1552
28b04113 1553 return phy_mii_ioctl(pdata->phy_dev, ifr, cmd);
fd9abb3d
SG		 1554}
1555
1556static int
1557smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1558{
1559 struct smsc911x_data *pdata = netdev_priv(dev);
1560
1561 cmd->maxtxpkt = 1;
1562 cmd->maxrxpkt = 1;
1563 return phy_ethtool_gset(pdata->phy_dev, cmd);
1564}
1565
1566static int
1567smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1568{
1569 struct smsc911x_data *pdata = netdev_priv(dev);
1570
1571 return phy_ethtool_sset(pdata->phy_dev, cmd);
1572}
1573
1574static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
1575 struct ethtool_drvinfo *info)
1576{
1577 strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
1578 strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
db1d7bf7 1579 strlcpy(info->bus_info, dev_name(dev->dev.parent),
fd9abb3d
SG		 1580 sizeof(info->bus_info));
1581}
1582
1583static int smsc911x_ethtool_nwayreset(struct net_device *dev)
1584{
1585 struct smsc911x_data *pdata = netdev_priv(dev);
1586
1587 return phy_start_aneg(pdata->phy_dev);
1588}
1589
1590static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
1591{
1592 struct smsc911x_data *pdata = netdev_priv(dev);
1593 return pdata->msg_enable;
1594}
1595
1596static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1597{
1598 struct smsc911x_data *pdata = netdev_priv(dev);
1599 pdata->msg_enable = level;
1600}
1601
1602static int smsc911x_ethtool_getregslen(struct net_device *dev)
1603{
1604 return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
1605 sizeof(u32);
1606}
1607
1608static void
1609smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
1610 void *buf)
1611{
1612 struct smsc911x_data *pdata = netdev_priv(dev);
1613 struct phy_device *phy_dev = pdata->phy_dev;
1614 unsigned long flags;
1615 unsigned int i;
1616 unsigned int j = 0;
1617 u32 *data = buf;
1618
1619 regs->version = pdata->idrev;
1620 for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
1621 data[j++] = smsc911x_reg_read(pdata, i);
1622
1623 for (i = MAC_CR; i <= WUCSR; i++) {
1624 spin_lock_irqsave(&pdata->mac_lock, flags);
1625 data[j++] = smsc911x_mac_read(pdata, i);
1626 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1627 }
1628
1629 for (i = 0; i <= 31; i++)
1630 data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
1631}
1632
1633static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
1634{
1635 unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
1636 temp &= ~GPIO_CFG_EEPR_EN_;
1637 smsc911x_reg_write(pdata, GPIO_CFG, temp);
1638 msleep(1);
1639}
1640
1641static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
1642{
1643 int timeout = 100;
1644 u32 e2cmd;
1645
1646 SMSC_TRACE(DRV, "op 0x%08x", op);
1647 if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
1648 SMSC_WARNING(DRV, "Busy at start");
1649 return -EBUSY;
1650 }
1651
1652 e2cmd = op | E2P_CMD_EPC_BUSY_;
1653 smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
1654
1655 do {
1656 msleep(1);
1657 e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
2cf0dbed 1658 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
fd9abb3d
SG		 1659
1660 if (!timeout) {
1661 SMSC_TRACE(DRV, "TIMED OUT");
1662 return -EAGAIN;
1663 }
1664
1665 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
1666 SMSC_TRACE(DRV, "Error occured during eeprom operation");
1667 return -EINVAL;
1668 }
1669
1670 return 0;
1671}
1672
1673static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
1674 u8 address, u8 *data)
1675{
1676 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
1677 int ret;
1678
1679 SMSC_TRACE(DRV, "address 0x%x", address);
1680 ret = smsc911x_eeprom_send_cmd(pdata, op);
1681
1682 if (!ret)
1683 data[address] = smsc911x_reg_read(pdata, E2P_DATA);
1684
1685 return ret;
1686}
1687
1688static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
1689 u8 address, u8 data)
1690{
1691 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
58add9fc 1692 u32 temp;
fd9abb3d
SG		 1693 int ret;
1694
1695 SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
1696 ret = smsc911x_eeprom_send_cmd(pdata, op);
1697
1698 if (!ret) {
1699 op = E2P_CMD_EPC_CMD_WRITE_ | address;
1700 smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
58add9fc
SG		 1701
1702 /* Workaround for hardware read-after-write restriction */
1703 temp = smsc911x_reg_read(pdata, BYTE_TEST);
1704
fd9abb3d
SG		 1705 ret = smsc911x_eeprom_send_cmd(pdata, op);
1706 }
1707
1708 return ret;
1709}
1710
1711static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
1712{
1713 return SMSC911X_EEPROM_SIZE;
1714}
1715
1716static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
1717 struct ethtool_eeprom *eeprom, u8 *data)
1718{
1719 struct smsc911x_data *pdata = netdev_priv(dev);
1720 u8 eeprom_data[SMSC911X_EEPROM_SIZE];
1721 int len;
1722 int i;
1723
1724 smsc911x_eeprom_enable_access(pdata);
1725
1726 len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
1727 for (i = 0; i < len; i++) {
1728 int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
1729 if (ret < 0) {
1730 eeprom->len = 0;
1731 return ret;
1732 }
1733 }
1734
1735 memcpy(data, &eeprom_data[eeprom->offset], len);
1736 eeprom->len = len;
1737 return 0;
1738}
1739
1740static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
1741 struct ethtool_eeprom *eeprom, u8 *data)
1742{
1743 int ret;
1744 struct smsc911x_data *pdata = netdev_priv(dev);
1745
1746 smsc911x_eeprom_enable_access(pdata);
1747 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
1748 ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
1749 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
1750
1751 /* Single byte write, according to man page */
1752 eeprom->len = 1;
1753
1754 return ret;
1755}
1756
cb5b04fe 1757static const struct ethtool_ops smsc911x_ethtool_ops = {
fd9abb3d
SG		 1758 .get_settings = smsc911x_ethtool_getsettings,
1759 .set_settings = smsc911x_ethtool_setsettings,
1760 .get_link = ethtool_op_get_link,
1761 .get_drvinfo = smsc911x_ethtool_getdrvinfo,
1762 .nway_reset = smsc911x_ethtool_nwayreset,
1763 .get_msglevel = smsc911x_ethtool_getmsglevel,
1764 .set_msglevel = smsc911x_ethtool_setmsglevel,
1765 .get_regs_len = smsc911x_ethtool_getregslen,
1766 .get_regs = smsc911x_ethtool_getregs,
1767 .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
1768 .get_eeprom = smsc911x_ethtool_get_eeprom,
1769 .set_eeprom = smsc911x_ethtool_set_eeprom,
1770};
1771
631b7568
SG		 1772static const struct net_device_ops smsc911x_netdev_ops = {
1773 .ndo_open = smsc911x_open,
1774 .ndo_stop = smsc911x_stop,
1775 .ndo_start_xmit = smsc911x_hard_start_xmit,
1776 .ndo_get_stats = smsc911x_get_stats,
1777 .ndo_set_multicast_list = smsc911x_set_multicast_list,
1778 .ndo_do_ioctl = smsc911x_do_ioctl,
635ecaa7 1779 .ndo_change_mtu = eth_change_mtu,
631b7568 1780 .ndo_validate_addr = eth_validate_addr,
225ddf49 1781 .ndo_set_mac_address = smsc911x_set_mac_address,
631b7568
SG		 1782#ifdef CONFIG_NET_POLL_CONTROLLER
1783 .ndo_poll_controller = smsc911x_poll_controller,
1784#endif
1785};
1786
31f45747
SG		 1787/* copies the current mac address from hardware to dev->dev_addr */
1788static void __devinit smsc911x_read_mac_address(struct net_device *dev)
1789{
1790 struct smsc911x_data *pdata = netdev_priv(dev);
1791 u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
1792 u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
1793
1794 dev->dev_addr[0] = (u8)(mac_low32);
1795 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
1796 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
1797 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
1798 dev->dev_addr[4] = (u8)(mac_high16);
1799 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
1800}
1801
fd9abb3d
SG		 1802/* Initializing private device structures, only called from probe */
1803static int __devinit smsc911x_init(struct net_device *dev)
1804{
1805 struct smsc911x_data *pdata = netdev_priv(dev);
1806 unsigned int byte_test;
1807
1808 SMSC_TRACE(PROBE, "Driver Parameters:");
1809 SMSC_TRACE(PROBE, "LAN base: 0x%08lX",
1810 (unsigned long)pdata->ioaddr);
1811 SMSC_TRACE(PROBE, "IRQ: %d", dev->irq);
1812 SMSC_TRACE(PROBE, "PHY will be autodetected.");
1813
fd9abb3d 1814 spin_lock_init(&pdata->dev_lock);
fd9abb3d
SG		 1815
1816 if (pdata->ioaddr == 0) {
1817 SMSC_WARNING(PROBE, "pdata->ioaddr: 0x00000000");
1818 return -ENODEV;
1819 }
1820
1821 /* Check byte ordering */
1822 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1823 SMSC_TRACE(PROBE, "BYTE_TEST: 0x%08X", byte_test);
1824 if (byte_test == 0x43218765) {
1825 SMSC_TRACE(PROBE, "BYTE_TEST looks swapped, "
1826 "applying WORD_SWAP");
1827 smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
1828
1829 /* 1 dummy read of BYTE_TEST is needed after a write to
1830 * WORD_SWAP before its contents are valid */
1831 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1832
1833 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1834 }
1835
1836 if (byte_test != 0x87654321) {
1837 SMSC_WARNING(DRV, "BYTE_TEST: 0x%08X", byte_test);
1838 if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
1839 SMSC_WARNING(PROBE,
1840 "top 16 bits equal to bottom 16 bits");
1841 SMSC_TRACE(PROBE, "This may mean the chip is set "
1842 "for 32 bit while the bus is reading 16 bit");
1843 }
1844 return -ENODEV;
1845 }
1846
1847 /* Default generation to zero (all workarounds apply) */
1848 pdata->generation = 0;
1849
1850 pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
1851 switch (pdata->idrev & 0xFFFF0000) {
1852 case 0x01180000:
1853 case 0x01170000:
1854 case 0x01160000:
1855 case 0x01150000:
1856 /* LAN911[5678] family */
1857 pdata->generation = pdata->idrev & 0x0000FFFF;
1858 break;
1859
1860 case 0x118A0000:
1861 case 0x117A0000:
1862 case 0x116A0000:
1863 case 0x115A0000:
1864 /* LAN921[5678] family */
1865 pdata->generation = 3;
1866 break;
1867
1868 case 0x92100000:
1869 case 0x92110000:
1870 case 0x92200000:
1871 case 0x92210000:
1872 /* LAN9210/LAN9211/LAN9220/LAN9221 */
1873 pdata->generation = 4;
1874 break;
1875
1876 default:
1877 SMSC_WARNING(PROBE, "LAN911x not identified, idrev: 0x%08X",
1878 pdata->idrev);
1879 return -ENODEV;
1880 }
1881
1882 SMSC_TRACE(PROBE, "LAN911x identified, idrev: 0x%08X, generation: %d",
1883 pdata->idrev, pdata->generation);
1884
1885 if (pdata->generation == 0)
1886 SMSC_WARNING(PROBE,
1887 "This driver is not intended for this chip revision");
1888
31f45747
SG		 1889 /* workaround for platforms without an eeprom, where the mac address
1890 * is stored elsewhere and set by the bootloader. This saves the
1891 * mac address before resetting the device */
1892 if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS)
1893 smsc911x_read_mac_address(dev);
1894
fd9abb3d
SG		 1895 /* Reset the LAN911x */
1896 if (smsc911x_soft_reset(pdata))
1897 return -ENODEV;
1898
1899 /* Disable all interrupt sources until we bring the device up */
1900 smsc911x_reg_write(pdata, INT_EN, 0);
1901
1902 ether_setup(dev);
fd9abb3d 1903 dev->flags |= IFF_MULTICAST;
fd9abb3d 1904 netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
631b7568 1905 dev->netdev_ops = &smsc911x_netdev_ops;
fd9abb3d
SG		 1906 dev->ethtool_ops = &smsc911x_ethtool_ops;
1907
fd9abb3d
SG		 1908 return 0;
1909}
1910
1911static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
1912{
1913 struct net_device *dev;
1914 struct smsc911x_data *pdata;
1915 struct resource *res;
1916
1917 dev = platform_get_drvdata(pdev);
1918 BUG_ON(!dev);
1919 pdata = netdev_priv(dev);
1920 BUG_ON(!pdata);
1921 BUG_ON(!pdata->ioaddr);
1922 BUG_ON(!pdata->phy_dev);
1923
1924 SMSC_TRACE(IFDOWN, "Stopping driver.");
1925
1926 phy_disconnect(pdata->phy_dev);
1927 pdata->phy_dev = NULL;
1928 mdiobus_unregister(pdata->mii_bus);
1929 mdiobus_free(pdata->mii_bus);
1930
1931 platform_set_drvdata(pdev, NULL);
1932 unregister_netdev(dev);
1933 free_irq(dev->irq, dev);
1934 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1935 "smsc911x-memory");
1936 if (!res)
d4522739 1937 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fd9abb3d 1938
39424539 1939 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 1940
1941 iounmap(pdata->ioaddr);
1942
1943 free_netdev(dev);
1944
1945 return 0;
1946}
1947
1948static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
1949{
1950 struct net_device *dev;
1951 struct smsc911x_data *pdata;
2107fb8b 1952 struct smsc911x_platform_config *config = pdev->dev.platform_data;
61307ed8 1953 struct resource *res, *irq_res;
fd9abb3d 1954 unsigned int intcfg = 0;
61307ed8 1955 int res_size, irq_flags;
fd9abb3d 1956 int retval;
fd9abb3d
SG		 1957
1958 pr_info("%s: Driver version %s.\n", SMSC_CHIPNAME, SMSC_DRV_VERSION);
1959
2107fb8b
SG		 1960 /* platform data specifies irq & dynamic bus configuration */
1961 if (!pdev->dev.platform_data) {
1962 pr_warning("%s: platform_data not provided\n", SMSC_CHIPNAME);
1963 retval = -ENODEV;
1964 goto out_0;
1965 }
1966
fd9abb3d
SG		 1967 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1968 "smsc911x-memory");
1969 if (!res)
1970 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1971 if (!res) {
1972 pr_warning("%s: Could not allocate resource.\n",
1973 SMSC_CHIPNAME);
1974 retval = -ENODEV;
1975 goto out_0;
1976 }
39424539 1977 res_size = resource_size(res);
fd9abb3d 1978
61307ed8
SG		 1979 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1980 if (!irq_res) {
1981 pr_warning("%s: Could not allocate irq resource.\n",
1982 SMSC_CHIPNAME);
1983 retval = -ENODEV;
1984 goto out_0;
1985 }
1986
fd9abb3d
SG		 1987 if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
1988 retval = -EBUSY;
1989 goto out_0;
1990 }
1991
1992 dev = alloc_etherdev(sizeof(struct smsc911x_data));
1993 if (!dev) {
1994 pr_warning("%s: Could not allocate device.\n", SMSC_CHIPNAME);
1995 retval = -ENOMEM;
1996 goto out_release_io_1;
1997 }
1998
1999 SET_NETDEV_DEV(dev, &pdev->dev);
2000
2001 pdata = netdev_priv(dev);
2002
61307ed8
SG		 2003 dev->irq = irq_res->start;
2004 irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
fd9abb3d
SG		 2005 pdata->ioaddr = ioremap_nocache(res->start, res_size);
2006
2107fb8b
SG		 2007 /* copy config parameters across to pdata */
2008 memcpy(&pdata->config, config, sizeof(pdata->config));
fd9abb3d
SG		 2009
2010 pdata->dev = dev;
2011 pdata->msg_enable = ((1 << debug) - 1);
2012
2013 if (pdata->ioaddr == NULL) {
2014 SMSC_WARNING(PROBE,
2015 "Error smsc911x base address invalid");
2016 retval = -ENOMEM;
2017 goto out_free_netdev_2;
2018 }
2019
2020 retval = smsc911x_init(dev);
2021 if (retval < 0)
2022 goto out_unmap_io_3;
2023
2024 /* configure irq polarity and type before connecting isr */
2107fb8b 2025 if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
fd9abb3d
SG		 2026 intcfg |= INT_CFG_IRQ_POL_;
2027
2107fb8b 2028 if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
fd9abb3d
SG		 2029 intcfg |= INT_CFG_IRQ_TYPE_;
2030
2031 smsc911x_reg_write(pdata, INT_CFG, intcfg);
2032
2033 /* Ensure interrupts are globally disabled before connecting ISR */
2034 smsc911x_reg_write(pdata, INT_EN, 0);
2035 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
2036
61307ed8 2037 retval = request_irq(dev->irq, smsc911x_irqhandler,
e81259b4 2038 irq_flags | IRQF_SHARED, dev->name, dev);
fd9abb3d
SG		 2039 if (retval) {
2040 SMSC_WARNING(PROBE,
2041 "Unable to claim requested irq: %d", dev->irq);
2042 goto out_unmap_io_3;
2043 }
2044
2045 platform_set_drvdata(pdev, dev);
2046
2047 retval = register_netdev(dev);
2048 if (retval) {
2049 SMSC_WARNING(PROBE,
2050 "Error %i registering device", retval);
2051 goto out_unset_drvdata_4;
2052 } else {
2053 SMSC_TRACE(PROBE, "Network interface: \"%s\"", dev->name);
2054 }
2055
2056 spin_lock_init(&pdata->mac_lock);
2057
2058 retval = smsc911x_mii_init(pdev, dev);
2059 if (retval) {
2060 SMSC_WARNING(PROBE,
2061 "Error %i initialising mii", retval);
2062 goto out_unregister_netdev_5;
2063 }
2064
2065 spin_lock_irq(&pdata->mac_lock);
2066
2067 /* Check if mac address has been specified when bringing interface up */
2068 if (is_valid_ether_addr(dev->dev_addr)) {
225ddf49 2069 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d 2070 SMSC_TRACE(PROBE, "MAC Address is specified by configuration");
aace4959
ML		 2071 } else if (is_valid_ether_addr(pdata->config.mac)) {
2072 memcpy(dev->dev_addr, pdata->config.mac, 6);
2073 SMSC_TRACE(PROBE, "MAC Address specified by platform data");
fd9abb3d
SG		 2074 } else {
2075 /* Try reading mac address from device. if EEPROM is present
2076 * it will already have been set */
31f45747 2077 smsc911x_read_mac_address(dev);
fd9abb3d
SG		 2078
2079 if (is_valid_ether_addr(dev->dev_addr)) {
2080 /* eeprom values are valid so use them */
2081 SMSC_TRACE(PROBE,
2082 "Mac Address is read from LAN911x EEPROM");
2083 } else {
2084 /* eeprom values are invalid, generate random MAC */
2085 random_ether_addr(dev->dev_addr);
225ddf49 2086 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 2087 SMSC_TRACE(PROBE,
2088 "MAC Address is set to random_ether_addr");
2089 }
2090 }
2091
2092 spin_unlock_irq(&pdata->mac_lock);
2093
63a2ebb0 2094 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
fd9abb3d
SG		 2095
2096 return 0;
2097
2098out_unregister_netdev_5:
2099 unregister_netdev(dev);
2100out_unset_drvdata_4:
2101 platform_set_drvdata(pdev, NULL);
2102 free_irq(dev->irq, dev);
2103out_unmap_io_3:
2104 iounmap(pdata->ioaddr);
2105out_free_netdev_2:
2106 free_netdev(dev);
2107out_release_io_1:
39424539 2108 release_mem_region(res->start, resource_size(res));
fd9abb3d
SG		 2109out_0:
2110 return retval;
2111}
2112
b6907b0c
DM		 2113#ifdef CONFIG_PM
2114/* This implementation assumes the devices remains powered on its VDDVARIO
2115 * pins during suspend. */
2116
6cb87823
DM		 2117/* TODO: implement freeze/thaw callbacks for hibernation.*/
2118
2119static int smsc911x_suspend(struct device *dev)
b6907b0c 2120{
6cb87823
DM		 2121 struct net_device *ndev = dev_get_drvdata(dev);
2122 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2123
2124 /* enable wake on LAN, energy detection and the external PME
2125 * signal. */
2126 smsc911x_reg_write(pdata, PMT_CTRL,
2127 PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
2128 PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
2129
2130 return 0;
2131}
2132
6cb87823 2133static int smsc911x_resume(struct device *dev)
b6907b0c 2134{
6cb87823
DM		 2135 struct net_device *ndev = dev_get_drvdata(dev);
2136 struct smsc911x_data *pdata = netdev_priv(ndev);
b6907b0c
DM		 2137 unsigned int to = 100;
2138
2139 /* Note 3.11 from the datasheet:
2140 * "When the LAN9220 is in a power saving state, a write of any
2141 * data to the BYTE_TEST register will wake-up the device."
2142 */
2143 smsc911x_reg_write(pdata, BYTE_TEST, 0);
2144
2145 /* poll the READY bit in PMT_CTRL. Any other access to the device is
2146 * forbidden while this bit isn't set. Try for 100ms and return -EIO
2147 * if it failed. */
2148 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
2149 udelay(1000);
2150
2151 return (to == 0) ? -EIO : 0;
2152}
2153
47145210 2154static const struct dev_pm_ops smsc911x_pm_ops = {
6cb87823
DM		 2155 .suspend = smsc911x_suspend,
2156 .resume = smsc911x_resume,
2157};
2158
2159#define SMSC911X_PM_OPS (&smsc911x_pm_ops)
2160
b6907b0c 2161#else
6cb87823 2162#define SMSC911X_PM_OPS NULL
b6907b0c
DM		 2163#endif
2164
fd9abb3d
SG		 2165static struct platform_driver smsc911x_driver = {
2166 .probe = smsc911x_drv_probe,
df911e2d 2167 .remove = __devexit_p(smsc911x_drv_remove),
fd9abb3d 2168 .driver = {
6cb87823
DM		 2169 .name = SMSC_CHIPNAME,
2170 .owner = THIS_MODULE,
2171 .pm = SMSC911X_PM_OPS,
fd9abb3d
SG		 2172 },
2173};
2174
2175/* Entry point for loading the module */
2176static int __init smsc911x_init_module(void)
2177{
2178 return platform_driver_register(&smsc911x_driver);
2179}
2180
2181/* entry point for unloading the module */
2182static void __exit smsc911x_cleanup_module(void)
2183{
2184 platform_driver_unregister(&smsc911x_driver);
2185}
2186
2187module_init(smsc911x_init_module);
2188module_exit(smsc911x_cleanup_module);
Clone of davem's net-next-2.6 tree