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gianfar: fix headroom expansion code
[net-next-2.6.git] / drivers / net / smsc911x.c
CommitLineData
fd9abb3d
SG		 1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************
21 * Rewritten, heavily based on smsc911x simple driver by SMSC.
22 * Partly uses io macros from smc91x.c by Nicolas Pitre
23 *
24 * Supported devices:
25 * LAN9115, LAN9116, LAN9117, LAN9118
26 * LAN9215, LAN9216, LAN9217, LAN9218
27 * LAN9210, LAN9211
28 * LAN9220, LAN9221
29 *
30 */
31
32#include <linux/crc32.h>
33#include <linux/delay.h>
34#include <linux/errno.h>
35#include <linux/etherdevice.h>
36#include <linux/ethtool.h>
37#include <linux/init.h>
38#include <linux/ioport.h>
39#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/netdevice.h>
42#include <linux/platform_device.h>
43#include <linux/sched.h>
44#include <linux/slab.h>
45#include <linux/timer.h>
46#include <linux/version.h>
47#include <linux/bug.h>
48#include <linux/bitops.h>
49#include <linux/irq.h>
50#include <linux/io.h>
51#include <linux/phy.h>
52#include <linux/smsc911x.h>
53#include "smsc911x.h"
54
55#define SMSC_CHIPNAME "smsc911x"
56#define SMSC_MDIONAME "smsc911x-mdio"
57#define SMSC_DRV_VERSION "2008-10-21"
58
59MODULE_LICENSE("GPL");
60MODULE_VERSION(SMSC_DRV_VERSION);
61
62#if USE_DEBUG > 0
63static int debug = 16;
64#else
65static int debug = 3;
66#endif
67
68module_param(debug, int, 0);
69MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
70
71struct smsc911x_data {
72 void __iomem *ioaddr;
73
74 unsigned int idrev;
75
76 /* used to decide which workarounds apply */
77 unsigned int generation;
78
79 /* device configuration (copied from platform_data during probe) */
2107fb8b 80 struct smsc911x_platform_config config;
fd9abb3d
SG		 81
82 /* This needs to be acquired before calling any of below:
83 * smsc911x_mac_read(), smsc911x_mac_write()
84 */
85 spinlock_t mac_lock;
86
2107fb8b
SG		 87 /* spinlock to ensure 16-bit accesses are serialised.
88 * unused with a 32-bit bus */
fd9abb3d 89 spinlock_t dev_lock;
fd9abb3d
SG		 90
91 struct phy_device *phy_dev;
92 struct mii_bus *mii_bus;
93 int phy_irq[PHY_MAX_ADDR];
94 unsigned int using_extphy;
95 int last_duplex;
96 int last_carrier;
97
98 u32 msg_enable;
99 unsigned int gpio_setting;
100 unsigned int gpio_orig_setting;
101 struct net_device *dev;
102 struct napi_struct napi;
103
104 unsigned int software_irq_signal;
105
106#ifdef USE_PHY_WORK_AROUND
107#define MIN_PACKET_SIZE (64)
108 char loopback_tx_pkt[MIN_PACKET_SIZE];
109 char loopback_rx_pkt[MIN_PACKET_SIZE];
110 unsigned int resetcount;
111#endif
112
113 /* Members for Multicast filter workaround */
114 unsigned int multicast_update_pending;
115 unsigned int set_bits_mask;
116 unsigned int clear_bits_mask;
117 unsigned int hashhi;
118 unsigned int hashlo;
119};
120
2107fb8b 121/* The 16-bit access functions are significantly slower, due to the locking
fd9abb3d
SG		 122 * necessary. If your bus hardware can be configured to do this for you
123 * (in response to a single 32-bit operation from software), you should use
124 * the 32-bit access functions instead. */
125
126static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
127{
2107fb8b
SG		 128 if (pdata->config.flags & SMSC911X_USE_32BIT)
129 return readl(pdata->ioaddr + reg);
130
131 if (pdata->config.flags & SMSC911X_USE_16BIT) {
132 u32 data;
133 unsigned long flags;
134
135 /* these two 16-bit reads must be performed consecutively, so
136 * must not be interrupted by our own ISR (which would start
137 * another read operation) */
138 spin_lock_irqsave(&pdata->dev_lock, flags);
139 data = ((readw(pdata->ioaddr + reg) & 0xFFFF) |
140 ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
141 spin_unlock_irqrestore(&pdata->dev_lock, flags);
142
143 return data;
144 }
fd9abb3d 145
2107fb8b 146 BUG();
702403af 147 return 0;
fd9abb3d
SG		 148}
149
150static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
151 u32 val)
152{
2107fb8b
SG		 153 if (pdata->config.flags & SMSC911X_USE_32BIT) {
154 writel(val, pdata->ioaddr + reg);
155 return;
156 }
157
158 if (pdata->config.flags & SMSC911X_USE_16BIT) {
159 unsigned long flags;
160
161 /* these two 16-bit writes must be performed consecutively, so
162 * must not be interrupted by our own ISR (which would start
163 * another read operation) */
164 spin_lock_irqsave(&pdata->dev_lock, flags);
165 writew(val & 0xFFFF, pdata->ioaddr + reg);
166 writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
167 spin_unlock_irqrestore(&pdata->dev_lock, flags);
168 return;
169 }
fd9abb3d 170
2107fb8b 171 BUG();
fd9abb3d
SG		 172}
173
174/* Writes a packet to the TX_DATA_FIFO */
175static inline void
176smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
177 unsigned int wordcount)
178{
2107fb8b
SG		 179 if (pdata->config.flags & SMSC911X_USE_32BIT) {
180 writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
181 return;
182 }
183
184 if (pdata->config.flags & SMSC911X_USE_16BIT) {
185 while (wordcount--)
186 smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
187 return;
188 }
189
190 BUG();
fd9abb3d
SG		 191}
192
193/* Reads a packet out of the RX_DATA_FIFO */
194static inline void
195smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
196 unsigned int wordcount)
197{
2107fb8b
SG		 198 if (pdata->config.flags & SMSC911X_USE_32BIT) {
199 readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
200 return;
201 }
fd9abb3d 202
2107fb8b
SG		 203 if (pdata->config.flags & SMSC911X_USE_16BIT) {
204 while (wordcount--)
205 *buf++ = smsc911x_reg_read(pdata, RX_DATA_FIFO);
206 return;
207 }
208
209 BUG();
210}
fd9abb3d
SG		 211
212/* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
213 * and smsc911x_mac_write, so assumes mac_lock is held */
214static int smsc911x_mac_complete(struct smsc911x_data *pdata)
215{
216 int i;
217 u32 val;
218
219 SMSC_ASSERT_MAC_LOCK(pdata);
220
221 for (i = 0; i < 40; i++) {
222 val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
223 if (!(val & MAC_CSR_CMD_CSR_BUSY_))
224 return 0;
225 }
226 SMSC_WARNING(HW, "Timed out waiting for MAC not BUSY. "
227 "MAC_CSR_CMD: 0x%08X", val);
228 return -EIO;
229}
230
231/* Fetches a MAC register value. Assumes mac_lock is acquired */
232static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
233{
234 unsigned int temp;
235
236 SMSC_ASSERT_MAC_LOCK(pdata);
237
238 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
239 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
240 SMSC_WARNING(HW, "MAC busy at entry");
241 return 0xFFFFFFFF;
242 }
243
244 /* Send the MAC cmd */
245 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
246 MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
247
248 /* Workaround for hardware read-after-write restriction */
249 temp = smsc911x_reg_read(pdata, BYTE_TEST);
250
251 /* Wait for the read to complete */
252 if (likely(smsc911x_mac_complete(pdata) == 0))
253 return smsc911x_reg_read(pdata, MAC_CSR_DATA);
254
255 SMSC_WARNING(HW, "MAC busy after read");
256 return 0xFFFFFFFF;
257}
258
259/* Set a mac register, mac_lock must be acquired before calling */
260static void smsc911x_mac_write(struct smsc911x_data *pdata,
261 unsigned int offset, u32 val)
262{
263 unsigned int temp;
264
265 SMSC_ASSERT_MAC_LOCK(pdata);
266
267 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
268 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
269 SMSC_WARNING(HW,
270 "smsc911x_mac_write failed, MAC busy at entry");
271 return;
272 }
273
274 /* Send data to write */
275 smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
276
277 /* Write the actual data */
278 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
279 MAC_CSR_CMD_CSR_BUSY_));
280
281 /* Workaround for hardware read-after-write restriction */
282 temp = smsc911x_reg_read(pdata, BYTE_TEST);
283
284 /* Wait for the write to complete */
285 if (likely(smsc911x_mac_complete(pdata) == 0))
286 return;
287
288 SMSC_WARNING(HW,
289 "smsc911x_mac_write failed, MAC busy after write");
290}
291
292/* Get a phy register */
293static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
294{
295 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
296 unsigned long flags;
297 unsigned int addr;
298 int i, reg;
299
300 spin_lock_irqsave(&pdata->mac_lock, flags);
301
302 /* Confirm MII not busy */
303 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
304 SMSC_WARNING(HW,
305 "MII is busy in smsc911x_mii_read???");
306 reg = -EIO;
307 goto out;
308 }
309
310 /* Set the address, index & direction (read from PHY) */
311 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
312 smsc911x_mac_write(pdata, MII_ACC, addr);
313
314 /* Wait for read to complete w/ timeout */
315 for (i = 0; i < 100; i++)
316 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
317 reg = smsc911x_mac_read(pdata, MII_DATA);
318 goto out;
319 }
320
321 SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
322 reg = -EIO;
323
324out:
325 spin_unlock_irqrestore(&pdata->mac_lock, flags);
326 return reg;
327}
328
329/* Set a phy register */
330static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
331 u16 val)
332{
333 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
334 unsigned long flags;
335 unsigned int addr;
336 int i, reg;
337
338 spin_lock_irqsave(&pdata->mac_lock, flags);
339
340 /* Confirm MII not busy */
341 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
342 SMSC_WARNING(HW,
343 "MII is busy in smsc911x_mii_write???");
344 reg = -EIO;
345 goto out;
346 }
347
348 /* Put the data to write in the MAC */
349 smsc911x_mac_write(pdata, MII_DATA, val);
350
351 /* Set the address, index & direction (write to PHY) */
352 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
353 MII_ACC_MII_WRITE_;
354 smsc911x_mac_write(pdata, MII_ACC, addr);
355
356 /* Wait for write to complete w/ timeout */
357 for (i = 0; i < 100; i++)
358 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
359 reg = 0;
360 goto out;
361 }
362
363 SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
364 reg = -EIO;
365
366out:
367 spin_unlock_irqrestore(&pdata->mac_lock, flags);
368 return reg;
369}
370
d23f028a
SG		 371/* Switch to external phy. Assumes tx and rx are stopped. */
372static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
fd9abb3d
SG		 373{
374 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
375
d23f028a
SG		 376 /* Disable phy clocks to the MAC */
377 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
378 hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
379 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
380 udelay(10); /* Enough time for clocks to stop */
fd9abb3d 381
d23f028a
SG		 382 /* Switch to external phy */
383 hwcfg |= HW_CFG_EXT_PHY_EN_;
384 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
fd9abb3d 385
d23f028a
SG		 386 /* Enable phy clocks to the MAC */
387 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
388 hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
389 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
390 udelay(10); /* Enough time for clocks to restart */
fd9abb3d 391
d23f028a
SG		 392 hwcfg |= HW_CFG_SMI_SEL_;
393 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
394}
fd9abb3d 395
d23f028a
SG		 396/* Autodetects and enables external phy if present on supported chips.
397 * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
398 * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
399static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
400{
401 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
fd9abb3d 402
d23f028a
SG		 403 if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
404 SMSC_TRACE(HW, "Forcing internal PHY");
405 pdata->using_extphy = 0;
406 } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
407 SMSC_TRACE(HW, "Forcing external PHY");
408 smsc911x_phy_enable_external(pdata);
409 pdata->using_extphy = 1;
410 } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
411 SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET set, using external PHY");
412 smsc911x_phy_enable_external(pdata);
fd9abb3d
SG		 413 pdata->using_extphy = 1;
414 } else {
d23f028a
SG		 415 SMSC_TRACE(HW, "HW_CFG EXT_PHY_DET clear, using internal PHY");
416 pdata->using_extphy = 0;
fd9abb3d 417 }
fd9abb3d
SG		 418}
419
420/* Fetches a tx status out of the status fifo */
421static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
422{
423 unsigned int result =
424 smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
425
426 if (result != 0)
427 result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
428
429 return result;
430}
431
432/* Fetches the next rx status */
433static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
434{
435 unsigned int result =
436 smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
437
438 if (result != 0)
439 result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
440
441 return result;
442}
443
444#ifdef USE_PHY_WORK_AROUND
445static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
446{
447 unsigned int tries;
448 u32 wrsz;
449 u32 rdsz;
450 ulong bufp;
451
452 for (tries = 0; tries < 10; tries++) {
453 unsigned int txcmd_a;
454 unsigned int txcmd_b;
455 unsigned int status;
456 unsigned int pktlength;
457 unsigned int i;
458
459 /* Zero-out rx packet memory */
460 memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
461
462 /* Write tx packet to 118 */
463 txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
464 txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
465 txcmd_a |= MIN_PACKET_SIZE;
466
467 txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
468
469 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
470 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
471
472 bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
473 wrsz = MIN_PACKET_SIZE + 3;
474 wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
475 wrsz >>= 2;
476
477 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
478
479 /* Wait till transmit is done */
480 i = 60;
481 do {
482 udelay(5);
483 status = smsc911x_tx_get_txstatus(pdata);
484 } while ((i--) && (!status));
485
486 if (!status) {
487 SMSC_WARNING(HW, "Failed to transmit "
488 "during loopback test");
489 continue;
490 }
491 if (status & TX_STS_ES_) {
492 SMSC_WARNING(HW, "Transmit encountered "
493 "errors during loopback test");
494 continue;
495 }
496
497 /* Wait till receive is done */
498 i = 60;
499 do {
500 udelay(5);
501 status = smsc911x_rx_get_rxstatus(pdata);
502 } while ((i--) && (!status));
503
504 if (!status) {
505 SMSC_WARNING(HW,
506 "Failed to receive during loopback test");
507 continue;
508 }
509 if (status & RX_STS_ES_) {
510 SMSC_WARNING(HW, "Receive encountered "
511 "errors during loopback test");
512 continue;
513 }
514
515 pktlength = ((status & 0x3FFF0000UL) >> 16);
516 bufp = (ulong)pdata->loopback_rx_pkt;
517 rdsz = pktlength + 3;
518 rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
519 rdsz >>= 2;
520
521 smsc911x_rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
522
523 if (pktlength != (MIN_PACKET_SIZE + 4)) {
524 SMSC_WARNING(HW, "Unexpected packet size "
525 "during loop back test, size=%d, will retry",
526 pktlength);
527 } else {
528 unsigned int j;
529 int mismatch = 0;
530 for (j = 0; j < MIN_PACKET_SIZE; j++) {
531 if (pdata->loopback_tx_pkt[j]
532 != pdata->loopback_rx_pkt[j]) {
533 mismatch = 1;
534 break;
535 }
536 }
537 if (!mismatch) {
538 SMSC_TRACE(HW, "Successfully verified "
539 "loopback packet");
540 return 0;
541 } else {
542 SMSC_WARNING(HW, "Data mismatch "
543 "during loop back test, will retry");
544 }
545 }
546 }
547
548 return -EIO;
549}
550
551static int smsc911x_phy_reset(struct smsc911x_data *pdata)
552{
553 struct phy_device *phy_dev = pdata->phy_dev;
554 unsigned int temp;
555 unsigned int i = 100000;
556
557 BUG_ON(!phy_dev);
558 BUG_ON(!phy_dev->bus);
559
560 SMSC_TRACE(HW, "Performing PHY BCR Reset");
561 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
562 do {
563 msleep(1);
564 temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
565 MII_BMCR);
566 } while ((i--) && (temp & BMCR_RESET));
567
568 if (temp & BMCR_RESET) {
569 SMSC_WARNING(HW, "PHY reset failed to complete.");
570 return -EIO;
571 }
572 /* Extra delay required because the phy may not be completed with
573 * its reset when BMCR_RESET is cleared. Specs say 256 uS is
574 * enough delay but using 1ms here to be safe */
575 msleep(1);
576
577 return 0;
578}
579
580static int smsc911x_phy_loopbacktest(struct net_device *dev)
581{
582 struct smsc911x_data *pdata = netdev_priv(dev);
583 struct phy_device *phy_dev = pdata->phy_dev;
584 int result = -EIO;
585 unsigned int i, val;
586 unsigned long flags;
587
588 /* Initialise tx packet using broadcast destination address */
589 memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
590
591 /* Use incrementing source address */
592 for (i = 6; i < 12; i++)
593 pdata->loopback_tx_pkt[i] = (char)i;
594
595 /* Set length type field */
596 pdata->loopback_tx_pkt[12] = 0x00;
597 pdata->loopback_tx_pkt[13] = 0x00;
598
599 for (i = 14; i < MIN_PACKET_SIZE; i++)
600 pdata->loopback_tx_pkt[i] = (char)i;
601
602 val = smsc911x_reg_read(pdata, HW_CFG);
603 val &= HW_CFG_TX_FIF_SZ_;
604 val |= HW_CFG_SF_;
605 smsc911x_reg_write(pdata, HW_CFG, val);
606
607 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
608 smsc911x_reg_write(pdata, RX_CFG,
609 (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
610
611 for (i = 0; i < 10; i++) {
612 /* Set PHY to 10/FD, no ANEG, and loopback mode */
613 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
614 BMCR_LOOPBACK | BMCR_FULLDPLX);
615
616 /* Enable MAC tx/rx, FD */
617 spin_lock_irqsave(&pdata->mac_lock, flags);
618 smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
619 | MAC_CR_TXEN_ | MAC_CR_RXEN_);
620 spin_unlock_irqrestore(&pdata->mac_lock, flags);
621
622 if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
623 result = 0;
624 break;
625 }
626 pdata->resetcount++;
627
628 /* Disable MAC rx */
629 spin_lock_irqsave(&pdata->mac_lock, flags);
630 smsc911x_mac_write(pdata, MAC_CR, 0);
631 spin_unlock_irqrestore(&pdata->mac_lock, flags);
632
633 smsc911x_phy_reset(pdata);
634 }
635
636 /* Disable MAC */
637 spin_lock_irqsave(&pdata->mac_lock, flags);
638 smsc911x_mac_write(pdata, MAC_CR, 0);
639 spin_unlock_irqrestore(&pdata->mac_lock, flags);
640
641 /* Cancel PHY loopback mode */
642 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
643
644 smsc911x_reg_write(pdata, TX_CFG, 0);
645 smsc911x_reg_write(pdata, RX_CFG, 0);
646
647 return result;
648}
649#endif /* USE_PHY_WORK_AROUND */
650
fd9abb3d
SG		 651static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
652{
653 struct phy_device *phy_dev = pdata->phy_dev;
654 u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
655 u32 flow;
656 unsigned long flags;
657
658 if (phy_dev->duplex == DUPLEX_FULL) {
659 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
660 u16 rmtadv = phy_read(phy_dev, MII_LPA);
bc02ff95 661 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
fd9abb3d
SG		 662
663 if (cap & FLOW_CTRL_RX)
664 flow = 0xFFFF0002;
665 else
666 flow = 0;
667
668 if (cap & FLOW_CTRL_TX)
669 afc |= 0xF;
670 else
671 afc &= ~0xF;
672
673 SMSC_TRACE(HW, "rx pause %s, tx pause %s",
674 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
675 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
676 } else {
677 SMSC_TRACE(HW, "half duplex");
678 flow = 0;
679 afc |= 0xF;
680 }
681
682 spin_lock_irqsave(&pdata->mac_lock, flags);
683 smsc911x_mac_write(pdata, FLOW, flow);
684 spin_unlock_irqrestore(&pdata->mac_lock, flags);
685
686 smsc911x_reg_write(pdata, AFC_CFG, afc);
687}
688
689/* Update link mode if anything has changed. Called periodically when the
690 * PHY is in polling mode, even if nothing has changed. */
691static void smsc911x_phy_adjust_link(struct net_device *dev)
692{
693 struct smsc911x_data *pdata = netdev_priv(dev);
694 struct phy_device *phy_dev = pdata->phy_dev;
695 unsigned long flags;
696 int carrier;
697
698 if (phy_dev->duplex != pdata->last_duplex) {
699 unsigned int mac_cr;
700 SMSC_TRACE(HW, "duplex state has changed");
701
702 spin_lock_irqsave(&pdata->mac_lock, flags);
703 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
704 if (phy_dev->duplex) {
705 SMSC_TRACE(HW,
706 "configuring for full duplex mode");
707 mac_cr |= MAC_CR_FDPX_;
708 } else {
709 SMSC_TRACE(HW,
710 "configuring for half duplex mode");
711 mac_cr &= ~MAC_CR_FDPX_;
712 }
713 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
714 spin_unlock_irqrestore(&pdata->mac_lock, flags);
715
716 smsc911x_phy_update_flowcontrol(pdata);
717 pdata->last_duplex = phy_dev->duplex;
718 }
719
720 carrier = netif_carrier_ok(dev);
721 if (carrier != pdata->last_carrier) {
722 SMSC_TRACE(HW, "carrier state has changed");
723 if (carrier) {
724 SMSC_TRACE(HW, "configuring for carrier OK");
725 if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
726 (!pdata->using_extphy)) {
727 /* Restore orginal GPIO configuration */
728 pdata->gpio_setting = pdata->gpio_orig_setting;
729 smsc911x_reg_write(pdata, GPIO_CFG,
730 pdata->gpio_setting);
731 }
732 } else {
733 SMSC_TRACE(HW, "configuring for no carrier");
734 /* Check global setting that LED1
735 * usage is 10/100 indicator */
736 pdata->gpio_setting = smsc911x_reg_read(pdata,
737 GPIO_CFG);
738 if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_)
739 && (!pdata->using_extphy)) {
740 /* Force 10/100 LED off, after saving
741 * orginal GPIO configuration */
742 pdata->gpio_orig_setting = pdata->gpio_setting;
743
744 pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
745 pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
746 | GPIO_CFG_GPIODIR0_
747 | GPIO_CFG_GPIOD0_);
748 smsc911x_reg_write(pdata, GPIO_CFG,
749 pdata->gpio_setting);
750 }
751 }
752 pdata->last_carrier = carrier;
753 }
754}
755
756static int smsc911x_mii_probe(struct net_device *dev)
757{
758 struct smsc911x_data *pdata = netdev_priv(dev);
759 struct phy_device *phydev = NULL;
760 int phy_addr;
761
762 /* find the first phy */
763 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
764 if (pdata->mii_bus->phy_map[phy_addr]) {
765 phydev = pdata->mii_bus->phy_map[phy_addr];
766 SMSC_TRACE(PROBE, "PHY %d: addr %d, phy_id 0x%08X",
767 phy_addr, phydev->addr, phydev->phy_id);
768 break;
769 }
770 }
771
772 if (!phydev) {
773 pr_err("%s: no PHY found\n", dev->name);
774 return -ENODEV;
775 }
776
db1d7bf7 777 phydev = phy_connect(dev, dev_name(&phydev->dev),
2107fb8b 778 &smsc911x_phy_adjust_link, 0, pdata->config.phy_interface);
fd9abb3d
SG		 779
780 if (IS_ERR(phydev)) {
781 pr_err("%s: Could not attach to PHY\n", dev->name);
782 return PTR_ERR(phydev);
783 }
784
785 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
db1d7bf7
KS		 786 dev->name, phydev->drv->name,
787 dev_name(&phydev->dev), phydev->irq);
fd9abb3d
SG		 788
789 /* mask with MAC supported features */
790 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
791 SUPPORTED_Asym_Pause);
792 phydev->advertising = phydev->supported;
793
794 pdata->phy_dev = phydev;
795 pdata->last_duplex = -1;
796 pdata->last_carrier = -1;
797
798#ifdef USE_PHY_WORK_AROUND
799 if (smsc911x_phy_loopbacktest(dev) < 0) {
800 SMSC_WARNING(HW, "Failed Loop Back Test");
801 return -ENODEV;
802 }
803 SMSC_TRACE(HW, "Passed Loop Back Test");
804#endif /* USE_PHY_WORK_AROUND */
805
806 SMSC_TRACE(HW, "phy initialised succesfully");
807 return 0;
808}
809
810static int __devinit smsc911x_mii_init(struct platform_device *pdev,
811 struct net_device *dev)
812{
813 struct smsc911x_data *pdata = netdev_priv(dev);
814 int err = -ENXIO, i;
815
816 pdata->mii_bus = mdiobus_alloc();
817 if (!pdata->mii_bus) {
818 err = -ENOMEM;
819 goto err_out_1;
820 }
821
822 pdata->mii_bus->name = SMSC_MDIONAME;
823 snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
824 pdata->mii_bus->priv = pdata;
825 pdata->mii_bus->read = smsc911x_mii_read;
826 pdata->mii_bus->write = smsc911x_mii_write;
827 pdata->mii_bus->irq = pdata->phy_irq;
828 for (i = 0; i < PHY_MAX_ADDR; ++i)
829 pdata->mii_bus->irq[i] = PHY_POLL;
830
831 pdata->mii_bus->parent = &pdev->dev;
fd9abb3d 832
fd9abb3d
SG		 833 switch (pdata->idrev & 0xFFFF0000) {
834 case 0x01170000:
835 case 0x01150000:
836 case 0x117A0000:
837 case 0x115A0000:
838 /* External PHY supported, try to autodetect */
d23f028a 839 smsc911x_phy_initialise_external(pdata);
fd9abb3d
SG		 840 break;
841 default:
842 SMSC_TRACE(HW, "External PHY is not supported, "
843 "using internal PHY");
d23f028a 844 pdata->using_extphy = 0;
fd9abb3d
SG		 845 break;
846 }
847
848 if (!pdata->using_extphy) {
849 /* Mask all PHYs except ID 1 (internal) */
850 pdata->mii_bus->phy_mask = ~(1 << 1);
851 }
852
853 if (mdiobus_register(pdata->mii_bus)) {
854 SMSC_WARNING(PROBE, "Error registering mii bus");
855 goto err_out_free_bus_2;
856 }
857
858 if (smsc911x_mii_probe(dev) < 0) {
859 SMSC_WARNING(PROBE, "Error registering mii bus");
860 goto err_out_unregister_bus_3;
861 }
862
863 return 0;
864
865err_out_unregister_bus_3:
866 mdiobus_unregister(pdata->mii_bus);
867err_out_free_bus_2:
868 mdiobus_free(pdata->mii_bus);
869err_out_1:
870 return err;
871}
872
873/* Gets the number of tx statuses in the fifo */
874static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
875{
876 return (smsc911x_reg_read(pdata, TX_FIFO_INF)
877 & TX_FIFO_INF_TSUSED_) >> 16;
878}
879
880/* Reads tx statuses and increments counters where necessary */
881static void smsc911x_tx_update_txcounters(struct net_device *dev)
882{
883 struct smsc911x_data *pdata = netdev_priv(dev);
884 unsigned int tx_stat;
885
886 while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
887 if (unlikely(tx_stat & 0x80000000)) {
888 /* In this driver the packet tag is used as the packet
889 * length. Since a packet length can never reach the
890 * size of 0x8000, this bit is reserved. It is worth
891 * noting that the "reserved bit" in the warning above
892 * does not reference a hardware defined reserved bit
893 * but rather a driver defined one.
894 */
895 SMSC_WARNING(HW,
896 "Packet tag reserved bit is high");
897 } else {
785b6f97 898 if (unlikely(tx_stat & TX_STS_ES_)) {
fd9abb3d
SG		 899 dev->stats.tx_errors++;
900 } else {
901 dev->stats.tx_packets++;
902 dev->stats.tx_bytes += (tx_stat >> 16);
903 }
785b6f97 904 if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
fd9abb3d
SG		 905 dev->stats.collisions += 16;
906 dev->stats.tx_aborted_errors += 1;
907 } else {
908 dev->stats.collisions +=
909 ((tx_stat >> 3) & 0xF);
910 }
785b6f97 911 if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
fd9abb3d 912 dev->stats.tx_carrier_errors += 1;
785b6f97 913 if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
fd9abb3d
SG		 914 dev->stats.collisions++;
915 dev->stats.tx_aborted_errors++;
916 }
917 }
918 }
919}
920
921/* Increments the Rx error counters */
922static void
923smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
924{
925 int crc_err = 0;
926
785b6f97 927 if (unlikely(rxstat & RX_STS_ES_)) {
fd9abb3d 928 dev->stats.rx_errors++;
785b6f97 929 if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
fd9abb3d
SG		 930 dev->stats.rx_crc_errors++;
931 crc_err = 1;
932 }
933 }
934 if (likely(!crc_err)) {
785b6f97
SG		 935 if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
936 (rxstat & RX_STS_LENGTH_ERR_)))
fd9abb3d 937 dev->stats.rx_length_errors++;
fd9abb3d
SG		 938 if (rxstat & RX_STS_MCAST_)
939 dev->stats.multicast++;
940 }
941}
942
943/* Quickly dumps bad packets */
944static void
945smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
946{
947 unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
948
949 if (likely(pktwords >= 4)) {
950 unsigned int timeout = 500;
951 unsigned int val;
952 smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
953 do {
954 udelay(1);
955 val = smsc911x_reg_read(pdata, RX_DP_CTRL);
8dacd548 956 } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
fd9abb3d
SG		 957
958 if (unlikely(timeout == 0))
959 SMSC_WARNING(HW, "Timed out waiting for "
960 "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
961 } else {
962 unsigned int temp;
963 while (pktwords--)
964 temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
965 }
966}
967
968/* NAPI poll function */
969static int smsc911x_poll(struct napi_struct *napi, int budget)
970{
971 struct smsc911x_data *pdata =
972 container_of(napi, struct smsc911x_data, napi);
973 struct net_device *dev = pdata->dev;
974 int npackets = 0;
975
976 while (likely(netif_running(dev)) && (npackets < budget)) {
977 unsigned int pktlength;
978 unsigned int pktwords;
979 struct sk_buff *skb;
980 unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
981
982 if (!rxstat) {
983 unsigned int temp;
984 /* We processed all packets available. Tell NAPI it can
985 * stop polling then re-enable rx interrupts */
986 smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
288379f0 987 napi_complete(napi);
fd9abb3d
SG		 988 temp = smsc911x_reg_read(pdata, INT_EN);
989 temp |= INT_EN_RSFL_EN_;
990 smsc911x_reg_write(pdata, INT_EN, temp);
991 break;
992 }
993
994 /* Count packet for NAPI scheduling, even if it has an error.
995 * Error packets still require cycles to discard */
996 npackets++;
997
998 pktlength = ((rxstat & 0x3FFF0000) >> 16);
999 pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
1000 smsc911x_rx_counterrors(dev, rxstat);
1001
1002 if (unlikely(rxstat & RX_STS_ES_)) {
1003 SMSC_WARNING(RX_ERR,
1004 "Discarding packet with error bit set");
1005 /* Packet has an error, discard it and continue with
1006 * the next */
1007 smsc911x_rx_fastforward(pdata, pktwords);
1008 dev->stats.rx_dropped++;
1009 continue;
1010 }
1011
1012 skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
1013 if (unlikely(!skb)) {
1014 SMSC_WARNING(RX_ERR,
1015 "Unable to allocate skb for rx packet");
1016 /* Drop the packet and stop this polling iteration */
1017 smsc911x_rx_fastforward(pdata, pktwords);
1018 dev->stats.rx_dropped++;
1019 break;
1020 }
1021
1022 skb->data = skb->head;
1023 skb_reset_tail_pointer(skb);
1024
1025 /* Align IP on 16B boundary */
1026 skb_reserve(skb, NET_IP_ALIGN);
1027 skb_put(skb, pktlength - 4);
1028 smsc911x_rx_readfifo(pdata, (unsigned int *)skb->head,
1029 pktwords);
1030 skb->protocol = eth_type_trans(skb, dev);
1031 skb->ip_summed = CHECKSUM_NONE;
1032 netif_receive_skb(skb);
1033
1034 /* Update counters */
1035 dev->stats.rx_packets++;
1036 dev->stats.rx_bytes += (pktlength - 4);
1037 dev->last_rx = jiffies;
1038 }
1039
1040 /* Return total received packets */
1041 return npackets;
1042}
1043
1044/* Returns hash bit number for given MAC address
1045 * Example:
1046 * 01 00 5E 00 00 01 -> returns bit number 31 */
1047static unsigned int smsc911x_hash(char addr[ETH_ALEN])
1048{
1049 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
1050}
1051
1052static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
1053{
1054 /* Performs the multicast & mac_cr update. This is called when
1055 * safe on the current hardware, and with the mac_lock held */
1056 unsigned int mac_cr;
1057
1058 SMSC_ASSERT_MAC_LOCK(pdata);
1059
1060 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1061 mac_cr |= pdata->set_bits_mask;
1062 mac_cr &= ~(pdata->clear_bits_mask);
1063 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1064 smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
1065 smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
1066 SMSC_TRACE(HW, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
1067 mac_cr, pdata->hashhi, pdata->hashlo);
1068}
1069
1070static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
1071{
1072 unsigned int mac_cr;
1073
1074 /* This function is only called for older LAN911x devices
1075 * (revA or revB), where MAC_CR, HASHH and HASHL should not
1076 * be modified during Rx - newer devices immediately update the
1077 * registers.
1078 *
1079 * This is called from interrupt context */
1080
1081 spin_lock(&pdata->mac_lock);
1082
1083 /* Check Rx has stopped */
1084 if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
1085 SMSC_WARNING(DRV, "Rx not stopped");
1086
1087 /* Perform the update - safe to do now Rx has stopped */
1088 smsc911x_rx_multicast_update(pdata);
1089
1090 /* Re-enable Rx */
1091 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1092 mac_cr |= MAC_CR_RXEN_;
1093 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1094
1095 pdata->multicast_update_pending = 0;
1096
1097 spin_unlock(&pdata->mac_lock);
1098}
1099
1100static int smsc911x_soft_reset(struct smsc911x_data *pdata)
1101{
1102 unsigned int timeout;
1103 unsigned int temp;
1104
1105 /* Reset the LAN911x */
1106 smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
1107 timeout = 10;
1108 do {
1109 udelay(10);
1110 temp = smsc911x_reg_read(pdata, HW_CFG);
1111 } while ((--timeout) && (temp & HW_CFG_SRST_));
1112
1113 if (unlikely(temp & HW_CFG_SRST_)) {
1114 SMSC_WARNING(DRV, "Failed to complete reset");
1115 return -EIO;
1116 }
1117 return 0;
1118}
1119
1120/* Sets the device MAC address to dev_addr, called with mac_lock held */
1121static void
225ddf49 1122smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
fd9abb3d
SG		 1123{
1124 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
1125 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
1126 (dev_addr[1] << 8) | dev_addr[0];
1127
1128 SMSC_ASSERT_MAC_LOCK(pdata);
1129
1130 smsc911x_mac_write(pdata, ADDRH, mac_high16);
1131 smsc911x_mac_write(pdata, ADDRL, mac_low32);
1132}
1133
1134static int smsc911x_open(struct net_device *dev)
1135{
1136 struct smsc911x_data *pdata = netdev_priv(dev);
1137 unsigned int timeout;
1138 unsigned int temp;
1139 unsigned int intcfg;
1140
1141 /* if the phy is not yet registered, retry later*/
1142 if (!pdata->phy_dev) {
1143 SMSC_WARNING(HW, "phy_dev is NULL");
1144 return -EAGAIN;
1145 }
1146
1147 if (!is_valid_ether_addr(dev->dev_addr)) {
1148 SMSC_WARNING(HW, "dev_addr is not a valid MAC address");
1149 return -EADDRNOTAVAIL;
1150 }
1151
1152 /* Reset the LAN911x */
1153 if (smsc911x_soft_reset(pdata)) {
1154 SMSC_WARNING(HW, "soft reset failed");
1155 return -EIO;
1156 }
1157
1158 smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
1159 smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
1160
1161 /* Make sure EEPROM has finished loading before setting GPIO_CFG */
1162 timeout = 50;
f7efb6cc
SG		 1163 while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
1164 --timeout) {
fd9abb3d
SG		 1165 udelay(10);
1166 }
1167
1168 if (unlikely(timeout == 0))
1169 SMSC_WARNING(IFUP,
1170 "Timed out waiting for EEPROM busy bit to clear");
1171
1172 smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
1173
1174 /* The soft reset above cleared the device's MAC address,
1175 * restore it from local copy (set in probe) */
1176 spin_lock_irq(&pdata->mac_lock);
225ddf49 1177 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 1178 spin_unlock_irq(&pdata->mac_lock);
1179
1180 /* Initialise irqs, but leave all sources disabled */
1181 smsc911x_reg_write(pdata, INT_EN, 0);
1182 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
1183
1184 /* Set interrupt deassertion to 100uS */
1185 intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
1186
2107fb8b 1187 if (pdata->config.irq_polarity) {
fd9abb3d
SG		 1188 SMSC_TRACE(IFUP, "irq polarity: active high");
1189 intcfg |= INT_CFG_IRQ_POL_;
1190 } else {
1191 SMSC_TRACE(IFUP, "irq polarity: active low");
1192 }
1193
2107fb8b 1194 if (pdata->config.irq_type) {
fd9abb3d
SG		 1195 SMSC_TRACE(IFUP, "irq type: push-pull");
1196 intcfg |= INT_CFG_IRQ_TYPE_;
1197 } else {
1198 SMSC_TRACE(IFUP, "irq type: open drain");
1199 }
1200
1201 smsc911x_reg_write(pdata, INT_CFG, intcfg);
1202
1203 SMSC_TRACE(IFUP, "Testing irq handler using IRQ %d", dev->irq);
1204 pdata->software_irq_signal = 0;
1205 smp_wmb();
1206
1207 temp = smsc911x_reg_read(pdata, INT_EN);
1208 temp |= INT_EN_SW_INT_EN_;
1209 smsc911x_reg_write(pdata, INT_EN, temp);
1210
1211 timeout = 1000;
1212 while (timeout--) {
1213 if (pdata->software_irq_signal)
1214 break;
1215 msleep(1);
1216 }
1217
1218 if (!pdata->software_irq_signal) {
1219 dev_warn(&dev->dev, "ISR failed signaling test (IRQ %d)\n",
1220 dev->irq);
1221 return -ENODEV;
1222 }
1223 SMSC_TRACE(IFUP, "IRQ handler passed test using IRQ %d", dev->irq);
1224
1225 dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
1226 (unsigned long)pdata->ioaddr, dev->irq);
1227
44c1d6f9
SG		 1228 /* Reset the last known duplex and carrier */
1229 pdata->last_duplex = -1;
1230 pdata->last_carrier = -1;
1231
fd9abb3d
SG		 1232 /* Bring the PHY up */
1233 phy_start(pdata->phy_dev);
1234
1235 temp = smsc911x_reg_read(pdata, HW_CFG);
1236 /* Preserve TX FIFO size and external PHY configuration */
1237 temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
1238 temp |= HW_CFG_SF_;
1239 smsc911x_reg_write(pdata, HW_CFG, temp);
1240
1241 temp = smsc911x_reg_read(pdata, FIFO_INT);
1242 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1243 temp &= ~(FIFO_INT_RX_STS_LEVEL_);
1244 smsc911x_reg_write(pdata, FIFO_INT, temp);
1245
1246 /* set RX Data offset to 2 bytes for alignment */
1247 smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
1248
1249 /* enable NAPI polling before enabling RX interrupts */
1250 napi_enable(&pdata->napi);
1251
1252 temp = smsc911x_reg_read(pdata, INT_EN);
1373c0fd 1253 temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
fd9abb3d
SG		 1254 smsc911x_reg_write(pdata, INT_EN, temp);
1255
1256 spin_lock_irq(&pdata->mac_lock);
1257 temp = smsc911x_mac_read(pdata, MAC_CR);
1258 temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
1259 smsc911x_mac_write(pdata, MAC_CR, temp);
1260 spin_unlock_irq(&pdata->mac_lock);
1261
1262 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
1263
1264 netif_start_queue(dev);
1265 return 0;
1266}
1267
1268/* Entry point for stopping the interface */
1269static int smsc911x_stop(struct net_device *dev)
1270{
1271 struct smsc911x_data *pdata = netdev_priv(dev);
1272 unsigned int temp;
1273
fd9abb3d
SG		 1274 /* Disable all device interrupts */
1275 temp = smsc911x_reg_read(pdata, INT_CFG);
1276 temp &= ~INT_CFG_IRQ_EN_;
1277 smsc911x_reg_write(pdata, INT_CFG, temp);
1278
1279 /* Stop Tx and Rx polling */
1280 netif_stop_queue(dev);
1281 napi_disable(&pdata->napi);
1282
1283 /* At this point all Rx and Tx activity is stopped */
1284 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1285 smsc911x_tx_update_txcounters(dev);
1286
1287 /* Bring the PHY down */
dd045193
SG		 1288 if (pdata->phy_dev)
1289 phy_stop(pdata->phy_dev);
fd9abb3d
SG		 1290
1291 SMSC_TRACE(IFDOWN, "Interface stopped");
1292 return 0;
1293}
1294
1295/* Entry point for transmitting a packet */
1296static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1297{
1298 struct smsc911x_data *pdata = netdev_priv(dev);
1299 unsigned int freespace;
1300 unsigned int tx_cmd_a;
1301 unsigned int tx_cmd_b;
1302 unsigned int temp;
1303 u32 wrsz;
1304 ulong bufp;
1305
1306 freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
1307
1308 if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
1309 SMSC_WARNING(TX_ERR,
1310 "Tx data fifo low, space available: %d", freespace);
1311
1312 /* Word alignment adjustment */
1313 tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
1314 tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
1315 tx_cmd_a |= (unsigned int)skb->len;
1316
1317 tx_cmd_b = ((unsigned int)skb->len) << 16;
1318 tx_cmd_b |= (unsigned int)skb->len;
1319
1320 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
1321 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
1322
1323 bufp = (ulong)skb->data & (~0x3);
1324 wrsz = (u32)skb->len + 3;
1325 wrsz += (u32)((ulong)skb->data & 0x3);
1326 wrsz >>= 2;
1327
1328 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
1329 freespace -= (skb->len + 32);
1330 dev_kfree_skb(skb);
1331 dev->trans_start = jiffies;
1332
1333 if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
1334 smsc911x_tx_update_txcounters(dev);
1335
1336 if (freespace < TX_FIFO_LOW_THRESHOLD) {
1337 netif_stop_queue(dev);
1338 temp = smsc911x_reg_read(pdata, FIFO_INT);
1339 temp &= 0x00FFFFFF;
1340 temp |= 0x32000000;
1341 smsc911x_reg_write(pdata, FIFO_INT, temp);
1342 }
1343
1344 return NETDEV_TX_OK;
1345}
1346
1347/* Entry point for getting status counters */
1348static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
1349{
1350 struct smsc911x_data *pdata = netdev_priv(dev);
1351 smsc911x_tx_update_txcounters(dev);
1352 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1353 return &dev->stats;
1354}
1355
1356/* Entry point for setting addressing modes */
1357static void smsc911x_set_multicast_list(struct net_device *dev)
1358{
1359 struct smsc911x_data *pdata = netdev_priv(dev);
1360 unsigned long flags;
1361
1362 if (dev->flags & IFF_PROMISC) {
1363 /* Enabling promiscuous mode */
1364 pdata->set_bits_mask = MAC_CR_PRMS_;
1365 pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1366 pdata->hashhi = 0;
1367 pdata->hashlo = 0;
1368 } else if (dev->flags & IFF_ALLMULTI) {
1369 /* Enabling all multicast mode */
1370 pdata->set_bits_mask = MAC_CR_MCPAS_;
1371 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
1372 pdata->hashhi = 0;
1373 pdata->hashlo = 0;
1374 } else if (dev->mc_count > 0) {
1375 /* Enabling specific multicast addresses */
1376 unsigned int hash_high = 0;
1377 unsigned int hash_low = 0;
1378 unsigned int count = 0;
1379 struct dev_mc_list *mc_list = dev->mc_list;
1380
1381 pdata->set_bits_mask = MAC_CR_HPFILT_;
1382 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1383
1384 while (mc_list) {
1385 count++;
1386 if ((mc_list->dmi_addrlen) == ETH_ALEN) {
1387 unsigned int bitnum =
1388 smsc911x_hash(mc_list->dmi_addr);
1389 unsigned int mask = 0x01 << (bitnum & 0x1F);
1390 if (bitnum & 0x20)
1391 hash_high |= mask;
1392 else
1393 hash_low |= mask;
1394 } else {
1395 SMSC_WARNING(DRV, "dmi_addrlen != 6");
1396 }
1397 mc_list = mc_list->next;
1398 }
1399 if (count != (unsigned int)dev->mc_count)
1400 SMSC_WARNING(DRV, "mc_count != dev->mc_count");
1401
1402 pdata->hashhi = hash_high;
1403 pdata->hashlo = hash_low;
1404 } else {
1405 /* Enabling local MAC address only */
1406 pdata->set_bits_mask = 0;
1407 pdata->clear_bits_mask =
1408 (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1409 pdata->hashhi = 0;
1410 pdata->hashlo = 0;
1411 }
1412
1413 spin_lock_irqsave(&pdata->mac_lock, flags);
1414
1415 if (pdata->generation <= 1) {
1416 /* Older hardware revision - cannot change these flags while
1417 * receiving data */
1418 if (!pdata->multicast_update_pending) {
1419 unsigned int temp;
1420 SMSC_TRACE(HW, "scheduling mcast update");
1421 pdata->multicast_update_pending = 1;
1422
1423 /* Request the hardware to stop, then perform the
1424 * update when we get an RX_STOP interrupt */
fd9abb3d
SG		 1425 temp = smsc911x_mac_read(pdata, MAC_CR);
1426 temp &= ~(MAC_CR_RXEN_);
1427 smsc911x_mac_write(pdata, MAC_CR, temp);
1428 } else {
1429 /* There is another update pending, this should now
1430 * use the newer values */
1431 }
1432 } else {
1433 /* Newer hardware revision - can write immediately */
1434 smsc911x_rx_multicast_update(pdata);
1435 }
1436
1437 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1438}
1439
1440static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
1441{
1442 struct net_device *dev = dev_id;
1443 struct smsc911x_data *pdata = netdev_priv(dev);
1444 u32 intsts = smsc911x_reg_read(pdata, INT_STS);
1445 u32 inten = smsc911x_reg_read(pdata, INT_EN);
1446 int serviced = IRQ_NONE;
1447 u32 temp;
1448
1449 if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
1450 temp = smsc911x_reg_read(pdata, INT_EN);
1451 temp &= (~INT_EN_SW_INT_EN_);
1452 smsc911x_reg_write(pdata, INT_EN, temp);
1453 smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
1454 pdata->software_irq_signal = 1;
1455 smp_wmb();
1456 serviced = IRQ_HANDLED;
1457 }
1458
1459 if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
1460 /* Called when there is a multicast update scheduled and
1461 * it is now safe to complete the update */
1462 SMSC_TRACE(INTR, "RX Stop interrupt");
fd9abb3d 1463 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
1373c0fd
SG		 1464 if (pdata->multicast_update_pending)
1465 smsc911x_rx_multicast_update_workaround(pdata);
fd9abb3d
SG		 1466 serviced = IRQ_HANDLED;
1467 }
1468
1469 if (intsts & inten & INT_STS_TDFA_) {
1470 temp = smsc911x_reg_read(pdata, FIFO_INT);
1471 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1472 smsc911x_reg_write(pdata, FIFO_INT, temp);
1473 smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
1474 netif_wake_queue(dev);
1475 serviced = IRQ_HANDLED;
1476 }
1477
1478 if (unlikely(intsts & inten & INT_STS_RXE_)) {
1479 SMSC_TRACE(INTR, "RX Error interrupt");
1480 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
1481 serviced = IRQ_HANDLED;
1482 }
1483
1484 if (likely(intsts & inten & INT_STS_RSFL_)) {
288379f0 1485 if (likely(napi_schedule_prep(&pdata->napi))) {
fd9abb3d
SG		 1486 /* Disable Rx interrupts */
1487 temp = smsc911x_reg_read(pdata, INT_EN);
1488 temp &= (~INT_EN_RSFL_EN_);
1489 smsc911x_reg_write(pdata, INT_EN, temp);
1490 /* Schedule a NAPI poll */
288379f0 1491 __napi_schedule(&pdata->napi);
fd9abb3d
SG		 1492 } else {
1493 SMSC_WARNING(RX_ERR,
288379f0 1494 "napi_schedule_prep failed");
fd9abb3d
SG		 1495 }
1496 serviced = IRQ_HANDLED;
1497 }
1498
1499 return serviced;
1500}
1501
1502#ifdef CONFIG_NET_POLL_CONTROLLER
1757ab2f 1503static void smsc911x_poll_controller(struct net_device *dev)
fd9abb3d
SG		 1504{
1505 disable_irq(dev->irq);
1506 smsc911x_irqhandler(0, dev);
1507 enable_irq(dev->irq);
1508}
1509#endif /* CONFIG_NET_POLL_CONTROLLER */
1510
225ddf49
SG		 1511static int smsc911x_set_mac_address(struct net_device *dev, void *p)
1512{
1513 struct smsc911x_data *pdata = netdev_priv(dev);
1514 struct sockaddr *addr = p;
1515
1516 /* On older hardware revisions we cannot change the mac address
1517 * registers while receiving data. Newer devices can safely change
1518 * this at any time. */
1519 if (pdata->generation <= 1 && netif_running(dev))
1520 return -EBUSY;
1521
1522 if (!is_valid_ether_addr(addr->sa_data))
1523 return -EADDRNOTAVAIL;
1524
1525 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1526
1527 spin_lock_irq(&pdata->mac_lock);
1528 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
1529 spin_unlock_irq(&pdata->mac_lock);
1530
1531 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1532
1533 return 0;
1534}
1535
fd9abb3d
SG		 1536/* Standard ioctls for mii-tool */
1537static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1538{
1539 struct smsc911x_data *pdata = netdev_priv(dev);
1540
1541 if (!netif_running(dev) || !pdata->phy_dev)
1542 return -EINVAL;
1543
1544 return phy_mii_ioctl(pdata->phy_dev, if_mii(ifr), cmd);
1545}
1546
1547static int
1548smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1549{
1550 struct smsc911x_data *pdata = netdev_priv(dev);
1551
1552 cmd->maxtxpkt = 1;
1553 cmd->maxrxpkt = 1;
1554 return phy_ethtool_gset(pdata->phy_dev, cmd);
1555}
1556
1557static int
1558smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1559{
1560 struct smsc911x_data *pdata = netdev_priv(dev);
1561
1562 return phy_ethtool_sset(pdata->phy_dev, cmd);
1563}
1564
1565static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
1566 struct ethtool_drvinfo *info)
1567{
1568 strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
1569 strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
db1d7bf7 1570 strlcpy(info->bus_info, dev_name(dev->dev.parent),
fd9abb3d
SG		 1571 sizeof(info->bus_info));
1572}
1573
1574static int smsc911x_ethtool_nwayreset(struct net_device *dev)
1575{
1576 struct smsc911x_data *pdata = netdev_priv(dev);
1577
1578 return phy_start_aneg(pdata->phy_dev);
1579}
1580
1581static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
1582{
1583 struct smsc911x_data *pdata = netdev_priv(dev);
1584 return pdata->msg_enable;
1585}
1586
1587static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1588{
1589 struct smsc911x_data *pdata = netdev_priv(dev);
1590 pdata->msg_enable = level;
1591}
1592
1593static int smsc911x_ethtool_getregslen(struct net_device *dev)
1594{
1595 return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
1596 sizeof(u32);
1597}
1598
1599static void
1600smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
1601 void *buf)
1602{
1603 struct smsc911x_data *pdata = netdev_priv(dev);
1604 struct phy_device *phy_dev = pdata->phy_dev;
1605 unsigned long flags;
1606 unsigned int i;
1607 unsigned int j = 0;
1608 u32 *data = buf;
1609
1610 regs->version = pdata->idrev;
1611 for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
1612 data[j++] = smsc911x_reg_read(pdata, i);
1613
1614 for (i = MAC_CR; i <= WUCSR; i++) {
1615 spin_lock_irqsave(&pdata->mac_lock, flags);
1616 data[j++] = smsc911x_mac_read(pdata, i);
1617 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1618 }
1619
1620 for (i = 0; i <= 31; i++)
1621 data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
1622}
1623
1624static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
1625{
1626 unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
1627 temp &= ~GPIO_CFG_EEPR_EN_;
1628 smsc911x_reg_write(pdata, GPIO_CFG, temp);
1629 msleep(1);
1630}
1631
1632static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
1633{
1634 int timeout = 100;
1635 u32 e2cmd;
1636
1637 SMSC_TRACE(DRV, "op 0x%08x", op);
1638 if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
1639 SMSC_WARNING(DRV, "Busy at start");
1640 return -EBUSY;
1641 }
1642
1643 e2cmd = op | E2P_CMD_EPC_BUSY_;
1644 smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
1645
1646 do {
1647 msleep(1);
1648 e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
2cf0dbed 1649 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
fd9abb3d
SG		 1650
1651 if (!timeout) {
1652 SMSC_TRACE(DRV, "TIMED OUT");
1653 return -EAGAIN;
1654 }
1655
1656 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
1657 SMSC_TRACE(DRV, "Error occured during eeprom operation");
1658 return -EINVAL;
1659 }
1660
1661 return 0;
1662}
1663
1664static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
1665 u8 address, u8 *data)
1666{
1667 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
1668 int ret;
1669
1670 SMSC_TRACE(DRV, "address 0x%x", address);
1671 ret = smsc911x_eeprom_send_cmd(pdata, op);
1672
1673 if (!ret)
1674 data[address] = smsc911x_reg_read(pdata, E2P_DATA);
1675
1676 return ret;
1677}
1678
1679static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
1680 u8 address, u8 data)
1681{
1682 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
1683 int ret;
1684
1685 SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
1686 ret = smsc911x_eeprom_send_cmd(pdata, op);
1687
1688 if (!ret) {
1689 op = E2P_CMD_EPC_CMD_WRITE_ | address;
1690 smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
1691 ret = smsc911x_eeprom_send_cmd(pdata, op);
1692 }
1693
1694 return ret;
1695}
1696
1697static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
1698{
1699 return SMSC911X_EEPROM_SIZE;
1700}
1701
1702static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
1703 struct ethtool_eeprom *eeprom, u8 *data)
1704{
1705 struct smsc911x_data *pdata = netdev_priv(dev);
1706 u8 eeprom_data[SMSC911X_EEPROM_SIZE];
1707 int len;
1708 int i;
1709
1710 smsc911x_eeprom_enable_access(pdata);
1711
1712 len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
1713 for (i = 0; i < len; i++) {
1714 int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
1715 if (ret < 0) {
1716 eeprom->len = 0;
1717 return ret;
1718 }
1719 }
1720
1721 memcpy(data, &eeprom_data[eeprom->offset], len);
1722 eeprom->len = len;
1723 return 0;
1724}
1725
1726static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
1727 struct ethtool_eeprom *eeprom, u8 *data)
1728{
1729 int ret;
1730 struct smsc911x_data *pdata = netdev_priv(dev);
1731
1732 smsc911x_eeprom_enable_access(pdata);
1733 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
1734 ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
1735 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
1736
1737 /* Single byte write, according to man page */
1738 eeprom->len = 1;
1739
1740 return ret;
1741}
1742
cb5b04fe 1743static const struct ethtool_ops smsc911x_ethtool_ops = {
fd9abb3d
SG		 1744 .get_settings = smsc911x_ethtool_getsettings,
1745 .set_settings = smsc911x_ethtool_setsettings,
1746 .get_link = ethtool_op_get_link,
1747 .get_drvinfo = smsc911x_ethtool_getdrvinfo,
1748 .nway_reset = smsc911x_ethtool_nwayreset,
1749 .get_msglevel = smsc911x_ethtool_getmsglevel,
1750 .set_msglevel = smsc911x_ethtool_setmsglevel,
1751 .get_regs_len = smsc911x_ethtool_getregslen,
1752 .get_regs = smsc911x_ethtool_getregs,
1753 .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
1754 .get_eeprom = smsc911x_ethtool_get_eeprom,
1755 .set_eeprom = smsc911x_ethtool_set_eeprom,
1756};
1757
631b7568
SG		 1758static const struct net_device_ops smsc911x_netdev_ops = {
1759 .ndo_open = smsc911x_open,
1760 .ndo_stop = smsc911x_stop,
1761 .ndo_start_xmit = smsc911x_hard_start_xmit,
1762 .ndo_get_stats = smsc911x_get_stats,
1763 .ndo_set_multicast_list = smsc911x_set_multicast_list,
1764 .ndo_do_ioctl = smsc911x_do_ioctl,
1765 .ndo_validate_addr = eth_validate_addr,
225ddf49 1766 .ndo_set_mac_address = smsc911x_set_mac_address,
631b7568
SG		 1767#ifdef CONFIG_NET_POLL_CONTROLLER
1768 .ndo_poll_controller = smsc911x_poll_controller,
1769#endif
1770};
1771
31f45747
SG		 1772/* copies the current mac address from hardware to dev->dev_addr */
1773static void __devinit smsc911x_read_mac_address(struct net_device *dev)
1774{
1775 struct smsc911x_data *pdata = netdev_priv(dev);
1776 u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
1777 u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
1778
1779 dev->dev_addr[0] = (u8)(mac_low32);
1780 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
1781 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
1782 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
1783 dev->dev_addr[4] = (u8)(mac_high16);
1784 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
1785}
1786
fd9abb3d
SG		 1787/* Initializing private device structures, only called from probe */
1788static int __devinit smsc911x_init(struct net_device *dev)
1789{
1790 struct smsc911x_data *pdata = netdev_priv(dev);
1791 unsigned int byte_test;
1792
1793 SMSC_TRACE(PROBE, "Driver Parameters:");
1794 SMSC_TRACE(PROBE, "LAN base: 0x%08lX",
1795 (unsigned long)pdata->ioaddr);
1796 SMSC_TRACE(PROBE, "IRQ: %d", dev->irq);
1797 SMSC_TRACE(PROBE, "PHY will be autodetected.");
1798
fd9abb3d 1799 spin_lock_init(&pdata->dev_lock);
fd9abb3d
SG		 1800
1801 if (pdata->ioaddr == 0) {
1802 SMSC_WARNING(PROBE, "pdata->ioaddr: 0x00000000");
1803 return -ENODEV;
1804 }
1805
1806 /* Check byte ordering */
1807 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1808 SMSC_TRACE(PROBE, "BYTE_TEST: 0x%08X", byte_test);
1809 if (byte_test == 0x43218765) {
1810 SMSC_TRACE(PROBE, "BYTE_TEST looks swapped, "
1811 "applying WORD_SWAP");
1812 smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
1813
1814 /* 1 dummy read of BYTE_TEST is needed after a write to
1815 * WORD_SWAP before its contents are valid */
1816 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1817
1818 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1819 }
1820
1821 if (byte_test != 0x87654321) {
1822 SMSC_WARNING(DRV, "BYTE_TEST: 0x%08X", byte_test);
1823 if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
1824 SMSC_WARNING(PROBE,
1825 "top 16 bits equal to bottom 16 bits");
1826 SMSC_TRACE(PROBE, "This may mean the chip is set "
1827 "for 32 bit while the bus is reading 16 bit");
1828 }
1829 return -ENODEV;
1830 }
1831
1832 /* Default generation to zero (all workarounds apply) */
1833 pdata->generation = 0;
1834
1835 pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
1836 switch (pdata->idrev & 0xFFFF0000) {
1837 case 0x01180000:
1838 case 0x01170000:
1839 case 0x01160000:
1840 case 0x01150000:
1841 /* LAN911[5678] family */
1842 pdata->generation = pdata->idrev & 0x0000FFFF;
1843 break;
1844
1845 case 0x118A0000:
1846 case 0x117A0000:
1847 case 0x116A0000:
1848 case 0x115A0000:
1849 /* LAN921[5678] family */
1850 pdata->generation = 3;
1851 break;
1852
1853 case 0x92100000:
1854 case 0x92110000:
1855 case 0x92200000:
1856 case 0x92210000:
1857 /* LAN9210/LAN9211/LAN9220/LAN9221 */
1858 pdata->generation = 4;
1859 break;
1860
1861 default:
1862 SMSC_WARNING(PROBE, "LAN911x not identified, idrev: 0x%08X",
1863 pdata->idrev);
1864 return -ENODEV;
1865 }
1866
1867 SMSC_TRACE(PROBE, "LAN911x identified, idrev: 0x%08X, generation: %d",
1868 pdata->idrev, pdata->generation);
1869
1870 if (pdata->generation == 0)
1871 SMSC_WARNING(PROBE,
1872 "This driver is not intended for this chip revision");
1873
31f45747
SG		 1874 /* workaround for platforms without an eeprom, where the mac address
1875 * is stored elsewhere and set by the bootloader. This saves the
1876 * mac address before resetting the device */
1877 if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS)
1878 smsc911x_read_mac_address(dev);
1879
fd9abb3d
SG		 1880 /* Reset the LAN911x */
1881 if (smsc911x_soft_reset(pdata))
1882 return -ENODEV;
1883
1884 /* Disable all interrupt sources until we bring the device up */
1885 smsc911x_reg_write(pdata, INT_EN, 0);
1886
1887 ether_setup(dev);
fd9abb3d 1888 dev->flags |= IFF_MULTICAST;
fd9abb3d 1889 netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
631b7568 1890 dev->netdev_ops = &smsc911x_netdev_ops;
fd9abb3d
SG		 1891 dev->ethtool_ops = &smsc911x_ethtool_ops;
1892
fd9abb3d
SG		 1893 return 0;
1894}
1895
1896static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
1897{
1898 struct net_device *dev;
1899 struct smsc911x_data *pdata;
1900 struct resource *res;
1901
1902 dev = platform_get_drvdata(pdev);
1903 BUG_ON(!dev);
1904 pdata = netdev_priv(dev);
1905 BUG_ON(!pdata);
1906 BUG_ON(!pdata->ioaddr);
1907 BUG_ON(!pdata->phy_dev);
1908
1909 SMSC_TRACE(IFDOWN, "Stopping driver.");
1910
1911 phy_disconnect(pdata->phy_dev);
1912 pdata->phy_dev = NULL;
1913 mdiobus_unregister(pdata->mii_bus);
1914 mdiobus_free(pdata->mii_bus);
1915
1916 platform_set_drvdata(pdev, NULL);
1917 unregister_netdev(dev);
1918 free_irq(dev->irq, dev);
1919 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1920 "smsc911x-memory");
1921 if (!res)
d4522739 1922 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fd9abb3d
SG		 1923
1924 release_mem_region(res->start, res->end - res->start);
1925
1926 iounmap(pdata->ioaddr);
1927
1928 free_netdev(dev);
1929
1930 return 0;
1931}
1932
1933static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
1934{
1935 struct net_device *dev;
1936 struct smsc911x_data *pdata;
2107fb8b 1937 struct smsc911x_platform_config *config = pdev->dev.platform_data;
61307ed8 1938 struct resource *res, *irq_res;
fd9abb3d 1939 unsigned int intcfg = 0;
61307ed8 1940 int res_size, irq_flags;
fd9abb3d 1941 int retval;
fd9abb3d
SG		 1942
1943 pr_info("%s: Driver version %s.\n", SMSC_CHIPNAME, SMSC_DRV_VERSION);
1944
2107fb8b
SG		 1945 /* platform data specifies irq & dynamic bus configuration */
1946 if (!pdev->dev.platform_data) {
1947 pr_warning("%s: platform_data not provided\n", SMSC_CHIPNAME);
1948 retval = -ENODEV;
1949 goto out_0;
1950 }
1951
fd9abb3d
SG		 1952 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1953 "smsc911x-memory");
1954 if (!res)
1955 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1956 if (!res) {
1957 pr_warning("%s: Could not allocate resource.\n",
1958 SMSC_CHIPNAME);
1959 retval = -ENODEV;
1960 goto out_0;
1961 }
1962 res_size = res->end - res->start;
1963
61307ed8
SG		 1964 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1965 if (!irq_res) {
1966 pr_warning("%s: Could not allocate irq resource.\n",
1967 SMSC_CHIPNAME);
1968 retval = -ENODEV;
1969 goto out_0;
1970 }
1971
fd9abb3d
SG		 1972 if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
1973 retval = -EBUSY;
1974 goto out_0;
1975 }
1976
1977 dev = alloc_etherdev(sizeof(struct smsc911x_data));
1978 if (!dev) {
1979 pr_warning("%s: Could not allocate device.\n", SMSC_CHIPNAME);
1980 retval = -ENOMEM;
1981 goto out_release_io_1;
1982 }
1983
1984 SET_NETDEV_DEV(dev, &pdev->dev);
1985
1986 pdata = netdev_priv(dev);
1987
61307ed8
SG		 1988 dev->irq = irq_res->start;
1989 irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
fd9abb3d
SG		 1990 pdata->ioaddr = ioremap_nocache(res->start, res_size);
1991
2107fb8b
SG		 1992 /* copy config parameters across to pdata */
1993 memcpy(&pdata->config, config, sizeof(pdata->config));
fd9abb3d
SG		 1994
1995 pdata->dev = dev;
1996 pdata->msg_enable = ((1 << debug) - 1);
1997
1998 if (pdata->ioaddr == NULL) {
1999 SMSC_WARNING(PROBE,
2000 "Error smsc911x base address invalid");
2001 retval = -ENOMEM;
2002 goto out_free_netdev_2;
2003 }
2004
2005 retval = smsc911x_init(dev);
2006 if (retval < 0)
2007 goto out_unmap_io_3;
2008
2009 /* configure irq polarity and type before connecting isr */
2107fb8b 2010 if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
fd9abb3d
SG		 2011 intcfg |= INT_CFG_IRQ_POL_;
2012
2107fb8b 2013 if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
fd9abb3d
SG		 2014 intcfg |= INT_CFG_IRQ_TYPE_;
2015
2016 smsc911x_reg_write(pdata, INT_CFG, intcfg);
2017
2018 /* Ensure interrupts are globally disabled before connecting ISR */
2019 smsc911x_reg_write(pdata, INT_EN, 0);
2020 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
2021
61307ed8 2022 retval = request_irq(dev->irq, smsc911x_irqhandler,
e81259b4 2023 irq_flags | IRQF_SHARED, dev->name, dev);
fd9abb3d
SG		 2024 if (retval) {
2025 SMSC_WARNING(PROBE,
2026 "Unable to claim requested irq: %d", dev->irq);
2027 goto out_unmap_io_3;
2028 }
2029
2030 platform_set_drvdata(pdev, dev);
2031
2032 retval = register_netdev(dev);
2033 if (retval) {
2034 SMSC_WARNING(PROBE,
2035 "Error %i registering device", retval);
2036 goto out_unset_drvdata_4;
2037 } else {
2038 SMSC_TRACE(PROBE, "Network interface: \"%s\"", dev->name);
2039 }
2040
2041 spin_lock_init(&pdata->mac_lock);
2042
2043 retval = smsc911x_mii_init(pdev, dev);
2044 if (retval) {
2045 SMSC_WARNING(PROBE,
2046 "Error %i initialising mii", retval);
2047 goto out_unregister_netdev_5;
2048 }
2049
2050 spin_lock_irq(&pdata->mac_lock);
2051
2052 /* Check if mac address has been specified when bringing interface up */
2053 if (is_valid_ether_addr(dev->dev_addr)) {
225ddf49 2054 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 2055 SMSC_TRACE(PROBE, "MAC Address is specified by configuration");
2056 } else {
2057 /* Try reading mac address from device. if EEPROM is present
2058 * it will already have been set */
31f45747 2059 smsc911x_read_mac_address(dev);
fd9abb3d
SG		 2060
2061 if (is_valid_ether_addr(dev->dev_addr)) {
2062 /* eeprom values are valid so use them */
2063 SMSC_TRACE(PROBE,
2064 "Mac Address is read from LAN911x EEPROM");
2065 } else {
2066 /* eeprom values are invalid, generate random MAC */
2067 random_ether_addr(dev->dev_addr);
225ddf49 2068 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
fd9abb3d
SG		 2069 SMSC_TRACE(PROBE,
2070 "MAC Address is set to random_ether_addr");
2071 }
2072 }
2073
2074 spin_unlock_irq(&pdata->mac_lock);
2075
63a2ebb0 2076 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
fd9abb3d
SG		 2077
2078 return 0;
2079
2080out_unregister_netdev_5:
2081 unregister_netdev(dev);
2082out_unset_drvdata_4:
2083 platform_set_drvdata(pdev, NULL);
2084 free_irq(dev->irq, dev);
2085out_unmap_io_3:
2086 iounmap(pdata->ioaddr);
2087out_free_netdev_2:
2088 free_netdev(dev);
2089out_release_io_1:
2090 release_mem_region(res->start, res->end - res->start);
2091out_0:
2092 return retval;
2093}
2094
2095static struct platform_driver smsc911x_driver = {
2096 .probe = smsc911x_drv_probe,
2097 .remove = smsc911x_drv_remove,
2098 .driver = {
2099 .name = SMSC_CHIPNAME,
2100 },
2101};
2102
2103/* Entry point for loading the module */
2104static int __init smsc911x_init_module(void)
2105{
2106 return platform_driver_register(&smsc911x_driver);
2107}
2108
2109/* entry point for unloading the module */
2110static void __exit smsc911x_cleanup_module(void)
2111{
2112 platform_driver_unregister(&smsc911x_driver);
2113}
2114
2115module_init(smsc911x_init_module);
2116module_exit(smsc911x_cleanup_module);
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