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[PATCH] sky2: allow dual port usage
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
cd28ab6a 26#include <linux/config.h>
793b883e 27#include <linux/crc32.h>
cd28ab6a
SH		 28#include <linux/kernel.h>
29#include <linux/version.h>
30#include <linux/module.h>
31#include <linux/netdevice.h>
d0bbccfa 32#include <linux/dma-mapping.h>
cd28ab6a
SH		 33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/in.h>
39#include <linux/delay.h>
91c86df5 40#include <linux/workqueue.h>
d1f13708 41#include <linux/if_vlan.h>
d70cd51a 42#include <linux/prefetch.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
6d4b0f61 54#define DRV_VERSION "1.3"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
62 */
63
13210ce5 64#define RX_LE_SIZE 512
cd28ab6a 65#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 66#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 67#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 68#define RX_SKB_ALIGN 8
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
bdb5c58e
SH		 93static int copybreak __read_mostly = 256;
94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
01bd7564
SH		 101static int idle_timeout = 100;
102module_param(idle_timeout, int, 0);
103MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
cd28ab6a 105static const struct pci_device_id sky2_id_table[] = {
793b883e 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
cd28ab6a
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 123 { 0 }
124};
793b883e 125
cd28ab6a
SH		 126MODULE_DEVICE_TABLE(pci, sky2_id_table);
127
128/* Avoid conditionals by using array */
129static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
130static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 131static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 132
92f965e8
SH		 133/* This driver supports yukon2 chipset only */
134static const char *yukon2_name[] = {
135 "XL", /* 0xb3 */
136 "EC Ultra", /* 0xb4 */
137 "UNKNOWN", /* 0xb5 */
138 "EC", /* 0xb6 */
139 "FE", /* 0xb7 */
793b883e
SH		 140};
141
793b883e 142/* Access to external PHY */
ef743d33 143static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 144{
145 int i;
146
147 gma_write16(hw, port, GM_SMI_DATA, val);
148 gma_write16(hw, port, GM_SMI_CTRL,
149 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
150
151 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 152 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 153 return 0;
793b883e 154 udelay(1);
cd28ab6a 155 }
ef743d33 156
793b883e 157 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 158 return -ETIMEDOUT;
cd28ab6a
SH		 159}
160
ef743d33 161static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 162{
163 int i;
164
793b883e 165 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 166 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
167
168 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 169 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
170 *val = gma_read16(hw, port, GM_SMI_DATA);
171 return 0;
172 }
173
793b883e 174 udelay(1);
cd28ab6a
SH		 175 }
176
ef743d33
SH		 177 return -ETIMEDOUT;
178}
179
180static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
181{
182 u16 v;
183
184 if (__gm_phy_read(hw, port, reg, &v) != 0)
185 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
186 return v;
cd28ab6a
SH		 187}
188
5afa0a9c
SH		 189static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
190{
191 u16 power_control;
192 u32 reg1;
193 int vaux;
194 int ret = 0;
195
196 pr_debug("sky2_set_power_state %d\n", state);
197 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
198
56a645cc 199 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 200 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c
SH		 201 (power_control & PCI_PM_CAP_PME_D3cold);
202
56a645cc 203 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c
SH		 204
205 power_control |= PCI_PM_CTRL_PME_STATUS;
206 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
207
208 switch (state) {
209 case PCI_D0:
210 /* switch power to VCC (WA for VAUX problem) */
211 sky2_write8(hw, B0_POWER_CTRL,
212 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
213
214 /* disable Core Clock Division, */
215 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
216
217 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
218 /* enable bits are inverted */
219 sky2_write8(hw, B2_Y2_CLK_GATE,
220 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
221 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
222 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
223 else
224 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
225
226 /* Turn off phy power saving */
56a645cc 227 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c
SH		 228 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
229
d571b694 230 /* looks like this XL is back asswards .. */
5afa0a9c
SH		 231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
232 reg1 |= PCI_Y2_PHY1_COMA;
233 if (hw->ports > 1)
234 reg1 |= PCI_Y2_PHY2_COMA;
235 }
977bdf06
SH		 236
237 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
56a645cc
SH		 238 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
239 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 240 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 241 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
242 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 243 }
244
56a645cc 245 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
977bdf06 246
5afa0a9c
SH		 247 break;
248
249 case PCI_D3hot:
250 case PCI_D3cold:
251 /* Turn on phy power saving */
56a645cc 252 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c
SH		 253 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
254 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
255 else
256 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
56a645cc 257 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
5afa0a9c
SH		 258
259 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
260 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
261 else
262 /* enable bits are inverted */
263 sky2_write8(hw, B2_Y2_CLK_GATE,
264 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
265 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
266 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
267
268 /* switch power to VAUX */
269 if (vaux && state != PCI_D3cold)
270 sky2_write8(hw, B0_POWER_CTRL,
271 (PC_VAUX_ENA | PC_VCC_ENA |
272 PC_VAUX_ON | PC_VCC_OFF));
273 break;
274 default:
275 printk(KERN_ERR PFX "Unknown power state %d\n", state);
276 ret = -1;
277 }
278
56a645cc 279 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c
SH		 280 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
281 return ret;
282}
283
cd28ab6a
SH		 284static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
285{
286 u16 reg;
287
288 /* disable all GMAC IRQ's */
289 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
290 /* disable PHY IRQs */
291 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 292
cd28ab6a
SH		 293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
294 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
297
298 reg = gma_read16(hw, port, GM_RX_CTRL);
299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
300 gma_write16(hw, port, GM_RX_CTRL, reg);
301}
302
303static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
304{
305 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 306 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 307
ed6d32c7
SH		 308 if (sky2->autoneg == AUTONEG_ENABLE &&
309 (hw->chip_id != CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 310 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
311
312 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 313 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 314 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
315
316 if (hw->chip_id == CHIP_ID_YUKON_EC)
317 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
318 else
319 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
320
321 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
322 }
323
324 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
325 if (hw->copper) {
326 if (hw->chip_id == CHIP_ID_YUKON_FE) {
327 /* enable automatic crossover */
328 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
329 } else {
330 /* disable energy detect */
331 ctrl &= ~PHY_M_PC_EN_DET_MSK;
332
333 /* enable automatic crossover */
334 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
335
336 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 337 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 338 ctrl &= ~PHY_M_PC_DSC_MSK;
339 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
340 }
341 }
342 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
343 } else {
344 /* workaround for deviation #4.88 (CRC errors) */
345 /* disable Automatic Crossover */
346
347 ctrl &= ~PHY_M_PC_MDIX_MSK;
348 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
349
350 if (hw->chip_id == CHIP_ID_YUKON_XL) {
351 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
352 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
354 ctrl &= ~PHY_M_MAC_MD_MSK;
355 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
356 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
357
358 /* select page 1 to access Fiber registers */
359 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
360 }
cd28ab6a
SH		 361 }
362
363 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
364 if (sky2->autoneg == AUTONEG_DISABLE)
365 ctrl &= ~PHY_CT_ANE;
366 else
367 ctrl |= PHY_CT_ANE;
368
369 ctrl |= PHY_CT_RESET;
370 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
371
372 ctrl = 0;
373 ct1000 = 0;
374 adv = PHY_AN_CSMA;
375
376 if (sky2->autoneg == AUTONEG_ENABLE) {
377 if (hw->copper) {
378 if (sky2->advertising & ADVERTISED_1000baseT_Full)
379 ct1000 |= PHY_M_1000C_AFD;
380 if (sky2->advertising & ADVERTISED_1000baseT_Half)
381 ct1000 |= PHY_M_1000C_AHD;
382 if (sky2->advertising & ADVERTISED_100baseT_Full)
383 adv |= PHY_M_AN_100_FD;
384 if (sky2->advertising & ADVERTISED_100baseT_Half)
385 adv |= PHY_M_AN_100_HD;
386 if (sky2->advertising & ADVERTISED_10baseT_Full)
387 adv |= PHY_M_AN_10_FD;
388 if (sky2->advertising & ADVERTISED_10baseT_Half)
389 adv |= PHY_M_AN_10_HD;
793b883e 390 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 391 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
392
393 /* Set Flow-control capabilities */
394 if (sky2->tx_pause && sky2->rx_pause)
793b883e 395 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 396 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 397 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 398 else if (!sky2->rx_pause && sky2->tx_pause)
399 adv |= PHY_AN_PAUSE_ASYM; /* local */
400
401 /* Restart Auto-negotiation */
402 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
403 } else {
404 /* forced speed/duplex settings */
405 ct1000 = PHY_M_1000C_MSE;
406
407 if (sky2->duplex == DUPLEX_FULL)
408 ctrl |= PHY_CT_DUP_MD;
409
410 switch (sky2->speed) {
411 case SPEED_1000:
412 ctrl |= PHY_CT_SP1000;
413 break;
414 case SPEED_100:
415 ctrl |= PHY_CT_SP100;
416 break;
417 }
418
419 ctrl |= PHY_CT_RESET;
420 }
421
422 if (hw->chip_id != CHIP_ID_YUKON_FE)
423 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
424
425 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
426 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
427
428 /* Setup Phy LED's */
429 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
430 ledover = 0;
431
432 switch (hw->chip_id) {
433 case CHIP_ID_YUKON_FE:
434 /* on 88E3082 these bits are at 11..9 (shifted left) */
435 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
436
437 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
438
439 /* delete ACT LED control bits */
440 ctrl &= ~PHY_M_FELP_LED1_MSK;
441 /* change ACT LED control to blink mode */
442 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
443 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
444 break;
445
446 case CHIP_ID_YUKON_XL:
793b883e 447 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 448
449 /* select page 3 to access LED control register */
450 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
451
452 /* set LED Function Control register */
ed6d32c7
SH		 453 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
454 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
455 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
456 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
457 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 458
459 /* set Polarity Control register */
460 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 461 (PHY_M_POLC_LS1_P_MIX(4) |
462 PHY_M_POLC_IS0_P_MIX(4) |
463 PHY_M_POLC_LOS_CTRL(2) |
464 PHY_M_POLC_INIT_CTRL(2) |
465 PHY_M_POLC_STA1_CTRL(2) |
466 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 467
468 /* restore page register */
793b883e 469 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 470 break;
ed6d32c7
SH		 471 case CHIP_ID_YUKON_EC_U:
472 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
473
474 /* select page 3 to access LED control register */
475 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
476
477 /* set LED Function Control register */
478 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
479 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
480 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
481 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
482 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
483
484 /* set Blink Rate in LED Timer Control Register */
485 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
486 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
487 /* restore page register */
488 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
489 break;
cd28ab6a
SH		 490
491 default:
492 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
493 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
494 /* turn off the Rx LED (LED_RX) */
495 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
496 }
497
ed6d32c7 498 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 499 /* apply fixes in PHY AFE */
ed6d32c7
SH		 500 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
501 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
502
977bdf06 503 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 504 gm_phy_write(hw, port, 0x18, 0xaa99);
505 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 506
977bdf06 507 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 508 gm_phy_write(hw, port, 0x18, 0xa204);
509 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 510
511 /* set page register to 0 */
ed6d32c7 512 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 513 } else {
514 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 515
977bdf06
SH		 516 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
517 /* turn on 100 Mbps LED (LED_LINK100) */
518 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
519 }
cd28ab6a 520
977bdf06
SH		 521 if (ledover)
522 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
523
524 }
d571b694 525 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 526 if (sky2->autoneg == AUTONEG_ENABLE)
527 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
528 else
529 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
530}
531
1b537565
SH		 532/* Force a renegotiation */
533static void sky2_phy_reinit(struct sky2_port *sky2)
534{
e07b1aa8 535 spin_lock_bh(&sky2->phy_lock);
1b537565 536 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 537 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 538}
539
cd28ab6a
SH		 540static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
541{
542 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
543 u16 reg;
544 int i;
545 const u8 *addr = hw->dev[port]->dev_addr;
546
42eeea01
SH		 547 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
548 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 549
550 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
551
793b883e 552 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 553 /* WA DEV_472 -- looks like crossed wires on port 2 */
554 /* clear GMAC 1 Control reset */
555 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
556 do {
557 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
558 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
559 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
560 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
561 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
562 }
563
cd28ab6a
SH		 564 if (sky2->autoneg == AUTONEG_DISABLE) {
565 reg = gma_read16(hw, port, GM_GP_CTRL);
566 reg |= GM_GPCR_AU_ALL_DIS;
567 gma_write16(hw, port, GM_GP_CTRL, reg);
568 gma_read16(hw, port, GM_GP_CTRL);
569
cd28ab6a
SH		 570 switch (sky2->speed) {
571 case SPEED_1000:
6f4c56b2 572 reg &= ~GM_GPCR_SPEED_100;
cd28ab6a 573 reg |= GM_GPCR_SPEED_1000;
6f4c56b2 574 break;
cd28ab6a 575 case SPEED_100:
6f4c56b2 576 reg &= ~GM_GPCR_SPEED_1000;
cd28ab6a 577 reg |= GM_GPCR_SPEED_100;
6f4c56b2
SH		 578 break;
579 case SPEED_10:
580 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
581 break;
cd28ab6a
SH		 582 }
583
584 if (sky2->duplex == DUPLEX_FULL)
585 reg |= GM_GPCR_DUP_FULL;
ed6d32c7
SH		 586
587 /* turn off pause in 10/100mbps half duplex */
588 else if (sky2->speed != SPEED_1000 &&
589 hw->chip_id != CHIP_ID_YUKON_EC_U)
590 sky2->tx_pause = sky2->rx_pause = 0;
cd28ab6a
SH		 591 } else
592 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
593
594 if (!sky2->tx_pause && !sky2->rx_pause) {
595 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 596 reg |=
597 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
598 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 599 /* disable Rx flow-control */
600 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
601 }
602
603 gma_write16(hw, port, GM_GP_CTRL, reg);
604
793b883e 605 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 606
e07b1aa8 607 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 608 sky2_phy_init(hw, port);
e07b1aa8 609 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 610
611 /* MIB clear */
612 reg = gma_read16(hw, port, GM_PHY_ADDR);
613 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
614
43f2f104
SH		 615 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
616 gma_read16(hw, port, i);
cd28ab6a
SH		 617 gma_write16(hw, port, GM_PHY_ADDR, reg);
618
619 /* transmit control */
620 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
621
622 /* receive control reg: unicast + multicast + no FCS */
623 gma_write16(hw, port, GM_RX_CTRL,
793b883e 624 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 625
626 /* transmit flow control */
627 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
628
629 /* transmit parameter */
630 gma_write16(hw, port, GM_TX_PARAM,
631 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
632 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
633 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
634 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
635
636 /* serial mode register */
637 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 638 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 639
6b1a3aef 640 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 641 reg |= GM_SMOD_JUMBO_ENA;
642
643 gma_write16(hw, port, GM_SERIAL_MODE, reg);
644
cd28ab6a
SH		 645 /* virtual address for data */
646 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
647
793b883e
SH		 648 /* physical address: used for pause frames */
649 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
650
651 /* ignore counter overflows */
cd28ab6a
SH		 652 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
653 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
654 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
655
656 /* Configure Rx MAC FIFO */
657 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 658 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
659 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 660
d571b694 661 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 662 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 663
793b883e
SH		 664 /* Set threshold to 0xa (64 bytes)
665 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 666 */
667 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
668
669 /* Configure Tx MAC FIFO */
670 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
671 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 672
673 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
674 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
675 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
676 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
677 /* set Tx GMAC FIFO Almost Empty Threshold */
678 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
679 /* Disable Store & Forward mode for TX */
680 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
681 }
682 }
683
cd28ab6a
SH		 684}
685
1c28f6ba
SH		 686/* Assign Ram Buffer allocation.
687 * start and end are in units of 4k bytes
688 * ram registers are in units of 64bit words
689 */
690static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 691{
1c28f6ba 692 u32 start, end;
cd28ab6a 693
1c28f6ba
SH		 694 start = startk * 4096/8;
695 end = (endk * 4096/8) - 1;
793b883e 696
cd28ab6a
SH		 697 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
698 sky2_write32(hw, RB_ADDR(q, RB_START), start);
699 sky2_write32(hw, RB_ADDR(q, RB_END), end);
700 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
701 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
702
703 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 704 u32 space = (endk - startk) * 4096/8;
705 u32 tp = space - space/4;
793b883e 706
1c28f6ba
SH		 707 /* On receive queue's set the thresholds
708 * give receiver priority when > 3/4 full
709 * send pause when down to 2K
710 */
711 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
712 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 713
1c28f6ba
SH		 714 tp = space - 2048/8;
715 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
716 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 717 } else {
718 /* Enable store & forward on Tx queue's because
719 * Tx FIFO is only 1K on Yukon
720 */
721 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
722 }
723
724 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 725 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 726}
727
cd28ab6a 728/* Setup Bus Memory Interface */
af4ed7e6 729static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 730{
731 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
732 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
733 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 734 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 735}
736
cd28ab6a
SH		 737/* Setup prefetch unit registers. This is the interface between
738 * hardware and driver list elements
739 */
8cc048e3 740static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 741 u64 addr, u32 last)
742{
cd28ab6a
SH		 743 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
744 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
745 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
746 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
747 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
748 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 749
750 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 751}
752
793b883e
SH		 753static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
754{
755 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
756
cb5d9547 757 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
793b883e
SH		 758 return le;
759}
cd28ab6a 760
290d4de5
SH		 761/* Update chip's next pointer */
762static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 763{
762c2de2 764 wmb();
290d4de5 765 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
762c2de2 766 mmiowb();
cd28ab6a
SH		 767}
768
793b883e 769
cd28ab6a
SH		 770static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
771{
772 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 773 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
cd28ab6a
SH		 774 return le;
775}
776
a018e330
SH		 777/* Return high part of DMA address (could be 32 or 64 bit) */
778static inline u32 high32(dma_addr_t a)
779{
a036119f 780 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 781}
782
793b883e 783/* Build description to hardware about buffer */
28bd181a 784static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 785{
786 struct sky2_rx_le *le;
734d1868
SH		 787 u32 hi = high32(map);
788 u16 len = sky2->rx_bufsize;
cd28ab6a 789
793b883e 790 if (sky2->rx_addr64 != hi) {
cd28ab6a 791 le = sky2_next_rx(sky2);
793b883e 792 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 793 le->ctrl = 0;
794 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 795 sky2->rx_addr64 = high32(map + len);
cd28ab6a 796 }
793b883e 797
cd28ab6a 798 le = sky2_next_rx(sky2);
734d1868
SH		 799 le->addr = cpu_to_le32((u32) map);
800 le->length = cpu_to_le16(len);
cd28ab6a
SH		 801 le->ctrl = 0;
802 le->opcode = OP_PACKET | HW_OWNER;
803}
804
793b883e 805
cd28ab6a
SH		 806/* Tell chip where to start receive checksum.
807 * Actually has two checksums, but set both same to avoid possible byte
808 * order problems.
809 */
793b883e 810static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 811{
812 struct sky2_rx_le *le;
813
cd28ab6a 814 le = sky2_next_rx(sky2);
793b883e 815 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 816 le->ctrl = 0;
817 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 818
793b883e
SH		 819 sky2_write32(sky2->hw,
820 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
821 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 822
823}
824
6b1a3aef
SH		 825/*
826 * The RX Stop command will not work for Yukon-2 if the BMU does not
827 * reach the end of packet and since we can't make sure that we have
828 * incoming data, we must reset the BMU while it is not doing a DMA
829 * transfer. Since it is possible that the RX path is still active,
830 * the RX RAM buffer will be stopped first, so any possible incoming
831 * data will not trigger a DMA. After the RAM buffer is stopped, the
832 * BMU is polled until any DMA in progress is ended and only then it
833 * will be reset.
834 */
835static void sky2_rx_stop(struct sky2_port *sky2)
836{
837 struct sky2_hw *hw = sky2->hw;
838 unsigned rxq = rxqaddr[sky2->port];
839 int i;
840
841 /* disable the RAM Buffer receive queue */
842 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
843
844 for (i = 0; i < 0xffff; i++)
845 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
846 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
847 goto stopped;
848
849 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
850 sky2->netdev->name);
851stopped:
852 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
853
854 /* reset the Rx prefetch unit */
855 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
856}
793b883e 857
d571b694 858/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 859static void sky2_rx_clean(struct sky2_port *sky2)
860{
861 unsigned i;
862
863 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 864 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 865 struct ring_info *re = sky2->rx_ring + i;
866
867 if (re->skb) {
793b883e 868 pci_unmap_single(sky2->hw->pdev,
734d1868 869 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 870 PCI_DMA_FROMDEVICE);
871 kfree_skb(re->skb);
872 re->skb = NULL;
873 }
874 }
875}
876
ef743d33
SH		 877/* Basic MII support */
878static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
879{
880 struct mii_ioctl_data *data = if_mii(ifr);
881 struct sky2_port *sky2 = netdev_priv(dev);
882 struct sky2_hw *hw = sky2->hw;
883 int err = -EOPNOTSUPP;
884
885 if (!netif_running(dev))
886 return -ENODEV; /* Phy still in reset */
887
d89e1343 888 switch (cmd) {
ef743d33
SH		 889 case SIOCGMIIPHY:
890 data->phy_id = PHY_ADDR_MARV;
891
892 /* fallthru */
893 case SIOCGMIIREG: {
894 u16 val = 0;
91c86df5 895
e07b1aa8 896 spin_lock_bh(&sky2->phy_lock);
ef743d33 897 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 898 spin_unlock_bh(&sky2->phy_lock);
91c86df5 899
ef743d33
SH		 900 data->val_out = val;
901 break;
902 }
903
904 case SIOCSMIIREG:
905 if (!capable(CAP_NET_ADMIN))
906 return -EPERM;
907
e07b1aa8 908 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 909 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
910 data->val_in);
e07b1aa8 911 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 912 break;
913 }
914 return err;
915}
916
d1f13708
SH		 917#ifdef SKY2_VLAN_TAG_USED
918static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
919{
920 struct sky2_port *sky2 = netdev_priv(dev);
921 struct sky2_hw *hw = sky2->hw;
922 u16 port = sky2->port;
d1f13708 923
302d1252 924 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 925
926 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
927 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
928 sky2->vlgrp = grp;
929
302d1252 930 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 931}
932
933static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
934{
935 struct sky2_port *sky2 = netdev_priv(dev);
936 struct sky2_hw *hw = sky2->hw;
937 u16 port = sky2->port;
d1f13708 938
302d1252 939 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 940
941 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
942 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
943 if (sky2->vlgrp)
944 sky2->vlgrp->vlan_devices[vid] = NULL;
945
302d1252 946 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 947}
948#endif
949
82788c7a
SH		 950/*
951 * It appears the hardware has a bug in the FIFO logic that
952 * cause it to hang if the FIFO gets overrun and the receive buffer
953 * is not aligned. ALso alloc_skb() won't align properly if slab
954 * debugging is enabled.
955 */
956static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
957{
958 struct sk_buff *skb;
959
960 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
961 if (likely(skb)) {
962 unsigned long p = (unsigned long) skb->data;
4a15d56f 963 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
82788c7a
SH		 964 }
965
966 return skb;
967}
968
cd28ab6a
SH		 969/*
970 * Allocate and setup receiver buffer pool.
971 * In case of 64 bit dma, there are 2X as many list elements
972 * available as ring entries
973 * and need to reserve one list element so we don't wrap around.
974 */
6b1a3aef 975static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 976{
6b1a3aef 977 struct sky2_hw *hw = sky2->hw;
6b1a3aef
SH		 978 unsigned rxq = rxqaddr[sky2->port];
979 int i;
cd28ab6a 980
6b1a3aef 981 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 982 sky2_qset(hw, rxq);
977bdf06
SH		 983
984 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
985 /* MAC Rx RAM Read is controlled by hardware */
986 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
987 }
988
6b1a3aef
SH		 989 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
990
991 rx_set_checksum(sky2);
793b883e 992 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 993 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 994
82788c7a 995 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
cd28ab6a
SH		 996 if (!re->skb)
997 goto nomem;
998
6b1a3aef 999 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 1000 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1001 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 1002 }
1003
70f1be48
SH		 1004 /* Truncate oversize frames */
1005 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
1006 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1007
6b1a3aef
SH		 1008 /* Tell chip about available buffers */
1009 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1010 return 0;
1011nomem:
1012 sky2_rx_clean(sky2);
1013 return -ENOMEM;
1014}
1015
1016/* Bring up network interface. */
1017static int sky2_up(struct net_device *dev)
1018{
1019 struct sky2_port *sky2 = netdev_priv(dev);
1020 struct sky2_hw *hw = sky2->hw;
1021 unsigned port = sky2->port;
e07b1aa8 1022 u32 ramsize, rxspace, imask;
ee7abb04 1023 int cap, err = -ENOMEM;
843a46f4 1024 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1025
ee7abb04
SH		 1026 /*
1027 * On dual port PCI-X card, there is an problem where status
1028 * can be received out of order due to split transactions
843a46f4 1029 */
ee7abb04
SH		 1030 if (otherdev && netif_running(otherdev) &&
1031 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1032 struct sky2_port *osky2 = netdev_priv(otherdev);
1033 u16 cmd;
1034
1035 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1036 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1037 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1038
1039 sky2->rx_csum = 0;
1040 osky2->rx_csum = 0;
1041 }
843a46f4 1042
cd28ab6a
SH		 1043 if (netif_msg_ifup(sky2))
1044 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1045
1046 /* must be power of 2 */
1047 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1048 TX_RING_SIZE *
1049 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1050 &sky2->tx_le_map);
1051 if (!sky2->tx_le)
1052 goto err_out;
1053
6cdbbdf3 1054 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1055 GFP_KERNEL);
1056 if (!sky2->tx_ring)
1057 goto err_out;
1058 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1059
1060 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1061 &sky2->rx_le_map);
1062 if (!sky2->rx_le)
1063 goto err_out;
1064 memset(sky2->rx_le, 0, RX_LE_BYTES);
1065
6cdbbdf3 1066 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 1067 GFP_KERNEL);
1068 if (!sky2->rx_ring)
1069 goto err_out;
1070
1071 sky2_mac_init(hw, port);
1072
1c28f6ba
SH		 1073 /* Determine available ram buffer space (in 4K blocks).
1074 * Note: not sure about the FE setting below yet
1075 */
1076 if (hw->chip_id == CHIP_ID_YUKON_FE)
1077 ramsize = 4;
1078 else
1079 ramsize = sky2_read8(hw, B2_E_0);
1080
1081 /* Give transmitter one third (rounded up) */
1082 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1083
cd28ab6a 1084 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1085 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1086
793b883e
SH		 1087 /* Make sure SyncQ is disabled */
1088 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1089 RB_RST_SET);
1090
af4ed7e6 1091 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1092
977bdf06
SH		 1093 /* Set almost empty threshold */
1094 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1095 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1096
6b1a3aef
SH		 1097 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1098 TX_RING_SIZE - 1);
cd28ab6a 1099
6b1a3aef 1100 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1101 if (err)
1102 goto err_out;
1103
cd28ab6a 1104 /* Enable interrupts from phy/mac for port */
e07b1aa8 1105 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1106 imask |= portirq_msk[port];
e07b1aa8
SH		 1107 sky2_write32(hw, B0_IMSK, imask);
1108
cd28ab6a
SH		 1109 return 0;
1110
1111err_out:
1b537565 1112 if (sky2->rx_le) {
cd28ab6a
SH		 1113 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1114 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1115 sky2->rx_le = NULL;
1116 }
1117 if (sky2->tx_le) {
cd28ab6a
SH		 1118 pci_free_consistent(hw->pdev,
1119 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1120 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1121 sky2->tx_le = NULL;
1122 }
1123 kfree(sky2->tx_ring);
1124 kfree(sky2->rx_ring);
cd28ab6a 1125
1b537565
SH		 1126 sky2->tx_ring = NULL;
1127 sky2->rx_ring = NULL;
cd28ab6a
SH		 1128 return err;
1129}
1130
793b883e
SH		 1131/* Modular subtraction in ring */
1132static inline int tx_dist(unsigned tail, unsigned head)
1133{
cb5d9547 1134 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1135}
cd28ab6a 1136
793b883e
SH		 1137/* Number of list elements available for next tx */
1138static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1139{
793b883e 1140 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1141}
1142
793b883e 1143/* Estimate of number of transmit list elements required */
28bd181a 1144static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1145{
793b883e
SH		 1146 unsigned count;
1147
1148 count = sizeof(dma_addr_t) / sizeof(u32);
1149 count += skb_shinfo(skb)->nr_frags * count;
1150
1151 if (skb_shinfo(skb)->tso_size)
1152 ++count;
1153
0e3ff6aa 1154 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1155 ++count;
1156
1157 return count;
cd28ab6a
SH		 1158}
1159
793b883e
SH		 1160/*
1161 * Put one packet in ring for transmit.
1162 * A single packet can generate multiple list elements, and
1163 * the number of ring elements will probably be less than the number
1164 * of list elements used.
f2e46561
SH		 1165 *
1166 * No BH disabling for tx_lock here (like tg3)
793b883e 1167 */
cd28ab6a
SH		 1168static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1169{
1170 struct sky2_port *sky2 = netdev_priv(dev);
1171 struct sky2_hw *hw = sky2->hw;
d1f13708 1172 struct sky2_tx_le *le = NULL;
6cdbbdf3 1173 struct tx_ring_info *re;
cd28ab6a 1174 unsigned i, len;
b19666d9 1175 int avail;
cd28ab6a
SH		 1176 dma_addr_t mapping;
1177 u32 addr64;
1178 u16 mss;
1179 u8 ctrl;
1180
302d1252
SH		 1181 /* No BH disabling for tx_lock here. We are running in BH disabled
1182 * context and TX reclaim runs via poll inside of a software
1183 * interrupt, and no related locks in IRQ processing.
1184 */
f2e46561 1185 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1186 return NETDEV_TX_LOCKED;
1187
793b883e 1188 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1189 /* There is a known but harmless race with lockless tx
1190 * and netif_stop_queue.
1191 */
1192 if (!netif_queue_stopped(dev)) {
1193 netif_stop_queue(dev);
3be92a70
SH		 1194 if (net_ratelimit())
1195 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1196 dev->name);
8c463ef7 1197 }
f2e46561 1198 spin_unlock(&sky2->tx_lock);
cd28ab6a 1199
cd28ab6a
SH		 1200 return NETDEV_TX_BUSY;
1201 }
1202
793b883e 1203 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1204 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1205 dev->name, sky2->tx_prod, skb->len);
1206
cd28ab6a
SH		 1207 len = skb_headlen(skb);
1208 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1209 addr64 = high32(mapping);
793b883e
SH		 1210
1211 re = sky2->tx_ring + sky2->tx_prod;
1212
a018e330
SH		 1213 /* Send high bits if changed or crosses boundary */
1214 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1215 le = get_tx_le(sky2);
1216 le->tx.addr = cpu_to_le32(addr64);
1217 le->ctrl = 0;
1218 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1219 sky2->tx_addr64 = high32(mapping + len);
793b883e 1220 }
cd28ab6a
SH		 1221
1222 /* Check for TCP Segmentation Offload */
1223 mss = skb_shinfo(skb)->tso_size;
793b883e 1224 if (mss != 0) {
cd28ab6a
SH		 1225 /* just drop the packet if non-linear expansion fails */
1226 if (skb_header_cloned(skb) &&
1227 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
15240072 1228 dev_kfree_skb(skb);
793b883e 1229 goto out_unlock;
cd28ab6a
SH		 1230 }
1231
1232 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1233 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1234 mss += ETH_HLEN;
793b883e 1235 }
cd28ab6a 1236
793b883e 1237 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1238 le = get_tx_le(sky2);
1239 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1240 le->tx.tso.rsvd = 0;
cd28ab6a 1241 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1242 le->ctrl = 0;
793b883e 1243 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1244 }
1245
cd28ab6a 1246 ctrl = 0;
d1f13708
SH		 1247#ifdef SKY2_VLAN_TAG_USED
1248 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1249 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1250 if (!le) {
1251 le = get_tx_le(sky2);
1252 le->tx.addr = 0;
1253 le->opcode = OP_VLAN|HW_OWNER;
1254 le->ctrl = 0;
1255 } else
1256 le->opcode |= OP_VLAN;
1257 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1258 ctrl |= INS_VLAN;
1259 }
1260#endif
1261
1262 /* Handle TCP checksum offload */
cd28ab6a 1263 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1264 u16 hdr = skb->h.raw - skb->data;
1265 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1266
1267 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1268 if (skb->nh.iph->protocol == IPPROTO_UDP)
1269 ctrl |= UDPTCP;
1270
1271 le = get_tx_le(sky2);
1272 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1273 le->tx.csum.offset = cpu_to_le16(offset);
1274 le->length = 0; /* initial checksum value */
cd28ab6a 1275 le->ctrl = 1; /* one packet */
793b883e 1276 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1277 }
1278
1279 le = get_tx_le(sky2);
1280 le->tx.addr = cpu_to_le32((u32) mapping);
1281 le->length = cpu_to_le16(len);
1282 le->ctrl = ctrl;
793b883e 1283 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1284
793b883e 1285 /* Record the transmit mapping info */
cd28ab6a 1286 re->skb = skb;
6cdbbdf3 1287 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1288
1289 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1290 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1291 struct tx_ring_info *fre;
cd28ab6a
SH		 1292
1293 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1294 frag->size, PCI_DMA_TODEVICE);
a036119f 1295 addr64 = high32(mapping);
793b883e
SH		 1296 if (addr64 != sky2->tx_addr64) {
1297 le = get_tx_le(sky2);
1298 le->tx.addr = cpu_to_le32(addr64);
1299 le->ctrl = 0;
1300 le->opcode = OP_ADDR64 | HW_OWNER;
1301 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1302 }
1303
1304 le = get_tx_le(sky2);
1305 le->tx.addr = cpu_to_le32((u32) mapping);
1306 le->length = cpu_to_le16(frag->size);
1307 le->ctrl = ctrl;
793b883e 1308 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1309
793b883e 1310 fre = sky2->tx_ring
cb5d9547 1311 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
6cdbbdf3 1312 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1313 }
6cdbbdf3 1314
793b883e 1315 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1316 le->ctrl |= EOP;
1317
b19666d9
SH		 1318 avail = tx_avail(sky2);
1319 if (mss != 0 || avail < TX_MIN_PENDING) {
1320 le->ctrl |= FRC_STAT;
1321 if (avail <= MAX_SKB_TX_LE)
1322 netif_stop_queue(dev);
1323 }
1324
290d4de5 1325 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1326
793b883e 1327out_unlock:
f2e46561 1328 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1329
1330 dev->trans_start = jiffies;
1331 return NETDEV_TX_OK;
1332}
1333
cd28ab6a 1334/*
793b883e
SH		 1335 * Free ring elements from starting at tx_cons until "done"
1336 *
1337 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1338 * buffers; these are deferred until completion.
cd28ab6a 1339 */
d11c13e7 1340static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1341{
d11c13e7 1342 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1343 struct pci_dev *pdev = sky2->hw->pdev;
1344 u16 nxt, put;
793b883e 1345 unsigned i;
cd28ab6a 1346
0e3ff6aa 1347 BUG_ON(done >= TX_RING_SIZE);
2224795d 1348
d11c13e7 1349 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1350 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1351 dev->name, done);
cd28ab6a 1352
af2a58ac
SH		 1353 for (put = sky2->tx_cons; put != done; put = nxt) {
1354 struct tx_ring_info *re = sky2->tx_ring + put;
1355 struct sk_buff *skb = re->skb;
cd28ab6a 1356
d89e1343 1357 nxt = re->idx;
af2a58ac 1358 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1359 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1360
793b883e 1361 /* Check for partial status */
af2a58ac
SH		 1362 if (tx_dist(put, done) < tx_dist(put, nxt))
1363 break;
793b883e
SH		 1364
1365 skb = re->skb;
af2a58ac 1366 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1367 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1368
1369 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1370 struct tx_ring_info *fre;
cb5d9547 1371 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
af2a58ac 1372 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
d89e1343 1373 skb_shinfo(skb)->frags[i].size,
734d1868 1374 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1375 }
1376
15240072 1377 dev_kfree_skb(skb);
793b883e 1378 }
793b883e 1379
af2a58ac 1380 sky2->tx_cons = put;
8f24664d 1381 if (tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a 1382 netif_wake_queue(dev);
cd28ab6a
SH		 1383}
1384
1385/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1386static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1387{
302d1252 1388 spin_lock_bh(&sky2->tx_lock);
d11c13e7 1389 sky2_tx_complete(sky2, sky2->tx_prod);
302d1252 1390 spin_unlock_bh(&sky2->tx_lock);
cd28ab6a
SH		 1391}
1392
1393/* Network shutdown */
1394static int sky2_down(struct net_device *dev)
1395{
1396 struct sky2_port *sky2 = netdev_priv(dev);
1397 struct sky2_hw *hw = sky2->hw;
1398 unsigned port = sky2->port;
1399 u16 ctrl;
e07b1aa8 1400 u32 imask;
cd28ab6a 1401
1b537565
SH		 1402 /* Never really got started! */
1403 if (!sky2->tx_le)
1404 return 0;
1405
cd28ab6a
SH		 1406 if (netif_msg_ifdown(sky2))
1407 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1408
018d1c66 1409 /* Stop more packets from being queued */
cd28ab6a
SH		 1410 netif_stop_queue(dev);
1411
793b883e
SH		 1412 sky2_phy_reset(hw, port);
1413
cd28ab6a
SH		 1414 /* Stop transmitter */
1415 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1416 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1417
1418 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1419 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1420
1421 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1422 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1423 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1424
1425 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1426
1427 /* Workaround shared GMAC reset */
793b883e
SH		 1428 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1429 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1430 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1431
1432 /* Disable Force Sync bit and Enable Alloc bit */
1433 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1434 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1435
1436 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1437 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1438 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1439
1440 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1441 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1442 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1443
1444 /* Reset the Tx prefetch units */
1445 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1446 PREF_UNIT_RST_SET);
1447
1448 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1449
6b1a3aef 1450 sky2_rx_stop(sky2);
cd28ab6a
SH		 1451
1452 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1453 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1454
e07b1aa8
SH		 1455 /* Disable port IRQ */
1456 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1457 imask &= ~portirq_msk[port];
e07b1aa8
SH		 1458 sky2_write32(hw, B0_IMSK, imask);
1459
d571b694 1460 /* turn off LED's */
cd28ab6a
SH		 1461 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1462
018d1c66
SH		 1463 synchronize_irq(hw->pdev->irq);
1464
cd28ab6a
SH		 1465 sky2_tx_clean(sky2);
1466 sky2_rx_clean(sky2);
1467
1468 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1469 sky2->rx_le, sky2->rx_le_map);
1470 kfree(sky2->rx_ring);
1471
1472 pci_free_consistent(hw->pdev,
1473 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1474 sky2->tx_le, sky2->tx_le_map);
1475 kfree(sky2->tx_ring);
1476
1b537565
SH		 1477 sky2->tx_le = NULL;
1478 sky2->rx_le = NULL;
1479
1480 sky2->rx_ring = NULL;
1481 sky2->tx_ring = NULL;
1482
cd28ab6a
SH		 1483 return 0;
1484}
1485
1486static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1487{
793b883e
SH		 1488 if (!hw->copper)
1489 return SPEED_1000;
1490
cd28ab6a
SH		 1491 if (hw->chip_id == CHIP_ID_YUKON_FE)
1492 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1493
1494 switch (aux & PHY_M_PS_SPEED_MSK) {
1495 case PHY_M_PS_SPEED_1000:
1496 return SPEED_1000;
1497 case PHY_M_PS_SPEED_100:
1498 return SPEED_100;
1499 default:
1500 return SPEED_10;
1501 }
1502}
1503
1504static void sky2_link_up(struct sky2_port *sky2)
1505{
1506 struct sky2_hw *hw = sky2->hw;
1507 unsigned port = sky2->port;
1508 u16 reg;
1509
1510 /* Enable Transmit FIFO Underrun */
793b883e 1511 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1512
1513 reg = gma_read16(hw, port, GM_GP_CTRL);
6f4c56b2
SH		 1514 if (sky2->autoneg == AUTONEG_DISABLE) {
1515 reg |= GM_GPCR_AU_ALL_DIS;
1516
1517 /* Is write/read necessary? Copied from sky2_mac_init */
1518 gma_write16(hw, port, GM_GP_CTRL, reg);
1519 gma_read16(hw, port, GM_GP_CTRL);
1520
1521 switch (sky2->speed) {
1522 case SPEED_1000:
1523 reg &= ~GM_GPCR_SPEED_100;
1524 reg |= GM_GPCR_SPEED_1000;
1525 break;
1526 case SPEED_100:
1527 reg &= ~GM_GPCR_SPEED_1000;
1528 reg |= GM_GPCR_SPEED_100;
1529 break;
1530 case SPEED_10:
1531 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1532 break;
1533 }
1534 } else
1535 reg &= ~GM_GPCR_AU_ALL_DIS;
1536
cd28ab6a
SH		 1537 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1538 reg |= GM_GPCR_DUP_FULL;
1539
cd28ab6a
SH		 1540 /* enable Rx/Tx */
1541 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1542 gma_write16(hw, port, GM_GP_CTRL, reg);
1543 gma_read16(hw, port, GM_GP_CTRL);
1544
1545 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1546
1547 netif_carrier_on(sky2->netdev);
1548 netif_wake_queue(sky2->netdev);
1549
1550 /* Turn on link LED */
793b883e 1551 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1552 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1553
ed6d32c7 1554 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1555 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1556 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1557
1558 switch(sky2->speed) {
1559 case SPEED_10:
1560 led |= PHY_M_LEDC_INIT_CTRL(7);
1561 break;
1562
1563 case SPEED_100:
1564 led |= PHY_M_LEDC_STA1_CTRL(7);
1565 break;
1566
1567 case SPEED_1000:
1568 led |= PHY_M_LEDC_STA0_CTRL(7);
1569 break;
1570 }
793b883e
SH		 1571
1572 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1573 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1574 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1575 }
1576
cd28ab6a
SH		 1577 if (netif_msg_link(sky2))
1578 printk(KERN_INFO PFX
d571b694 1579 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1580 sky2->netdev->name, sky2->speed,
1581 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1582 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1583 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1584}
1585
1586static void sky2_link_down(struct sky2_port *sky2)
1587{
1588 struct sky2_hw *hw = sky2->hw;
1589 unsigned port = sky2->port;
1590 u16 reg;
1591
1592 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1593
1594 reg = gma_read16(hw, port, GM_GP_CTRL);
1595 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1596 gma_write16(hw, port, GM_GP_CTRL, reg);
1597 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1598
1599 if (sky2->rx_pause && !sky2->tx_pause) {
1600 /* restore Asymmetric Pause bit */
1601 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1602 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1603 | PHY_M_AN_ASP);
cd28ab6a
SH		 1604 }
1605
cd28ab6a
SH		 1606 netif_carrier_off(sky2->netdev);
1607 netif_stop_queue(sky2->netdev);
1608
1609 /* Turn on link LED */
1610 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1611
1612 if (netif_msg_link(sky2))
1613 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1614 sky2_phy_init(hw, port);
1615}
1616
793b883e
SH		 1617static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1618{
1619 struct sky2_hw *hw = sky2->hw;
1620 unsigned port = sky2->port;
1621 u16 lpa;
1622
1623 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1624
1625 if (lpa & PHY_M_AN_RF) {
1626 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1627 return -1;
1628 }
1629
1630 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1631 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1632 printk(KERN_ERR PFX "%s: master/slave fault",
1633 sky2->netdev->name);
1634 return -1;
1635 }
1636
1637 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1638 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1639 sky2->netdev->name);
1640 return -1;
1641 }
1642
1643 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1644
1645 sky2->speed = sky2_phy_speed(hw, aux);
1646
1647 /* Pause bits are offset (9..8) */
ed6d32c7 1648 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1649 aux >>= 6;
1650
1651 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1652 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1653
1654 if ((sky2->tx_pause || sky2->rx_pause)
1655 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1656 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1657 else
1658 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1659
1660 return 0;
1661}
cd28ab6a 1662
e07b1aa8
SH		 1663/* Interrupt from PHY */
1664static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1665{
e07b1aa8
SH		 1666 struct net_device *dev = hw->dev[port];
1667 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1668 u16 istatus, phystat;
1669
e07b1aa8
SH		 1670 spin_lock(&sky2->phy_lock);
1671 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1672 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1673
1674 if (!netif_running(dev))
1675 goto out;
cd28ab6a
SH		 1676
1677 if (netif_msg_intr(sky2))
1678 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1679 sky2->netdev->name, istatus, phystat);
1680
1681 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1682 if (sky2_autoneg_done(sky2, phystat) == 0)
1683 sky2_link_up(sky2);
1684 goto out;
1685 }
cd28ab6a 1686
793b883e
SH		 1687 if (istatus & PHY_M_IS_LSP_CHANGE)
1688 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1689
793b883e
SH		 1690 if (istatus & PHY_M_IS_DUP_CHANGE)
1691 sky2->duplex =
1692 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1693
793b883e
SH		 1694 if (istatus & PHY_M_IS_LST_CHANGE) {
1695 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1696 sky2_link_up(sky2);
793b883e
SH		 1697 else
1698 sky2_link_down(sky2);
cd28ab6a 1699 }
793b883e 1700out:
e07b1aa8 1701 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1702}
1703
302d1252
SH		 1704
1705/* Transmit timeout is only called if we are running, carries is up
1706 * and tx queue is full (stopped).
1707 */
cd28ab6a
SH		 1708static void sky2_tx_timeout(struct net_device *dev)
1709{
1710 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1711 struct sky2_hw *hw = sky2->hw;
1712 unsigned txq = txqaddr[sky2->port];
8f24664d 1713 u16 report, done;
cd28ab6a
SH		 1714
1715 if (netif_msg_timer(sky2))
1716 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1717
8f24664d
SH		 1718 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1719 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1720
8f24664d
SH		 1721 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1722 dev->name,
1723 sky2->tx_cons, sky2->tx_prod, report, done);
1724
1725 if (report != done) {
1726 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1727
1728 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1729 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1730 } else if (report != sky2->tx_cons) {
1731 printk(KERN_INFO PFX "status report lost?\n");
1732
1733 spin_lock_bh(&sky2->tx_lock);
1734 sky2_tx_complete(sky2, report);
1735 spin_unlock_bh(&sky2->tx_lock);
1736 } else {
1737 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1738
8f24664d
SH		 1739 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1740 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1741
1742 sky2_tx_clean(sky2);
1743
1744 sky2_qset(hw, txq);
1745 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1746 }
cd28ab6a
SH		 1747}
1748
734d1868 1749
70f1be48
SH		 1750/* Want receive buffer size to be multiple of 64 bits
1751 * and incl room for vlan and truncation
1752 */
734d1868
SH		 1753static inline unsigned sky2_buf_size(int mtu)
1754{
4a15d56f 1755 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
734d1868
SH		 1756}
1757
cd28ab6a
SH		 1758static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1759{
6b1a3aef
SH		 1760 struct sky2_port *sky2 = netdev_priv(dev);
1761 struct sky2_hw *hw = sky2->hw;
1762 int err;
1763 u16 ctl, mode;
e07b1aa8 1764 u32 imask;
cd28ab6a
SH		 1765
1766 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1767 return -EINVAL;
1768
5a5b1ea0
SH		 1769 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1770 return -EINVAL;
1771
6b1a3aef
SH		 1772 if (!netif_running(dev)) {
1773 dev->mtu = new_mtu;
1774 return 0;
1775 }
1776
e07b1aa8 1777 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1778 sky2_write32(hw, B0_IMSK, 0);
1779
018d1c66
SH		 1780 dev->trans_start = jiffies; /* prevent tx timeout */
1781 netif_stop_queue(dev);
1782 netif_poll_disable(hw->dev[0]);
1783
e07b1aa8
SH		 1784 synchronize_irq(hw->pdev->irq);
1785
6b1a3aef
SH		 1786 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1787 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1788 sky2_rx_stop(sky2);
1789 sky2_rx_clean(sky2);
cd28ab6a
SH		 1790
1791 dev->mtu = new_mtu;
734d1868 1792 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef
SH		 1793 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1794 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1795
1796 if (dev->mtu > ETH_DATA_LEN)
1797 mode |= GM_SMOD_JUMBO_ENA;
1798
1799 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1800
6b1a3aef 1801 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1802
6b1a3aef 1803 err = sky2_rx_start(sky2);
e07b1aa8 1804 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1805
1b537565
SH		 1806 if (err)
1807 dev_close(dev);
1808 else {
1809 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1810
1811 netif_poll_enable(hw->dev[0]);
1812 netif_wake_queue(dev);
1813 }
1814
cd28ab6a
SH		 1815 return err;
1816}
1817
1818/*
1819 * Receive one packet.
1820 * For small packets or errors, just reuse existing skb.
d571b694 1821 * For larger packets, get new buffer.
cd28ab6a 1822 */
d11c13e7 1823static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1824 u16 length, u32 status)
1825{
cd28ab6a 1826 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1827 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1828
1829 if (unlikely(netif_msg_rx_status(sky2)))
1830 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1831 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1832
793b883e 1833 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1834 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1835
42eeea01 1836 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1837 goto error;
1838
42eeea01
SH		 1839 if (!(status & GMR_FS_RX_OK))
1840 goto resubmit;
1841
70f1be48 1842 if (length > sky2->netdev->mtu + ETH_HLEN)
6e15b712
SH		 1843 goto oversize;
1844
bdb5c58e 1845 if (length < copybreak) {
79e57d32
SH		 1846 skb = alloc_skb(length + 2, GFP_ATOMIC);
1847 if (!skb)
793b883e
SH		 1848 goto resubmit;
1849
79e57d32 1850 skb_reserve(skb, 2);
793b883e
SH		 1851 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1852 length, PCI_DMA_FROMDEVICE);
79e57d32 1853 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1854 skb->ip_summed = re->skb->ip_summed;
1855 skb->csum = re->skb->csum;
793b883e
SH		 1856 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1857 length, PCI_DMA_FROMDEVICE);
793b883e 1858 } else {
79e57d32
SH		 1859 struct sk_buff *nskb;
1860
82788c7a 1861 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1862 if (!nskb)
1863 goto resubmit;
cd28ab6a 1864
793b883e 1865 skb = re->skb;
79e57d32 1866 re->skb = nskb;
793b883e 1867 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1868 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1869 prefetch(skb->data);
cd28ab6a 1870
793b883e 1871 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1872 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1873 }
cd28ab6a 1874
79e57d32 1875 skb_put(skb, length);
793b883e 1876resubmit:
d11c13e7 1877 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1878 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1879
bea86103 1880 /* Tell receiver about new buffers. */
290d4de5 1881 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
bea86103 1882
cd28ab6a
SH		 1883 return skb;
1884
6e15b712
SH		 1885oversize:
1886 ++sky2->net_stats.rx_over_errors;
1887 goto resubmit;
1888
cd28ab6a 1889error:
6e15b712
SH		 1890 ++sky2->net_stats.rx_errors;
1891
3be92a70 1892 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a
SH		 1893 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1894 sky2->netdev->name, status, length);
793b883e
SH		 1895
1896 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1897 sky2->net_stats.rx_length_errors++;
1898 if (status & GMR_FS_FRAGMENT)
1899 sky2->net_stats.rx_frame_errors++;
1900 if (status & GMR_FS_CRC_ERR)
1901 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1902 if (status & GMR_FS_RX_FF_OV)
1903 sky2->net_stats.rx_fifo_errors++;
79e57d32 1904
793b883e 1905 goto resubmit;
cd28ab6a
SH		 1906}
1907
e07b1aa8
SH		 1908/* Transmit complete */
1909static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 1910{
e07b1aa8 1911 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 1912
e07b1aa8
SH		 1913 if (netif_running(dev)) {
1914 spin_lock(&sky2->tx_lock);
1915 sky2_tx_complete(sky2, last);
1916 spin_unlock(&sky2->tx_lock);
2224795d 1917 }
cd28ab6a
SH		 1918}
1919
e07b1aa8
SH		 1920/* Process status response ring */
1921static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 1922{
e07b1aa8 1923 int work_done = 0;
e71ebd73 1924 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 1925
af2a58ac 1926 rmb();
bea86103 1927
e71ebd73 1928 while (hw->st_idx != hwidx) {
13210ce5
SH		 1929 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1930 struct net_device *dev;
d11c13e7 1931 struct sky2_port *sky2;
cd28ab6a 1932 struct sk_buff *skb;
cd28ab6a
SH		 1933 u32 status;
1934 u16 length;
1935
cb5d9547 1936 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 1937
e71ebd73
SH		 1938 BUG_ON(le->link >= 2);
1939 dev = hw->dev[le->link];
13210ce5
SH		 1940
1941 sky2 = netdev_priv(dev);
e07b1aa8
SH		 1942 length = le->length;
1943 status = le->status;
cd28ab6a 1944
e71ebd73 1945 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1946 case OP_RXSTAT:
d11c13e7 1947 skb = sky2_receive(sky2, length, status);
d1f13708
SH		 1948 if (!skb)
1949 break;
13210ce5
SH		 1950
1951 skb->dev = dev;
1952 skb->protocol = eth_type_trans(skb, dev);
1953 dev->last_rx = jiffies;
1954
d1f13708
SH		 1955#ifdef SKY2_VLAN_TAG_USED
1956 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1957 vlan_hwaccel_receive_skb(skb,
1958 sky2->vlgrp,
1959 be16_to_cpu(sky2->rx_tag));
1960 } else
1961#endif
cd28ab6a 1962 netif_receive_skb(skb);
13210ce5
SH		 1963
1964 if (++work_done >= to_do)
1965 goto exit_loop;
cd28ab6a
SH		 1966 break;
1967
d1f13708
SH		 1968#ifdef SKY2_VLAN_TAG_USED
1969 case OP_RXVLAN:
1970 sky2->rx_tag = length;
1971 break;
1972
1973 case OP_RXCHKSVLAN:
1974 sky2->rx_tag = length;
1975 /* fall through */
1976#endif
cd28ab6a 1977 case OP_RXCHKS:
d11c13e7
SH		 1978 skb = sky2->rx_ring[sky2->rx_next].skb;
1979 skb->ip_summed = CHECKSUM_HW;
1980 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1981 break;
1982
1983 case OP_TXINDEXLE:
13b97b74 1984 /* TX index reports status for both ports */
f55925d7
SH		 1985 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
1986 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 1987 if (hw->dev[1])
1988 sky2_tx_done(hw->dev[1],
1989 ((status >> 24) & 0xff)
1990 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 1991 break;
1992
cd28ab6a
SH		 1993 default:
1994 if (net_ratelimit())
793b883e 1995 printk(KERN_WARNING PFX
e71ebd73
SH		 1996 "unknown status opcode 0x%x\n", le->opcode);
1997 goto exit_loop;
cd28ab6a 1998 }
13210ce5 1999 }
cd28ab6a 2000
13210ce5 2001exit_loop:
e07b1aa8 2002 return work_done;
cd28ab6a
SH		 2003}
2004
2005static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2006{
2007 struct net_device *dev = hw->dev[port];
2008
3be92a70
SH		 2009 if (net_ratelimit())
2010 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2011 dev->name, status);
cd28ab6a
SH		 2012
2013 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2014 if (net_ratelimit())
2015 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2016 dev->name);
cd28ab6a
SH		 2017 /* Clear IRQ */
2018 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2019 }
2020
2021 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2022 if (net_ratelimit())
2023 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2024 dev->name);
cd28ab6a
SH		 2025
2026 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2027 }
2028
2029 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2030 if (net_ratelimit())
2031 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2032 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2033 }
2034
2035 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2036 if (net_ratelimit())
2037 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2038 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2039 }
2040
2041 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2042 if (net_ratelimit())
2043 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2044 dev->name);
cd28ab6a
SH		 2045 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2046 }
2047}
2048
2049static void sky2_hw_intr(struct sky2_hw *hw)
2050{
2051 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2052
793b883e 2053 if (status & Y2_IS_TIST_OV)
cd28ab6a 2054 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2055
2056 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2057 u16 pci_err;
2058
56a645cc 2059 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2060 if (net_ratelimit())
2061 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2062 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2063
2064 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2065 sky2_pci_write16(hw, PCI_STATUS,
793b883e 2066 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2067 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2068 }
2069
2070 if (status & Y2_IS_PCI_EXP) {
d571b694 2071 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2072 u32 pex_err;
2073
56a645cc 2074 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2075
3be92a70
SH		 2076 if (net_ratelimit())
2077 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2078 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2079
2080 /* clear the interrupt */
2081 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2082 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
793b883e 2083 0xffffffffUL);
cd28ab6a
SH		 2084 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2085
2086 if (pex_err & PEX_FATAL_ERRORS) {
2087 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2088 hwmsk &= ~Y2_IS_PCI_EXP;
2089 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2090 }
2091 }
2092
2093 if (status & Y2_HWE_L1_MASK)
2094 sky2_hw_error(hw, 0, status);
2095 status >>= 8;
2096 if (status & Y2_HWE_L1_MASK)
2097 sky2_hw_error(hw, 1, status);
2098}
2099
2100static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2101{
2102 struct net_device *dev = hw->dev[port];
2103 struct sky2_port *sky2 = netdev_priv(dev);
2104 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2105
2106 if (netif_msg_intr(sky2))
2107 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2108 dev->name, status);
2109
2110 if (status & GM_IS_RX_FF_OR) {
2111 ++sky2->net_stats.rx_fifo_errors;
2112 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2113 }
2114
2115 if (status & GM_IS_TX_FF_UR) {
2116 ++sky2->net_stats.tx_fifo_errors;
2117 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2118 }
cd28ab6a
SH		 2119}
2120
d257924e
SH		 2121/* This should never happen it is a fatal situation */
2122static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2123 const char *rxtx, u32 mask)
2124{
2125 struct net_device *dev = hw->dev[port];
2126 struct sky2_port *sky2 = netdev_priv(dev);
2127 u32 imask;
2128
2129 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2130 dev ? dev->name : "<not registered>", rxtx);
2131
2132 imask = sky2_read32(hw, B0_IMSK);
2133 imask &= ~mask;
2134 sky2_write32(hw, B0_IMSK, imask);
2135
2136 if (dev) {
2137 spin_lock(&sky2->phy_lock);
2138 sky2_link_down(sky2);
2139 spin_unlock(&sky2->phy_lock);
2140 }
2141}
cd28ab6a 2142
d27ed387
SH		 2143/* If idle then force a fake soft NAPI poll once a second
2144 * to work around cases where sharing an edge triggered interrupt.
2145 */
2146static void sky2_idle(unsigned long arg)
2147{
01bd7564
SH		 2148 struct sky2_hw *hw = (struct sky2_hw *) arg;
2149 struct net_device *dev = hw->dev[0];
d27ed387 2150
d27ed387
SH		 2151 if (__netif_rx_schedule_prep(dev))
2152 __netif_rx_schedule(dev);
01bd7564
SH		 2153
2154 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2155}
2156
2157
e07b1aa8 2158static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2159{
e07b1aa8
SH		 2160 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2161 int work_limit = min(dev0->quota, *budget);
2162 int work_done = 0;
fb2690a9 2163 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2164
1e5f1283
SH		 2165 if (status & Y2_IS_HW_ERR)
2166 sky2_hw_intr(hw);
d257924e 2167
1e5f1283
SH		 2168 if (status & Y2_IS_IRQ_PHY1)
2169 sky2_phy_intr(hw, 0);
cd28ab6a 2170
1e5f1283
SH		 2171 if (status & Y2_IS_IRQ_PHY2)
2172 sky2_phy_intr(hw, 1);
cd28ab6a 2173
1e5f1283
SH		 2174 if (status & Y2_IS_IRQ_MAC1)
2175 sky2_mac_intr(hw, 0);
cd28ab6a 2176
1e5f1283
SH		 2177 if (status & Y2_IS_IRQ_MAC2)
2178 sky2_mac_intr(hw, 1);
cd28ab6a 2179
1e5f1283
SH		 2180 if (status & Y2_IS_CHK_RX1)
2181 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2182
1e5f1283
SH		 2183 if (status & Y2_IS_CHK_RX2)
2184 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2185
1e5f1283
SH		 2186 if (status & Y2_IS_CHK_TXA1)
2187 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2188
1e5f1283
SH		 2189 if (status & Y2_IS_CHK_TXA2)
2190 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2191
1e5f1283
SH		 2192 if (status & Y2_IS_STAT_BMU)
2193 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
e07b1aa8 2194
1e5f1283
SH		 2195 work_done = sky2_status_intr(hw, work_limit);
2196 *budget -= work_done;
2197 dev0->quota -= work_done;
e07b1aa8 2198
1e5f1283
SH		 2199 if (work_done >= work_limit)
2200 return 1;
e07b1aa8 2201
d3240312 2202 netif_rx_complete(dev0);
e07b1aa8 2203
fb2690a9 2204 status = sky2_read32(hw, B0_Y2_SP_LISR);
e07b1aa8
SH		 2205 return 0;
2206}
2207
2208static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2209{
2210 struct sky2_hw *hw = dev_id;
2211 struct net_device *dev0 = hw->dev[0];
2212 u32 status;
2213
2214 /* Reading this mask interrupts as side effect */
2215 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2216 if (status == 0 || status == ~0)
2217 return IRQ_NONE;
793b883e 2218
e07b1aa8
SH		 2219 prefetch(&hw->st_le[hw->st_idx]);
2220 if (likely(__netif_rx_schedule_prep(dev0)))
2221 __netif_rx_schedule(dev0);
793b883e 2222
cd28ab6a
SH		 2223 return IRQ_HANDLED;
2224}
2225
2226#ifdef CONFIG_NET_POLL_CONTROLLER
2227static void sky2_netpoll(struct net_device *dev)
2228{
2229 struct sky2_port *sky2 = netdev_priv(dev);
2230
793b883e 2231 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 2232}
2233#endif
2234
2235/* Chip internal frequency for clock calculations */
fb17358f 2236static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2237{
793b883e 2238 switch (hw->chip_id) {
cd28ab6a 2239 case CHIP_ID_YUKON_EC:
5a5b1ea0 2240 case CHIP_ID_YUKON_EC_U:
fb17358f 2241 return 125; /* 125 Mhz */
cd28ab6a 2242 case CHIP_ID_YUKON_FE:
fb17358f 2243 return 100; /* 100 Mhz */
793b883e 2244 default: /* YUKON_XL */
fb17358f 2245 return 156; /* 156 Mhz */
cd28ab6a
SH		 2246 }
2247}
2248
fb17358f 2249static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2250{
fb17358f 2251 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2252}
2253
fb17358f 2254static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2255{
fb17358f 2256 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2257}
2258
fb17358f 2259
98712e5e 2260static int __devinit sky2_reset(struct sky2_hw *hw)
cd28ab6a 2261{
cd28ab6a
SH		 2262 u16 status;
2263 u8 t8, pmd_type;
56a645cc 2264 int i;
cd28ab6a 2265
cd28ab6a 2266 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2267
cd28ab6a
SH		 2268 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2269 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2270 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2271 pci_name(hw->pdev), hw->chip_id);
2272 return -EOPNOTSUPP;
2273 }
2274
290d4de5
SH		 2275 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2276
2277 /* This rev is really old, and requires untested workarounds */
2278 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2279 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2280 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2281 hw->chip_id, hw->chip_rev);
2282 return -EOPNOTSUPP;
2283 }
2284
cd28ab6a
SH		 2285 /* disable ASF */
2286 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2287 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2288 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2289 }
2290
2291 /* do a SW reset */
2292 sky2_write8(hw, B0_CTST, CS_RST_SET);
2293 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2294
2295 /* clear PCI errors, if any */
56a645cc 2296 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2297
cd28ab6a 2298 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2299 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2300
cd28ab6a
SH		 2301
2302 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2303
2304 /* clear any PEX errors */
d89e1343 2305 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
56a645cc
SH		 2306 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2307
cd28ab6a
SH		 2308
2309 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2310 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2311
2312 hw->ports = 1;
2313 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2314 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2315 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2316 ++hw->ports;
2317 }
cd28ab6a 2318
5afa0a9c 2319 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2320
2321 for (i = 0; i < hw->ports; i++) {
2322 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2323 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2324 }
2325
2326 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2327
793b883e
SH		 2328 /* Clear I2C IRQ noise */
2329 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2330
2331 /* turn off hardware timer (unused) */
2332 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2333 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2334
cd28ab6a
SH		 2335 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2336
69634ee7
SH		 2337 /* Turn off descriptor polling */
2338 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2339
2340 /* Turn off receive timestamp */
2341 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2342 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2343
2344 /* enable the Tx Arbiters */
2345 for (i = 0; i < hw->ports; i++)
2346 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2347
2348 /* Initialize ram interface */
2349 for (i = 0; i < hw->ports; i++) {
793b883e 2350 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2351
2352 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2353 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2354 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2355 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2356 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2357 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2358 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2359 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2360 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2361 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2362 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2363 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2364 }
2365
cd28ab6a
SH		 2366 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2367
cd28ab6a
SH		 2368 for (i = 0; i < hw->ports; i++)
2369 sky2_phy_reset(hw, i);
cd28ab6a 2370
cd28ab6a
SH		 2371 memset(hw->st_le, 0, STATUS_LE_BYTES);
2372 hw->st_idx = 0;
2373
2374 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2375 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2376
2377 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2378 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2379
2380 /* Set the list last index */
793b883e 2381 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2382
290d4de5
SH		 2383 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2384 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2385
290d4de5
SH		 2386 /* set Status-FIFO ISR watermark */
2387 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2388 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2389 else
2390 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2391
290d4de5 2392 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2393 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2394 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2395
793b883e 2396 /* enable status unit */
cd28ab6a
SH		 2397 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2398
2399 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2400 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2401 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2402
2403 return 0;
2404}
2405
28bd181a 2406static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a
SH		 2407{
2408 u32 modes;
2409 if (hw->copper) {
793b883e
SH		 2410 modes = SUPPORTED_10baseT_Half
2411 | SUPPORTED_10baseT_Full
2412 | SUPPORTED_100baseT_Half
2413 | SUPPORTED_100baseT_Full
2414 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2415
2416 if (hw->chip_id != CHIP_ID_YUKON_FE)
2417 modes |= SUPPORTED_1000baseT_Half
793b883e 2418 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2419 } else
2420 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2421 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2422 return modes;
2423}
2424
793b883e 2425static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2426{
2427 struct sky2_port *sky2 = netdev_priv(dev);
2428 struct sky2_hw *hw = sky2->hw;
2429
2430 ecmd->transceiver = XCVR_INTERNAL;
2431 ecmd->supported = sky2_supported_modes(hw);
2432 ecmd->phy_address = PHY_ADDR_MARV;
2433 if (hw->copper) {
2434 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2435 | SUPPORTED_10baseT_Full
2436 | SUPPORTED_100baseT_Half
2437 | SUPPORTED_100baseT_Full
2438 | SUPPORTED_1000baseT_Half
2439 | SUPPORTED_1000baseT_Full
2440 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2441 ecmd->port = PORT_TP;
2442 } else
2443 ecmd->port = PORT_FIBRE;
2444
2445 ecmd->advertising = sky2->advertising;
2446 ecmd->autoneg = sky2->autoneg;
2447 ecmd->speed = sky2->speed;
2448 ecmd->duplex = sky2->duplex;
2449 return 0;
2450}
2451
2452static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2453{
2454 struct sky2_port *sky2 = netdev_priv(dev);
2455 const struct sky2_hw *hw = sky2->hw;
2456 u32 supported = sky2_supported_modes(hw);
2457
2458 if (ecmd->autoneg == AUTONEG_ENABLE) {
2459 ecmd->advertising = supported;
2460 sky2->duplex = -1;
2461 sky2->speed = -1;
2462 } else {
2463 u32 setting;
2464
793b883e 2465 switch (ecmd->speed) {
cd28ab6a
SH		 2466 case SPEED_1000:
2467 if (ecmd->duplex == DUPLEX_FULL)
2468 setting = SUPPORTED_1000baseT_Full;
2469 else if (ecmd->duplex == DUPLEX_HALF)
2470 setting = SUPPORTED_1000baseT_Half;
2471 else
2472 return -EINVAL;
2473 break;
2474 case SPEED_100:
2475 if (ecmd->duplex == DUPLEX_FULL)
2476 setting = SUPPORTED_100baseT_Full;
2477 else if (ecmd->duplex == DUPLEX_HALF)
2478 setting = SUPPORTED_100baseT_Half;
2479 else
2480 return -EINVAL;
2481 break;
2482
2483 case SPEED_10:
2484 if (ecmd->duplex == DUPLEX_FULL)
2485 setting = SUPPORTED_10baseT_Full;
2486 else if (ecmd->duplex == DUPLEX_HALF)
2487 setting = SUPPORTED_10baseT_Half;
2488 else
2489 return -EINVAL;
2490 break;
2491 default:
2492 return -EINVAL;
2493 }
2494
2495 if ((setting & supported) == 0)
2496 return -EINVAL;
2497
2498 sky2->speed = ecmd->speed;
2499 sky2->duplex = ecmd->duplex;
2500 }
2501
2502 sky2->autoneg = ecmd->autoneg;
2503 sky2->advertising = ecmd->advertising;
2504
1b537565
SH		 2505 if (netif_running(dev))
2506 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2507
2508 return 0;
2509}
2510
2511static void sky2_get_drvinfo(struct net_device *dev,
2512 struct ethtool_drvinfo *info)
2513{
2514 struct sky2_port *sky2 = netdev_priv(dev);
2515
2516 strcpy(info->driver, DRV_NAME);
2517 strcpy(info->version, DRV_VERSION);
2518 strcpy(info->fw_version, "N/A");
2519 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2520}
2521
2522static const struct sky2_stat {
793b883e
SH		 2523 char name[ETH_GSTRING_LEN];
2524 u16 offset;
cd28ab6a
SH		 2525} sky2_stats[] = {
2526 { "tx_bytes", GM_TXO_OK_HI },
2527 { "rx_bytes", GM_RXO_OK_HI },
2528 { "tx_broadcast", GM_TXF_BC_OK },
2529 { "rx_broadcast", GM_RXF_BC_OK },
2530 { "tx_multicast", GM_TXF_MC_OK },
2531 { "rx_multicast", GM_RXF_MC_OK },
2532 { "tx_unicast", GM_TXF_UC_OK },
2533 { "rx_unicast", GM_RXF_UC_OK },
2534 { "tx_mac_pause", GM_TXF_MPAUSE },
2535 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2536 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2537 { "late_collision",GM_TXF_LAT_COL },
2538 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2539 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2540 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2541
d2604540 2542 { "rx_short", GM_RXF_SHT },
cd28ab6a 2543 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2544 { "rx_64_byte_packets", GM_RXF_64B },
2545 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2546 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2547 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2548 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2549 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2550 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2551 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2552 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2553 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2554 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2555
2556 { "tx_64_byte_packets", GM_TXF_64B },
2557 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2558 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2559 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2560 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2561 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2562 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2563 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2564};
2565
cd28ab6a
SH		 2566static u32 sky2_get_rx_csum(struct net_device *dev)
2567{
2568 struct sky2_port *sky2 = netdev_priv(dev);
2569
2570 return sky2->rx_csum;
2571}
2572
2573static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2574{
2575 struct sky2_port *sky2 = netdev_priv(dev);
2576
2577 sky2->rx_csum = data;
793b883e 2578
cd28ab6a
SH		 2579 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2580 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2581
2582 return 0;
2583}
2584
2585static u32 sky2_get_msglevel(struct net_device *netdev)
2586{
2587 struct sky2_port *sky2 = netdev_priv(netdev);
2588 return sky2->msg_enable;
2589}
2590
9a7ae0a9
SH		 2591static int sky2_nway_reset(struct net_device *dev)
2592{
2593 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2594
2595 if (sky2->autoneg != AUTONEG_ENABLE)
2596 return -EINVAL;
2597
1b537565 2598 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2599
2600 return 0;
2601}
2602
793b883e 2603static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2604{
2605 struct sky2_hw *hw = sky2->hw;
2606 unsigned port = sky2->port;
2607 int i;
2608
2609 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2610 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2611 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2612 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2613
793b883e 2614 for (i = 2; i < count; i++)
cd28ab6a
SH		 2615 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2616}
2617
cd28ab6a
SH		 2618static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2619{
2620 struct sky2_port *sky2 = netdev_priv(netdev);
2621 sky2->msg_enable = value;
2622}
2623
2624static int sky2_get_stats_count(struct net_device *dev)
2625{
2626 return ARRAY_SIZE(sky2_stats);
2627}
2628
2629static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2630 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2631{
2632 struct sky2_port *sky2 = netdev_priv(dev);
2633
793b883e 2634 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2635}
2636
793b883e 2637static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2638{
2639 int i;
2640
2641 switch (stringset) {
2642 case ETH_SS_STATS:
2643 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2644 memcpy(data + i * ETH_GSTRING_LEN,
2645 sky2_stats[i].name, ETH_GSTRING_LEN);
2646 break;
2647 }
2648}
2649
2650/* Use hardware MIB variables for critical path statistics and
2651 * transmit feedback not reported at interrupt.
2652 * Other errors are accounted for in interrupt handler.
2653 */
2654static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2655{
2656 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2657 u64 data[13];
cd28ab6a 2658
793b883e 2659 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2660
2661 sky2->net_stats.tx_bytes = data[0];
2662 sky2->net_stats.rx_bytes = data[1];
2663 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2664 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2665 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2666 sky2->net_stats.collisions = data[10];
2667 sky2->net_stats.tx_aborted_errors = data[12];
2668
2669 return &sky2->net_stats;
2670}
2671
2672static int sky2_set_mac_address(struct net_device *dev, void *p)
2673{
2674 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2675 struct sky2_hw *hw = sky2->hw;
2676 unsigned port = sky2->port;
2677 const struct sockaddr *addr = p;
cd28ab6a
SH		 2678
2679 if (!is_valid_ether_addr(addr->sa_data))
2680 return -EADDRNOTAVAIL;
2681
cd28ab6a 2682 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2683 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2684 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2685 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2686 dev->dev_addr, ETH_ALEN);
1b537565 2687
a8ab1ec0
SH		 2688 /* virtual address for data */
2689 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2690
2691 /* physical address: used for pause frames */
2692 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2693
2694 return 0;
cd28ab6a
SH		 2695}
2696
2697static void sky2_set_multicast(struct net_device *dev)
2698{
2699 struct sky2_port *sky2 = netdev_priv(dev);
2700 struct sky2_hw *hw = sky2->hw;
2701 unsigned port = sky2->port;
2702 struct dev_mc_list *list = dev->mc_list;
2703 u16 reg;
2704 u8 filter[8];
2705
2706 memset(filter, 0, sizeof(filter));
2707
2708 reg = gma_read16(hw, port, GM_RX_CTRL);
2709 reg |= GM_RXCR_UCF_ENA;
2710
d571b694 2711 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2712 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2713 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2714 memset(filter, 0xff, sizeof(filter));
793b883e 2715 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2716 reg &= ~GM_RXCR_MCF_ENA;
2717 else {
2718 int i;
2719 reg |= GM_RXCR_MCF_ENA;
2720
2721 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2722 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2723 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2724 }
2725 }
2726
cd28ab6a 2727 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2728 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2729 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2730 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2731 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2732 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2733 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2734 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2735
2736 gma_write16(hw, port, GM_RX_CTRL, reg);
2737}
2738
2739/* Can have one global because blinking is controlled by
2740 * ethtool and that is always under RTNL mutex
2741 */
91c86df5 2742static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2743{
793b883e
SH		 2744 u16 pg;
2745
793b883e
SH		 2746 switch (hw->chip_id) {
2747 case CHIP_ID_YUKON_XL:
2748 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2749 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2750 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2751 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2752 PHY_M_LEDC_INIT_CTRL(7) |
2753 PHY_M_LEDC_STA1_CTRL(7) |
2754 PHY_M_LEDC_STA0_CTRL(7))
2755 : 0);
2756
2757 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2758 break;
2759
2760 default:
2761 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2762 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2763 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2764 PHY_M_LED_MO_10(MO_LED_ON) |
2765 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2766 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2767 PHY_M_LED_MO_RX(MO_LED_ON)
2768 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2769 PHY_M_LED_MO_10(MO_LED_OFF) |
2770 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2771 PHY_M_LED_MO_1000(MO_LED_OFF) |
2772 PHY_M_LED_MO_RX(MO_LED_OFF));
2773
793b883e 2774 }
cd28ab6a
SH		 2775}
2776
2777/* blink LED's for finding board */
2778static int sky2_phys_id(struct net_device *dev, u32 data)
2779{
2780 struct sky2_port *sky2 = netdev_priv(dev);
2781 struct sky2_hw *hw = sky2->hw;
2782 unsigned port = sky2->port;
793b883e 2783 u16 ledctrl, ledover = 0;
cd28ab6a 2784 long ms;
91c86df5 2785 int interrupted;
cd28ab6a
SH		 2786 int onoff = 1;
2787
793b883e 2788 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2789 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2790 else
2791 ms = data * 1000;
2792
2793 /* save initial values */
e07b1aa8 2794 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2795 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2796 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2797 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2798 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2799 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2800 } else {
2801 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2802 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2803 }
cd28ab6a 2804
91c86df5
SH		 2805 interrupted = 0;
2806 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2807 sky2_led(hw, port, onoff);
2808 onoff = !onoff;
2809
e07b1aa8 2810 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2811 interrupted = msleep_interruptible(250);
e07b1aa8 2812 spin_lock_bh(&sky2->phy_lock);
91c86df5 2813
cd28ab6a
SH		 2814 ms -= 250;
2815 }
2816
2817 /* resume regularly scheduled programming */
793b883e
SH		 2818 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2819 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2820 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2821 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2822 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2823 } else {
2824 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2825 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2826 }
e07b1aa8 2827 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2828
2829 return 0;
2830}
2831
2832static void sky2_get_pauseparam(struct net_device *dev,
2833 struct ethtool_pauseparam *ecmd)
2834{
2835 struct sky2_port *sky2 = netdev_priv(dev);
2836
2837 ecmd->tx_pause = sky2->tx_pause;
2838 ecmd->rx_pause = sky2->rx_pause;
2839 ecmd->autoneg = sky2->autoneg;
2840}
2841
2842static int sky2_set_pauseparam(struct net_device *dev,
2843 struct ethtool_pauseparam *ecmd)
2844{
2845 struct sky2_port *sky2 = netdev_priv(dev);
2846 int err = 0;
2847
2848 sky2->autoneg = ecmd->autoneg;
2849 sky2->tx_pause = ecmd->tx_pause != 0;
2850 sky2->rx_pause = ecmd->rx_pause != 0;
2851
1b537565 2852 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2853
2854 return err;
2855}
2856
fb17358f
SH		 2857static int sky2_get_coalesce(struct net_device *dev,
2858 struct ethtool_coalesce *ecmd)
2859{
2860 struct sky2_port *sky2 = netdev_priv(dev);
2861 struct sky2_hw *hw = sky2->hw;
2862
2863 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2864 ecmd->tx_coalesce_usecs = 0;
2865 else {
2866 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2867 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2868 }
2869 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2870
2871 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2872 ecmd->rx_coalesce_usecs = 0;
2873 else {
2874 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2875 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2876 }
2877 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2878
2879 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2880 ecmd->rx_coalesce_usecs_irq = 0;
2881 else {
2882 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2883 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2884 }
2885
2886 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2887
2888 return 0;
2889}
2890
2891/* Note: this affect both ports */
2892static int sky2_set_coalesce(struct net_device *dev,
2893 struct ethtool_coalesce *ecmd)
2894{
2895 struct sky2_port *sky2 = netdev_priv(dev);
2896 struct sky2_hw *hw = sky2->hw;
77b3d6a2 2897 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 2898
77b3d6a2
SH		 2899 if (ecmd->tx_coalesce_usecs > tmax ||
2900 ecmd->rx_coalesce_usecs > tmax ||
2901 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 2902 return -EINVAL;
2903
ff81fbbe 2904 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 2905 return -EINVAL;
ff81fbbe 2906 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 2907 return -EINVAL;
ff81fbbe 2908 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 2909 return -EINVAL;
2910
2911 if (ecmd->tx_coalesce_usecs == 0)
2912 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2913 else {
2914 sky2_write32(hw, STAT_TX_TIMER_INI,
2915 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2916 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2917 }
2918 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2919
2920 if (ecmd->rx_coalesce_usecs == 0)
2921 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2922 else {
2923 sky2_write32(hw, STAT_LEV_TIMER_INI,
2924 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2925 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2926 }
2927 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2928
2929 if (ecmd->rx_coalesce_usecs_irq == 0)
2930 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2931 else {
d28d4870 2932 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 2933 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2934 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2935 }
2936 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2937 return 0;
2938}
2939
793b883e
SH		 2940static void sky2_get_ringparam(struct net_device *dev,
2941 struct ethtool_ringparam *ering)
2942{
2943 struct sky2_port *sky2 = netdev_priv(dev);
2944
2945 ering->rx_max_pending = RX_MAX_PENDING;
2946 ering->rx_mini_max_pending = 0;
2947 ering->rx_jumbo_max_pending = 0;
2948 ering->tx_max_pending = TX_RING_SIZE - 1;
2949
2950 ering->rx_pending = sky2->rx_pending;
2951 ering->rx_mini_pending = 0;
2952 ering->rx_jumbo_pending = 0;
2953 ering->tx_pending = sky2->tx_pending;
2954}
2955
2956static int sky2_set_ringparam(struct net_device *dev,
2957 struct ethtool_ringparam *ering)
2958{
2959 struct sky2_port *sky2 = netdev_priv(dev);
2960 int err = 0;
2961
2962 if (ering->rx_pending > RX_MAX_PENDING ||
2963 ering->rx_pending < 8 ||
2964 ering->tx_pending < MAX_SKB_TX_LE ||
2965 ering->tx_pending > TX_RING_SIZE - 1)
2966 return -EINVAL;
2967
2968 if (netif_running(dev))
2969 sky2_down(dev);
2970
2971 sky2->rx_pending = ering->rx_pending;
2972 sky2->tx_pending = ering->tx_pending;
2973
1b537565 2974 if (netif_running(dev)) {
793b883e 2975 err = sky2_up(dev);
1b537565
SH		 2976 if (err)
2977 dev_close(dev);
6ed995bb
SH		 2978 else
2979 sky2_set_multicast(dev);
1b537565 2980 }
793b883e
SH		 2981
2982 return err;
2983}
2984
793b883e
SH		 2985static int sky2_get_regs_len(struct net_device *dev)
2986{
6e4cbb34 2987 return 0x4000;
793b883e
SH		 2988}
2989
2990/*
2991 * Returns copy of control register region
6e4cbb34 2992 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2993 */
2994static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2995 void *p)
2996{
2997 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2998 const void __iomem *io = sky2->hw->regs;
793b883e 2999
6e4cbb34 3000 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3001 regs->version = 1;
6e4cbb34 3002 memset(p, 0, regs->len);
793b883e 3003
6e4cbb34
SH		 3004 memcpy_fromio(p, io, B3_RAM_ADDR);
3005
3006 memcpy_fromio(p + B3_RI_WTO_R1,
3007 io + B3_RI_WTO_R1,
3008 regs->len - B3_RI_WTO_R1);
793b883e 3009}
cd28ab6a
SH		 3010
3011static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3012 .get_settings = sky2_get_settings,
3013 .set_settings = sky2_set_settings,
3014 .get_drvinfo = sky2_get_drvinfo,
3015 .get_msglevel = sky2_get_msglevel,
3016 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3017 .nway_reset = sky2_nway_reset,
793b883e
SH		 3018 .get_regs_len = sky2_get_regs_len,
3019 .get_regs = sky2_get_regs,
3020 .get_link = ethtool_op_get_link,
3021 .get_sg = ethtool_op_get_sg,
3022 .set_sg = ethtool_op_set_sg,
3023 .get_tx_csum = ethtool_op_get_tx_csum,
3024 .set_tx_csum = ethtool_op_set_tx_csum,
3025 .get_tso = ethtool_op_get_tso,
3026 .set_tso = ethtool_op_set_tso,
3027 .get_rx_csum = sky2_get_rx_csum,
3028 .set_rx_csum = sky2_set_rx_csum,
3029 .get_strings = sky2_get_strings,
fb17358f
SH		 3030 .get_coalesce = sky2_get_coalesce,
3031 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3032 .get_ringparam = sky2_get_ringparam,
3033 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3034 .get_pauseparam = sky2_get_pauseparam,
3035 .set_pauseparam = sky2_set_pauseparam,
793b883e 3036 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3037 .get_stats_count = sky2_get_stats_count,
3038 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3039 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3040};
3041
3042/* Initialize network device */
3043static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3044 unsigned port, int highmem)
3045{
3046 struct sky2_port *sky2;
3047 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3048
3049 if (!dev) {
3050 printk(KERN_ERR "sky2 etherdev alloc failed");
3051 return NULL;
3052 }
3053
3054 SET_MODULE_OWNER(dev);
3055 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3056 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3057 dev->open = sky2_up;
3058 dev->stop = sky2_down;
ef743d33 3059 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3060 dev->hard_start_xmit = sky2_xmit_frame;
3061 dev->get_stats = sky2_get_stats;
3062 dev->set_multicast_list = sky2_set_multicast;
3063 dev->set_mac_address = sky2_set_mac_address;
3064 dev->change_mtu = sky2_change_mtu;
3065 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3066 dev->tx_timeout = sky2_tx_timeout;
3067 dev->watchdog_timeo = TX_WATCHDOG;
3068 if (port == 0)
3069 dev->poll = sky2_poll;
3070 dev->weight = NAPI_WEIGHT;
3071#ifdef CONFIG_NET_POLL_CONTROLLER
3072 dev->poll_controller = sky2_netpoll;
3073#endif
cd28ab6a
SH		 3074
3075 sky2 = netdev_priv(dev);
3076 sky2->netdev = dev;
3077 sky2->hw = hw;
3078 sky2->msg_enable = netif_msg_init(debug, default_msg);
3079
3080 spin_lock_init(&sky2->tx_lock);
3081 /* Auto speed and flow control */
3082 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3083 sky2->tx_pause = 1;
cd28ab6a
SH		 3084 sky2->rx_pause = 1;
3085 sky2->duplex = -1;
3086 sky2->speed = -1;
3087 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3088 sky2->rx_csum = 1;
75d070c5 3089
e07b1aa8 3090 spin_lock_init(&sky2->phy_lock);
793b883e 3091 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3092 sky2->rx_pending = RX_DEF_PENDING;
734d1868 3093 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 3094
3095 hw->dev[port] = dev;
3096
3097 sky2->port = port;
3098
5a5b1ea0
SH		 3099 dev->features |= NETIF_F_LLTX;
3100 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3101 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3102 if (highmem)
3103 dev->features |= NETIF_F_HIGHDMA;
793b883e 3104 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3105
d1f13708
SH		 3106#ifdef SKY2_VLAN_TAG_USED
3107 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3108 dev->vlan_rx_register = sky2_vlan_rx_register;
3109 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3110#endif
3111
cd28ab6a 3112 /* read the mac address */
793b883e 3113 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3114 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3115
3116 /* device is off until link detection */
3117 netif_carrier_off(dev);
3118 netif_stop_queue(dev);
3119
3120 return dev;
3121}
3122
28bd181a 3123static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3124{
3125 const struct sky2_port *sky2 = netdev_priv(dev);
3126
3127 if (netif_msg_probe(sky2))
3128 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3129 dev->name,
3130 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3131 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3132}
3133
fb2690a9
SH		 3134/* Handle software interrupt used during MSI test */
3135static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3136 struct pt_regs *regs)
3137{
3138 struct sky2_hw *hw = dev_id;
3139 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3140
3141 if (status == 0)
3142 return IRQ_NONE;
3143
3144 if (status & Y2_IS_IRQ_SW) {
3145 hw->msi_detected = 1;
3146 wake_up(&hw->msi_wait);
3147 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3148 }
3149 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3150
3151 return IRQ_HANDLED;
3152}
3153
3154/* Test interrupt path by forcing a a software IRQ */
3155static int __devinit sky2_test_msi(struct sky2_hw *hw)
3156{
3157 struct pci_dev *pdev = hw->pdev;
3158 int err;
3159
3160 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3161
3162 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3163 if (err) {
3164 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3165 pci_name(pdev), pdev->irq);
3166 return err;
3167 }
3168
3169 init_waitqueue_head (&hw->msi_wait);
3170
3171 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3172 wmb();
3173
3174 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3175
3176 if (!hw->msi_detected) {
3177 /* MSI test failed, go back to INTx mode */
3178 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3179 "switching to INTx mode. Please report this failure to "
3180 "the PCI maintainer and include system chipset information.\n",
3181 pci_name(pdev));
3182
3183 err = -EOPNOTSUPP;
3184 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3185 }
3186
3187 sky2_write32(hw, B0_IMSK, 0);
3188
3189 free_irq(pdev->irq, hw);
3190
3191 return err;
3192}
3193
cd28ab6a
SH		 3194static int __devinit sky2_probe(struct pci_dev *pdev,
3195 const struct pci_device_id *ent)
3196{
793b883e 3197 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3198 struct sky2_hw *hw;
5afa0a9c 3199 int err, pm_cap, using_dac = 0;
cd28ab6a 3200
793b883e
SH		 3201 err = pci_enable_device(pdev);
3202 if (err) {
cd28ab6a
SH		 3203 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3204 pci_name(pdev));
3205 goto err_out;
3206 }
3207
793b883e
SH		 3208 err = pci_request_regions(pdev, DRV_NAME);
3209 if (err) {
cd28ab6a
SH		 3210 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3211 pci_name(pdev));
793b883e 3212 goto err_out;
cd28ab6a
SH		 3213 }
3214
3215 pci_set_master(pdev);
3216
5afa0a9c
SH		 3217 /* Find power-management capability. */
3218 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3219 if (pm_cap == 0) {
3220 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3221 "aborting.\n");
3222 err = -EIO;
3223 goto err_out_free_regions;
3224 }
3225
d1f3d4dd
SH		 3226 if (sizeof(dma_addr_t) > sizeof(u32) &&
3227 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3228 using_dac = 1;
3229 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3230 if (err < 0) {
3231 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3232 "for consistent allocations\n", pci_name(pdev));
3233 goto err_out_free_regions;
3234 }
cd28ab6a 3235
d1f3d4dd 3236 } else {
cd28ab6a
SH		 3237 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3238 if (err) {
3239 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3240 pci_name(pdev));
3241 goto err_out_free_regions;
3242 }
3243 }
d1f3d4dd 3244
cd28ab6a 3245 err = -ENOMEM;
6aad85d6 3246 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3247 if (!hw) {
3248 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3249 pci_name(pdev));
3250 goto err_out_free_regions;
3251 }
3252
cd28ab6a 3253 hw->pdev = pdev;
cd28ab6a
SH		 3254
3255 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3256 if (!hw->regs) {
3257 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3258 pci_name(pdev));
3259 goto err_out_free_hw;
3260 }
5afa0a9c 3261 hw->pm_cap = pm_cap;
cd28ab6a 3262
56a645cc
SH		 3263#ifdef __BIG_ENDIAN
3264 /* byte swap descriptors in hardware */
3265 {
3266 u32 reg;
3267
3268 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3269 reg |= PCI_REV_DESC;
3270 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3271 }
3272#endif
3273
08c06d8a
SH		 3274 /* ring for status responses */
3275 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3276 &hw->st_dma);
3277 if (!hw->st_le)
3278 goto err_out_iounmap;
3279
cd28ab6a
SH		 3280 err = sky2_reset(hw);
3281 if (err)
793b883e 3282 goto err_out_iounmap;
cd28ab6a 3283
5f4f9dc1
SH		 3284 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3285 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
92f965e8 3286 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3287 hw->chip_id, hw->chip_rev);
cd28ab6a 3288
793b883e
SH		 3289 dev = sky2_init_netdev(hw, 0, using_dac);
3290 if (!dev)
cd28ab6a
SH		 3291 goto err_out_free_pci;
3292
793b883e
SH		 3293 err = register_netdev(dev);
3294 if (err) {
cd28ab6a
SH		 3295 printk(KERN_ERR PFX "%s: cannot register net device\n",
3296 pci_name(pdev));
3297 goto err_out_free_netdev;
3298 }
3299
3300 sky2_show_addr(dev);
3301
3302 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3303 if (register_netdev(dev1) == 0)
3304 sky2_show_addr(dev1);
3305 else {
3306 /* Failure to register second port need not be fatal */
793b883e
SH		 3307 printk(KERN_WARNING PFX
3308 "register of second port failed\n");
cd28ab6a
SH		 3309 hw->dev[1] = NULL;
3310 free_netdev(dev1);
3311 }
3312 }
3313
fb2690a9
SH		 3314 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3315 err = sky2_test_msi(hw);
3316 if (err == -EOPNOTSUPP)
3317 pci_disable_msi(pdev);
3318 else if (err)
3319 goto err_out_unregister;
3320 }
3321
3322 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
793b883e
SH		 3323 if (err) {
3324 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3325 pci_name(pdev), pdev->irq);
3326 goto err_out_unregister;
3327 }
3328
e07b1aa8 3329 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
793b883e 3330
01bd7564
SH		 3331 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3332 if (idle_timeout > 0)
3333 mod_timer(&hw->idle_timer,
3334 jiffies + msecs_to_jiffies(idle_timeout));
d27ed387 3335
793b883e
SH		 3336 pci_set_drvdata(pdev, hw);
3337
cd28ab6a
SH		 3338 return 0;
3339
793b883e 3340err_out_unregister:
fb2690a9 3341 pci_disable_msi(pdev);
793b883e
SH		 3342 if (dev1) {
3343 unregister_netdev(dev1);
3344 free_netdev(dev1);
3345 }
3346 unregister_netdev(dev);
cd28ab6a
SH		 3347err_out_free_netdev:
3348 free_netdev(dev);
cd28ab6a 3349err_out_free_pci:
793b883e 3350 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3351 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3352err_out_iounmap:
3353 iounmap(hw->regs);
3354err_out_free_hw:
3355 kfree(hw);
3356err_out_free_regions:
3357 pci_release_regions(pdev);
cd28ab6a 3358 pci_disable_device(pdev);
cd28ab6a
SH		 3359err_out:
3360 return err;
3361}
3362
3363static void __devexit sky2_remove(struct pci_dev *pdev)
3364{
793b883e 3365 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3366 struct net_device *dev0, *dev1;
3367
793b883e 3368 if (!hw)
cd28ab6a
SH		 3369 return;
3370
d27ed387
SH		 3371 del_timer_sync(&hw->idle_timer);
3372
3373 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3374 synchronize_irq(hw->pdev->irq);
3375
cd28ab6a 3376 dev0 = hw->dev[0];
793b883e
SH		 3377 dev1 = hw->dev[1];
3378 if (dev1)
3379 unregister_netdev(dev1);
cd28ab6a
SH		 3380 unregister_netdev(dev0);
3381
5afa0a9c 3382 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3383 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3384 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3385 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3386
3387 free_irq(pdev->irq, hw);
fb2690a9 3388 pci_disable_msi(pdev);
793b883e 3389 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3390 pci_release_regions(pdev);
3391 pci_disable_device(pdev);
793b883e 3392
cd28ab6a
SH		 3393 if (dev1)
3394 free_netdev(dev1);
3395 free_netdev(dev0);
3396 iounmap(hw->regs);
3397 kfree(hw);
5afa0a9c 3398
cd28ab6a
SH		 3399 pci_set_drvdata(pdev, NULL);
3400}
3401
3402#ifdef CONFIG_PM
3403static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3404{
793b883e 3405 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3406 int i;
cd28ab6a
SH		 3407
3408 for (i = 0; i < 2; i++) {
3409 struct net_device *dev = hw->dev[i];
3410
3411 if (dev) {
5afa0a9c
SH		 3412 if (!netif_running(dev))
3413 continue;
3414
3415 sky2_down(dev);
cd28ab6a 3416 netif_device_detach(dev);
cd28ab6a
SH		 3417 }
3418 }
3419
5afa0a9c 3420 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 3421}
3422
3423static int sky2_resume(struct pci_dev *pdev)
3424{
793b883e 3425 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3426 int i, err;
cd28ab6a 3427
cd28ab6a
SH		 3428 pci_restore_state(pdev);
3429 pci_enable_wake(pdev, PCI_D0, 0);
08c06d8a
SH		 3430 err = sky2_set_power_state(hw, PCI_D0);
3431 if (err)
3432 goto out;
cd28ab6a 3433
08c06d8a
SH		 3434 err = sky2_reset(hw);
3435 if (err)
3436 goto out;
cd28ab6a
SH		 3437
3438 for (i = 0; i < 2; i++) {
3439 struct net_device *dev = hw->dev[i];
08c06d8a
SH		 3440 if (dev && netif_running(dev)) {
3441 netif_device_attach(dev);
3442 err = sky2_up(dev);
3443 if (err) {
3444 printk(KERN_ERR PFX "%s: could not up: %d\n",
3445 dev->name, err);
3446 dev_close(dev);
3447 break;
5afa0a9c 3448 }
cd28ab6a
SH		 3449 }
3450 }
08c06d8a
SH		 3451out:
3452 return err;
cd28ab6a
SH		 3453}
3454#endif
3455
3456static struct pci_driver sky2_driver = {
793b883e
SH		 3457 .name = DRV_NAME,
3458 .id_table = sky2_id_table,
3459 .probe = sky2_probe,
3460 .remove = __devexit_p(sky2_remove),
cd28ab6a 3461#ifdef CONFIG_PM
793b883e
SH		 3462 .suspend = sky2_suspend,
3463 .resume = sky2_resume,
cd28ab6a
SH		 3464#endif
3465};
3466
3467static int __init sky2_init_module(void)
3468{
50241c4c 3469 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3470}
3471
3472static void __exit sky2_cleanup_module(void)
3473{
3474 pci_unregister_driver(&sky2_driver);
3475}
3476
3477module_init(sky2_init_module);
3478module_exit(sky2_cleanup_module);
3479
3480MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3481MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3482MODULE_LICENSE("GPL");
5f4f9dc1 3483MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree