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sky2: Refactor sky2_up into two functions
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
ac958154 53#define DRV_VERSION "1.26"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 66
ee5f68fe 67/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
ee5f68fe
SH		 71#define TX_MAX_PENDING 4096
72#define TX_DEF_PENDING 127
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
e6cac9ba 102static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 144 { 0 }
145};
793b883e 146
cd28ab6a
SH		 147MODULE_DEVICE_TABLE(pci, sky2_id_table);
148
149/* Avoid conditionals by using array */
150static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 152static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 153
d1b139c0
SH		 154static void sky2_set_multicast(struct net_device *dev);
155
af043aa5 156/* Access to PHY via serial interconnect */
ef743d33 157static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 158{
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 166 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
167 if (ctrl == 0xffff)
168 goto io_error;
169
170 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 171 return 0;
af043aa5
SH		 172
173 udelay(10);
cd28ab6a 174 }
ef743d33 175
af043aa5 176 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 177 return -ETIMEDOUT;
af043aa5
SH		 178
179io_error:
180 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
181 return -EIO;
cd28ab6a
SH		 182}
183
ef743d33 184static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 185{
186 int i;
187
793b883e 188 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 189 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
190
191 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 192 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
193 if (ctrl == 0xffff)
194 goto io_error;
195
196 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 197 *val = gma_read16(hw, port, GM_SMI_DATA);
198 return 0;
199 }
200
af043aa5 201 udelay(10);
cd28ab6a
SH		 202 }
203
af043aa5 204 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 205 return -ETIMEDOUT;
af043aa5
SH		 206io_error:
207 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
208 return -EIO;
ef743d33
SH		 209}
210
af043aa5 211static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 212{
213 u16 v;
af043aa5 214 __gm_phy_read(hw, port, reg, &v);
ef743d33 215 return v;
cd28ab6a
SH		 216}
217
5afa0a9c 218
ae306cca
SH		 219static void sky2_power_on(struct sky2_hw *hw)
220{
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw, B0_POWER_CTRL,
223 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 224
ae306cca
SH		 225 /* disable Core Clock Division, */
226 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 227
ae306cca
SH		 228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 /* enable bits are inverted */
230 sky2_write8(hw, B2_Y2_CLK_GATE,
231 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
232 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
233 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
234 else
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 236
ea76e635 237 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 238 u32 reg;
5afa0a9c 239
b32f40c4 240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 241
b32f40c4 242 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 245 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 246
b32f40c4 247 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 248 /* set all bits to 0 except bits 28 & 27 */
249 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 250 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 251
b32f40c4 252 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 253
5f8ae5c5 254 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
255
8f70920f
SH		 256 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
257 reg = sky2_read32(hw, B2_GP_IO);
258 reg |= GLB_GPIO_STAT_RACE_DIS;
259 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 260
261 sky2_read32(hw, B2_GP_IO);
5afa0a9c 262 }
10547ae2
SH		 263
264 /* Turn on "driver loaded" LED */
265 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 266}
5afa0a9c 267
ae306cca
SH		 268static void sky2_power_aux(struct sky2_hw *hw)
269{
270 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
271 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
272 else
273 /* enable bits are inverted */
274 sky2_write8(hw, B2_Y2_CLK_GATE,
275 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
276 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
277 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
278
c23ddf8f
SH		 279 /* switch power to VAUX if supported and PME from D3cold */
280 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
281 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 282 sky2_write8(hw, B0_POWER_CTRL,
283 (PC_VAUX_ENA | PC_VCC_ENA |
284 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 285
286 /* turn off "driver loaded LED" */
287 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c
SH		 288}
289
d3bcfbeb 290static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 291{
292 u16 reg;
293
294 /* disable all GMAC IRQ's */
295 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 296
cd28ab6a
SH		 297 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
298 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
299 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
300 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
301
302 reg = gma_read16(hw, port, GM_RX_CTRL);
303 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
304 gma_write16(hw, port, GM_RX_CTRL, reg);
305}
306
16ad91e1
SH		 307/* flow control to advertise bits */
308static const u16 copper_fc_adv[] = {
309 [FC_NONE] = 0,
310 [FC_TX] = PHY_M_AN_ASP,
311 [FC_RX] = PHY_M_AN_PC,
312 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
313};
314
315/* flow control to advertise bits when using 1000BaseX */
316static const u16 fiber_fc_adv[] = {
df3fe1f3 317 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 318 [FC_TX] = PHY_M_P_ASYM_MD_X,
319 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 320 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 321};
322
323/* flow control to GMA disable bits */
324static const u16 gm_fc_disable[] = {
325 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
326 [FC_TX] = GM_GPCR_FC_RX_DIS,
327 [FC_RX] = GM_GPCR_FC_TX_DIS,
328 [FC_BOTH] = 0,
329};
330
331
cd28ab6a
SH		 332static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
333{
334 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 335 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 336
0ea065e5 337 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 338 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 339 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
340
341 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 342 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 343 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
344
53419c68 345 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 346 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 347 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 348 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
349 else
53419c68
SH		 350 /* set master & slave downshift counter to 1x */
351 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 352
353 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
354 }
355
356 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 357 if (sky2_is_copper(hw)) {
05745c4a 358 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 359 /* enable automatic crossover */
360 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 361
362 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
363 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
364 u16 spec;
365
366 /* Enable Class A driver for FE+ A0 */
367 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
368 spec |= PHY_M_FESC_SEL_CL_A;
369 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
370 }
cd28ab6a
SH		 371 } else {
372 /* disable energy detect */
373 ctrl &= ~PHY_M_PC_EN_DET_MSK;
374
375 /* enable automatic crossover */
376 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
377
53419c68 378 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 379 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
380 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 381 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 382 ctrl &= ~PHY_M_PC_DSC_MSK;
383 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
384 }
385 }
cd28ab6a
SH		 386 } else {
387 /* workaround for deviation #4.88 (CRC errors) */
388 /* disable Automatic Crossover */
389
390 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 391 }
cd28ab6a 392
b89165f2
SH		 393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
394
395 /* special setup for PHY 88E1112 Fiber */
ea76e635 396 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 397 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 398
b89165f2
SH		 399 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
400 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
401 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
402 ctrl &= ~PHY_M_MAC_MD_MSK;
403 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
404 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
405
406 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 407 /* select page 1 to access Fiber registers */
408 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 409
410 /* for SFP-module set SIGDET polarity to low */
411 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
412 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 413 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 414 }
b89165f2
SH		 415
416 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 417 }
418
7800fddc 419 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 420 ct1000 = 0;
421 adv = PHY_AN_CSMA;
2eaba1a2 422 reg = 0;
cd28ab6a 423
0ea065e5 424 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 425 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 426 if (sky2->advertising & ADVERTISED_1000baseT_Full)
427 ct1000 |= PHY_M_1000C_AFD;
428 if (sky2->advertising & ADVERTISED_1000baseT_Half)
429 ct1000 |= PHY_M_1000C_AHD;
430 if (sky2->advertising & ADVERTISED_100baseT_Full)
431 adv |= PHY_M_AN_100_FD;
432 if (sky2->advertising & ADVERTISED_100baseT_Half)
433 adv |= PHY_M_AN_100_HD;
434 if (sky2->advertising & ADVERTISED_10baseT_Full)
435 adv |= PHY_M_AN_10_FD;
436 if (sky2->advertising & ADVERTISED_10baseT_Half)
437 adv |= PHY_M_AN_10_HD;
709c6e7b 438
b89165f2
SH		 439 } else { /* special defines for FIBER (88E1040S only) */
440 if (sky2->advertising & ADVERTISED_1000baseT_Full)
441 adv |= PHY_M_AN_1000X_AFD;
442 if (sky2->advertising & ADVERTISED_1000baseT_Half)
443 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 444 }
cd28ab6a
SH		 445
446 /* Restart Auto-negotiation */
447 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
448 } else {
449 /* forced speed/duplex settings */
450 ct1000 = PHY_M_1000C_MSE;
451
0ea065e5
SH		 452 /* Disable auto update for duplex flow control and duplex */
453 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 454
455 switch (sky2->speed) {
456 case SPEED_1000:
457 ctrl |= PHY_CT_SP1000;
2eaba1a2 458 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 459 break;
460 case SPEED_100:
461 ctrl |= PHY_CT_SP100;
2eaba1a2 462 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 463 break;
464 }
465
2eaba1a2
SH		 466 if (sky2->duplex == DUPLEX_FULL) {
467 reg |= GM_GPCR_DUP_FULL;
468 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 469 } else if (sky2->speed < SPEED_1000)
470 sky2->flow_mode = FC_NONE;
0ea065e5 471 }
2eaba1a2 472
0ea065e5
SH		 473 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
474 if (sky2_is_copper(hw))
475 adv |= copper_fc_adv[sky2->flow_mode];
476 else
477 adv |= fiber_fc_adv[sky2->flow_mode];
478 } else {
479 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 480 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 481
482 /* Forward pause packets to GMAC? */
16ad91e1 483 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 484 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
485 else
486 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 487 }
488
2eaba1a2
SH		 489 gma_write16(hw, port, GM_GP_CTRL, reg);
490
05745c4a 491 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 492 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
493
494 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
495 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
496
497 /* Setup Phy LED's */
498 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
499 ledover = 0;
500
501 switch (hw->chip_id) {
502 case CHIP_ID_YUKON_FE:
503 /* on 88E3082 these bits are at 11..9 (shifted left) */
504 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
505
506 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
507
508 /* delete ACT LED control bits */
509 ctrl &= ~PHY_M_FELP_LED1_MSK;
510 /* change ACT LED control to blink mode */
511 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
05745c4a
SH		 515 case CHIP_ID_YUKON_FE_P:
516 /* Enable Link Partner Next Page */
517 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
518 ctrl |= PHY_M_PC_ENA_LIP_NP;
519
520 /* disable Energy Detect and enable scrambler */
521 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
523
524 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
525 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
526 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
527 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
528
529 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
530 break;
531
cd28ab6a 532 case CHIP_ID_YUKON_XL:
793b883e 533 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 534
535 /* select page 3 to access LED control register */
536 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
537
538 /* set LED Function Control register */
ed6d32c7
SH		 539 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
540 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
541 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
542 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
543 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 544
545 /* set Polarity Control register */
546 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 547 (PHY_M_POLC_LS1_P_MIX(4) |
548 PHY_M_POLC_IS0_P_MIX(4) |
549 PHY_M_POLC_LOS_CTRL(2) |
550 PHY_M_POLC_INIT_CTRL(2) |
551 PHY_M_POLC_STA1_CTRL(2) |
552 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 553
554 /* restore page register */
793b883e 555 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 556 break;
93745494 557
ed6d32c7 558 case CHIP_ID_YUKON_EC_U:
93745494 559 case CHIP_ID_YUKON_EX:
ed4d4161 560 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 561 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
562
563 /* select page 3 to access LED control register */
564 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
565
566 /* set LED Function Control register */
567 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
568 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
569 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
570 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
571 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
572
573 /* set Blink Rate in LED Timer Control Register */
574 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
575 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
576 /* restore page register */
577 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
578 break;
cd28ab6a
SH		 579
580 default:
581 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
582 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 583
cd28ab6a 584 /* turn off the Rx LED (LED_RX) */
a84d0a3d 585 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 586 }
587
0ce8b98d 588 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 589 /* apply fixes in PHY AFE */
ed6d32c7
SH		 590 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
591
977bdf06 592 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 593 gm_phy_write(hw, port, 0x18, 0xaa99);
594 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 595
0ce8b98d
SH		 596 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
597 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
598 gm_phy_write(hw, port, 0x18, 0xa204);
599 gm_phy_write(hw, port, 0x17, 0x2002);
600 }
977bdf06
SH		 601
602 /* set page register to 0 */
9467a8fc 603 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 604 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
605 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
606 /* apply workaround for integrated resistors calibration */
607 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
608 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 609 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
610 /* apply fixes in PHY AFE */
611 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
612
613 /* apply RDAC termination workaround */
614 gm_phy_write(hw, port, 24, 0x2800);
615 gm_phy_write(hw, port, 23, 0x2001);
616
617 /* set page register back to 0 */
618 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 619 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
620 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 621 /* no effect on Yukon-XL */
977bdf06 622 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 623
8e95a202
JP		 624 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
625 sky2->speed == SPEED_100) {
977bdf06 626 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 627 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 628 }
cd28ab6a 629
977bdf06
SH		 630 if (ledover)
631 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
632
633 }
2eaba1a2 634
d571b694 635 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 636 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 637 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
638 else
639 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
640}
641
b96936da
SH		 642static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
643static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
644
645static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 646{
647 u32 reg1;
d3bcfbeb 648
a40ccc68 649 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 650 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 651 reg1 &= ~phy_power[port];
d3bcfbeb 652
b96936da 653 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 654 reg1 |= coma_mode[port];
655
b32f40c4 656 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 657 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 658 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 659
660 if (hw->chip_id == CHIP_ID_YUKON_FE)
661 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
662 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
663 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 664}
167f53d0 665
b96936da
SH		 666static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
667{
668 u32 reg1;
db99b988
SH		 669 u16 ctrl;
670
671 /* release GPHY Control reset */
672 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
673
674 /* release GMAC reset */
675 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
676
677 if (hw->flags & SKY2_HW_NEWER_PHY) {
678 /* select page 2 to access MAC control register */
679 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
680
681 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
682 /* allow GMII Power Down */
683 ctrl &= ~PHY_M_MAC_GMIF_PUP;
684 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
685
686 /* set page register back to 0 */
687 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
688 }
689
690 /* setup General Purpose Control Register */
691 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 692 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
693 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
694 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 695
696 if (hw->chip_id != CHIP_ID_YUKON_EC) {
697 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 698 /* select page 2 to access MAC control register */
699 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 700
e484d5f5 701 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 702 /* enable Power Down */
703 ctrl |= PHY_M_PC_POW_D_ENA;
704 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 705
706 /* set page register back to 0 */
707 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 708 }
709
710 /* set IEEE compatible Power Down Mode (dev. #4.99) */
711 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
712 }
b96936da 713
a40ccc68 714 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 715 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 716 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 717 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 718 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 719}
720
1b537565
SH		 721/* Force a renegotiation */
722static void sky2_phy_reinit(struct sky2_port *sky2)
723{
e07b1aa8 724 spin_lock_bh(&sky2->phy_lock);
1b537565 725 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 726 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 727}
728
e3173832
SH		 729/* Put device in state to listen for Wake On Lan */
730static void sky2_wol_init(struct sky2_port *sky2)
731{
732 struct sky2_hw *hw = sky2->hw;
733 unsigned port = sky2->port;
734 enum flow_control save_mode;
735 u16 ctrl;
e3173832
SH		 736
737 /* Bring hardware out of reset */
738 sky2_write16(hw, B0_CTST, CS_RST_CLR);
739 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
740
741 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
742 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
743
744 /* Force to 10/100
745 * sky2_reset will re-enable on resume
746 */
747 save_mode = sky2->flow_mode;
748 ctrl = sky2->advertising;
749
750 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
751 sky2->flow_mode = FC_NONE;
b96936da
SH		 752
753 spin_lock_bh(&sky2->phy_lock);
754 sky2_phy_power_up(hw, port);
755 sky2_phy_init(hw, port);
756 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 757
758 sky2->flow_mode = save_mode;
759 sky2->advertising = ctrl;
760
761 /* Set GMAC to no flow control and auto update for speed/duplex */
762 gma_write16(hw, port, GM_GP_CTRL,
763 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
764 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
765
766 /* Set WOL address */
767 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
768 sky2->netdev->dev_addr, ETH_ALEN);
769
770 /* Turn on appropriate WOL control bits */
771 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
772 ctrl = 0;
773 if (sky2->wol & WAKE_PHY)
774 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
775 else
776 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
777
778 if (sky2->wol & WAKE_MAGIC)
779 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
780 else
a419aef8 781 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 782
783 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
784 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
785
5f8ae5c5 786 /* Disable PiG firmware */
787 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
788
e3173832
SH		 789 /* block receiver */
790 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
e3173832
SH		 791}
792
69161611
SH		 793static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
794{
05745c4a
SH		 795 struct net_device *dev = hw->dev[port];
796
ed4d4161
SH		 797 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
798 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 799 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161 800 /* Yukon-Extreme B0 and further Extreme devices */
44dde56d 801 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
802 } else if (dev->mtu > ETH_DATA_LEN) {
803 /* set Tx GMAC FIFO Almost Empty Threshold */
804 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
805 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
05745c4a 806
44dde56d 807 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
808 } else
809 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
69161611
SH		 810}
811
cd28ab6a
SH		 812static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
813{
814 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
815 u16 reg;
25cccecc 816 u32 rx_reg;
cd28ab6a
SH		 817 int i;
818 const u8 *addr = hw->dev[port]->dev_addr;
819
f350339c
SH		 820 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
821 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 822
823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
824
793b883e 825 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 826 /* WA DEV_472 -- looks like crossed wires on port 2 */
827 /* clear GMAC 1 Control reset */
828 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
829 do {
830 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
831 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
832 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
833 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
834 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
835 }
836
793b883e 837 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 838
2eaba1a2
SH		 839 /* Enable Transmit FIFO Underrun */
840 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
841
e07b1aa8 842 spin_lock_bh(&sky2->phy_lock);
b96936da 843 sky2_phy_power_up(hw, port);
cd28ab6a 844 sky2_phy_init(hw, port);
e07b1aa8 845 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 846
847 /* MIB clear */
848 reg = gma_read16(hw, port, GM_PHY_ADDR);
849 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
850
43f2f104
SH		 851 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
852 gma_read16(hw, port, i);
cd28ab6a
SH		 853 gma_write16(hw, port, GM_PHY_ADDR, reg);
854
855 /* transmit control */
856 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
857
858 /* receive control reg: unicast + multicast + no FCS */
859 gma_write16(hw, port, GM_RX_CTRL,
793b883e 860 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 861
862 /* transmit flow control */
863 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
864
865 /* transmit parameter */
866 gma_write16(hw, port, GM_TX_PARAM,
867 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
868 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
869 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
870 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
871
872 /* serial mode register */
873 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 874 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 875
6b1a3aef 876 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 877 reg |= GM_SMOD_JUMBO_ENA;
878
879 gma_write16(hw, port, GM_SERIAL_MODE, reg);
880
cd28ab6a
SH		 881 /* virtual address for data */
882 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
883
793b883e
SH		 884 /* physical address: used for pause frames */
885 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
886
887 /* ignore counter overflows */
cd28ab6a
SH		 888 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
889 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
890 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
891
892 /* Configure Rx MAC FIFO */
893 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 894 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 895 if (hw->chip_id == CHIP_ID_YUKON_EX ||
896 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 897 rx_reg |= GMF_RX_OVER_ON;
69161611 898
25cccecc 899 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 900
798fdd07
SH		 901 if (hw->chip_id == CHIP_ID_YUKON_XL) {
902 /* Hardware errata - clear flush mask */
903 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
904 } else {
905 /* Flush Rx MAC FIFO on any flow control or error */
906 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
907 }
cd28ab6a 908
8df9a876 909 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 910 reg = RX_GMF_FL_THR_DEF + 1;
911 /* Another magic mystery workaround from sk98lin */
912 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
913 hw->chip_rev == CHIP_REV_YU_FE2_A0)
914 reg = 0x178;
915 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 916
917 /* Configure Tx MAC FIFO */
918 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
919 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 920
e0c28116 921 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 922 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 923 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 924 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
925 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 926 reg = 1568 / 8;
927 else
928 reg = 1024 / 8;
929 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
930 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 931
69161611 932 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 933 }
934
e970d1f8
SH		 935 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
936 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
937 /* disable dynamic watermark */
938 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
939 reg &= ~TX_DYN_WM_ENA;
940 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
941 }
cd28ab6a
SH		 942}
943
67712901
SH		 944/* Assign Ram Buffer allocation to queue */
945static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 946{
67712901
SH		 947 u32 end;
948
949 /* convert from K bytes to qwords used for hw register */
950 start *= 1024/8;
951 space *= 1024/8;
952 end = start + space - 1;
793b883e 953
cd28ab6a
SH		 954 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
955 sky2_write32(hw, RB_ADDR(q, RB_START), start);
956 sky2_write32(hw, RB_ADDR(q, RB_END), end);
957 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
958 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
959
960 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 961 u32 tp = space - space/4;
793b883e 962
1c28f6ba
SH		 963 /* On receive queue's set the thresholds
964 * give receiver priority when > 3/4 full
965 * send pause when down to 2K
966 */
967 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
968 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 969
1c28f6ba
SH		 970 tp = space - 2048/8;
971 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
972 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 973 } else {
974 /* Enable store & forward on Tx queue's because
975 * Tx FIFO is only 1K on Yukon
976 */
977 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
978 }
979
980 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 981 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 982}
983
cd28ab6a 984/* Setup Bus Memory Interface */
af4ed7e6 985static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 986{
987 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
988 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
989 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 990 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 991}
992
cd28ab6a
SH		 993/* Setup prefetch unit registers. This is the interface between
994 * hardware and driver list elements
995 */
8cc048e3 996static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 997 dma_addr_t addr, u32 last)
cd28ab6a 998{
cd28ab6a
SH		 999 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1000 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1001 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1002 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1003 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1004 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1005
1006 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1007}
1008
9b289c33 1009static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1010{
9b289c33 1011 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1012
ee5f68fe 1013 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1014 le->ctrl = 0;
793b883e
SH		 1015 return le;
1016}
cd28ab6a 1017
88f5f0ca
SH		 1018static void tx_init(struct sky2_port *sky2)
1019{
1020 struct sky2_tx_le *le;
1021
1022 sky2->tx_prod = sky2->tx_cons = 0;
1023 sky2->tx_tcpsum = 0;
1024 sky2->tx_last_mss = 0;
1025
9b289c33 1026 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1027 le->addr = 0;
1028 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1029 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1030}
1031
290d4de5
SH		 1032/* Update chip's next pointer */
1033static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1034{
50432cb5 1035 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1036 wmb();
50432cb5
SH		 1037 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1038
1039 /* Synchronize I/O on since next processor may write to tail */
1040 mmiowb();
cd28ab6a
SH		 1041}
1042
793b883e 1043
cd28ab6a
SH		 1044static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1045{
1046 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1047 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1048 le->ctrl = 0;
cd28ab6a
SH		 1049 return le;
1050}
1051
39ef110b
MM		 1052static unsigned sky2_get_rx_threshold(struct sky2_port* sky2)
1053{
1054 unsigned size;
1055
1056 /* Space needed for frame data + headers rounded up */
1057 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1058
1059 /* Stopping point for hardware truncation */
1060 return (size - 8) / sizeof(u32);
1061}
1062
1063static unsigned sky2_get_rx_data_size(struct sky2_port* sky2)
1064{
1065 struct rx_ring_info *re;
1066 unsigned size;
1067
1068 /* Space needed for frame data + headers rounded up */
1069 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1070
1071 sky2->rx_nfrags = size >> PAGE_SHIFT;
1072 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1073
1074 /* Compute residue after pages */
1075 size -= sky2->rx_nfrags << PAGE_SHIFT;
1076
1077 /* Optimize to handle small packets and headers */
1078 if (size < copybreak)
1079 size = copybreak;
1080 if (size < ETH_HLEN)
1081 size = ETH_HLEN;
1082
1083 return size;
1084}
1085
14d0263f
SH		 1086/* Build description to hardware for one receive segment */
1087static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1088 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1089{
1090 struct sky2_rx_le *le;
1091
86c6887e 1092 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1093 le = sky2_next_rx(sky2);
86c6887e 1094 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1095 le->opcode = OP_ADDR64 | HW_OWNER;
1096 }
793b883e 1097
cd28ab6a 1098 le = sky2_next_rx(sky2);
d6e74b6b 1099 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1100 le->length = cpu_to_le16(len);
14d0263f 1101 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1102}
1103
14d0263f
SH		 1104/* Build description to hardware for one possibly fragmented skb */
1105static void sky2_rx_submit(struct sky2_port *sky2,
1106 const struct rx_ring_info *re)
1107{
1108 int i;
1109
1110 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1111
1112 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1113 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1114}
1115
1116
454e6cb6 1117static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1118 unsigned size)
1119{
1120 struct sk_buff *skb = re->skb;
1121 int i;
1122
1123 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1124 if (pci_dma_mapping_error(pdev, re->data_addr))
1125 goto mapping_error;
454e6cb6 1126
14d0263f
SH		 1127 pci_unmap_len_set(re, data_size, size);
1128
3fbd9187 1129 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1130 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1131
1132 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1133 frag->page_offset,
1134 frag->size,
14d0263f 1135 PCI_DMA_FROMDEVICE);
3fbd9187 1136
1137 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1138 goto map_page_error;
1139 }
454e6cb6 1140 return 0;
3fbd9187 1141
1142map_page_error:
1143 while (--i >= 0) {
1144 pci_unmap_page(pdev, re->frag_addr[i],
1145 skb_shinfo(skb)->frags[i].size,
1146 PCI_DMA_FROMDEVICE);
1147 }
1148
1149 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1150 PCI_DMA_FROMDEVICE);
1151
1152mapping_error:
1153 if (net_ratelimit())
1154 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1155 skb->dev->name);
1156 return -EIO;
14d0263f
SH		 1157}
1158
1159static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1160{
1161 struct sk_buff *skb = re->skb;
1162 int i;
1163
1164 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1165 PCI_DMA_FROMDEVICE);
1166
1167 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1168 pci_unmap_page(pdev, re->frag_addr[i],
1169 skb_shinfo(skb)->frags[i].size,
1170 PCI_DMA_FROMDEVICE);
1171}
793b883e 1172
cd28ab6a
SH		 1173/* Tell chip where to start receive checksum.
1174 * Actually has two checksums, but set both same to avoid possible byte
1175 * order problems.
1176 */
793b883e 1177static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1178{
ea76e635 1179 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1180
ea76e635
SH		 1181 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1182 le->ctrl = 0;
1183 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1184
ea76e635
SH		 1185 sky2_write32(sky2->hw,
1186 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1187 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1188 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1189}
1190
6b1a3aef
SH		 1191/*
1192 * The RX Stop command will not work for Yukon-2 if the BMU does not
1193 * reach the end of packet and since we can't make sure that we have
1194 * incoming data, we must reset the BMU while it is not doing a DMA
1195 * transfer. Since it is possible that the RX path is still active,
1196 * the RX RAM buffer will be stopped first, so any possible incoming
1197 * data will not trigger a DMA. After the RAM buffer is stopped, the
1198 * BMU is polled until any DMA in progress is ended and only then it
1199 * will be reset.
1200 */
1201static void sky2_rx_stop(struct sky2_port *sky2)
1202{
1203 struct sky2_hw *hw = sky2->hw;
1204 unsigned rxq = rxqaddr[sky2->port];
1205 int i;
1206
1207 /* disable the RAM Buffer receive queue */
1208 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1209
1210 for (i = 0; i < 0xffff; i++)
1211 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1212 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1213 goto stopped;
1214
1215 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1216 sky2->netdev->name);
1217stopped:
1218 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1219
1220 /* reset the Rx prefetch unit */
1221 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1222 mmiowb();
6b1a3aef 1223}
793b883e 1224
d571b694 1225/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1226static void sky2_rx_clean(struct sky2_port *sky2)
1227{
1228 unsigned i;
1229
1230 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1231 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1232 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1233
1234 if (re->skb) {
14d0263f 1235 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1236 kfree_skb(re->skb);
1237 re->skb = NULL;
1238 }
1239 }
1240}
1241
ef743d33
SH		 1242/* Basic MII support */
1243static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1244{
1245 struct mii_ioctl_data *data = if_mii(ifr);
1246 struct sky2_port *sky2 = netdev_priv(dev);
1247 struct sky2_hw *hw = sky2->hw;
1248 int err = -EOPNOTSUPP;
1249
1250 if (!netif_running(dev))
1251 return -ENODEV; /* Phy still in reset */
1252
d89e1343 1253 switch (cmd) {
ef743d33
SH		 1254 case SIOCGMIIPHY:
1255 data->phy_id = PHY_ADDR_MARV;
1256
1257 /* fallthru */
1258 case SIOCGMIIREG: {
1259 u16 val = 0;
91c86df5 1260
e07b1aa8 1261 spin_lock_bh(&sky2->phy_lock);
ef743d33 1262 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1263 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1264
ef743d33
SH		 1265 data->val_out = val;
1266 break;
1267 }
1268
1269 case SIOCSMIIREG:
e07b1aa8 1270 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1271 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1272 data->val_in);
e07b1aa8 1273 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1274 break;
1275 }
1276 return err;
1277}
1278
d1f13708 1279#ifdef SKY2_VLAN_TAG_USED
d494eacd 1280static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1281{
d494eacd 1282 if (onoff) {
3d4e66f5
SH		 1283 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1284 RX_VLAN_STRIP_ON);
1285 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1286 TX_VLAN_TAG_ON);
1287 } else {
1288 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1289 RX_VLAN_STRIP_OFF);
1290 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1291 TX_VLAN_TAG_OFF);
1292 }
d494eacd
SH		 1293}
1294
1295static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1296{
1297 struct sky2_port *sky2 = netdev_priv(dev);
1298 struct sky2_hw *hw = sky2->hw;
1299 u16 port = sky2->port;
1300
1301 netif_tx_lock_bh(dev);
1302 napi_disable(&hw->napi);
1303
1304 sky2->vlgrp = grp;
1305 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1306
d1d08d12 1307 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1308 napi_enable(&hw->napi);
2bb8c262 1309 netif_tx_unlock_bh(dev);
d1f13708
SH		 1310}
1311#endif
1312
bd1c6869
SH		 1313/* Amount of required worst case padding in rx buffer */
1314static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1315{
1316 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1317}
1318
82788c7a 1319/*
14d0263f
SH		 1320 * Allocate an skb for receiving. If the MTU is large enough
1321 * make the skb non-linear with a fragment list of pages.
82788c7a 1322 */
14d0263f 1323static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1324{
1325 struct sk_buff *skb;
14d0263f 1326 int i;
82788c7a 1327
724b6942
SH		 1328 skb = netdev_alloc_skb(sky2->netdev,
1329 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1330 if (!skb)
1331 goto nomem;
1332
39dbd958 1333 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1334 unsigned char *start;
1335 /*
1336 * Workaround for a bug in FIFO that cause hang
1337 * if the FIFO if the receive buffer is not 64 byte aligned.
1338 * The buffer returned from netdev_alloc_skb is
1339 * aligned except if slab debugging is enabled.
1340 */
f03b8654
SH		 1341 start = PTR_ALIGN(skb->data, 8);
1342 skb_reserve(skb, start - skb->data);
bd1c6869 1343 } else
f03b8654 1344 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1345
1346 for (i = 0; i < sky2->rx_nfrags; i++) {
1347 struct page *page = alloc_page(GFP_ATOMIC);
1348
1349 if (!page)
1350 goto free_partial;
1351 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1352 }
1353
1354 return skb;
14d0263f
SH		 1355free_partial:
1356 kfree_skb(skb);
1357nomem:
1358 return NULL;
82788c7a
SH		 1359}
1360
55c9dd35
SH		 1361static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1362{
1363 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1364}
1365
200ac492
MM		 1366static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1367{
1368 struct sky2_hw *hw = sky2->hw;
1369 unsigned i;
1370
1371 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1372
1373 /* Fill Rx ring */
1374 for (i = 0; i < sky2->rx_pending; i++) {
1375 struct rx_ring_info *re = sky2->rx_ring + i;
1376
1377 re->skb = sky2_rx_alloc(sky2);
1378 if (!re->skb)
1379 return -ENOMEM;
1380
1381 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1382 dev_kfree_skb(re->skb);
1383 re->skb = NULL;
1384 return -ENOMEM;
1385 }
1386 }
1387 return 0;
1388}
1389
cd28ab6a 1390/*
200ac492 1391 * Setup receiver buffer pool.
14d0263f
SH		 1392 * Normal case this ends up creating one list element for skb
1393 * in the receive ring. Worst case if using large MTU and each
1394 * allocation falls on a different 64 bit region, that results
1395 * in 6 list elements per ring entry.
1396 * One element is used for checksum enable/disable, and one
1397 * extra to avoid wrap.
cd28ab6a 1398 */
200ac492 1399static void sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1400{
6b1a3aef 1401 struct sky2_hw *hw = sky2->hw;
14d0263f 1402 struct rx_ring_info *re;
6b1a3aef 1403 unsigned rxq = rxqaddr[sky2->port];
39ef110b 1404 unsigned i, thresh;
cd28ab6a 1405
6b1a3aef 1406 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1407 sky2_qset(hw, rxq);
977bdf06 1408
c3905bc4
SH		 1409 /* On PCI express lowering the watermark gives better performance */
1410 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1411 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1412
1413 /* These chips have no ram buffer?
1414 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1415 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
8e95a202
JP		 1416 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1417 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1418 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1419
6b1a3aef
SH		 1420 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1421
ea76e635
SH		 1422 if (!(hw->flags & SKY2_HW_NEW_LE))
1423 rx_set_checksum(sky2);
14d0263f 1424
200ac492 1425 /* submit Rx ring */
793b883e 1426 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1427 re = sky2->rx_ring + i;
14d0263f 1428 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1429 }
1430
a1433ac4
SH		 1431 /*
1432 * The receiver hangs if it receives frames larger than the
1433 * packet buffer. As a workaround, truncate oversize frames, but
1434 * the register is limited to 9 bits, so if you do frames > 2052
1435 * you better get the MTU right!
1436 */
39ef110b 1437 thresh = sky2_get_rx_threshold(sky2);
a1433ac4
SH		 1438 if (thresh > 0x1ff)
1439 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1440 else {
1441 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1442 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1443 }
1444
6b1a3aef 1445 /* Tell chip about available buffers */
55c9dd35 1446 sky2_rx_update(sky2, rxq);
877c8570
SH		 1447
1448 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1449 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1450 /*
1451 * Disable flushing of non ASF packets;
1452 * must be done after initializing the BMUs;
1453 * drivers without ASF support should do this too, otherwise
1454 * it may happen that they cannot run on ASF devices;
1455 * remember that the MAC FIFO isn't reset during initialization.
1456 */
1457 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1458 }
1459
1460 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1461 /* Enable RX Home Address & Routing Header checksum fix */
1462 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1463 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1464
1465 /* Enable TX Home Address & Routing Header checksum fix */
1466 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1467 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1468 }
cd28ab6a
SH		 1469}
1470
90bbebb4
MM		 1471static int sky2_alloc_buffers(struct sky2_port *sky2)
1472{
1473 struct sky2_hw *hw = sky2->hw;
1474
1475 /* must be power of 2 */
1476 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1477 sky2->tx_ring_size *
1478 sizeof(struct sky2_tx_le),
1479 &sky2->tx_le_map);
1480 if (!sky2->tx_le)
1481 goto nomem;
1482
1483 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1484 GFP_KERNEL);
1485 if (!sky2->tx_ring)
1486 goto nomem;
1487
1488 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1489 &sky2->rx_le_map);
1490 if (!sky2->rx_le)
1491 goto nomem;
1492 memset(sky2->rx_le, 0, RX_LE_BYTES);
1493
1494 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1495 GFP_KERNEL);
1496 if (!sky2->rx_ring)
1497 goto nomem;
1498
200ac492 1499 return sky2_alloc_rx_skbs(sky2);
90bbebb4
MM		 1500nomem:
1501 return -ENOMEM;
1502}
1503
1504static void sky2_free_buffers(struct sky2_port *sky2)
1505{
1506 struct sky2_hw *hw = sky2->hw;
1507
200ac492
MM		 1508 sky2_rx_clean(sky2);
1509
90bbebb4
MM		 1510 if (sky2->rx_le) {
1511 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1512 sky2->rx_le, sky2->rx_le_map);
1513 sky2->rx_le = NULL;
1514 }
1515 if (sky2->tx_le) {
1516 pci_free_consistent(hw->pdev,
1517 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1518 sky2->tx_le, sky2->tx_le_map);
1519 sky2->tx_le = NULL;
1520 }
1521 kfree(sky2->tx_ring);
1522 kfree(sky2->rx_ring);
1523
1524 sky2->tx_ring = NULL;
1525 sky2->rx_ring = NULL;
1526}
1527
ea0f71e5 1528static void sky2_hw_up(struct sky2_port *sky2)
cd28ab6a 1529{
cd28ab6a
SH		 1530 struct sky2_hw *hw = sky2->hw;
1531 unsigned port = sky2->port;
ea0f71e5
MM		 1532 u32 ramsize;
1533 int cap;
843a46f4 1534 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1535
ea0f71e5
MM		 1536 tx_init(sky2);
1537
ee7abb04
SH		 1538 /*
1539 * On dual port PCI-X card, there is an problem where status
1540 * can be received out of order due to split transactions
843a46f4 1541 */
ee7abb04
SH		 1542 if (otherdev && netif_running(otherdev) &&
1543 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1544 u16 cmd;
1545
b32f40c4 1546 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1547 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4 1548 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
ea0f71e5 1549 }
cd28ab6a 1550
cd28ab6a
SH		 1551 sky2_mac_init(hw, port);
1552
e0c28116
SH		 1553 /* Register is number of 4K blocks on internal RAM buffer. */
1554 ramsize = sky2_read8(hw, B2_E_0) * 4;
1555 if (ramsize > 0) {
67712901 1556 u32 rxspace;
cd28ab6a 1557
ea0f71e5 1558 pr_debug(PFX "%s: ram buffer %dK\n", sky2->netdev->name, ramsize);
67712901
SH		 1559 if (ramsize < 16)
1560 rxspace = ramsize / 2;
1561 else
1562 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1563
67712901
SH		 1564 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1565 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1566
1567 /* Make sure SyncQ is disabled */
1568 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1569 RB_RST_SET);
1570 }
793b883e 1571
af4ed7e6 1572 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1573
69161611
SH		 1574 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1575 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1576 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1577
977bdf06 1578 /* Set almost empty threshold */
8e95a202
JP		 1579 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1580 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1581 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1582
6b1a3aef 1583 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1584 sky2->tx_ring_size - 1);
cd28ab6a 1585
d494eacd
SH		 1586#ifdef SKY2_VLAN_TAG_USED
1587 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1588#endif
1589
200ac492 1590 sky2_rx_start(sky2);
ea0f71e5
MM		 1591}
1592
1593/* Bring up network interface. */
1594static int sky2_up(struct net_device *dev)
1595{
1596 struct sky2_port *sky2 = netdev_priv(dev);
1597 struct sky2_hw *hw = sky2->hw;
1598 unsigned port = sky2->port;
1599 u32 imask;
1600 int err;
1601
1602 netif_carrier_off(dev);
1603
1604 err = sky2_alloc_buffers(sky2);
1605 if (err)
1606 goto err_out;
1607
1608 sky2_hw_up(sky2);
cd28ab6a 1609
cd28ab6a 1610 /* Enable interrupts from phy/mac for port */
e07b1aa8 1611 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1612 imask |= portirq_msk[port];
e07b1aa8 1613 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1614 sky2_read32(hw, B0_IMSK);
e07b1aa8 1615
a11da890
AD		 1616 if (netif_msg_ifup(sky2))
1617 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
af18d8b8 1618
cd28ab6a
SH		 1619 return 0;
1620
1621err_out:
90bbebb4 1622 sky2_free_buffers(sky2);
cd28ab6a
SH		 1623 return err;
1624}
1625
793b883e 1626/* Modular subtraction in ring */
ee5f68fe 1627static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1628{
ee5f68fe 1629 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1630}
cd28ab6a 1631
793b883e
SH		 1632/* Number of list elements available for next tx */
1633static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1634{
ee5f68fe 1635 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1636}
1637
793b883e 1638/* Estimate of number of transmit list elements required */
28bd181a 1639static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1640{
793b883e
SH		 1641 unsigned count;
1642
07e31637
SH		 1643 count = (skb_shinfo(skb)->nr_frags + 1)
1644 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1645
89114afd 1646 if (skb_is_gso(skb))
793b883e 1647 ++count;
07e31637
SH		 1648 else if (sizeof(dma_addr_t) == sizeof(u32))
1649 ++count; /* possible vlan */
793b883e 1650
84fa7933 1651 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1652 ++count;
1653
1654 return count;
cd28ab6a
SH		 1655}
1656
f6815077 1657static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1658{
1659 if (re->flags & TX_MAP_SINGLE)
1660 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1661 pci_unmap_len(re, maplen),
1662 PCI_DMA_TODEVICE);
1663 else if (re->flags & TX_MAP_PAGE)
1664 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1665 pci_unmap_len(re, maplen),
1666 PCI_DMA_TODEVICE);
f6815077 1667 re->flags = 0;
6b84daca
SH		 1668}
1669
793b883e
SH		 1670/*
1671 * Put one packet in ring for transmit.
1672 * A single packet can generate multiple list elements, and
1673 * the number of ring elements will probably be less than the number
1674 * of list elements used.
1675 */
61357325
SH		 1676static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1677 struct net_device *dev)
cd28ab6a
SH		 1678{
1679 struct sky2_port *sky2 = netdev_priv(dev);
1680 struct sky2_hw *hw = sky2->hw;
d1f13708 1681 struct sky2_tx_le *le = NULL;
6cdbbdf3 1682 struct tx_ring_info *re;
9b289c33 1683 unsigned i, len;
cd28ab6a 1684 dma_addr_t mapping;
5dce95e5
SH		 1685 u32 upper;
1686 u16 slot;
cd28ab6a
SH		 1687 u16 mss;
1688 u8 ctrl;
1689
2bb8c262
SH		 1690 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1691 return NETDEV_TX_BUSY;
cd28ab6a 1692
cd28ab6a
SH		 1693 len = skb_headlen(skb);
1694 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1695
454e6cb6
SH		 1696 if (pci_dma_mapping_error(hw->pdev, mapping))
1697 goto mapping_error;
1698
9b289c33 1699 slot = sky2->tx_prod;
454e6cb6
SH		 1700 if (unlikely(netif_msg_tx_queued(sky2)))
1701 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
9b289c33 1702 dev->name, slot, skb->len);
454e6cb6 1703
86c6887e 1704 /* Send high bits if needed */
5dce95e5
SH		 1705 upper = upper_32_bits(mapping);
1706 if (upper != sky2->tx_last_upper) {
9b289c33 1707 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1708 le->addr = cpu_to_le32(upper);
1709 sky2->tx_last_upper = upper;
793b883e 1710 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1711 }
cd28ab6a
SH		 1712
1713 /* Check for TCP Segmentation Offload */
7967168c 1714 mss = skb_shinfo(skb)->gso_size;
793b883e 1715 if (mss != 0) {
ea76e635
SH		 1716
1717 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1718 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1719
1720 if (mss != sky2->tx_last_mss) {
9b289c33 1721 le = get_tx_le(sky2, &slot);
69161611 1722 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1723
1724 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1725 le->opcode = OP_MSS | HW_OWNER;
1726 else
1727 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1728 sky2->tx_last_mss = mss;
1729 }
cd28ab6a
SH		 1730 }
1731
cd28ab6a 1732 ctrl = 0;
d1f13708
SH		 1733#ifdef SKY2_VLAN_TAG_USED
1734 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1735 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1736 if (!le) {
9b289c33 1737 le = get_tx_le(sky2, &slot);
f65b138c 1738 le->addr = 0;
d1f13708 1739 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1740 } else
1741 le->opcode |= OP_VLAN;
1742 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1743 ctrl |= INS_VLAN;
1744 }
1745#endif
1746
1747 /* Handle TCP checksum offload */
84fa7933 1748 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1749 /* On Yukon EX (some versions) encoding change. */
ea76e635 1750 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1751 ctrl |= CALSUM; /* auto checksum */
1752 else {
1753 const unsigned offset = skb_transport_offset(skb);
1754 u32 tcpsum;
1755
1756 tcpsum = offset << 16; /* sum start */
1757 tcpsum |= offset + skb->csum_offset; /* sum write */
1758
1759 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1760 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1761 ctrl |= UDPTCP;
1762
1763 if (tcpsum != sky2->tx_tcpsum) {
1764 sky2->tx_tcpsum = tcpsum;
1765
9b289c33 1766 le = get_tx_le(sky2, &slot);
69161611
SH		 1767 le->addr = cpu_to_le32(tcpsum);
1768 le->length = 0; /* initial checksum value */
1769 le->ctrl = 1; /* one packet */
1770 le->opcode = OP_TCPLISW | HW_OWNER;
1771 }
1d179332 1772 }
cd28ab6a
SH		 1773 }
1774
6b84daca
SH		 1775 re = sky2->tx_ring + slot;
1776 re->flags = TX_MAP_SINGLE;
1777 pci_unmap_addr_set(re, mapaddr, mapping);
1778 pci_unmap_len_set(re, maplen, len);
1779
9b289c33 1780 le = get_tx_le(sky2, &slot);
d6e74b6b 1781 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1782 le->length = cpu_to_le16(len);
1783 le->ctrl = ctrl;
793b883e 1784 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1785
cd28ab6a
SH		 1786
1787 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1788 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1789
1790 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1791 frag->size, PCI_DMA_TODEVICE);
86c6887e 1792
454e6cb6
SH		 1793 if (pci_dma_mapping_error(hw->pdev, mapping))
1794 goto mapping_unwind;
1795
5dce95e5
SH		 1796 upper = upper_32_bits(mapping);
1797 if (upper != sky2->tx_last_upper) {
9b289c33 1798 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1799 le->addr = cpu_to_le32(upper);
1800 sky2->tx_last_upper = upper;
793b883e 1801 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1802 }
1803
6b84daca
SH		 1804 re = sky2->tx_ring + slot;
1805 re->flags = TX_MAP_PAGE;
1806 pci_unmap_addr_set(re, mapaddr, mapping);
1807 pci_unmap_len_set(re, maplen, frag->size);
1808
9b289c33 1809 le = get_tx_le(sky2, &slot);
d6e74b6b 1810 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1811 le->length = cpu_to_le16(frag->size);
1812 le->ctrl = ctrl;
793b883e 1813 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1814 }
6cdbbdf3 1815
6b84daca 1816 re->skb = skb;
cd28ab6a
SH		 1817 le->ctrl |= EOP;
1818
9b289c33
MM		 1819 sky2->tx_prod = slot;
1820
97bda706
SH		 1821 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1822 netif_stop_queue(dev);
b19666d9 1823
290d4de5 1824 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1825
cd28ab6a 1826 return NETDEV_TX_OK;
454e6cb6
SH		 1827
1828mapping_unwind:
ee5f68fe 1829 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1830 re = sky2->tx_ring + i;
1831
6b84daca 1832 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1833 }
1834
454e6cb6
SH		 1835mapping_error:
1836 if (net_ratelimit())
1837 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1838 dev_kfree_skb(skb);
1839 return NETDEV_TX_OK;
cd28ab6a
SH		 1840}
1841
cd28ab6a 1842/*
793b883e
SH		 1843 * Free ring elements from starting at tx_cons until "done"
1844 *
481cea4a
SH		 1845 * NB:
1846 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1847 * buffers so make sure not to free skb to early.
481cea4a
SH		 1848 * 2. This may run in parallel start_xmit because the it only
1849 * looks at the tail of the queue of FIFO (tx_cons), not
1850 * the head (tx_prod)
cd28ab6a 1851 */
d11c13e7 1852static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1853{
d11c13e7 1854 struct net_device *dev = sky2->netdev;
291ea614 1855 unsigned idx;
cd28ab6a 1856
ee5f68fe 1857 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1858
291ea614 1859 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1860 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1861 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1862 struct sk_buff *skb = re->skb;
291ea614 1863
6b84daca 1864 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1865
6b84daca 1866 if (skb) {
291ea614
SH		 1867 if (unlikely(netif_msg_tx_done(sky2)))
1868 printk(KERN_DEBUG "%s: tx done %u\n",
1869 dev->name, idx);
3cf26753 1870
7138a0f5 1871 dev->stats.tx_packets++;
bd1c6869
SH		 1872 dev->stats.tx_bytes += skb->len;
1873
f6815077 1874 re->skb = NULL;
724b6942 1875 dev_kfree_skb_any(skb);
2bf56fe2 1876
ee5f68fe 1877 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1878 }
793b883e 1879 }
793b883e 1880
291ea614 1881 sky2->tx_cons = idx;
50432cb5
SH		 1882 smp_mb();
1883
9db2f1be
JP		 1884 /* Wake unless it's detached, and called e.g. from sky2_down() */
1885 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4 && netif_device_present(dev))
cd28ab6a 1886 netif_wake_queue(dev);
cd28ab6a
SH		 1887}
1888
264bb4fa 1889static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1890{
a510996b
MM		 1891 /* Disable Force Sync bit and Enable Alloc bit */
1892 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1893 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1894
1895 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1896 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1897 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1898
1899 /* Reset the PCI FIFO of the async Tx queue */
1900 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1901 BMU_RST_SET | BMU_FIFO_RST);
1902
1903 /* Reset the Tx prefetch units */
1904 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1905 PREF_UNIT_RST_SET);
1906
1907 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1908 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1909}
1910
cd28ab6a
SH		 1911/* Network shutdown */
1912static int sky2_down(struct net_device *dev)
1913{
1914 struct sky2_port *sky2 = netdev_priv(dev);
1915 struct sky2_hw *hw = sky2->hw;
1916 unsigned port = sky2->port;
1917 u16 ctrl;
e07b1aa8 1918 u32 imask;
cd28ab6a 1919
1b537565
SH		 1920 /* Never really got started! */
1921 if (!sky2->tx_le)
1922 return 0;
1923
cd28ab6a
SH		 1924 if (netif_msg_ifdown(sky2))
1925 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1926
d104acaf
SH		 1927 /* Force flow control off */
1928 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1929
cd28ab6a
SH		 1930 /* Stop transmitter */
1931 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1932 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1933
1934 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1935 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1936
1937 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1938 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1939 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1940
1941 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1942
1943 /* Workaround shared GMAC reset */
8e95a202
JP		 1944 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1945 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1946 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1947
cd28ab6a 1948 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1949
6c83504f
SH		 1950 /* Force any delayed status interrrupt and NAPI */
1951 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1952 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1953 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1954 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1955
a947a39d
MM		 1956 sky2_rx_stop(sky2);
1957
1958 /* Disable port IRQ */
1959 imask = sky2_read32(hw, B0_IMSK);
1960 imask &= ~portirq_msk[port];
1961 sky2_write32(hw, B0_IMSK, imask);
1962 sky2_read32(hw, B0_IMSK);
1963
6c83504f
SH		 1964 synchronize_irq(hw->pdev->irq);
1965 napi_synchronize(&hw->napi);
1966
0da6d7b3 1967 spin_lock_bh(&sky2->phy_lock);
b96936da 1968 sky2_phy_power_down(hw, port);
0da6d7b3 1969 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1970
264bb4fa
MM		 1971 sky2_tx_reset(hw, port);
1972
481cea4a
SH		 1973 /* Free any pending frames stuck in HW queue */
1974 sky2_tx_complete(sky2, sky2->tx_prod);
1975
90bbebb4 1976 sky2_free_buffers(sky2);
1b537565 1977
cd28ab6a
SH		 1978 return 0;
1979}
1980
1981static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1982{
ea76e635 1983 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1984 return SPEED_1000;
1985
05745c4a
SH		 1986 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1987 if (aux & PHY_M_PS_SPEED_100)
1988 return SPEED_100;
1989 else
1990 return SPEED_10;
1991 }
cd28ab6a
SH		 1992
1993 switch (aux & PHY_M_PS_SPEED_MSK) {
1994 case PHY_M_PS_SPEED_1000:
1995 return SPEED_1000;
1996 case PHY_M_PS_SPEED_100:
1997 return SPEED_100;
1998 default:
1999 return SPEED_10;
2000 }
2001}
2002
2003static void sky2_link_up(struct sky2_port *sky2)
2004{
2005 struct sky2_hw *hw = sky2->hw;
2006 unsigned port = sky2->port;
2007 u16 reg;
16ad91e1
SH		 2008 static const char *fc_name[] = {
2009 [FC_NONE] = "none",
2010 [FC_TX] = "tx",
2011 [FC_RX] = "rx",
2012 [FC_BOTH] = "both",
2013 };
cd28ab6a 2014
cd28ab6a 2015 /* enable Rx/Tx */
2eaba1a2 2016 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 2017 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2018 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 2019
2020 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2021
2022 netif_carrier_on(sky2->netdev);
cd28ab6a 2023
75e80683 2024 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 2025
cd28ab6a 2026 /* Turn on link LED */
793b883e 2027 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2028 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2029
2030 if (netif_msg_link(sky2))
2031 printk(KERN_INFO PFX
d571b694 2032 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 2033 sky2->netdev->name, sky2->speed,
2034 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 2035 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2036}
2037
2038static void sky2_link_down(struct sky2_port *sky2)
2039{
2040 struct sky2_hw *hw = sky2->hw;
2041 unsigned port = sky2->port;
2042 u16 reg;
2043
2044 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2045
2046 reg = gma_read16(hw, port, GM_GP_CTRL);
2047 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2048 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2049
cd28ab6a 2050 netif_carrier_off(sky2->netdev);
cd28ab6a 2051
809aaaae 2052 /* Turn off link LED */
cd28ab6a
SH		 2053 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2054
2055 if (netif_msg_link(sky2))
2056 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 2057
cd28ab6a
SH		 2058 sky2_phy_init(hw, port);
2059}
2060
16ad91e1
SH		 2061static enum flow_control sky2_flow(int rx, int tx)
2062{
2063 if (rx)
2064 return tx ? FC_BOTH : FC_RX;
2065 else
2066 return tx ? FC_TX : FC_NONE;
2067}
2068
793b883e
SH		 2069static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2070{
2071 struct sky2_hw *hw = sky2->hw;
2072 unsigned port = sky2->port;
da4c1ff4 2073 u16 advert, lpa;
793b883e 2074
da4c1ff4 2075 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2076 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 2077 if (lpa & PHY_M_AN_RF) {
2078 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2079 return -1;
2080 }
2081
793b883e
SH		 2082 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2083 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2084 sky2->netdev->name);
2085 return -1;
2086 }
2087
793b883e 2088 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2089 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2090
da4c1ff4
SH		 2091 /* Since the pause result bits seem to in different positions on
2092 * different chips. look at registers.
2093 */
ea76e635 2094 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2095 /* Shift for bits in fiber PHY */
2096 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2097 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2098
2099 if (advert & ADVERTISE_1000XPAUSE)
2100 advert |= ADVERTISE_PAUSE_CAP;
2101 if (advert & ADVERTISE_1000XPSE_ASYM)
2102 advert |= ADVERTISE_PAUSE_ASYM;
2103 if (lpa & LPA_1000XPAUSE)
2104 lpa |= LPA_PAUSE_CAP;
2105 if (lpa & LPA_1000XPAUSE_ASYM)
2106 lpa |= LPA_PAUSE_ASYM;
2107 }
793b883e 2108
da4c1ff4
SH		 2109 sky2->flow_status = FC_NONE;
2110 if (advert & ADVERTISE_PAUSE_CAP) {
2111 if (lpa & LPA_PAUSE_CAP)
2112 sky2->flow_status = FC_BOTH;
2113 else if (advert & ADVERTISE_PAUSE_ASYM)
2114 sky2->flow_status = FC_RX;
2115 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2116 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2117 sky2->flow_status = FC_TX;
2118 }
793b883e 2119
8e95a202
JP		 2120 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2121 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2122 sky2->flow_status = FC_NONE;
2eaba1a2 2123
da4c1ff4 2124 if (sky2->flow_status & FC_TX)
793b883e
SH		 2125 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2126 else
2127 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2128
2129 return 0;
2130}
cd28ab6a 2131
e07b1aa8
SH		 2132/* Interrupt from PHY */
2133static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2134{
e07b1aa8
SH		 2135 struct net_device *dev = hw->dev[port];
2136 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2137 u16 istatus, phystat;
2138
ebc646f6
SH		 2139 if (!netif_running(dev))
2140 return;
2141
e07b1aa8
SH		 2142 spin_lock(&sky2->phy_lock);
2143 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2144 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2145
cd28ab6a
SH		 2146 if (netif_msg_intr(sky2))
2147 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2148 sky2->netdev->name, istatus, phystat);
2149
0ea065e5 2150 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2151 if (sky2_autoneg_done(sky2, phystat) == 0)
2152 sky2_link_up(sky2);
2153 goto out;
2154 }
cd28ab6a 2155
793b883e
SH		 2156 if (istatus & PHY_M_IS_LSP_CHANGE)
2157 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2158
793b883e
SH		 2159 if (istatus & PHY_M_IS_DUP_CHANGE)
2160 sky2->duplex =
2161 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2162
793b883e
SH		 2163 if (istatus & PHY_M_IS_LST_CHANGE) {
2164 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2165 sky2_link_up(sky2);
793b883e
SH		 2166 else
2167 sky2_link_down(sky2);
cd28ab6a 2168 }
793b883e 2169out:
e07b1aa8 2170 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2171}
2172
0f5aac70
SH		 2173/* Special quick link interrupt (Yukon-2 Optima only) */
2174static void sky2_qlink_intr(struct sky2_hw *hw)
2175{
2176 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2177 u32 imask;
2178 u16 phy;
2179
2180 /* disable irq */
2181 imask = sky2_read32(hw, B0_IMSK);
2182 imask &= ~Y2_IS_PHY_QLNK;
2183 sky2_write32(hw, B0_IMSK, imask);
2184
2185 /* reset PHY Link Detect */
2186 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2187 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2188 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2189 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2190
2191 sky2_link_up(sky2);
2192}
2193
62335ab0 2194/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2195 * and tx queue is full (stopped).
2196 */
cd28ab6a
SH		 2197static void sky2_tx_timeout(struct net_device *dev)
2198{
2199 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2200 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2201
2202 if (netif_msg_timer(sky2))
2203 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2204
8f24664d 2205 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2206 dev->name, sky2->tx_cons, sky2->tx_prod,
2207 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2208 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2209
81906791
SH		 2210 /* can't restart safely under softirq */
2211 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2212}
2213
2214static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2215{
6b1a3aef
SH		 2216 struct sky2_port *sky2 = netdev_priv(dev);
2217 struct sky2_hw *hw = sky2->hw;
b628ed98 2218 unsigned port = sky2->port;
6b1a3aef
SH		 2219 int err;
2220 u16 ctl, mode;
e07b1aa8 2221 u32 imask;
cd28ab6a 2222
44dde56d 2223 /* MTU size outside the spec */
cd28ab6a
SH		 2224 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2225 return -EINVAL;
2226
44dde56d 2227 /* MTU > 1500 on yukon FE and FE+ not allowed */
05745c4a
SH		 2228 if (new_mtu > ETH_DATA_LEN &&
2229 (hw->chip_id == CHIP_ID_YUKON_FE ||
2230 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2231 return -EINVAL;
2232
44dde56d 2233 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2234 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
2235 dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
2236
6b1a3aef
SH		 2237 if (!netif_running(dev)) {
2238 dev->mtu = new_mtu;
2239 return 0;
2240 }
2241
e07b1aa8 2242 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2243 sky2_write32(hw, B0_IMSK, 0);
2244
018d1c66
SH		 2245 dev->trans_start = jiffies; /* prevent tx timeout */
2246 netif_stop_queue(dev);
bea3348e 2247 napi_disable(&hw->napi);
018d1c66 2248
e07b1aa8
SH		 2249 synchronize_irq(hw->pdev->irq);
2250
39dbd958 2251 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2252 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2253
2254 ctl = gma_read16(hw, port, GM_GP_CTRL);
2255 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2256 sky2_rx_stop(sky2);
2257 sky2_rx_clean(sky2);
cd28ab6a
SH		 2258
2259 dev->mtu = new_mtu;
14d0263f 2260
6b1a3aef
SH		 2261 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2262 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2263
2264 if (dev->mtu > ETH_DATA_LEN)
2265 mode |= GM_SMOD_JUMBO_ENA;
2266
b628ed98 2267 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2268
b628ed98 2269 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2270
200ac492
MM		 2271 err = sky2_alloc_rx_skbs(sky2);
2272 if (!err)
2273 sky2_rx_start(sky2);
2274 else
2275 sky2_rx_clean(sky2);
e07b1aa8 2276 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2277
d1d08d12 2278 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2279 napi_enable(&hw->napi);
2280
1b537565
SH		 2281 if (err)
2282 dev_close(dev);
2283 else {
b628ed98 2284 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2285
1b537565
SH		 2286 netif_wake_queue(dev);
2287 }
2288
cd28ab6a
SH		 2289 return err;
2290}
2291
14d0263f
SH		 2292/* For small just reuse existing skb for next receive */
2293static struct sk_buff *receive_copy(struct sky2_port *sky2,
2294 const struct rx_ring_info *re,
2295 unsigned length)
2296{
2297 struct sk_buff *skb;
2298
89d71a66 2299 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2300 if (likely(skb)) {
14d0263f
SH		 2301 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2302 length, PCI_DMA_FROMDEVICE);
d626f62b 2303 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2304 skb->ip_summed = re->skb->ip_summed;
2305 skb->csum = re->skb->csum;
2306 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2307 length, PCI_DMA_FROMDEVICE);
2308 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2309 skb_put(skb, length);
14d0263f
SH		 2310 }
2311 return skb;
2312}
2313
2314/* Adjust length of skb with fragments to match received data */
2315static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2316 unsigned int length)
2317{
2318 int i, num_frags;
2319 unsigned int size;
2320
2321 /* put header into skb */
2322 size = min(length, hdr_space);
2323 skb->tail += size;
2324 skb->len += size;
2325 length -= size;
2326
2327 num_frags = skb_shinfo(skb)->nr_frags;
2328 for (i = 0; i < num_frags; i++) {
2329 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2330
2331 if (length == 0) {
2332 /* don't need this page */
2333 __free_page(frag->page);
2334 --skb_shinfo(skb)->nr_frags;
2335 } else {
2336 size = min(length, (unsigned) PAGE_SIZE);
2337
2338 frag->size = size;
2339 skb->data_len += size;
2340 skb->truesize += size;
2341 skb->len += size;
2342 length -= size;
2343 }
2344 }
2345}
2346
2347/* Normal packet - take skb from ring element and put in a new one */
2348static struct sk_buff *receive_new(struct sky2_port *sky2,
2349 struct rx_ring_info *re,
2350 unsigned int length)
2351{
3fbd9187 2352 struct sk_buff *skb;
2353 struct rx_ring_info nre;
14d0263f
SH		 2354 unsigned hdr_space = sky2->rx_data_size;
2355
3fbd9187 2356 nre.skb = sky2_rx_alloc(sky2);
2357 if (unlikely(!nre.skb))
2358 goto nobuf;
2359
2360 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2361 goto nomap;
14d0263f
SH		 2362
2363 skb = re->skb;
2364 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2365 prefetch(skb->data);
3fbd9187 2366 *re = nre;
14d0263f
SH		 2367
2368 if (skb_shinfo(skb)->nr_frags)
2369 skb_put_frags(skb, hdr_space, length);
2370 else
489b10c1 2371 skb_put(skb, length);
14d0263f 2372 return skb;
3fbd9187 2373
2374nomap:
2375 dev_kfree_skb(nre.skb);
2376nobuf:
2377 return NULL;
14d0263f
SH		 2378}
2379
cd28ab6a
SH		 2380/*
2381 * Receive one packet.
d571b694 2382 * For larger packets, get new buffer.
cd28ab6a 2383 */
497d7c86 2384static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2385 u16 length, u32 status)
2386{
497d7c86 2387 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2388 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2389 struct sk_buff *skb = NULL;
d6532232
SH		 2390 u16 count = (status & GMR_FS_LEN) >> 16;
2391
2392#ifdef SKY2_VLAN_TAG_USED
2393 /* Account for vlan tag */
2394 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2395 count -= VLAN_HLEN;
2396#endif
cd28ab6a
SH		 2397
2398 if (unlikely(netif_msg_rx_status(sky2)))
2399 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2400 dev->name, sky2->rx_next, status, length);
cd28ab6a 2401
793b883e 2402 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2403 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2404
3b12e014
SH		 2405 /* This chip has hardware problems that generates bogus status.
2406 * So do only marginal checking and expect higher level protocols
2407 * to handle crap frames.
2408 */
2409 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2410 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2411 length != count)
2412 goto okay;
2413
42eeea01 2414 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2415 goto error;
2416
42eeea01
SH		 2417 if (!(status & GMR_FS_RX_OK))
2418 goto resubmit;
2419
d6532232
SH		 2420 /* if length reported by DMA does not match PHY, packet was truncated */
2421 if (length != count)
3b12e014 2422 goto len_error;
71749531 2423
3b12e014 2424okay:
14d0263f
SH		 2425 if (length < copybreak)
2426 skb = receive_copy(sky2, re, length);
2427 else
2428 skb = receive_new(sky2, re, length);
90c30335
SH		 2429
2430 dev->stats.rx_dropped += (skb == NULL);
2431
793b883e 2432resubmit:
14d0263f 2433 sky2_rx_submit(sky2, re);
79e57d32 2434
cd28ab6a
SH		 2435 return skb;
2436
3b12e014 2437len_error:
71749531
SH		 2438 /* Truncation of overlength packets
2439 causes PHY length to not match MAC length */
7138a0f5 2440 ++dev->stats.rx_length_errors;
d6532232 2441 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2442 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2443 dev->name, status, length);
d6532232 2444 goto resubmit;
71749531 2445
cd28ab6a 2446error:
7138a0f5 2447 ++dev->stats.rx_errors;
b6d77734 2448 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2449 dev->stats.rx_over_errors++;
b6d77734
SH		 2450 goto resubmit;
2451 }
6e15b712 2452
3be92a70 2453 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2454 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2455 dev->name, status, length);
793b883e
SH		 2456
2457 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2458 dev->stats.rx_length_errors++;
cd28ab6a 2459 if (status & GMR_FS_FRAGMENT)
7138a0f5 2460 dev->stats.rx_frame_errors++;
cd28ab6a 2461 if (status & GMR_FS_CRC_ERR)
7138a0f5 2462 dev->stats.rx_crc_errors++;
79e57d32 2463
793b883e 2464 goto resubmit;
cd28ab6a
SH		 2465}
2466
e07b1aa8
SH		 2467/* Transmit complete */
2468static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2469{
e07b1aa8 2470 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2471
49d4b8ba 2472 if (netif_running(dev))
e07b1aa8 2473 sky2_tx_complete(sky2, last);
cd28ab6a
SH		 2474}
2475
37e5a243
SH		 2476static inline void sky2_skb_rx(const struct sky2_port *sky2,
2477 u32 status, struct sk_buff *skb)
2478{
2479#ifdef SKY2_VLAN_TAG_USED
2480 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2481 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2482 if (skb->ip_summed == CHECKSUM_NONE)
2483 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2484 else
2485 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2486 vlan_tag, skb);
2487 return;
2488 }
2489#endif
2490 if (skb->ip_summed == CHECKSUM_NONE)
2491 netif_receive_skb(skb);
2492 else
2493 napi_gro_receive(&sky2->hw->napi, skb);
2494}
2495
bf15fe99
SH		 2496static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2497 unsigned packets, unsigned bytes)
2498{
2499 if (packets) {
2500 struct net_device *dev = hw->dev[port];
2501
2502 dev->stats.rx_packets += packets;
2503 dev->stats.rx_bytes += bytes;
2504 dev->last_rx = jiffies;
2505 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2506 }
2507}
2508
375c5688 2509static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2510{
2511 /* If this happens then driver assuming wrong format for chip type */
2512 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2513
2514 /* Both checksum counters are programmed to start at
2515 * the same offset, so unless there is a problem they
2516 * should match. This failure is an early indication that
2517 * hardware receive checksumming won't work.
2518 */
2519 if (likely((u16)(status >> 16) == (u16)status)) {
2520 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2521 skb->ip_summed = CHECKSUM_COMPLETE;
2522 skb->csum = le16_to_cpu(status);
2523 } else {
2524 dev_notice(&sky2->hw->pdev->dev,
2525 "%s: receive checksum problem (status = %#x)\n",
2526 sky2->netdev->name, status);
2527
2528 /* Disable checksum offload */
2529 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2530 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2531 BMU_DIS_RX_CHKSUM);
2532 }
2533}
2534
e07b1aa8 2535/* Process status response ring */
26691830 2536static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2537{
e07b1aa8 2538 int work_done = 0;
bf15fe99
SH		 2539 unsigned int total_bytes[2] = { 0 };
2540 unsigned int total_packets[2] = { 0 };
a8fd6266 2541
af2a58ac 2542 rmb();
26691830 2543 do {
55c9dd35 2544 struct sky2_port *sky2;
13210ce5 2545 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2546 unsigned port;
13210ce5 2547 struct net_device *dev;
cd28ab6a 2548 struct sk_buff *skb;
cd28ab6a
SH		 2549 u32 status;
2550 u16 length;
ab5adecb
SH		 2551 u8 opcode = le->opcode;
2552
2553 if (!(opcode & HW_OWNER))
2554 break;
cd28ab6a 2555
cb5d9547 2556 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2557
ab5adecb 2558 port = le->css & CSS_LINK_BIT;
69161611 2559 dev = hw->dev[port];
13210ce5 2560 sky2 = netdev_priv(dev);
f65b138c
SH		 2561 length = le16_to_cpu(le->length);
2562 status = le32_to_cpu(le->status);
cd28ab6a 2563
ab5adecb
SH		 2564 le->opcode = 0;
2565 switch (opcode & ~HW_OWNER) {
cd28ab6a 2566 case OP_RXSTAT:
bf15fe99
SH		 2567 total_packets[port]++;
2568 total_bytes[port] += length;
90c30335 2569
497d7c86 2570 skb = sky2_receive(dev, length, status);
90c30335 2571 if (!skb)
55c9dd35 2572 break;
13210ce5 2573
69161611 2574 /* This chip reports checksum status differently */
05745c4a 2575 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2576 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2577 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2578 (le->css & CSS_TCPUDPCSOK))
2579 skb->ip_summed = CHECKSUM_UNNECESSARY;
2580 else
2581 skb->ip_summed = CHECKSUM_NONE;
2582 }
2583
13210ce5 2584 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2585
37e5a243 2586 sky2_skb_rx(sky2, status, skb);
13210ce5 2587
22e11703 2588 /* Stop after net poll weight */
13210ce5
SH		 2589 if (++work_done >= to_do)
2590 goto exit_loop;
cd28ab6a
SH		 2591 break;
2592
d1f13708
SH		 2593#ifdef SKY2_VLAN_TAG_USED
2594 case OP_RXVLAN:
2595 sky2->rx_tag = length;
2596 break;
2597
2598 case OP_RXCHKSVLAN:
2599 sky2->rx_tag = length;
2600 /* fall through */
2601#endif
cd28ab6a 2602 case OP_RXCHKS:
375c5688 2603 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2604 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2605 break;
2606
2607 case OP_TXINDEXLE:
13b97b74 2608 /* TX index reports status for both ports */
f55925d7 2609 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2610 if (hw->dev[1])
2611 sky2_tx_done(hw->dev[1],
2612 ((status >> 24) & 0xff)
2613 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2614 break;
2615
cd28ab6a
SH		 2616 default:
2617 if (net_ratelimit())
793b883e 2618 printk(KERN_WARNING PFX
ab5adecb 2619 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2620 }
26691830 2621 } while (hw->st_idx != idx);
cd28ab6a 2622
fe2a24df
SH		 2623 /* Fully processed status ring so clear irq */
2624 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2625
13210ce5 2626exit_loop:
bf15fe99
SH		 2627 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2628 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2629
e07b1aa8 2630 return work_done;
cd28ab6a
SH		 2631}
2632
2633static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2634{
2635 struct net_device *dev = hw->dev[port];
2636
3be92a70
SH		 2637 if (net_ratelimit())
2638 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2639 dev->name, status);
cd28ab6a
SH		 2640
2641 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2642 if (net_ratelimit())
2643 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2644 dev->name);
cd28ab6a
SH		 2645 /* Clear IRQ */
2646 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2647 }
2648
2649 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2650 if (net_ratelimit())
2651 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2652 dev->name);
cd28ab6a
SH		 2653
2654 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2655 }
2656
2657 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2658 if (net_ratelimit())
2659 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2660 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2661 }
2662
2663 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2664 if (net_ratelimit())
2665 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2666 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2667 }
2668
2669 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2670 if (net_ratelimit())
2671 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2672 dev->name);
cd28ab6a
SH		 2673 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2674 }
2675}
2676
2677static void sky2_hw_intr(struct sky2_hw *hw)
2678{
555382cb 2679 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2680 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2681 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2682
2683 status &= hwmsk;
cd28ab6a 2684
793b883e 2685 if (status & Y2_IS_TIST_OV)
cd28ab6a 2686 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2687
2688 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2689 u16 pci_err;
2690
a40ccc68 2691 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2692 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2693 if (net_ratelimit())
555382cb 2694 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2695 pci_err);
cd28ab6a 2696
b32f40c4 2697 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2698 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2699 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2700 }
2701
2702 if (status & Y2_IS_PCI_EXP) {
d571b694 2703 /* PCI-Express uncorrectable Error occurred */
555382cb 2704 u32 err;
cd28ab6a 2705
a40ccc68 2706 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2707 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2708 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2709 0xfffffffful);
3be92a70 2710 if (net_ratelimit())
555382cb 2711 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2712
7782c8c4 2713 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2714 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2715 }
2716
2717 if (status & Y2_HWE_L1_MASK)
2718 sky2_hw_error(hw, 0, status);
2719 status >>= 8;
2720 if (status & Y2_HWE_L1_MASK)
2721 sky2_hw_error(hw, 1, status);
2722}
2723
2724static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2725{
2726 struct net_device *dev = hw->dev[port];
2727 struct sky2_port *sky2 = netdev_priv(dev);
2728 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2729
2730 if (netif_msg_intr(sky2))
2731 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2732 dev->name, status);
2733
a3caeada
SH		 2734 if (status & GM_IS_RX_CO_OV)
2735 gma_read16(hw, port, GM_RX_IRQ_SRC);
2736
2737 if (status & GM_IS_TX_CO_OV)
2738 gma_read16(hw, port, GM_TX_IRQ_SRC);
2739
cd28ab6a 2740 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2741 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2742 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2743 }
2744
2745 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2746 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2747 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2748 }
cd28ab6a
SH		 2749}
2750
40b01727 2751/* This should never happen it is a bug. */
c119731d 2752static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2753{
2754 struct net_device *dev = hw->dev[port];
c119731d 2755 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2756
c119731d
SH		 2757 dev_err(&hw->pdev->dev, PFX
2758 "%s: descriptor error q=%#x get=%u put=%u\n",
2759 dev->name, (unsigned) q, (unsigned) idx,
2760 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2761
40b01727 2762 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2763}
cd28ab6a 2764
75e80683
SH		 2765static int sky2_rx_hung(struct net_device *dev)
2766{
2767 struct sky2_port *sky2 = netdev_priv(dev);
2768 struct sky2_hw *hw = sky2->hw;
2769 unsigned port = sky2->port;
2770 unsigned rxq = rxqaddr[port];
2771 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2772 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2773 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2774 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2775
2776 /* If idle and MAC or PCI is stuck */
2777 if (sky2->check.last == dev->last_rx &&
2778 ((mac_rp == sky2->check.mac_rp &&
2779 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2780 /* Check if the PCI RX hang */
2781 (fifo_rp == sky2->check.fifo_rp &&
2782 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2783 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2784 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2785 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2786 return 1;
2787 } else {
2788 sky2->check.last = dev->last_rx;
2789 sky2->check.mac_rp = mac_rp;
2790 sky2->check.mac_lev = mac_lev;
2791 sky2->check.fifo_rp = fifo_rp;
2792 sky2->check.fifo_lev = fifo_lev;
2793 return 0;
2794 }
2795}
2796
32c2c300 2797static void sky2_watchdog(unsigned long arg)
d27ed387 2798{
01bd7564 2799 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2800
75e80683 2801 /* Check for lost IRQ once a second */
32c2c300 2802 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2803 napi_schedule(&hw->napi);
75e80683
SH		 2804 } else {
2805 int i, active = 0;
2806
2807 for (i = 0; i < hw->ports; i++) {
bea3348e 2808 struct net_device *dev = hw->dev[i];
75e80683
SH		 2809 if (!netif_running(dev))
2810 continue;
2811 ++active;
2812
2813 /* For chips with Rx FIFO, check if stuck */
39dbd958 2814 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2815 sky2_rx_hung(dev)) {
2816 pr_info(PFX "%s: receiver hang detected\n",
2817 dev->name);
2818 schedule_work(&hw->restart_work);
2819 return;
2820 }
2821 }
2822
2823 if (active == 0)
2824 return;
32c2c300 2825 }
01bd7564 2826
75e80683 2827 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2828}
2829
40b01727
SH		 2830/* Hardware/software error handling */
2831static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2832{
40b01727
SH		 2833 if (net_ratelimit())
2834 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2835
1e5f1283
SH		 2836 if (status & Y2_IS_HW_ERR)
2837 sky2_hw_intr(hw);
d257924e 2838
1e5f1283
SH		 2839 if (status & Y2_IS_IRQ_MAC1)
2840 sky2_mac_intr(hw, 0);
cd28ab6a 2841
1e5f1283
SH		 2842 if (status & Y2_IS_IRQ_MAC2)
2843 sky2_mac_intr(hw, 1);
cd28ab6a 2844
1e5f1283 2845 if (status & Y2_IS_CHK_RX1)
c119731d 2846 sky2_le_error(hw, 0, Q_R1);
d257924e 2847
1e5f1283 2848 if (status & Y2_IS_CHK_RX2)
c119731d 2849 sky2_le_error(hw, 1, Q_R2);
d257924e 2850
1e5f1283 2851 if (status & Y2_IS_CHK_TXA1)
c119731d 2852 sky2_le_error(hw, 0, Q_XA1);
d257924e 2853
1e5f1283 2854 if (status & Y2_IS_CHK_TXA2)
c119731d 2855 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2856}
2857
bea3348e 2858static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2859{
bea3348e 2860 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2861 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2862 int work_done = 0;
26691830 2863 u16 idx;
40b01727
SH		 2864
2865 if (unlikely(status & Y2_IS_ERROR))
2866 sky2_err_intr(hw, status);
2867
2868 if (status & Y2_IS_IRQ_PHY1)
2869 sky2_phy_intr(hw, 0);
2870
2871 if (status & Y2_IS_IRQ_PHY2)
2872 sky2_phy_intr(hw, 1);
cd28ab6a 2873
0f5aac70
SH		 2874 if (status & Y2_IS_PHY_QLNK)
2875 sky2_qlink_intr(hw);
2876
26691830
SH		 2877 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2878 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2879
2880 if (work_done >= work_limit)
26691830
SH		 2881 goto done;
2882 }
6f535763 2883
26691830
SH		 2884 napi_complete(napi);
2885 sky2_read32(hw, B0_Y2_SP_LISR);
2886done:
6f535763 2887
bea3348e 2888 return work_done;
e07b1aa8
SH		 2889}
2890
7d12e780 2891static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2892{
2893 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2894 u32 status;
2895
2896 /* Reading this mask interrupts as side effect */
2897 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2898 if (status == 0 || status == ~0)
2899 return IRQ_NONE;
793b883e 2900
e07b1aa8 2901 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2902
2903 napi_schedule(&hw->napi);
793b883e 2904
cd28ab6a
SH		 2905 return IRQ_HANDLED;
2906}
2907
2908#ifdef CONFIG_NET_POLL_CONTROLLER
2909static void sky2_netpoll(struct net_device *dev)
2910{
2911 struct sky2_port *sky2 = netdev_priv(dev);
2912
bea3348e 2913 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2914}
2915#endif
2916
2917/* Chip internal frequency for clock calculations */
05745c4a 2918static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2919{
793b883e 2920 switch (hw->chip_id) {
cd28ab6a 2921 case CHIP_ID_YUKON_EC:
5a5b1ea0 2922 case CHIP_ID_YUKON_EC_U:
93745494 2923 case CHIP_ID_YUKON_EX:
ed4d4161 2924 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2925 case CHIP_ID_YUKON_UL_2:
0f5aac70 2926 case CHIP_ID_YUKON_OPT:
05745c4a
SH		 2927 return 125;
2928
cd28ab6a 2929 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2930 return 100;
2931
2932 case CHIP_ID_YUKON_FE_P:
2933 return 50;
2934
2935 case CHIP_ID_YUKON_XL:
2936 return 156;
2937
2938 default:
2939 BUG();
cd28ab6a
SH		 2940 }
2941}
2942
fb17358f 2943static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2944{
fb17358f 2945 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2946}
2947
fb17358f 2948static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2949{
fb17358f 2950 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2951}
2952
fb17358f 2953
e3173832 2954static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2955{
b89165f2 2956 u8 t8;
cd28ab6a 2957
167f53d0 2958 /* Enable all clocks and check for bad PCI access */
b32f40c4 2959 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2960
cd28ab6a 2961 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2962
cd28ab6a 2963 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2964 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2965
2966 switch(hw->chip_id) {
2967 case CHIP_ID_YUKON_XL:
39dbd958 2968 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2969 break;
2970
2971 case CHIP_ID_YUKON_EC_U:
2972 hw->flags = SKY2_HW_GIGABIT
2973 | SKY2_HW_NEWER_PHY
2974 | SKY2_HW_ADV_POWER_CTL;
2975 break;
2976
2977 case CHIP_ID_YUKON_EX:
2978 hw->flags = SKY2_HW_GIGABIT
2979 | SKY2_HW_NEWER_PHY
2980 | SKY2_HW_NEW_LE
2981 | SKY2_HW_ADV_POWER_CTL;
2982
2983 /* New transmit checksum */
2984 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2985 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2986 break;
2987
2988 case CHIP_ID_YUKON_EC:
2989 /* This rev is really old, and requires untested workarounds */
2990 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2991 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2992 return -EOPNOTSUPP;
2993 }
39dbd958 2994 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2995 break;
2996
2997 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2998 break;
2999
05745c4a
SH		 3000 case CHIP_ID_YUKON_FE_P:
3001 hw->flags = SKY2_HW_NEWER_PHY
3002 | SKY2_HW_NEW_LE
3003 | SKY2_HW_AUTO_TX_SUM
3004 | SKY2_HW_ADV_POWER_CTL;
3005 break;
ed4d4161
SH		 3006
3007 case CHIP_ID_YUKON_SUPR:
3008 hw->flags = SKY2_HW_GIGABIT
3009 | SKY2_HW_NEWER_PHY
3010 | SKY2_HW_NEW_LE
3011 | SKY2_HW_AUTO_TX_SUM
3012 | SKY2_HW_ADV_POWER_CTL;
3013 break;
3014
0ce8b98d 3015 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 3016 hw->flags = SKY2_HW_GIGABIT
3017 | SKY2_HW_ADV_POWER_CTL;
3018 break;
3019
0f5aac70 3020 case CHIP_ID_YUKON_OPT:
0ce8b98d 3021 hw->flags = SKY2_HW_GIGABIT
b338682d 3022 | SKY2_HW_NEW_LE
0ce8b98d
SH		 3023 | SKY2_HW_ADV_POWER_CTL;
3024 break;
3025
ea76e635 3026 default:
b02a9258
SH		 3027 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3028 hw->chip_id);
cd28ab6a
SH		 3029 return -EOPNOTSUPP;
3030 }
3031
ea76e635
SH		 3032 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3033 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3034 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3035
e3173832
SH		 3036 hw->ports = 1;
3037 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3038 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3039 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3040 ++hw->ports;
3041 }
3042
74a61ebf
MM		 3043 if (sky2_read8(hw, B2_E_0))
3044 hw->flags |= SKY2_HW_RAM_BUFFER;
3045
e3173832
SH		 3046 return 0;
3047}
3048
3049static void sky2_reset(struct sky2_hw *hw)
3050{
555382cb 3051 struct pci_dev *pdev = hw->pdev;
e3173832 3052 u16 status;
555382cb
SH		 3053 int i, cap;
3054 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3055
cd28ab6a 3056 /* disable ASF */
acd12dde 3057 if (hw->chip_id == CHIP_ID_YUKON_EX
3058 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3059 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3060 status = sky2_read16(hw, HCU_CCSR);
3061 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3062 HCU_CCSR_UC_STATE_MSK);
acd12dde 3063 /*
3064 * CPU clock divider shouldn't be used because
3065 * - ASF firmware may malfunction
3066 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3067 */
3068 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3069 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3070 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3071 } else
3072 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3073 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3074
3075 /* do a SW reset */
3076 sky2_write8(hw, B0_CTST, CS_RST_SET);
3077 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3078
ac93a394
SH		 3079 /* allow writes to PCI config */
3080 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3081
cd28ab6a 3082 /* clear PCI errors, if any */
b32f40c4 3083 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3084 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3085 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3086
3087 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3088
555382cb
SH		 3089 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3090 if (cap) {
7782c8c4
SH		 3091 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3092 0xfffffffful);
555382cb
SH		 3093
3094 /* If error bit is stuck on ignore it */
3095 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3096 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3097 else
555382cb
SH		 3098 hwe_mask |= Y2_IS_PCI_EXP;
3099 }
cd28ab6a 3100
ae306cca 3101 sky2_power_on(hw);
a40ccc68 3102 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3103
3104 for (i = 0; i < hw->ports; i++) {
3105 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3106 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3107
ed4d4161
SH		 3108 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3109 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3110 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3111 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3112 | GMC_BYP_RETR_ON);
877c8570
SH		 3113
3114 }
3115
3116 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3117 /* enable MACSec clock gating */
3118 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3119 }
3120
0f5aac70
SH		 3121 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3122 u16 reg;
3123 u32 msk;
3124
3125 if (hw->chip_rev == 0) {
3126 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3127 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3128
3129 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3130 reg = 10;
3131 } else {
3132 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3133 reg = 3;
3134 }
3135
3136 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3137
3138 /* reset PHY Link Detect */
a40ccc68 3139 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3140 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3141 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3142 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3143
3144
3145 /* enable PHY Quick Link */
3146 msk = sky2_read32(hw, B0_IMSK);
3147 msk |= Y2_IS_PHY_QLNK;
3148 sky2_write32(hw, B0_IMSK, msk);
3149
3150 /* check if PSMv2 was running before */
3151 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3152 if (reg & PCI_EXP_LNKCTL_ASPMC) {
8b055431 3153 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
0f5aac70
SH		 3154 /* restore the PCIe Link Control register */
3155 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3156 }
a40ccc68 3157 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3158
3159 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3160 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3161 }
3162
793b883e
SH		 3163 /* Clear I2C IRQ noise */
3164 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3165
3166 /* turn off hardware timer (unused) */
3167 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3168 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3169
69634ee7
SH		 3170 /* Turn off descriptor polling */
3171 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3172
3173 /* Turn off receive timestamp */
3174 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3175 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3176
3177 /* enable the Tx Arbiters */
3178 for (i = 0; i < hw->ports; i++)
3179 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3180
3181 /* Initialize ram interface */
3182 for (i = 0; i < hw->ports; i++) {
793b883e 3183 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3184
3185 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3186 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3187 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3188 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3189 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3190 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3191 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3192 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3193 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3194 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3195 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3196 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3197 }
3198
555382cb 3199 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3200
cd28ab6a 3201 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3202 sky2_gmac_reset(hw, i);
cd28ab6a 3203
cd28ab6a
SH		 3204 memset(hw->st_le, 0, STATUS_LE_BYTES);
3205 hw->st_idx = 0;
3206
3207 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3208 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3209
3210 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3211 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3212
3213 /* Set the list last index */
793b883e 3214 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3215
290d4de5
SH		 3216 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3217 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3218
290d4de5
SH		 3219 /* set Status-FIFO ISR watermark */
3220 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3221 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3222 else
3223 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3224
290d4de5 3225 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3226 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3227 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3228
793b883e 3229 /* enable status unit */
cd28ab6a
SH		 3230 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3231
3232 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3233 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3234 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3235}
3236
af18d8b8
SH		 3237/* Take device down (offline).
3238 * Equivalent to doing dev_stop() but this does not
3239 * inform upper layers of the transistion.
3240 */
3241static void sky2_detach(struct net_device *dev)
3242{
3243 if (netif_running(dev)) {
c36531b9 3244 netif_tx_lock(dev);
af18d8b8 3245 netif_device_detach(dev); /* stop txq */
c36531b9 3246 netif_tx_unlock(dev);
af18d8b8
SH		 3247 sky2_down(dev);
3248 }
3249}
3250
3251/* Bring device back after doing sky2_detach */
3252static int sky2_reattach(struct net_device *dev)
3253{
3254 int err = 0;
3255
3256 if (netif_running(dev)) {
3257 err = sky2_up(dev);
3258 if (err) {
3259 printk(KERN_INFO PFX "%s: could not restart %d\n",
3260 dev->name, err);
3261 dev_close(dev);
3262 } else {
3263 netif_device_attach(dev);
3264 sky2_set_multicast(dev);
3265 }
3266 }
3267
3268 return err;
3269}
3270
81906791
SH		 3271static void sky2_restart(struct work_struct *work)
3272{
3273 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
af18d8b8 3274 int i;
81906791 3275
81906791 3276 rtnl_lock();
af18d8b8
SH		 3277 for (i = 0; i < hw->ports; i++)
3278 sky2_detach(hw->dev[i]);
81906791 3279
8cfcbe99
SH		 3280 napi_disable(&hw->napi);
3281 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3282 sky2_reset(hw);
3283 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3284 napi_enable(&hw->napi);
81906791 3285
af18d8b8
SH		 3286 for (i = 0; i < hw->ports; i++)
3287 sky2_reattach(hw->dev[i]);
81906791 3288
81906791
SH		 3289 rtnl_unlock();
3290}
3291
e3173832
SH		 3292static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3293{
3294 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3295}
3296
3297static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3298{
3299 const struct sky2_port *sky2 = netdev_priv(dev);
3300
3301 wol->supported = sky2_wol_supported(sky2->hw);
3302 wol->wolopts = sky2->wol;
3303}
3304
3305static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3306{
3307 struct sky2_port *sky2 = netdev_priv(dev);
3308 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3309
8e95a202
JP		 3310 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3311 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3312 return -EOPNOTSUPP;
3313
3314 sky2->wol = wol->wolopts;
cd28ab6a
SH		 3315 return 0;
3316}
3317
28bd181a 3318static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3319{
b89165f2
SH		 3320 if (sky2_is_copper(hw)) {
3321 u32 modes = SUPPORTED_10baseT_Half
3322 | SUPPORTED_10baseT_Full
3323 | SUPPORTED_100baseT_Half
3324 | SUPPORTED_100baseT_Full
3325 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3326
ea76e635 3327 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3328 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3329 | SUPPORTED_1000baseT_Full;
3330 return modes;
cd28ab6a 3331 } else
b89165f2
SH		 3332 return SUPPORTED_1000baseT_Half
3333 | SUPPORTED_1000baseT_Full
3334 | SUPPORTED_Autoneg
3335 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3336}
3337
793b883e 3338static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3339{
3340 struct sky2_port *sky2 = netdev_priv(dev);
3341 struct sky2_hw *hw = sky2->hw;
3342
3343 ecmd->transceiver = XCVR_INTERNAL;
3344 ecmd->supported = sky2_supported_modes(hw);
3345 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3346 if (sky2_is_copper(hw)) {
cd28ab6a 3347 ecmd->port = PORT_TP;
b89165f2
SH		 3348 ecmd->speed = sky2->speed;
3349 } else {
3350 ecmd->speed = SPEED_1000;
cd28ab6a 3351 ecmd->port = PORT_FIBRE;
b89165f2 3352 }
cd28ab6a
SH		 3353
3354 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3355 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3356 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3357 ecmd->duplex = sky2->duplex;
3358 return 0;
3359}
3360
3361static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3362{
3363 struct sky2_port *sky2 = netdev_priv(dev);
3364 const struct sky2_hw *hw = sky2->hw;
3365 u32 supported = sky2_supported_modes(hw);
3366
3367 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3368 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3369 ecmd->advertising = supported;
3370 sky2->duplex = -1;
3371 sky2->speed = -1;
3372 } else {
3373 u32 setting;
3374
793b883e 3375 switch (ecmd->speed) {
cd28ab6a
SH		 3376 case SPEED_1000:
3377 if (ecmd->duplex == DUPLEX_FULL)
3378 setting = SUPPORTED_1000baseT_Full;
3379 else if (ecmd->duplex == DUPLEX_HALF)
3380 setting = SUPPORTED_1000baseT_Half;
3381 else
3382 return -EINVAL;
3383 break;
3384 case SPEED_100:
3385 if (ecmd->duplex == DUPLEX_FULL)
3386 setting = SUPPORTED_100baseT_Full;
3387 else if (ecmd->duplex == DUPLEX_HALF)
3388 setting = SUPPORTED_100baseT_Half;
3389 else
3390 return -EINVAL;
3391 break;
3392
3393 case SPEED_10:
3394 if (ecmd->duplex == DUPLEX_FULL)
3395 setting = SUPPORTED_10baseT_Full;
3396 else if (ecmd->duplex == DUPLEX_HALF)
3397 setting = SUPPORTED_10baseT_Half;
3398 else
3399 return -EINVAL;
3400 break;
3401 default:
3402 return -EINVAL;
3403 }
3404
3405 if ((setting & supported) == 0)
3406 return -EINVAL;
3407
3408 sky2->speed = ecmd->speed;
3409 sky2->duplex = ecmd->duplex;
0ea065e5 3410 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3411 }
3412
cd28ab6a
SH		 3413 sky2->advertising = ecmd->advertising;
3414
d1b139c0 3415 if (netif_running(dev)) {
1b537565 3416 sky2_phy_reinit(sky2);
d1b139c0
SH		 3417 sky2_set_multicast(dev);
3418 }
cd28ab6a
SH		 3419
3420 return 0;
3421}
3422
3423static void sky2_get_drvinfo(struct net_device *dev,
3424 struct ethtool_drvinfo *info)
3425{
3426 struct sky2_port *sky2 = netdev_priv(dev);
3427
3428 strcpy(info->driver, DRV_NAME);
3429 strcpy(info->version, DRV_VERSION);
3430 strcpy(info->fw_version, "N/A");
3431 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3432}
3433
3434static const struct sky2_stat {
793b883e
SH		 3435 char name[ETH_GSTRING_LEN];
3436 u16 offset;
cd28ab6a
SH		 3437} sky2_stats[] = {
3438 { "tx_bytes", GM_TXO_OK_HI },
3439 { "rx_bytes", GM_RXO_OK_HI },
3440 { "tx_broadcast", GM_TXF_BC_OK },
3441 { "rx_broadcast", GM_RXF_BC_OK },
3442 { "tx_multicast", GM_TXF_MC_OK },
3443 { "rx_multicast", GM_RXF_MC_OK },
3444 { "tx_unicast", GM_TXF_UC_OK },
3445 { "rx_unicast", GM_RXF_UC_OK },
3446 { "tx_mac_pause", GM_TXF_MPAUSE },
3447 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3448 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3449 { "late_collision",GM_TXF_LAT_COL },
3450 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3451 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3452 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3453
d2604540 3454 { "rx_short", GM_RXF_SHT },
cd28ab6a 3455 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3456 { "rx_64_byte_packets", GM_RXF_64B },
3457 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3458 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3459 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3460 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3461 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3462 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3463 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3464 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3465 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3466 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3467
3468 { "tx_64_byte_packets", GM_TXF_64B },
3469 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3470 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3471 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3472 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3473 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3474 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3475 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3476};
3477
cd28ab6a
SH		 3478static u32 sky2_get_rx_csum(struct net_device *dev)
3479{
3480 struct sky2_port *sky2 = netdev_priv(dev);
3481
0ea065e5 3482 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3483}
3484
3485static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3486{
3487 struct sky2_port *sky2 = netdev_priv(dev);
3488
0ea065e5
SH		 3489 if (data)
3490 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3491 else
3492 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3493
cd28ab6a
SH		 3494 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3495 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3496
3497 return 0;
3498}
3499
3500static u32 sky2_get_msglevel(struct net_device *netdev)
3501{
3502 struct sky2_port *sky2 = netdev_priv(netdev);
3503 return sky2->msg_enable;
3504}
3505
9a7ae0a9
SH		 3506static int sky2_nway_reset(struct net_device *dev)
3507{
3508 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3509
0ea065e5 3510 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3511 return -EINVAL;
3512
1b537565 3513 sky2_phy_reinit(sky2);
d1b139c0 3514 sky2_set_multicast(dev);
9a7ae0a9
SH		 3515
3516 return 0;
3517}
3518
793b883e 3519static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3520{
3521 struct sky2_hw *hw = sky2->hw;
3522 unsigned port = sky2->port;
3523 int i;
3524
3525 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3526 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3527 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3528 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3529
793b883e 3530 for (i = 2; i < count; i++)
cd28ab6a
SH		 3531 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3532}
3533
cd28ab6a
SH		 3534static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3535{
3536 struct sky2_port *sky2 = netdev_priv(netdev);
3537 sky2->msg_enable = value;
3538}
3539
b9f2c044 3540static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3541{
b9f2c044
JG		 3542 switch (sset) {
3543 case ETH_SS_STATS:
3544 return ARRAY_SIZE(sky2_stats);
3545 default:
3546 return -EOPNOTSUPP;
3547 }
cd28ab6a
SH		 3548}
3549
3550static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3551 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3552{
3553 struct sky2_port *sky2 = netdev_priv(dev);
3554
793b883e 3555 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3556}
3557
793b883e 3558static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3559{
3560 int i;
3561
3562 switch (stringset) {
3563 case ETH_SS_STATS:
3564 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3565 memcpy(data + i * ETH_GSTRING_LEN,
3566 sky2_stats[i].name, ETH_GSTRING_LEN);
3567 break;
3568 }
3569}
3570
cd28ab6a
SH		 3571static int sky2_set_mac_address(struct net_device *dev, void *p)
3572{
3573 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3574 struct sky2_hw *hw = sky2->hw;
3575 unsigned port = sky2->port;
3576 const struct sockaddr *addr = p;
cd28ab6a
SH		 3577
3578 if (!is_valid_ether_addr(addr->sa_data))
3579 return -EADDRNOTAVAIL;
3580
cd28ab6a 3581 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3582 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3583 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3584 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3585 dev->dev_addr, ETH_ALEN);
1b537565 3586
a8ab1ec0
SH		 3587 /* virtual address for data */
3588 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3589
3590 /* physical address: used for pause frames */
3591 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3592
3593 return 0;
cd28ab6a
SH		 3594}
3595
a052b52f
SH		 3596static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3597{
3598 u32 bit;
3599
3600 bit = ether_crc(ETH_ALEN, addr) & 63;
3601 filter[bit >> 3] |= 1 << (bit & 7);
3602}
3603
cd28ab6a
SH		 3604static void sky2_set_multicast(struct net_device *dev)
3605{
3606 struct sky2_port *sky2 = netdev_priv(dev);
3607 struct sky2_hw *hw = sky2->hw;
3608 unsigned port = sky2->port;
3609 struct dev_mc_list *list = dev->mc_list;
3610 u16 reg;
3611 u8 filter[8];
a052b52f
SH		 3612 int rx_pause;
3613 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3614
a052b52f 3615 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3616 memset(filter, 0, sizeof(filter));
3617
3618 reg = gma_read16(hw, port, GM_RX_CTRL);
3619 reg |= GM_RXCR_UCF_ENA;
3620
d571b694 3621 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3622 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3623 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3624 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3625 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3626 reg &= ~GM_RXCR_MCF_ENA;
3627 else {
3628 int i;
3629 reg |= GM_RXCR_MCF_ENA;
3630
a052b52f
SH		 3631 if (rx_pause)
3632 sky2_add_filter(filter, pause_mc_addr);
3633
4cd24eaf 3634 for (i = 0; list && i < netdev_mc_count(dev); i++, list = list->next)
a052b52f 3635 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3636 }
3637
cd28ab6a 3638 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3639 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3640 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3641 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3642 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3643 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3644 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3645 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3646
3647 gma_write16(hw, port, GM_RX_CTRL, reg);
3648}
3649
3650/* Can have one global because blinking is controlled by
3651 * ethtool and that is always under RTNL mutex
3652 */
a84d0a3d 3653static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3654{
a84d0a3d
SH		 3655 struct sky2_hw *hw = sky2->hw;
3656 unsigned port = sky2->port;
793b883e 3657
a84d0a3d
SH		 3658 spin_lock_bh(&sky2->phy_lock);
3659 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3660 hw->chip_id == CHIP_ID_YUKON_EX ||
3661 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3662 u16 pg;
793b883e
SH		 3663 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3664 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3665
a84d0a3d
SH		 3666 switch (mode) {
3667 case MO_LED_OFF:
3668 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3669 PHY_M_LEDC_LOS_CTRL(8) |
3670 PHY_M_LEDC_INIT_CTRL(8) |
3671 PHY_M_LEDC_STA1_CTRL(8) |
3672 PHY_M_LEDC_STA0_CTRL(8));
3673 break;
3674 case MO_LED_ON:
3675 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3676 PHY_M_LEDC_LOS_CTRL(9) |
3677 PHY_M_LEDC_INIT_CTRL(9) |
3678 PHY_M_LEDC_STA1_CTRL(9) |
3679 PHY_M_LEDC_STA0_CTRL(9));
3680 break;
3681 case MO_LED_BLINK:
3682 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3683 PHY_M_LEDC_LOS_CTRL(0xa) |
3684 PHY_M_LEDC_INIT_CTRL(0xa) |
3685 PHY_M_LEDC_STA1_CTRL(0xa) |
3686 PHY_M_LEDC_STA0_CTRL(0xa));
3687 break;
3688 case MO_LED_NORM:
3689 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3690 PHY_M_LEDC_LOS_CTRL(1) |
3691 PHY_M_LEDC_INIT_CTRL(8) |
3692 PHY_M_LEDC_STA1_CTRL(7) |
3693 PHY_M_LEDC_STA0_CTRL(7));
3694 }
793b883e 3695
a84d0a3d
SH		 3696 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3697 } else
7d2e3cb7 3698 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3699 PHY_M_LED_MO_DUP(mode) |
3700 PHY_M_LED_MO_10(mode) |
3701 PHY_M_LED_MO_100(mode) |
3702 PHY_M_LED_MO_1000(mode) |
3703 PHY_M_LED_MO_RX(mode) |
3704 PHY_M_LED_MO_TX(mode));
3705
3706 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3707}
3708
3709/* blink LED's for finding board */
3710static int sky2_phys_id(struct net_device *dev, u32 data)
3711{
3712 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3713 unsigned int i;
cd28ab6a 3714
a84d0a3d
SH		 3715 if (data == 0)
3716 data = UINT_MAX;
cd28ab6a 3717
a84d0a3d
SH		 3718 for (i = 0; i < data; i++) {
3719 sky2_led(sky2, MO_LED_ON);
3720 if (msleep_interruptible(500))
3721 break;
3722 sky2_led(sky2, MO_LED_OFF);
3723 if (msleep_interruptible(500))
3724 break;
793b883e 3725 }
a84d0a3d 3726 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3727
3728 return 0;
3729}
3730
3731static void sky2_get_pauseparam(struct net_device *dev,
3732 struct ethtool_pauseparam *ecmd)
3733{
3734 struct sky2_port *sky2 = netdev_priv(dev);
3735
16ad91e1
SH		 3736 switch (sky2->flow_mode) {
3737 case FC_NONE:
3738 ecmd->tx_pause = ecmd->rx_pause = 0;
3739 break;
3740 case FC_TX:
3741 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3742 break;
3743 case FC_RX:
3744 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3745 break;
3746 case FC_BOTH:
3747 ecmd->tx_pause = ecmd->rx_pause = 1;
3748 }
3749
0ea065e5
SH		 3750 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3751 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3752}
3753
3754static int sky2_set_pauseparam(struct net_device *dev,
3755 struct ethtool_pauseparam *ecmd)
3756{
3757 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3758
0ea065e5
SH		 3759 if (ecmd->autoneg == AUTONEG_ENABLE)
3760 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3761 else
3762 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3763
16ad91e1 3764 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3765
16ad91e1
SH		 3766 if (netif_running(dev))
3767 sky2_phy_reinit(sky2);
cd28ab6a 3768
2eaba1a2 3769 return 0;
cd28ab6a
SH		 3770}
3771
fb17358f
SH		 3772static int sky2_get_coalesce(struct net_device *dev,
3773 struct ethtool_coalesce *ecmd)
3774{
3775 struct sky2_port *sky2 = netdev_priv(dev);
3776 struct sky2_hw *hw = sky2->hw;
3777
3778 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3779 ecmd->tx_coalesce_usecs = 0;
3780 else {
3781 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3782 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3783 }
3784 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3785
3786 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3787 ecmd->rx_coalesce_usecs = 0;
3788 else {
3789 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3790 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3791 }
3792 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3793
3794 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3795 ecmd->rx_coalesce_usecs_irq = 0;
3796 else {
3797 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3798 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3799 }
3800
3801 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3802
3803 return 0;
3804}
3805
3806/* Note: this affect both ports */
3807static int sky2_set_coalesce(struct net_device *dev,
3808 struct ethtool_coalesce *ecmd)
3809{
3810 struct sky2_port *sky2 = netdev_priv(dev);
3811 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3812 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3813
77b3d6a2
SH		 3814 if (ecmd->tx_coalesce_usecs > tmax ||
3815 ecmd->rx_coalesce_usecs > tmax ||
3816 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3817 return -EINVAL;
3818
ee5f68fe 3819 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3820 return -EINVAL;
ff81fbbe 3821 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3822 return -EINVAL;
ff81fbbe 3823 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3824 return -EINVAL;
3825
3826 if (ecmd->tx_coalesce_usecs == 0)
3827 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3828 else {
3829 sky2_write32(hw, STAT_TX_TIMER_INI,
3830 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3831 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3832 }
3833 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3834
3835 if (ecmd->rx_coalesce_usecs == 0)
3836 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3837 else {
3838 sky2_write32(hw, STAT_LEV_TIMER_INI,
3839 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3840 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3841 }
3842 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3843
3844 if (ecmd->rx_coalesce_usecs_irq == 0)
3845 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3846 else {
d28d4870 3847 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3848 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3849 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3850 }
3851 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3852 return 0;
3853}
3854
793b883e
SH		 3855static void sky2_get_ringparam(struct net_device *dev,
3856 struct ethtool_ringparam *ering)
3857{
3858 struct sky2_port *sky2 = netdev_priv(dev);
3859
3860 ering->rx_max_pending = RX_MAX_PENDING;
3861 ering->rx_mini_max_pending = 0;
3862 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3863 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3864
3865 ering->rx_pending = sky2->rx_pending;
3866 ering->rx_mini_pending = 0;
3867 ering->rx_jumbo_pending = 0;
3868 ering->tx_pending = sky2->tx_pending;
3869}
3870
3871static int sky2_set_ringparam(struct net_device *dev,
3872 struct ethtool_ringparam *ering)
3873{
3874 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3875
3876 if (ering->rx_pending > RX_MAX_PENDING ||
3877 ering->rx_pending < 8 ||
ee5f68fe
SH		 3878 ering->tx_pending < TX_MIN_PENDING ||
3879 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3880 return -EINVAL;
3881
af18d8b8 3882 sky2_detach(dev);
793b883e
SH		 3883
3884 sky2->rx_pending = ering->rx_pending;
3885 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3886 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3887
af18d8b8 3888 return sky2_reattach(dev);
793b883e
SH		 3889}
3890
793b883e
SH		 3891static int sky2_get_regs_len(struct net_device *dev)
3892{
6e4cbb34 3893 return 0x4000;
793b883e
SH		 3894}
3895
c32bbff8
MM		 3896static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3897{
3898 /* This complicated switch statement is to make sure and
3899 * only access regions that are unreserved.
3900 * Some blocks are only valid on dual port cards.
3901 */
3902 switch (b) {
3903 /* second port */
3904 case 5: /* Tx Arbiter 2 */
3905 case 9: /* RX2 */
3906 case 14 ... 15: /* TX2 */
3907 case 17: case 19: /* Ram Buffer 2 */
3908 case 22 ... 23: /* Tx Ram Buffer 2 */
3909 case 25: /* Rx MAC Fifo 1 */
3910 case 27: /* Tx MAC Fifo 2 */
3911 case 31: /* GPHY 2 */
3912 case 40 ... 47: /* Pattern Ram 2 */
3913 case 52: case 54: /* TCP Segmentation 2 */
3914 case 112 ... 116: /* GMAC 2 */
3915 return hw->ports > 1;
3916
3917 case 0: /* Control */
3918 case 2: /* Mac address */
3919 case 4: /* Tx Arbiter 1 */
3920 case 7: /* PCI express reg */
3921 case 8: /* RX1 */
3922 case 12 ... 13: /* TX1 */
3923 case 16: case 18:/* Rx Ram Buffer 1 */
3924 case 20 ... 21: /* Tx Ram Buffer 1 */
3925 case 24: /* Rx MAC Fifo 1 */
3926 case 26: /* Tx MAC Fifo 1 */
3927 case 28 ... 29: /* Descriptor and status unit */
3928 case 30: /* GPHY 1*/
3929 case 32 ... 39: /* Pattern Ram 1 */
3930 case 48: case 50: /* TCP Segmentation 1 */
3931 case 56 ... 60: /* PCI space */
3932 case 80 ... 84: /* GMAC 1 */
3933 return 1;
3934
3935 default:
3936 return 0;
3937 }
3938}
3939
793b883e
SH		 3940/*
3941 * Returns copy of control register region
3ead5db7 3942 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3943 */
3944static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3945 void *p)
3946{
3947 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3948 const void __iomem *io = sky2->hw->regs;
295b54c4 3949 unsigned int b;
793b883e
SH		 3950
3951 regs->version = 1;
793b883e 3952
295b54c4 3953 for (b = 0; b < 128; b++) {
c32bbff8
MM		 3954 /* skip poisonous diagnostic ram region in block 3 */
3955 if (b == 3)
295b54c4 3956 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 3957 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 3958 memcpy_fromio(p, io, 128);
c32bbff8 3959 else
295b54c4 3960 memset(p, 0, 128);
3ead5db7 3961
295b54c4
SH		 3962 p += 128;
3963 io += 128;
3964 }
793b883e 3965}
cd28ab6a 3966
b628ed98
SH		 3967/* In order to do Jumbo packets on these chips, need to turn off the
3968 * transmit store/forward. Therefore checksum offload won't work.
3969 */
3970static int no_tx_offload(struct net_device *dev)
3971{
3972 const struct sky2_port *sky2 = netdev_priv(dev);
3973 const struct sky2_hw *hw = sky2->hw;
3974
69161611 3975 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3976}
3977
3978static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3979{
3980 if (data && no_tx_offload(dev))
3981 return -EINVAL;
3982
3983 return ethtool_op_set_tx_csum(dev, data);
3984}
3985
3986
3987static int sky2_set_tso(struct net_device *dev, u32 data)
3988{
3989 if (data && no_tx_offload(dev))
3990 return -EINVAL;
3991
3992 return ethtool_op_set_tso(dev, data);
3993}
3994
f4331a6d
SH		 3995static int sky2_get_eeprom_len(struct net_device *dev)
3996{
3997 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3998 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3999 u16 reg2;
4000
b32f40c4 4001 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 4002 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4003}
4004
1413235c 4005static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 4006{
1413235c 4007 unsigned long start = jiffies;
f4331a6d 4008
1413235c
SH		 4009 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4010 /* Can take up to 10.6 ms for write */
4011 if (time_after(jiffies, start + HZ/4)) {
4012 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
4013 return -ETIMEDOUT;
4014 }
4015 mdelay(1);
4016 }
167f53d0 4017
1413235c
SH		 4018 return 0;
4019}
167f53d0 4020
1413235c
SH		 4021static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4022 u16 offset, size_t length)
4023{
4024 int rc = 0;
4025
4026 while (length > 0) {
4027 u32 val;
4028
4029 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4030 rc = sky2_vpd_wait(hw, cap, 0);
4031 if (rc)
4032 break;
4033
4034 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4035
4036 memcpy(data, &val, min(sizeof(val), length));
4037 offset += sizeof(u32);
4038 data += sizeof(u32);
4039 length -= sizeof(u32);
4040 }
4041
4042 return rc;
f4331a6d
SH		 4043}
4044
1413235c
SH		 4045static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4046 u16 offset, unsigned int length)
f4331a6d 4047{
1413235c
SH		 4048 unsigned int i;
4049 int rc = 0;
4050
4051 for (i = 0; i < length; i += sizeof(u32)) {
4052 u32 val = *(u32 *)(data + i);
4053
4054 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4055 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4056
4057 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4058 if (rc)
4059 break;
4060 }
4061 return rc;
f4331a6d
SH		 4062}
4063
4064static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4065 u8 *data)
4066{
4067 struct sky2_port *sky2 = netdev_priv(dev);
4068 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4069
4070 if (!cap)
4071 return -EINVAL;
4072
4073 eeprom->magic = SKY2_EEPROM_MAGIC;
4074
1413235c 4075 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4076}
4077
4078static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4079 u8 *data)
4080{
4081 struct sky2_port *sky2 = netdev_priv(dev);
4082 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4083
4084 if (!cap)
4085 return -EINVAL;
4086
4087 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4088 return -EINVAL;
4089
1413235c
SH		 4090 /* Partial writes not supported */
4091 if ((eeprom->offset & 3) || (eeprom->len & 3))
4092 return -EINVAL;
f4331a6d 4093
1413235c 4094 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4095}
4096
4097
7282d491 4098static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4099 .get_settings = sky2_get_settings,
4100 .set_settings = sky2_set_settings,
4101 .get_drvinfo = sky2_get_drvinfo,
4102 .get_wol = sky2_get_wol,
4103 .set_wol = sky2_set_wol,
4104 .get_msglevel = sky2_get_msglevel,
4105 .set_msglevel = sky2_set_msglevel,
4106 .nway_reset = sky2_nway_reset,
4107 .get_regs_len = sky2_get_regs_len,
4108 .get_regs = sky2_get_regs,
4109 .get_link = ethtool_op_get_link,
4110 .get_eeprom_len = sky2_get_eeprom_len,
4111 .get_eeprom = sky2_get_eeprom,
4112 .set_eeprom = sky2_set_eeprom,
f4331a6d 4113 .set_sg = ethtool_op_set_sg,
f4331a6d 4114 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 4115 .set_tso = sky2_set_tso,
4116 .get_rx_csum = sky2_get_rx_csum,
4117 .set_rx_csum = sky2_set_rx_csum,
4118 .get_strings = sky2_get_strings,
4119 .get_coalesce = sky2_get_coalesce,
4120 .set_coalesce = sky2_set_coalesce,
4121 .get_ringparam = sky2_get_ringparam,
4122 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4123 .get_pauseparam = sky2_get_pauseparam,
4124 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 4125 .phys_id = sky2_phys_id,
b9f2c044 4126 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 4127 .get_ethtool_stats = sky2_get_ethtool_stats,
4128};
4129
3cf26753
SH		 4130#ifdef CONFIG_SKY2_DEBUG
4131
4132static struct dentry *sky2_debug;
4133
e4c2abe2
SH		 4134
4135/*
4136 * Read and parse the first part of Vital Product Data
4137 */
4138#define VPD_SIZE 128
4139#define VPD_MAGIC 0x82
4140
4141static const struct vpd_tag {
4142 char tag[2];
4143 char *label;
4144} vpd_tags[] = {
4145 { "PN", "Part Number" },
4146 { "EC", "Engineering Level" },
4147 { "MN", "Manufacturer" },
4148 { "SN", "Serial Number" },
4149 { "YA", "Asset Tag" },
4150 { "VL", "First Error Log Message" },
4151 { "VF", "Second Error Log Message" },
4152 { "VB", "Boot Agent ROM Configuration" },
4153 { "VE", "EFI UNDI Configuration" },
4154};
4155
4156static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4157{
4158 size_t vpd_size;
4159 loff_t offs;
4160 u8 len;
4161 unsigned char *buf;
4162 u16 reg2;
4163
4164 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4165 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4166
4167 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4168 buf = kmalloc(vpd_size, GFP_KERNEL);
4169 if (!buf) {
4170 seq_puts(seq, "no memory!\n");
4171 return;
4172 }
4173
4174 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4175 seq_puts(seq, "VPD read failed\n");
4176 goto out;
4177 }
4178
4179 if (buf[0] != VPD_MAGIC) {
4180 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4181 goto out;
4182 }
4183 len = buf[1];
4184 if (len == 0 || len > vpd_size - 4) {
4185 seq_printf(seq, "Invalid id length: %d\n", len);
4186 goto out;
4187 }
4188
4189 seq_printf(seq, "%.*s\n", len, buf + 3);
4190 offs = len + 3;
4191
4192 while (offs < vpd_size - 4) {
4193 int i;
4194
4195 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4196 break;
4197 len = buf[offs + 2];
4198 if (offs + len + 3 >= vpd_size)
4199 break;
4200
4201 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4202 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4203 seq_printf(seq, " %s: %.*s\n",
4204 vpd_tags[i].label, len, buf + offs + 3);
4205 break;
4206 }
4207 }
4208 offs += len + 3;
4209 }
4210out:
4211 kfree(buf);
4212}
4213
3cf26753
SH		 4214static int sky2_debug_show(struct seq_file *seq, void *v)
4215{
4216 struct net_device *dev = seq->private;
4217 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4218 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4219 unsigned port = sky2->port;
4220 unsigned idx, last;
4221 int sop;
4222
e4c2abe2 4223 sky2_show_vpd(seq, hw);
3cf26753 4224
e4c2abe2 4225 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4226 sky2_read32(hw, B0_ISRC),
4227 sky2_read32(hw, B0_IMSK),
4228 sky2_read32(hw, B0_Y2_SP_ICR));
4229
e4c2abe2
SH		 4230 if (!netif_running(dev)) {
4231 seq_printf(seq, "network not running\n");
4232 return 0;
4233 }
4234
bea3348e 4235 napi_disable(&hw->napi);
3cf26753
SH		 4236 last = sky2_read16(hw, STAT_PUT_IDX);
4237
4238 if (hw->st_idx == last)
4239 seq_puts(seq, "Status ring (empty)\n");
4240 else {
4241 seq_puts(seq, "Status ring\n");
4242 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4243 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4244 const struct sky2_status_le *le = hw->st_le + idx;
4245 seq_printf(seq, "[%d] %#x %d %#x\n",
4246 idx, le->opcode, le->length, le->status);
4247 }
4248 seq_puts(seq, "\n");
4249 }
4250
4251 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4252 sky2->tx_cons, sky2->tx_prod,
4253 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4254 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4255
4256 /* Dump contents of tx ring */
4257 sop = 1;
ee5f68fe
SH		 4258 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4259 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4260 const struct sky2_tx_le *le = sky2->tx_le + idx;
4261 u32 a = le32_to_cpu(le->addr);
4262
4263 if (sop)
4264 seq_printf(seq, "%u:", idx);
4265 sop = 0;
4266
4267 switch(le->opcode & ~HW_OWNER) {
4268 case OP_ADDR64:
4269 seq_printf(seq, " %#x:", a);
4270 break;
4271 case OP_LRGLEN:
4272 seq_printf(seq, " mtu=%d", a);
4273 break;
4274 case OP_VLAN:
4275 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4276 break;
4277 case OP_TCPLISW:
4278 seq_printf(seq, " csum=%#x", a);
4279 break;
4280 case OP_LARGESEND:
4281 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4282 break;
4283 case OP_PACKET:
4284 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4285 break;
4286 case OP_BUFFER:
4287 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4288 break;
4289 default:
4290 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4291 a, le16_to_cpu(le->length));
4292 }
4293
4294 if (le->ctrl & EOP) {
4295 seq_putc(seq, '\n');
4296 sop = 1;
4297 }
4298 }
4299
4300 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4301 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4302 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4303 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4304
d1d08d12 4305 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4306 napi_enable(&hw->napi);
3cf26753
SH		 4307 return 0;
4308}
4309
4310static int sky2_debug_open(struct inode *inode, struct file *file)
4311{
4312 return single_open(file, sky2_debug_show, inode->i_private);
4313}
4314
4315static const struct file_operations sky2_debug_fops = {
4316 .owner = THIS_MODULE,
4317 .open = sky2_debug_open,
4318 .read = seq_read,
4319 .llseek = seq_lseek,
4320 .release = single_release,
4321};
4322
4323/*
4324 * Use network device events to create/remove/rename
4325 * debugfs file entries
4326 */
4327static int sky2_device_event(struct notifier_block *unused,
4328 unsigned long event, void *ptr)
4329{
4330 struct net_device *dev = ptr;
5b296bc9 4331 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4332
1436b301 4333 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4334 return NOTIFY_DONE;
3cf26753 4335
5b296bc9
SH		 4336 switch(event) {
4337 case NETDEV_CHANGENAME:
4338 if (sky2->debugfs) {
4339 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4340 sky2_debug, dev->name);
4341 }
4342 break;
3cf26753 4343
5b296bc9
SH		 4344 case NETDEV_GOING_DOWN:
4345 if (sky2->debugfs) {
4346 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4347 dev->name);
4348 debugfs_remove(sky2->debugfs);
4349 sky2->debugfs = NULL;
3cf26753 4350 }
5b296bc9
SH		 4351 break;
4352
4353 case NETDEV_UP:
4354 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4355 sky2_debug, dev,
4356 &sky2_debug_fops);
4357 if (IS_ERR(sky2->debugfs))
4358 sky2->debugfs = NULL;
3cf26753
SH		 4359 }
4360
4361 return NOTIFY_DONE;
4362}
4363
4364static struct notifier_block sky2_notifier = {
4365 .notifier_call = sky2_device_event,
4366};
4367
4368
4369static __init void sky2_debug_init(void)
4370{
4371 struct dentry *ent;
4372
4373 ent = debugfs_create_dir("sky2", NULL);
4374 if (!ent || IS_ERR(ent))
4375 return;
4376
4377 sky2_debug = ent;
4378 register_netdevice_notifier(&sky2_notifier);
4379}
4380
4381static __exit void sky2_debug_cleanup(void)
4382{
4383 if (sky2_debug) {
4384 unregister_netdevice_notifier(&sky2_notifier);
4385 debugfs_remove(sky2_debug);
4386 sky2_debug = NULL;
4387 }
4388}
4389
4390#else
4391#define sky2_debug_init()
4392#define sky2_debug_cleanup()
4393#endif
4394
1436b301
SH		 4395/* Two copies of network device operations to handle special case of
4396 not allowing netpoll on second port */
4397static const struct net_device_ops sky2_netdev_ops[2] = {
4398 {
4399 .ndo_open = sky2_up,
4400 .ndo_stop = sky2_down,
00829823 4401 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4402 .ndo_do_ioctl = sky2_ioctl,
4403 .ndo_validate_addr = eth_validate_addr,
4404 .ndo_set_mac_address = sky2_set_mac_address,
4405 .ndo_set_multicast_list = sky2_set_multicast,
4406 .ndo_change_mtu = sky2_change_mtu,
4407 .ndo_tx_timeout = sky2_tx_timeout,
4408#ifdef SKY2_VLAN_TAG_USED
4409 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4410#endif
4411#ifdef CONFIG_NET_POLL_CONTROLLER
4412 .ndo_poll_controller = sky2_netpoll,
4413#endif
4414 },
4415 {
4416 .ndo_open = sky2_up,
4417 .ndo_stop = sky2_down,
00829823 4418 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4419 .ndo_do_ioctl = sky2_ioctl,
4420 .ndo_validate_addr = eth_validate_addr,
4421 .ndo_set_mac_address = sky2_set_mac_address,
4422 .ndo_set_multicast_list = sky2_set_multicast,
4423 .ndo_change_mtu = sky2_change_mtu,
4424 .ndo_tx_timeout = sky2_tx_timeout,
4425#ifdef SKY2_VLAN_TAG_USED
4426 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4427#endif
4428 },
4429};
3cf26753 4430
cd28ab6a
SH		 4431/* Initialize network device */
4432static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4433 unsigned port,
be63a21c 4434 int highmem, int wol)
cd28ab6a
SH		 4435{
4436 struct sky2_port *sky2;
4437 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4438
4439 if (!dev) {
898eb71c 4440 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4441 return NULL;
4442 }
4443
cd28ab6a 4444 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4445 dev->irq = hw->pdev->irq;
cd28ab6a 4446 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4447 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4448 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4449
4450 sky2 = netdev_priv(dev);
4451 sky2->netdev = dev;
4452 sky2->hw = hw;
4453 sky2->msg_enable = netif_msg_init(debug, default_msg);
4454
cd28ab6a 4455 /* Auto speed and flow control */
0ea065e5
SH		 4456 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4457 if (hw->chip_id != CHIP_ID_YUKON_XL)
4458 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4459
16ad91e1
SH		 4460 sky2->flow_mode = FC_BOTH;
4461
cd28ab6a
SH		 4462 sky2->duplex = -1;
4463 sky2->speed = -1;
4464 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4465 sky2->wol = wol;
75d070c5 4466
e07b1aa8 4467 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4468
793b883e 4469 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4470 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4471 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4472
4473 hw->dev[port] = dev;
4474
4475 sky2->port = port;
4476
4a50a876 4477 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4478 if (highmem)
4479 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4480
d1f13708 4481#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4482 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4483 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4484 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4485 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4486 }
d1f13708
SH		 4487#endif
4488
cd28ab6a 4489 /* read the mac address */
793b883e 4490 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4491 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4492
cd28ab6a
SH		 4493 return dev;
4494}
4495
28bd181a 4496static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4497{
4498 const struct sky2_port *sky2 = netdev_priv(dev);
4499
4500 if (netif_msg_probe(sky2))
e174961c
JB		 4501 printk(KERN_INFO PFX "%s: addr %pM\n",
4502 dev->name, dev->dev_addr);
cd28ab6a
SH		 4503}
4504
fb2690a9 4505/* Handle software interrupt used during MSI test */
7d12e780 4506static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4507{
4508 struct sky2_hw *hw = dev_id;
4509 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4510
4511 if (status == 0)
4512 return IRQ_NONE;
4513
4514 if (status & Y2_IS_IRQ_SW) {
ea76e635 4515 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4516 wake_up(&hw->msi_wait);
4517 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4518 }
4519 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4520
4521 return IRQ_HANDLED;
4522}
4523
4524/* Test interrupt path by forcing a a software IRQ */
4525static int __devinit sky2_test_msi(struct sky2_hw *hw)
4526{
4527 struct pci_dev *pdev = hw->pdev;
4528 int err;
4529
bb507fe1
SH		 4530 init_waitqueue_head (&hw->msi_wait);
4531
fb2690a9
SH		 4532 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4533
b0a20ded 4534 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4535 if (err) {
b02a9258 4536 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4537 return err;
4538 }
4539
fb2690a9 4540 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4541 sky2_read8(hw, B0_CTST);
fb2690a9 4542
ea76e635 4543 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4544
ea76e635 4545 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4546 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4547 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4548 "switching to INTx mode.\n");
fb2690a9
SH		 4549
4550 err = -EOPNOTSUPP;
4551 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4552 }
4553
4554 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4555 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4556
4557 free_irq(pdev->irq, hw);
4558
4559 return err;
4560}
4561
c7127a34
SH		 4562/* This driver supports yukon2 chipset only */
4563static const char *sky2_name(u8 chipid, char *buf, int sz)
4564{
4565 const char *name[] = {
4566 "XL", /* 0xb3 */
4567 "EC Ultra", /* 0xb4 */
4568 "Extreme", /* 0xb5 */
4569 "EC", /* 0xb6 */
4570 "FE", /* 0xb7 */
4571 "FE+", /* 0xb8 */
4572 "Supreme", /* 0xb9 */
0ce8b98d 4573 "UL 2", /* 0xba */
0f5aac70
SH		 4574 "Unknown", /* 0xbb */
4575 "Optima", /* 0xbc */
c7127a34
SH		 4576 };
4577
dae3a511 4578 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
c7127a34
SH		 4579 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4580 else
4581 snprintf(buf, sz, "(chip %#x)", chipid);
4582 return buf;
4583}
4584
cd28ab6a
SH		 4585static int __devinit sky2_probe(struct pci_dev *pdev,
4586 const struct pci_device_id *ent)
4587{
7f60c64b 4588 struct net_device *dev;
cd28ab6a 4589 struct sky2_hw *hw;
be63a21c 4590 int err, using_dac = 0, wol_default;
3834507d 4591 u32 reg;
c7127a34 4592 char buf1[16];
cd28ab6a 4593
793b883e
SH		 4594 err = pci_enable_device(pdev);
4595 if (err) {
b02a9258 4596 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4597 goto err_out;
4598 }
4599
6cc90a5a
SH		 4600 /* Get configuration information
4601 * Note: only regular PCI config access once to test for HW issues
4602 * other PCI access through shared memory for speed and to
4603 * avoid MMCONFIG problems.
4604 */
4605 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4606 if (err) {
4607 dev_err(&pdev->dev, "PCI read config failed\n");
4608 goto err_out;
4609 }
4610
4611 if (~reg == 0) {
4612 dev_err(&pdev->dev, "PCI configuration read error\n");
4613 goto err_out;
4614 }
4615
793b883e
SH		 4616 err = pci_request_regions(pdev, DRV_NAME);
4617 if (err) {
b02a9258 4618 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4619 goto err_out_disable;
cd28ab6a
SH		 4620 }
4621
4622 pci_set_master(pdev);
4623
d1f3d4dd 4624 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4625 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4626 using_dac = 1;
6a35528a 4627 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4628 if (err < 0) {
b02a9258
SH		 4629 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4630 "for consistent allocations\n");
d1f3d4dd
SH		 4631 goto err_out_free_regions;
4632 }
d1f3d4dd 4633 } else {
284901a9 4634 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4635 if (err) {
b02a9258 4636 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4637 goto err_out_free_regions;
4638 }
4639 }
d1f3d4dd 4640
3834507d
SH		 4641
4642#ifdef __BIG_ENDIAN
4643 /* The sk98lin vendor driver uses hardware byte swapping but
4644 * this driver uses software swapping.
4645 */
4646 reg &= ~PCI_REV_DESC;
4647 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4648 if (err) {
4649 dev_err(&pdev->dev, "PCI write config failed\n");
4650 goto err_out_free_regions;
4651 }
4652#endif
4653
9d731d77 4654 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4655
cd28ab6a 4656 err = -ENOMEM;
66466797
SH		 4657
4658 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4659 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4660 if (!hw) {
b02a9258 4661 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4662 goto err_out_free_regions;
4663 }
4664
cd28ab6a 4665 hw->pdev = pdev;
66466797 4666 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4667
4668 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4669 if (!hw->regs) {
b02a9258 4670 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4671 goto err_out_free_hw;
4672 }
4673
08c06d8a 4674 /* ring for status responses */
167f53d0 4675 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4676 if (!hw->st_le)
4677 goto err_out_iounmap;
4678
e3173832 4679 err = sky2_init(hw);
cd28ab6a 4680 if (err)
793b883e 4681 goto err_out_iounmap;
cd28ab6a 4682
c844d483
SH		 4683 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4684 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4685
e3173832
SH		 4686 sky2_reset(hw);
4687
be63a21c 4688 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4689 if (!dev) {
4690 err = -ENOMEM;
cd28ab6a 4691 goto err_out_free_pci;
7f60c64b 4692 }
cd28ab6a 4693
9fa1b1f3
SH		 4694 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4695 err = sky2_test_msi(hw);
4696 if (err == -EOPNOTSUPP)
4697 pci_disable_msi(pdev);
4698 else if (err)
4699 goto err_out_free_netdev;
4700 }
4701
793b883e
SH		 4702 err = register_netdev(dev);
4703 if (err) {
b02a9258 4704 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4705 goto err_out_free_netdev;
4706 }
4707
33cb7d33
BP		 4708 netif_carrier_off(dev);
4709
6de16237
SH		 4710 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4711
ea76e635
SH		 4712 err = request_irq(pdev->irq, sky2_intr,
4713 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4714 hw->irq_name, hw);
9fa1b1f3 4715 if (err) {
b02a9258 4716 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4717 goto err_out_unregister;
4718 }
4719 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4720 napi_enable(&hw->napi);
9fa1b1f3 4721
cd28ab6a
SH		 4722 sky2_show_addr(dev);
4723
7f60c64b 4724 if (hw->ports > 1) {
4725 struct net_device *dev1;
4726
ca519274 4727 err = -ENOMEM;
be63a21c 4728 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4729 if (dev1 && (err = register_netdev(dev1)) == 0)
4730 sky2_show_addr(dev1);
4731 else {
b02a9258
SH		 4732 dev_warn(&pdev->dev,
4733 "register of second port failed (%d)\n", err);
cd28ab6a 4734 hw->dev[1] = NULL;
ca519274
SH		 4735 hw->ports = 1;
4736 if (dev1)
4737 free_netdev(dev1);
4738 }
cd28ab6a
SH		 4739 }
4740
32c2c300 4741 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4742 INIT_WORK(&hw->restart_work, sky2_restart);
4743
793b883e 4744 pci_set_drvdata(pdev, hw);
1ae861e6 4745 pdev->d3_delay = 150;
793b883e 4746
cd28ab6a
SH		 4747 return 0;
4748
793b883e 4749err_out_unregister:
ea76e635 4750 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4751 pci_disable_msi(pdev);
793b883e 4752 unregister_netdev(dev);
cd28ab6a
SH		 4753err_out_free_netdev:
4754 free_netdev(dev);
cd28ab6a 4755err_out_free_pci:
793b883e 4756 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4757 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4758err_out_iounmap:
4759 iounmap(hw->regs);
4760err_out_free_hw:
4761 kfree(hw);
4762err_out_free_regions:
4763 pci_release_regions(pdev);
44a1d2e5 4764err_out_disable:
cd28ab6a 4765 pci_disable_device(pdev);
cd28ab6a 4766err_out:
549a68c3 4767 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4768 return err;
4769}
4770
4771static void __devexit sky2_remove(struct pci_dev *pdev)
4772{
793b883e 4773 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4774 int i;
cd28ab6a 4775
793b883e 4776 if (!hw)
cd28ab6a
SH		 4777 return;
4778
32c2c300 4779 del_timer_sync(&hw->watchdog_timer);
6de16237 4780 cancel_work_sync(&hw->restart_work);
d27ed387 4781
b877fe28 4782 for (i = hw->ports-1; i >= 0; --i)
6de16237 4783 unregister_netdev(hw->dev[i]);
81906791 4784
d27ed387 4785 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4786
ae306cca
SH		 4787 sky2_power_aux(hw);
4788
793b883e 4789 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4790 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4791
4792 free_irq(pdev->irq, hw);
ea76e635 4793 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4794 pci_disable_msi(pdev);
793b883e 4795 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4796 pci_release_regions(pdev);
4797 pci_disable_device(pdev);
793b883e 4798
b877fe28 4799 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4800 free_netdev(hw->dev[i]);
4801
cd28ab6a
SH		 4802 iounmap(hw->regs);
4803 kfree(hw);
5afa0a9c 4804
cd28ab6a
SH		 4805 pci_set_drvdata(pdev, NULL);
4806}
4807
cd28ab6a
SH		 4808static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4809{
793b883e 4810 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4811 int i, wol = 0;
cd28ab6a 4812
549a68c3
SH		 4813 if (!hw)
4814 return 0;
4815
063a0b38
SH		 4816 del_timer_sync(&hw->watchdog_timer);
4817 cancel_work_sync(&hw->restart_work);
4818
19720737 4819 rtnl_lock();
f05267e7 4820 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4821 struct net_device *dev = hw->dev[i];
e3173832 4822 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4823
af18d8b8 4824 sky2_detach(dev);
e3173832
SH		 4825
4826 if (sky2->wol)
4827 sky2_wol_init(sky2);
4828
4829 wol |= sky2->wol;
cd28ab6a
SH		 4830 }
4831
5f8ae5c5 4832 device_set_wakeup_enable(&pdev->dev, wol != 0);
4833
8ab8fca2 4834 sky2_write32(hw, B0_IMSK, 0);
6de16237 4835 napi_disable(&hw->napi);
ae306cca 4836 sky2_power_aux(hw);
19720737 4837 rtnl_unlock();
e3173832 4838
d374c1c1 4839 pci_save_state(pdev);
e3173832 4840 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4841 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4842
2ccc99b7 4843 return 0;
cd28ab6a
SH		 4844}
4845
5f8ae5c5 4846#ifdef CONFIG_PM
cd28ab6a
SH		 4847static int sky2_resume(struct pci_dev *pdev)
4848{
793b883e 4849 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4850 int i, err;
cd28ab6a 4851
549a68c3
SH		 4852 if (!hw)
4853 return 0;
4854
f71eb1a2
SH		 4855 err = pci_set_power_state(pdev, PCI_D0);
4856 if (err)
4857 goto out;
ae306cca
SH		 4858
4859 err = pci_restore_state(pdev);
4860 if (err)
4861 goto out;
4862
cd28ab6a 4863 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4864
4865 /* Re-enable all clocks */
a0db28b8 4866 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4867 if (err) {
4868 dev_err(&pdev->dev, "PCI write config failed\n");
4869 goto out;
4870 }
1ad5b4a5 4871
e3173832 4872 sky2_reset(hw);
8ab8fca2 4873 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4874 napi_enable(&hw->napi);
8ab8fca2 4875
af18d8b8 4876 rtnl_lock();
f05267e7 4877 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4878 err = sky2_reattach(hw->dev[i]);
4879 if (err)
4880 goto out;
cd28ab6a 4881 }
af18d8b8 4882 rtnl_unlock();
eb35cf60 4883
ae306cca 4884 return 0;
08c06d8a 4885out:
af18d8b8
SH		 4886 rtnl_unlock();
4887
b02a9258 4888 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4889 pci_disable_device(pdev);
08c06d8a 4890 return err;
cd28ab6a
SH		 4891}
4892#endif
4893
e3173832
SH		 4894static void sky2_shutdown(struct pci_dev *pdev)
4895{
5f8ae5c5 4896 sky2_suspend(pdev, PMSG_SUSPEND);
e3173832
SH		 4897}
4898
cd28ab6a 4899static struct pci_driver sky2_driver = {
793b883e
SH		 4900 .name = DRV_NAME,
4901 .id_table = sky2_id_table,
4902 .probe = sky2_probe,
4903 .remove = __devexit_p(sky2_remove),
cd28ab6a 4904#ifdef CONFIG_PM
793b883e
SH		 4905 .suspend = sky2_suspend,
4906 .resume = sky2_resume,
cd28ab6a 4907#endif
e3173832 4908 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4909};
4910
4911static int __init sky2_init_module(void)
4912{
c844d483
SH		 4913 pr_info(PFX "driver version " DRV_VERSION "\n");
4914
3cf26753 4915 sky2_debug_init();
50241c4c 4916 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4917}
4918
4919static void __exit sky2_cleanup_module(void)
4920{
4921 pci_unregister_driver(&sky2_driver);
3cf26753 4922 sky2_debug_cleanup();
cd28ab6a
SH		 4923}
4924
4925module_init(sky2_init_module);
4926module_exit(sky2_cleanup_module);
4927
4928MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4929MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4930MODULE_LICENSE("GPL");
5f4f9dc1 4931MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree