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[PATCH] sky2: version 0.12
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
cd28ab6a
SH		 27 * TOTEST
28 * - speed setting
724bca3c 29 * - suspend/resume
cd28ab6a
SH		 30 */
31
32#include <linux/config.h>
793b883e 33#include <linux/crc32.h>
cd28ab6a
SH		 34#include <linux/kernel.h>
35#include <linux/version.h>
36#include <linux/module.h>
37#include <linux/netdevice.h>
d0bbccfa 38#include <linux/dma-mapping.h>
cd28ab6a
SH		 39#include <linux/etherdevice.h>
40#include <linux/ethtool.h>
41#include <linux/pci.h>
42#include <linux/ip.h>
43#include <linux/tcp.h>
44#include <linux/in.h>
45#include <linux/delay.h>
91c86df5 46#include <linux/workqueue.h>
d1f13708 47#include <linux/if_vlan.h>
d70cd51a 48#include <linux/prefetch.h>
ef743d33 49#include <linux/mii.h>
cd28ab6a
SH		 50
51#include <asm/irq.h>
52
d1f13708
SH		 53#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
54#define SKY2_VLAN_TAG_USED 1
55#endif
56
cd28ab6a
SH		 57#include "sky2.h"
58
59#define DRV_NAME "sky2"
e0c94455 60#define DRV_VERSION "0.12"
cd28ab6a
SH		 61#define PFX DRV_NAME " "
62
63/*
64 * The Yukon II chipset takes 64 bit command blocks (called list elements)
65 * that are organized into three (receive, transmit, status) different rings
66 * similar to Tigon3. A transmit can require several elements;
67 * a receive requires one (or two if using 64 bit dma).
68 */
69
cd28ab6a 70#define is_ec_a1(hw) \
21437643
SH		 71 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
72 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
cd28ab6a 73
13210ce5 74#define RX_LE_SIZE 512
cd28ab6a 75#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 76#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 77#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 78#define RX_SKB_ALIGN 8
793b883e
SH		 79
80#define TX_RING_SIZE 512
81#define TX_DEF_PENDING (TX_RING_SIZE - 1)
82#define TX_MIN_PENDING 64
83#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
cd28ab6a 84
793b883e 85#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 86#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
87#define ETH_JUMBO_MTU 9000
88#define TX_WATCHDOG (5 * HZ)
89#define NAPI_WEIGHT 64
90#define PHY_RETRIES 1000
91
92static const u32 default_msg =
793b883e
SH		 93 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
94 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
95 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
cd28ab6a 96
793b883e 97static int debug = -1; /* defaults above */
cd28ab6a
SH		 98module_param(debug, int, 0);
99MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
100
bdb5c58e
SH		 101static int copybreak __read_mostly = 256;
102module_param(copybreak, int, 0);
103MODULE_PARM_DESC(copybreak, "Receive copy threshold");
104
cd28ab6a 105static const struct pci_device_id sky2_id_table[] = {
793b883e 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a
SH		 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 125 { 0 }
126};
793b883e 127
cd28ab6a
SH		 128MODULE_DEVICE_TABLE(pci, sky2_id_table);
129
130/* Avoid conditionals by using array */
131static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
132static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
133
92f965e8
SH		 134/* This driver supports yukon2 chipset only */
135static const char *yukon2_name[] = {
136 "XL", /* 0xb3 */
137 "EC Ultra", /* 0xb4 */
138 "UNKNOWN", /* 0xb5 */
139 "EC", /* 0xb6 */
140 "FE", /* 0xb7 */
793b883e
SH		 141};
142
793b883e 143/* Access to external PHY */
ef743d33 144static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 145{
146 int i;
147
148 gma_write16(hw, port, GM_SMI_DATA, val);
149 gma_write16(hw, port, GM_SMI_CTRL,
150 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
151
152 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 153 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 154 return 0;
793b883e 155 udelay(1);
cd28ab6a 156 }
ef743d33 157
793b883e 158 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 159 return -ETIMEDOUT;
cd28ab6a
SH		 160}
161
ef743d33 162static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 163{
164 int i;
165
793b883e 166 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 167 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
168
169 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 170 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
171 *val = gma_read16(hw, port, GM_SMI_DATA);
172 return 0;
173 }
174
793b883e 175 udelay(1);
cd28ab6a
SH		 176 }
177
ef743d33
SH		 178 return -ETIMEDOUT;
179}
180
181static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
182{
183 u16 v;
184
185 if (__gm_phy_read(hw, port, reg, &v) != 0)
186 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
187 return v;
cd28ab6a
SH		 188}
189
5afa0a9c
SH		 190static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
191{
192 u16 power_control;
193 u32 reg1;
194 int vaux;
195 int ret = 0;
196
197 pr_debug("sky2_set_power_state %d\n", state);
198 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
199
200 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
201 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
202 (power_control & PCI_PM_CAP_PME_D3cold);
203
204 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
205
206 power_control |= PCI_PM_CTRL_PME_STATUS;
207 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
208
209 switch (state) {
210 case PCI_D0:
211 /* switch power to VCC (WA for VAUX problem) */
212 sky2_write8(hw, B0_POWER_CTRL,
213 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
214
215 /* disable Core Clock Division, */
216 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
217
218 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
219 /* enable bits are inverted */
220 sky2_write8(hw, B2_Y2_CLK_GATE,
221 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
222 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
223 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
224 else
225 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
226
227 /* Turn off phy power saving */
228 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
229 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
230
d571b694 231 /* looks like this XL is back asswards .. */
5afa0a9c
SH		 232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
233 reg1 |= PCI_Y2_PHY1_COMA;
234 if (hw->ports > 1)
235 reg1 |= PCI_Y2_PHY2_COMA;
236 }
237 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
238 break;
239
240 case PCI_D3hot:
241 case PCI_D3cold:
242 /* Turn on phy power saving */
243 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
244 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
245 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
246 else
247 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
248 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
249
250 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
251 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
252 else
253 /* enable bits are inverted */
254 sky2_write8(hw, B2_Y2_CLK_GATE,
255 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
256 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
257 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
258
259 /* switch power to VAUX */
260 if (vaux && state != PCI_D3cold)
261 sky2_write8(hw, B0_POWER_CTRL,
262 (PC_VAUX_ENA | PC_VCC_ENA |
263 PC_VAUX_ON | PC_VCC_OFF));
264 break;
265 default:
266 printk(KERN_ERR PFX "Unknown power state %d\n", state);
267 ret = -1;
268 }
269
270 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
271 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
272 return ret;
273}
274
cd28ab6a
SH		 275static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
276{
277 u16 reg;
278
279 /* disable all GMAC IRQ's */
280 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
281 /* disable PHY IRQs */
282 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 283
cd28ab6a
SH		 284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292}
293
294static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
295{
296 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 297 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 298
793b883e 299 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
cd28ab6a
SH		 300 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
301
302 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 303 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 304 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
305
306 if (hw->chip_id == CHIP_ID_YUKON_EC)
307 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
308 else
309 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
310
311 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
312 }
313
314 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
315 if (hw->copper) {
316 if (hw->chip_id == CHIP_ID_YUKON_FE) {
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
319 } else {
320 /* disable energy detect */
321 ctrl &= ~PHY_M_PC_EN_DET_MSK;
322
323 /* enable automatic crossover */
324 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
325
326 if (sky2->autoneg == AUTONEG_ENABLE &&
327 hw->chip_id == CHIP_ID_YUKON_XL) {
328 ctrl &= ~PHY_M_PC_DSC_MSK;
329 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
330 }
331 }
332 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
333 } else {
334 /* workaround for deviation #4.88 (CRC errors) */
335 /* disable Automatic Crossover */
336
337 ctrl &= ~PHY_M_PC_MDIX_MSK;
338 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
339
340 if (hw->chip_id == CHIP_ID_YUKON_XL) {
341 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 ctrl &= ~PHY_M_MAC_MD_MSK;
345 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
347
348 /* select page 1 to access Fiber registers */
349 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
350 }
cd28ab6a
SH		 351 }
352
353 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
354 if (sky2->autoneg == AUTONEG_DISABLE)
355 ctrl &= ~PHY_CT_ANE;
356 else
357 ctrl |= PHY_CT_ANE;
358
359 ctrl |= PHY_CT_RESET;
360 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
361
362 ctrl = 0;
363 ct1000 = 0;
364 adv = PHY_AN_CSMA;
365
366 if (sky2->autoneg == AUTONEG_ENABLE) {
367 if (hw->copper) {
368 if (sky2->advertising & ADVERTISED_1000baseT_Full)
369 ct1000 |= PHY_M_1000C_AFD;
370 if (sky2->advertising & ADVERTISED_1000baseT_Half)
371 ct1000 |= PHY_M_1000C_AHD;
372 if (sky2->advertising & ADVERTISED_100baseT_Full)
373 adv |= PHY_M_AN_100_FD;
374 if (sky2->advertising & ADVERTISED_100baseT_Half)
375 adv |= PHY_M_AN_100_HD;
376 if (sky2->advertising & ADVERTISED_10baseT_Full)
377 adv |= PHY_M_AN_10_FD;
378 if (sky2->advertising & ADVERTISED_10baseT_Half)
379 adv |= PHY_M_AN_10_HD;
793b883e 380 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 381 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
382
383 /* Set Flow-control capabilities */
384 if (sky2->tx_pause && sky2->rx_pause)
793b883e 385 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 386 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 387 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 388 else if (!sky2->rx_pause && sky2->tx_pause)
389 adv |= PHY_AN_PAUSE_ASYM; /* local */
390
391 /* Restart Auto-negotiation */
392 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
393 } else {
394 /* forced speed/duplex settings */
395 ct1000 = PHY_M_1000C_MSE;
396
397 if (sky2->duplex == DUPLEX_FULL)
398 ctrl |= PHY_CT_DUP_MD;
399
400 switch (sky2->speed) {
401 case SPEED_1000:
402 ctrl |= PHY_CT_SP1000;
403 break;
404 case SPEED_100:
405 ctrl |= PHY_CT_SP100;
406 break;
407 }
408
409 ctrl |= PHY_CT_RESET;
410 }
411
412 if (hw->chip_id != CHIP_ID_YUKON_FE)
413 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
414
415 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
416 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
417
418 /* Setup Phy LED's */
419 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
420 ledover = 0;
421
422 switch (hw->chip_id) {
423 case CHIP_ID_YUKON_FE:
424 /* on 88E3082 these bits are at 11..9 (shifted left) */
425 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
426
427 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
428
429 /* delete ACT LED control bits */
430 ctrl &= ~PHY_M_FELP_LED1_MSK;
431 /* change ACT LED control to blink mode */
432 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
433 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
434 break;
435
436 case CHIP_ID_YUKON_XL:
793b883e 437 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 438
439 /* select page 3 to access LED control register */
440 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
441
442 /* set LED Function Control register */
793b883e
SH		 443 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
444 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
445 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
446 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 447
448 /* set Polarity Control register */
449 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 450 (PHY_M_POLC_LS1_P_MIX(4) |
451 PHY_M_POLC_IS0_P_MIX(4) |
452 PHY_M_POLC_LOS_CTRL(2) |
453 PHY_M_POLC_INIT_CTRL(2) |
454 PHY_M_POLC_STA1_CTRL(2) |
455 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 456
457 /* restore page register */
793b883e 458 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 459 break;
460
461 default:
462 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
463 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
464 /* turn off the Rx LED (LED_RX) */
465 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
466 }
467
468 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
469
470 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
471 /* turn on 100 Mbps LED (LED_LINK100) */
472 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
473 }
474
475 if (ledover)
476 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
477
d571b694 478 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 479 if (sky2->autoneg == AUTONEG_ENABLE)
480 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
481 else
482 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
483}
484
1b537565
SH		 485/* Force a renegotiation */
486static void sky2_phy_reinit(struct sky2_port *sky2)
487{
488 down(&sky2->phy_sema);
489 sky2_phy_init(sky2->hw, sky2->port);
490 up(&sky2->phy_sema);
491}
492
cd28ab6a
SH		 493static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
494{
495 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
496 u16 reg;
497 int i;
498 const u8 *addr = hw->dev[port]->dev_addr;
499
42eeea01
SH		 500 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
501 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 502
503 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
504
793b883e 505 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 506 /* WA DEV_472 -- looks like crossed wires on port 2 */
507 /* clear GMAC 1 Control reset */
508 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
509 do {
510 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
511 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
512 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
513 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
514 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
515 }
516
cd28ab6a
SH		 517 if (sky2->autoneg == AUTONEG_DISABLE) {
518 reg = gma_read16(hw, port, GM_GP_CTRL);
519 reg |= GM_GPCR_AU_ALL_DIS;
520 gma_write16(hw, port, GM_GP_CTRL, reg);
521 gma_read16(hw, port, GM_GP_CTRL);
522
cd28ab6a
SH		 523 switch (sky2->speed) {
524 case SPEED_1000:
525 reg |= GM_GPCR_SPEED_1000;
526 /* fallthru */
527 case SPEED_100:
528 reg |= GM_GPCR_SPEED_100;
529 }
530
531 if (sky2->duplex == DUPLEX_FULL)
532 reg |= GM_GPCR_DUP_FULL;
533 } else
534 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
535
536 if (!sky2->tx_pause && !sky2->rx_pause) {
537 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 538 reg |=
539 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
540 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 541 /* disable Rx flow-control */
542 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
543 }
544
545 gma_write16(hw, port, GM_GP_CTRL, reg);
546
793b883e 547 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 548
91c86df5 549 down(&sky2->phy_sema);
cd28ab6a 550 sky2_phy_init(hw, port);
91c86df5 551 up(&sky2->phy_sema);
cd28ab6a
SH		 552
553 /* MIB clear */
554 reg = gma_read16(hw, port, GM_PHY_ADDR);
555 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
556
557 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
793b883e 558 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
cd28ab6a
SH		 559 gma_write16(hw, port, GM_PHY_ADDR, reg);
560
561 /* transmit control */
562 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
563
564 /* receive control reg: unicast + multicast + no FCS */
565 gma_write16(hw, port, GM_RX_CTRL,
793b883e 566 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 567
568 /* transmit flow control */
569 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
570
571 /* transmit parameter */
572 gma_write16(hw, port, GM_TX_PARAM,
573 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
574 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
575 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
576 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
577
578 /* serial mode register */
579 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 580 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 581
6b1a3aef 582 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 583 reg |= GM_SMOD_JUMBO_ENA;
584
585 gma_write16(hw, port, GM_SERIAL_MODE, reg);
586
cd28ab6a
SH		 587 /* virtual address for data */
588 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
589
793b883e
SH		 590 /* physical address: used for pause frames */
591 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
592
593 /* ignore counter overflows */
cd28ab6a
SH		 594 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
595 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
596 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
597
598 /* Configure Rx MAC FIFO */
599 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
793b883e 600 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
d1f13708 601 GMF_RX_CTRL_DEF);
cd28ab6a 602
d571b694 603 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 604 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 605
793b883e
SH		 606 /* Set threshold to 0xa (64 bytes)
607 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 608 */
609 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
610
611 /* Configure Tx MAC FIFO */
612 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
613 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 614
615 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
616 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
617 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
618 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
619 /* set Tx GMAC FIFO Almost Empty Threshold */
620 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
621 /* Disable Store & Forward mode for TX */
622 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
623 }
624 }
625
cd28ab6a
SH		 626}
627
628static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
629{
630 u32 end;
631
632 start /= 8;
633 len /= 8;
634 end = start + len - 1;
793b883e 635
cd28ab6a
SH		 636 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
637 sky2_write32(hw, RB_ADDR(q, RB_START), start);
638 sky2_write32(hw, RB_ADDR(q, RB_END), end);
639 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
640 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
641
642 if (q == Q_R1 || q == Q_R2) {
793b883e
SH		 643 u32 rxup, rxlo;
644
645 rxlo = len/2;
646 rxup = rxlo + len/4;
793b883e 647
cd28ab6a 648 /* Set thresholds on receive queue's */
793b883e
SH		 649 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
650 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
cd28ab6a
SH		 651 } else {
652 /* Enable store & forward on Tx queue's because
653 * Tx FIFO is only 1K on Yukon
654 */
655 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
656 }
657
658 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 659 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 660}
661
cd28ab6a 662/* Setup Bus Memory Interface */
af4ed7e6 663static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 664{
665 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
666 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
667 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 668 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 669}
670
cd28ab6a
SH		 671/* Setup prefetch unit registers. This is the interface between
672 * hardware and driver list elements
673 */
8cc048e3 674static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 675 u64 addr, u32 last)
676{
cd28ab6a
SH		 677 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
678 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
679 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
680 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
681 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
682 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 683
684 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 685}
686
793b883e
SH		 687static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
688{
689 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
690
691 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
692 return le;
693}
cd28ab6a
SH		 694
695/*
d571b694 696 * This is a workaround code taken from SysKonnect sk98lin driver
793b883e 697 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
cd28ab6a
SH		 698 */
699static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
700 u16 idx, u16 *last, u16 size)
cd28ab6a 701{
cd28ab6a
SH		 702 if (is_ec_a1(hw) && idx < *last) {
703 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
704
705 if (hwget == 0) {
706 /* Start prefetching again */
793b883e 707 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
cd28ab6a
SH		 708 goto setnew;
709 }
710
793b883e 711 if (hwget == size - 1) {
cd28ab6a
SH		 712 /* set watermark to one list element */
713 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
714
715 /* set put index to first list element */
716 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
793b883e
SH		 717 } else /* have hardware go to end of list */
718 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
719 size - 1);
cd28ab6a 720 } else {
793b883e 721setnew:
cd28ab6a 722 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
cd28ab6a 723 }
bea86103 724 *last = idx;
cd28ab6a
SH		 725}
726
793b883e 727
cd28ab6a
SH		 728static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
729{
730 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
731 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
732 return le;
733}
734
a018e330
SH		 735/* Return high part of DMA address (could be 32 or 64 bit) */
736static inline u32 high32(dma_addr_t a)
737{
738 return (a >> 16) >> 16;
739}
740
793b883e 741/* Build description to hardware about buffer */
734d1868 742static inline void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 743{
744 struct sky2_rx_le *le;
734d1868
SH		 745 u32 hi = high32(map);
746 u16 len = sky2->rx_bufsize;
cd28ab6a 747
793b883e 748 if (sky2->rx_addr64 != hi) {
cd28ab6a 749 le = sky2_next_rx(sky2);
793b883e 750 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 751 le->ctrl = 0;
752 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 753 sky2->rx_addr64 = high32(map + len);
cd28ab6a 754 }
793b883e 755
cd28ab6a 756 le = sky2_next_rx(sky2);
734d1868
SH		 757 le->addr = cpu_to_le32((u32) map);
758 le->length = cpu_to_le16(len);
cd28ab6a
SH		 759 le->ctrl = 0;
760 le->opcode = OP_PACKET | HW_OWNER;
761}
762
793b883e 763
cd28ab6a
SH		 764/* Tell chip where to start receive checksum.
765 * Actually has two checksums, but set both same to avoid possible byte
766 * order problems.
767 */
793b883e 768static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 769{
770 struct sky2_rx_le *le;
771
cd28ab6a 772 le = sky2_next_rx(sky2);
793b883e 773 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 774 le->ctrl = 0;
775 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 776
793b883e
SH		 777 sky2_write32(sky2->hw,
778 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
779 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 780
781}
782
6b1a3aef
SH		 783/*
784 * The RX Stop command will not work for Yukon-2 if the BMU does not
785 * reach the end of packet and since we can't make sure that we have
786 * incoming data, we must reset the BMU while it is not doing a DMA
787 * transfer. Since it is possible that the RX path is still active,
788 * the RX RAM buffer will be stopped first, so any possible incoming
789 * data will not trigger a DMA. After the RAM buffer is stopped, the
790 * BMU is polled until any DMA in progress is ended and only then it
791 * will be reset.
792 */
793static void sky2_rx_stop(struct sky2_port *sky2)
794{
795 struct sky2_hw *hw = sky2->hw;
796 unsigned rxq = rxqaddr[sky2->port];
797 int i;
798
799 /* disable the RAM Buffer receive queue */
800 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
801
802 for (i = 0; i < 0xffff; i++)
803 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
804 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
805 goto stopped;
806
807 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
808 sky2->netdev->name);
809stopped:
810 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
811
812 /* reset the Rx prefetch unit */
813 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
814}
793b883e 815
d571b694 816/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 817static void sky2_rx_clean(struct sky2_port *sky2)
818{
819 unsigned i;
820
821 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 822 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 823 struct ring_info *re = sky2->rx_ring + i;
824
825 if (re->skb) {
793b883e 826 pci_unmap_single(sky2->hw->pdev,
734d1868 827 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 828 PCI_DMA_FROMDEVICE);
829 kfree_skb(re->skb);
830 re->skb = NULL;
831 }
832 }
833}
834
ef743d33
SH		 835/* Basic MII support */
836static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
837{
838 struct mii_ioctl_data *data = if_mii(ifr);
839 struct sky2_port *sky2 = netdev_priv(dev);
840 struct sky2_hw *hw = sky2->hw;
841 int err = -EOPNOTSUPP;
842
843 if (!netif_running(dev))
844 return -ENODEV; /* Phy still in reset */
845
846 switch(cmd) {
847 case SIOCGMIIPHY:
848 data->phy_id = PHY_ADDR_MARV;
849
850 /* fallthru */
851 case SIOCGMIIREG: {
852 u16 val = 0;
91c86df5
SH		 853
854 down(&sky2->phy_sema);
ef743d33 855 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
91c86df5
SH		 856 up(&sky2->phy_sema);
857
ef743d33
SH		 858 data->val_out = val;
859 break;
860 }
861
862 case SIOCSMIIREG:
863 if (!capable(CAP_NET_ADMIN))
864 return -EPERM;
865
91c86df5 866 down(&sky2->phy_sema);
ef743d33
SH		 867 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
868 data->val_in);
91c86df5 869 up(&sky2->phy_sema);
ef743d33
SH		 870 break;
871 }
872 return err;
873}
874
d1f13708
SH		 875#ifdef SKY2_VLAN_TAG_USED
876static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
877{
878 struct sky2_port *sky2 = netdev_priv(dev);
879 struct sky2_hw *hw = sky2->hw;
880 u16 port = sky2->port;
d1f13708 881
f2e46561 882 spin_lock(&sky2->tx_lock);
d1f13708
SH		 883
884 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
885 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
886 sky2->vlgrp = grp;
887
f2e46561 888 spin_unlock(&sky2->tx_lock);
d1f13708
SH		 889}
890
891static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
892{
893 struct sky2_port *sky2 = netdev_priv(dev);
894 struct sky2_hw *hw = sky2->hw;
895 u16 port = sky2->port;
d1f13708 896
f2e46561 897 spin_lock(&sky2->tx_lock);
d1f13708
SH		 898
899 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
900 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
901 if (sky2->vlgrp)
902 sky2->vlgrp->vlan_devices[vid] = NULL;
903
f2e46561 904 spin_unlock(&sky2->tx_lock);
d1f13708
SH		 905}
906#endif
907
82788c7a
SH		 908/*
909 * It appears the hardware has a bug in the FIFO logic that
910 * cause it to hang if the FIFO gets overrun and the receive buffer
911 * is not aligned. ALso alloc_skb() won't align properly if slab
912 * debugging is enabled.
913 */
914static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
915{
916 struct sk_buff *skb;
917
918 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
919 if (likely(skb)) {
920 unsigned long p = (unsigned long) skb->data;
921 skb_reserve(skb,
922 ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
923 }
924
925 return skb;
926}
927
cd28ab6a
SH		 928/*
929 * Allocate and setup receiver buffer pool.
930 * In case of 64 bit dma, there are 2X as many list elements
931 * available as ring entries
932 * and need to reserve one list element so we don't wrap around.
933 */
6b1a3aef 934static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 935{
6b1a3aef 936 struct sky2_hw *hw = sky2->hw;
6b1a3aef
SH		 937 unsigned rxq = rxqaddr[sky2->port];
938 int i;
cd28ab6a 939
6b1a3aef 940 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 941 sky2_qset(hw, rxq);
6b1a3aef
SH		 942 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
943
944 rx_set_checksum(sky2);
793b883e 945 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 946 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 947
82788c7a 948 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
cd28ab6a
SH		 949 if (!re->skb)
950 goto nomem;
951
6b1a3aef 952 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 953 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
954 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 955 }
956
6b1a3aef
SH		 957 /* Tell chip about available buffers */
958 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
959 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
cd28ab6a
SH		 960 return 0;
961nomem:
962 sky2_rx_clean(sky2);
963 return -ENOMEM;
964}
965
966/* Bring up network interface. */
967static int sky2_up(struct net_device *dev)
968{
969 struct sky2_port *sky2 = netdev_priv(dev);
970 struct sky2_hw *hw = sky2->hw;
971 unsigned port = sky2->port;
972 u32 ramsize, rxspace;
973 int err = -ENOMEM;
974
975 if (netif_msg_ifup(sky2))
976 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
977
978 /* must be power of 2 */
979 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 980 TX_RING_SIZE *
981 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 982 &sky2->tx_le_map);
983 if (!sky2->tx_le)
984 goto err_out;
985
6cdbbdf3 986 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 987 GFP_KERNEL);
988 if (!sky2->tx_ring)
989 goto err_out;
990 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 991
992 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
993 &sky2->rx_le_map);
994 if (!sky2->rx_le)
995 goto err_out;
996 memset(sky2->rx_le, 0, RX_LE_BYTES);
997
6cdbbdf3 998 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 999 GFP_KERNEL);
1000 if (!sky2->rx_ring)
1001 goto err_out;
1002
1003 sky2_mac_init(hw, port);
1004
1005 /* Configure RAM buffers */
1006 if (hw->chip_id == CHIP_ID_YUKON_FE ||
1007 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
1008 ramsize = 4096;
1009 else {
793b883e
SH		 1010 u8 e0 = sky2_read8(hw, B2_E_0);
1011 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
cd28ab6a
SH		 1012 }
1013
1014 /* 2/3 for Rx */
1015 rxspace = (2 * ramsize) / 3;
1016 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1017 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1018
793b883e
SH		 1019 /* Make sure SyncQ is disabled */
1020 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1021 RB_RST_SET);
1022
af4ed7e6 1023 sky2_qset(hw, txqaddr[port]);
5a5b1ea0
SH		 1024 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1025 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1026
1027
6b1a3aef
SH		 1028 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1029 TX_RING_SIZE - 1);
cd28ab6a 1030
6b1a3aef 1031 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1032 if (err)
1033 goto err_out;
1034
cd28ab6a
SH		 1035 /* Enable interrupts from phy/mac for port */
1036 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1037 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1038 return 0;
1039
1040err_out:
1b537565 1041 if (sky2->rx_le) {
cd28ab6a
SH		 1042 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1043 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1044 sky2->rx_le = NULL;
1045 }
1046 if (sky2->tx_le) {
cd28ab6a
SH		 1047 pci_free_consistent(hw->pdev,
1048 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1049 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1050 sky2->tx_le = NULL;
1051 }
1052 kfree(sky2->tx_ring);
1053 kfree(sky2->rx_ring);
cd28ab6a 1054
1b537565
SH		 1055 sky2->tx_ring = NULL;
1056 sky2->rx_ring = NULL;
cd28ab6a
SH		 1057 return err;
1058}
1059
793b883e
SH		 1060/* Modular subtraction in ring */
1061static inline int tx_dist(unsigned tail, unsigned head)
1062{
129372d0 1063 return (head - tail) % TX_RING_SIZE;
793b883e 1064}
cd28ab6a 1065
793b883e
SH		 1066/* Number of list elements available for next tx */
1067static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1068{
793b883e 1069 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1070}
1071
793b883e
SH		 1072/* Estimate of number of transmit list elements required */
1073static inline unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1074{
793b883e
SH		 1075 unsigned count;
1076
1077 count = sizeof(dma_addr_t) / sizeof(u32);
1078 count += skb_shinfo(skb)->nr_frags * count;
1079
1080 if (skb_shinfo(skb)->tso_size)
1081 ++count;
1082
0e3ff6aa 1083 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1084 ++count;
1085
1086 return count;
cd28ab6a
SH		 1087}
1088
793b883e
SH		 1089/*
1090 * Put one packet in ring for transmit.
1091 * A single packet can generate multiple list elements, and
1092 * the number of ring elements will probably be less than the number
1093 * of list elements used.
f2e46561
SH		 1094 *
1095 * No BH disabling for tx_lock here (like tg3)
793b883e 1096 */
cd28ab6a
SH		 1097static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1098{
1099 struct sky2_port *sky2 = netdev_priv(dev);
1100 struct sky2_hw *hw = sky2->hw;
d1f13708 1101 struct sky2_tx_le *le = NULL;
6cdbbdf3 1102 struct tx_ring_info *re;
cd28ab6a
SH		 1103 unsigned i, len;
1104 dma_addr_t mapping;
1105 u32 addr64;
1106 u16 mss;
1107 u8 ctrl;
1108
f2e46561 1109 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1110 return NETDEV_TX_LOCKED;
1111
793b883e 1112 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1113 /* There is a known but harmless race with lockless tx
1114 * and netif_stop_queue.
1115 */
1116 if (!netif_queue_stopped(dev)) {
1117 netif_stop_queue(dev);
1118 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1119 dev->name);
1120 }
f2e46561 1121 spin_unlock(&sky2->tx_lock);
cd28ab6a 1122
cd28ab6a
SH		 1123 return NETDEV_TX_BUSY;
1124 }
1125
793b883e 1126 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1127 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1128 dev->name, sky2->tx_prod, skb->len);
1129
cd28ab6a
SH		 1130 len = skb_headlen(skb);
1131 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1132 addr64 = high32(mapping);
793b883e
SH		 1133
1134 re = sky2->tx_ring + sky2->tx_prod;
1135
a018e330
SH		 1136 /* Send high bits if changed or crosses boundary */
1137 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1138 le = get_tx_le(sky2);
1139 le->tx.addr = cpu_to_le32(addr64);
1140 le->ctrl = 0;
1141 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1142 sky2->tx_addr64 = high32(mapping + len);
793b883e 1143 }
cd28ab6a
SH		 1144
1145 /* Check for TCP Segmentation Offload */
1146 mss = skb_shinfo(skb)->tso_size;
793b883e 1147 if (mss != 0) {
cd28ab6a
SH		 1148 /* just drop the packet if non-linear expansion fails */
1149 if (skb_header_cloned(skb) &&
1150 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
793b883e
SH		 1151 dev_kfree_skb_any(skb);
1152 goto out_unlock;
cd28ab6a
SH		 1153 }
1154
1155 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1156 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1157 mss += ETH_HLEN;
793b883e 1158 }
cd28ab6a 1159
793b883e 1160 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1161 le = get_tx_le(sky2);
1162 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1163 le->tx.tso.rsvd = 0;
cd28ab6a 1164 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1165 le->ctrl = 0;
793b883e 1166 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1167 }
1168
cd28ab6a 1169 ctrl = 0;
d1f13708
SH		 1170#ifdef SKY2_VLAN_TAG_USED
1171 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1172 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1173 if (!le) {
1174 le = get_tx_le(sky2);
1175 le->tx.addr = 0;
1176 le->opcode = OP_VLAN|HW_OWNER;
1177 le->ctrl = 0;
1178 } else
1179 le->opcode |= OP_VLAN;
1180 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1181 ctrl |= INS_VLAN;
1182 }
1183#endif
1184
1185 /* Handle TCP checksum offload */
cd28ab6a 1186 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1187 u16 hdr = skb->h.raw - skb->data;
1188 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1189
1190 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1191 if (skb->nh.iph->protocol == IPPROTO_UDP)
1192 ctrl |= UDPTCP;
1193
1194 le = get_tx_le(sky2);
1195 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1196 le->tx.csum.offset = cpu_to_le16(offset);
1197 le->length = 0; /* initial checksum value */
cd28ab6a 1198 le->ctrl = 1; /* one packet */
793b883e 1199 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1200 }
1201
1202 le = get_tx_le(sky2);
1203 le->tx.addr = cpu_to_le32((u32) mapping);
1204 le->length = cpu_to_le16(len);
1205 le->ctrl = ctrl;
793b883e 1206 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1207
793b883e 1208 /* Record the transmit mapping info */
cd28ab6a 1209 re->skb = skb;
6cdbbdf3 1210 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1211
1212 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1213 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1214 struct tx_ring_info *fre;
cd28ab6a
SH		 1215
1216 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1217 frag->size, PCI_DMA_TODEVICE);
793b883e
SH		 1218 addr64 = (mapping >> 16) >> 16;
1219 if (addr64 != sky2->tx_addr64) {
1220 le = get_tx_le(sky2);
1221 le->tx.addr = cpu_to_le32(addr64);
1222 le->ctrl = 0;
1223 le->opcode = OP_ADDR64 | HW_OWNER;
1224 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1225 }
1226
1227 le = get_tx_le(sky2);
1228 le->tx.addr = cpu_to_le32((u32) mapping);
1229 le->length = cpu_to_le16(frag->size);
1230 le->ctrl = ctrl;
793b883e 1231 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1232
793b883e
SH		 1233 fre = sky2->tx_ring
1234 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
6cdbbdf3 1235 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1236 }
6cdbbdf3 1237
793b883e 1238 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1239 le->ctrl |= EOP;
1240
724bca3c 1241 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
cd28ab6a
SH		 1242 &sky2->tx_last_put, TX_RING_SIZE);
1243
0e3ff6aa 1244 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
cd28ab6a 1245 netif_stop_queue(dev);
793b883e
SH		 1246
1247out_unlock:
1248 mmiowb();
f2e46561 1249 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1250
1251 dev->trans_start = jiffies;
1252 return NETDEV_TX_OK;
1253}
1254
cd28ab6a 1255/*
793b883e
SH		 1256 * Free ring elements from starting at tx_cons until "done"
1257 *
1258 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1259 * buffers; these are deferred until completion.
cd28ab6a 1260 */
d11c13e7 1261static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1262{
d11c13e7 1263 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1264 struct pci_dev *pdev = sky2->hw->pdev;
1265 u16 nxt, put;
793b883e 1266 unsigned i;
cd28ab6a 1267
0e3ff6aa 1268 BUG_ON(done >= TX_RING_SIZE);
2224795d 1269
d11c13e7 1270 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1271 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1272 dev->name, done);
cd28ab6a 1273
af2a58ac
SH		 1274 for (put = sky2->tx_cons; put != done; put = nxt) {
1275 struct tx_ring_info *re = sky2->tx_ring + put;
1276 struct sk_buff *skb = re->skb;
cd28ab6a 1277
af2a58ac
SH		 1278 nxt = re->idx;
1279 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1280 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1281
793b883e 1282 /* Check for partial status */
af2a58ac
SH		 1283 if (tx_dist(put, done) < tx_dist(put, nxt))
1284 break;
793b883e
SH		 1285
1286 skb = re->skb;
af2a58ac 1287 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1288 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1289
1290 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1291 struct tx_ring_info *fre;
af2a58ac
SH		 1292 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1293 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1294 skb_shinfo(skb)->frags[i].size,
734d1868 1295 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1296 }
1297
cd28ab6a 1298 dev_kfree_skb_any(skb);
793b883e 1299 }
793b883e 1300
af2a58ac
SH		 1301 spin_lock(&sky2->tx_lock);
1302 sky2->tx_cons = put;
793b883e 1303 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a
SH		 1304 netif_wake_queue(dev);
1305 spin_unlock(&sky2->tx_lock);
1306}
1307
1308/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1309static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1310{
d11c13e7 1311 sky2_tx_complete(sky2, sky2->tx_prod);
cd28ab6a
SH		 1312}
1313
1314/* Network shutdown */
1315static int sky2_down(struct net_device *dev)
1316{
1317 struct sky2_port *sky2 = netdev_priv(dev);
1318 struct sky2_hw *hw = sky2->hw;
1319 unsigned port = sky2->port;
1320 u16 ctrl;
cd28ab6a 1321
1b537565
SH		 1322 /* Never really got started! */
1323 if (!sky2->tx_le)
1324 return 0;
1325
cd28ab6a
SH		 1326 if (netif_msg_ifdown(sky2))
1327 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1328
018d1c66 1329 /* Stop more packets from being queued */
cd28ab6a
SH		 1330 netif_stop_queue(dev);
1331
018d1c66
SH		 1332 /* Disable port IRQ */
1333 local_irq_disable();
1334 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1335 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1336 local_irq_enable();
1337
91c86df5 1338 flush_scheduled_work();
018d1c66 1339
793b883e
SH		 1340 sky2_phy_reset(hw, port);
1341
cd28ab6a
SH		 1342 /* Stop transmitter */
1343 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1344 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1345
1346 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1347 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1348
1349 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1350 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1351 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1352
1353 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1354
1355 /* Workaround shared GMAC reset */
793b883e
SH		 1356 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1357 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1358 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1359
1360 /* Disable Force Sync bit and Enable Alloc bit */
1361 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1362 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1363
1364 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1365 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1366 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1367
1368 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1369 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1370 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1371
1372 /* Reset the Tx prefetch units */
1373 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1374 PREF_UNIT_RST_SET);
1375
1376 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1377
6b1a3aef 1378 sky2_rx_stop(sky2);
cd28ab6a
SH		 1379
1380 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1381 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1382
d571b694 1383 /* turn off LED's */
cd28ab6a
SH		 1384 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1385
018d1c66
SH		 1386 synchronize_irq(hw->pdev->irq);
1387
cd28ab6a
SH		 1388 sky2_tx_clean(sky2);
1389 sky2_rx_clean(sky2);
1390
1391 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1392 sky2->rx_le, sky2->rx_le_map);
1393 kfree(sky2->rx_ring);
1394
1395 pci_free_consistent(hw->pdev,
1396 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1397 sky2->tx_le, sky2->tx_le_map);
1398 kfree(sky2->tx_ring);
1399
1b537565
SH		 1400 sky2->tx_le = NULL;
1401 sky2->rx_le = NULL;
1402
1403 sky2->rx_ring = NULL;
1404 sky2->tx_ring = NULL;
1405
cd28ab6a
SH		 1406 return 0;
1407}
1408
1409static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1410{
793b883e
SH		 1411 if (!hw->copper)
1412 return SPEED_1000;
1413
cd28ab6a
SH		 1414 if (hw->chip_id == CHIP_ID_YUKON_FE)
1415 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1416
1417 switch (aux & PHY_M_PS_SPEED_MSK) {
1418 case PHY_M_PS_SPEED_1000:
1419 return SPEED_1000;
1420 case PHY_M_PS_SPEED_100:
1421 return SPEED_100;
1422 default:
1423 return SPEED_10;
1424 }
1425}
1426
1427static void sky2_link_up(struct sky2_port *sky2)
1428{
1429 struct sky2_hw *hw = sky2->hw;
1430 unsigned port = sky2->port;
1431 u16 reg;
1432
1433 /* Enable Transmit FIFO Underrun */
793b883e 1434 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1435
1436 reg = gma_read16(hw, port, GM_GP_CTRL);
1437 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1438 reg |= GM_GPCR_DUP_FULL;
1439
cd28ab6a
SH		 1440 /* enable Rx/Tx */
1441 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1442 gma_write16(hw, port, GM_GP_CTRL, reg);
1443 gma_read16(hw, port, GM_GP_CTRL);
1444
1445 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1446
1447 netif_carrier_on(sky2->netdev);
1448 netif_wake_queue(sky2->netdev);
1449
1450 /* Turn on link LED */
793b883e 1451 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1452 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1453
793b883e
SH		 1454 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1455 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1456
1457 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1458 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1459 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1460 SPEED_10 ? 7 : 0) |
1461 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1462 SPEED_100 ? 7 : 0) |
1463 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1464 SPEED_1000 ? 7 : 0));
1465 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1466 }
1467
cd28ab6a
SH		 1468 if (netif_msg_link(sky2))
1469 printk(KERN_INFO PFX
d571b694 1470 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1471 sky2->netdev->name, sky2->speed,
1472 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1473 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1474 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1475}
1476
1477static void sky2_link_down(struct sky2_port *sky2)
1478{
1479 struct sky2_hw *hw = sky2->hw;
1480 unsigned port = sky2->port;
1481 u16 reg;
1482
1483 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1484
1485 reg = gma_read16(hw, port, GM_GP_CTRL);
1486 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1487 gma_write16(hw, port, GM_GP_CTRL, reg);
1488 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1489
1490 if (sky2->rx_pause && !sky2->tx_pause) {
1491 /* restore Asymmetric Pause bit */
1492 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1493 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1494 | PHY_M_AN_ASP);
cd28ab6a
SH		 1495 }
1496
cd28ab6a
SH		 1497 netif_carrier_off(sky2->netdev);
1498 netif_stop_queue(sky2->netdev);
1499
1500 /* Turn on link LED */
1501 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1502
1503 if (netif_msg_link(sky2))
1504 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1505 sky2_phy_init(hw, port);
1506}
1507
793b883e
SH		 1508static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1509{
1510 struct sky2_hw *hw = sky2->hw;
1511 unsigned port = sky2->port;
1512 u16 lpa;
1513
1514 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1515
1516 if (lpa & PHY_M_AN_RF) {
1517 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1518 return -1;
1519 }
1520
1521 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1522 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1523 printk(KERN_ERR PFX "%s: master/slave fault",
1524 sky2->netdev->name);
1525 return -1;
1526 }
1527
1528 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1529 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1530 sky2->netdev->name);
1531 return -1;
1532 }
1533
1534 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1535
1536 sky2->speed = sky2_phy_speed(hw, aux);
1537
1538 /* Pause bits are offset (9..8) */
1539 if (hw->chip_id == CHIP_ID_YUKON_XL)
1540 aux >>= 6;
1541
1542 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1543 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1544
1545 if ((sky2->tx_pause || sky2->rx_pause)
1546 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1547 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1548 else
1549 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1550
1551 return 0;
1552}
cd28ab6a
SH		 1553
1554/*
91c86df5 1555 * Interrupt from PHY are handled outside of interrupt context
cd28ab6a
SH		 1556 * because accessing phy registers requires spin wait which might
1557 * cause excess interrupt latency.
1558 */
91c86df5 1559static void sky2_phy_task(void *arg)
cd28ab6a 1560{
91c86df5 1561 struct sky2_port *sky2 = arg;
cd28ab6a 1562 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1563 u16 istatus, phystat;
1564
91c86df5 1565 down(&sky2->phy_sema);
793b883e
SH		 1566 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1567 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
cd28ab6a
SH		 1568
1569 if (netif_msg_intr(sky2))
1570 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1571 sky2->netdev->name, istatus, phystat);
1572
1573 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1574 if (sky2_autoneg_done(sky2, phystat) == 0)
1575 sky2_link_up(sky2);
1576 goto out;
1577 }
cd28ab6a 1578
793b883e
SH		 1579 if (istatus & PHY_M_IS_LSP_CHANGE)
1580 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1581
793b883e
SH		 1582 if (istatus & PHY_M_IS_DUP_CHANGE)
1583 sky2->duplex =
1584 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1585
793b883e
SH		 1586 if (istatus & PHY_M_IS_LST_CHANGE) {
1587 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1588 sky2_link_up(sky2);
793b883e
SH		 1589 else
1590 sky2_link_down(sky2);
cd28ab6a 1591 }
793b883e 1592out:
91c86df5 1593 up(&sky2->phy_sema);
cd28ab6a
SH		 1594
1595 local_irq_disable();
793b883e 1596 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
cd28ab6a
SH		 1597 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1598 local_irq_enable();
1599}
1600
1601static void sky2_tx_timeout(struct net_device *dev)
1602{
1603 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1604 struct sky2_hw *hw = sky2->hw;
1605 unsigned txq = txqaddr[sky2->port];
cd28ab6a
SH		 1606
1607 if (netif_msg_timer(sky2))
1608 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1609
8cc048e3
SH		 1610 netif_stop_queue(dev);
1611
1612 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1613 sky2_read32(hw, Q_ADDR(txq, Q_CSR));
1614
1615 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
cd28ab6a
SH		 1616
1617 sky2_tx_clean(sky2);
8cc048e3
SH		 1618
1619 sky2_qset(hw, txq);
1620 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1621
1622 netif_wake_queue(dev);
cd28ab6a
SH		 1623}
1624
734d1868
SH		 1625
1626#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1627/* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1628static inline unsigned sky2_buf_size(int mtu)
1629{
1630 return roundup(mtu + ETH_HLEN + 4, 8);
1631}
1632
cd28ab6a
SH		 1633static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1634{
6b1a3aef
SH		 1635 struct sky2_port *sky2 = netdev_priv(dev);
1636 struct sky2_hw *hw = sky2->hw;
1637 int err;
1638 u16 ctl, mode;
cd28ab6a
SH		 1639
1640 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1641 return -EINVAL;
1642
5a5b1ea0
SH		 1643 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1644 return -EINVAL;
1645
6b1a3aef
SH		 1646 if (!netif_running(dev)) {
1647 dev->mtu = new_mtu;
1648 return 0;
1649 }
1650
6b1a3aef
SH		 1651 sky2_write32(hw, B0_IMSK, 0);
1652
018d1c66
SH		 1653 dev->trans_start = jiffies; /* prevent tx timeout */
1654 netif_stop_queue(dev);
1655 netif_poll_disable(hw->dev[0]);
1656
6b1a3aef
SH		 1657 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1658 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1659 sky2_rx_stop(sky2);
1660 sky2_rx_clean(sky2);
cd28ab6a
SH		 1661
1662 dev->mtu = new_mtu;
734d1868 1663 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef
SH		 1664 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1665 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1666
1667 if (dev->mtu > ETH_DATA_LEN)
1668 mode |= GM_SMOD_JUMBO_ENA;
1669
1670 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1671
6b1a3aef 1672 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1673
6b1a3aef 1674 err = sky2_rx_start(sky2);
6b1a3aef 1675 sky2_write32(hw, B0_IMSK, hw->intr_mask);
018d1c66 1676
1b537565
SH		 1677 if (err)
1678 dev_close(dev);
1679 else {
1680 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1681
1682 netif_poll_enable(hw->dev[0]);
1683 netif_wake_queue(dev);
1684 }
1685
cd28ab6a
SH		 1686 return err;
1687}
1688
1689/*
1690 * Receive one packet.
1691 * For small packets or errors, just reuse existing skb.
d571b694 1692 * For larger packets, get new buffer.
cd28ab6a 1693 */
d11c13e7 1694static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1695 u16 length, u32 status)
1696{
cd28ab6a 1697 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1698 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1699
1700 if (unlikely(netif_msg_rx_status(sky2)))
1701 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1702 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1703
793b883e 1704 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1705 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1706
42eeea01 1707 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1708 goto error;
1709
42eeea01
SH		 1710 if (!(status & GMR_FS_RX_OK))
1711 goto resubmit;
1712
6e15b712
SH		 1713 if ((status >> 16) != length || length > sky2->rx_bufsize)
1714 goto oversize;
1715
bdb5c58e 1716 if (length < copybreak) {
79e57d32
SH		 1717 skb = alloc_skb(length + 2, GFP_ATOMIC);
1718 if (!skb)
793b883e
SH		 1719 goto resubmit;
1720
79e57d32 1721 skb_reserve(skb, 2);
793b883e
SH		 1722 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1723 length, PCI_DMA_FROMDEVICE);
79e57d32 1724 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1725 skb->ip_summed = re->skb->ip_summed;
1726 skb->csum = re->skb->csum;
793b883e
SH		 1727 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1728 length, PCI_DMA_FROMDEVICE);
793b883e 1729 } else {
79e57d32
SH		 1730 struct sk_buff *nskb;
1731
82788c7a 1732 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1733 if (!nskb)
1734 goto resubmit;
cd28ab6a 1735
793b883e 1736 skb = re->skb;
79e57d32 1737 re->skb = nskb;
793b883e 1738 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1739 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1740 prefetch(skb->data);
cd28ab6a 1741
793b883e 1742 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1743 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1744 }
cd28ab6a 1745
79e57d32 1746 skb_put(skb, length);
793b883e 1747resubmit:
d11c13e7 1748 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1749 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1750
bea86103
SH		 1751 /* Tell receiver about new buffers. */
1752 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1753 &sky2->rx_last_put, RX_LE_SIZE);
1754
cd28ab6a
SH		 1755 return skb;
1756
6e15b712
SH		 1757oversize:
1758 ++sky2->net_stats.rx_over_errors;
1759 goto resubmit;
1760
cd28ab6a 1761error:
6e15b712
SH		 1762 ++sky2->net_stats.rx_errors;
1763
cd28ab6a
SH		 1764 if (netif_msg_rx_err(sky2))
1765 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1766 sky2->netdev->name, status, length);
793b883e
SH		 1767
1768 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1769 sky2->net_stats.rx_length_errors++;
1770 if (status & GMR_FS_FRAGMENT)
1771 sky2->net_stats.rx_frame_errors++;
1772 if (status & GMR_FS_CRC_ERR)
1773 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1774 if (status & GMR_FS_RX_FF_OV)
1775 sky2->net_stats.rx_fifo_errors++;
79e57d32 1776
793b883e 1777 goto resubmit;
cd28ab6a
SH		 1778}
1779
2224795d
SH		 1780/*
1781 * Check for transmit complete
793b883e 1782 */
13b97b74 1783#define TX_NO_STATUS 0xffff
2224795d 1784
13b97b74
SH		 1785static inline void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1786{
1787 if (last != TX_NO_STATUS) {
1788 struct net_device *dev = hw->dev[port];
1789 if (dev && netif_running(dev)) {
1790 struct sky2_port *sky2 = netdev_priv(dev);
1791 sky2_tx_complete(sky2, last);
1792 }
2224795d 1793 }
cd28ab6a
SH		 1794}
1795
1796/*
cd28ab6a
SH		 1797 * Both ports share the same status interrupt, therefore there is only
1798 * one poll routine.
cd28ab6a 1799 */
d11c13e7 1800static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 1801{
d11c13e7
SH		 1802 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1803 unsigned int to_do = min(dev0->quota, *budget);
cd28ab6a 1804 unsigned int work_done = 0;
793b883e 1805 u16 hwidx;
13b97b74 1806 u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
cd28ab6a 1807
793b883e 1808 hwidx = sky2_read16(hw, STAT_PUT_IDX);
79e57d32 1809 BUG_ON(hwidx >= STATUS_RING_SIZE);
af2a58ac 1810 rmb();
bea86103 1811
13210ce5
SH		 1812 while (hwidx != hw->st_idx) {
1813 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1814 struct net_device *dev;
d11c13e7 1815 struct sky2_port *sky2;
cd28ab6a 1816 struct sk_buff *skb;
cd28ab6a
SH		 1817 u32 status;
1818 u16 length;
13210ce5 1819 u8 op;
cd28ab6a 1820
13210ce5 1821 le = hw->st_le + hw->st_idx;
bea86103 1822 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
13210ce5 1823 prefetch(hw->st_le + hw->st_idx);
bea86103 1824
13210ce5
SH		 1825 BUG_ON(le->link >= 2);
1826 dev = hw->dev[le->link];
1827 if (dev == NULL || !netif_running(dev))
1828 continue;
1829
1830 sky2 = netdev_priv(dev);
cd28ab6a
SH		 1831 status = le32_to_cpu(le->status);
1832 length = le16_to_cpu(le->length);
13210ce5
SH		 1833 op = le->opcode & ~HW_OWNER;
1834 le->opcode = 0;
cd28ab6a 1835
13210ce5 1836 switch (op) {
cd28ab6a 1837 case OP_RXSTAT:
d11c13e7 1838 skb = sky2_receive(sky2, length, status);
d1f13708
SH		 1839 if (!skb)
1840 break;
13210ce5
SH		 1841
1842 skb->dev = dev;
1843 skb->protocol = eth_type_trans(skb, dev);
1844 dev->last_rx = jiffies;
1845
d1f13708
SH		 1846#ifdef SKY2_VLAN_TAG_USED
1847 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1848 vlan_hwaccel_receive_skb(skb,
1849 sky2->vlgrp,
1850 be16_to_cpu(sky2->rx_tag));
1851 } else
1852#endif
cd28ab6a 1853 netif_receive_skb(skb);
13210ce5
SH		 1854
1855 if (++work_done >= to_do)
1856 goto exit_loop;
cd28ab6a
SH		 1857 break;
1858
d1f13708
SH		 1859#ifdef SKY2_VLAN_TAG_USED
1860 case OP_RXVLAN:
1861 sky2->rx_tag = length;
1862 break;
1863
1864 case OP_RXCHKSVLAN:
1865 sky2->rx_tag = length;
1866 /* fall through */
1867#endif
cd28ab6a 1868 case OP_RXCHKS:
d11c13e7
SH		 1869 skb = sky2->rx_ring[sky2->rx_next].skb;
1870 skb->ip_summed = CHECKSUM_HW;
1871 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1872 break;
1873
1874 case OP_TXINDEXLE:
13b97b74
SH		 1875 /* TX index reports status for both ports */
1876 tx_done[0] = status & 0xffff;
1877 tx_done[1] = ((status >> 24) & 0xff)
1878 | (u16)(length & 0xf) << 8;
cd28ab6a
SH		 1879 break;
1880
cd28ab6a
SH		 1881 default:
1882 if (net_ratelimit())
793b883e 1883 printk(KERN_WARNING PFX
13210ce5 1884 "unknown status opcode 0x%x\n", op);
cd28ab6a
SH		 1885 break;
1886 }
13210ce5 1887 }
cd28ab6a 1888
13210ce5 1889exit_loop:
3e4b32e1 1890 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
793b883e
SH		 1891 mmiowb();
1892
13b97b74
SH		 1893 sky2_tx_check(hw, 0, tx_done[0]);
1894 sky2_tx_check(hw, 1, tx_done[1]);
1895
3e4b32e1 1896 if (sky2_read16(hw, STAT_PUT_IDX) == hw->st_idx) {
13b97b74 1897 /* need to restart TX timer */
cd28ab6a
SH		 1898 if (is_ec_a1(hw)) {
1899 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1900 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1901 }
1902
bea86103 1903 netif_rx_complete(dev0);
cd28ab6a
SH		 1904 hw->intr_mask |= Y2_IS_STAT_BMU;
1905 sky2_write32(hw, B0_IMSK, hw->intr_mask);
13210ce5
SH		 1906 mmiowb();
1907 return 0;
1908 } else {
1909 *budget -= work_done;
1910 dev0->quota -= work_done;
1911 return 1;
cd28ab6a 1912 }
cd28ab6a
SH		 1913}
1914
1915static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1916{
1917 struct net_device *dev = hw->dev[port];
1918
1919 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1920 dev->name, status);
1921
1922 if (status & Y2_IS_PAR_RD1) {
1923 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1924 dev->name);
1925 /* Clear IRQ */
1926 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1927 }
1928
1929 if (status & Y2_IS_PAR_WR1) {
1930 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1931 dev->name);
1932
1933 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1934 }
1935
1936 if (status & Y2_IS_PAR_MAC1) {
1937 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1938 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1939 }
1940
1941 if (status & Y2_IS_PAR_RX1) {
1942 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1943 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1944 }
1945
1946 if (status & Y2_IS_TCP_TXA1) {
1947 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1948 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1949 }
1950}
1951
1952static void sky2_hw_intr(struct sky2_hw *hw)
1953{
1954 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1955
793b883e 1956 if (status & Y2_IS_TIST_OV)
cd28ab6a 1957 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 1958
1959 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 1960 u16 pci_err;
1961
1962 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
cd28ab6a
SH		 1963 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1964 pci_name(hw->pdev), pci_err);
1965
1966 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1967 pci_write_config_word(hw->pdev, PCI_STATUS,
1968 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 1969 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1970 }
1971
1972 if (status & Y2_IS_PCI_EXP) {
d571b694 1973 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 1974 u32 pex_err;
1975
1976 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
cd28ab6a 1977
cd28ab6a
SH		 1978 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1979 pci_name(hw->pdev), pex_err);
1980
1981 /* clear the interrupt */
1982 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1983 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1984 0xffffffffUL);
cd28ab6a
SH		 1985 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1986
1987 if (pex_err & PEX_FATAL_ERRORS) {
1988 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1989 hwmsk &= ~Y2_IS_PCI_EXP;
1990 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1991 }
1992 }
1993
1994 if (status & Y2_HWE_L1_MASK)
1995 sky2_hw_error(hw, 0, status);
1996 status >>= 8;
1997 if (status & Y2_HWE_L1_MASK)
1998 sky2_hw_error(hw, 1, status);
1999}
2000
2001static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2002{
2003 struct net_device *dev = hw->dev[port];
2004 struct sky2_port *sky2 = netdev_priv(dev);
2005 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2006
2007 if (netif_msg_intr(sky2))
2008 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2009 dev->name, status);
2010
2011 if (status & GM_IS_RX_FF_OR) {
2012 ++sky2->net_stats.rx_fifo_errors;
2013 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2014 }
2015
2016 if (status & GM_IS_TX_FF_UR) {
2017 ++sky2->net_stats.tx_fifo_errors;
2018 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2019 }
cd28ab6a
SH		 2020}
2021
2022static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2023{
2024 struct net_device *dev = hw->dev[port];
2025 struct sky2_port *sky2 = netdev_priv(dev);
2026
2027 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2028 sky2_write32(hw, B0_IMSK, hw->intr_mask);
91c86df5 2029 schedule_work(&sky2->phy_task);
cd28ab6a
SH		 2030}
2031
2032static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2033{
2034 struct sky2_hw *hw = dev_id;
bea86103 2035 struct net_device *dev0 = hw->dev[0];
cd28ab6a
SH		 2036 u32 status;
2037
2038 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
793b883e 2039 if (status == 0 || status == ~0)
cd28ab6a
SH		 2040 return IRQ_NONE;
2041
2042 if (status & Y2_IS_HW_ERR)
2043 sky2_hw_intr(hw);
2044
793b883e 2045 /* Do NAPI for Rx and Tx status */
bea86103 2046 if (status & Y2_IS_STAT_BMU) {
cd28ab6a
SH		 2047 hw->intr_mask &= ~Y2_IS_STAT_BMU;
2048 sky2_write32(hw, B0_IMSK, hw->intr_mask);
bea86103 2049
0a122576
SH		 2050 if (likely(__netif_rx_schedule_prep(dev0))) {
2051 prefetch(&hw->st_le[hw->st_idx]);
bea86103 2052 __netif_rx_schedule(dev0);
0a122576 2053 }
cd28ab6a
SH		 2054 }
2055
793b883e 2056 if (status & Y2_IS_IRQ_PHY1)
cd28ab6a
SH		 2057 sky2_phy_intr(hw, 0);
2058
2059 if (status & Y2_IS_IRQ_PHY2)
2060 sky2_phy_intr(hw, 1);
2061
2062 if (status & Y2_IS_IRQ_MAC1)
2063 sky2_mac_intr(hw, 0);
2064
2065 if (status & Y2_IS_IRQ_MAC2)
2066 sky2_mac_intr(hw, 1);
2067
cd28ab6a 2068 sky2_write32(hw, B0_Y2_SP_ICR, 2);
793b883e
SH		 2069
2070 sky2_read32(hw, B0_IMSK);
2071
cd28ab6a
SH		 2072 return IRQ_HANDLED;
2073}
2074
2075#ifdef CONFIG_NET_POLL_CONTROLLER
2076static void sky2_netpoll(struct net_device *dev)
2077{
2078 struct sky2_port *sky2 = netdev_priv(dev);
2079
793b883e 2080 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 2081}
2082#endif
2083
2084/* Chip internal frequency for clock calculations */
fb17358f 2085static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2086{
793b883e 2087 switch (hw->chip_id) {
cd28ab6a 2088 case CHIP_ID_YUKON_EC:
5a5b1ea0 2089 case CHIP_ID_YUKON_EC_U:
fb17358f 2090 return 125; /* 125 Mhz */
cd28ab6a 2091 case CHIP_ID_YUKON_FE:
fb17358f 2092 return 100; /* 100 Mhz */
793b883e 2093 default: /* YUKON_XL */
fb17358f 2094 return 156; /* 156 Mhz */
cd28ab6a
SH		 2095 }
2096}
2097
fb17358f 2098static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2099{
fb17358f 2100 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2101}
2102
fb17358f 2103static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2104{
fb17358f 2105 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2106}
2107
fb17358f 2108
cd28ab6a
SH		 2109static int sky2_reset(struct sky2_hw *hw)
2110{
5afa0a9c 2111 u32 ctst;
cd28ab6a
SH		 2112 u16 status;
2113 u8 t8, pmd_type;
2114 int i;
2115
2116 ctst = sky2_read32(hw, B0_CTST);
2117
2118 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2119 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2120 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2121 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2122 pci_name(hw->pdev), hw->chip_id);
2123 return -EOPNOTSUPP;
2124 }
2125
793b883e
SH		 2126 /* ring for status responses */
2127 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
2128 &hw->st_dma);
2129 if (!hw->st_le)
2130 return -ENOMEM;
2131
cd28ab6a
SH		 2132 /* disable ASF */
2133 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2134 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2135 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2136 }
2137
2138 /* do a SW reset */
2139 sky2_write8(hw, B0_CTST, CS_RST_SET);
2140 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2141
2142 /* clear PCI errors, if any */
793b883e 2143 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
cd28ab6a 2144 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 2145 pci_write_config_word(hw->pdev, PCI_STATUS,
2146 status | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2147
2148 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2149
2150 /* clear any PEX errors */
2151 if (is_pciex(hw)) {
793b883e
SH		 2152 u16 lstat;
2153 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2154 0xffffffffUL);
2155 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
cd28ab6a
SH		 2156 }
2157
2158 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2159 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2160
2161 hw->ports = 1;
2162 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2163 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2164 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2165 ++hw->ports;
2166 }
2167 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2168
5afa0a9c 2169 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2170
2171 for (i = 0; i < hw->ports; i++) {
2172 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2173 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2174 }
2175
2176 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2177
793b883e
SH		 2178 /* Clear I2C IRQ noise */
2179 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2180
2181 /* turn off hardware timer (unused) */
2182 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2183 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2184
cd28ab6a
SH		 2185 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2186
69634ee7
SH		 2187 /* Turn off descriptor polling */
2188 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2189
2190 /* Turn off receive timestamp */
2191 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2192 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2193
2194 /* enable the Tx Arbiters */
2195 for (i = 0; i < hw->ports; i++)
2196 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2197
2198 /* Initialize ram interface */
2199 for (i = 0; i < hw->ports; i++) {
793b883e 2200 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2201
2202 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2203 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2204 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2205 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2206 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2207 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2208 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2209 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2210 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2211 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2212 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2213 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2214 }
2215
cd28ab6a
SH		 2216 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2217
cd28ab6a
SH		 2218 for (i = 0; i < hw->ports; i++)
2219 sky2_phy_reset(hw, i);
cd28ab6a 2220
cd28ab6a
SH		 2221 memset(hw->st_le, 0, STATUS_LE_BYTES);
2222 hw->st_idx = 0;
2223
2224 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2225 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2226
2227 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2228 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2229
2230 /* Set the list last index */
793b883e 2231 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2232
793b883e 2233 /* These status setup values are copied from SysKonnect's driver */
cd28ab6a
SH		 2234 if (is_ec_a1(hw)) {
2235 /* WA for dev. #4.3 */
793b883e 2236 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
cd28ab6a
SH		 2237
2238 /* set Status-FIFO watermark */
2239 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2240
2241 /* set Status-FIFO ISR watermark */
793b883e 2242 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
69634ee7 2243 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
cd28ab6a 2244 } else {
69634ee7
SH		 2245 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2246 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a
SH		 2247
2248 /* set Status-FIFO ISR watermark */
2249 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
69634ee7
SH		 2250 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2251 else
2252 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2253
69634ee7
SH		 2254 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2255 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2256 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
cd28ab6a
SH		 2257 }
2258
793b883e 2259 /* enable status unit */
cd28ab6a
SH		 2260 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2261
2262 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2263 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2264 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2265
2266 return 0;
2267}
2268
2269static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2270{
2271 u32 modes;
2272 if (hw->copper) {
793b883e
SH		 2273 modes = SUPPORTED_10baseT_Half
2274 | SUPPORTED_10baseT_Full
2275 | SUPPORTED_100baseT_Half
2276 | SUPPORTED_100baseT_Full
2277 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2278
2279 if (hw->chip_id != CHIP_ID_YUKON_FE)
2280 modes |= SUPPORTED_1000baseT_Half
793b883e 2281 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2282 } else
2283 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2284 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2285 return modes;
2286}
2287
793b883e 2288static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2289{
2290 struct sky2_port *sky2 = netdev_priv(dev);
2291 struct sky2_hw *hw = sky2->hw;
2292
2293 ecmd->transceiver = XCVR_INTERNAL;
2294 ecmd->supported = sky2_supported_modes(hw);
2295 ecmd->phy_address = PHY_ADDR_MARV;
2296 if (hw->copper) {
2297 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2298 | SUPPORTED_10baseT_Full
2299 | SUPPORTED_100baseT_Half
2300 | SUPPORTED_100baseT_Full
2301 | SUPPORTED_1000baseT_Half
2302 | SUPPORTED_1000baseT_Full
2303 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2304 ecmd->port = PORT_TP;
2305 } else
2306 ecmd->port = PORT_FIBRE;
2307
2308 ecmd->advertising = sky2->advertising;
2309 ecmd->autoneg = sky2->autoneg;
2310 ecmd->speed = sky2->speed;
2311 ecmd->duplex = sky2->duplex;
2312 return 0;
2313}
2314
2315static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2316{
2317 struct sky2_port *sky2 = netdev_priv(dev);
2318 const struct sky2_hw *hw = sky2->hw;
2319 u32 supported = sky2_supported_modes(hw);
2320
2321 if (ecmd->autoneg == AUTONEG_ENABLE) {
2322 ecmd->advertising = supported;
2323 sky2->duplex = -1;
2324 sky2->speed = -1;
2325 } else {
2326 u32 setting;
2327
793b883e 2328 switch (ecmd->speed) {
cd28ab6a
SH		 2329 case SPEED_1000:
2330 if (ecmd->duplex == DUPLEX_FULL)
2331 setting = SUPPORTED_1000baseT_Full;
2332 else if (ecmd->duplex == DUPLEX_HALF)
2333 setting = SUPPORTED_1000baseT_Half;
2334 else
2335 return -EINVAL;
2336 break;
2337 case SPEED_100:
2338 if (ecmd->duplex == DUPLEX_FULL)
2339 setting = SUPPORTED_100baseT_Full;
2340 else if (ecmd->duplex == DUPLEX_HALF)
2341 setting = SUPPORTED_100baseT_Half;
2342 else
2343 return -EINVAL;
2344 break;
2345
2346 case SPEED_10:
2347 if (ecmd->duplex == DUPLEX_FULL)
2348 setting = SUPPORTED_10baseT_Full;
2349 else if (ecmd->duplex == DUPLEX_HALF)
2350 setting = SUPPORTED_10baseT_Half;
2351 else
2352 return -EINVAL;
2353 break;
2354 default:
2355 return -EINVAL;
2356 }
2357
2358 if ((setting & supported) == 0)
2359 return -EINVAL;
2360
2361 sky2->speed = ecmd->speed;
2362 sky2->duplex = ecmd->duplex;
2363 }
2364
2365 sky2->autoneg = ecmd->autoneg;
2366 sky2->advertising = ecmd->advertising;
2367
1b537565
SH		 2368 if (netif_running(dev))
2369 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2370
2371 return 0;
2372}
2373
2374static void sky2_get_drvinfo(struct net_device *dev,
2375 struct ethtool_drvinfo *info)
2376{
2377 struct sky2_port *sky2 = netdev_priv(dev);
2378
2379 strcpy(info->driver, DRV_NAME);
2380 strcpy(info->version, DRV_VERSION);
2381 strcpy(info->fw_version, "N/A");
2382 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2383}
2384
2385static const struct sky2_stat {
793b883e
SH		 2386 char name[ETH_GSTRING_LEN];
2387 u16 offset;
cd28ab6a
SH		 2388} sky2_stats[] = {
2389 { "tx_bytes", GM_TXO_OK_HI },
2390 { "rx_bytes", GM_RXO_OK_HI },
2391 { "tx_broadcast", GM_TXF_BC_OK },
2392 { "rx_broadcast", GM_RXF_BC_OK },
2393 { "tx_multicast", GM_TXF_MC_OK },
2394 { "rx_multicast", GM_RXF_MC_OK },
2395 { "tx_unicast", GM_TXF_UC_OK },
2396 { "rx_unicast", GM_RXF_UC_OK },
2397 { "tx_mac_pause", GM_TXF_MPAUSE },
2398 { "rx_mac_pause", GM_RXF_MPAUSE },
2399 { "collisions", GM_TXF_SNG_COL },
2400 { "late_collision",GM_TXF_LAT_COL },
2401 { "aborted", GM_TXF_ABO_COL },
2402 { "multi_collisions", GM_TXF_MUL_COL },
2403 { "fifo_underrun", GM_TXE_FIFO_UR },
2404 { "fifo_overflow", GM_RXE_FIFO_OV },
2405 { "rx_toolong", GM_RXF_LNG_ERR },
2406 { "rx_jabber", GM_RXF_JAB_PKT },
2407 { "rx_runt", GM_RXE_FRAG },
2408 { "rx_too_long", GM_RXF_LNG_ERR },
2409 { "rx_fcs_error", GM_RXF_FCS_ERR },
2410};
2411
cd28ab6a
SH		 2412static u32 sky2_get_rx_csum(struct net_device *dev)
2413{
2414 struct sky2_port *sky2 = netdev_priv(dev);
2415
2416 return sky2->rx_csum;
2417}
2418
2419static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2420{
2421 struct sky2_port *sky2 = netdev_priv(dev);
2422
2423 sky2->rx_csum = data;
793b883e 2424
cd28ab6a
SH		 2425 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2426 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2427
2428 return 0;
2429}
2430
2431static u32 sky2_get_msglevel(struct net_device *netdev)
2432{
2433 struct sky2_port *sky2 = netdev_priv(netdev);
2434 return sky2->msg_enable;
2435}
2436
9a7ae0a9
SH		 2437static int sky2_nway_reset(struct net_device *dev)
2438{
2439 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2440
2441 if (sky2->autoneg != AUTONEG_ENABLE)
2442 return -EINVAL;
2443
1b537565 2444 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2445
2446 return 0;
2447}
2448
793b883e 2449static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2450{
2451 struct sky2_hw *hw = sky2->hw;
2452 unsigned port = sky2->port;
2453 int i;
2454
2455 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2456 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2457 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2458 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2459
793b883e 2460 for (i = 2; i < count; i++)
cd28ab6a
SH		 2461 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2462}
2463
cd28ab6a
SH		 2464static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2465{
2466 struct sky2_port *sky2 = netdev_priv(netdev);
2467 sky2->msg_enable = value;
2468}
2469
2470static int sky2_get_stats_count(struct net_device *dev)
2471{
2472 return ARRAY_SIZE(sky2_stats);
2473}
2474
2475static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2476 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2477{
2478 struct sky2_port *sky2 = netdev_priv(dev);
2479
793b883e 2480 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2481}
2482
793b883e 2483static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2484{
2485 int i;
2486
2487 switch (stringset) {
2488 case ETH_SS_STATS:
2489 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2490 memcpy(data + i * ETH_GSTRING_LEN,
2491 sky2_stats[i].name, ETH_GSTRING_LEN);
2492 break;
2493 }
2494}
2495
2496/* Use hardware MIB variables for critical path statistics and
2497 * transmit feedback not reported at interrupt.
2498 * Other errors are accounted for in interrupt handler.
2499 */
2500static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2501{
2502 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2503 u64 data[13];
cd28ab6a 2504
793b883e 2505 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2506
2507 sky2->net_stats.tx_bytes = data[0];
2508 sky2->net_stats.rx_bytes = data[1];
2509 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2510 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2511 sky2->net_stats.multicast = data[5] + data[7];
2512 sky2->net_stats.collisions = data[10];
2513 sky2->net_stats.tx_aborted_errors = data[12];
2514
2515 return &sky2->net_stats;
2516}
2517
2518static int sky2_set_mac_address(struct net_device *dev, void *p)
2519{
2520 struct sky2_port *sky2 = netdev_priv(dev);
2521 struct sockaddr *addr = p;
cd28ab6a
SH		 2522
2523 if (!is_valid_ether_addr(addr->sa_data))
2524 return -EADDRNOTAVAIL;
2525
cd28ab6a 2526 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
793b883e 2527 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
cd28ab6a 2528 dev->dev_addr, ETH_ALEN);
793b883e 2529 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
cd28ab6a 2530 dev->dev_addr, ETH_ALEN);
1b537565
SH		 2531
2532 if (netif_running(dev))
2533 sky2_phy_reinit(sky2);
2534
2535 return 0;
cd28ab6a
SH		 2536}
2537
2538static void sky2_set_multicast(struct net_device *dev)
2539{
2540 struct sky2_port *sky2 = netdev_priv(dev);
2541 struct sky2_hw *hw = sky2->hw;
2542 unsigned port = sky2->port;
2543 struct dev_mc_list *list = dev->mc_list;
2544 u16 reg;
2545 u8 filter[8];
2546
2547 memset(filter, 0, sizeof(filter));
2548
2549 reg = gma_read16(hw, port, GM_RX_CTRL);
2550 reg |= GM_RXCR_UCF_ENA;
2551
d571b694 2552 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2553 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2554 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2555 memset(filter, 0xff, sizeof(filter));
793b883e 2556 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2557 reg &= ~GM_RXCR_MCF_ENA;
2558 else {
2559 int i;
2560 reg |= GM_RXCR_MCF_ENA;
2561
2562 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2563 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2564 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2565 }
2566 }
2567
cd28ab6a 2568 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2569 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2570 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2571 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2572 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2573 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2574 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2575 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2576
2577 gma_write16(hw, port, GM_RX_CTRL, reg);
2578}
2579
2580/* Can have one global because blinking is controlled by
2581 * ethtool and that is always under RTNL mutex
2582 */
91c86df5 2583static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2584{
793b883e
SH		 2585 u16 pg;
2586
793b883e
SH		 2587 switch (hw->chip_id) {
2588 case CHIP_ID_YUKON_XL:
2589 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2590 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2591 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2592 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2593 PHY_M_LEDC_INIT_CTRL(7) |
2594 PHY_M_LEDC_STA1_CTRL(7) |
2595 PHY_M_LEDC_STA0_CTRL(7))
2596 : 0);
2597
2598 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2599 break;
2600
2601 default:
2602 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2603 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2604 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2605 PHY_M_LED_MO_10(MO_LED_ON) |
2606 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2607 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2608 PHY_M_LED_MO_RX(MO_LED_ON)
2609 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2610 PHY_M_LED_MO_10(MO_LED_OFF) |
2611 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2612 PHY_M_LED_MO_1000(MO_LED_OFF) |
2613 PHY_M_LED_MO_RX(MO_LED_OFF));
2614
793b883e 2615 }
cd28ab6a
SH		 2616}
2617
2618/* blink LED's for finding board */
2619static int sky2_phys_id(struct net_device *dev, u32 data)
2620{
2621 struct sky2_port *sky2 = netdev_priv(dev);
2622 struct sky2_hw *hw = sky2->hw;
2623 unsigned port = sky2->port;
793b883e 2624 u16 ledctrl, ledover = 0;
cd28ab6a 2625 long ms;
91c86df5 2626 int interrupted;
cd28ab6a
SH		 2627 int onoff = 1;
2628
793b883e 2629 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2630 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2631 else
2632 ms = data * 1000;
2633
2634 /* save initial values */
91c86df5 2635 down(&sky2->phy_sema);
793b883e
SH		 2636 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2637 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2638 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2639 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2640 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2641 } else {
2642 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2643 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2644 }
cd28ab6a 2645
91c86df5
SH		 2646 interrupted = 0;
2647 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2648 sky2_led(hw, port, onoff);
2649 onoff = !onoff;
2650
91c86df5
SH		 2651 up(&sky2->phy_sema);
2652 interrupted = msleep_interruptible(250);
2653 down(&sky2->phy_sema);
2654
cd28ab6a
SH		 2655 ms -= 250;
2656 }
2657
2658 /* resume regularly scheduled programming */
793b883e
SH		 2659 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2660 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2661 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2662 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2663 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2664 } else {
2665 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2666 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2667 }
91c86df5 2668 up(&sky2->phy_sema);
cd28ab6a
SH		 2669
2670 return 0;
2671}
2672
2673static void sky2_get_pauseparam(struct net_device *dev,
2674 struct ethtool_pauseparam *ecmd)
2675{
2676 struct sky2_port *sky2 = netdev_priv(dev);
2677
2678 ecmd->tx_pause = sky2->tx_pause;
2679 ecmd->rx_pause = sky2->rx_pause;
2680 ecmd->autoneg = sky2->autoneg;
2681}
2682
2683static int sky2_set_pauseparam(struct net_device *dev,
2684 struct ethtool_pauseparam *ecmd)
2685{
2686 struct sky2_port *sky2 = netdev_priv(dev);
2687 int err = 0;
2688
2689 sky2->autoneg = ecmd->autoneg;
2690 sky2->tx_pause = ecmd->tx_pause != 0;
2691 sky2->rx_pause = ecmd->rx_pause != 0;
2692
1b537565 2693 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2694
2695 return err;
2696}
2697
2698#ifdef CONFIG_PM
2699static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2700{
2701 struct sky2_port *sky2 = netdev_priv(dev);
2702
2703 wol->supported = WAKE_MAGIC;
2704 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2705}
2706
2707static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2708{
2709 struct sky2_port *sky2 = netdev_priv(dev);
2710 struct sky2_hw *hw = sky2->hw;
2711
2712 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2713 return -EOPNOTSUPP;
2714
2715 sky2->wol = wol->wolopts == WAKE_MAGIC;
2716
2717 if (sky2->wol) {
2718 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2719
2720 sky2_write16(hw, WOL_CTRL_STAT,
2721 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2722 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2723 } else
2724 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2725
2726 return 0;
2727}
2728#endif
2729
fb17358f
SH		 2730static int sky2_get_coalesce(struct net_device *dev,
2731 struct ethtool_coalesce *ecmd)
2732{
2733 struct sky2_port *sky2 = netdev_priv(dev);
2734 struct sky2_hw *hw = sky2->hw;
2735
2736 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2737 ecmd->tx_coalesce_usecs = 0;
2738 else {
2739 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2740 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2741 }
2742 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2743
2744 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2745 ecmd->rx_coalesce_usecs = 0;
2746 else {
2747 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2748 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2749 }
2750 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2751
2752 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2753 ecmd->rx_coalesce_usecs_irq = 0;
2754 else {
2755 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2756 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2757 }
2758
2759 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2760
2761 return 0;
2762}
2763
2764/* Note: this affect both ports */
2765static int sky2_set_coalesce(struct net_device *dev,
2766 struct ethtool_coalesce *ecmd)
2767{
2768 struct sky2_port *sky2 = netdev_priv(dev);
2769 struct sky2_hw *hw = sky2->hw;
2770 const u32 tmin = sky2_clk2us(hw, 1);
2771 const u32 tmax = 5000;
2772
2773 if (ecmd->tx_coalesce_usecs != 0 &&
2774 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2775 return -EINVAL;
2776
2777 if (ecmd->rx_coalesce_usecs != 0 &&
2778 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2779 return -EINVAL;
2780
2781 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2782 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2783 return -EINVAL;
2784
2785 if (ecmd->tx_max_coalesced_frames > 0xffff)
2786 return -EINVAL;
2787 if (ecmd->rx_max_coalesced_frames > 0xff)
2788 return -EINVAL;
2789 if (ecmd->rx_max_coalesced_frames_irq > 0xff)
2790 return -EINVAL;
2791
2792 if (ecmd->tx_coalesce_usecs == 0)
2793 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2794 else {
2795 sky2_write32(hw, STAT_TX_TIMER_INI,
2796 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2797 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2798 }
2799 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2800
2801 if (ecmd->rx_coalesce_usecs == 0)
2802 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2803 else {
2804 sky2_write32(hw, STAT_LEV_TIMER_INI,
2805 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2806 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2807 }
2808 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2809
2810 if (ecmd->rx_coalesce_usecs_irq == 0)
2811 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2812 else {
2813 sky2_write32(hw, STAT_TX_TIMER_INI,
2814 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2815 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2816 }
2817 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2818 return 0;
2819}
2820
793b883e
SH		 2821static void sky2_get_ringparam(struct net_device *dev,
2822 struct ethtool_ringparam *ering)
2823{
2824 struct sky2_port *sky2 = netdev_priv(dev);
2825
2826 ering->rx_max_pending = RX_MAX_PENDING;
2827 ering->rx_mini_max_pending = 0;
2828 ering->rx_jumbo_max_pending = 0;
2829 ering->tx_max_pending = TX_RING_SIZE - 1;
2830
2831 ering->rx_pending = sky2->rx_pending;
2832 ering->rx_mini_pending = 0;
2833 ering->rx_jumbo_pending = 0;
2834 ering->tx_pending = sky2->tx_pending;
2835}
2836
2837static int sky2_set_ringparam(struct net_device *dev,
2838 struct ethtool_ringparam *ering)
2839{
2840 struct sky2_port *sky2 = netdev_priv(dev);
2841 int err = 0;
2842
2843 if (ering->rx_pending > RX_MAX_PENDING ||
2844 ering->rx_pending < 8 ||
2845 ering->tx_pending < MAX_SKB_TX_LE ||
2846 ering->tx_pending > TX_RING_SIZE - 1)
2847 return -EINVAL;
2848
2849 if (netif_running(dev))
2850 sky2_down(dev);
2851
2852 sky2->rx_pending = ering->rx_pending;
2853 sky2->tx_pending = ering->tx_pending;
2854
1b537565 2855 if (netif_running(dev)) {
793b883e 2856 err = sky2_up(dev);
1b537565
SH		 2857 if (err)
2858 dev_close(dev);
6ed995bb
SH		 2859 else
2860 sky2_set_multicast(dev);
1b537565 2861 }
793b883e
SH		 2862
2863 return err;
2864}
2865
793b883e
SH		 2866static int sky2_get_regs_len(struct net_device *dev)
2867{
6e4cbb34 2868 return 0x4000;
793b883e
SH		 2869}
2870
2871/*
2872 * Returns copy of control register region
6e4cbb34 2873 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2874 */
2875static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2876 void *p)
2877{
2878 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2879 const void __iomem *io = sky2->hw->regs;
793b883e 2880
6e4cbb34 2881 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 2882 regs->version = 1;
6e4cbb34 2883 memset(p, 0, regs->len);
793b883e 2884
6e4cbb34
SH		 2885 memcpy_fromio(p, io, B3_RAM_ADDR);
2886
2887 memcpy_fromio(p + B3_RI_WTO_R1,
2888 io + B3_RI_WTO_R1,
2889 regs->len - B3_RI_WTO_R1);
793b883e 2890}
cd28ab6a
SH		 2891
2892static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 2893 .get_settings = sky2_get_settings,
2894 .set_settings = sky2_set_settings,
2895 .get_drvinfo = sky2_get_drvinfo,
2896 .get_msglevel = sky2_get_msglevel,
2897 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 2898 .nway_reset = sky2_nway_reset,
793b883e
SH		 2899 .get_regs_len = sky2_get_regs_len,
2900 .get_regs = sky2_get_regs,
2901 .get_link = ethtool_op_get_link,
2902 .get_sg = ethtool_op_get_sg,
2903 .set_sg = ethtool_op_set_sg,
2904 .get_tx_csum = ethtool_op_get_tx_csum,
2905 .set_tx_csum = ethtool_op_set_tx_csum,
2906 .get_tso = ethtool_op_get_tso,
2907 .set_tso = ethtool_op_set_tso,
2908 .get_rx_csum = sky2_get_rx_csum,
2909 .set_rx_csum = sky2_set_rx_csum,
2910 .get_strings = sky2_get_strings,
fb17358f
SH		 2911 .get_coalesce = sky2_get_coalesce,
2912 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 2913 .get_ringparam = sky2_get_ringparam,
2914 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 2915 .get_pauseparam = sky2_get_pauseparam,
2916 .set_pauseparam = sky2_set_pauseparam,
2917#ifdef CONFIG_PM
793b883e
SH		 2918 .get_wol = sky2_get_wol,
2919 .set_wol = sky2_set_wol,
cd28ab6a 2920#endif
793b883e 2921 .phys_id = sky2_phys_id,
cd28ab6a
SH		 2922 .get_stats_count = sky2_get_stats_count,
2923 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 2924 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 2925};
2926
2927/* Initialize network device */
2928static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2929 unsigned port, int highmem)
2930{
2931 struct sky2_port *sky2;
2932 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2933
2934 if (!dev) {
2935 printk(KERN_ERR "sky2 etherdev alloc failed");
2936 return NULL;
2937 }
2938
2939 SET_MODULE_OWNER(dev);
2940 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 2941 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 2942 dev->open = sky2_up;
2943 dev->stop = sky2_down;
ef743d33 2944 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 2945 dev->hard_start_xmit = sky2_xmit_frame;
2946 dev->get_stats = sky2_get_stats;
2947 dev->set_multicast_list = sky2_set_multicast;
2948 dev->set_mac_address = sky2_set_mac_address;
2949 dev->change_mtu = sky2_change_mtu;
2950 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2951 dev->tx_timeout = sky2_tx_timeout;
2952 dev->watchdog_timeo = TX_WATCHDOG;
2953 if (port == 0)
2954 dev->poll = sky2_poll;
2955 dev->weight = NAPI_WEIGHT;
2956#ifdef CONFIG_NET_POLL_CONTROLLER
2957 dev->poll_controller = sky2_netpoll;
2958#endif
cd28ab6a
SH		 2959
2960 sky2 = netdev_priv(dev);
2961 sky2->netdev = dev;
2962 sky2->hw = hw;
2963 sky2->msg_enable = netif_msg_init(debug, default_msg);
2964
2965 spin_lock_init(&sky2->tx_lock);
2966 /* Auto speed and flow control */
2967 sky2->autoneg = AUTONEG_ENABLE;
585b5601 2968 sky2->tx_pause = 1;
cd28ab6a
SH		 2969 sky2->rx_pause = 1;
2970 sky2->duplex = -1;
2971 sky2->speed = -1;
2972 sky2->advertising = sky2_supported_modes(hw);
75d070c5
SH		 2973
2974 /* Receive checksum disabled for Yukon XL
2975 * because of observed problems with incorrect
2976 * values when multiple packets are received in one interrupt
2977 */
2978 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
2979
91c86df5
SH		 2980 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
2981 init_MUTEX(&sky2->phy_sema);
793b883e
SH		 2982 sky2->tx_pending = TX_DEF_PENDING;
2983 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
734d1868 2984 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 2985
2986 hw->dev[port] = dev;
2987
2988 sky2->port = port;
2989
5a5b1ea0
SH		 2990 dev->features |= NETIF_F_LLTX;
2991 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
2992 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 2993 if (highmem)
2994 dev->features |= NETIF_F_HIGHDMA;
793b883e 2995 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 2996
d1f13708
SH		 2997#ifdef SKY2_VLAN_TAG_USED
2998 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2999 dev->vlan_rx_register = sky2_vlan_rx_register;
3000 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3001#endif
3002
cd28ab6a 3003 /* read the mac address */
793b883e 3004 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3005 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3006
3007 /* device is off until link detection */
3008 netif_carrier_off(dev);
3009 netif_stop_queue(dev);
3010
3011 return dev;
3012}
3013
3014static inline void sky2_show_addr(struct net_device *dev)
3015{
3016 const struct sky2_port *sky2 = netdev_priv(dev);
3017
3018 if (netif_msg_probe(sky2))
3019 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3020 dev->name,
3021 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3022 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3023}
3024
3025static int __devinit sky2_probe(struct pci_dev *pdev,
3026 const struct pci_device_id *ent)
3027{
793b883e 3028 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3029 struct sky2_hw *hw;
5afa0a9c 3030 int err, pm_cap, using_dac = 0;
cd28ab6a 3031
793b883e
SH		 3032 err = pci_enable_device(pdev);
3033 if (err) {
cd28ab6a
SH		 3034 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3035 pci_name(pdev));
3036 goto err_out;
3037 }
3038
793b883e
SH		 3039 err = pci_request_regions(pdev, DRV_NAME);
3040 if (err) {
cd28ab6a
SH		 3041 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3042 pci_name(pdev));
793b883e 3043 goto err_out;
cd28ab6a
SH		 3044 }
3045
3046 pci_set_master(pdev);
3047
5afa0a9c
SH		 3048 /* Find power-management capability. */
3049 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3050 if (pm_cap == 0) {
3051 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3052 "aborting.\n");
3053 err = -EIO;
3054 goto err_out_free_regions;
3055 }
3056
d1f3d4dd
SH		 3057 if (sizeof(dma_addr_t) > sizeof(u32) &&
3058 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3059 using_dac = 1;
3060 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3061 if (err < 0) {
3062 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3063 "for consistent allocations\n", pci_name(pdev));
3064 goto err_out_free_regions;
3065 }
cd28ab6a 3066
d1f3d4dd 3067 } else {
cd28ab6a
SH		 3068 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3069 if (err) {
3070 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3071 pci_name(pdev));
3072 goto err_out_free_regions;
3073 }
3074 }
d1f3d4dd 3075
cd28ab6a 3076#ifdef __BIG_ENDIAN
d571b694 3077 /* byte swap descriptors in hardware */
cd28ab6a
SH		 3078 {
3079 u32 reg;
3080
3081 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3082 reg |= PCI_REV_DESC;
3083 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3084 }
3085#endif
3086
3087 err = -ENOMEM;
3088 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3089 if (!hw) {
3090 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3091 pci_name(pdev));
3092 goto err_out_free_regions;
3093 }
3094
3095 memset(hw, 0, sizeof(*hw));
3096 hw->pdev = pdev;
cd28ab6a
SH		 3097
3098 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3099 if (!hw->regs) {
3100 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3101 pci_name(pdev));
3102 goto err_out_free_hw;
3103 }
5afa0a9c 3104 hw->pm_cap = pm_cap;
cd28ab6a 3105
cd28ab6a
SH		 3106 err = sky2_reset(hw);
3107 if (err)
793b883e 3108 goto err_out_iounmap;
cd28ab6a 3109
5f4f9dc1
SH		 3110 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3111 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
92f965e8 3112 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3113 hw->chip_id, hw->chip_rev);
cd28ab6a 3114
793b883e
SH		 3115 dev = sky2_init_netdev(hw, 0, using_dac);
3116 if (!dev)
cd28ab6a
SH		 3117 goto err_out_free_pci;
3118
793b883e
SH		 3119 err = register_netdev(dev);
3120 if (err) {
cd28ab6a
SH		 3121 printk(KERN_ERR PFX "%s: cannot register net device\n",
3122 pci_name(pdev));
3123 goto err_out_free_netdev;
3124 }
3125
3126 sky2_show_addr(dev);
3127
3128 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3129 if (register_netdev(dev1) == 0)
3130 sky2_show_addr(dev1);
3131 else {
3132 /* Failure to register second port need not be fatal */
793b883e
SH		 3133 printk(KERN_WARNING PFX
3134 "register of second port failed\n");
cd28ab6a
SH		 3135 hw->dev[1] = NULL;
3136 free_netdev(dev1);
3137 }
3138 }
3139
793b883e
SH		 3140 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3141 if (err) {
3142 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3143 pci_name(pdev), pdev->irq);
3144 goto err_out_unregister;
3145 }
3146
3147 hw->intr_mask = Y2_IS_BASE;
3148 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3149
3150 pci_set_drvdata(pdev, hw);
3151
cd28ab6a
SH		 3152 return 0;
3153
793b883e
SH		 3154err_out_unregister:
3155 if (dev1) {
3156 unregister_netdev(dev1);
3157 free_netdev(dev1);
3158 }
3159 unregister_netdev(dev);
cd28ab6a
SH		 3160err_out_free_netdev:
3161 free_netdev(dev);
cd28ab6a 3162err_out_free_pci:
793b883e 3163 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3164 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3165err_out_iounmap:
3166 iounmap(hw->regs);
3167err_out_free_hw:
3168 kfree(hw);
3169err_out_free_regions:
3170 pci_release_regions(pdev);
cd28ab6a 3171 pci_disable_device(pdev);
cd28ab6a
SH		 3172err_out:
3173 return err;
3174}
3175
3176static void __devexit sky2_remove(struct pci_dev *pdev)
3177{
793b883e 3178 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3179 struct net_device *dev0, *dev1;
3180
793b883e 3181 if (!hw)
cd28ab6a
SH		 3182 return;
3183
cd28ab6a 3184 dev0 = hw->dev[0];
793b883e
SH		 3185 dev1 = hw->dev[1];
3186 if (dev1)
3187 unregister_netdev(dev1);
cd28ab6a
SH		 3188 unregister_netdev(dev0);
3189
793b883e 3190 sky2_write32(hw, B0_IMSK, 0);
5afa0a9c 3191 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3192 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3193 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3194 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3195
3196 free_irq(pdev->irq, hw);
793b883e 3197 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3198 pci_release_regions(pdev);
3199 pci_disable_device(pdev);
793b883e 3200
cd28ab6a
SH		 3201 if (dev1)
3202 free_netdev(dev1);
3203 free_netdev(dev0);
3204 iounmap(hw->regs);
3205 kfree(hw);
5afa0a9c 3206
cd28ab6a
SH		 3207 pci_set_drvdata(pdev, NULL);
3208}
3209
3210#ifdef CONFIG_PM
3211static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3212{
793b883e 3213 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3214 int i;
cd28ab6a
SH		 3215
3216 for (i = 0; i < 2; i++) {
3217 struct net_device *dev = hw->dev[i];
3218
3219 if (dev) {
5afa0a9c
SH		 3220 if (!netif_running(dev))
3221 continue;
3222
3223 sky2_down(dev);
cd28ab6a 3224 netif_device_detach(dev);
cd28ab6a
SH		 3225 }
3226 }
3227
5afa0a9c 3228 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 3229}
3230
3231static int sky2_resume(struct pci_dev *pdev)
3232{
793b883e 3233 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3234 int i;
3235
cd28ab6a
SH		 3236 pci_restore_state(pdev);
3237 pci_enable_wake(pdev, PCI_D0, 0);
5afa0a9c 3238 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 3239
3240 sky2_reset(hw);
3241
3242 for (i = 0; i < 2; i++) {
3243 struct net_device *dev = hw->dev[i];
3244 if (dev) {
5afa0a9c
SH		 3245 if (netif_running(dev)) {
3246 netif_device_attach(dev);
1b537565
SH		 3247 if (sky2_up(dev))
3248 dev_close(dev);
5afa0a9c 3249 }
cd28ab6a
SH		 3250 }
3251 }
3252 return 0;
3253}
3254#endif
3255
3256static struct pci_driver sky2_driver = {
793b883e
SH		 3257 .name = DRV_NAME,
3258 .id_table = sky2_id_table,
3259 .probe = sky2_probe,
3260 .remove = __devexit_p(sky2_remove),
cd28ab6a 3261#ifdef CONFIG_PM
793b883e
SH		 3262 .suspend = sky2_suspend,
3263 .resume = sky2_resume,
cd28ab6a
SH		 3264#endif
3265};
3266
3267static int __init sky2_init_module(void)
3268{
50241c4c 3269 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3270}
3271
3272static void __exit sky2_cleanup_module(void)
3273{
3274 pci_unregister_driver(&sky2_driver);
3275}
3276
3277module_init(sky2_init_module);
3278module_exit(sky2_cleanup_module);
3279
3280MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3281MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3282MODULE_LICENSE("GPL");
5f4f9dc1 3283MODULE_VERSION(DRV_VERSION);
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