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sky2: support Yukon EC_U rev B1 and later
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
ada1db5c
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
793b883e 27#include <linux/crc32.h>
cd28ab6a 28#include <linux/kernel.h>
cd28ab6a
SH		 29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
c9bdd4b5 36#include <net/ip.h>
cd28ab6a
SH		 37#include <linux/tcp.h>
38#include <linux/in.h>
39#include <linux/delay.h>
91c86df5 40#include <linux/workqueue.h>
d1f13708 41#include <linux/if_vlan.h>
d70cd51a 42#include <linux/prefetch.h>
3cf26753 43#include <linux/debugfs.h>
ef743d33 44#include <linux/mii.h>
cd28ab6a
SH		 45
46#include <asm/irq.h>
47
d1f13708
SH		 48#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49#define SKY2_VLAN_TAG_USED 1
50#endif
51
cd28ab6a
SH		 52#include "sky2.h"
53
54#define DRV_NAME "sky2"
cfc0861b 55#define DRV_VERSION "1.27"
cd28ab6a
SH		 56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 67
ee5f68fe 68/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 69 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
70#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 71#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
ee5f68fe
SH		 72#define TX_MAX_PENDING 4096
73#define TX_DEF_PENDING 127
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 77#define TX_WATCHDOG (5 * HZ)
78#define NAPI_WEIGHT 64
79#define PHY_RETRIES 1000
80
f4331a6d
SH		 81#define SKY2_EEPROM_MAGIC 0x9955aabb
82
83
cb5d9547
SH		 84#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85
cd28ab6a 86static const u32 default_msg =
793b883e
SH		 87 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
88 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 89 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 90
793b883e 91static int debug = -1; /* defaults above */
cd28ab6a
SH		 92module_param(debug, int, 0);
93MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
14d0263f 95static int copybreak __read_mostly = 128;
bdb5c58e
SH		 96module_param(copybreak, int, 0);
97MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98
fb2690a9
SH		 99static int disable_msi = 0;
100module_param(disable_msi, int, 0);
101MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102
e6cac9ba 103static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 144 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 145 { 0 }
146};
793b883e 147
cd28ab6a
SH		 148MODULE_DEVICE_TABLE(pci, sky2_id_table);
149
150/* Avoid conditionals by using array */
151static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
152static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 153static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 154
d1b139c0
SH		 155static void sky2_set_multicast(struct net_device *dev);
156
af043aa5 157/* Access to PHY via serial interconnect */
ef743d33 158static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 159{
160 int i;
161
162 gma_write16(hw, port, GM_SMI_DATA, val);
163 gma_write16(hw, port, GM_SMI_CTRL,
164 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
165
166 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 167 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
168 if (ctrl == 0xffff)
169 goto io_error;
170
171 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 172 return 0;
af043aa5
SH		 173
174 udelay(10);
cd28ab6a 175 }
ef743d33 176
af043aa5 177 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 178 return -ETIMEDOUT;
af043aa5
SH		 179
180io_error:
181 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
182 return -EIO;
cd28ab6a
SH		 183}
184
ef743d33 185static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 186{
187 int i;
188
793b883e 189 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 190 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
191
192 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 193 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
194 if (ctrl == 0xffff)
195 goto io_error;
196
197 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 198 *val = gma_read16(hw, port, GM_SMI_DATA);
199 return 0;
200 }
201
af043aa5 202 udelay(10);
cd28ab6a
SH		 203 }
204
af043aa5 205 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 206 return -ETIMEDOUT;
af043aa5
SH		 207io_error:
208 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
209 return -EIO;
ef743d33
SH		 210}
211
af043aa5 212static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 213{
214 u16 v;
af043aa5 215 __gm_phy_read(hw, port, reg, &v);
ef743d33 216 return v;
cd28ab6a
SH		 217}
218
5afa0a9c 219
ae306cca
SH		 220static void sky2_power_on(struct sky2_hw *hw)
221{
222 /* switch power to VCC (WA for VAUX problem) */
223 sky2_write8(hw, B0_POWER_CTRL,
224 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 225
ae306cca
SH		 226 /* disable Core Clock Division, */
227 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 228
ae306cca
SH		 229 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
230 /* enable bits are inverted */
231 sky2_write8(hw, B2_Y2_CLK_GATE,
232 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
233 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
234 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
235 else
236 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 237
ea76e635 238 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 239 u32 reg;
5afa0a9c 240
b32f40c4 241 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 242
b32f40c4 243 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 244 /* set all bits to 0 except bits 15..12 and 8 */
245 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 247
b32f40c4 248 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 249 /* set all bits to 0 except bits 28 & 27 */
250 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 251 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 252
b32f40c4 253 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 254
5f8ae5c5 255 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
256
8f70920f
SH		 257 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
258 reg = sky2_read32(hw, B2_GP_IO);
259 reg |= GLB_GPIO_STAT_RACE_DIS;
260 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 261
262 sky2_read32(hw, B2_GP_IO);
5afa0a9c 263 }
10547ae2
SH		 264
265 /* Turn on "driver loaded" LED */
266 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 267}
5afa0a9c 268
ae306cca
SH		 269static void sky2_power_aux(struct sky2_hw *hw)
270{
271 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
272 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
273 else
274 /* enable bits are inverted */
275 sky2_write8(hw, B2_Y2_CLK_GATE,
276 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
277 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
278 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
279
c23ddf8f
SH		 280 /* switch power to VAUX if supported and PME from D3cold */
281 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
282 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 283 sky2_write8(hw, B0_POWER_CTRL,
284 (PC_VAUX_ENA | PC_VCC_ENA |
285 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 286
287 /* turn off "driver loaded LED" */
288 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c
SH		 289}
290
d3bcfbeb 291static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 292{
293 u16 reg;
294
295 /* disable all GMAC IRQ's */
296 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 297
cd28ab6a
SH		 298 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
299 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
300 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
301 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
302
303 reg = gma_read16(hw, port, GM_RX_CTRL);
304 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
305 gma_write16(hw, port, GM_RX_CTRL, reg);
306}
307
16ad91e1
SH		 308/* flow control to advertise bits */
309static const u16 copper_fc_adv[] = {
310 [FC_NONE] = 0,
311 [FC_TX] = PHY_M_AN_ASP,
312 [FC_RX] = PHY_M_AN_PC,
313 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
314};
315
316/* flow control to advertise bits when using 1000BaseX */
317static const u16 fiber_fc_adv[] = {
df3fe1f3 318 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 319 [FC_TX] = PHY_M_P_ASYM_MD_X,
320 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 321 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 322};
323
324/* flow control to GMA disable bits */
325static const u16 gm_fc_disable[] = {
326 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
327 [FC_TX] = GM_GPCR_FC_RX_DIS,
328 [FC_RX] = GM_GPCR_FC_TX_DIS,
329 [FC_BOTH] = 0,
330};
331
332
cd28ab6a
SH		 333static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
334{
335 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 336 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 337
0ea065e5 338 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 339 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 340 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
341
342 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 343 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 344 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
345
53419c68 346 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 347 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 348 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 349 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
350 else
53419c68
SH		 351 /* set master & slave downshift counter to 1x */
352 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 353
354 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
355 }
356
357 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 358 if (sky2_is_copper(hw)) {
05745c4a 359 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 360 /* enable automatic crossover */
361 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 362
363 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
364 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
365 u16 spec;
366
367 /* Enable Class A driver for FE+ A0 */
368 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
369 spec |= PHY_M_FESC_SEL_CL_A;
370 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
371 }
cd28ab6a
SH		 372 } else {
373 /* disable energy detect */
374 ctrl &= ~PHY_M_PC_EN_DET_MSK;
375
376 /* enable automatic crossover */
377 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
378
53419c68 379 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 380 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
381 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 382 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 383 ctrl &= ~PHY_M_PC_DSC_MSK;
384 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
385 }
386 }
cd28ab6a
SH		 387 } else {
388 /* workaround for deviation #4.88 (CRC errors) */
389 /* disable Automatic Crossover */
390
391 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 392 }
cd28ab6a 393
b89165f2
SH		 394 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
395
396 /* special setup for PHY 88E1112 Fiber */
ea76e635 397 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 398 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 399
b89165f2
SH		 400 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
401 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
402 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
403 ctrl &= ~PHY_M_MAC_MD_MSK;
404 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
405 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
406
407 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 408 /* select page 1 to access Fiber registers */
409 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 410
411 /* for SFP-module set SIGDET polarity to low */
412 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
413 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 414 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 415 }
b89165f2
SH		 416
417 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 418 }
419
7800fddc 420 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 421 ct1000 = 0;
422 adv = PHY_AN_CSMA;
2eaba1a2 423 reg = 0;
cd28ab6a 424
0ea065e5 425 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 426 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 427 if (sky2->advertising & ADVERTISED_1000baseT_Full)
428 ct1000 |= PHY_M_1000C_AFD;
429 if (sky2->advertising & ADVERTISED_1000baseT_Half)
430 ct1000 |= PHY_M_1000C_AHD;
431 if (sky2->advertising & ADVERTISED_100baseT_Full)
432 adv |= PHY_M_AN_100_FD;
433 if (sky2->advertising & ADVERTISED_100baseT_Half)
434 adv |= PHY_M_AN_100_HD;
435 if (sky2->advertising & ADVERTISED_10baseT_Full)
436 adv |= PHY_M_AN_10_FD;
437 if (sky2->advertising & ADVERTISED_10baseT_Half)
438 adv |= PHY_M_AN_10_HD;
709c6e7b 439
b89165f2
SH		 440 } else { /* special defines for FIBER (88E1040S only) */
441 if (sky2->advertising & ADVERTISED_1000baseT_Full)
442 adv |= PHY_M_AN_1000X_AFD;
443 if (sky2->advertising & ADVERTISED_1000baseT_Half)
444 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 445 }
cd28ab6a
SH		 446
447 /* Restart Auto-negotiation */
448 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
449 } else {
450 /* forced speed/duplex settings */
451 ct1000 = PHY_M_1000C_MSE;
452
0ea065e5
SH		 453 /* Disable auto update for duplex flow control and duplex */
454 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 455
456 switch (sky2->speed) {
457 case SPEED_1000:
458 ctrl |= PHY_CT_SP1000;
2eaba1a2 459 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 460 break;
461 case SPEED_100:
462 ctrl |= PHY_CT_SP100;
2eaba1a2 463 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 464 break;
465 }
466
2eaba1a2
SH		 467 if (sky2->duplex == DUPLEX_FULL) {
468 reg |= GM_GPCR_DUP_FULL;
469 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 470 } else if (sky2->speed < SPEED_1000)
471 sky2->flow_mode = FC_NONE;
0ea065e5 472 }
2eaba1a2 473
0ea065e5
SH		 474 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
475 if (sky2_is_copper(hw))
476 adv |= copper_fc_adv[sky2->flow_mode];
477 else
478 adv |= fiber_fc_adv[sky2->flow_mode];
479 } else {
480 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 481 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 482
483 /* Forward pause packets to GMAC? */
16ad91e1 484 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 485 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
486 else
487 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 488 }
489
2eaba1a2
SH		 490 gma_write16(hw, port, GM_GP_CTRL, reg);
491
05745c4a 492 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 493 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
494
495 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
496 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
497
498 /* Setup Phy LED's */
499 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
500 ledover = 0;
501
502 switch (hw->chip_id) {
503 case CHIP_ID_YUKON_FE:
504 /* on 88E3082 these bits are at 11..9 (shifted left) */
505 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
506
507 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
508
509 /* delete ACT LED control bits */
510 ctrl &= ~PHY_M_FELP_LED1_MSK;
511 /* change ACT LED control to blink mode */
512 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
513 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
514 break;
515
05745c4a
SH		 516 case CHIP_ID_YUKON_FE_P:
517 /* Enable Link Partner Next Page */
518 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
519 ctrl |= PHY_M_PC_ENA_LIP_NP;
520
521 /* disable Energy Detect and enable scrambler */
522 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
523 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
524
525 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
526 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
527 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
528 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
529
530 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
531 break;
532
cd28ab6a 533 case CHIP_ID_YUKON_XL:
793b883e 534 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 535
536 /* select page 3 to access LED control register */
537 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
538
539 /* set LED Function Control register */
ed6d32c7
SH		 540 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
541 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
542 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
543 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
544 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 545
546 /* set Polarity Control register */
547 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 548 (PHY_M_POLC_LS1_P_MIX(4) |
549 PHY_M_POLC_IS0_P_MIX(4) |
550 PHY_M_POLC_LOS_CTRL(2) |
551 PHY_M_POLC_INIT_CTRL(2) |
552 PHY_M_POLC_STA1_CTRL(2) |
553 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 554
555 /* restore page register */
793b883e 556 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 557 break;
93745494 558
ed6d32c7 559 case CHIP_ID_YUKON_EC_U:
93745494 560 case CHIP_ID_YUKON_EX:
ed4d4161 561 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 562 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
563
564 /* select page 3 to access LED control register */
565 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
566
567 /* set LED Function Control register */
568 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
569 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
570 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
571 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
572 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
573
574 /* set Blink Rate in LED Timer Control Register */
575 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
576 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
577 /* restore page register */
578 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
579 break;
cd28ab6a
SH		 580
581 default:
582 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
583 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 584
cd28ab6a 585 /* turn off the Rx LED (LED_RX) */
a84d0a3d 586 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 587 }
588
0ce8b98d 589 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 590 /* apply fixes in PHY AFE */
ed6d32c7
SH		 591 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
592
977bdf06 593 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 594 gm_phy_write(hw, port, 0x18, 0xaa99);
595 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 596
0ce8b98d
SH		 597 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
598 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
599 gm_phy_write(hw, port, 0x18, 0xa204);
600 gm_phy_write(hw, port, 0x17, 0x2002);
601 }
977bdf06
SH		 602
603 /* set page register to 0 */
9467a8fc 604 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 605 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
606 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
607 /* apply workaround for integrated resistors calibration */
608 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
609 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 610 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
611 /* apply fixes in PHY AFE */
612 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
613
614 /* apply RDAC termination workaround */
615 gm_phy_write(hw, port, 24, 0x2800);
616 gm_phy_write(hw, port, 23, 0x2001);
617
618 /* set page register back to 0 */
619 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 620 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
621 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 622 /* no effect on Yukon-XL */
977bdf06 623 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 624
8e95a202
JP		 625 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
626 sky2->speed == SPEED_100) {
977bdf06 627 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 628 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 629 }
cd28ab6a 630
977bdf06
SH		 631 if (ledover)
632 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
633
634 }
2eaba1a2 635
d571b694 636 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 637 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 638 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
639 else
640 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
641}
642
b96936da
SH		 643static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
644static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
645
646static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 647{
648 u32 reg1;
d3bcfbeb 649
a40ccc68 650 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 651 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 652 reg1 &= ~phy_power[port];
d3bcfbeb 653
b96936da 654 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 655 reg1 |= coma_mode[port];
656
b32f40c4 657 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 658 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 659 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 660
661 if (hw->chip_id == CHIP_ID_YUKON_FE)
662 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
663 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
664 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 665}
167f53d0 666
b96936da
SH		 667static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
668{
669 u32 reg1;
db99b988
SH		 670 u16 ctrl;
671
672 /* release GPHY Control reset */
673 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
674
675 /* release GMAC reset */
676 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
677
678 if (hw->flags & SKY2_HW_NEWER_PHY) {
679 /* select page 2 to access MAC control register */
680 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
681
682 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
683 /* allow GMII Power Down */
684 ctrl &= ~PHY_M_MAC_GMIF_PUP;
685 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
686
687 /* set page register back to 0 */
688 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
689 }
690
691 /* setup General Purpose Control Register */
692 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 693 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
694 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
695 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 696
697 if (hw->chip_id != CHIP_ID_YUKON_EC) {
698 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 699 /* select page 2 to access MAC control register */
700 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 701
e484d5f5 702 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 703 /* enable Power Down */
704 ctrl |= PHY_M_PC_POW_D_ENA;
705 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 706
707 /* set page register back to 0 */
708 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 709 }
710
711 /* set IEEE compatible Power Down Mode (dev. #4.99) */
712 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
713 }
b96936da 714
a40ccc68 715 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 716 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 717 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 718 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 719 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 720}
721
1b537565
SH		 722/* Force a renegotiation */
723static void sky2_phy_reinit(struct sky2_port *sky2)
724{
e07b1aa8 725 spin_lock_bh(&sky2->phy_lock);
1b537565 726 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 727 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 728}
729
e3173832
SH		 730/* Put device in state to listen for Wake On Lan */
731static void sky2_wol_init(struct sky2_port *sky2)
732{
733 struct sky2_hw *hw = sky2->hw;
734 unsigned port = sky2->port;
735 enum flow_control save_mode;
736 u16 ctrl;
e3173832
SH		 737
738 /* Bring hardware out of reset */
739 sky2_write16(hw, B0_CTST, CS_RST_CLR);
740 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
741
742 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
743 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
744
745 /* Force to 10/100
746 * sky2_reset will re-enable on resume
747 */
748 save_mode = sky2->flow_mode;
749 ctrl = sky2->advertising;
750
751 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
752 sky2->flow_mode = FC_NONE;
b96936da
SH		 753
754 spin_lock_bh(&sky2->phy_lock);
755 sky2_phy_power_up(hw, port);
756 sky2_phy_init(hw, port);
757 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 758
759 sky2->flow_mode = save_mode;
760 sky2->advertising = ctrl;
761
762 /* Set GMAC to no flow control and auto update for speed/duplex */
763 gma_write16(hw, port, GM_GP_CTRL,
764 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
765 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
766
767 /* Set WOL address */
768 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
769 sky2->netdev->dev_addr, ETH_ALEN);
770
771 /* Turn on appropriate WOL control bits */
772 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
773 ctrl = 0;
774 if (sky2->wol & WAKE_PHY)
775 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
776 else
777 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
778
779 if (sky2->wol & WAKE_MAGIC)
780 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
781 else
a419aef8 782 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 783
784 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
785 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
786
5f8ae5c5 787 /* Disable PiG firmware */
788 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
789
e3173832
SH		 790 /* block receiver */
791 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
e3173832
SH		 792}
793
69161611
SH		 794static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
795{
05745c4a
SH		 796 struct net_device *dev = hw->dev[port];
797
ed4d4161
SH		 798 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
799 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 800 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161 801 /* Yukon-Extreme B0 and further Extreme devices */
44dde56d 802 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
803 } else if (dev->mtu > ETH_DATA_LEN) {
804 /* set Tx GMAC FIFO Almost Empty Threshold */
805 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
806 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
05745c4a 807
44dde56d 808 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
809 } else
810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
69161611
SH		 811}
812
cd28ab6a
SH		 813static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
814{
815 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
816 u16 reg;
25cccecc 817 u32 rx_reg;
cd28ab6a
SH		 818 int i;
819 const u8 *addr = hw->dev[port]->dev_addr;
820
f350339c
SH		 821 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
822 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 823
824 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
825
793b883e 826 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 827 /* WA DEV_472 -- looks like crossed wires on port 2 */
828 /* clear GMAC 1 Control reset */
829 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
830 do {
831 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
832 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
833 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
834 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
835 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
836 }
837
793b883e 838 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 839
2eaba1a2
SH		 840 /* Enable Transmit FIFO Underrun */
841 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
842
e07b1aa8 843 spin_lock_bh(&sky2->phy_lock);
b96936da 844 sky2_phy_power_up(hw, port);
cd28ab6a 845 sky2_phy_init(hw, port);
e07b1aa8 846 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 847
848 /* MIB clear */
849 reg = gma_read16(hw, port, GM_PHY_ADDR);
850 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
851
43f2f104
SH		 852 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
853 gma_read16(hw, port, i);
cd28ab6a
SH		 854 gma_write16(hw, port, GM_PHY_ADDR, reg);
855
856 /* transmit control */
857 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
858
859 /* receive control reg: unicast + multicast + no FCS */
860 gma_write16(hw, port, GM_RX_CTRL,
793b883e 861 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 862
863 /* transmit flow control */
864 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
865
866 /* transmit parameter */
867 gma_write16(hw, port, GM_TX_PARAM,
868 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
869 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
870 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
871 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
872
873 /* serial mode register */
874 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 875 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 876
6b1a3aef 877 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 878 reg |= GM_SMOD_JUMBO_ENA;
879
c1cd0a85 880 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
881 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
882 reg |= GM_NEW_FLOW_CTRL;
883
cd28ab6a
SH		 884 gma_write16(hw, port, GM_SERIAL_MODE, reg);
885
cd28ab6a
SH		 886 /* virtual address for data */
887 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
888
793b883e
SH		 889 /* physical address: used for pause frames */
890 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
891
892 /* ignore counter overflows */
cd28ab6a
SH		 893 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
894 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
895 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
896
897 /* Configure Rx MAC FIFO */
898 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 899 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 900 if (hw->chip_id == CHIP_ID_YUKON_EX ||
901 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 902 rx_reg |= GMF_RX_OVER_ON;
69161611 903
25cccecc 904 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 905
798fdd07
SH		 906 if (hw->chip_id == CHIP_ID_YUKON_XL) {
907 /* Hardware errata - clear flush mask */
908 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
909 } else {
910 /* Flush Rx MAC FIFO on any flow control or error */
911 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
912 }
cd28ab6a 913
8df9a876 914 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 915 reg = RX_GMF_FL_THR_DEF + 1;
916 /* Another magic mystery workaround from sk98lin */
917 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
918 hw->chip_rev == CHIP_REV_YU_FE2_A0)
919 reg = 0x178;
920 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 921
922 /* Configure Tx MAC FIFO */
923 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
924 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 925
e0c28116 926 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 927 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 928 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 929 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
930 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 931 reg = 1568 / 8;
932 else
933 reg = 1024 / 8;
934 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
935 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 936
69161611 937 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 938 }
939
e970d1f8
SH		 940 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
941 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
942 /* disable dynamic watermark */
943 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
944 reg &= ~TX_DYN_WM_ENA;
945 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
946 }
cd28ab6a
SH		 947}
948
67712901
SH		 949/* Assign Ram Buffer allocation to queue */
950static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 951{
67712901
SH		 952 u32 end;
953
954 /* convert from K bytes to qwords used for hw register */
955 start *= 1024/8;
956 space *= 1024/8;
957 end = start + space - 1;
793b883e 958
cd28ab6a
SH		 959 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
960 sky2_write32(hw, RB_ADDR(q, RB_START), start);
961 sky2_write32(hw, RB_ADDR(q, RB_END), end);
962 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
963 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
964
965 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 966 u32 tp = space - space/4;
793b883e 967
1c28f6ba
SH		 968 /* On receive queue's set the thresholds
969 * give receiver priority when > 3/4 full
970 * send pause when down to 2K
971 */
972 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
973 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 974
1c28f6ba
SH		 975 tp = space - 2048/8;
976 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
977 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 978 } else {
979 /* Enable store & forward on Tx queue's because
980 * Tx FIFO is only 1K on Yukon
981 */
982 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
983 }
984
985 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 986 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 987}
988
cd28ab6a 989/* Setup Bus Memory Interface */
af4ed7e6 990static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 991{
992 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
993 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
994 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 995 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 996}
997
cd28ab6a
SH		 998/* Setup prefetch unit registers. This is the interface between
999 * hardware and driver list elements
1000 */
8cc048e3 1001static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 1002 dma_addr_t addr, u32 last)
cd28ab6a 1003{
cd28ab6a
SH		 1004 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1005 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1006 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1007 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1008 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1009 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1010
1011 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1012}
1013
9b289c33 1014static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1015{
9b289c33 1016 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1017
ee5f68fe 1018 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1019 le->ctrl = 0;
793b883e
SH		 1020 return le;
1021}
cd28ab6a 1022
88f5f0ca
SH		 1023static void tx_init(struct sky2_port *sky2)
1024{
1025 struct sky2_tx_le *le;
1026
1027 sky2->tx_prod = sky2->tx_cons = 0;
1028 sky2->tx_tcpsum = 0;
1029 sky2->tx_last_mss = 0;
1030
9b289c33 1031 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1032 le->addr = 0;
1033 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1034 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1035}
1036
290d4de5
SH		 1037/* Update chip's next pointer */
1038static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1039{
50432cb5 1040 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1041 wmb();
50432cb5
SH		 1042 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1043
1044 /* Synchronize I/O on since next processor may write to tail */
1045 mmiowb();
cd28ab6a
SH		 1046}
1047
793b883e 1048
cd28ab6a
SH		 1049static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1050{
1051 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1052 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1053 le->ctrl = 0;
cd28ab6a
SH		 1054 return le;
1055}
1056
39ef110b
MM		 1057static unsigned sky2_get_rx_threshold(struct sky2_port* sky2)
1058{
1059 unsigned size;
1060
1061 /* Space needed for frame data + headers rounded up */
1062 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1063
1064 /* Stopping point for hardware truncation */
1065 return (size - 8) / sizeof(u32);
1066}
1067
1068static unsigned sky2_get_rx_data_size(struct sky2_port* sky2)
1069{
1070 struct rx_ring_info *re;
1071 unsigned size;
1072
1073 /* Space needed for frame data + headers rounded up */
1074 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1075
1076 sky2->rx_nfrags = size >> PAGE_SHIFT;
1077 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1078
1079 /* Compute residue after pages */
1080 size -= sky2->rx_nfrags << PAGE_SHIFT;
1081
1082 /* Optimize to handle small packets and headers */
1083 if (size < copybreak)
1084 size = copybreak;
1085 if (size < ETH_HLEN)
1086 size = ETH_HLEN;
1087
1088 return size;
1089}
1090
14d0263f
SH		 1091/* Build description to hardware for one receive segment */
1092static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1093 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1094{
1095 struct sky2_rx_le *le;
1096
86c6887e 1097 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1098 le = sky2_next_rx(sky2);
86c6887e 1099 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1100 le->opcode = OP_ADDR64 | HW_OWNER;
1101 }
793b883e 1102
cd28ab6a 1103 le = sky2_next_rx(sky2);
d6e74b6b 1104 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1105 le->length = cpu_to_le16(len);
14d0263f 1106 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1107}
1108
14d0263f
SH		 1109/* Build description to hardware for one possibly fragmented skb */
1110static void sky2_rx_submit(struct sky2_port *sky2,
1111 const struct rx_ring_info *re)
1112{
1113 int i;
1114
1115 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1116
1117 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1118 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1119}
1120
1121
454e6cb6 1122static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1123 unsigned size)
1124{
1125 struct sk_buff *skb = re->skb;
1126 int i;
1127
1128 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1129 if (pci_dma_mapping_error(pdev, re->data_addr))
1130 goto mapping_error;
454e6cb6 1131
14d0263f
SH		 1132 pci_unmap_len_set(re, data_size, size);
1133
3fbd9187 1134 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1135 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1136
1137 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1138 frag->page_offset,
1139 frag->size,
14d0263f 1140 PCI_DMA_FROMDEVICE);
3fbd9187 1141
1142 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1143 goto map_page_error;
1144 }
454e6cb6 1145 return 0;
3fbd9187 1146
1147map_page_error:
1148 while (--i >= 0) {
1149 pci_unmap_page(pdev, re->frag_addr[i],
1150 skb_shinfo(skb)->frags[i].size,
1151 PCI_DMA_FROMDEVICE);
1152 }
1153
1154 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1155 PCI_DMA_FROMDEVICE);
1156
1157mapping_error:
1158 if (net_ratelimit())
1159 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1160 skb->dev->name);
1161 return -EIO;
14d0263f
SH		 1162}
1163
1164static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1165{
1166 struct sk_buff *skb = re->skb;
1167 int i;
1168
1169 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1170 PCI_DMA_FROMDEVICE);
1171
1172 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1173 pci_unmap_page(pdev, re->frag_addr[i],
1174 skb_shinfo(skb)->frags[i].size,
1175 PCI_DMA_FROMDEVICE);
1176}
793b883e 1177
cd28ab6a
SH		 1178/* Tell chip where to start receive checksum.
1179 * Actually has two checksums, but set both same to avoid possible byte
1180 * order problems.
1181 */
793b883e 1182static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1183{
ea76e635 1184 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1185
ea76e635
SH		 1186 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1187 le->ctrl = 0;
1188 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1189
ea76e635
SH		 1190 sky2_write32(sky2->hw,
1191 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1192 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1193 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1194}
1195
6b1a3aef
SH		 1196/*
1197 * The RX Stop command will not work for Yukon-2 if the BMU does not
1198 * reach the end of packet and since we can't make sure that we have
1199 * incoming data, we must reset the BMU while it is not doing a DMA
1200 * transfer. Since it is possible that the RX path is still active,
1201 * the RX RAM buffer will be stopped first, so any possible incoming
1202 * data will not trigger a DMA. After the RAM buffer is stopped, the
1203 * BMU is polled until any DMA in progress is ended and only then it
1204 * will be reset.
1205 */
1206static void sky2_rx_stop(struct sky2_port *sky2)
1207{
1208 struct sky2_hw *hw = sky2->hw;
1209 unsigned rxq = rxqaddr[sky2->port];
1210 int i;
1211
1212 /* disable the RAM Buffer receive queue */
1213 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1214
1215 for (i = 0; i < 0xffff; i++)
1216 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1217 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1218 goto stopped;
1219
ada1db5c 1220 netdev_warn(sky2->netdev, "receiver stop failed\n");
6b1a3aef
SH		 1221stopped:
1222 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1223
1224 /* reset the Rx prefetch unit */
1225 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1226 mmiowb();
6b1a3aef 1227}
793b883e 1228
d571b694 1229/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1230static void sky2_rx_clean(struct sky2_port *sky2)
1231{
1232 unsigned i;
1233
1234 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1235 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1236 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1237
1238 if (re->skb) {
14d0263f 1239 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1240 kfree_skb(re->skb);
1241 re->skb = NULL;
1242 }
1243 }
1244}
1245
ef743d33
SH		 1246/* Basic MII support */
1247static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1248{
1249 struct mii_ioctl_data *data = if_mii(ifr);
1250 struct sky2_port *sky2 = netdev_priv(dev);
1251 struct sky2_hw *hw = sky2->hw;
1252 int err = -EOPNOTSUPP;
1253
1254 if (!netif_running(dev))
1255 return -ENODEV; /* Phy still in reset */
1256
d89e1343 1257 switch (cmd) {
ef743d33
SH		 1258 case SIOCGMIIPHY:
1259 data->phy_id = PHY_ADDR_MARV;
1260
1261 /* fallthru */
1262 case SIOCGMIIREG: {
1263 u16 val = 0;
91c86df5 1264
e07b1aa8 1265 spin_lock_bh(&sky2->phy_lock);
ef743d33 1266 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1267 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1268
ef743d33
SH		 1269 data->val_out = val;
1270 break;
1271 }
1272
1273 case SIOCSMIIREG:
e07b1aa8 1274 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1275 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1276 data->val_in);
e07b1aa8 1277 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1278 break;
1279 }
1280 return err;
1281}
1282
d1f13708 1283#ifdef SKY2_VLAN_TAG_USED
d494eacd 1284static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1285{
d494eacd 1286 if (onoff) {
3d4e66f5
SH		 1287 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1288 RX_VLAN_STRIP_ON);
1289 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1290 TX_VLAN_TAG_ON);
1291 } else {
1292 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1293 RX_VLAN_STRIP_OFF);
1294 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1295 TX_VLAN_TAG_OFF);
1296 }
d494eacd
SH		 1297}
1298
1299static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1300{
1301 struct sky2_port *sky2 = netdev_priv(dev);
1302 struct sky2_hw *hw = sky2->hw;
1303 u16 port = sky2->port;
1304
1305 netif_tx_lock_bh(dev);
1306 napi_disable(&hw->napi);
1307
1308 sky2->vlgrp = grp;
1309 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1310
d1d08d12 1311 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1312 napi_enable(&hw->napi);
2bb8c262 1313 netif_tx_unlock_bh(dev);
d1f13708
SH		 1314}
1315#endif
1316
bd1c6869
SH		 1317/* Amount of required worst case padding in rx buffer */
1318static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1319{
1320 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1321}
1322
82788c7a 1323/*
14d0263f
SH		 1324 * Allocate an skb for receiving. If the MTU is large enough
1325 * make the skb non-linear with a fragment list of pages.
82788c7a 1326 */
14d0263f 1327static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1328{
1329 struct sk_buff *skb;
14d0263f 1330 int i;
82788c7a 1331
724b6942
SH		 1332 skb = netdev_alloc_skb(sky2->netdev,
1333 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1334 if (!skb)
1335 goto nomem;
1336
39dbd958 1337 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1338 unsigned char *start;
1339 /*
1340 * Workaround for a bug in FIFO that cause hang
1341 * if the FIFO if the receive buffer is not 64 byte aligned.
1342 * The buffer returned from netdev_alloc_skb is
1343 * aligned except if slab debugging is enabled.
1344 */
f03b8654
SH		 1345 start = PTR_ALIGN(skb->data, 8);
1346 skb_reserve(skb, start - skb->data);
bd1c6869 1347 } else
f03b8654 1348 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1349
1350 for (i = 0; i < sky2->rx_nfrags; i++) {
1351 struct page *page = alloc_page(GFP_ATOMIC);
1352
1353 if (!page)
1354 goto free_partial;
1355 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1356 }
1357
1358 return skb;
14d0263f
SH		 1359free_partial:
1360 kfree_skb(skb);
1361nomem:
1362 return NULL;
82788c7a
SH		 1363}
1364
55c9dd35
SH		 1365static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1366{
1367 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1368}
1369
200ac492
MM		 1370static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1371{
1372 struct sky2_hw *hw = sky2->hw;
1373 unsigned i;
1374
1375 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1376
1377 /* Fill Rx ring */
1378 for (i = 0; i < sky2->rx_pending; i++) {
1379 struct rx_ring_info *re = sky2->rx_ring + i;
1380
1381 re->skb = sky2_rx_alloc(sky2);
1382 if (!re->skb)
1383 return -ENOMEM;
1384
1385 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1386 dev_kfree_skb(re->skb);
1387 re->skb = NULL;
1388 return -ENOMEM;
1389 }
1390 }
1391 return 0;
1392}
1393
cd28ab6a 1394/*
200ac492 1395 * Setup receiver buffer pool.
14d0263f
SH		 1396 * Normal case this ends up creating one list element for skb
1397 * in the receive ring. Worst case if using large MTU and each
1398 * allocation falls on a different 64 bit region, that results
1399 * in 6 list elements per ring entry.
1400 * One element is used for checksum enable/disable, and one
1401 * extra to avoid wrap.
cd28ab6a 1402 */
200ac492 1403static void sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1404{
6b1a3aef 1405 struct sky2_hw *hw = sky2->hw;
14d0263f 1406 struct rx_ring_info *re;
6b1a3aef 1407 unsigned rxq = rxqaddr[sky2->port];
39ef110b 1408 unsigned i, thresh;
cd28ab6a 1409
6b1a3aef 1410 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1411 sky2_qset(hw, rxq);
977bdf06 1412
c3905bc4
SH		 1413 /* On PCI express lowering the watermark gives better performance */
1414 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1415 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1416
1417 /* These chips have no ram buffer?
1418 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1419 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c1cd0a85 1420 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
f449c7c1 1421 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1422
6b1a3aef
SH		 1423 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1424
ea76e635
SH		 1425 if (!(hw->flags & SKY2_HW_NEW_LE))
1426 rx_set_checksum(sky2);
14d0263f 1427
200ac492 1428 /* submit Rx ring */
793b883e 1429 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1430 re = sky2->rx_ring + i;
14d0263f 1431 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1432 }
1433
a1433ac4
SH		 1434 /*
1435 * The receiver hangs if it receives frames larger than the
1436 * packet buffer. As a workaround, truncate oversize frames, but
1437 * the register is limited to 9 bits, so if you do frames > 2052
1438 * you better get the MTU right!
1439 */
39ef110b 1440 thresh = sky2_get_rx_threshold(sky2);
a1433ac4
SH		 1441 if (thresh > 0x1ff)
1442 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1443 else {
1444 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1445 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1446 }
1447
6b1a3aef 1448 /* Tell chip about available buffers */
55c9dd35 1449 sky2_rx_update(sky2, rxq);
877c8570
SH		 1450
1451 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1452 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1453 /*
1454 * Disable flushing of non ASF packets;
1455 * must be done after initializing the BMUs;
1456 * drivers without ASF support should do this too, otherwise
1457 * it may happen that they cannot run on ASF devices;
1458 * remember that the MAC FIFO isn't reset during initialization.
1459 */
1460 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1461 }
1462
1463 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1464 /* Enable RX Home Address & Routing Header checksum fix */
1465 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1466 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1467
1468 /* Enable TX Home Address & Routing Header checksum fix */
1469 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1470 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1471 }
cd28ab6a
SH		 1472}
1473
90bbebb4
MM		 1474static int sky2_alloc_buffers(struct sky2_port *sky2)
1475{
1476 struct sky2_hw *hw = sky2->hw;
1477
1478 /* must be power of 2 */
1479 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1480 sky2->tx_ring_size *
1481 sizeof(struct sky2_tx_le),
1482 &sky2->tx_le_map);
1483 if (!sky2->tx_le)
1484 goto nomem;
1485
1486 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1487 GFP_KERNEL);
1488 if (!sky2->tx_ring)
1489 goto nomem;
1490
1491 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1492 &sky2->rx_le_map);
1493 if (!sky2->rx_le)
1494 goto nomem;
1495 memset(sky2->rx_le, 0, RX_LE_BYTES);
1496
1497 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1498 GFP_KERNEL);
1499 if (!sky2->rx_ring)
1500 goto nomem;
1501
200ac492 1502 return sky2_alloc_rx_skbs(sky2);
90bbebb4
MM		 1503nomem:
1504 return -ENOMEM;
1505}
1506
1507static void sky2_free_buffers(struct sky2_port *sky2)
1508{
1509 struct sky2_hw *hw = sky2->hw;
1510
200ac492
MM		 1511 sky2_rx_clean(sky2);
1512
90bbebb4
MM		 1513 if (sky2->rx_le) {
1514 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1515 sky2->rx_le, sky2->rx_le_map);
1516 sky2->rx_le = NULL;
1517 }
1518 if (sky2->tx_le) {
1519 pci_free_consistent(hw->pdev,
1520 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1521 sky2->tx_le, sky2->tx_le_map);
1522 sky2->tx_le = NULL;
1523 }
1524 kfree(sky2->tx_ring);
1525 kfree(sky2->rx_ring);
1526
1527 sky2->tx_ring = NULL;
1528 sky2->rx_ring = NULL;
1529}
1530
ea0f71e5 1531static void sky2_hw_up(struct sky2_port *sky2)
cd28ab6a 1532{
cd28ab6a
SH		 1533 struct sky2_hw *hw = sky2->hw;
1534 unsigned port = sky2->port;
ea0f71e5
MM		 1535 u32 ramsize;
1536 int cap;
843a46f4 1537 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1538
ea0f71e5
MM		 1539 tx_init(sky2);
1540
ee7abb04
SH		 1541 /*
1542 * On dual port PCI-X card, there is an problem where status
1543 * can be received out of order due to split transactions
843a46f4 1544 */
ee7abb04
SH		 1545 if (otherdev && netif_running(otherdev) &&
1546 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1547 u16 cmd;
1548
b32f40c4 1549 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1550 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4 1551 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
ea0f71e5 1552 }
cd28ab6a 1553
cd28ab6a
SH		 1554 sky2_mac_init(hw, port);
1555
e0c28116
SH		 1556 /* Register is number of 4K blocks on internal RAM buffer. */
1557 ramsize = sky2_read8(hw, B2_E_0) * 4;
1558 if (ramsize > 0) {
67712901 1559 u32 rxspace;
cd28ab6a 1560
ada1db5c 1561 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
67712901
SH		 1562 if (ramsize < 16)
1563 rxspace = ramsize / 2;
1564 else
1565 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1566
67712901
SH		 1567 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1568 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1569
1570 /* Make sure SyncQ is disabled */
1571 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1572 RB_RST_SET);
1573 }
793b883e 1574
af4ed7e6 1575 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1576
69161611
SH		 1577 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1578 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1579 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1580
977bdf06 1581 /* Set almost empty threshold */
8e95a202
JP		 1582 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1583 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1584 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1585
6b1a3aef 1586 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1587 sky2->tx_ring_size - 1);
cd28ab6a 1588
d494eacd
SH		 1589#ifdef SKY2_VLAN_TAG_USED
1590 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1591#endif
1592
200ac492 1593 sky2_rx_start(sky2);
ea0f71e5
MM		 1594}
1595
1596/* Bring up network interface. */
1597static int sky2_up(struct net_device *dev)
1598{
1599 struct sky2_port *sky2 = netdev_priv(dev);
1600 struct sky2_hw *hw = sky2->hw;
1601 unsigned port = sky2->port;
1602 u32 imask;
1603 int err;
1604
1605 netif_carrier_off(dev);
1606
1607 err = sky2_alloc_buffers(sky2);
1608 if (err)
1609 goto err_out;
1610
1611 sky2_hw_up(sky2);
cd28ab6a 1612
cd28ab6a 1613 /* Enable interrupts from phy/mac for port */
e07b1aa8 1614 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1615 imask |= portirq_msk[port];
e07b1aa8 1616 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1617 sky2_read32(hw, B0_IMSK);
e07b1aa8 1618
6c35abae 1619 netif_info(sky2, ifup, dev, "enabling interface\n");
af18d8b8 1620
cd28ab6a
SH		 1621 return 0;
1622
1623err_out:
90bbebb4 1624 sky2_free_buffers(sky2);
cd28ab6a
SH		 1625 return err;
1626}
1627
793b883e 1628/* Modular subtraction in ring */
ee5f68fe 1629static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1630{
ee5f68fe 1631 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1632}
cd28ab6a 1633
793b883e
SH		 1634/* Number of list elements available for next tx */
1635static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1636{
ee5f68fe 1637 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1638}
1639
793b883e 1640/* Estimate of number of transmit list elements required */
28bd181a 1641static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1642{
793b883e
SH		 1643 unsigned count;
1644
07e31637
SH		 1645 count = (skb_shinfo(skb)->nr_frags + 1)
1646 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1647
89114afd 1648 if (skb_is_gso(skb))
793b883e 1649 ++count;
07e31637
SH		 1650 else if (sizeof(dma_addr_t) == sizeof(u32))
1651 ++count; /* possible vlan */
793b883e 1652
84fa7933 1653 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1654 ++count;
1655
1656 return count;
cd28ab6a
SH		 1657}
1658
f6815077 1659static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1660{
1661 if (re->flags & TX_MAP_SINGLE)
1662 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1663 pci_unmap_len(re, maplen),
1664 PCI_DMA_TODEVICE);
1665 else if (re->flags & TX_MAP_PAGE)
1666 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1667 pci_unmap_len(re, maplen),
1668 PCI_DMA_TODEVICE);
f6815077 1669 re->flags = 0;
6b84daca
SH		 1670}
1671
793b883e
SH		 1672/*
1673 * Put one packet in ring for transmit.
1674 * A single packet can generate multiple list elements, and
1675 * the number of ring elements will probably be less than the number
1676 * of list elements used.
1677 */
61357325
SH		 1678static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1679 struct net_device *dev)
cd28ab6a
SH		 1680{
1681 struct sky2_port *sky2 = netdev_priv(dev);
1682 struct sky2_hw *hw = sky2->hw;
d1f13708 1683 struct sky2_tx_le *le = NULL;
6cdbbdf3 1684 struct tx_ring_info *re;
9b289c33 1685 unsigned i, len;
cd28ab6a 1686 dma_addr_t mapping;
5dce95e5
SH		 1687 u32 upper;
1688 u16 slot;
cd28ab6a
SH		 1689 u16 mss;
1690 u8 ctrl;
1691
2bb8c262
SH		 1692 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1693 return NETDEV_TX_BUSY;
cd28ab6a 1694
cd28ab6a
SH		 1695 len = skb_headlen(skb);
1696 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1697
454e6cb6
SH		 1698 if (pci_dma_mapping_error(hw->pdev, mapping))
1699 goto mapping_error;
1700
9b289c33 1701 slot = sky2->tx_prod;
6c35abae
JP		 1702 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1703 "tx queued, slot %u, len %d\n", slot, skb->len);
454e6cb6 1704
86c6887e 1705 /* Send high bits if needed */
5dce95e5
SH		 1706 upper = upper_32_bits(mapping);
1707 if (upper != sky2->tx_last_upper) {
9b289c33 1708 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1709 le->addr = cpu_to_le32(upper);
1710 sky2->tx_last_upper = upper;
793b883e 1711 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1712 }
cd28ab6a
SH		 1713
1714 /* Check for TCP Segmentation Offload */
7967168c 1715 mss = skb_shinfo(skb)->gso_size;
793b883e 1716 if (mss != 0) {
ea76e635
SH		 1717
1718 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1719 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1720
1721 if (mss != sky2->tx_last_mss) {
9b289c33 1722 le = get_tx_le(sky2, &slot);
69161611 1723 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1724
1725 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1726 le->opcode = OP_MSS | HW_OWNER;
1727 else
1728 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1729 sky2->tx_last_mss = mss;
1730 }
cd28ab6a
SH		 1731 }
1732
cd28ab6a 1733 ctrl = 0;
d1f13708
SH		 1734#ifdef SKY2_VLAN_TAG_USED
1735 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1736 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1737 if (!le) {
9b289c33 1738 le = get_tx_le(sky2, &slot);
f65b138c 1739 le->addr = 0;
d1f13708 1740 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1741 } else
1742 le->opcode |= OP_VLAN;
1743 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1744 ctrl |= INS_VLAN;
1745 }
1746#endif
1747
1748 /* Handle TCP checksum offload */
84fa7933 1749 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1750 /* On Yukon EX (some versions) encoding change. */
ea76e635 1751 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1752 ctrl |= CALSUM; /* auto checksum */
1753 else {
1754 const unsigned offset = skb_transport_offset(skb);
1755 u32 tcpsum;
1756
1757 tcpsum = offset << 16; /* sum start */
1758 tcpsum |= offset + skb->csum_offset; /* sum write */
1759
1760 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1761 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1762 ctrl |= UDPTCP;
1763
1764 if (tcpsum != sky2->tx_tcpsum) {
1765 sky2->tx_tcpsum = tcpsum;
1766
9b289c33 1767 le = get_tx_le(sky2, &slot);
69161611
SH		 1768 le->addr = cpu_to_le32(tcpsum);
1769 le->length = 0; /* initial checksum value */
1770 le->ctrl = 1; /* one packet */
1771 le->opcode = OP_TCPLISW | HW_OWNER;
1772 }
1d179332 1773 }
cd28ab6a
SH		 1774 }
1775
6b84daca
SH		 1776 re = sky2->tx_ring + slot;
1777 re->flags = TX_MAP_SINGLE;
1778 pci_unmap_addr_set(re, mapaddr, mapping);
1779 pci_unmap_len_set(re, maplen, len);
1780
9b289c33 1781 le = get_tx_le(sky2, &slot);
d6e74b6b 1782 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1783 le->length = cpu_to_le16(len);
1784 le->ctrl = ctrl;
793b883e 1785 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1786
cd28ab6a
SH		 1787
1788 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1789 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1790
1791 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1792 frag->size, PCI_DMA_TODEVICE);
86c6887e 1793
454e6cb6
SH		 1794 if (pci_dma_mapping_error(hw->pdev, mapping))
1795 goto mapping_unwind;
1796
5dce95e5
SH		 1797 upper = upper_32_bits(mapping);
1798 if (upper != sky2->tx_last_upper) {
9b289c33 1799 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1800 le->addr = cpu_to_le32(upper);
1801 sky2->tx_last_upper = upper;
793b883e 1802 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1803 }
1804
6b84daca
SH		 1805 re = sky2->tx_ring + slot;
1806 re->flags = TX_MAP_PAGE;
1807 pci_unmap_addr_set(re, mapaddr, mapping);
1808 pci_unmap_len_set(re, maplen, frag->size);
1809
9b289c33 1810 le = get_tx_le(sky2, &slot);
d6e74b6b 1811 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1812 le->length = cpu_to_le16(frag->size);
1813 le->ctrl = ctrl;
793b883e 1814 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1815 }
6cdbbdf3 1816
6b84daca 1817 re->skb = skb;
cd28ab6a
SH		 1818 le->ctrl |= EOP;
1819
9b289c33
MM		 1820 sky2->tx_prod = slot;
1821
97bda706
SH		 1822 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1823 netif_stop_queue(dev);
b19666d9 1824
290d4de5 1825 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1826
cd28ab6a 1827 return NETDEV_TX_OK;
454e6cb6
SH		 1828
1829mapping_unwind:
ee5f68fe 1830 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1831 re = sky2->tx_ring + i;
1832
6b84daca 1833 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1834 }
1835
454e6cb6
SH		 1836mapping_error:
1837 if (net_ratelimit())
1838 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1839 dev_kfree_skb(skb);
1840 return NETDEV_TX_OK;
cd28ab6a
SH		 1841}
1842
cd28ab6a 1843/*
793b883e
SH		 1844 * Free ring elements from starting at tx_cons until "done"
1845 *
481cea4a
SH		 1846 * NB:
1847 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1848 * buffers so make sure not to free skb to early.
481cea4a
SH		 1849 * 2. This may run in parallel start_xmit because the it only
1850 * looks at the tail of the queue of FIFO (tx_cons), not
1851 * the head (tx_prod)
cd28ab6a 1852 */
d11c13e7 1853static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1854{
d11c13e7 1855 struct net_device *dev = sky2->netdev;
291ea614 1856 unsigned idx;
cd28ab6a 1857
ee5f68fe 1858 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1859
291ea614 1860 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1861 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1862 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1863 struct sk_buff *skb = re->skb;
291ea614 1864
6b84daca 1865 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1866
6b84daca 1867 if (skb) {
6c35abae
JP		 1868 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1869 "tx done %u\n", idx);
3cf26753 1870
7138a0f5 1871 dev->stats.tx_packets++;
bd1c6869
SH		 1872 dev->stats.tx_bytes += skb->len;
1873
f6815077 1874 re->skb = NULL;
724b6942 1875 dev_kfree_skb_any(skb);
2bf56fe2 1876
ee5f68fe 1877 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1878 }
793b883e 1879 }
793b883e 1880
291ea614 1881 sky2->tx_cons = idx;
50432cb5 1882 smp_mb();
cd28ab6a
SH		 1883}
1884
264bb4fa 1885static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1886{
a510996b
MM		 1887 /* Disable Force Sync bit and Enable Alloc bit */
1888 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1889 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1890
1891 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1892 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1893 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1894
1895 /* Reset the PCI FIFO of the async Tx queue */
1896 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1897 BMU_RST_SET | BMU_FIFO_RST);
1898
1899 /* Reset the Tx prefetch units */
1900 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1901 PREF_UNIT_RST_SET);
1902
1903 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1904 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1905}
1906
f2b31cb3 1907static void sky2_hw_down(struct sky2_port *sky2)
cd28ab6a 1908{
cd28ab6a
SH		 1909 struct sky2_hw *hw = sky2->hw;
1910 unsigned port = sky2->port;
f2b31cb3 1911 u16 ctrl;
cd28ab6a 1912
d104acaf
SH		 1913 /* Force flow control off */
1914 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1915
cd28ab6a
SH		 1916 /* Stop transmitter */
1917 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1918 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1919
1920 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1921 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1922
1923 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1924 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1925 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1926
1927 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1928
1929 /* Workaround shared GMAC reset */
8e95a202
JP		 1930 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1931 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1932 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1933
cd28ab6a 1934 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1935
6c83504f
SH		 1936 /* Force any delayed status interrrupt and NAPI */
1937 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1938 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1939 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1940 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1941
a947a39d
MM		 1942 sky2_rx_stop(sky2);
1943
0da6d7b3 1944 spin_lock_bh(&sky2->phy_lock);
b96936da 1945 sky2_phy_power_down(hw, port);
0da6d7b3 1946 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1947
264bb4fa
MM		 1948 sky2_tx_reset(hw, port);
1949
481cea4a
SH		 1950 /* Free any pending frames stuck in HW queue */
1951 sky2_tx_complete(sky2, sky2->tx_prod);
f2b31cb3
MM		 1952}
1953
1954/* Network shutdown */
1955static int sky2_down(struct net_device *dev)
1956{
1957 struct sky2_port *sky2 = netdev_priv(dev);
8a0c9228 1958 struct sky2_hw *hw = sky2->hw;
f2b31cb3
MM		 1959
1960 /* Never really got started! */
1961 if (!sky2->tx_le)
1962 return 0;
1963
6c35abae 1964 netif_info(sky2, ifdown, dev, "disabling interface\n");
f2b31cb3 1965
8a0c9228
MM		 1966 /* Disable port IRQ */
1967 sky2_write32(hw, B0_IMSK,
1968 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
1969 sky2_read32(hw, B0_IMSK);
1970
1971 synchronize_irq(hw->pdev->irq);
1972 napi_synchronize(&hw->napi);
1973
f2b31cb3 1974 sky2_hw_down(sky2);
481cea4a 1975
90bbebb4 1976 sky2_free_buffers(sky2);
1b537565 1977
cd28ab6a
SH		 1978 return 0;
1979}
1980
1981static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1982{
ea76e635 1983 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1984 return SPEED_1000;
1985
05745c4a
SH		 1986 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1987 if (aux & PHY_M_PS_SPEED_100)
1988 return SPEED_100;
1989 else
1990 return SPEED_10;
1991 }
cd28ab6a
SH		 1992
1993 switch (aux & PHY_M_PS_SPEED_MSK) {
1994 case PHY_M_PS_SPEED_1000:
1995 return SPEED_1000;
1996 case PHY_M_PS_SPEED_100:
1997 return SPEED_100;
1998 default:
1999 return SPEED_10;
2000 }
2001}
2002
2003static void sky2_link_up(struct sky2_port *sky2)
2004{
2005 struct sky2_hw *hw = sky2->hw;
2006 unsigned port = sky2->port;
2007 u16 reg;
16ad91e1
SH		 2008 static const char *fc_name[] = {
2009 [FC_NONE] = "none",
2010 [FC_TX] = "tx",
2011 [FC_RX] = "rx",
2012 [FC_BOTH] = "both",
2013 };
cd28ab6a 2014
cd28ab6a 2015 /* enable Rx/Tx */
2eaba1a2 2016 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 2017 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2018 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 2019
2020 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2021
2022 netif_carrier_on(sky2->netdev);
cd28ab6a 2023
75e80683 2024 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 2025
cd28ab6a 2026 /* Turn on link LED */
793b883e 2027 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2028 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2029
6c35abae
JP		 2030 netif_info(sky2, link, sky2->netdev,
2031 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2032 sky2->speed,
2033 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2034 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2035}
2036
2037static void sky2_link_down(struct sky2_port *sky2)
2038{
2039 struct sky2_hw *hw = sky2->hw;
2040 unsigned port = sky2->port;
2041 u16 reg;
2042
2043 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2044
2045 reg = gma_read16(hw, port, GM_GP_CTRL);
2046 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2047 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2048
cd28ab6a 2049 netif_carrier_off(sky2->netdev);
cd28ab6a 2050
809aaaae 2051 /* Turn off link LED */
cd28ab6a
SH		 2052 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2053
6c35abae 2054 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2eaba1a2 2055
cd28ab6a
SH		 2056 sky2_phy_init(hw, port);
2057}
2058
16ad91e1
SH		 2059static enum flow_control sky2_flow(int rx, int tx)
2060{
2061 if (rx)
2062 return tx ? FC_BOTH : FC_RX;
2063 else
2064 return tx ? FC_TX : FC_NONE;
2065}
2066
793b883e
SH		 2067static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2068{
2069 struct sky2_hw *hw = sky2->hw;
2070 unsigned port = sky2->port;
da4c1ff4 2071 u16 advert, lpa;
793b883e 2072
da4c1ff4 2073 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2074 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e 2075 if (lpa & PHY_M_AN_RF) {
ada1db5c 2076 netdev_err(sky2->netdev, "remote fault\n");
793b883e
SH		 2077 return -1;
2078 }
2079
793b883e 2080 if (!(aux & PHY_M_PS_SPDUP_RES)) {
ada1db5c 2081 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
793b883e
SH		 2082 return -1;
2083 }
2084
793b883e 2085 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2086 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2087
da4c1ff4
SH		 2088 /* Since the pause result bits seem to in different positions on
2089 * different chips. look at registers.
2090 */
ea76e635 2091 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2092 /* Shift for bits in fiber PHY */
2093 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2094 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2095
2096 if (advert & ADVERTISE_1000XPAUSE)
2097 advert |= ADVERTISE_PAUSE_CAP;
2098 if (advert & ADVERTISE_1000XPSE_ASYM)
2099 advert |= ADVERTISE_PAUSE_ASYM;
2100 if (lpa & LPA_1000XPAUSE)
2101 lpa |= LPA_PAUSE_CAP;
2102 if (lpa & LPA_1000XPAUSE_ASYM)
2103 lpa |= LPA_PAUSE_ASYM;
2104 }
793b883e 2105
da4c1ff4
SH		 2106 sky2->flow_status = FC_NONE;
2107 if (advert & ADVERTISE_PAUSE_CAP) {
2108 if (lpa & LPA_PAUSE_CAP)
2109 sky2->flow_status = FC_BOTH;
2110 else if (advert & ADVERTISE_PAUSE_ASYM)
2111 sky2->flow_status = FC_RX;
2112 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2113 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2114 sky2->flow_status = FC_TX;
2115 }
793b883e 2116
8e95a202
JP		 2117 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2118 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2119 sky2->flow_status = FC_NONE;
2eaba1a2 2120
da4c1ff4 2121 if (sky2->flow_status & FC_TX)
793b883e
SH		 2122 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2123 else
2124 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2125
2126 return 0;
2127}
cd28ab6a 2128
e07b1aa8
SH		 2129/* Interrupt from PHY */
2130static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2131{
e07b1aa8
SH		 2132 struct net_device *dev = hw->dev[port];
2133 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2134 u16 istatus, phystat;
2135
ebc646f6
SH		 2136 if (!netif_running(dev))
2137 return;
2138
e07b1aa8
SH		 2139 spin_lock(&sky2->phy_lock);
2140 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2141 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2142
6c35abae
JP		 2143 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2144 istatus, phystat);
cd28ab6a 2145
0ea065e5 2146 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2147 if (sky2_autoneg_done(sky2, phystat) == 0)
2148 sky2_link_up(sky2);
2149 goto out;
2150 }
cd28ab6a 2151
793b883e
SH		 2152 if (istatus & PHY_M_IS_LSP_CHANGE)
2153 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2154
793b883e
SH		 2155 if (istatus & PHY_M_IS_DUP_CHANGE)
2156 sky2->duplex =
2157 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2158
793b883e
SH		 2159 if (istatus & PHY_M_IS_LST_CHANGE) {
2160 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2161 sky2_link_up(sky2);
793b883e
SH		 2162 else
2163 sky2_link_down(sky2);
cd28ab6a 2164 }
793b883e 2165out:
e07b1aa8 2166 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2167}
2168
0f5aac70
SH		 2169/* Special quick link interrupt (Yukon-2 Optima only) */
2170static void sky2_qlink_intr(struct sky2_hw *hw)
2171{
2172 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2173 u32 imask;
2174 u16 phy;
2175
2176 /* disable irq */
2177 imask = sky2_read32(hw, B0_IMSK);
2178 imask &= ~Y2_IS_PHY_QLNK;
2179 sky2_write32(hw, B0_IMSK, imask);
2180
2181 /* reset PHY Link Detect */
2182 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2183 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2184 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2185 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2186
2187 sky2_link_up(sky2);
2188}
2189
62335ab0 2190/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2191 * and tx queue is full (stopped).
2192 */
cd28ab6a
SH		 2193static void sky2_tx_timeout(struct net_device *dev)
2194{
2195 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2196 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2197
6c35abae 2198 netif_err(sky2, timer, dev, "tx timeout\n");
cd28ab6a 2199
ada1db5c
JP		 2200 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2201 sky2->tx_cons, sky2->tx_prod,
2202 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2203 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2204
81906791
SH		 2205 /* can't restart safely under softirq */
2206 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2207}
2208
2209static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2210{
6b1a3aef
SH		 2211 struct sky2_port *sky2 = netdev_priv(dev);
2212 struct sky2_hw *hw = sky2->hw;
b628ed98 2213 unsigned port = sky2->port;
6b1a3aef
SH		 2214 int err;
2215 u16 ctl, mode;
e07b1aa8 2216 u32 imask;
cd28ab6a 2217
44dde56d 2218 /* MTU size outside the spec */
cd28ab6a
SH		 2219 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2220 return -EINVAL;
2221
44dde56d 2222 /* MTU > 1500 on yukon FE and FE+ not allowed */
05745c4a
SH		 2223 if (new_mtu > ETH_DATA_LEN &&
2224 (hw->chip_id == CHIP_ID_YUKON_FE ||
2225 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2226 return -EINVAL;
2227
44dde56d 2228 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2229 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
2230 dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
2231
6b1a3aef
SH		 2232 if (!netif_running(dev)) {
2233 dev->mtu = new_mtu;
2234 return 0;
2235 }
2236
e07b1aa8 2237 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2238 sky2_write32(hw, B0_IMSK, 0);
2239
018d1c66
SH		 2240 dev->trans_start = jiffies; /* prevent tx timeout */
2241 netif_stop_queue(dev);
bea3348e 2242 napi_disable(&hw->napi);
018d1c66 2243
e07b1aa8
SH		 2244 synchronize_irq(hw->pdev->irq);
2245
39dbd958 2246 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2247 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2248
2249 ctl = gma_read16(hw, port, GM_GP_CTRL);
2250 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2251 sky2_rx_stop(sky2);
2252 sky2_rx_clean(sky2);
cd28ab6a
SH		 2253
2254 dev->mtu = new_mtu;
14d0263f 2255
6b1a3aef
SH		 2256 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2257 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2258
2259 if (dev->mtu > ETH_DATA_LEN)
2260 mode |= GM_SMOD_JUMBO_ENA;
2261
b628ed98 2262 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2263
b628ed98 2264 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2265
200ac492
MM		 2266 err = sky2_alloc_rx_skbs(sky2);
2267 if (!err)
2268 sky2_rx_start(sky2);
2269 else
2270 sky2_rx_clean(sky2);
e07b1aa8 2271 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2272
d1d08d12 2273 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2274 napi_enable(&hw->napi);
2275
1b537565
SH		 2276 if (err)
2277 dev_close(dev);
2278 else {
b628ed98 2279 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2280
1b537565
SH		 2281 netif_wake_queue(dev);
2282 }
2283
cd28ab6a
SH		 2284 return err;
2285}
2286
14d0263f
SH		 2287/* For small just reuse existing skb for next receive */
2288static struct sk_buff *receive_copy(struct sky2_port *sky2,
2289 const struct rx_ring_info *re,
2290 unsigned length)
2291{
2292 struct sk_buff *skb;
2293
89d71a66 2294 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2295 if (likely(skb)) {
14d0263f
SH		 2296 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2297 length, PCI_DMA_FROMDEVICE);
d626f62b 2298 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2299 skb->ip_summed = re->skb->ip_summed;
2300 skb->csum = re->skb->csum;
2301 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2302 length, PCI_DMA_FROMDEVICE);
2303 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2304 skb_put(skb, length);
14d0263f
SH		 2305 }
2306 return skb;
2307}
2308
2309/* Adjust length of skb with fragments to match received data */
2310static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2311 unsigned int length)
2312{
2313 int i, num_frags;
2314 unsigned int size;
2315
2316 /* put header into skb */
2317 size = min(length, hdr_space);
2318 skb->tail += size;
2319 skb->len += size;
2320 length -= size;
2321
2322 num_frags = skb_shinfo(skb)->nr_frags;
2323 for (i = 0; i < num_frags; i++) {
2324 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2325
2326 if (length == 0) {
2327 /* don't need this page */
2328 __free_page(frag->page);
2329 --skb_shinfo(skb)->nr_frags;
2330 } else {
2331 size = min(length, (unsigned) PAGE_SIZE);
2332
2333 frag->size = size;
2334 skb->data_len += size;
2335 skb->truesize += size;
2336 skb->len += size;
2337 length -= size;
2338 }
2339 }
2340}
2341
2342/* Normal packet - take skb from ring element and put in a new one */
2343static struct sk_buff *receive_new(struct sky2_port *sky2,
2344 struct rx_ring_info *re,
2345 unsigned int length)
2346{
3fbd9187 2347 struct sk_buff *skb;
2348 struct rx_ring_info nre;
14d0263f
SH		 2349 unsigned hdr_space = sky2->rx_data_size;
2350
3fbd9187 2351 nre.skb = sky2_rx_alloc(sky2);
2352 if (unlikely(!nre.skb))
2353 goto nobuf;
2354
2355 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2356 goto nomap;
14d0263f
SH		 2357
2358 skb = re->skb;
2359 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2360 prefetch(skb->data);
3fbd9187 2361 *re = nre;
14d0263f
SH		 2362
2363 if (skb_shinfo(skb)->nr_frags)
2364 skb_put_frags(skb, hdr_space, length);
2365 else
489b10c1 2366 skb_put(skb, length);
14d0263f 2367 return skb;
3fbd9187 2368
2369nomap:
2370 dev_kfree_skb(nre.skb);
2371nobuf:
2372 return NULL;
14d0263f
SH		 2373}
2374
cd28ab6a
SH		 2375/*
2376 * Receive one packet.
d571b694 2377 * For larger packets, get new buffer.
cd28ab6a 2378 */
497d7c86 2379static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2380 u16 length, u32 status)
2381{
497d7c86 2382 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2383 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2384 struct sk_buff *skb = NULL;
d6532232
SH		 2385 u16 count = (status & GMR_FS_LEN) >> 16;
2386
2387#ifdef SKY2_VLAN_TAG_USED
2388 /* Account for vlan tag */
2389 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2390 count -= VLAN_HLEN;
2391#endif
cd28ab6a 2392
6c35abae
JP		 2393 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2394 "rx slot %u status 0x%x len %d\n",
2395 sky2->rx_next, status, length);
cd28ab6a 2396
793b883e 2397 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2398 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2399
3b12e014
SH		 2400 /* This chip has hardware problems that generates bogus status.
2401 * So do only marginal checking and expect higher level protocols
2402 * to handle crap frames.
2403 */
2404 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2405 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2406 length != count)
2407 goto okay;
2408
42eeea01 2409 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2410 goto error;
2411
42eeea01
SH		 2412 if (!(status & GMR_FS_RX_OK))
2413 goto resubmit;
2414
d6532232
SH		 2415 /* if length reported by DMA does not match PHY, packet was truncated */
2416 if (length != count)
3b12e014 2417 goto len_error;
71749531 2418
3b12e014 2419okay:
14d0263f
SH		 2420 if (length < copybreak)
2421 skb = receive_copy(sky2, re, length);
2422 else
2423 skb = receive_new(sky2, re, length);
90c30335
SH		 2424
2425 dev->stats.rx_dropped += (skb == NULL);
2426
793b883e 2427resubmit:
14d0263f 2428 sky2_rx_submit(sky2, re);
79e57d32 2429
cd28ab6a
SH		 2430 return skb;
2431
3b12e014 2432len_error:
71749531
SH		 2433 /* Truncation of overlength packets
2434 causes PHY length to not match MAC length */
7138a0f5 2435 ++dev->stats.rx_length_errors;
6c35abae
JP		 2436 if (net_ratelimit())
2437 netif_info(sky2, rx_err, dev,
2438 "rx length error: status %#x length %d\n",
2439 status, length);
d6532232 2440 goto resubmit;
71749531 2441
cd28ab6a 2442error:
7138a0f5 2443 ++dev->stats.rx_errors;
b6d77734 2444 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2445 dev->stats.rx_over_errors++;
b6d77734
SH		 2446 goto resubmit;
2447 }
6e15b712 2448
6c35abae
JP		 2449 if (net_ratelimit())
2450 netif_info(sky2, rx_err, dev,
2451 "rx error, status 0x%x length %d\n", status, length);
793b883e
SH		 2452
2453 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2454 dev->stats.rx_length_errors++;
cd28ab6a 2455 if (status & GMR_FS_FRAGMENT)
7138a0f5 2456 dev->stats.rx_frame_errors++;
cd28ab6a 2457 if (status & GMR_FS_CRC_ERR)
7138a0f5 2458 dev->stats.rx_crc_errors++;
79e57d32 2459
793b883e 2460 goto resubmit;
cd28ab6a
SH		 2461}
2462
e07b1aa8
SH		 2463/* Transmit complete */
2464static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2465{
e07b1aa8 2466 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2467
8a0c9228 2468 if (netif_running(dev)) {
e07b1aa8 2469 sky2_tx_complete(sky2, last);
8a0c9228
MM		 2470
2471 /* Wake unless it's detached, and called e.g. from sky2_down() */
2472 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2473 netif_wake_queue(dev);
2474 }
cd28ab6a
SH		 2475}
2476
37e5a243
SH		 2477static inline void sky2_skb_rx(const struct sky2_port *sky2,
2478 u32 status, struct sk_buff *skb)
2479{
2480#ifdef SKY2_VLAN_TAG_USED
2481 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2482 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2483 if (skb->ip_summed == CHECKSUM_NONE)
2484 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2485 else
2486 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2487 vlan_tag, skb);
2488 return;
2489 }
2490#endif
2491 if (skb->ip_summed == CHECKSUM_NONE)
2492 netif_receive_skb(skb);
2493 else
2494 napi_gro_receive(&sky2->hw->napi, skb);
2495}
2496
bf15fe99
SH		 2497static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2498 unsigned packets, unsigned bytes)
2499{
2500 if (packets) {
2501 struct net_device *dev = hw->dev[port];
2502
2503 dev->stats.rx_packets += packets;
2504 dev->stats.rx_bytes += bytes;
2505 dev->last_rx = jiffies;
2506 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2507 }
2508}
2509
375c5688 2510static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2511{
2512 /* If this happens then driver assuming wrong format for chip type */
2513 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2514
2515 /* Both checksum counters are programmed to start at
2516 * the same offset, so unless there is a problem they
2517 * should match. This failure is an early indication that
2518 * hardware receive checksumming won't work.
2519 */
2520 if (likely((u16)(status >> 16) == (u16)status)) {
2521 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2522 skb->ip_summed = CHECKSUM_COMPLETE;
2523 skb->csum = le16_to_cpu(status);
2524 } else {
2525 dev_notice(&sky2->hw->pdev->dev,
2526 "%s: receive checksum problem (status = %#x)\n",
2527 sky2->netdev->name, status);
2528
2529 /* Disable checksum offload */
2530 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2531 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2532 BMU_DIS_RX_CHKSUM);
2533 }
2534}
2535
e07b1aa8 2536/* Process status response ring */
26691830 2537static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2538{
e07b1aa8 2539 int work_done = 0;
bf15fe99
SH		 2540 unsigned int total_bytes[2] = { 0 };
2541 unsigned int total_packets[2] = { 0 };
a8fd6266 2542
af2a58ac 2543 rmb();
26691830 2544 do {
55c9dd35 2545 struct sky2_port *sky2;
13210ce5 2546 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2547 unsigned port;
13210ce5 2548 struct net_device *dev;
cd28ab6a 2549 struct sk_buff *skb;
cd28ab6a
SH		 2550 u32 status;
2551 u16 length;
ab5adecb
SH		 2552 u8 opcode = le->opcode;
2553
2554 if (!(opcode & HW_OWNER))
2555 break;
cd28ab6a 2556
cb5d9547 2557 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2558
ab5adecb 2559 port = le->css & CSS_LINK_BIT;
69161611 2560 dev = hw->dev[port];
13210ce5 2561 sky2 = netdev_priv(dev);
f65b138c
SH		 2562 length = le16_to_cpu(le->length);
2563 status = le32_to_cpu(le->status);
cd28ab6a 2564
ab5adecb
SH		 2565 le->opcode = 0;
2566 switch (opcode & ~HW_OWNER) {
cd28ab6a 2567 case OP_RXSTAT:
bf15fe99
SH		 2568 total_packets[port]++;
2569 total_bytes[port] += length;
90c30335 2570
497d7c86 2571 skb = sky2_receive(dev, length, status);
90c30335 2572 if (!skb)
55c9dd35 2573 break;
13210ce5 2574
69161611 2575 /* This chip reports checksum status differently */
05745c4a 2576 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2577 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2578 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2579 (le->css & CSS_TCPUDPCSOK))
2580 skb->ip_summed = CHECKSUM_UNNECESSARY;
2581 else
2582 skb->ip_summed = CHECKSUM_NONE;
2583 }
2584
13210ce5 2585 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2586
37e5a243 2587 sky2_skb_rx(sky2, status, skb);
13210ce5 2588
22e11703 2589 /* Stop after net poll weight */
13210ce5
SH		 2590 if (++work_done >= to_do)
2591 goto exit_loop;
cd28ab6a
SH		 2592 break;
2593
d1f13708
SH		 2594#ifdef SKY2_VLAN_TAG_USED
2595 case OP_RXVLAN:
2596 sky2->rx_tag = length;
2597 break;
2598
2599 case OP_RXCHKSVLAN:
2600 sky2->rx_tag = length;
2601 /* fall through */
2602#endif
cd28ab6a 2603 case OP_RXCHKS:
375c5688 2604 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2605 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2606 break;
2607
2608 case OP_TXINDEXLE:
13b97b74 2609 /* TX index reports status for both ports */
f55925d7 2610 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2611 if (hw->dev[1])
2612 sky2_tx_done(hw->dev[1],
2613 ((status >> 24) & 0xff)
2614 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2615 break;
2616
cd28ab6a
SH		 2617 default:
2618 if (net_ratelimit())
ada1db5c 2619 pr_warning("unknown status opcode 0x%x\n", opcode);
cd28ab6a 2620 }
26691830 2621 } while (hw->st_idx != idx);
cd28ab6a 2622
fe2a24df
SH		 2623 /* Fully processed status ring so clear irq */
2624 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2625
13210ce5 2626exit_loop:
bf15fe99
SH		 2627 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2628 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2629
e07b1aa8 2630 return work_done;
cd28ab6a
SH		 2631}
2632
2633static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2634{
2635 struct net_device *dev = hw->dev[port];
2636
3be92a70 2637 if (net_ratelimit())
ada1db5c 2638 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
cd28ab6a
SH		 2639
2640 if (status & Y2_IS_PAR_RD1) {
3be92a70 2641 if (net_ratelimit())
ada1db5c 2642 netdev_err(dev, "ram data read parity error\n");
cd28ab6a
SH		 2643 /* Clear IRQ */
2644 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2645 }
2646
2647 if (status & Y2_IS_PAR_WR1) {
3be92a70 2648 if (net_ratelimit())
ada1db5c 2649 netdev_err(dev, "ram data write parity error\n");
cd28ab6a
SH		 2650
2651 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2652 }
2653
2654 if (status & Y2_IS_PAR_MAC1) {
3be92a70 2655 if (net_ratelimit())
ada1db5c 2656 netdev_err(dev, "MAC parity error\n");
cd28ab6a
SH		 2657 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2658 }
2659
2660 if (status & Y2_IS_PAR_RX1) {
3be92a70 2661 if (net_ratelimit())
ada1db5c 2662 netdev_err(dev, "RX parity error\n");
cd28ab6a
SH		 2663 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2664 }
2665
2666 if (status & Y2_IS_TCP_TXA1) {
3be92a70 2667 if (net_ratelimit())
ada1db5c 2668 netdev_err(dev, "TCP segmentation error\n");
cd28ab6a
SH		 2669 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2670 }
2671}
2672
2673static void sky2_hw_intr(struct sky2_hw *hw)
2674{
555382cb 2675 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2676 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2677 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2678
2679 status &= hwmsk;
cd28ab6a 2680
793b883e 2681 if (status & Y2_IS_TIST_OV)
cd28ab6a 2682 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2683
2684 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2685 u16 pci_err;
2686
a40ccc68 2687 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2688 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2689 if (net_ratelimit())
555382cb 2690 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2691 pci_err);
cd28ab6a 2692
b32f40c4 2693 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2694 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2695 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2696 }
2697
2698 if (status & Y2_IS_PCI_EXP) {
d571b694 2699 /* PCI-Express uncorrectable Error occurred */
555382cb 2700 u32 err;
cd28ab6a 2701
a40ccc68 2702 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2703 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2704 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2705 0xfffffffful);
3be92a70 2706 if (net_ratelimit())
555382cb 2707 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2708
7782c8c4 2709 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2710 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2711 }
2712
2713 if (status & Y2_HWE_L1_MASK)
2714 sky2_hw_error(hw, 0, status);
2715 status >>= 8;
2716 if (status & Y2_HWE_L1_MASK)
2717 sky2_hw_error(hw, 1, status);
2718}
2719
2720static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2721{
2722 struct net_device *dev = hw->dev[port];
2723 struct sky2_port *sky2 = netdev_priv(dev);
2724 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2725
6c35abae 2726 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
cd28ab6a 2727
a3caeada
SH		 2728 if (status & GM_IS_RX_CO_OV)
2729 gma_read16(hw, port, GM_RX_IRQ_SRC);
2730
2731 if (status & GM_IS_TX_CO_OV)
2732 gma_read16(hw, port, GM_TX_IRQ_SRC);
2733
cd28ab6a 2734 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2735 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2736 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2737 }
2738
2739 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2740 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2741 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2742 }
cd28ab6a
SH		 2743}
2744
40b01727 2745/* This should never happen it is a bug. */
c119731d 2746static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2747{
2748 struct net_device *dev = hw->dev[port];
c119731d 2749 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2750
ada1db5c 2751 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
c119731d
SH		 2752 dev->name, (unsigned) q, (unsigned) idx,
2753 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2754
40b01727 2755 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2756}
cd28ab6a 2757
75e80683
SH		 2758static int sky2_rx_hung(struct net_device *dev)
2759{
2760 struct sky2_port *sky2 = netdev_priv(dev);
2761 struct sky2_hw *hw = sky2->hw;
2762 unsigned port = sky2->port;
2763 unsigned rxq = rxqaddr[port];
2764 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2765 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2766 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2767 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2768
2769 /* If idle and MAC or PCI is stuck */
2770 if (sky2->check.last == dev->last_rx &&
2771 ((mac_rp == sky2->check.mac_rp &&
2772 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2773 /* Check if the PCI RX hang */
2774 (fifo_rp == sky2->check.fifo_rp &&
2775 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
ada1db5c
JP		 2776 netdev_printk(KERN_DEBUG, dev,
2777 "hung mac %d:%d fifo %d (%d:%d)\n",
2778 mac_lev, mac_rp, fifo_lev,
2779 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
75e80683
SH		 2780 return 1;
2781 } else {
2782 sky2->check.last = dev->last_rx;
2783 sky2->check.mac_rp = mac_rp;
2784 sky2->check.mac_lev = mac_lev;
2785 sky2->check.fifo_rp = fifo_rp;
2786 sky2->check.fifo_lev = fifo_lev;
2787 return 0;
2788 }
2789}
2790
32c2c300 2791static void sky2_watchdog(unsigned long arg)
d27ed387 2792{
01bd7564 2793 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2794
75e80683 2795 /* Check for lost IRQ once a second */
32c2c300 2796 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2797 napi_schedule(&hw->napi);
75e80683
SH		 2798 } else {
2799 int i, active = 0;
2800
2801 for (i = 0; i < hw->ports; i++) {
bea3348e 2802 struct net_device *dev = hw->dev[i];
75e80683
SH		 2803 if (!netif_running(dev))
2804 continue;
2805 ++active;
2806
2807 /* For chips with Rx FIFO, check if stuck */
39dbd958 2808 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683 2809 sky2_rx_hung(dev)) {
ada1db5c 2810 netdev_info(dev, "receiver hang detected\n");
75e80683
SH		 2811 schedule_work(&hw->restart_work);
2812 return;
2813 }
2814 }
2815
2816 if (active == 0)
2817 return;
32c2c300 2818 }
01bd7564 2819
75e80683 2820 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2821}
2822
40b01727
SH		 2823/* Hardware/software error handling */
2824static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2825{
40b01727
SH		 2826 if (net_ratelimit())
2827 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2828
1e5f1283
SH		 2829 if (status & Y2_IS_HW_ERR)
2830 sky2_hw_intr(hw);
d257924e 2831
1e5f1283
SH		 2832 if (status & Y2_IS_IRQ_MAC1)
2833 sky2_mac_intr(hw, 0);
cd28ab6a 2834
1e5f1283
SH		 2835 if (status & Y2_IS_IRQ_MAC2)
2836 sky2_mac_intr(hw, 1);
cd28ab6a 2837
1e5f1283 2838 if (status & Y2_IS_CHK_RX1)
c119731d 2839 sky2_le_error(hw, 0, Q_R1);
d257924e 2840
1e5f1283 2841 if (status & Y2_IS_CHK_RX2)
c119731d 2842 sky2_le_error(hw, 1, Q_R2);
d257924e 2843
1e5f1283 2844 if (status & Y2_IS_CHK_TXA1)
c119731d 2845 sky2_le_error(hw, 0, Q_XA1);
d257924e 2846
1e5f1283 2847 if (status & Y2_IS_CHK_TXA2)
c119731d 2848 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2849}
2850
bea3348e 2851static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2852{
bea3348e 2853 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2854 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2855 int work_done = 0;
26691830 2856 u16 idx;
40b01727
SH		 2857
2858 if (unlikely(status & Y2_IS_ERROR))
2859 sky2_err_intr(hw, status);
2860
2861 if (status & Y2_IS_IRQ_PHY1)
2862 sky2_phy_intr(hw, 0);
2863
2864 if (status & Y2_IS_IRQ_PHY2)
2865 sky2_phy_intr(hw, 1);
cd28ab6a 2866
0f5aac70
SH		 2867 if (status & Y2_IS_PHY_QLNK)
2868 sky2_qlink_intr(hw);
2869
26691830
SH		 2870 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2871 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2872
2873 if (work_done >= work_limit)
26691830
SH		 2874 goto done;
2875 }
6f535763 2876
26691830
SH		 2877 napi_complete(napi);
2878 sky2_read32(hw, B0_Y2_SP_LISR);
2879done:
6f535763 2880
bea3348e 2881 return work_done;
e07b1aa8
SH		 2882}
2883
7d12e780 2884static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2885{
2886 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2887 u32 status;
2888
2889 /* Reading this mask interrupts as side effect */
2890 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2891 if (status == 0 || status == ~0)
2892 return IRQ_NONE;
793b883e 2893
e07b1aa8 2894 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2895
2896 napi_schedule(&hw->napi);
793b883e 2897
cd28ab6a
SH		 2898 return IRQ_HANDLED;
2899}
2900
2901#ifdef CONFIG_NET_POLL_CONTROLLER
2902static void sky2_netpoll(struct net_device *dev)
2903{
2904 struct sky2_port *sky2 = netdev_priv(dev);
2905
bea3348e 2906 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2907}
2908#endif
2909
2910/* Chip internal frequency for clock calculations */
05745c4a 2911static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2912{
793b883e 2913 switch (hw->chip_id) {
cd28ab6a 2914 case CHIP_ID_YUKON_EC:
5a5b1ea0 2915 case CHIP_ID_YUKON_EC_U:
93745494 2916 case CHIP_ID_YUKON_EX:
ed4d4161 2917 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2918 case CHIP_ID_YUKON_UL_2:
0f5aac70 2919 case CHIP_ID_YUKON_OPT:
05745c4a
SH		 2920 return 125;
2921
cd28ab6a 2922 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2923 return 100;
2924
2925 case CHIP_ID_YUKON_FE_P:
2926 return 50;
2927
2928 case CHIP_ID_YUKON_XL:
2929 return 156;
2930
2931 default:
2932 BUG();
cd28ab6a
SH		 2933 }
2934}
2935
fb17358f 2936static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2937{
fb17358f 2938 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2939}
2940
fb17358f 2941static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2942{
fb17358f 2943 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2944}
2945
fb17358f 2946
e3173832 2947static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2948{
b89165f2 2949 u8 t8;
cd28ab6a 2950
167f53d0 2951 /* Enable all clocks and check for bad PCI access */
b32f40c4 2952 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2953
cd28ab6a 2954 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2955
cd28ab6a 2956 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2957 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2958
2959 switch(hw->chip_id) {
2960 case CHIP_ID_YUKON_XL:
39dbd958 2961 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2962 break;
2963
2964 case CHIP_ID_YUKON_EC_U:
2965 hw->flags = SKY2_HW_GIGABIT
2966 | SKY2_HW_NEWER_PHY
2967 | SKY2_HW_ADV_POWER_CTL;
2968 break;
2969
2970 case CHIP_ID_YUKON_EX:
2971 hw->flags = SKY2_HW_GIGABIT
2972 | SKY2_HW_NEWER_PHY
2973 | SKY2_HW_NEW_LE
2974 | SKY2_HW_ADV_POWER_CTL;
2975
2976 /* New transmit checksum */
2977 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2978 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2979 break;
2980
2981 case CHIP_ID_YUKON_EC:
2982 /* This rev is really old, and requires untested workarounds */
2983 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2984 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2985 return -EOPNOTSUPP;
2986 }
39dbd958 2987 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2988 break;
2989
2990 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2991 break;
2992
05745c4a
SH		 2993 case CHIP_ID_YUKON_FE_P:
2994 hw->flags = SKY2_HW_NEWER_PHY
2995 | SKY2_HW_NEW_LE
2996 | SKY2_HW_AUTO_TX_SUM
2997 | SKY2_HW_ADV_POWER_CTL;
2998 break;
ed4d4161
SH		 2999
3000 case CHIP_ID_YUKON_SUPR:
3001 hw->flags = SKY2_HW_GIGABIT
3002 | SKY2_HW_NEWER_PHY
3003 | SKY2_HW_NEW_LE
3004 | SKY2_HW_AUTO_TX_SUM
3005 | SKY2_HW_ADV_POWER_CTL;
3006 break;
3007
0ce8b98d 3008 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 3009 hw->flags = SKY2_HW_GIGABIT
3010 | SKY2_HW_ADV_POWER_CTL;
3011 break;
3012
0f5aac70 3013 case CHIP_ID_YUKON_OPT:
0ce8b98d 3014 hw->flags = SKY2_HW_GIGABIT
b338682d 3015 | SKY2_HW_NEW_LE
0ce8b98d
SH		 3016 | SKY2_HW_ADV_POWER_CTL;
3017 break;
3018
ea76e635 3019 default:
b02a9258
SH		 3020 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3021 hw->chip_id);
cd28ab6a
SH		 3022 return -EOPNOTSUPP;
3023 }
3024
ea76e635
SH		 3025 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3026 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3027 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3028
e3173832
SH		 3029 hw->ports = 1;
3030 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3031 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3032 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3033 ++hw->ports;
3034 }
3035
74a61ebf
MM		 3036 if (sky2_read8(hw, B2_E_0))
3037 hw->flags |= SKY2_HW_RAM_BUFFER;
3038
e3173832
SH		 3039 return 0;
3040}
3041
3042static void sky2_reset(struct sky2_hw *hw)
3043{
555382cb 3044 struct pci_dev *pdev = hw->pdev;
e3173832 3045 u16 status;
555382cb
SH		 3046 int i, cap;
3047 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3048
cd28ab6a 3049 /* disable ASF */
acd12dde 3050 if (hw->chip_id == CHIP_ID_YUKON_EX
3051 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3052 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3053 status = sky2_read16(hw, HCU_CCSR);
3054 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3055 HCU_CCSR_UC_STATE_MSK);
acd12dde 3056 /*
3057 * CPU clock divider shouldn't be used because
3058 * - ASF firmware may malfunction
3059 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3060 */
3061 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3062 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3063 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3064 } else
3065 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3066 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3067
3068 /* do a SW reset */
3069 sky2_write8(hw, B0_CTST, CS_RST_SET);
3070 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3071
ac93a394
SH		 3072 /* allow writes to PCI config */
3073 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3074
cd28ab6a 3075 /* clear PCI errors, if any */
b32f40c4 3076 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3077 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3078 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3079
3080 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3081
555382cb
SH		 3082 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3083 if (cap) {
7782c8c4
SH		 3084 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3085 0xfffffffful);
555382cb
SH		 3086
3087 /* If error bit is stuck on ignore it */
3088 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3089 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3090 else
555382cb
SH		 3091 hwe_mask |= Y2_IS_PCI_EXP;
3092 }
cd28ab6a 3093
ae306cca 3094 sky2_power_on(hw);
a40ccc68 3095 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3096
3097 for (i = 0; i < hw->ports; i++) {
3098 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3099 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3100
ed4d4161
SH		 3101 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3102 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3103 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3104 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3105 | GMC_BYP_RETR_ON);
877c8570
SH		 3106
3107 }
3108
3109 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3110 /* enable MACSec clock gating */
3111 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3112 }
3113
0f5aac70
SH		 3114 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3115 u16 reg;
3116 u32 msk;
3117
3118 if (hw->chip_rev == 0) {
3119 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3120 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3121
3122 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3123 reg = 10;
3124 } else {
3125 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3126 reg = 3;
3127 }
3128
3129 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3130
3131 /* reset PHY Link Detect */
a40ccc68 3132 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3133 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3134 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3135 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3136
3137
3138 /* enable PHY Quick Link */
3139 msk = sky2_read32(hw, B0_IMSK);
3140 msk |= Y2_IS_PHY_QLNK;
3141 sky2_write32(hw, B0_IMSK, msk);
3142
3143 /* check if PSMv2 was running before */
3144 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3145 if (reg & PCI_EXP_LNKCTL_ASPMC) {
8b055431 3146 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
0f5aac70
SH		 3147 /* restore the PCIe Link Control register */
3148 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3149 }
a40ccc68 3150 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3151
3152 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3153 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3154 }
3155
793b883e
SH		 3156 /* Clear I2C IRQ noise */
3157 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3158
3159 /* turn off hardware timer (unused) */
3160 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3161 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3162
69634ee7
SH		 3163 /* Turn off descriptor polling */
3164 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3165
3166 /* Turn off receive timestamp */
3167 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3168 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3169
3170 /* enable the Tx Arbiters */
3171 for (i = 0; i < hw->ports; i++)
3172 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3173
3174 /* Initialize ram interface */
3175 for (i = 0; i < hw->ports; i++) {
793b883e 3176 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3177
3178 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3179 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3180 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3181 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3182 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3183 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3184 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3185 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3186 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3187 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3188 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3189 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3190 }
3191
555382cb 3192 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3193
cd28ab6a 3194 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3195 sky2_gmac_reset(hw, i);
cd28ab6a 3196
cd28ab6a
SH		 3197 memset(hw->st_le, 0, STATUS_LE_BYTES);
3198 hw->st_idx = 0;
3199
3200 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3201 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3202
3203 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3204 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3205
3206 /* Set the list last index */
793b883e 3207 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3208
290d4de5
SH		 3209 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3210 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3211
290d4de5
SH		 3212 /* set Status-FIFO ISR watermark */
3213 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3214 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3215 else
3216 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3217
290d4de5 3218 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3219 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3220 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3221
793b883e 3222 /* enable status unit */
cd28ab6a
SH		 3223 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3224
3225 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3226 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3227 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3228}
3229
af18d8b8
SH		 3230/* Take device down (offline).
3231 * Equivalent to doing dev_stop() but this does not
3232 * inform upper layers of the transistion.
3233 */
3234static void sky2_detach(struct net_device *dev)
3235{
3236 if (netif_running(dev)) {
c36531b9 3237 netif_tx_lock(dev);
af18d8b8 3238 netif_device_detach(dev); /* stop txq */
c36531b9 3239 netif_tx_unlock(dev);
af18d8b8
SH		 3240 sky2_down(dev);
3241 }
3242}
3243
3244/* Bring device back after doing sky2_detach */
3245static int sky2_reattach(struct net_device *dev)
3246{
3247 int err = 0;
3248
3249 if (netif_running(dev)) {
3250 err = sky2_up(dev);
3251 if (err) {
ada1db5c 3252 netdev_info(dev, "could not restart %d\n", err);
af18d8b8
SH		 3253 dev_close(dev);
3254 } else {
3255 netif_device_attach(dev);
3256 sky2_set_multicast(dev);
3257 }
3258 }
3259
3260 return err;
3261}
3262
81906791
SH		 3263static void sky2_restart(struct work_struct *work)
3264{
3265 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
8a0c9228 3266 u32 imask;
af18d8b8 3267 int i;
81906791 3268
81906791 3269 rtnl_lock();
81906791 3270
8cfcbe99 3271 napi_disable(&hw->napi);
8a0c9228
MM		 3272 synchronize_irq(hw->pdev->irq);
3273 imask = sky2_read32(hw, B0_IMSK);
8cfcbe99 3274 sky2_write32(hw, B0_IMSK, 0);
8a0c9228
MM		 3275
3276 for (i = 0; i < hw->ports; i++) {
3277 struct net_device *dev = hw->dev[i];
3278 struct sky2_port *sky2 = netdev_priv(dev);
3279
3280 if (!netif_running(dev))
3281 continue;
3282
3283 netif_carrier_off(dev);
3284 netif_tx_disable(dev);
3285 sky2_hw_down(sky2);
3286 }
3287
81906791 3288 sky2_reset(hw);
81906791 3289
8a0c9228
MM		 3290 for (i = 0; i < hw->ports; i++) {
3291 struct net_device *dev = hw->dev[i];
3292 struct sky2_port *sky2 = netdev_priv(dev);
3293
3294 if (!netif_running(dev))
3295 continue;
3296
3297 sky2_hw_up(sky2);
3298 netif_wake_queue(dev);
3299 }
3300
3301 sky2_write32(hw, B0_IMSK, imask);
3302 sky2_read32(hw, B0_IMSK);
3303
3304 sky2_read32(hw, B0_Y2_SP_LISR);
3305 napi_enable(&hw->napi);
81906791 3306
81906791
SH		 3307 rtnl_unlock();
3308}
3309
e3173832
SH		 3310static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3311{
3312 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3313}
3314
3315static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3316{
3317 const struct sky2_port *sky2 = netdev_priv(dev);
3318
3319 wol->supported = sky2_wol_supported(sky2->hw);
3320 wol->wolopts = sky2->wol;
3321}
3322
3323static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3324{
3325 struct sky2_port *sky2 = netdev_priv(dev);
3326 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3327
8e95a202
JP		 3328 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3329 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3330 return -EOPNOTSUPP;
3331
3332 sky2->wol = wol->wolopts;
cd28ab6a
SH		 3333 return 0;
3334}
3335
28bd181a 3336static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3337{
b89165f2
SH		 3338 if (sky2_is_copper(hw)) {
3339 u32 modes = SUPPORTED_10baseT_Half
3340 | SUPPORTED_10baseT_Full
3341 | SUPPORTED_100baseT_Half
3342 | SUPPORTED_100baseT_Full
3343 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3344
ea76e635 3345 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3346 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3347 | SUPPORTED_1000baseT_Full;
3348 return modes;
cd28ab6a 3349 } else
b89165f2
SH		 3350 return SUPPORTED_1000baseT_Half
3351 | SUPPORTED_1000baseT_Full
3352 | SUPPORTED_Autoneg
3353 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3354}
3355
793b883e 3356static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3357{
3358 struct sky2_port *sky2 = netdev_priv(dev);
3359 struct sky2_hw *hw = sky2->hw;
3360
3361 ecmd->transceiver = XCVR_INTERNAL;
3362 ecmd->supported = sky2_supported_modes(hw);
3363 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3364 if (sky2_is_copper(hw)) {
cd28ab6a 3365 ecmd->port = PORT_TP;
b89165f2
SH		 3366 ecmd->speed = sky2->speed;
3367 } else {
3368 ecmd->speed = SPEED_1000;
cd28ab6a 3369 ecmd->port = PORT_FIBRE;
b89165f2 3370 }
cd28ab6a
SH		 3371
3372 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3373 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3374 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3375 ecmd->duplex = sky2->duplex;
3376 return 0;
3377}
3378
3379static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3380{
3381 struct sky2_port *sky2 = netdev_priv(dev);
3382 const struct sky2_hw *hw = sky2->hw;
3383 u32 supported = sky2_supported_modes(hw);
3384
3385 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3386 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3387 ecmd->advertising = supported;
3388 sky2->duplex = -1;
3389 sky2->speed = -1;
3390 } else {
3391 u32 setting;
3392
793b883e 3393 switch (ecmd->speed) {
cd28ab6a
SH		 3394 case SPEED_1000:
3395 if (ecmd->duplex == DUPLEX_FULL)
3396 setting = SUPPORTED_1000baseT_Full;
3397 else if (ecmd->duplex == DUPLEX_HALF)
3398 setting = SUPPORTED_1000baseT_Half;
3399 else
3400 return -EINVAL;
3401 break;
3402 case SPEED_100:
3403 if (ecmd->duplex == DUPLEX_FULL)
3404 setting = SUPPORTED_100baseT_Full;
3405 else if (ecmd->duplex == DUPLEX_HALF)
3406 setting = SUPPORTED_100baseT_Half;
3407 else
3408 return -EINVAL;
3409 break;
3410
3411 case SPEED_10:
3412 if (ecmd->duplex == DUPLEX_FULL)
3413 setting = SUPPORTED_10baseT_Full;
3414 else if (ecmd->duplex == DUPLEX_HALF)
3415 setting = SUPPORTED_10baseT_Half;
3416 else
3417 return -EINVAL;
3418 break;
3419 default:
3420 return -EINVAL;
3421 }
3422
3423 if ((setting & supported) == 0)
3424 return -EINVAL;
3425
3426 sky2->speed = ecmd->speed;
3427 sky2->duplex = ecmd->duplex;
0ea065e5 3428 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3429 }
3430
cd28ab6a
SH		 3431 sky2->advertising = ecmd->advertising;
3432
d1b139c0 3433 if (netif_running(dev)) {
1b537565 3434 sky2_phy_reinit(sky2);
d1b139c0
SH		 3435 sky2_set_multicast(dev);
3436 }
cd28ab6a
SH		 3437
3438 return 0;
3439}
3440
3441static void sky2_get_drvinfo(struct net_device *dev,
3442 struct ethtool_drvinfo *info)
3443{
3444 struct sky2_port *sky2 = netdev_priv(dev);
3445
3446 strcpy(info->driver, DRV_NAME);
3447 strcpy(info->version, DRV_VERSION);
3448 strcpy(info->fw_version, "N/A");
3449 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3450}
3451
3452static const struct sky2_stat {
793b883e
SH		 3453 char name[ETH_GSTRING_LEN];
3454 u16 offset;
cd28ab6a
SH		 3455} sky2_stats[] = {
3456 { "tx_bytes", GM_TXO_OK_HI },
3457 { "rx_bytes", GM_RXO_OK_HI },
3458 { "tx_broadcast", GM_TXF_BC_OK },
3459 { "rx_broadcast", GM_RXF_BC_OK },
3460 { "tx_multicast", GM_TXF_MC_OK },
3461 { "rx_multicast", GM_RXF_MC_OK },
3462 { "tx_unicast", GM_TXF_UC_OK },
3463 { "rx_unicast", GM_RXF_UC_OK },
3464 { "tx_mac_pause", GM_TXF_MPAUSE },
3465 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3466 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3467 { "late_collision",GM_TXF_LAT_COL },
3468 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3469 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3470 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3471
d2604540 3472 { "rx_short", GM_RXF_SHT },
cd28ab6a 3473 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3474 { "rx_64_byte_packets", GM_RXF_64B },
3475 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3476 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3477 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3478 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3479 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3480 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3481 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3482 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3483 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3484 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3485
3486 { "tx_64_byte_packets", GM_TXF_64B },
3487 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3488 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3489 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3490 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3491 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3492 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3493 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3494};
3495
cd28ab6a
SH		 3496static u32 sky2_get_rx_csum(struct net_device *dev)
3497{
3498 struct sky2_port *sky2 = netdev_priv(dev);
3499
0ea065e5 3500 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3501}
3502
3503static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3504{
3505 struct sky2_port *sky2 = netdev_priv(dev);
3506
0ea065e5
SH		 3507 if (data)
3508 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3509 else
3510 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3511
cd28ab6a
SH		 3512 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3513 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3514
3515 return 0;
3516}
3517
3518static u32 sky2_get_msglevel(struct net_device *netdev)
3519{
3520 struct sky2_port *sky2 = netdev_priv(netdev);
3521 return sky2->msg_enable;
3522}
3523
9a7ae0a9
SH		 3524static int sky2_nway_reset(struct net_device *dev)
3525{
3526 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3527
0ea065e5 3528 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3529 return -EINVAL;
3530
1b537565 3531 sky2_phy_reinit(sky2);
d1b139c0 3532 sky2_set_multicast(dev);
9a7ae0a9
SH		 3533
3534 return 0;
3535}
3536
793b883e 3537static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3538{
3539 struct sky2_hw *hw = sky2->hw;
3540 unsigned port = sky2->port;
3541 int i;
3542
3543 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3544 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3545 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3546 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3547
793b883e 3548 for (i = 2; i < count; i++)
cd28ab6a
SH		 3549 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3550}
3551
cd28ab6a
SH		 3552static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3553{
3554 struct sky2_port *sky2 = netdev_priv(netdev);
3555 sky2->msg_enable = value;
3556}
3557
b9f2c044 3558static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3559{
b9f2c044
JG		 3560 switch (sset) {
3561 case ETH_SS_STATS:
3562 return ARRAY_SIZE(sky2_stats);
3563 default:
3564 return -EOPNOTSUPP;
3565 }
cd28ab6a
SH		 3566}
3567
3568static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3569 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3570{
3571 struct sky2_port *sky2 = netdev_priv(dev);
3572
793b883e 3573 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3574}
3575
793b883e 3576static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3577{
3578 int i;
3579
3580 switch (stringset) {
3581 case ETH_SS_STATS:
3582 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3583 memcpy(data + i * ETH_GSTRING_LEN,
3584 sky2_stats[i].name, ETH_GSTRING_LEN);
3585 break;
3586 }
3587}
3588
cd28ab6a
SH		 3589static int sky2_set_mac_address(struct net_device *dev, void *p)
3590{
3591 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3592 struct sky2_hw *hw = sky2->hw;
3593 unsigned port = sky2->port;
3594 const struct sockaddr *addr = p;
cd28ab6a
SH		 3595
3596 if (!is_valid_ether_addr(addr->sa_data))
3597 return -EADDRNOTAVAIL;
3598
cd28ab6a 3599 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3600 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3601 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3602 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3603 dev->dev_addr, ETH_ALEN);
1b537565 3604
a8ab1ec0
SH		 3605 /* virtual address for data */
3606 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3607
3608 /* physical address: used for pause frames */
3609 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3610
3611 return 0;
cd28ab6a
SH		 3612}
3613
a052b52f
SH		 3614static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3615{
3616 u32 bit;
3617
3618 bit = ether_crc(ETH_ALEN, addr) & 63;
3619 filter[bit >> 3] |= 1 << (bit & 7);
3620}
3621
cd28ab6a
SH		 3622static void sky2_set_multicast(struct net_device *dev)
3623{
3624 struct sky2_port *sky2 = netdev_priv(dev);
3625 struct sky2_hw *hw = sky2->hw;
3626 unsigned port = sky2->port;
5508590c 3627 struct dev_mc_list *list;
cd28ab6a
SH		 3628 u16 reg;
3629 u8 filter[8];
a052b52f
SH		 3630 int rx_pause;
3631 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3632
a052b52f 3633 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3634 memset(filter, 0, sizeof(filter));
3635
3636 reg = gma_read16(hw, port, GM_RX_CTRL);
3637 reg |= GM_RXCR_UCF_ENA;
3638
d571b694 3639 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3640 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3641 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3642 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3643 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3644 reg &= ~GM_RXCR_MCF_ENA;
3645 else {
cd28ab6a
SH		 3646 reg |= GM_RXCR_MCF_ENA;
3647
a052b52f
SH		 3648 if (rx_pause)
3649 sky2_add_filter(filter, pause_mc_addr);
3650
5508590c 3651 netdev_for_each_mc_addr(list, dev)
a052b52f 3652 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3653 }
3654
cd28ab6a 3655 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3656 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3657 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3658 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3659 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3660 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3661 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3662 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3663
3664 gma_write16(hw, port, GM_RX_CTRL, reg);
3665}
3666
3667/* Can have one global because blinking is controlled by
3668 * ethtool and that is always under RTNL mutex
3669 */
a84d0a3d 3670static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3671{
a84d0a3d
SH		 3672 struct sky2_hw *hw = sky2->hw;
3673 unsigned port = sky2->port;
793b883e 3674
a84d0a3d
SH		 3675 spin_lock_bh(&sky2->phy_lock);
3676 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3677 hw->chip_id == CHIP_ID_YUKON_EX ||
3678 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3679 u16 pg;
793b883e
SH		 3680 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3681 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3682
a84d0a3d
SH		 3683 switch (mode) {
3684 case MO_LED_OFF:
3685 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3686 PHY_M_LEDC_LOS_CTRL(8) |
3687 PHY_M_LEDC_INIT_CTRL(8) |
3688 PHY_M_LEDC_STA1_CTRL(8) |
3689 PHY_M_LEDC_STA0_CTRL(8));
3690 break;
3691 case MO_LED_ON:
3692 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3693 PHY_M_LEDC_LOS_CTRL(9) |
3694 PHY_M_LEDC_INIT_CTRL(9) |
3695 PHY_M_LEDC_STA1_CTRL(9) |
3696 PHY_M_LEDC_STA0_CTRL(9));
3697 break;
3698 case MO_LED_BLINK:
3699 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3700 PHY_M_LEDC_LOS_CTRL(0xa) |
3701 PHY_M_LEDC_INIT_CTRL(0xa) |
3702 PHY_M_LEDC_STA1_CTRL(0xa) |
3703 PHY_M_LEDC_STA0_CTRL(0xa));
3704 break;
3705 case MO_LED_NORM:
3706 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3707 PHY_M_LEDC_LOS_CTRL(1) |
3708 PHY_M_LEDC_INIT_CTRL(8) |
3709 PHY_M_LEDC_STA1_CTRL(7) |
3710 PHY_M_LEDC_STA0_CTRL(7));
3711 }
793b883e 3712
a84d0a3d
SH		 3713 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3714 } else
7d2e3cb7 3715 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3716 PHY_M_LED_MO_DUP(mode) |
3717 PHY_M_LED_MO_10(mode) |
3718 PHY_M_LED_MO_100(mode) |
3719 PHY_M_LED_MO_1000(mode) |
3720 PHY_M_LED_MO_RX(mode) |
3721 PHY_M_LED_MO_TX(mode));
3722
3723 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3724}
3725
3726/* blink LED's for finding board */
3727static int sky2_phys_id(struct net_device *dev, u32 data)
3728{
3729 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3730 unsigned int i;
cd28ab6a 3731
a84d0a3d
SH		 3732 if (data == 0)
3733 data = UINT_MAX;
cd28ab6a 3734
a84d0a3d
SH		 3735 for (i = 0; i < data; i++) {
3736 sky2_led(sky2, MO_LED_ON);
3737 if (msleep_interruptible(500))
3738 break;
3739 sky2_led(sky2, MO_LED_OFF);
3740 if (msleep_interruptible(500))
3741 break;
793b883e 3742 }
a84d0a3d 3743 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3744
3745 return 0;
3746}
3747
3748static void sky2_get_pauseparam(struct net_device *dev,
3749 struct ethtool_pauseparam *ecmd)
3750{
3751 struct sky2_port *sky2 = netdev_priv(dev);
3752
16ad91e1
SH		 3753 switch (sky2->flow_mode) {
3754 case FC_NONE:
3755 ecmd->tx_pause = ecmd->rx_pause = 0;
3756 break;
3757 case FC_TX:
3758 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3759 break;
3760 case FC_RX:
3761 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3762 break;
3763 case FC_BOTH:
3764 ecmd->tx_pause = ecmd->rx_pause = 1;
3765 }
3766
0ea065e5
SH		 3767 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3768 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3769}
3770
3771static int sky2_set_pauseparam(struct net_device *dev,
3772 struct ethtool_pauseparam *ecmd)
3773{
3774 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3775
0ea065e5
SH		 3776 if (ecmd->autoneg == AUTONEG_ENABLE)
3777 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3778 else
3779 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3780
16ad91e1 3781 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3782
16ad91e1
SH		 3783 if (netif_running(dev))
3784 sky2_phy_reinit(sky2);
cd28ab6a 3785
2eaba1a2 3786 return 0;
cd28ab6a
SH		 3787}
3788
fb17358f
SH		 3789static int sky2_get_coalesce(struct net_device *dev,
3790 struct ethtool_coalesce *ecmd)
3791{
3792 struct sky2_port *sky2 = netdev_priv(dev);
3793 struct sky2_hw *hw = sky2->hw;
3794
3795 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3796 ecmd->tx_coalesce_usecs = 0;
3797 else {
3798 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3799 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3800 }
3801 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3802
3803 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3804 ecmd->rx_coalesce_usecs = 0;
3805 else {
3806 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3807 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3808 }
3809 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3810
3811 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3812 ecmd->rx_coalesce_usecs_irq = 0;
3813 else {
3814 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3815 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3816 }
3817
3818 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3819
3820 return 0;
3821}
3822
3823/* Note: this affect both ports */
3824static int sky2_set_coalesce(struct net_device *dev,
3825 struct ethtool_coalesce *ecmd)
3826{
3827 struct sky2_port *sky2 = netdev_priv(dev);
3828 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3829 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3830
77b3d6a2
SH		 3831 if (ecmd->tx_coalesce_usecs > tmax ||
3832 ecmd->rx_coalesce_usecs > tmax ||
3833 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3834 return -EINVAL;
3835
ee5f68fe 3836 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3837 return -EINVAL;
ff81fbbe 3838 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3839 return -EINVAL;
ff81fbbe 3840 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3841 return -EINVAL;
3842
3843 if (ecmd->tx_coalesce_usecs == 0)
3844 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3845 else {
3846 sky2_write32(hw, STAT_TX_TIMER_INI,
3847 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3848 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3849 }
3850 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3851
3852 if (ecmd->rx_coalesce_usecs == 0)
3853 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3854 else {
3855 sky2_write32(hw, STAT_LEV_TIMER_INI,
3856 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3857 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3858 }
3859 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3860
3861 if (ecmd->rx_coalesce_usecs_irq == 0)
3862 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3863 else {
d28d4870 3864 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3865 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3866 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3867 }
3868 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3869 return 0;
3870}
3871
793b883e
SH		 3872static void sky2_get_ringparam(struct net_device *dev,
3873 struct ethtool_ringparam *ering)
3874{
3875 struct sky2_port *sky2 = netdev_priv(dev);
3876
3877 ering->rx_max_pending = RX_MAX_PENDING;
3878 ering->rx_mini_max_pending = 0;
3879 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3880 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3881
3882 ering->rx_pending = sky2->rx_pending;
3883 ering->rx_mini_pending = 0;
3884 ering->rx_jumbo_pending = 0;
3885 ering->tx_pending = sky2->tx_pending;
3886}
3887
3888static int sky2_set_ringparam(struct net_device *dev,
3889 struct ethtool_ringparam *ering)
3890{
3891 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3892
3893 if (ering->rx_pending > RX_MAX_PENDING ||
3894 ering->rx_pending < 8 ||
ee5f68fe
SH		 3895 ering->tx_pending < TX_MIN_PENDING ||
3896 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3897 return -EINVAL;
3898
af18d8b8 3899 sky2_detach(dev);
793b883e
SH		 3900
3901 sky2->rx_pending = ering->rx_pending;
3902 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3903 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3904
af18d8b8 3905 return sky2_reattach(dev);
793b883e
SH		 3906}
3907
793b883e
SH		 3908static int sky2_get_regs_len(struct net_device *dev)
3909{
6e4cbb34 3910 return 0x4000;
793b883e
SH		 3911}
3912
c32bbff8
MM		 3913static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3914{
3915 /* This complicated switch statement is to make sure and
3916 * only access regions that are unreserved.
3917 * Some blocks are only valid on dual port cards.
3918 */
3919 switch (b) {
3920 /* second port */
3921 case 5: /* Tx Arbiter 2 */
3922 case 9: /* RX2 */
3923 case 14 ... 15: /* TX2 */
3924 case 17: case 19: /* Ram Buffer 2 */
3925 case 22 ... 23: /* Tx Ram Buffer 2 */
3926 case 25: /* Rx MAC Fifo 1 */
3927 case 27: /* Tx MAC Fifo 2 */
3928 case 31: /* GPHY 2 */
3929 case 40 ... 47: /* Pattern Ram 2 */
3930 case 52: case 54: /* TCP Segmentation 2 */
3931 case 112 ... 116: /* GMAC 2 */
3932 return hw->ports > 1;
3933
3934 case 0: /* Control */
3935 case 2: /* Mac address */
3936 case 4: /* Tx Arbiter 1 */
3937 case 7: /* PCI express reg */
3938 case 8: /* RX1 */
3939 case 12 ... 13: /* TX1 */
3940 case 16: case 18:/* Rx Ram Buffer 1 */
3941 case 20 ... 21: /* Tx Ram Buffer 1 */
3942 case 24: /* Rx MAC Fifo 1 */
3943 case 26: /* Tx MAC Fifo 1 */
3944 case 28 ... 29: /* Descriptor and status unit */
3945 case 30: /* GPHY 1*/
3946 case 32 ... 39: /* Pattern Ram 1 */
3947 case 48: case 50: /* TCP Segmentation 1 */
3948 case 56 ... 60: /* PCI space */
3949 case 80 ... 84: /* GMAC 1 */
3950 return 1;
3951
3952 default:
3953 return 0;
3954 }
3955}
3956
793b883e
SH		 3957/*
3958 * Returns copy of control register region
3ead5db7 3959 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3960 */
3961static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3962 void *p)
3963{
3964 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3965 const void __iomem *io = sky2->hw->regs;
295b54c4 3966 unsigned int b;
793b883e
SH		 3967
3968 regs->version = 1;
793b883e 3969
295b54c4 3970 for (b = 0; b < 128; b++) {
c32bbff8
MM		 3971 /* skip poisonous diagnostic ram region in block 3 */
3972 if (b == 3)
295b54c4 3973 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 3974 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 3975 memcpy_fromio(p, io, 128);
c32bbff8 3976 else
295b54c4 3977 memset(p, 0, 128);
3ead5db7 3978
295b54c4
SH		 3979 p += 128;
3980 io += 128;
3981 }
793b883e 3982}
cd28ab6a 3983
b628ed98
SH		 3984/* In order to do Jumbo packets on these chips, need to turn off the
3985 * transmit store/forward. Therefore checksum offload won't work.
3986 */
3987static int no_tx_offload(struct net_device *dev)
3988{
3989 const struct sky2_port *sky2 = netdev_priv(dev);
3990 const struct sky2_hw *hw = sky2->hw;
3991
69161611 3992 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3993}
3994
3995static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3996{
3997 if (data && no_tx_offload(dev))
3998 return -EINVAL;
3999
4000 return ethtool_op_set_tx_csum(dev, data);
4001}
4002
4003
4004static int sky2_set_tso(struct net_device *dev, u32 data)
4005{
4006 if (data && no_tx_offload(dev))
4007 return -EINVAL;
4008
4009 return ethtool_op_set_tso(dev, data);
4010}
4011
f4331a6d
SH		 4012static int sky2_get_eeprom_len(struct net_device *dev)
4013{
4014 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 4015 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 4016 u16 reg2;
4017
b32f40c4 4018 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 4019 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4020}
4021
1413235c 4022static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 4023{
1413235c 4024 unsigned long start = jiffies;
f4331a6d 4025
1413235c
SH		 4026 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4027 /* Can take up to 10.6 ms for write */
4028 if (time_after(jiffies, start + HZ/4)) {
ada1db5c 4029 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
1413235c
SH		 4030 return -ETIMEDOUT;
4031 }
4032 mdelay(1);
4033 }
167f53d0 4034
1413235c
SH		 4035 return 0;
4036}
167f53d0 4037
1413235c
SH		 4038static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4039 u16 offset, size_t length)
4040{
4041 int rc = 0;
4042
4043 while (length > 0) {
4044 u32 val;
4045
4046 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4047 rc = sky2_vpd_wait(hw, cap, 0);
4048 if (rc)
4049 break;
4050
4051 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4052
4053 memcpy(data, &val, min(sizeof(val), length));
4054 offset += sizeof(u32);
4055 data += sizeof(u32);
4056 length -= sizeof(u32);
4057 }
4058
4059 return rc;
f4331a6d
SH		 4060}
4061
1413235c
SH		 4062static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4063 u16 offset, unsigned int length)
f4331a6d 4064{
1413235c
SH		 4065 unsigned int i;
4066 int rc = 0;
4067
4068 for (i = 0; i < length; i += sizeof(u32)) {
4069 u32 val = *(u32 *)(data + i);
4070
4071 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4072 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4073
4074 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4075 if (rc)
4076 break;
4077 }
4078 return rc;
f4331a6d
SH		 4079}
4080
4081static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4082 u8 *data)
4083{
4084 struct sky2_port *sky2 = netdev_priv(dev);
4085 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4086
4087 if (!cap)
4088 return -EINVAL;
4089
4090 eeprom->magic = SKY2_EEPROM_MAGIC;
4091
1413235c 4092 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4093}
4094
4095static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4096 u8 *data)
4097{
4098 struct sky2_port *sky2 = netdev_priv(dev);
4099 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4100
4101 if (!cap)
4102 return -EINVAL;
4103
4104 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4105 return -EINVAL;
4106
1413235c
SH		 4107 /* Partial writes not supported */
4108 if ((eeprom->offset & 3) || (eeprom->len & 3))
4109 return -EINVAL;
f4331a6d 4110
1413235c 4111 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4112}
4113
4114
7282d491 4115static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4116 .get_settings = sky2_get_settings,
4117 .set_settings = sky2_set_settings,
4118 .get_drvinfo = sky2_get_drvinfo,
4119 .get_wol = sky2_get_wol,
4120 .set_wol = sky2_set_wol,
4121 .get_msglevel = sky2_get_msglevel,
4122 .set_msglevel = sky2_set_msglevel,
4123 .nway_reset = sky2_nway_reset,
4124 .get_regs_len = sky2_get_regs_len,
4125 .get_regs = sky2_get_regs,
4126 .get_link = ethtool_op_get_link,
4127 .get_eeprom_len = sky2_get_eeprom_len,
4128 .get_eeprom = sky2_get_eeprom,
4129 .set_eeprom = sky2_set_eeprom,
f4331a6d 4130 .set_sg = ethtool_op_set_sg,
f4331a6d 4131 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 4132 .set_tso = sky2_set_tso,
4133 .get_rx_csum = sky2_get_rx_csum,
4134 .set_rx_csum = sky2_set_rx_csum,
4135 .get_strings = sky2_get_strings,
4136 .get_coalesce = sky2_get_coalesce,
4137 .set_coalesce = sky2_set_coalesce,
4138 .get_ringparam = sky2_get_ringparam,
4139 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4140 .get_pauseparam = sky2_get_pauseparam,
4141 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 4142 .phys_id = sky2_phys_id,
b9f2c044 4143 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 4144 .get_ethtool_stats = sky2_get_ethtool_stats,
4145};
4146
3cf26753
SH		 4147#ifdef CONFIG_SKY2_DEBUG
4148
4149static struct dentry *sky2_debug;
4150
e4c2abe2
SH		 4151
4152/*
4153 * Read and parse the first part of Vital Product Data
4154 */
4155#define VPD_SIZE 128
4156#define VPD_MAGIC 0x82
4157
4158static const struct vpd_tag {
4159 char tag[2];
4160 char *label;
4161} vpd_tags[] = {
4162 { "PN", "Part Number" },
4163 { "EC", "Engineering Level" },
4164 { "MN", "Manufacturer" },
4165 { "SN", "Serial Number" },
4166 { "YA", "Asset Tag" },
4167 { "VL", "First Error Log Message" },
4168 { "VF", "Second Error Log Message" },
4169 { "VB", "Boot Agent ROM Configuration" },
4170 { "VE", "EFI UNDI Configuration" },
4171};
4172
4173static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4174{
4175 size_t vpd_size;
4176 loff_t offs;
4177 u8 len;
4178 unsigned char *buf;
4179 u16 reg2;
4180
4181 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4182 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4183
4184 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4185 buf = kmalloc(vpd_size, GFP_KERNEL);
4186 if (!buf) {
4187 seq_puts(seq, "no memory!\n");
4188 return;
4189 }
4190
4191 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4192 seq_puts(seq, "VPD read failed\n");
4193 goto out;
4194 }
4195
4196 if (buf[0] != VPD_MAGIC) {
4197 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4198 goto out;
4199 }
4200 len = buf[1];
4201 if (len == 0 || len > vpd_size - 4) {
4202 seq_printf(seq, "Invalid id length: %d\n", len);
4203 goto out;
4204 }
4205
4206 seq_printf(seq, "%.*s\n", len, buf + 3);
4207 offs = len + 3;
4208
4209 while (offs < vpd_size - 4) {
4210 int i;
4211
4212 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4213 break;
4214 len = buf[offs + 2];
4215 if (offs + len + 3 >= vpd_size)
4216 break;
4217
4218 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4219 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4220 seq_printf(seq, " %s: %.*s\n",
4221 vpd_tags[i].label, len, buf + offs + 3);
4222 break;
4223 }
4224 }
4225 offs += len + 3;
4226 }
4227out:
4228 kfree(buf);
4229}
4230
3cf26753
SH		 4231static int sky2_debug_show(struct seq_file *seq, void *v)
4232{
4233 struct net_device *dev = seq->private;
4234 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4235 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4236 unsigned port = sky2->port;
4237 unsigned idx, last;
4238 int sop;
4239
e4c2abe2 4240 sky2_show_vpd(seq, hw);
3cf26753 4241
e4c2abe2 4242 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4243 sky2_read32(hw, B0_ISRC),
4244 sky2_read32(hw, B0_IMSK),
4245 sky2_read32(hw, B0_Y2_SP_ICR));
4246
e4c2abe2
SH		 4247 if (!netif_running(dev)) {
4248 seq_printf(seq, "network not running\n");
4249 return 0;
4250 }
4251
bea3348e 4252 napi_disable(&hw->napi);
3cf26753
SH		 4253 last = sky2_read16(hw, STAT_PUT_IDX);
4254
4255 if (hw->st_idx == last)
4256 seq_puts(seq, "Status ring (empty)\n");
4257 else {
4258 seq_puts(seq, "Status ring\n");
4259 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4260 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4261 const struct sky2_status_le *le = hw->st_le + idx;
4262 seq_printf(seq, "[%d] %#x %d %#x\n",
4263 idx, le->opcode, le->length, le->status);
4264 }
4265 seq_puts(seq, "\n");
4266 }
4267
4268 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4269 sky2->tx_cons, sky2->tx_prod,
4270 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4271 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4272
4273 /* Dump contents of tx ring */
4274 sop = 1;
ee5f68fe
SH		 4275 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4276 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4277 const struct sky2_tx_le *le = sky2->tx_le + idx;
4278 u32 a = le32_to_cpu(le->addr);
4279
4280 if (sop)
4281 seq_printf(seq, "%u:", idx);
4282 sop = 0;
4283
4284 switch(le->opcode & ~HW_OWNER) {
4285 case OP_ADDR64:
4286 seq_printf(seq, " %#x:", a);
4287 break;
4288 case OP_LRGLEN:
4289 seq_printf(seq, " mtu=%d", a);
4290 break;
4291 case OP_VLAN:
4292 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4293 break;
4294 case OP_TCPLISW:
4295 seq_printf(seq, " csum=%#x", a);
4296 break;
4297 case OP_LARGESEND:
4298 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4299 break;
4300 case OP_PACKET:
4301 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4302 break;
4303 case OP_BUFFER:
4304 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4305 break;
4306 default:
4307 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4308 a, le16_to_cpu(le->length));
4309 }
4310
4311 if (le->ctrl & EOP) {
4312 seq_putc(seq, '\n');
4313 sop = 1;
4314 }
4315 }
4316
4317 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4318 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4319 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4320 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4321
d1d08d12 4322 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4323 napi_enable(&hw->napi);
3cf26753
SH		 4324 return 0;
4325}
4326
4327static int sky2_debug_open(struct inode *inode, struct file *file)
4328{
4329 return single_open(file, sky2_debug_show, inode->i_private);
4330}
4331
4332static const struct file_operations sky2_debug_fops = {
4333 .owner = THIS_MODULE,
4334 .open = sky2_debug_open,
4335 .read = seq_read,
4336 .llseek = seq_lseek,
4337 .release = single_release,
4338};
4339
4340/*
4341 * Use network device events to create/remove/rename
4342 * debugfs file entries
4343 */
4344static int sky2_device_event(struct notifier_block *unused,
4345 unsigned long event, void *ptr)
4346{
4347 struct net_device *dev = ptr;
5b296bc9 4348 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4349
1436b301 4350 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4351 return NOTIFY_DONE;
3cf26753 4352
5b296bc9
SH		 4353 switch(event) {
4354 case NETDEV_CHANGENAME:
4355 if (sky2->debugfs) {
4356 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4357 sky2_debug, dev->name);
4358 }
4359 break;
3cf26753 4360
5b296bc9
SH		 4361 case NETDEV_GOING_DOWN:
4362 if (sky2->debugfs) {
ada1db5c 4363 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
5b296bc9
SH		 4364 debugfs_remove(sky2->debugfs);
4365 sky2->debugfs = NULL;
3cf26753 4366 }
5b296bc9
SH		 4367 break;
4368
4369 case NETDEV_UP:
4370 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4371 sky2_debug, dev,
4372 &sky2_debug_fops);
4373 if (IS_ERR(sky2->debugfs))
4374 sky2->debugfs = NULL;
3cf26753
SH		 4375 }
4376
4377 return NOTIFY_DONE;
4378}
4379
4380static struct notifier_block sky2_notifier = {
4381 .notifier_call = sky2_device_event,
4382};
4383
4384
4385static __init void sky2_debug_init(void)
4386{
4387 struct dentry *ent;
4388
4389 ent = debugfs_create_dir("sky2", NULL);
4390 if (!ent || IS_ERR(ent))
4391 return;
4392
4393 sky2_debug = ent;
4394 register_netdevice_notifier(&sky2_notifier);
4395}
4396
4397static __exit void sky2_debug_cleanup(void)
4398{
4399 if (sky2_debug) {
4400 unregister_netdevice_notifier(&sky2_notifier);
4401 debugfs_remove(sky2_debug);
4402 sky2_debug = NULL;
4403 }
4404}
4405
4406#else
4407#define sky2_debug_init()
4408#define sky2_debug_cleanup()
4409#endif
4410
1436b301
SH		 4411/* Two copies of network device operations to handle special case of
4412 not allowing netpoll on second port */
4413static const struct net_device_ops sky2_netdev_ops[2] = {
4414 {
4415 .ndo_open = sky2_up,
4416 .ndo_stop = sky2_down,
00829823 4417 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4418 .ndo_do_ioctl = sky2_ioctl,
4419 .ndo_validate_addr = eth_validate_addr,
4420 .ndo_set_mac_address = sky2_set_mac_address,
4421 .ndo_set_multicast_list = sky2_set_multicast,
4422 .ndo_change_mtu = sky2_change_mtu,
4423 .ndo_tx_timeout = sky2_tx_timeout,
4424#ifdef SKY2_VLAN_TAG_USED
4425 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4426#endif
4427#ifdef CONFIG_NET_POLL_CONTROLLER
4428 .ndo_poll_controller = sky2_netpoll,
4429#endif
4430 },
4431 {
4432 .ndo_open = sky2_up,
4433 .ndo_stop = sky2_down,
00829823 4434 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4435 .ndo_do_ioctl = sky2_ioctl,
4436 .ndo_validate_addr = eth_validate_addr,
4437 .ndo_set_mac_address = sky2_set_mac_address,
4438 .ndo_set_multicast_list = sky2_set_multicast,
4439 .ndo_change_mtu = sky2_change_mtu,
4440 .ndo_tx_timeout = sky2_tx_timeout,
4441#ifdef SKY2_VLAN_TAG_USED
4442 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4443#endif
4444 },
4445};
3cf26753 4446
cd28ab6a
SH		 4447/* Initialize network device */
4448static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4449 unsigned port,
be63a21c 4450 int highmem, int wol)
cd28ab6a
SH		 4451{
4452 struct sky2_port *sky2;
4453 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4454
4455 if (!dev) {
898eb71c 4456 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4457 return NULL;
4458 }
4459
cd28ab6a 4460 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4461 dev->irq = hw->pdev->irq;
cd28ab6a 4462 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4463 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4464 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4465
4466 sky2 = netdev_priv(dev);
4467 sky2->netdev = dev;
4468 sky2->hw = hw;
4469 sky2->msg_enable = netif_msg_init(debug, default_msg);
4470
cd28ab6a 4471 /* Auto speed and flow control */
0ea065e5
SH		 4472 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4473 if (hw->chip_id != CHIP_ID_YUKON_XL)
4474 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4475
16ad91e1
SH		 4476 sky2->flow_mode = FC_BOTH;
4477
cd28ab6a
SH		 4478 sky2->duplex = -1;
4479 sky2->speed = -1;
4480 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4481 sky2->wol = wol;
75d070c5 4482
e07b1aa8 4483 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4484
793b883e 4485 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4486 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4487 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4488
4489 hw->dev[port] = dev;
4490
4491 sky2->port = port;
4492
4a50a876 4493 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4494 if (highmem)
4495 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4496
d1f13708 4497#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4498 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4499 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4500 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4501 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4502 }
d1f13708
SH		 4503#endif
4504
cd28ab6a 4505 /* read the mac address */
793b883e 4506 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4507 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4508
cd28ab6a
SH		 4509 return dev;
4510}
4511
28bd181a 4512static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4513{
4514 const struct sky2_port *sky2 = netdev_priv(dev);
4515
6c35abae 4516 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
cd28ab6a
SH		 4517}
4518
fb2690a9 4519/* Handle software interrupt used during MSI test */
7d12e780 4520static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4521{
4522 struct sky2_hw *hw = dev_id;
4523 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4524
4525 if (status == 0)
4526 return IRQ_NONE;
4527
4528 if (status & Y2_IS_IRQ_SW) {
ea76e635 4529 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4530 wake_up(&hw->msi_wait);
4531 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4532 }
4533 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4534
4535 return IRQ_HANDLED;
4536}
4537
4538/* Test interrupt path by forcing a a software IRQ */
4539static int __devinit sky2_test_msi(struct sky2_hw *hw)
4540{
4541 struct pci_dev *pdev = hw->pdev;
4542 int err;
4543
bb507fe1
SH		 4544 init_waitqueue_head (&hw->msi_wait);
4545
fb2690a9
SH		 4546 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4547
b0a20ded 4548 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4549 if (err) {
b02a9258 4550 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4551 return err;
4552 }
4553
fb2690a9 4554 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4555 sky2_read8(hw, B0_CTST);
fb2690a9 4556
ea76e635 4557 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4558
ea76e635 4559 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4560 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4561 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4562 "switching to INTx mode.\n");
fb2690a9
SH		 4563
4564 err = -EOPNOTSUPP;
4565 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4566 }
4567
4568 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4569 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4570
4571 free_irq(pdev->irq, hw);
4572
4573 return err;
4574}
4575
c7127a34
SH		 4576/* This driver supports yukon2 chipset only */
4577static const char *sky2_name(u8 chipid, char *buf, int sz)
4578{
4579 const char *name[] = {
4580 "XL", /* 0xb3 */
4581 "EC Ultra", /* 0xb4 */
4582 "Extreme", /* 0xb5 */
4583 "EC", /* 0xb6 */
4584 "FE", /* 0xb7 */
4585 "FE+", /* 0xb8 */
4586 "Supreme", /* 0xb9 */
0ce8b98d 4587 "UL 2", /* 0xba */
0f5aac70
SH		 4588 "Unknown", /* 0xbb */
4589 "Optima", /* 0xbc */
c7127a34
SH		 4590 };
4591
dae3a511 4592 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
c7127a34
SH		 4593 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4594 else
4595 snprintf(buf, sz, "(chip %#x)", chipid);
4596 return buf;
4597}
4598
cd28ab6a
SH		 4599static int __devinit sky2_probe(struct pci_dev *pdev,
4600 const struct pci_device_id *ent)
4601{
7f60c64b 4602 struct net_device *dev;
cd28ab6a 4603 struct sky2_hw *hw;
be63a21c 4604 int err, using_dac = 0, wol_default;
3834507d 4605 u32 reg;
c7127a34 4606 char buf1[16];
cd28ab6a 4607
793b883e
SH		 4608 err = pci_enable_device(pdev);
4609 if (err) {
b02a9258 4610 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4611 goto err_out;
4612 }
4613
6cc90a5a
SH		 4614 /* Get configuration information
4615 * Note: only regular PCI config access once to test for HW issues
4616 * other PCI access through shared memory for speed and to
4617 * avoid MMCONFIG problems.
4618 */
4619 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4620 if (err) {
4621 dev_err(&pdev->dev, "PCI read config failed\n");
4622 goto err_out;
4623 }
4624
4625 if (~reg == 0) {
4626 dev_err(&pdev->dev, "PCI configuration read error\n");
4627 goto err_out;
4628 }
4629
793b883e
SH		 4630 err = pci_request_regions(pdev, DRV_NAME);
4631 if (err) {
b02a9258 4632 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4633 goto err_out_disable;
cd28ab6a
SH		 4634 }
4635
4636 pci_set_master(pdev);
4637
d1f3d4dd 4638 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4639 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4640 using_dac = 1;
6a35528a 4641 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4642 if (err < 0) {
b02a9258
SH		 4643 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4644 "for consistent allocations\n");
d1f3d4dd
SH		 4645 goto err_out_free_regions;
4646 }
d1f3d4dd 4647 } else {
284901a9 4648 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4649 if (err) {
b02a9258 4650 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4651 goto err_out_free_regions;
4652 }
4653 }
d1f3d4dd 4654
3834507d
SH		 4655
4656#ifdef __BIG_ENDIAN
4657 /* The sk98lin vendor driver uses hardware byte swapping but
4658 * this driver uses software swapping.
4659 */
4660 reg &= ~PCI_REV_DESC;
4661 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4662 if (err) {
4663 dev_err(&pdev->dev, "PCI write config failed\n");
4664 goto err_out_free_regions;
4665 }
4666#endif
4667
9d731d77 4668 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4669
cd28ab6a 4670 err = -ENOMEM;
66466797
SH		 4671
4672 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4673 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4674 if (!hw) {
b02a9258 4675 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4676 goto err_out_free_regions;
4677 }
4678
cd28ab6a 4679 hw->pdev = pdev;
66466797 4680 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4681
4682 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4683 if (!hw->regs) {
b02a9258 4684 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4685 goto err_out_free_hw;
4686 }
4687
08c06d8a 4688 /* ring for status responses */
167f53d0 4689 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4690 if (!hw->st_le)
4691 goto err_out_iounmap;
4692
e3173832 4693 err = sky2_init(hw);
cd28ab6a 4694 if (err)
793b883e 4695 goto err_out_iounmap;
cd28ab6a 4696
c844d483
SH		 4697 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4698 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4699
e3173832
SH		 4700 sky2_reset(hw);
4701
be63a21c 4702 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4703 if (!dev) {
4704 err = -ENOMEM;
cd28ab6a 4705 goto err_out_free_pci;
7f60c64b 4706 }
cd28ab6a 4707
9fa1b1f3
SH		 4708 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4709 err = sky2_test_msi(hw);
4710 if (err == -EOPNOTSUPP)
4711 pci_disable_msi(pdev);
4712 else if (err)
4713 goto err_out_free_netdev;
4714 }
4715
793b883e
SH		 4716 err = register_netdev(dev);
4717 if (err) {
b02a9258 4718 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4719 goto err_out_free_netdev;
4720 }
4721
33cb7d33
BP		 4722 netif_carrier_off(dev);
4723
6de16237
SH		 4724 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4725
ea76e635
SH		 4726 err = request_irq(pdev->irq, sky2_intr,
4727 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4728 hw->irq_name, hw);
9fa1b1f3 4729 if (err) {
b02a9258 4730 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4731 goto err_out_unregister;
4732 }
4733 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4734 napi_enable(&hw->napi);
9fa1b1f3 4735
cd28ab6a
SH		 4736 sky2_show_addr(dev);
4737
7f60c64b 4738 if (hw->ports > 1) {
4739 struct net_device *dev1;
4740
ca519274 4741 err = -ENOMEM;
be63a21c 4742 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4743 if (dev1 && (err = register_netdev(dev1)) == 0)
4744 sky2_show_addr(dev1);
4745 else {
b02a9258
SH		 4746 dev_warn(&pdev->dev,
4747 "register of second port failed (%d)\n", err);
cd28ab6a 4748 hw->dev[1] = NULL;
ca519274
SH		 4749 hw->ports = 1;
4750 if (dev1)
4751 free_netdev(dev1);
4752 }
cd28ab6a
SH		 4753 }
4754
32c2c300 4755 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4756 INIT_WORK(&hw->restart_work, sky2_restart);
4757
793b883e 4758 pci_set_drvdata(pdev, hw);
1ae861e6 4759 pdev->d3_delay = 150;
793b883e 4760
cd28ab6a
SH		 4761 return 0;
4762
793b883e 4763err_out_unregister:
ea76e635 4764 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4765 pci_disable_msi(pdev);
793b883e 4766 unregister_netdev(dev);
cd28ab6a
SH		 4767err_out_free_netdev:
4768 free_netdev(dev);
cd28ab6a 4769err_out_free_pci:
793b883e 4770 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4771 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4772err_out_iounmap:
4773 iounmap(hw->regs);
4774err_out_free_hw:
4775 kfree(hw);
4776err_out_free_regions:
4777 pci_release_regions(pdev);
44a1d2e5 4778err_out_disable:
cd28ab6a 4779 pci_disable_device(pdev);
cd28ab6a 4780err_out:
549a68c3 4781 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4782 return err;
4783}
4784
4785static void __devexit sky2_remove(struct pci_dev *pdev)
4786{
793b883e 4787 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4788 int i;
cd28ab6a 4789
793b883e 4790 if (!hw)
cd28ab6a
SH		 4791 return;
4792
32c2c300 4793 del_timer_sync(&hw->watchdog_timer);
6de16237 4794 cancel_work_sync(&hw->restart_work);
d27ed387 4795
b877fe28 4796 for (i = hw->ports-1; i >= 0; --i)
6de16237 4797 unregister_netdev(hw->dev[i]);
81906791 4798
d27ed387 4799 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4800
ae306cca
SH		 4801 sky2_power_aux(hw);
4802
793b883e 4803 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4804 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4805
4806 free_irq(pdev->irq, hw);
ea76e635 4807 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4808 pci_disable_msi(pdev);
793b883e 4809 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4810 pci_release_regions(pdev);
4811 pci_disable_device(pdev);
793b883e 4812
b877fe28 4813 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4814 free_netdev(hw->dev[i]);
4815
cd28ab6a
SH		 4816 iounmap(hw->regs);
4817 kfree(hw);
5afa0a9c 4818
cd28ab6a
SH		 4819 pci_set_drvdata(pdev, NULL);
4820}
4821
cd28ab6a
SH		 4822static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4823{
793b883e 4824 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4825 int i, wol = 0;
cd28ab6a 4826
549a68c3
SH		 4827 if (!hw)
4828 return 0;
4829
063a0b38
SH		 4830 del_timer_sync(&hw->watchdog_timer);
4831 cancel_work_sync(&hw->restart_work);
4832
19720737 4833 rtnl_lock();
f05267e7 4834 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4835 struct net_device *dev = hw->dev[i];
e3173832 4836 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4837
af18d8b8 4838 sky2_detach(dev);
e3173832
SH		 4839
4840 if (sky2->wol)
4841 sky2_wol_init(sky2);
4842
4843 wol |= sky2->wol;
cd28ab6a
SH		 4844 }
4845
5f8ae5c5 4846 device_set_wakeup_enable(&pdev->dev, wol != 0);
4847
8ab8fca2 4848 sky2_write32(hw, B0_IMSK, 0);
6de16237 4849 napi_disable(&hw->napi);
ae306cca 4850 sky2_power_aux(hw);
19720737 4851 rtnl_unlock();
e3173832 4852
d374c1c1 4853 pci_save_state(pdev);
e3173832 4854 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4855 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4856
2ccc99b7 4857 return 0;
cd28ab6a
SH		 4858}
4859
5f8ae5c5 4860#ifdef CONFIG_PM
cd28ab6a
SH		 4861static int sky2_resume(struct pci_dev *pdev)
4862{
793b883e 4863 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4864 int i, err;
cd28ab6a 4865
549a68c3
SH		 4866 if (!hw)
4867 return 0;
4868
2a400189 4869 rtnl_lock();
f71eb1a2
SH		 4870 err = pci_set_power_state(pdev, PCI_D0);
4871 if (err)
4872 goto out;
ae306cca
SH		 4873
4874 err = pci_restore_state(pdev);
4875 if (err)
4876 goto out;
4877
cd28ab6a 4878 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4879
4880 /* Re-enable all clocks */
a0db28b8 4881 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4882 if (err) {
4883 dev_err(&pdev->dev, "PCI write config failed\n");
4884 goto out;
4885 }
1ad5b4a5 4886
e3173832 4887 sky2_reset(hw);
8ab8fca2 4888 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4889 napi_enable(&hw->napi);
8ab8fca2 4890
f05267e7 4891 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4892 err = sky2_reattach(hw->dev[i]);
4893 if (err)
4894 goto out;
cd28ab6a 4895 }
af18d8b8 4896 rtnl_unlock();
eb35cf60 4897
ae306cca 4898 return 0;
08c06d8a 4899out:
af18d8b8
SH		 4900 rtnl_unlock();
4901
b02a9258 4902 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4903 pci_disable_device(pdev);
08c06d8a 4904 return err;
cd28ab6a
SH		 4905}
4906#endif
4907
e3173832
SH		 4908static void sky2_shutdown(struct pci_dev *pdev)
4909{
5f8ae5c5 4910 sky2_suspend(pdev, PMSG_SUSPEND);
e3173832
SH		 4911}
4912
cd28ab6a 4913static struct pci_driver sky2_driver = {
793b883e
SH		 4914 .name = DRV_NAME,
4915 .id_table = sky2_id_table,
4916 .probe = sky2_probe,
4917 .remove = __devexit_p(sky2_remove),
cd28ab6a 4918#ifdef CONFIG_PM
793b883e
SH		 4919 .suspend = sky2_suspend,
4920 .resume = sky2_resume,
cd28ab6a 4921#endif
e3173832 4922 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4923};
4924
4925static int __init sky2_init_module(void)
4926{
ada1db5c 4927 pr_info("driver version " DRV_VERSION "\n");
c844d483 4928
3cf26753 4929 sky2_debug_init();
50241c4c 4930 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4931}
4932
4933static void __exit sky2_cleanup_module(void)
4934{
4935 pci_unregister_driver(&sky2_driver);
3cf26753 4936 sky2_debug_cleanup();
cd28ab6a
SH		 4937}
4938
4939module_init(sky2_init_module);
4940module_exit(sky2_cleanup_module);
4941
4942MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4943MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4944MODULE_LICENSE("GPL");
5f4f9dc1 4945MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree