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cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
743d32ad 53#define DRV_VERSION "1.22"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 66
67#define TX_RING_SIZE 512
e9c1be80 68#define TX_DEF_PENDING 128
b19666d9 69#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
cd28ab6a 71
793b883e 72#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 73#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 74#define TX_WATCHDOG (5 * HZ)
75#define NAPI_WEIGHT 64
76#define PHY_RETRIES 1000
77
f4331a6d
SH		 78#define SKY2_EEPROM_MAGIC 0x9955aabb
79
80
cb5d9547
SH		 81#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
cd28ab6a 83static const u32 default_msg =
793b883e
SH		 84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 87
793b883e 88static int debug = -1; /* defaults above */
cd28ab6a
SH		 89module_param(debug, int, 0);
90MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
14d0263f 92static int copybreak __read_mostly = 128;
bdb5c58e
SH		 93module_param(copybreak, int, 0);
94MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
fb2690a9
SH		 96static int disable_msi = 0;
97module_param(disable_msi, int, 0);
98MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
e6cac9ba 100static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
SH		 140 { 0 }
141};
793b883e 142
cd28ab6a
SH		 143MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145/* Avoid conditionals by using array */
146static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 148static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 149
d1b139c0
SH		 150static void sky2_set_multicast(struct net_device *dev);
151
af043aa5 152/* Access to PHY via serial interconnect */
ef743d33 153static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 154{
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
af043aa5
SH		 168
169 udelay(10);
cd28ab6a 170 }
ef743d33 171
af043aa5 172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 173 return -ETIMEDOUT;
af043aa5
SH		 174
175io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
cd28ab6a
SH		 178}
179
ef743d33 180static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 181{
182 int i;
183
793b883e 184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
af043aa5 197 udelay(10);
cd28ab6a
SH		 198 }
199
af043aa5 200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 201 return -ETIMEDOUT;
af043aa5
SH		 202io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
ef743d33
SH		 205}
206
af043aa5 207static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 208{
209 u16 v;
af043aa5 210 __gm_phy_read(hw, port, reg, &v);
ef743d33 211 return v;
cd28ab6a
SH		 212}
213
5afa0a9c 214
ae306cca
SH		 215static void sky2_power_on(struct sky2_hw *hw)
216{
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 220
ae306cca
SH		 221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 223
ae306cca
SH		 224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 232
ea76e635 233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 234 u32 reg;
5afa0a9c 235
b32f40c4 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 237
b32f40c4 238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 242
b32f40c4 243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 247
b32f40c4 248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 254
255 sky2_read32(hw, B2_GP_IO);
5afa0a9c 256 }
ae306cca 257}
5afa0a9c 258
ae306cca
SH		 259static void sky2_power_aux(struct sky2_hw *hw)
260{
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 275}
276
d3bcfbeb 277static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 278{
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 283
cd28ab6a
SH		 284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292}
293
16ad91e1
SH		 294/* flow control to advertise bits */
295static const u16 copper_fc_adv[] = {
296 [FC_NONE] = 0,
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
300};
301
302/* flow control to advertise bits when using 1000BaseX */
303static const u16 fiber_fc_adv[] = {
df3fe1f3 304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 308};
309
310/* flow control to GMA disable bits */
311static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
315 [FC_BOTH] = 0,
316};
317
318
cd28ab6a
SH		 319static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
320{
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 323
ea76e635
SH		 324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
327
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 329 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
331
53419c68 332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 333 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 334 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
336 else
53419c68
SH		 337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 339
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
341 }
342
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 344 if (sky2_is_copper(hw)) {
05745c4a 345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 348
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
351 u16 spec;
352
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
357 }
cd28ab6a
SH		 358 } else {
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
361
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
364
53419c68 365 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 366 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 368 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
371 }
372 }
cd28ab6a
SH		 373 } else {
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
376
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 378 }
cd28ab6a 379
b89165f2
SH		 380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
381
382 /* special setup for PHY 88E1112 Fiber */
ea76e635 383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 385
b89165f2
SH		 386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 396
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 401 }
b89165f2
SH		 402
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 404 }
405
7800fddc 406 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 407 ct1000 = 0;
408 adv = PHY_AN_CSMA;
2eaba1a2 409 reg = 0;
cd28ab6a
SH		 410
411 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 412 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
709c6e7b 425
16ad91e1 426 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 432
16ad91e1 433 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 434 }
cd28ab6a
SH		 435
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
438 } else {
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
441
2eaba1a2
SH		 442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 444
445 switch (sky2->speed) {
446 case SPEED_1000:
447 ctrl |= PHY_CT_SP1000;
2eaba1a2 448 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 449 break;
450 case SPEED_100:
451 ctrl |= PHY_CT_SP100;
2eaba1a2 452 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 453 break;
454 }
455
2eaba1a2
SH		 456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
2eaba1a2 461
2eaba1a2 462
16ad91e1 463 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 464
465 /* Forward pause packets to GMAC? */
16ad91e1 466 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
468 else
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 470 }
471
2eaba1a2
SH		 472 gma_write16(hw, port, GM_GP_CTRL, reg);
473
05745c4a 474 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
476
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
479
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
482 ledover = 0;
483
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
488
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
490
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
496 break;
497
05745c4a
SH		 498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
502
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
506
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
511
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
cd28ab6a 515 case CHIP_ID_YUKON_XL:
793b883e 516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 517
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
520
521 /* set LED Function Control register */
ed6d32c7
SH		 522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 527
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 536
537 /* restore page register */
793b883e 538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 539 break;
93745494 540
ed6d32c7 541 case CHIP_ID_YUKON_EC_U:
93745494 542 case CHIP_ID_YUKON_EX:
ed4d4161 543 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
545
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
548
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
555
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
561 break;
cd28ab6a
SH		 562
563 default:
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 566
cd28ab6a 567 /* turn off the Rx LED (LED_RX) */
a84d0a3d 568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 569 }
570
0ce8b98d 571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 572 /* apply fixes in PHY AFE */
ed6d32c7
SH		 573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
574
977bdf06 575 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 578
0ce8b98d
SH		 579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
583 }
977bdf06
SH		 584
585 /* set page register to 0 */
9467a8fc 586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 594 /* no effect on Yukon-XL */
977bdf06 595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 596
977bdf06
SH		 597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 600 }
cd28ab6a 601
977bdf06
SH		 602 if (ledover)
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
604
605 }
2eaba1a2 606
d571b694 607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
610 else
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
612}
613
b96936da
SH		 614static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
616
617static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 618{
619 u32 reg1;
d3bcfbeb 620
82637e80 621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 623 reg1 &= ~phy_power[port];
d3bcfbeb 624
b96936da 625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 626 reg1 |= coma_mode[port];
627
b32f40c4 628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 631
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 636}
167f53d0 637
b96936da
SH		 638static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
639{
640 u32 reg1;
db99b988
SH		 641 u16 ctrl;
642
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
645
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
648
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
652
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
657
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
660 }
661
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
665
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 668 /* select page 2 to access MAC control register */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 670
e484d5f5 671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 672 /* enable Power Down */
673 ctrl |= PHY_M_PC_POW_D_ENA;
674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 675
676 /* set page register back to 0 */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 678 }
679
680 /* set IEEE compatible Power Down Mode (dev. #4.99) */
681 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
682 }
b96936da
SH		 683
684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
685 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 686 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 687 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 689}
690
1b537565
SH		 691/* Force a renegotiation */
692static void sky2_phy_reinit(struct sky2_port *sky2)
693{
e07b1aa8 694 spin_lock_bh(&sky2->phy_lock);
1b537565 695 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 696 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 697}
698
e3173832
SH		 699/* Put device in state to listen for Wake On Lan */
700static void sky2_wol_init(struct sky2_port *sky2)
701{
702 struct sky2_hw *hw = sky2->hw;
703 unsigned port = sky2->port;
704 enum flow_control save_mode;
705 u16 ctrl;
706 u32 reg1;
707
708 /* Bring hardware out of reset */
709 sky2_write16(hw, B0_CTST, CS_RST_CLR);
710 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
711
712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
713 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
714
715 /* Force to 10/100
716 * sky2_reset will re-enable on resume
717 */
718 save_mode = sky2->flow_mode;
719 ctrl = sky2->advertising;
720
721 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
722 sky2->flow_mode = FC_NONE;
b96936da
SH		 723
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_power_up(hw, port);
726 sky2_phy_init(hw, port);
727 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 728
729 sky2->flow_mode = save_mode;
730 sky2->advertising = ctrl;
731
732 /* Set GMAC to no flow control and auto update for speed/duplex */
733 gma_write16(hw, port, GM_GP_CTRL,
734 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
735 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
736
737 /* Set WOL address */
738 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
739 sky2->netdev->dev_addr, ETH_ALEN);
740
741 /* Turn on appropriate WOL control bits */
742 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
743 ctrl = 0;
744 if (sky2->wol & WAKE_PHY)
745 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
746 else
747 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
748
749 if (sky2->wol & WAKE_MAGIC)
750 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
751 else
752 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
753
754 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
755 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
756
757 /* Turn on legacy PCI-Express PME mode */
b32f40c4 758 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 759 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 760 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 761
762 /* block receiver */
763 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
764
765}
766
69161611
SH		 767static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
768{
05745c4a
SH		 769 struct net_device *dev = hw->dev[port];
770
ed4d4161
SH		 771 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
772 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
773 hw->chip_id == CHIP_ID_YUKON_FE_P ||
774 hw->chip_id == CHIP_ID_YUKON_SUPR) {
775 /* Yukon-Extreme B0 and further Extreme devices */
776 /* enable Store & Forward mode for TX */
05745c4a 777
ed4d4161
SH		 778 if (dev->mtu <= ETH_DATA_LEN)
779 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
780 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 781
ed4d4161
SH		 782 else
783 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
784 TX_JUMBO_ENA| TX_STFW_ENA);
785 } else {
786 if (dev->mtu <= ETH_DATA_LEN)
787 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
788 else {
789 /* set Tx GMAC FIFO Almost Empty Threshold */
790 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
791 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 792
ed4d4161
SH		 793 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
794
795 /* Can't do offload because of lack of store/forward */
796 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
797 }
69161611
SH		 798 }
799}
800
cd28ab6a
SH		 801static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
802{
803 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
804 u16 reg;
25cccecc 805 u32 rx_reg;
cd28ab6a
SH		 806 int i;
807 const u8 *addr = hw->dev[port]->dev_addr;
808
f350339c
SH		 809 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
810 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 811
812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
813
793b883e 814 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 815 /* WA DEV_472 -- looks like crossed wires on port 2 */
816 /* clear GMAC 1 Control reset */
817 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
818 do {
819 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
820 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
821 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
822 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
823 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
824 }
825
793b883e 826 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 827
2eaba1a2
SH		 828 /* Enable Transmit FIFO Underrun */
829 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
830
e07b1aa8 831 spin_lock_bh(&sky2->phy_lock);
b96936da 832 sky2_phy_power_up(hw, port);
cd28ab6a 833 sky2_phy_init(hw, port);
e07b1aa8 834 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 835
836 /* MIB clear */
837 reg = gma_read16(hw, port, GM_PHY_ADDR);
838 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
839
43f2f104
SH		 840 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
841 gma_read16(hw, port, i);
cd28ab6a
SH		 842 gma_write16(hw, port, GM_PHY_ADDR, reg);
843
844 /* transmit control */
845 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
846
847 /* receive control reg: unicast + multicast + no FCS */
848 gma_write16(hw, port, GM_RX_CTRL,
793b883e 849 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 850
851 /* transmit flow control */
852 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
853
854 /* transmit parameter */
855 gma_write16(hw, port, GM_TX_PARAM,
856 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
857 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
858 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
859 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
860
861 /* serial mode register */
862 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 863 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 864
6b1a3aef 865 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 866 reg |= GM_SMOD_JUMBO_ENA;
867
868 gma_write16(hw, port, GM_SERIAL_MODE, reg);
869
cd28ab6a
SH		 870 /* virtual address for data */
871 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
872
793b883e
SH		 873 /* physical address: used for pause frames */
874 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
875
876 /* ignore counter overflows */
cd28ab6a
SH		 877 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
878 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
879 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
880
881 /* Configure Rx MAC FIFO */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 883 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 884 if (hw->chip_id == CHIP_ID_YUKON_EX ||
885 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 886 rx_reg |= GMF_RX_OVER_ON;
69161611 887
25cccecc 888 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 889
798fdd07
SH		 890 if (hw->chip_id == CHIP_ID_YUKON_XL) {
891 /* Hardware errata - clear flush mask */
892 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
893 } else {
894 /* Flush Rx MAC FIFO on any flow control or error */
895 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
896 }
cd28ab6a 897
8df9a876 898 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 899 reg = RX_GMF_FL_THR_DEF + 1;
900 /* Another magic mystery workaround from sk98lin */
901 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
902 hw->chip_rev == CHIP_REV_YU_FE2_A0)
903 reg = 0x178;
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 905
906 /* Configure Tx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
908 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 909
e0c28116 910 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 911 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 912 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 913 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 914
69161611 915 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 916 }
917
e970d1f8
SH		 918 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
919 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
920 /* disable dynamic watermark */
921 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
922 reg &= ~TX_DYN_WM_ENA;
923 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
924 }
cd28ab6a
SH		 925}
926
67712901
SH		 927/* Assign Ram Buffer allocation to queue */
928static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 929{
67712901
SH		 930 u32 end;
931
932 /* convert from K bytes to qwords used for hw register */
933 start *= 1024/8;
934 space *= 1024/8;
935 end = start + space - 1;
793b883e 936
cd28ab6a
SH		 937 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
938 sky2_write32(hw, RB_ADDR(q, RB_START), start);
939 sky2_write32(hw, RB_ADDR(q, RB_END), end);
940 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
941 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
942
943 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 944 u32 tp = space - space/4;
793b883e 945
1c28f6ba
SH		 946 /* On receive queue's set the thresholds
947 * give receiver priority when > 3/4 full
948 * send pause when down to 2K
949 */
950 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
951 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 952
1c28f6ba
SH		 953 tp = space - 2048/8;
954 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
955 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 956 } else {
957 /* Enable store & forward on Tx queue's because
958 * Tx FIFO is only 1K on Yukon
959 */
960 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
961 }
962
963 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 964 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 965}
966
cd28ab6a 967/* Setup Bus Memory Interface */
af4ed7e6 968static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 969{
970 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
971 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
972 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 973 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 974}
975
cd28ab6a
SH		 976/* Setup prefetch unit registers. This is the interface between
977 * hardware and driver list elements
978 */
8cc048e3 979static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 980 u64 addr, u32 last)
981{
cd28ab6a
SH		 982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
984 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
985 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
986 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
987 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 988
989 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 990}
991
793b883e
SH		 992static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
993{
994 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
995
cb5d9547 996 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 997 le->ctrl = 0;
793b883e
SH		 998 return le;
999}
cd28ab6a 1000
88f5f0ca
SH		 1001static void tx_init(struct sky2_port *sky2)
1002{
1003 struct sky2_tx_le *le;
1004
1005 sky2->tx_prod = sky2->tx_cons = 0;
1006 sky2->tx_tcpsum = 0;
1007 sky2->tx_last_mss = 0;
1008
1009 le = get_tx_le(sky2);
1010 le->addr = 0;
1011 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 1012}
1013
291ea614
SH		 1014static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1015 struct sky2_tx_le *le)
1016{
1017 return sky2->tx_ring + (le - sky2->tx_le);
1018}
1019
290d4de5
SH		 1020/* Update chip's next pointer */
1021static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1022{
50432cb5 1023 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1024 wmb();
50432cb5
SH		 1025 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1026
1027 /* Synchronize I/O on since next processor may write to tail */
1028 mmiowb();
cd28ab6a
SH		 1029}
1030
793b883e 1031
cd28ab6a
SH		 1032static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1033{
1034 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1035 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1036 le->ctrl = 0;
cd28ab6a
SH		 1037 return le;
1038}
1039
14d0263f
SH		 1040/* Build description to hardware for one receive segment */
1041static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1042 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1043{
1044 struct sky2_rx_le *le;
1045
86c6887e 1046 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1047 le = sky2_next_rx(sky2);
86c6887e 1048 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1049 le->opcode = OP_ADDR64 | HW_OWNER;
1050 }
793b883e 1051
cd28ab6a 1052 le = sky2_next_rx(sky2);
734d1868
SH		 1053 le->addr = cpu_to_le32((u32) map);
1054 le->length = cpu_to_le16(len);
14d0263f 1055 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1056}
1057
14d0263f
SH		 1058/* Build description to hardware for one possibly fragmented skb */
1059static void sky2_rx_submit(struct sky2_port *sky2,
1060 const struct rx_ring_info *re)
1061{
1062 int i;
1063
1064 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1065
1066 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1067 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1068}
1069
1070
454e6cb6 1071static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1072 unsigned size)
1073{
1074 struct sk_buff *skb = re->skb;
1075 int i;
1076
1077 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
454e6cb6
SH		 1078 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1079 return -EIO;
1080
14d0263f
SH		 1081 pci_unmap_len_set(re, data_size, size);
1082
1083 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1084 re->frag_addr[i] = pci_map_page(pdev,
1085 skb_shinfo(skb)->frags[i].page,
1086 skb_shinfo(skb)->frags[i].page_offset,
1087 skb_shinfo(skb)->frags[i].size,
1088 PCI_DMA_FROMDEVICE);
454e6cb6 1089 return 0;
14d0263f
SH		 1090}
1091
1092static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1093{
1094 struct sk_buff *skb = re->skb;
1095 int i;
1096
1097 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1098 PCI_DMA_FROMDEVICE);
1099
1100 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1101 pci_unmap_page(pdev, re->frag_addr[i],
1102 skb_shinfo(skb)->frags[i].size,
1103 PCI_DMA_FROMDEVICE);
1104}
793b883e 1105
cd28ab6a
SH		 1106/* Tell chip where to start receive checksum.
1107 * Actually has two checksums, but set both same to avoid possible byte
1108 * order problems.
1109 */
793b883e 1110static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1111{
ea76e635 1112 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1113
ea76e635
SH		 1114 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1115 le->ctrl = 0;
1116 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1117
ea76e635
SH		 1118 sky2_write32(sky2->hw,
1119 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1120 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1121}
1122
6b1a3aef
SH		 1123/*
1124 * The RX Stop command will not work for Yukon-2 if the BMU does not
1125 * reach the end of packet and since we can't make sure that we have
1126 * incoming data, we must reset the BMU while it is not doing a DMA
1127 * transfer. Since it is possible that the RX path is still active,
1128 * the RX RAM buffer will be stopped first, so any possible incoming
1129 * data will not trigger a DMA. After the RAM buffer is stopped, the
1130 * BMU is polled until any DMA in progress is ended and only then it
1131 * will be reset.
1132 */
1133static void sky2_rx_stop(struct sky2_port *sky2)
1134{
1135 struct sky2_hw *hw = sky2->hw;
1136 unsigned rxq = rxqaddr[sky2->port];
1137 int i;
1138
1139 /* disable the RAM Buffer receive queue */
1140 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1141
1142 for (i = 0; i < 0xffff; i++)
1143 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1144 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1145 goto stopped;
1146
1147 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1148 sky2->netdev->name);
1149stopped:
1150 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1151
1152 /* reset the Rx prefetch unit */
1153 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
c0bad0f2
SH		 1154
1155 /* Reset the RAM Buffer receive queue */
1156 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_RST_SET);
1157
1158 /* Reset Rx MAC FIFO */
1159 sky2_write8(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), GMF_RST_SET);
1160
1161 sky2_read8(hw, B0_CTST);
6b1a3aef 1162}
793b883e 1163
d571b694 1164/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1165static void sky2_rx_clean(struct sky2_port *sky2)
1166{
1167 unsigned i;
1168
1169 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1170 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1171 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1172
1173 if (re->skb) {
14d0263f 1174 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1175 kfree_skb(re->skb);
1176 re->skb = NULL;
1177 }
1178 }
bd1c6869 1179 skb_queue_purge(&sky2->rx_recycle);
cd28ab6a
SH		 1180}
1181
ef743d33
SH		 1182/* Basic MII support */
1183static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1184{
1185 struct mii_ioctl_data *data = if_mii(ifr);
1186 struct sky2_port *sky2 = netdev_priv(dev);
1187 struct sky2_hw *hw = sky2->hw;
1188 int err = -EOPNOTSUPP;
1189
1190 if (!netif_running(dev))
1191 return -ENODEV; /* Phy still in reset */
1192
d89e1343 1193 switch (cmd) {
ef743d33
SH		 1194 case SIOCGMIIPHY:
1195 data->phy_id = PHY_ADDR_MARV;
1196
1197 /* fallthru */
1198 case SIOCGMIIREG: {
1199 u16 val = 0;
91c86df5 1200
e07b1aa8 1201 spin_lock_bh(&sky2->phy_lock);
ef743d33 1202 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1203 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1204
ef743d33
SH		 1205 data->val_out = val;
1206 break;
1207 }
1208
1209 case SIOCSMIIREG:
1210 if (!capable(CAP_NET_ADMIN))
1211 return -EPERM;
1212
e07b1aa8 1213 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1214 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1215 data->val_in);
e07b1aa8 1216 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1217 break;
1218 }
1219 return err;
1220}
1221
d1f13708 1222#ifdef SKY2_VLAN_TAG_USED
d494eacd 1223static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1224{
d494eacd 1225 if (onoff) {
3d4e66f5
SH		 1226 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1227 RX_VLAN_STRIP_ON);
1228 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1229 TX_VLAN_TAG_ON);
1230 } else {
1231 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1232 RX_VLAN_STRIP_OFF);
1233 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1234 TX_VLAN_TAG_OFF);
1235 }
d494eacd
SH		 1236}
1237
1238static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1239{
1240 struct sky2_port *sky2 = netdev_priv(dev);
1241 struct sky2_hw *hw = sky2->hw;
1242 u16 port = sky2->port;
1243
1244 netif_tx_lock_bh(dev);
1245 napi_disable(&hw->napi);
1246
1247 sky2->vlgrp = grp;
1248 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1249
d1d08d12 1250 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1251 napi_enable(&hw->napi);
2bb8c262 1252 netif_tx_unlock_bh(dev);
d1f13708
SH		 1253}
1254#endif
1255
bd1c6869
SH		 1256/* Amount of required worst case padding in rx buffer */
1257static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1258{
1259 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1260}
1261
82788c7a 1262/*
14d0263f
SH		 1263 * Allocate an skb for receiving. If the MTU is large enough
1264 * make the skb non-linear with a fragment list of pages.
82788c7a 1265 */
14d0263f 1266static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1267{
1268 struct sk_buff *skb;
14d0263f 1269 int i;
82788c7a 1270
bd1c6869
SH		 1271 skb = __skb_dequeue(&sky2->rx_recycle);
1272 if (!skb)
1273 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size
1274 + sky2_rx_pad(sky2->hw));
1275 if (!skb)
1276 goto nomem;
1277
39dbd958 1278 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1279 unsigned char *start;
1280 /*
1281 * Workaround for a bug in FIFO that cause hang
1282 * if the FIFO if the receive buffer is not 64 byte aligned.
1283 * The buffer returned from netdev_alloc_skb is
1284 * aligned except if slab debugging is enabled.
1285 */
f03b8654
SH		 1286 start = PTR_ALIGN(skb->data, 8);
1287 skb_reserve(skb, start - skb->data);
bd1c6869 1288 } else
f03b8654 1289 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1290
1291 for (i = 0; i < sky2->rx_nfrags; i++) {
1292 struct page *page = alloc_page(GFP_ATOMIC);
1293
1294 if (!page)
1295 goto free_partial;
1296 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1297 }
1298
1299 return skb;
14d0263f
SH		 1300free_partial:
1301 kfree_skb(skb);
1302nomem:
1303 return NULL;
82788c7a
SH		 1304}
1305
55c9dd35
SH		 1306static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1307{
1308 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1309}
1310
cd28ab6a
SH		 1311/*
1312 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1313 * Normal case this ends up creating one list element for skb
1314 * in the receive ring. Worst case if using large MTU and each
1315 * allocation falls on a different 64 bit region, that results
1316 * in 6 list elements per ring entry.
1317 * One element is used for checksum enable/disable, and one
1318 * extra to avoid wrap.
cd28ab6a 1319 */
6b1a3aef 1320static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1321{
6b1a3aef 1322 struct sky2_hw *hw = sky2->hw;
14d0263f 1323 struct rx_ring_info *re;
6b1a3aef 1324 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1325 unsigned i, size, thresh;
cd28ab6a 1326
6b1a3aef 1327 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1328 sky2_qset(hw, rxq);
977bdf06 1329
c3905bc4
SH		 1330 /* On PCI express lowering the watermark gives better performance */
1331 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1332 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1333
1334 /* These chips have no ram buffer?
1335 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1336 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1337 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1338 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1339 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1340
6b1a3aef
SH		 1341 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1342
ea76e635
SH		 1343 if (!(hw->flags & SKY2_HW_NEW_LE))
1344 rx_set_checksum(sky2);
14d0263f
SH		 1345
1346 /* Space needed for frame data + headers rounded up */
f957da2a 1347 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1348
1349 /* Stopping point for hardware truncation */
1350 thresh = (size - 8) / sizeof(u32);
1351
5f06eba4 1352 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1353 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1354
5f06eba4
SH		 1355 /* Compute residue after pages */
1356 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1357
5f06eba4
SH		 1358 /* Optimize to handle small packets and headers */
1359 if (size < copybreak)
1360 size = copybreak;
1361 if (size < ETH_HLEN)
1362 size = ETH_HLEN;
14d0263f 1363
14d0263f
SH		 1364 sky2->rx_data_size = size;
1365
bd1c6869
SH		 1366 skb_queue_head_init(&sky2->rx_recycle);
1367
14d0263f 1368 /* Fill Rx ring */
793b883e 1369 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1370 re = sky2->rx_ring + i;
cd28ab6a 1371
14d0263f 1372 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1373 if (!re->skb)
1374 goto nomem;
1375
454e6cb6
SH		 1376 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1377 dev_kfree_skb(re->skb);
1378 re->skb = NULL;
1379 goto nomem;
1380 }
1381
14d0263f 1382 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1383 }
1384
a1433ac4
SH		 1385 /*
1386 * The receiver hangs if it receives frames larger than the
1387 * packet buffer. As a workaround, truncate oversize frames, but
1388 * the register is limited to 9 bits, so if you do frames > 2052
1389 * you better get the MTU right!
1390 */
a1433ac4
SH		 1391 if (thresh > 0x1ff)
1392 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1393 else {
1394 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1395 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1396 }
1397
6b1a3aef 1398 /* Tell chip about available buffers */
55c9dd35 1399 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1400 return 0;
1401nomem:
1402 sky2_rx_clean(sky2);
1403 return -ENOMEM;
1404}
1405
1406/* Bring up network interface. */
1407static int sky2_up(struct net_device *dev)
1408{
1409 struct sky2_port *sky2 = netdev_priv(dev);
1410 struct sky2_hw *hw = sky2->hw;
1411 unsigned port = sky2->port;
e0c28116 1412 u32 imask, ramsize;
ee7abb04 1413 int cap, err = -ENOMEM;
843a46f4 1414 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1415
ee7abb04
SH		 1416 /*
1417 * On dual port PCI-X card, there is an problem where status
1418 * can be received out of order due to split transactions
843a46f4 1419 */
ee7abb04
SH		 1420 if (otherdev && netif_running(otherdev) &&
1421 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1422 u16 cmd;
1423
b32f40c4 1424 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1425 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1426 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1427
ee7abb04 1428 }
843a46f4 1429
55d7b4e6
SH		 1430 netif_carrier_off(dev);
1431
cd28ab6a
SH		 1432 /* must be power of 2 */
1433 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1434 TX_RING_SIZE *
1435 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1436 &sky2->tx_le_map);
1437 if (!sky2->tx_le)
1438 goto err_out;
1439
6cdbbdf3 1440 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1441 GFP_KERNEL);
1442 if (!sky2->tx_ring)
1443 goto err_out;
88f5f0ca
SH		 1444
1445 tx_init(sky2);
cd28ab6a
SH		 1446
1447 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1448 &sky2->rx_le_map);
1449 if (!sky2->rx_le)
1450 goto err_out;
1451 memset(sky2->rx_le, 0, RX_LE_BYTES);
1452
291ea614 1453 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1454 GFP_KERNEL);
1455 if (!sky2->rx_ring)
1456 goto err_out;
1457
1458 sky2_mac_init(hw, port);
1459
e0c28116
SH		 1460 /* Register is number of 4K blocks on internal RAM buffer. */
1461 ramsize = sky2_read8(hw, B2_E_0) * 4;
1462 if (ramsize > 0) {
67712901 1463 u32 rxspace;
cd28ab6a 1464
39dbd958 1465 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1466 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1467 if (ramsize < 16)
1468 rxspace = ramsize / 2;
1469 else
1470 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1471
67712901
SH		 1472 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1473 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1474
1475 /* Make sure SyncQ is disabled */
1476 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1477 RB_RST_SET);
1478 }
793b883e 1479
af4ed7e6 1480 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1481
69161611
SH		 1482 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1483 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1484 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1485
977bdf06 1486 /* Set almost empty threshold */
c2716fb4
SH		 1487 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1488 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1489 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1490
6b1a3aef
SH		 1491 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1492 TX_RING_SIZE - 1);
cd28ab6a 1493
d494eacd
SH		 1494#ifdef SKY2_VLAN_TAG_USED
1495 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1496#endif
1497
6b1a3aef 1498 err = sky2_rx_start(sky2);
6de16237 1499 if (err)
cd28ab6a
SH		 1500 goto err_out;
1501
cd28ab6a 1502 /* Enable interrupts from phy/mac for port */
e07b1aa8 1503 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1504 imask |= portirq_msk[port];
e07b1aa8 1505 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1506 sky2_read32(hw, B0_IMSK);
e07b1aa8 1507
a7bffe72 1508 sky2_set_multicast(dev);
a11da890
AD		 1509
1510 if (netif_msg_ifup(sky2))
1511 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
cd28ab6a
SH		 1512 return 0;
1513
1514err_out:
1b537565 1515 if (sky2->rx_le) {
cd28ab6a
SH		 1516 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1517 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1518 sky2->rx_le = NULL;
1519 }
1520 if (sky2->tx_le) {
cd28ab6a
SH		 1521 pci_free_consistent(hw->pdev,
1522 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1523 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1524 sky2->tx_le = NULL;
1525 }
1526 kfree(sky2->tx_ring);
1527 kfree(sky2->rx_ring);
cd28ab6a 1528
1b537565
SH		 1529 sky2->tx_ring = NULL;
1530 sky2->rx_ring = NULL;
cd28ab6a
SH		 1531 return err;
1532}
1533
793b883e
SH		 1534/* Modular subtraction in ring */
1535static inline int tx_dist(unsigned tail, unsigned head)
1536{
cb5d9547 1537 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1538}
cd28ab6a 1539
793b883e
SH		 1540/* Number of list elements available for next tx */
1541static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1542{
793b883e 1543 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1544}
1545
793b883e 1546/* Estimate of number of transmit list elements required */
28bd181a 1547static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1548{
793b883e
SH		 1549 unsigned count;
1550
1551 count = sizeof(dma_addr_t) / sizeof(u32);
1552 count += skb_shinfo(skb)->nr_frags * count;
1553
89114afd 1554 if (skb_is_gso(skb))
793b883e
SH		 1555 ++count;
1556
84fa7933 1557 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1558 ++count;
1559
1560 return count;
cd28ab6a
SH		 1561}
1562
793b883e
SH		 1563/*
1564 * Put one packet in ring for transmit.
1565 * A single packet can generate multiple list elements, and
1566 * the number of ring elements will probably be less than the number
1567 * of list elements used.
1568 */
cd28ab6a
SH		 1569static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1570{
1571 struct sky2_port *sky2 = netdev_priv(dev);
1572 struct sky2_hw *hw = sky2->hw;
d1f13708 1573 struct sky2_tx_le *le = NULL;
6cdbbdf3 1574 struct tx_ring_info *re;
454e6cb6 1575 unsigned i, len, first_slot;
cd28ab6a 1576 dma_addr_t mapping;
cd28ab6a
SH		 1577 u16 mss;
1578 u8 ctrl;
1579
2bb8c262
SH		 1580 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1581 return NETDEV_TX_BUSY;
cd28ab6a 1582
cd28ab6a
SH		 1583 len = skb_headlen(skb);
1584 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1585
454e6cb6
SH		 1586 if (pci_dma_mapping_error(hw->pdev, mapping))
1587 goto mapping_error;
1588
1589 first_slot = sky2->tx_prod;
1590 if (unlikely(netif_msg_tx_queued(sky2)))
1591 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1592 dev->name, first_slot, skb->len);
1593
86c6887e
SH		 1594 /* Send high bits if needed */
1595 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1596 le = get_tx_le(sky2);
86c6887e 1597 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1598 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1599 }
cd28ab6a
SH		 1600
1601 /* Check for TCP Segmentation Offload */
7967168c 1602 mss = skb_shinfo(skb)->gso_size;
793b883e 1603 if (mss != 0) {
ea76e635
SH		 1604
1605 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1606 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1607
1608 if (mss != sky2->tx_last_mss) {
1609 le = get_tx_le(sky2);
1610 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1611
1612 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1613 le->opcode = OP_MSS | HW_OWNER;
1614 else
1615 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1616 sky2->tx_last_mss = mss;
1617 }
cd28ab6a
SH		 1618 }
1619
cd28ab6a 1620 ctrl = 0;
d1f13708
SH		 1621#ifdef SKY2_VLAN_TAG_USED
1622 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1623 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1624 if (!le) {
1625 le = get_tx_le(sky2);
f65b138c 1626 le->addr = 0;
d1f13708 1627 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1628 } else
1629 le->opcode |= OP_VLAN;
1630 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1631 ctrl |= INS_VLAN;
1632 }
1633#endif
1634
1635 /* Handle TCP checksum offload */
84fa7933 1636 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1637 /* On Yukon EX (some versions) encoding change. */
ea76e635 1638 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1639 ctrl |= CALSUM; /* auto checksum */
1640 else {
1641 const unsigned offset = skb_transport_offset(skb);
1642 u32 tcpsum;
1643
1644 tcpsum = offset << 16; /* sum start */
1645 tcpsum |= offset + skb->csum_offset; /* sum write */
1646
1647 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1648 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1649 ctrl |= UDPTCP;
1650
1651 if (tcpsum != sky2->tx_tcpsum) {
1652 sky2->tx_tcpsum = tcpsum;
1653
1654 le = get_tx_le(sky2);
1655 le->addr = cpu_to_le32(tcpsum);
1656 le->length = 0; /* initial checksum value */
1657 le->ctrl = 1; /* one packet */
1658 le->opcode = OP_TCPLISW | HW_OWNER;
1659 }
1d179332 1660 }
cd28ab6a
SH		 1661 }
1662
1663 le = get_tx_le(sky2);
f65b138c 1664 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1665 le->length = cpu_to_le16(len);
1666 le->ctrl = ctrl;
793b883e 1667 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1668
291ea614 1669 re = tx_le_re(sky2, le);
cd28ab6a 1670 re->skb = skb;
6cdbbdf3 1671 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1672 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1673
1674 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1675 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1676
1677 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1678 frag->size, PCI_DMA_TODEVICE);
86c6887e 1679
454e6cb6
SH		 1680 if (pci_dma_mapping_error(hw->pdev, mapping))
1681 goto mapping_unwind;
1682
86c6887e 1683 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1684 le = get_tx_le(sky2);
86c6887e 1685 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1686 le->ctrl = 0;
1687 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1688 }
1689
1690 le = get_tx_le(sky2);
f65b138c 1691 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1692 le->length = cpu_to_le16(frag->size);
1693 le->ctrl = ctrl;
793b883e 1694 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1695
291ea614
SH		 1696 re = tx_le_re(sky2, le);
1697 re->skb = skb;
1698 pci_unmap_addr_set(re, mapaddr, mapping);
1699 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1700 }
6cdbbdf3 1701
cd28ab6a
SH		 1702 le->ctrl |= EOP;
1703
97bda706
SH		 1704 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1705 netif_stop_queue(dev);
b19666d9 1706
290d4de5 1707 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1708
cd28ab6a 1709 return NETDEV_TX_OK;
454e6cb6
SH		 1710
1711mapping_unwind:
1712 for (i = first_slot; i != sky2->tx_prod; i = RING_NEXT(i, TX_RING_SIZE)) {
1713 le = sky2->tx_le + i;
1714 re = sky2->tx_ring + i;
1715
1716 switch(le->opcode & ~HW_OWNER) {
1717 case OP_LARGESEND:
1718 case OP_PACKET:
1719 pci_unmap_single(hw->pdev,
1720 pci_unmap_addr(re, mapaddr),
1721 pci_unmap_len(re, maplen),
1722 PCI_DMA_TODEVICE);
1723 break;
1724 case OP_BUFFER:
1725 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1726 pci_unmap_len(re, maplen),
1727 PCI_DMA_TODEVICE);
1728 break;
1729 }
1730 }
1731
1732 sky2->tx_prod = first_slot;
1733mapping_error:
1734 if (net_ratelimit())
1735 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1736 dev_kfree_skb(skb);
1737 return NETDEV_TX_OK;
cd28ab6a
SH		 1738}
1739
cd28ab6a 1740/*
793b883e
SH		 1741 * Free ring elements from starting at tx_cons until "done"
1742 *
1743 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1744 * buffers so make sure not to free skb to early.
cd28ab6a 1745 */
d11c13e7 1746static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1747{
d11c13e7 1748 struct net_device *dev = sky2->netdev;
af2a58ac 1749 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1750 unsigned idx;
cd28ab6a 1751
0e3ff6aa 1752 BUG_ON(done >= TX_RING_SIZE);
2224795d 1753
291ea614
SH		 1754 for (idx = sky2->tx_cons; idx != done;
1755 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1756 struct sky2_tx_le *le = sky2->tx_le + idx;
1757 struct tx_ring_info *re = sky2->tx_ring + idx;
1758
1759 switch(le->opcode & ~HW_OWNER) {
1760 case OP_LARGESEND:
1761 case OP_PACKET:
1762 pci_unmap_single(pdev,
1763 pci_unmap_addr(re, mapaddr),
1764 pci_unmap_len(re, maplen),
1765 PCI_DMA_TODEVICE);
af2a58ac 1766 break;
291ea614
SH		 1767 case OP_BUFFER:
1768 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1769 pci_unmap_len(re, maplen),
734d1868 1770 PCI_DMA_TODEVICE);
291ea614
SH		 1771 break;
1772 }
1773
1774 if (le->ctrl & EOP) {
bd1c6869
SH		 1775 struct sk_buff *skb = re->skb;
1776
291ea614
SH		 1777 if (unlikely(netif_msg_tx_done(sky2)))
1778 printk(KERN_DEBUG "%s: tx done %u\n",
1779 dev->name, idx);
3cf26753 1780
7138a0f5 1781 dev->stats.tx_packets++;
bd1c6869
SH		 1782 dev->stats.tx_bytes += skb->len;
1783
1784 if (skb_queue_len(&sky2->rx_recycle) < sky2->rx_pending
1785 && skb_recycle_check(skb, sky2->rx_data_size
1786 + sky2_rx_pad(sky2->hw)))
1787 __skb_queue_head(&sky2->rx_recycle, skb);
1788 else
1789 dev_kfree_skb_any(skb);
2bf56fe2 1790
3cf26753 1791 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1792 }
793b883e 1793 }
793b883e 1794
291ea614 1795 sky2->tx_cons = idx;
50432cb5
SH		 1796 smp_mb();
1797
22e11703 1798 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1799 netif_wake_queue(dev);
cd28ab6a
SH		 1800}
1801
1802/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1803static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1804{
2bb8c262
SH		 1805 struct sky2_port *sky2 = netdev_priv(dev);
1806
1807 netif_tx_lock_bh(dev);
d11c13e7 1808 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1809 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1810}
1811
1812/* Network shutdown */
1813static int sky2_down(struct net_device *dev)
1814{
1815 struct sky2_port *sky2 = netdev_priv(dev);
1816 struct sky2_hw *hw = sky2->hw;
1817 unsigned port = sky2->port;
1818 u16 ctrl;
e07b1aa8 1819 u32 imask;
cd28ab6a 1820
1b537565
SH		 1821 /* Never really got started! */
1822 if (!sky2->tx_le)
1823 return 0;
1824
cd28ab6a
SH		 1825 if (netif_msg_ifdown(sky2))
1826 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1827
ebc646f6
SH		 1828 /* Disable port IRQ */
1829 imask = sky2_read32(hw, B0_IMSK);
1830 imask &= ~portirq_msk[port];
1831 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1832 sky2_read32(hw, B0_IMSK);
ebc646f6 1833
d104acaf
SH		 1834 /* Force flow control off */
1835 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1836
cd28ab6a
SH		 1837 /* Stop transmitter */
1838 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1839 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1840
1841 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1842 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1843
1844 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1845 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1846 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1847
1848 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1849
1850 /* Workaround shared GMAC reset */
793b883e
SH		 1851 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1852 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1853 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1854
1855 /* Disable Force Sync bit and Enable Alloc bit */
1856 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1857 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1858
1859 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1860 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1861 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1862
1863 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1864 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1865 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1866
1867 /* Reset the Tx prefetch units */
1868 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1869 PREF_UNIT_RST_SET);
1870
1871 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1872
6b1a3aef 1873 sky2_rx_stop(sky2);
cd28ab6a
SH		 1874
1875 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1876 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1877
6c83504f
SH		 1878 /* Force any delayed status interrrupt and NAPI */
1879 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1880 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1881 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1882 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1883
1884 synchronize_irq(hw->pdev->irq);
1885 napi_synchronize(&hw->napi);
1886
b96936da 1887 sky2_phy_power_down(hw, port);
d3bcfbeb 1888
d571b694 1889 /* turn off LED's */
cd28ab6a
SH		 1890 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1891
2bb8c262 1892 sky2_tx_clean(dev);
cd28ab6a
SH		 1893 sky2_rx_clean(sky2);
1894
1895 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1896 sky2->rx_le, sky2->rx_le_map);
1897 kfree(sky2->rx_ring);
1898
1899 pci_free_consistent(hw->pdev,
1900 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1901 sky2->tx_le, sky2->tx_le_map);
1902 kfree(sky2->tx_ring);
1903
1b537565
SH		 1904 sky2->tx_le = NULL;
1905 sky2->rx_le = NULL;
1906
1907 sky2->rx_ring = NULL;
1908 sky2->tx_ring = NULL;
1909
cd28ab6a
SH		 1910 return 0;
1911}
1912
1913static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1914{
ea76e635 1915 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1916 return SPEED_1000;
1917
05745c4a
SH		 1918 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1919 if (aux & PHY_M_PS_SPEED_100)
1920 return SPEED_100;
1921 else
1922 return SPEED_10;
1923 }
cd28ab6a
SH		 1924
1925 switch (aux & PHY_M_PS_SPEED_MSK) {
1926 case PHY_M_PS_SPEED_1000:
1927 return SPEED_1000;
1928 case PHY_M_PS_SPEED_100:
1929 return SPEED_100;
1930 default:
1931 return SPEED_10;
1932 }
1933}
1934
1935static void sky2_link_up(struct sky2_port *sky2)
1936{
1937 struct sky2_hw *hw = sky2->hw;
1938 unsigned port = sky2->port;
1939 u16 reg;
16ad91e1
SH		 1940 static const char *fc_name[] = {
1941 [FC_NONE] = "none",
1942 [FC_TX] = "tx",
1943 [FC_RX] = "rx",
1944 [FC_BOTH] = "both",
1945 };
cd28ab6a 1946
cd28ab6a 1947 /* enable Rx/Tx */
2eaba1a2 1948 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1949 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1950 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1951
1952 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1953
1954 netif_carrier_on(sky2->netdev);
cd28ab6a 1955
75e80683 1956 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1957
cd28ab6a 1958 /* Turn on link LED */
793b883e 1959 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1960 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1961
1962 if (netif_msg_link(sky2))
1963 printk(KERN_INFO PFX
d571b694 1964 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1965 sky2->netdev->name, sky2->speed,
1966 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1967 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1968}
1969
1970static void sky2_link_down(struct sky2_port *sky2)
1971{
1972 struct sky2_hw *hw = sky2->hw;
1973 unsigned port = sky2->port;
1974 u16 reg;
1975
1976 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1977
1978 reg = gma_read16(hw, port, GM_GP_CTRL);
1979 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1980 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1981
cd28ab6a 1982 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1983
1984 /* Turn on link LED */
1985 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1986
1987 if (netif_msg_link(sky2))
1988 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1989
cd28ab6a
SH		 1990 sky2_phy_init(hw, port);
1991}
1992
16ad91e1
SH		 1993static enum flow_control sky2_flow(int rx, int tx)
1994{
1995 if (rx)
1996 return tx ? FC_BOTH : FC_RX;
1997 else
1998 return tx ? FC_TX : FC_NONE;
1999}
2000
793b883e
SH		 2001static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2002{
2003 struct sky2_hw *hw = sky2->hw;
2004 unsigned port = sky2->port;
da4c1ff4 2005 u16 advert, lpa;
793b883e 2006
da4c1ff4 2007 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2008 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 2009 if (lpa & PHY_M_AN_RF) {
2010 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2011 return -1;
2012 }
2013
793b883e
SH		 2014 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2015 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2016 sky2->netdev->name);
2017 return -1;
2018 }
2019
793b883e 2020 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2021 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2022
da4c1ff4
SH		 2023 /* Since the pause result bits seem to in different positions on
2024 * different chips. look at registers.
2025 */
ea76e635 2026 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2027 /* Shift for bits in fiber PHY */
2028 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2029 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2030
2031 if (advert & ADVERTISE_1000XPAUSE)
2032 advert |= ADVERTISE_PAUSE_CAP;
2033 if (advert & ADVERTISE_1000XPSE_ASYM)
2034 advert |= ADVERTISE_PAUSE_ASYM;
2035 if (lpa & LPA_1000XPAUSE)
2036 lpa |= LPA_PAUSE_CAP;
2037 if (lpa & LPA_1000XPAUSE_ASYM)
2038 lpa |= LPA_PAUSE_ASYM;
2039 }
793b883e 2040
da4c1ff4
SH		 2041 sky2->flow_status = FC_NONE;
2042 if (advert & ADVERTISE_PAUSE_CAP) {
2043 if (lpa & LPA_PAUSE_CAP)
2044 sky2->flow_status = FC_BOTH;
2045 else if (advert & ADVERTISE_PAUSE_ASYM)
2046 sky2->flow_status = FC_RX;
2047 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2048 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2049 sky2->flow_status = FC_TX;
2050 }
793b883e 2051
16ad91e1 2052 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 2053 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2054 sky2->flow_status = FC_NONE;
2eaba1a2 2055
da4c1ff4 2056 if (sky2->flow_status & FC_TX)
793b883e
SH		 2057 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2058 else
2059 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2060
2061 return 0;
2062}
cd28ab6a 2063
e07b1aa8
SH		 2064/* Interrupt from PHY */
2065static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2066{
e07b1aa8
SH		 2067 struct net_device *dev = hw->dev[port];
2068 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2069 u16 istatus, phystat;
2070
ebc646f6
SH		 2071 if (!netif_running(dev))
2072 return;
2073
e07b1aa8
SH		 2074 spin_lock(&sky2->phy_lock);
2075 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2076 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2077
cd28ab6a
SH		 2078 if (netif_msg_intr(sky2))
2079 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2080 sky2->netdev->name, istatus, phystat);
2081
2eaba1a2 2082 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 2083 if (sky2_autoneg_done(sky2, phystat) == 0)
2084 sky2_link_up(sky2);
2085 goto out;
2086 }
cd28ab6a 2087
793b883e
SH		 2088 if (istatus & PHY_M_IS_LSP_CHANGE)
2089 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2090
793b883e
SH		 2091 if (istatus & PHY_M_IS_DUP_CHANGE)
2092 sky2->duplex =
2093 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2094
793b883e
SH		 2095 if (istatus & PHY_M_IS_LST_CHANGE) {
2096 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2097 sky2_link_up(sky2);
793b883e
SH		 2098 else
2099 sky2_link_down(sky2);
cd28ab6a 2100 }
793b883e 2101out:
e07b1aa8 2102 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2103}
2104
62335ab0 2105/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2106 * and tx queue is full (stopped).
2107 */
cd28ab6a
SH		 2108static void sky2_tx_timeout(struct net_device *dev)
2109{
2110 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2111 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2112
2113 if (netif_msg_timer(sky2))
2114 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2115
8f24664d 2116 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2117 dev->name, sky2->tx_cons, sky2->tx_prod,
2118 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2119 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2120
81906791
SH		 2121 /* can't restart safely under softirq */
2122 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2123}
2124
2125static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2126{
6b1a3aef
SH		 2127 struct sky2_port *sky2 = netdev_priv(dev);
2128 struct sky2_hw *hw = sky2->hw;
b628ed98 2129 unsigned port = sky2->port;
6b1a3aef
SH		 2130 int err;
2131 u16 ctl, mode;
e07b1aa8 2132 u32 imask;
cd28ab6a
SH		 2133
2134 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2135 return -EINVAL;
2136
05745c4a
SH		 2137 if (new_mtu > ETH_DATA_LEN &&
2138 (hw->chip_id == CHIP_ID_YUKON_FE ||
2139 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2140 return -EINVAL;
2141
6b1a3aef
SH		 2142 if (!netif_running(dev)) {
2143 dev->mtu = new_mtu;
2144 return 0;
2145 }
2146
e07b1aa8 2147 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2148 sky2_write32(hw, B0_IMSK, 0);
2149
018d1c66
SH		 2150 dev->trans_start = jiffies; /* prevent tx timeout */
2151 netif_stop_queue(dev);
bea3348e 2152 napi_disable(&hw->napi);
018d1c66 2153
e07b1aa8
SH		 2154 synchronize_irq(hw->pdev->irq);
2155
39dbd958 2156 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2157 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2158
2159 ctl = gma_read16(hw, port, GM_GP_CTRL);
2160 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2161 sky2_rx_stop(sky2);
2162 sky2_rx_clean(sky2);
cd28ab6a
SH		 2163
2164 dev->mtu = new_mtu;
14d0263f 2165
6b1a3aef
SH		 2166 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2167 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2168
2169 if (dev->mtu > ETH_DATA_LEN)
2170 mode |= GM_SMOD_JUMBO_ENA;
2171
b628ed98 2172 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2173
b628ed98 2174 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2175
6b1a3aef 2176 err = sky2_rx_start(sky2);
e07b1aa8 2177 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2178
d1d08d12 2179 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2180 napi_enable(&hw->napi);
2181
1b537565
SH		 2182 if (err)
2183 dev_close(dev);
2184 else {
b628ed98 2185 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2186
1b537565
SH		 2187 netif_wake_queue(dev);
2188 }
2189
cd28ab6a
SH		 2190 return err;
2191}
2192
14d0263f
SH		 2193/* For small just reuse existing skb for next receive */
2194static struct sk_buff *receive_copy(struct sky2_port *sky2,
2195 const struct rx_ring_info *re,
2196 unsigned length)
2197{
2198 struct sk_buff *skb;
2199
2200 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2201 if (likely(skb)) {
2202 skb_reserve(skb, 2);
2203 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2204 length, PCI_DMA_FROMDEVICE);
d626f62b 2205 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2206 skb->ip_summed = re->skb->ip_summed;
2207 skb->csum = re->skb->csum;
2208 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2209 length, PCI_DMA_FROMDEVICE);
2210 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2211 skb_put(skb, length);
14d0263f
SH		 2212 }
2213 return skb;
2214}
2215
2216/* Adjust length of skb with fragments to match received data */
2217static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2218 unsigned int length)
2219{
2220 int i, num_frags;
2221 unsigned int size;
2222
2223 /* put header into skb */
2224 size = min(length, hdr_space);
2225 skb->tail += size;
2226 skb->len += size;
2227 length -= size;
2228
2229 num_frags = skb_shinfo(skb)->nr_frags;
2230 for (i = 0; i < num_frags; i++) {
2231 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2232
2233 if (length == 0) {
2234 /* don't need this page */
2235 __free_page(frag->page);
2236 --skb_shinfo(skb)->nr_frags;
2237 } else {
2238 size = min(length, (unsigned) PAGE_SIZE);
2239
2240 frag->size = size;
2241 skb->data_len += size;
2242 skb->truesize += size;
2243 skb->len += size;
2244 length -= size;
2245 }
2246 }
2247}
2248
2249/* Normal packet - take skb from ring element and put in a new one */
2250static struct sk_buff *receive_new(struct sky2_port *sky2,
2251 struct rx_ring_info *re,
2252 unsigned int length)
2253{
2254 struct sk_buff *skb, *nskb;
2255 unsigned hdr_space = sky2->rx_data_size;
2256
14d0263f
SH		 2257 /* Don't be tricky about reusing pages (yet) */
2258 nskb = sky2_rx_alloc(sky2);
2259 if (unlikely(!nskb))
2260 return NULL;
2261
2262 skb = re->skb;
2263 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2264
2265 prefetch(skb->data);
2266 re->skb = nskb;
454e6cb6
SH		 2267 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2268 dev_kfree_skb(nskb);
2269 re->skb = skb;
2270 return NULL;
2271 }
14d0263f
SH		 2272
2273 if (skb_shinfo(skb)->nr_frags)
2274 skb_put_frags(skb, hdr_space, length);
2275 else
489b10c1 2276 skb_put(skb, length);
14d0263f
SH		 2277 return skb;
2278}
2279
cd28ab6a
SH		 2280/*
2281 * Receive one packet.
d571b694 2282 * For larger packets, get new buffer.
cd28ab6a 2283 */
497d7c86 2284static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2285 u16 length, u32 status)
2286{
497d7c86 2287 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2288 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2289 struct sk_buff *skb = NULL;
d6532232
SH		 2290 u16 count = (status & GMR_FS_LEN) >> 16;
2291
2292#ifdef SKY2_VLAN_TAG_USED
2293 /* Account for vlan tag */
2294 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2295 count -= VLAN_HLEN;
2296#endif
cd28ab6a
SH		 2297
2298 if (unlikely(netif_msg_rx_status(sky2)))
2299 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2300 dev->name, sky2->rx_next, status, length);
cd28ab6a 2301
793b883e 2302 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2303 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2304
3b12e014
SH		 2305 /* This chip has hardware problems that generates bogus status.
2306 * So do only marginal checking and expect higher level protocols
2307 * to handle crap frames.
2308 */
2309 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2310 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2311 length != count)
2312 goto okay;
2313
42eeea01 2314 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2315 goto error;
2316
42eeea01
SH		 2317 if (!(status & GMR_FS_RX_OK))
2318 goto resubmit;
2319
d6532232
SH		 2320 /* if length reported by DMA does not match PHY, packet was truncated */
2321 if (length != count)
3b12e014 2322 goto len_error;
71749531 2323
3b12e014 2324okay:
14d0263f
SH		 2325 if (length < copybreak)
2326 skb = receive_copy(sky2, re, length);
2327 else
2328 skb = receive_new(sky2, re, length);
793b883e 2329resubmit:
14d0263f 2330 sky2_rx_submit(sky2, re);
79e57d32 2331
cd28ab6a
SH		 2332 return skb;
2333
3b12e014 2334len_error:
71749531
SH		 2335 /* Truncation of overlength packets
2336 causes PHY length to not match MAC length */
7138a0f5 2337 ++dev->stats.rx_length_errors;
d6532232 2338 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2339 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2340 dev->name, status, length);
d6532232 2341 goto resubmit;
71749531 2342
cd28ab6a 2343error:
7138a0f5 2344 ++dev->stats.rx_errors;
b6d77734 2345 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2346 dev->stats.rx_over_errors++;
b6d77734
SH		 2347 goto resubmit;
2348 }
6e15b712 2349
3be92a70 2350 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2351 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2352 dev->name, status, length);
793b883e
SH		 2353
2354 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2355 dev->stats.rx_length_errors++;
cd28ab6a 2356 if (status & GMR_FS_FRAGMENT)
7138a0f5 2357 dev->stats.rx_frame_errors++;
cd28ab6a 2358 if (status & GMR_FS_CRC_ERR)
7138a0f5 2359 dev->stats.rx_crc_errors++;
79e57d32 2360
793b883e 2361 goto resubmit;
cd28ab6a
SH		 2362}
2363
e07b1aa8
SH		 2364/* Transmit complete */
2365static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2366{
e07b1aa8 2367 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2368
e07b1aa8 2369 if (netif_running(dev)) {
2bb8c262 2370 netif_tx_lock(dev);
e07b1aa8 2371 sky2_tx_complete(sky2, last);
2bb8c262 2372 netif_tx_unlock(dev);
2224795d 2373 }
cd28ab6a
SH		 2374}
2375
bf15fe99
SH		 2376static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2377 unsigned packets, unsigned bytes)
2378{
2379 if (packets) {
2380 struct net_device *dev = hw->dev[port];
2381
2382 dev->stats.rx_packets += packets;
2383 dev->stats.rx_bytes += bytes;
2384 dev->last_rx = jiffies;
2385 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2386 }
2387}
2388
e07b1aa8 2389/* Process status response ring */
26691830 2390static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2391{
e07b1aa8 2392 int work_done = 0;
bf15fe99
SH		 2393 unsigned int total_bytes[2] = { 0 };
2394 unsigned int total_packets[2] = { 0 };
a8fd6266 2395
af2a58ac 2396 rmb();
26691830 2397 do {
55c9dd35 2398 struct sky2_port *sky2;
13210ce5 2399 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2400 unsigned port;
13210ce5 2401 struct net_device *dev;
cd28ab6a 2402 struct sk_buff *skb;
cd28ab6a
SH		 2403 u32 status;
2404 u16 length;
ab5adecb
SH		 2405 u8 opcode = le->opcode;
2406
2407 if (!(opcode & HW_OWNER))
2408 break;
cd28ab6a 2409
cb5d9547 2410 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2411
ab5adecb 2412 port = le->css & CSS_LINK_BIT;
69161611 2413 dev = hw->dev[port];
13210ce5 2414 sky2 = netdev_priv(dev);
f65b138c
SH		 2415 length = le16_to_cpu(le->length);
2416 status = le32_to_cpu(le->status);
cd28ab6a 2417
ab5adecb
SH		 2418 le->opcode = 0;
2419 switch (opcode & ~HW_OWNER) {
cd28ab6a 2420 case OP_RXSTAT:
bf15fe99
SH		 2421 total_packets[port]++;
2422 total_bytes[port] += length;
497d7c86 2423 skb = sky2_receive(dev, length, status);
3225b919 2424 if (unlikely(!skb)) {
7138a0f5 2425 dev->stats.rx_dropped++;
55c9dd35 2426 break;
3225b919 2427 }
13210ce5 2428
69161611 2429 /* This chip reports checksum status differently */
05745c4a 2430 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2431 if (sky2->rx_csum &&
2432 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2433 (le->css & CSS_TCPUDPCSOK))
2434 skb->ip_summed = CHECKSUM_UNNECESSARY;
2435 else
2436 skb->ip_summed = CHECKSUM_NONE;
2437 }
2438
13210ce5 2439 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2440
d1f13708
SH		 2441#ifdef SKY2_VLAN_TAG_USED
2442 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2443 vlan_hwaccel_receive_skb(skb,
2444 sky2->vlgrp,
2445 be16_to_cpu(sky2->rx_tag));
2446 } else
2447#endif
cd28ab6a 2448 netif_receive_skb(skb);
13210ce5 2449
22e11703 2450 /* Stop after net poll weight */
13210ce5
SH		 2451 if (++work_done >= to_do)
2452 goto exit_loop;
cd28ab6a
SH		 2453 break;
2454
d1f13708
SH		 2455#ifdef SKY2_VLAN_TAG_USED
2456 case OP_RXVLAN:
2457 sky2->rx_tag = length;
2458 break;
2459
2460 case OP_RXCHKSVLAN:
2461 sky2->rx_tag = length;
2462 /* fall through */
2463#endif
cd28ab6a 2464 case OP_RXCHKS:
87418307
SH		 2465 if (!sky2->rx_csum)
2466 break;
2467
05745c4a
SH		 2468 /* If this happens then driver assuming wrong format */
2469 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2470 if (net_ratelimit())
2471 printk(KERN_NOTICE "%s: unexpected"
2472 " checksum status\n",
2473 dev->name);
69161611 2474 break;
05745c4a 2475 }
69161611 2476
87418307
SH		 2477 /* Both checksum counters are programmed to start at
2478 * the same offset, so unless there is a problem they
2479 * should match. This failure is an early indication that
2480 * hardware receive checksumming won't work.
2481 */
2482 if (likely(status >> 16 == (status & 0xffff))) {
2483 skb = sky2->rx_ring[sky2->rx_next].skb;
2484 skb->ip_summed = CHECKSUM_COMPLETE;
2485 skb->csum = status & 0xffff;
2486 } else {
2487 printk(KERN_NOTICE PFX "%s: hardware receive "
2488 "checksum problem (status = %#x)\n",
2489 dev->name, status);
2490 sky2->rx_csum = 0;
2491 sky2_write32(sky2->hw,
69161611 2492 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2493 BMU_DIS_RX_CHKSUM);
2494 }
cd28ab6a
SH		 2495 break;
2496
2497 case OP_TXINDEXLE:
13b97b74 2498 /* TX index reports status for both ports */
f55925d7
SH		 2499 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2500 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2501 if (hw->dev[1])
2502 sky2_tx_done(hw->dev[1],
2503 ((status >> 24) & 0xff)
2504 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2505 break;
2506
cd28ab6a
SH		 2507 default:
2508 if (net_ratelimit())
793b883e 2509 printk(KERN_WARNING PFX
ab5adecb 2510 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2511 }
26691830 2512 } while (hw->st_idx != idx);
cd28ab6a 2513
fe2a24df
SH		 2514 /* Fully processed status ring so clear irq */
2515 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2516
13210ce5 2517exit_loop:
bf15fe99
SH		 2518 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2519 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2520
e07b1aa8 2521 return work_done;
cd28ab6a
SH		 2522}
2523
2524static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2525{
2526 struct net_device *dev = hw->dev[port];
2527
3be92a70
SH		 2528 if (net_ratelimit())
2529 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2530 dev->name, status);
cd28ab6a
SH		 2531
2532 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2533 if (net_ratelimit())
2534 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2535 dev->name);
cd28ab6a
SH		 2536 /* Clear IRQ */
2537 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2538 }
2539
2540 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2541 if (net_ratelimit())
2542 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2543 dev->name);
cd28ab6a
SH		 2544
2545 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2546 }
2547
2548 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2549 if (net_ratelimit())
2550 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2551 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2552 }
2553
2554 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2555 if (net_ratelimit())
2556 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2557 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2558 }
2559
2560 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2561 if (net_ratelimit())
2562 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2563 dev->name);
cd28ab6a
SH		 2564 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2565 }
2566}
2567
2568static void sky2_hw_intr(struct sky2_hw *hw)
2569{
555382cb 2570 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2571 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2572 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2573
2574 status &= hwmsk;
cd28ab6a 2575
793b883e 2576 if (status & Y2_IS_TIST_OV)
cd28ab6a 2577 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2578
2579 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2580 u16 pci_err;
2581
82637e80 2582 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2583 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2584 if (net_ratelimit())
555382cb 2585 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2586 pci_err);
cd28ab6a 2587
b32f40c4 2588 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2589 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2590 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2591 }
2592
2593 if (status & Y2_IS_PCI_EXP) {
d571b694 2594 /* PCI-Express uncorrectable Error occurred */
555382cb 2595 u32 err;
cd28ab6a 2596
82637e80 2597 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2598 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2599 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2600 0xfffffffful);
3be92a70 2601 if (net_ratelimit())
555382cb 2602 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2603
7782c8c4 2604 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2605 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2606 }
2607
2608 if (status & Y2_HWE_L1_MASK)
2609 sky2_hw_error(hw, 0, status);
2610 status >>= 8;
2611 if (status & Y2_HWE_L1_MASK)
2612 sky2_hw_error(hw, 1, status);
2613}
2614
2615static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2616{
2617 struct net_device *dev = hw->dev[port];
2618 struct sky2_port *sky2 = netdev_priv(dev);
2619 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2620
2621 if (netif_msg_intr(sky2))
2622 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2623 dev->name, status);
2624
a3caeada
SH		 2625 if (status & GM_IS_RX_CO_OV)
2626 gma_read16(hw, port, GM_RX_IRQ_SRC);
2627
2628 if (status & GM_IS_TX_CO_OV)
2629 gma_read16(hw, port, GM_TX_IRQ_SRC);
2630
cd28ab6a 2631 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2632 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2633 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2634 }
2635
2636 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2637 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2638 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2639 }
cd28ab6a
SH		 2640}
2641
40b01727
SH		 2642/* This should never happen it is a bug. */
2643static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2644 u16 q, unsigned ring_size)
d257924e
SH		 2645{
2646 struct net_device *dev = hw->dev[port];
2647 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2648 unsigned idx;
2649 const u64 *le = (q == Q_R1 || q == Q_R2)
2650 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2651
40b01727
SH		 2652 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2653 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2654 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2655 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2656
40b01727 2657 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2658}
cd28ab6a 2659
75e80683
SH		 2660static int sky2_rx_hung(struct net_device *dev)
2661{
2662 struct sky2_port *sky2 = netdev_priv(dev);
2663 struct sky2_hw *hw = sky2->hw;
2664 unsigned port = sky2->port;
2665 unsigned rxq = rxqaddr[port];
2666 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2667 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2668 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2669 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2670
2671 /* If idle and MAC or PCI is stuck */
2672 if (sky2->check.last == dev->last_rx &&
2673 ((mac_rp == sky2->check.mac_rp &&
2674 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2675 /* Check if the PCI RX hang */
2676 (fifo_rp == sky2->check.fifo_rp &&
2677 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2678 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2679 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2680 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2681 return 1;
2682 } else {
2683 sky2->check.last = dev->last_rx;
2684 sky2->check.mac_rp = mac_rp;
2685 sky2->check.mac_lev = mac_lev;
2686 sky2->check.fifo_rp = fifo_rp;
2687 sky2->check.fifo_lev = fifo_lev;
2688 return 0;
2689 }
2690}
2691
32c2c300 2692static void sky2_watchdog(unsigned long arg)
d27ed387 2693{
01bd7564 2694 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2695
75e80683 2696 /* Check for lost IRQ once a second */
32c2c300 2697 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2698 napi_schedule(&hw->napi);
75e80683
SH		 2699 } else {
2700 int i, active = 0;
2701
2702 for (i = 0; i < hw->ports; i++) {
bea3348e 2703 struct net_device *dev = hw->dev[i];
75e80683
SH		 2704 if (!netif_running(dev))
2705 continue;
2706 ++active;
2707
2708 /* For chips with Rx FIFO, check if stuck */
39dbd958 2709 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2710 sky2_rx_hung(dev)) {
2711 pr_info(PFX "%s: receiver hang detected\n",
2712 dev->name);
2713 schedule_work(&hw->restart_work);
2714 return;
2715 }
2716 }
2717
2718 if (active == 0)
2719 return;
32c2c300 2720 }
01bd7564 2721
75e80683 2722 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2723}
2724
40b01727
SH		 2725/* Hardware/software error handling */
2726static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2727{
40b01727
SH		 2728 if (net_ratelimit())
2729 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2730
1e5f1283
SH		 2731 if (status & Y2_IS_HW_ERR)
2732 sky2_hw_intr(hw);
d257924e 2733
1e5f1283
SH		 2734 if (status & Y2_IS_IRQ_MAC1)
2735 sky2_mac_intr(hw, 0);
cd28ab6a 2736
1e5f1283
SH		 2737 if (status & Y2_IS_IRQ_MAC2)
2738 sky2_mac_intr(hw, 1);
cd28ab6a 2739
1e5f1283 2740 if (status & Y2_IS_CHK_RX1)
40b01727 2741 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2742
1e5f1283 2743 if (status & Y2_IS_CHK_RX2)
40b01727 2744 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2745
1e5f1283 2746 if (status & Y2_IS_CHK_TXA1)
40b01727 2747 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2748
1e5f1283 2749 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2750 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2751}
2752
bea3348e 2753static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2754{
bea3348e 2755 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2756 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2757 int work_done = 0;
26691830 2758 u16 idx;
40b01727
SH		 2759
2760 if (unlikely(status & Y2_IS_ERROR))
2761 sky2_err_intr(hw, status);
2762
2763 if (status & Y2_IS_IRQ_PHY1)
2764 sky2_phy_intr(hw, 0);
2765
2766 if (status & Y2_IS_IRQ_PHY2)
2767 sky2_phy_intr(hw, 1);
cd28ab6a 2768
26691830
SH		 2769 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2770 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2771
2772 if (work_done >= work_limit)
26691830
SH		 2773 goto done;
2774 }
6f535763 2775
26691830
SH		 2776 napi_complete(napi);
2777 sky2_read32(hw, B0_Y2_SP_LISR);
2778done:
6f535763 2779
bea3348e 2780 return work_done;
e07b1aa8
SH		 2781}
2782
7d12e780 2783static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2784{
2785 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2786 u32 status;
2787
2788 /* Reading this mask interrupts as side effect */
2789 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2790 if (status == 0 || status == ~0)
2791 return IRQ_NONE;
793b883e 2792
e07b1aa8 2793 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2794
2795 napi_schedule(&hw->napi);
793b883e 2796
cd28ab6a
SH		 2797 return IRQ_HANDLED;
2798}
2799
2800#ifdef CONFIG_NET_POLL_CONTROLLER
2801static void sky2_netpoll(struct net_device *dev)
2802{
2803 struct sky2_port *sky2 = netdev_priv(dev);
2804
bea3348e 2805 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2806}
2807#endif
2808
2809/* Chip internal frequency for clock calculations */
05745c4a 2810static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2811{
793b883e 2812 switch (hw->chip_id) {
cd28ab6a 2813 case CHIP_ID_YUKON_EC:
5a5b1ea0 2814 case CHIP_ID_YUKON_EC_U:
93745494 2815 case CHIP_ID_YUKON_EX:
ed4d4161 2816 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2817 case CHIP_ID_YUKON_UL_2:
05745c4a
SH		 2818 return 125;
2819
cd28ab6a 2820 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2821 return 100;
2822
2823 case CHIP_ID_YUKON_FE_P:
2824 return 50;
2825
2826 case CHIP_ID_YUKON_XL:
2827 return 156;
2828
2829 default:
2830 BUG();
cd28ab6a
SH		 2831 }
2832}
2833
fb17358f 2834static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2835{
fb17358f 2836 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2837}
2838
fb17358f 2839static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2840{
fb17358f 2841 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2842}
2843
fb17358f 2844
e3173832 2845static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2846{
b89165f2 2847 u8 t8;
cd28ab6a 2848
167f53d0 2849 /* Enable all clocks and check for bad PCI access */
b32f40c4 2850 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2851
cd28ab6a 2852 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2853
cd28ab6a 2854 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2855 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2856
2857 switch(hw->chip_id) {
2858 case CHIP_ID_YUKON_XL:
39dbd958 2859 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2860 break;
2861
2862 case CHIP_ID_YUKON_EC_U:
2863 hw->flags = SKY2_HW_GIGABIT
2864 | SKY2_HW_NEWER_PHY
2865 | SKY2_HW_ADV_POWER_CTL;
2866 break;
2867
2868 case CHIP_ID_YUKON_EX:
2869 hw->flags = SKY2_HW_GIGABIT
2870 | SKY2_HW_NEWER_PHY
2871 | SKY2_HW_NEW_LE
2872 | SKY2_HW_ADV_POWER_CTL;
2873
2874 /* New transmit checksum */
2875 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2876 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2877 break;
2878
2879 case CHIP_ID_YUKON_EC:
2880 /* This rev is really old, and requires untested workarounds */
2881 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2882 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2883 return -EOPNOTSUPP;
2884 }
39dbd958 2885 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2886 break;
2887
2888 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2889 break;
2890
05745c4a
SH		 2891 case CHIP_ID_YUKON_FE_P:
2892 hw->flags = SKY2_HW_NEWER_PHY
2893 | SKY2_HW_NEW_LE
2894 | SKY2_HW_AUTO_TX_SUM
2895 | SKY2_HW_ADV_POWER_CTL;
2896 break;
ed4d4161
SH		 2897
2898 case CHIP_ID_YUKON_SUPR:
2899 hw->flags = SKY2_HW_GIGABIT
2900 | SKY2_HW_NEWER_PHY
2901 | SKY2_HW_NEW_LE
2902 | SKY2_HW_AUTO_TX_SUM
2903 | SKY2_HW_ADV_POWER_CTL;
2904 break;
2905
0ce8b98d
SH		 2906 case CHIP_ID_YUKON_UL_2:
2907 hw->flags = SKY2_HW_GIGABIT
2908 | SKY2_HW_ADV_POWER_CTL;
2909 break;
2910
ea76e635 2911 default:
b02a9258
SH		 2912 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2913 hw->chip_id);
cd28ab6a
SH		 2914 return -EOPNOTSUPP;
2915 }
2916
ea76e635
SH		 2917 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2918 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2919 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2920
e3173832
SH		 2921 hw->ports = 1;
2922 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2923 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2924 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2925 ++hw->ports;
2926 }
2927
2928 return 0;
2929}
2930
2931static void sky2_reset(struct sky2_hw *hw)
2932{
555382cb 2933 struct pci_dev *pdev = hw->pdev;
e3173832 2934 u16 status;
555382cb
SH		 2935 int i, cap;
2936 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2937
cd28ab6a 2938 /* disable ASF */
4f44d8ba
SH		 2939 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2940 status = sky2_read16(hw, HCU_CCSR);
2941 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2942 HCU_CCSR_UC_STATE_MSK);
2943 sky2_write16(hw, HCU_CCSR, status);
2944 } else
2945 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2946 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2947
2948 /* do a SW reset */
2949 sky2_write8(hw, B0_CTST, CS_RST_SET);
2950 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2951
ac93a394
SH		 2952 /* allow writes to PCI config */
2953 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2954
cd28ab6a 2955 /* clear PCI errors, if any */
b32f40c4 2956 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2957 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2958 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2959
2960 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2961
555382cb
SH		 2962 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2963 if (cap) {
7782c8c4
SH		 2964 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2965 0xfffffffful);
555382cb
SH		 2966
2967 /* If error bit is stuck on ignore it */
2968 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2969 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2970 else
555382cb
SH		 2971 hwe_mask |= Y2_IS_PCI_EXP;
2972 }
cd28ab6a 2973
ae306cca 2974 sky2_power_on(hw);
82637e80 2975 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2976
2977 for (i = 0; i < hw->ports; i++) {
2978 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2979 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2980
ed4d4161
SH		 2981 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2982 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2983 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2984 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2985 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2986 }
2987
793b883e
SH		 2988 /* Clear I2C IRQ noise */
2989 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2990
2991 /* turn off hardware timer (unused) */
2992 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2993 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2994
cd28ab6a
SH		 2995 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2996
69634ee7
SH		 2997 /* Turn off descriptor polling */
2998 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2999
3000 /* Turn off receive timestamp */
3001 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3002 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3003
3004 /* enable the Tx Arbiters */
3005 for (i = 0; i < hw->ports; i++)
3006 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3007
3008 /* Initialize ram interface */
3009 for (i = 0; i < hw->ports; i++) {
793b883e 3010 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3011
3012 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3013 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3014 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3015 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3016 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3017 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3018 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3019 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3020 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3021 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3022 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3023 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3024 }
3025
555382cb 3026 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3027
cd28ab6a 3028 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3029 sky2_gmac_reset(hw, i);
cd28ab6a 3030
cd28ab6a
SH		 3031 memset(hw->st_le, 0, STATUS_LE_BYTES);
3032 hw->st_idx = 0;
3033
3034 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3035 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3036
3037 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3038 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3039
3040 /* Set the list last index */
793b883e 3041 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3042
290d4de5
SH		 3043 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3044 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3045
290d4de5
SH		 3046 /* set Status-FIFO ISR watermark */
3047 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3048 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3049 else
3050 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3051
290d4de5 3052 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3053 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3054 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3055
793b883e 3056 /* enable status unit */
cd28ab6a
SH		 3057 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3058
3059 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3060 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3061 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3062}
3063
81906791
SH		 3064static void sky2_restart(struct work_struct *work)
3065{
3066 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3067 struct net_device *dev;
3068 int i, err;
3069
81906791 3070 rtnl_lock();
81906791
SH		 3071 for (i = 0; i < hw->ports; i++) {
3072 dev = hw->dev[i];
3073 if (netif_running(dev))
3074 sky2_down(dev);
3075 }
3076
8cfcbe99
SH		 3077 napi_disable(&hw->napi);
3078 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3079 sky2_reset(hw);
3080 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3081 napi_enable(&hw->napi);
81906791
SH		 3082
3083 for (i = 0; i < hw->ports; i++) {
3084 dev = hw->dev[i];
3085 if (netif_running(dev)) {
3086 err = sky2_up(dev);
3087 if (err) {
3088 printk(KERN_INFO PFX "%s: could not restart %d\n",
3089 dev->name, err);
3090 dev_close(dev);
3091 }
3092 }
3093 }
3094
81906791
SH		 3095 rtnl_unlock();
3096}
3097
e3173832
SH		 3098static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3099{
3100 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3101}
3102
3103static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3104{
3105 const struct sky2_port *sky2 = netdev_priv(dev);
3106
3107 wol->supported = sky2_wol_supported(sky2->hw);
3108 wol->wolopts = sky2->wol;
3109}
3110
3111static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3112{
3113 struct sky2_port *sky2 = netdev_priv(dev);
3114 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3115
9d731d77
RW		 3116 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3117 || !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3118 return -EOPNOTSUPP;
3119
3120 sky2->wol = wol->wolopts;
3121
05745c4a
SH		 3122 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3123 hw->chip_id == CHIP_ID_YUKON_EX ||
3124 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3125 sky2_write32(hw, B0_CTST, sky2->wol
3126 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3127
9d731d77
RW		 3128 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3129
e3173832
SH		 3130 if (!netif_running(dev))
3131 sky2_wol_init(sky2);
cd28ab6a
SH		 3132 return 0;
3133}
3134
28bd181a 3135static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3136{
b89165f2
SH		 3137 if (sky2_is_copper(hw)) {
3138 u32 modes = SUPPORTED_10baseT_Half
3139 | SUPPORTED_10baseT_Full
3140 | SUPPORTED_100baseT_Half
3141 | SUPPORTED_100baseT_Full
3142 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3143
ea76e635 3144 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3145 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3146 | SUPPORTED_1000baseT_Full;
3147 return modes;
cd28ab6a 3148 } else
b89165f2
SH		 3149 return SUPPORTED_1000baseT_Half
3150 | SUPPORTED_1000baseT_Full
3151 | SUPPORTED_Autoneg
3152 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3153}
3154
793b883e 3155static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3156{
3157 struct sky2_port *sky2 = netdev_priv(dev);
3158 struct sky2_hw *hw = sky2->hw;
3159
3160 ecmd->transceiver = XCVR_INTERNAL;
3161 ecmd->supported = sky2_supported_modes(hw);
3162 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3163 if (sky2_is_copper(hw)) {
cd28ab6a 3164 ecmd->port = PORT_TP;
b89165f2
SH		 3165 ecmd->speed = sky2->speed;
3166 } else {
3167 ecmd->speed = SPEED_1000;
cd28ab6a 3168 ecmd->port = PORT_FIBRE;
b89165f2 3169 }
cd28ab6a
SH		 3170
3171 ecmd->advertising = sky2->advertising;
3172 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3173 ecmd->duplex = sky2->duplex;
3174 return 0;
3175}
3176
3177static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3178{
3179 struct sky2_port *sky2 = netdev_priv(dev);
3180 const struct sky2_hw *hw = sky2->hw;
3181 u32 supported = sky2_supported_modes(hw);
3182
3183 if (ecmd->autoneg == AUTONEG_ENABLE) {
3184 ecmd->advertising = supported;
3185 sky2->duplex = -1;
3186 sky2->speed = -1;
3187 } else {
3188 u32 setting;
3189
793b883e 3190 switch (ecmd->speed) {
cd28ab6a
SH		 3191 case SPEED_1000:
3192 if (ecmd->duplex == DUPLEX_FULL)
3193 setting = SUPPORTED_1000baseT_Full;
3194 else if (ecmd->duplex == DUPLEX_HALF)
3195 setting = SUPPORTED_1000baseT_Half;
3196 else
3197 return -EINVAL;
3198 break;
3199 case SPEED_100:
3200 if (ecmd->duplex == DUPLEX_FULL)
3201 setting = SUPPORTED_100baseT_Full;
3202 else if (ecmd->duplex == DUPLEX_HALF)
3203 setting = SUPPORTED_100baseT_Half;
3204 else
3205 return -EINVAL;
3206 break;
3207
3208 case SPEED_10:
3209 if (ecmd->duplex == DUPLEX_FULL)
3210 setting = SUPPORTED_10baseT_Full;
3211 else if (ecmd->duplex == DUPLEX_HALF)
3212 setting = SUPPORTED_10baseT_Half;
3213 else
3214 return -EINVAL;
3215 break;
3216 default:
3217 return -EINVAL;
3218 }
3219
3220 if ((setting & supported) == 0)
3221 return -EINVAL;
3222
3223 sky2->speed = ecmd->speed;
3224 sky2->duplex = ecmd->duplex;
3225 }
3226
3227 sky2->autoneg = ecmd->autoneg;
3228 sky2->advertising = ecmd->advertising;
3229
d1b139c0 3230 if (netif_running(dev)) {
1b537565 3231 sky2_phy_reinit(sky2);
d1b139c0
SH		 3232 sky2_set_multicast(dev);
3233 }
cd28ab6a
SH		 3234
3235 return 0;
3236}
3237
3238static void sky2_get_drvinfo(struct net_device *dev,
3239 struct ethtool_drvinfo *info)
3240{
3241 struct sky2_port *sky2 = netdev_priv(dev);
3242
3243 strcpy(info->driver, DRV_NAME);
3244 strcpy(info->version, DRV_VERSION);
3245 strcpy(info->fw_version, "N/A");
3246 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3247}
3248
3249static const struct sky2_stat {
793b883e
SH		 3250 char name[ETH_GSTRING_LEN];
3251 u16 offset;
cd28ab6a
SH		 3252} sky2_stats[] = {
3253 { "tx_bytes", GM_TXO_OK_HI },
3254 { "rx_bytes", GM_RXO_OK_HI },
3255 { "tx_broadcast", GM_TXF_BC_OK },
3256 { "rx_broadcast", GM_RXF_BC_OK },
3257 { "tx_multicast", GM_TXF_MC_OK },
3258 { "rx_multicast", GM_RXF_MC_OK },
3259 { "tx_unicast", GM_TXF_UC_OK },
3260 { "rx_unicast", GM_RXF_UC_OK },
3261 { "tx_mac_pause", GM_TXF_MPAUSE },
3262 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3263 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3264 { "late_collision",GM_TXF_LAT_COL },
3265 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3266 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3267 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3268
d2604540 3269 { "rx_short", GM_RXF_SHT },
cd28ab6a 3270 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3271 { "rx_64_byte_packets", GM_RXF_64B },
3272 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3273 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3274 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3275 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3276 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3277 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3278 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3279 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3280 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3281 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3282
3283 { "tx_64_byte_packets", GM_TXF_64B },
3284 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3285 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3286 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3287 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3288 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3289 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3290 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3291};
3292
cd28ab6a
SH		 3293static u32 sky2_get_rx_csum(struct net_device *dev)
3294{
3295 struct sky2_port *sky2 = netdev_priv(dev);
3296
3297 return sky2->rx_csum;
3298}
3299
3300static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3301{
3302 struct sky2_port *sky2 = netdev_priv(dev);
3303
3304 sky2->rx_csum = data;
793b883e 3305
cd28ab6a
SH		 3306 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3307 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3308
3309 return 0;
3310}
3311
3312static u32 sky2_get_msglevel(struct net_device *netdev)
3313{
3314 struct sky2_port *sky2 = netdev_priv(netdev);
3315 return sky2->msg_enable;
3316}
3317
9a7ae0a9
SH		 3318static int sky2_nway_reset(struct net_device *dev)
3319{
3320 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3321
16ad91e1 3322 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3323 return -EINVAL;
3324
1b537565 3325 sky2_phy_reinit(sky2);
d1b139c0 3326 sky2_set_multicast(dev);
9a7ae0a9
SH		 3327
3328 return 0;
3329}
3330
793b883e 3331static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3332{
3333 struct sky2_hw *hw = sky2->hw;
3334 unsigned port = sky2->port;
3335 int i;
3336
3337 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3338 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3339 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3340 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3341
793b883e 3342 for (i = 2; i < count; i++)
cd28ab6a
SH		 3343 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3344}
3345
cd28ab6a
SH		 3346static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3347{
3348 struct sky2_port *sky2 = netdev_priv(netdev);
3349 sky2->msg_enable = value;
3350}
3351
b9f2c044 3352static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3353{
b9f2c044
JG		 3354 switch (sset) {
3355 case ETH_SS_STATS:
3356 return ARRAY_SIZE(sky2_stats);
3357 default:
3358 return -EOPNOTSUPP;
3359 }
cd28ab6a
SH		 3360}
3361
3362static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3363 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3364{
3365 struct sky2_port *sky2 = netdev_priv(dev);
3366
793b883e 3367 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3368}
3369
793b883e 3370static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3371{
3372 int i;
3373
3374 switch (stringset) {
3375 case ETH_SS_STATS:
3376 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3377 memcpy(data + i * ETH_GSTRING_LEN,
3378 sky2_stats[i].name, ETH_GSTRING_LEN);
3379 break;
3380 }
3381}
3382
cd28ab6a
SH		 3383static int sky2_set_mac_address(struct net_device *dev, void *p)
3384{
3385 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3386 struct sky2_hw *hw = sky2->hw;
3387 unsigned port = sky2->port;
3388 const struct sockaddr *addr = p;
cd28ab6a
SH		 3389
3390 if (!is_valid_ether_addr(addr->sa_data))
3391 return -EADDRNOTAVAIL;
3392
cd28ab6a 3393 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3394 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3395 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3396 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3397 dev->dev_addr, ETH_ALEN);
1b537565 3398
a8ab1ec0
SH		 3399 /* virtual address for data */
3400 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3401
3402 /* physical address: used for pause frames */
3403 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3404
3405 return 0;
cd28ab6a
SH		 3406}
3407
a052b52f
SH		 3408static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3409{
3410 u32 bit;
3411
3412 bit = ether_crc(ETH_ALEN, addr) & 63;
3413 filter[bit >> 3] |= 1 << (bit & 7);
3414}
3415
cd28ab6a
SH		 3416static void sky2_set_multicast(struct net_device *dev)
3417{
3418 struct sky2_port *sky2 = netdev_priv(dev);
3419 struct sky2_hw *hw = sky2->hw;
3420 unsigned port = sky2->port;
3421 struct dev_mc_list *list = dev->mc_list;
3422 u16 reg;
3423 u8 filter[8];
a052b52f
SH		 3424 int rx_pause;
3425 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3426
a052b52f 3427 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3428 memset(filter, 0, sizeof(filter));
3429
3430 reg = gma_read16(hw, port, GM_RX_CTRL);
3431 reg |= GM_RXCR_UCF_ENA;
3432
d571b694 3433 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3434 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3435 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3436 memset(filter, 0xff, sizeof(filter));
a052b52f 3437 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3438 reg &= ~GM_RXCR_MCF_ENA;
3439 else {
3440 int i;
3441 reg |= GM_RXCR_MCF_ENA;
3442
a052b52f
SH		 3443 if (rx_pause)
3444 sky2_add_filter(filter, pause_mc_addr);
3445
3446 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3447 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3448 }
3449
cd28ab6a 3450 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3451 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3452 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3453 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3454 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3455 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3456 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3457 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3458
3459 gma_write16(hw, port, GM_RX_CTRL, reg);
3460}
3461
3462/* Can have one global because blinking is controlled by
3463 * ethtool and that is always under RTNL mutex
3464 */
a84d0a3d 3465static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3466{
a84d0a3d
SH		 3467 struct sky2_hw *hw = sky2->hw;
3468 unsigned port = sky2->port;
793b883e 3469
a84d0a3d
SH		 3470 spin_lock_bh(&sky2->phy_lock);
3471 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3472 hw->chip_id == CHIP_ID_YUKON_EX ||
3473 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3474 u16 pg;
793b883e
SH		 3475 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3476 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3477
a84d0a3d
SH		 3478 switch (mode) {
3479 case MO_LED_OFF:
3480 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3481 PHY_M_LEDC_LOS_CTRL(8) |
3482 PHY_M_LEDC_INIT_CTRL(8) |
3483 PHY_M_LEDC_STA1_CTRL(8) |
3484 PHY_M_LEDC_STA0_CTRL(8));
3485 break;
3486 case MO_LED_ON:
3487 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3488 PHY_M_LEDC_LOS_CTRL(9) |
3489 PHY_M_LEDC_INIT_CTRL(9) |
3490 PHY_M_LEDC_STA1_CTRL(9) |
3491 PHY_M_LEDC_STA0_CTRL(9));
3492 break;
3493 case MO_LED_BLINK:
3494 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3495 PHY_M_LEDC_LOS_CTRL(0xa) |
3496 PHY_M_LEDC_INIT_CTRL(0xa) |
3497 PHY_M_LEDC_STA1_CTRL(0xa) |
3498 PHY_M_LEDC_STA0_CTRL(0xa));
3499 break;
3500 case MO_LED_NORM:
3501 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3502 PHY_M_LEDC_LOS_CTRL(1) |
3503 PHY_M_LEDC_INIT_CTRL(8) |
3504 PHY_M_LEDC_STA1_CTRL(7) |
3505 PHY_M_LEDC_STA0_CTRL(7));
3506 }
793b883e 3507
a84d0a3d
SH		 3508 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3509 } else
7d2e3cb7 3510 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3511 PHY_M_LED_MO_DUP(mode) |
3512 PHY_M_LED_MO_10(mode) |
3513 PHY_M_LED_MO_100(mode) |
3514 PHY_M_LED_MO_1000(mode) |
3515 PHY_M_LED_MO_RX(mode) |
3516 PHY_M_LED_MO_TX(mode));
3517
3518 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3519}
3520
3521/* blink LED's for finding board */
3522static int sky2_phys_id(struct net_device *dev, u32 data)
3523{
3524 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3525 unsigned int i;
cd28ab6a 3526
a84d0a3d
SH		 3527 if (data == 0)
3528 data = UINT_MAX;
cd28ab6a 3529
a84d0a3d
SH		 3530 for (i = 0; i < data; i++) {
3531 sky2_led(sky2, MO_LED_ON);
3532 if (msleep_interruptible(500))
3533 break;
3534 sky2_led(sky2, MO_LED_OFF);
3535 if (msleep_interruptible(500))
3536 break;
793b883e 3537 }
a84d0a3d 3538 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3539
3540 return 0;
3541}
3542
3543static void sky2_get_pauseparam(struct net_device *dev,
3544 struct ethtool_pauseparam *ecmd)
3545{
3546 struct sky2_port *sky2 = netdev_priv(dev);
3547
16ad91e1
SH		 3548 switch (sky2->flow_mode) {
3549 case FC_NONE:
3550 ecmd->tx_pause = ecmd->rx_pause = 0;
3551 break;
3552 case FC_TX:
3553 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3554 break;
3555 case FC_RX:
3556 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3557 break;
3558 case FC_BOTH:
3559 ecmd->tx_pause = ecmd->rx_pause = 1;
3560 }
3561
cd28ab6a
SH		 3562 ecmd->autoneg = sky2->autoneg;
3563}
3564
3565static int sky2_set_pauseparam(struct net_device *dev,
3566 struct ethtool_pauseparam *ecmd)
3567{
3568 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3569
3570 sky2->autoneg = ecmd->autoneg;
16ad91e1 3571 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3572
16ad91e1
SH		 3573 if (netif_running(dev))
3574 sky2_phy_reinit(sky2);
cd28ab6a 3575
2eaba1a2 3576 return 0;
cd28ab6a
SH		 3577}
3578
fb17358f
SH		 3579static int sky2_get_coalesce(struct net_device *dev,
3580 struct ethtool_coalesce *ecmd)
3581{
3582 struct sky2_port *sky2 = netdev_priv(dev);
3583 struct sky2_hw *hw = sky2->hw;
3584
3585 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3586 ecmd->tx_coalesce_usecs = 0;
3587 else {
3588 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3589 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3590 }
3591 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3592
3593 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3594 ecmd->rx_coalesce_usecs = 0;
3595 else {
3596 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3597 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3598 }
3599 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3600
3601 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3602 ecmd->rx_coalesce_usecs_irq = 0;
3603 else {
3604 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3605 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3606 }
3607
3608 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3609
3610 return 0;
3611}
3612
3613/* Note: this affect both ports */
3614static int sky2_set_coalesce(struct net_device *dev,
3615 struct ethtool_coalesce *ecmd)
3616{
3617 struct sky2_port *sky2 = netdev_priv(dev);
3618 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3619 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3620
77b3d6a2
SH		 3621 if (ecmd->tx_coalesce_usecs > tmax ||
3622 ecmd->rx_coalesce_usecs > tmax ||
3623 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3624 return -EINVAL;
3625
ff81fbbe 3626 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3627 return -EINVAL;
ff81fbbe 3628 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3629 return -EINVAL;
ff81fbbe 3630 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3631 return -EINVAL;
3632
3633 if (ecmd->tx_coalesce_usecs == 0)
3634 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3635 else {
3636 sky2_write32(hw, STAT_TX_TIMER_INI,
3637 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3638 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3639 }
3640 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3641
3642 if (ecmd->rx_coalesce_usecs == 0)
3643 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3644 else {
3645 sky2_write32(hw, STAT_LEV_TIMER_INI,
3646 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3647 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3648 }
3649 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3650
3651 if (ecmd->rx_coalesce_usecs_irq == 0)
3652 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3653 else {
d28d4870 3654 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3655 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3656 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3657 }
3658 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3659 return 0;
3660}
3661
793b883e
SH		 3662static void sky2_get_ringparam(struct net_device *dev,
3663 struct ethtool_ringparam *ering)
3664{
3665 struct sky2_port *sky2 = netdev_priv(dev);
3666
3667 ering->rx_max_pending = RX_MAX_PENDING;
3668 ering->rx_mini_max_pending = 0;
3669 ering->rx_jumbo_max_pending = 0;
3670 ering->tx_max_pending = TX_RING_SIZE - 1;
3671
3672 ering->rx_pending = sky2->rx_pending;
3673 ering->rx_mini_pending = 0;
3674 ering->rx_jumbo_pending = 0;
3675 ering->tx_pending = sky2->tx_pending;
3676}
3677
3678static int sky2_set_ringparam(struct net_device *dev,
3679 struct ethtool_ringparam *ering)
3680{
3681 struct sky2_port *sky2 = netdev_priv(dev);
3682 int err = 0;
3683
3684 if (ering->rx_pending > RX_MAX_PENDING ||
3685 ering->rx_pending < 8 ||
3686 ering->tx_pending < MAX_SKB_TX_LE ||
3687 ering->tx_pending > TX_RING_SIZE - 1)
3688 return -EINVAL;
3689
3690 if (netif_running(dev))
3691 sky2_down(dev);
3692
3693 sky2->rx_pending = ering->rx_pending;
3694 sky2->tx_pending = ering->tx_pending;
3695
1b537565 3696 if (netif_running(dev)) {
793b883e 3697 err = sky2_up(dev);
1b537565
SH		 3698 if (err)
3699 dev_close(dev);
3700 }
793b883e
SH		 3701
3702 return err;
3703}
3704
793b883e
SH		 3705static int sky2_get_regs_len(struct net_device *dev)
3706{
6e4cbb34 3707 return 0x4000;
793b883e
SH		 3708}
3709
3710/*
3711 * Returns copy of control register region
3ead5db7 3712 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3713 */
3714static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3715 void *p)
3716{
3717 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3718 const void __iomem *io = sky2->hw->regs;
295b54c4 3719 unsigned int b;
793b883e
SH		 3720
3721 regs->version = 1;
793b883e 3722
295b54c4
SH		 3723 for (b = 0; b < 128; b++) {
3724 /* This complicated switch statement is to make sure and
3725 * only access regions that are unreserved.
3726 * Some blocks are only valid on dual port cards.
3727 * and block 3 has some special diagnostic registers that
3728 * are poison.
3729 */
3730 switch (b) {
3731 case 3:
3732 /* skip diagnostic ram region */
3733 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3734 break;
3ead5db7 3735
295b54c4
SH		 3736 /* dual port cards only */
3737 case 5: /* Tx Arbiter 2 */
3738 case 9: /* RX2 */
3739 case 14 ... 15: /* TX2 */
3740 case 17: case 19: /* Ram Buffer 2 */
3741 case 22 ... 23: /* Tx Ram Buffer 2 */
3742 case 25: /* Rx MAC Fifo 1 */
3743 case 27: /* Tx MAC Fifo 2 */
3744 case 31: /* GPHY 2 */
3745 case 40 ... 47: /* Pattern Ram 2 */
3746 case 52: case 54: /* TCP Segmentation 2 */
3747 case 112 ... 116: /* GMAC 2 */
3748 if (sky2->hw->ports == 1)
3749 goto reserved;
3750 /* fall through */
3751 case 0: /* Control */
3752 case 2: /* Mac address */
3753 case 4: /* Tx Arbiter 1 */
3754 case 7: /* PCI express reg */
3755 case 8: /* RX1 */
3756 case 12 ... 13: /* TX1 */
3757 case 16: case 18:/* Rx Ram Buffer 1 */
3758 case 20 ... 21: /* Tx Ram Buffer 1 */
3759 case 24: /* Rx MAC Fifo 1 */
3760 case 26: /* Tx MAC Fifo 1 */
3761 case 28 ... 29: /* Descriptor and status unit */
3762 case 30: /* GPHY 1*/
3763 case 32 ... 39: /* Pattern Ram 1 */
3764 case 48: case 50: /* TCP Segmentation 1 */
3765 case 56 ... 60: /* PCI space */
3766 case 80 ... 84: /* GMAC 1 */
3767 memcpy_fromio(p, io, 128);
3768 break;
3769 default:
3770reserved:
3771 memset(p, 0, 128);
3772 }
3ead5db7 3773
295b54c4
SH		 3774 p += 128;
3775 io += 128;
3776 }
793b883e 3777}
cd28ab6a 3778
b628ed98
SH		 3779/* In order to do Jumbo packets on these chips, need to turn off the
3780 * transmit store/forward. Therefore checksum offload won't work.
3781 */
3782static int no_tx_offload(struct net_device *dev)
3783{
3784 const struct sky2_port *sky2 = netdev_priv(dev);
3785 const struct sky2_hw *hw = sky2->hw;
3786
69161611 3787 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3788}
3789
3790static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3791{
3792 if (data && no_tx_offload(dev))
3793 return -EINVAL;
3794
3795 return ethtool_op_set_tx_csum(dev, data);
3796}
3797
3798
3799static int sky2_set_tso(struct net_device *dev, u32 data)
3800{
3801 if (data && no_tx_offload(dev))
3802 return -EINVAL;
3803
3804 return ethtool_op_set_tso(dev, data);
3805}
3806
f4331a6d
SH		 3807static int sky2_get_eeprom_len(struct net_device *dev)
3808{
3809 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3810 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3811 u16 reg2;
3812
b32f40c4 3813 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3814 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3815}
3816
1413235c 3817static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3818{
1413235c 3819 unsigned long start = jiffies;
f4331a6d 3820
1413235c
SH		 3821 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3822 /* Can take up to 10.6 ms for write */
3823 if (time_after(jiffies, start + HZ/4)) {
3824 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3825 return -ETIMEDOUT;
3826 }
3827 mdelay(1);
3828 }
167f53d0 3829
1413235c
SH		 3830 return 0;
3831}
167f53d0 3832
1413235c
SH		 3833static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3834 u16 offset, size_t length)
3835{
3836 int rc = 0;
3837
3838 while (length > 0) {
3839 u32 val;
3840
3841 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3842 rc = sky2_vpd_wait(hw, cap, 0);
3843 if (rc)
3844 break;
3845
3846 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3847
3848 memcpy(data, &val, min(sizeof(val), length));
3849 offset += sizeof(u32);
3850 data += sizeof(u32);
3851 length -= sizeof(u32);
3852 }
3853
3854 return rc;
f4331a6d
SH		 3855}
3856
1413235c
SH		 3857static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3858 u16 offset, unsigned int length)
f4331a6d 3859{
1413235c
SH		 3860 unsigned int i;
3861 int rc = 0;
3862
3863 for (i = 0; i < length; i += sizeof(u32)) {
3864 u32 val = *(u32 *)(data + i);
3865
3866 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3867 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3868
3869 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3870 if (rc)
3871 break;
3872 }
3873 return rc;
f4331a6d
SH		 3874}
3875
3876static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3877 u8 *data)
3878{
3879 struct sky2_port *sky2 = netdev_priv(dev);
3880 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3881
3882 if (!cap)
3883 return -EINVAL;
3884
3885 eeprom->magic = SKY2_EEPROM_MAGIC;
3886
1413235c 3887 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3888}
3889
3890static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3891 u8 *data)
3892{
3893 struct sky2_port *sky2 = netdev_priv(dev);
3894 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3895
3896 if (!cap)
3897 return -EINVAL;
3898
3899 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3900 return -EINVAL;
3901
1413235c
SH		 3902 /* Partial writes not supported */
3903 if ((eeprom->offset & 3) || (eeprom->len & 3))
3904 return -EINVAL;
f4331a6d 3905
1413235c 3906 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3907}
3908
3909
7282d491 3910static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3911 .get_settings = sky2_get_settings,
3912 .set_settings = sky2_set_settings,
3913 .get_drvinfo = sky2_get_drvinfo,
3914 .get_wol = sky2_get_wol,
3915 .set_wol = sky2_set_wol,
3916 .get_msglevel = sky2_get_msglevel,
3917 .set_msglevel = sky2_set_msglevel,
3918 .nway_reset = sky2_nway_reset,
3919 .get_regs_len = sky2_get_regs_len,
3920 .get_regs = sky2_get_regs,
3921 .get_link = ethtool_op_get_link,
3922 .get_eeprom_len = sky2_get_eeprom_len,
3923 .get_eeprom = sky2_get_eeprom,
3924 .set_eeprom = sky2_set_eeprom,
f4331a6d 3925 .set_sg = ethtool_op_set_sg,
f4331a6d 3926 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3927 .set_tso = sky2_set_tso,
3928 .get_rx_csum = sky2_get_rx_csum,
3929 .set_rx_csum = sky2_set_rx_csum,
3930 .get_strings = sky2_get_strings,
3931 .get_coalesce = sky2_get_coalesce,
3932 .set_coalesce = sky2_set_coalesce,
3933 .get_ringparam = sky2_get_ringparam,
3934 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3935 .get_pauseparam = sky2_get_pauseparam,
3936 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3937 .phys_id = sky2_phys_id,
b9f2c044 3938 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3939 .get_ethtool_stats = sky2_get_ethtool_stats,
3940};
3941
3cf26753
SH		 3942#ifdef CONFIG_SKY2_DEBUG
3943
3944static struct dentry *sky2_debug;
3945
e4c2abe2
SH		 3946
3947/*
3948 * Read and parse the first part of Vital Product Data
3949 */
3950#define VPD_SIZE 128
3951#define VPD_MAGIC 0x82
3952
3953static const struct vpd_tag {
3954 char tag[2];
3955 char *label;
3956} vpd_tags[] = {
3957 { "PN", "Part Number" },
3958 { "EC", "Engineering Level" },
3959 { "MN", "Manufacturer" },
3960 { "SN", "Serial Number" },
3961 { "YA", "Asset Tag" },
3962 { "VL", "First Error Log Message" },
3963 { "VF", "Second Error Log Message" },
3964 { "VB", "Boot Agent ROM Configuration" },
3965 { "VE", "EFI UNDI Configuration" },
3966};
3967
3968static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3969{
3970 size_t vpd_size;
3971 loff_t offs;
3972 u8 len;
3973 unsigned char *buf;
3974 u16 reg2;
3975
3976 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3977 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3978
3979 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
3980 buf = kmalloc(vpd_size, GFP_KERNEL);
3981 if (!buf) {
3982 seq_puts(seq, "no memory!\n");
3983 return;
3984 }
3985
3986 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
3987 seq_puts(seq, "VPD read failed\n");
3988 goto out;
3989 }
3990
3991 if (buf[0] != VPD_MAGIC) {
3992 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
3993 goto out;
3994 }
3995 len = buf[1];
3996 if (len == 0 || len > vpd_size - 4) {
3997 seq_printf(seq, "Invalid id length: %d\n", len);
3998 goto out;
3999 }
4000
4001 seq_printf(seq, "%.*s\n", len, buf + 3);
4002 offs = len + 3;
4003
4004 while (offs < vpd_size - 4) {
4005 int i;
4006
4007 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4008 break;
4009 len = buf[offs + 2];
4010 if (offs + len + 3 >= vpd_size)
4011 break;
4012
4013 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4014 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4015 seq_printf(seq, " %s: %.*s\n",
4016 vpd_tags[i].label, len, buf + offs + 3);
4017 break;
4018 }
4019 }
4020 offs += len + 3;
4021 }
4022out:
4023 kfree(buf);
4024}
4025
3cf26753
SH		 4026static int sky2_debug_show(struct seq_file *seq, void *v)
4027{
4028 struct net_device *dev = seq->private;
4029 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4030 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4031 unsigned port = sky2->port;
4032 unsigned idx, last;
4033 int sop;
4034
e4c2abe2 4035 sky2_show_vpd(seq, hw);
3cf26753 4036
e4c2abe2 4037 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4038 sky2_read32(hw, B0_ISRC),
4039 sky2_read32(hw, B0_IMSK),
4040 sky2_read32(hw, B0_Y2_SP_ICR));
4041
e4c2abe2
SH		 4042 if (!netif_running(dev)) {
4043 seq_printf(seq, "network not running\n");
4044 return 0;
4045 }
4046
bea3348e 4047 napi_disable(&hw->napi);
3cf26753
SH		 4048 last = sky2_read16(hw, STAT_PUT_IDX);
4049
4050 if (hw->st_idx == last)
4051 seq_puts(seq, "Status ring (empty)\n");
4052 else {
4053 seq_puts(seq, "Status ring\n");
4054 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4055 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4056 const struct sky2_status_le *le = hw->st_le + idx;
4057 seq_printf(seq, "[%d] %#x %d %#x\n",
4058 idx, le->opcode, le->length, le->status);
4059 }
4060 seq_puts(seq, "\n");
4061 }
4062
4063 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4064 sky2->tx_cons, sky2->tx_prod,
4065 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4066 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4067
4068 /* Dump contents of tx ring */
4069 sop = 1;
4070 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
4071 idx = RING_NEXT(idx, TX_RING_SIZE)) {
4072 const struct sky2_tx_le *le = sky2->tx_le + idx;
4073 u32 a = le32_to_cpu(le->addr);
4074
4075 if (sop)
4076 seq_printf(seq, "%u:", idx);
4077 sop = 0;
4078
4079 switch(le->opcode & ~HW_OWNER) {
4080 case OP_ADDR64:
4081 seq_printf(seq, " %#x:", a);
4082 break;
4083 case OP_LRGLEN:
4084 seq_printf(seq, " mtu=%d", a);
4085 break;
4086 case OP_VLAN:
4087 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4088 break;
4089 case OP_TCPLISW:
4090 seq_printf(seq, " csum=%#x", a);
4091 break;
4092 case OP_LARGESEND:
4093 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4094 break;
4095 case OP_PACKET:
4096 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4097 break;
4098 case OP_BUFFER:
4099 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4100 break;
4101 default:
4102 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4103 a, le16_to_cpu(le->length));
4104 }
4105
4106 if (le->ctrl & EOP) {
4107 seq_putc(seq, '\n');
4108 sop = 1;
4109 }
4110 }
4111
4112 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4113 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4114 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4115 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4116
d1d08d12 4117 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4118 napi_enable(&hw->napi);
3cf26753
SH		 4119 return 0;
4120}
4121
4122static int sky2_debug_open(struct inode *inode, struct file *file)
4123{
4124 return single_open(file, sky2_debug_show, inode->i_private);
4125}
4126
4127static const struct file_operations sky2_debug_fops = {
4128 .owner = THIS_MODULE,
4129 .open = sky2_debug_open,
4130 .read = seq_read,
4131 .llseek = seq_lseek,
4132 .release = single_release,
4133};
4134
4135/*
4136 * Use network device events to create/remove/rename
4137 * debugfs file entries
4138 */
4139static int sky2_device_event(struct notifier_block *unused,
4140 unsigned long event, void *ptr)
4141{
4142 struct net_device *dev = ptr;
5b296bc9 4143 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4144
1436b301 4145 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4146 return NOTIFY_DONE;
3cf26753 4147
5b296bc9
SH		 4148 switch(event) {
4149 case NETDEV_CHANGENAME:
4150 if (sky2->debugfs) {
4151 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4152 sky2_debug, dev->name);
4153 }
4154 break;
3cf26753 4155
5b296bc9
SH		 4156 case NETDEV_GOING_DOWN:
4157 if (sky2->debugfs) {
4158 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4159 dev->name);
4160 debugfs_remove(sky2->debugfs);
4161 sky2->debugfs = NULL;
3cf26753 4162 }
5b296bc9
SH		 4163 break;
4164
4165 case NETDEV_UP:
4166 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4167 sky2_debug, dev,
4168 &sky2_debug_fops);
4169 if (IS_ERR(sky2->debugfs))
4170 sky2->debugfs = NULL;
3cf26753
SH		 4171 }
4172
4173 return NOTIFY_DONE;
4174}
4175
4176static struct notifier_block sky2_notifier = {
4177 .notifier_call = sky2_device_event,
4178};
4179
4180
4181static __init void sky2_debug_init(void)
4182{
4183 struct dentry *ent;
4184
4185 ent = debugfs_create_dir("sky2", NULL);
4186 if (!ent || IS_ERR(ent))
4187 return;
4188
4189 sky2_debug = ent;
4190 register_netdevice_notifier(&sky2_notifier);
4191}
4192
4193static __exit void sky2_debug_cleanup(void)
4194{
4195 if (sky2_debug) {
4196 unregister_netdevice_notifier(&sky2_notifier);
4197 debugfs_remove(sky2_debug);
4198 sky2_debug = NULL;
4199 }
4200}
4201
4202#else
4203#define sky2_debug_init()
4204#define sky2_debug_cleanup()
4205#endif
4206
1436b301
SH		 4207/* Two copies of network device operations to handle special case of
4208 not allowing netpoll on second port */
4209static const struct net_device_ops sky2_netdev_ops[2] = {
4210 {
4211 .ndo_open = sky2_up,
4212 .ndo_stop = sky2_down,
00829823 4213 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4214 .ndo_do_ioctl = sky2_ioctl,
4215 .ndo_validate_addr = eth_validate_addr,
4216 .ndo_set_mac_address = sky2_set_mac_address,
4217 .ndo_set_multicast_list = sky2_set_multicast,
4218 .ndo_change_mtu = sky2_change_mtu,
4219 .ndo_tx_timeout = sky2_tx_timeout,
4220#ifdef SKY2_VLAN_TAG_USED
4221 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4222#endif
4223#ifdef CONFIG_NET_POLL_CONTROLLER
4224 .ndo_poll_controller = sky2_netpoll,
4225#endif
4226 },
4227 {
4228 .ndo_open = sky2_up,
4229 .ndo_stop = sky2_down,
00829823 4230 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4231 .ndo_do_ioctl = sky2_ioctl,
4232 .ndo_validate_addr = eth_validate_addr,
4233 .ndo_set_mac_address = sky2_set_mac_address,
4234 .ndo_set_multicast_list = sky2_set_multicast,
4235 .ndo_change_mtu = sky2_change_mtu,
4236 .ndo_tx_timeout = sky2_tx_timeout,
4237#ifdef SKY2_VLAN_TAG_USED
4238 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4239#endif
4240 },
4241};
3cf26753 4242
cd28ab6a
SH		 4243/* Initialize network device */
4244static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4245 unsigned port,
be63a21c 4246 int highmem, int wol)
cd28ab6a
SH		 4247{
4248 struct sky2_port *sky2;
4249 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4250
4251 if (!dev) {
898eb71c 4252 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4253 return NULL;
4254 }
4255
cd28ab6a 4256 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4257 dev->irq = hw->pdev->irq;
cd28ab6a 4258 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4259 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4260 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4261
4262 sky2 = netdev_priv(dev);
4263 sky2->netdev = dev;
4264 sky2->hw = hw;
4265 sky2->msg_enable = netif_msg_init(debug, default_msg);
4266
cd28ab6a
SH		 4267 /* Auto speed and flow control */
4268 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4269 sky2->flow_mode = FC_BOTH;
4270
cd28ab6a
SH		 4271 sky2->duplex = -1;
4272 sky2->speed = -1;
4273 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4274 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4275 sky2->wol = wol;
75d070c5 4276
e07b1aa8 4277 spin_lock_init(&sky2->phy_lock);
793b883e 4278 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4279 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4280
4281 hw->dev[port] = dev;
4282
4283 sky2->port = port;
4284
4a50a876 4285 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4286 if (highmem)
4287 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4288
d1f13708 4289#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4290 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4291 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4292 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4293 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4294 }
d1f13708
SH		 4295#endif
4296
cd28ab6a 4297 /* read the mac address */
793b883e 4298 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4299 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4300
cd28ab6a
SH		 4301 return dev;
4302}
4303
28bd181a 4304static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4305{
4306 const struct sky2_port *sky2 = netdev_priv(dev);
4307
4308 if (netif_msg_probe(sky2))
e174961c
JB		 4309 printk(KERN_INFO PFX "%s: addr %pM\n",
4310 dev->name, dev->dev_addr);
cd28ab6a
SH		 4311}
4312
fb2690a9 4313/* Handle software interrupt used during MSI test */
7d12e780 4314static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4315{
4316 struct sky2_hw *hw = dev_id;
4317 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4318
4319 if (status == 0)
4320 return IRQ_NONE;
4321
4322 if (status & Y2_IS_IRQ_SW) {
ea76e635 4323 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4324 wake_up(&hw->msi_wait);
4325 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4326 }
4327 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4328
4329 return IRQ_HANDLED;
4330}
4331
4332/* Test interrupt path by forcing a a software IRQ */
4333static int __devinit sky2_test_msi(struct sky2_hw *hw)
4334{
4335 struct pci_dev *pdev = hw->pdev;
4336 int err;
4337
bb507fe1
SH		 4338 init_waitqueue_head (&hw->msi_wait);
4339
fb2690a9
SH		 4340 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4341
b0a20ded 4342 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4343 if (err) {
b02a9258 4344 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4345 return err;
4346 }
4347
fb2690a9 4348 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4349 sky2_read8(hw, B0_CTST);
fb2690a9 4350
ea76e635 4351 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4352
ea76e635 4353 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4354 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4355 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4356 "switching to INTx mode.\n");
fb2690a9
SH		 4357
4358 err = -EOPNOTSUPP;
4359 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4360 }
4361
4362 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4363 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4364
4365 free_irq(pdev->irq, hw);
4366
4367 return err;
4368}
4369
c7127a34
SH		 4370/* This driver supports yukon2 chipset only */
4371static const char *sky2_name(u8 chipid, char *buf, int sz)
4372{
4373 const char *name[] = {
4374 "XL", /* 0xb3 */
4375 "EC Ultra", /* 0xb4 */
4376 "Extreme", /* 0xb5 */
4377 "EC", /* 0xb6 */
4378 "FE", /* 0xb7 */
4379 "FE+", /* 0xb8 */
4380 "Supreme", /* 0xb9 */
0ce8b98d 4381 "UL 2", /* 0xba */
c7127a34
SH		 4382 };
4383
0ce8b98d 4384 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH		 4385 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4386 else
4387 snprintf(buf, sz, "(chip %#x)", chipid);
4388 return buf;
4389}
4390
cd28ab6a
SH		 4391static int __devinit sky2_probe(struct pci_dev *pdev,
4392 const struct pci_device_id *ent)
4393{
7f60c64b 4394 struct net_device *dev;
cd28ab6a 4395 struct sky2_hw *hw;
be63a21c 4396 int err, using_dac = 0, wol_default;
3834507d 4397 u32 reg;
c7127a34 4398 char buf1[16];
cd28ab6a 4399
793b883e
SH		 4400 err = pci_enable_device(pdev);
4401 if (err) {
b02a9258 4402 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4403 goto err_out;
4404 }
4405
6cc90a5a
SH		 4406 /* Get configuration information
4407 * Note: only regular PCI config access once to test for HW issues
4408 * other PCI access through shared memory for speed and to
4409 * avoid MMCONFIG problems.
4410 */
4411 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4412 if (err) {
4413 dev_err(&pdev->dev, "PCI read config failed\n");
4414 goto err_out;
4415 }
4416
4417 if (~reg == 0) {
4418 dev_err(&pdev->dev, "PCI configuration read error\n");
4419 goto err_out;
4420 }
4421
793b883e
SH		 4422 err = pci_request_regions(pdev, DRV_NAME);
4423 if (err) {
b02a9258 4424 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4425 goto err_out_disable;
cd28ab6a
SH		 4426 }
4427
4428 pci_set_master(pdev);
4429
d1f3d4dd 4430 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4431 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4432 using_dac = 1;
6a35528a 4433 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4434 if (err < 0) {
b02a9258
SH		 4435 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4436 "for consistent allocations\n");
d1f3d4dd
SH		 4437 goto err_out_free_regions;
4438 }
d1f3d4dd 4439 } else {
284901a9 4440 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4441 if (err) {
b02a9258 4442 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4443 goto err_out_free_regions;
4444 }
4445 }
d1f3d4dd 4446
3834507d
SH		 4447
4448#ifdef __BIG_ENDIAN
4449 /* The sk98lin vendor driver uses hardware byte swapping but
4450 * this driver uses software swapping.
4451 */
4452 reg &= ~PCI_REV_DESC;
4453 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4454 if (err) {
4455 dev_err(&pdev->dev, "PCI write config failed\n");
4456 goto err_out_free_regions;
4457 }
4458#endif
4459
9d731d77 4460 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4461
cd28ab6a 4462 err = -ENOMEM;
6aad85d6 4463 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4464 if (!hw) {
b02a9258 4465 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4466 goto err_out_free_regions;
4467 }
4468
cd28ab6a 4469 hw->pdev = pdev;
cd28ab6a
SH		 4470
4471 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4472 if (!hw->regs) {
b02a9258 4473 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4474 goto err_out_free_hw;
4475 }
4476
08c06d8a 4477 /* ring for status responses */
167f53d0 4478 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4479 if (!hw->st_le)
4480 goto err_out_iounmap;
4481
e3173832 4482 err = sky2_init(hw);
cd28ab6a 4483 if (err)
793b883e 4484 goto err_out_iounmap;
cd28ab6a 4485
c844d483
SH		 4486 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4487 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4488
e3173832
SH		 4489 sky2_reset(hw);
4490
be63a21c 4491 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4492 if (!dev) {
4493 err = -ENOMEM;
cd28ab6a 4494 goto err_out_free_pci;
7f60c64b 4495 }
cd28ab6a 4496
9fa1b1f3
SH		 4497 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4498 err = sky2_test_msi(hw);
4499 if (err == -EOPNOTSUPP)
4500 pci_disable_msi(pdev);
4501 else if (err)
4502 goto err_out_free_netdev;
4503 }
4504
793b883e
SH		 4505 err = register_netdev(dev);
4506 if (err) {
b02a9258 4507 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4508 goto err_out_free_netdev;
4509 }
4510
6de16237
SH		 4511 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4512
ea76e635
SH		 4513 err = request_irq(pdev->irq, sky2_intr,
4514 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4515 dev->name, hw);
9fa1b1f3 4516 if (err) {
b02a9258 4517 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4518 goto err_out_unregister;
4519 }
4520 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4521 napi_enable(&hw->napi);
9fa1b1f3 4522
cd28ab6a
SH		 4523 sky2_show_addr(dev);
4524
7f60c64b 4525 if (hw->ports > 1) {
4526 struct net_device *dev1;
4527
be63a21c 4528 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4529 if (!dev1)
4530 dev_warn(&pdev->dev, "allocation for second device failed\n");
4531 else if ((err = register_netdev(dev1))) {
4532 dev_warn(&pdev->dev,
4533 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4534 hw->dev[1] = NULL;
4535 free_netdev(dev1);
b02a9258
SH		 4536 } else
4537 sky2_show_addr(dev1);
cd28ab6a
SH		 4538 }
4539
32c2c300 4540 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4541 INIT_WORK(&hw->restart_work, sky2_restart);
4542
793b883e
SH		 4543 pci_set_drvdata(pdev, hw);
4544
cd28ab6a
SH		 4545 return 0;
4546
793b883e 4547err_out_unregister:
ea76e635 4548 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4549 pci_disable_msi(pdev);
793b883e 4550 unregister_netdev(dev);
cd28ab6a
SH		 4551err_out_free_netdev:
4552 free_netdev(dev);
cd28ab6a 4553err_out_free_pci:
793b883e 4554 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4555 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4556err_out_iounmap:
4557 iounmap(hw->regs);
4558err_out_free_hw:
4559 kfree(hw);
4560err_out_free_regions:
4561 pci_release_regions(pdev);
44a1d2e5 4562err_out_disable:
cd28ab6a 4563 pci_disable_device(pdev);
cd28ab6a 4564err_out:
549a68c3 4565 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4566 return err;
4567}
4568
4569static void __devexit sky2_remove(struct pci_dev *pdev)
4570{
793b883e 4571 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4572 int i;
cd28ab6a 4573
793b883e 4574 if (!hw)
cd28ab6a
SH		 4575 return;
4576
32c2c300 4577 del_timer_sync(&hw->watchdog_timer);
6de16237 4578 cancel_work_sync(&hw->restart_work);
d27ed387 4579
b877fe28 4580 for (i = hw->ports-1; i >= 0; --i)
6de16237 4581 unregister_netdev(hw->dev[i]);
81906791 4582
d27ed387 4583 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4584
ae306cca
SH		 4585 sky2_power_aux(hw);
4586
cd28ab6a 4587 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4588 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4589 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4590
4591 free_irq(pdev->irq, hw);
ea76e635 4592 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4593 pci_disable_msi(pdev);
793b883e 4594 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4595 pci_release_regions(pdev);
4596 pci_disable_device(pdev);
793b883e 4597
b877fe28 4598 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4599 free_netdev(hw->dev[i]);
4600
cd28ab6a
SH		 4601 iounmap(hw->regs);
4602 kfree(hw);
5afa0a9c 4603
cd28ab6a
SH		 4604 pci_set_drvdata(pdev, NULL);
4605}
4606
4607#ifdef CONFIG_PM
4608static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4609{
793b883e 4610 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4611 int i, wol = 0;
cd28ab6a 4612
549a68c3
SH		 4613 if (!hw)
4614 return 0;
4615
063a0b38
SH		 4616 del_timer_sync(&hw->watchdog_timer);
4617 cancel_work_sync(&hw->restart_work);
4618
f05267e7 4619 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4620 struct net_device *dev = hw->dev[i];
e3173832 4621 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4622
063a0b38 4623 netif_device_detach(dev);
e3173832 4624 if (netif_running(dev))
5afa0a9c 4625 sky2_down(dev);
e3173832
SH		 4626
4627 if (sky2->wol)
4628 sky2_wol_init(sky2);
4629
4630 wol |= sky2->wol;
cd28ab6a
SH		 4631 }
4632
8ab8fca2 4633 sky2_write32(hw, B0_IMSK, 0);
6de16237 4634 napi_disable(&hw->napi);
ae306cca 4635 sky2_power_aux(hw);
e3173832 4636
d374c1c1 4637 pci_save_state(pdev);
e3173832 4638 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4639 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4640
2ccc99b7 4641 return 0;
cd28ab6a
SH		 4642}
4643
4644static int sky2_resume(struct pci_dev *pdev)
4645{
793b883e 4646 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4647 int i, err;
cd28ab6a 4648
549a68c3
SH		 4649 if (!hw)
4650 return 0;
4651
f71eb1a2
SH		 4652 err = pci_set_power_state(pdev, PCI_D0);
4653 if (err)
4654 goto out;
ae306cca
SH		 4655
4656 err = pci_restore_state(pdev);
4657 if (err)
4658 goto out;
4659
cd28ab6a 4660 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4661
4662 /* Re-enable all clocks */
05745c4a
SH		 4663 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4664 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4665 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4666 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4667
e3173832 4668 sky2_reset(hw);
8ab8fca2 4669 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4670 napi_enable(&hw->napi);
8ab8fca2 4671
f05267e7 4672 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4673 struct net_device *dev = hw->dev[i];
063a0b38
SH		 4674
4675 netif_device_attach(dev);
6a5706b9 4676 if (netif_running(dev)) {
08c06d8a
SH		 4677 err = sky2_up(dev);
4678 if (err) {
4679 printk(KERN_ERR PFX "%s: could not up: %d\n",
4680 dev->name, err);
68c28898 4681 rtnl_lock();
08c06d8a 4682 dev_close(dev);
68c28898 4683 rtnl_unlock();
eb35cf60 4684 goto out;
5afa0a9c 4685 }
cd28ab6a
SH		 4686 }
4687 }
eb35cf60 4688
ae306cca 4689 return 0;
08c06d8a 4690out:
b02a9258 4691 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4692 pci_disable_device(pdev);
08c06d8a 4693 return err;
cd28ab6a
SH		 4694}
4695#endif
4696
e3173832
SH		 4697static void sky2_shutdown(struct pci_dev *pdev)
4698{
4699 struct sky2_hw *hw = pci_get_drvdata(pdev);
4700 int i, wol = 0;
4701
549a68c3
SH		 4702 if (!hw)
4703 return;
4704
5c0d6b34 4705 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4706
4707 for (i = 0; i < hw->ports; i++) {
4708 struct net_device *dev = hw->dev[i];
4709 struct sky2_port *sky2 = netdev_priv(dev);
4710
4711 if (sky2->wol) {
4712 wol = 1;
4713 sky2_wol_init(sky2);
4714 }
4715 }
4716
4717 if (wol)
4718 sky2_power_aux(hw);
4719
4720 pci_enable_wake(pdev, PCI_D3hot, wol);
4721 pci_enable_wake(pdev, PCI_D3cold, wol);
4722
4723 pci_disable_device(pdev);
f71eb1a2 4724 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4725}
4726
cd28ab6a 4727static struct pci_driver sky2_driver = {
793b883e
SH		 4728 .name = DRV_NAME,
4729 .id_table = sky2_id_table,
4730 .probe = sky2_probe,
4731 .remove = __devexit_p(sky2_remove),
cd28ab6a 4732#ifdef CONFIG_PM
793b883e
SH		 4733 .suspend = sky2_suspend,
4734 .resume = sky2_resume,
cd28ab6a 4735#endif
e3173832 4736 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4737};
4738
4739static int __init sky2_init_module(void)
4740{
c844d483
SH		 4741 pr_info(PFX "driver version " DRV_VERSION "\n");
4742
3cf26753 4743 sky2_debug_init();
50241c4c 4744 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4745}
4746
4747static void __exit sky2_cleanup_module(void)
4748{
4749 pci_unregister_driver(&sky2_driver);
3cf26753 4750 sky2_debug_cleanup();
cd28ab6a
SH		 4751}
4752
4753module_init(sky2_init_module);
4754module_exit(sky2_cleanup_module);
4755
4756MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4757MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4758MODULE_LICENSE("GPL");
5f4f9dc1 4759MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree