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sky2: turn carrier off when down
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
ef743d33 41#include <linux/mii.h>
cd28ab6a
SH		 42
43#include <asm/irq.h>
44
d1f13708
SH		 45#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46#define SKY2_VLAN_TAG_USED 1
47#endif
48
cd28ab6a
SH		 49#include "sky2.h"
50
51#define DRV_NAME "sky2"
62ba7e6c 52#define DRV_VERSION "1.13"
cd28ab6a
SH		 53#define PFX DRV_NAME " "
54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
14d0263f 58 * similar to Tigon3.
cd28ab6a
SH		 59 */
60
14d0263f 61#define RX_LE_SIZE 1024
cd28ab6a 62#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 63#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 64#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 65#define RX_SKB_ALIGN 8
22e11703 66#define RX_BUF_WRITE 16
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
cb5d9547
SH		 79#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80
cd28ab6a 81static const u32 default_msg =
793b883e
SH		 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 85
793b883e 86static int debug = -1; /* defaults above */
cd28ab6a
SH		 87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
14d0263f 90static int copybreak __read_mostly = 128;
bdb5c58e
SH		 91module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
fb2690a9
SH		 94static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
e561a83b 98static int idle_timeout = 0;
01bd7564 99module_param(idle_timeout, int, 0);
e561a83b 100MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 133 { 0 }
134};
793b883e 135
cd28ab6a
SH		 136MODULE_DEVICE_TABLE(pci, sky2_id_table);
137
138/* Avoid conditionals by using array */
139static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
140static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 141static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 142
92f965e8
SH		 143/* This driver supports yukon2 chipset only */
144static const char *yukon2_name[] = {
145 "XL", /* 0xb3 */
146 "EC Ultra", /* 0xb4 */
93745494 147 "Extreme", /* 0xb5 */
92f965e8
SH		 148 "EC", /* 0xb6 */
149 "FE", /* 0xb7 */
793b883e
SH		 150};
151
793b883e 152/* Access to external PHY */
ef743d33 153static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 154{
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 162 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 163 return 0;
793b883e 164 udelay(1);
cd28ab6a 165 }
ef743d33 166
793b883e 167 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 168 return -ETIMEDOUT;
cd28ab6a
SH		 169}
170
ef743d33 171static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 172{
173 int i;
174
793b883e 175 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 176 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
177
178 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 179 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
180 *val = gma_read16(hw, port, GM_SMI_DATA);
181 return 0;
182 }
183
793b883e 184 udelay(1);
cd28ab6a
SH		 185 }
186
ef743d33
SH		 187 return -ETIMEDOUT;
188}
189
190static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
191{
192 u16 v;
193
194 if (__gm_phy_read(hw, port, reg, &v) != 0)
195 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
196 return v;
cd28ab6a
SH		 197}
198
5afa0a9c 199
ae306cca
SH		 200static void sky2_power_on(struct sky2_hw *hw)
201{
202 /* switch power to VCC (WA for VAUX problem) */
203 sky2_write8(hw, B0_POWER_CTRL,
204 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 205
ae306cca
SH		 206 /* disable Core Clock Division, */
207 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 208
ae306cca
SH		 209 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
210 /* enable bits are inverted */
211 sky2_write8(hw, B2_Y2_CLK_GATE,
212 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
213 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
214 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
215 else
216 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 217
93745494 218 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
ae306cca 219 u32 reg1;
5afa0a9c 220
ae306cca
SH		 221 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
222 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
223 reg1 &= P_ASPM_CONTROL_MSK;
224 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
225 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
5afa0a9c 226 }
ae306cca 227}
5afa0a9c 228
ae306cca
SH		 229static void sky2_power_aux(struct sky2_hw *hw)
230{
231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
232 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
233 else
234 /* enable bits are inverted */
235 sky2_write8(hw, B2_Y2_CLK_GATE,
236 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
237 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
238 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
239
240 /* switch power to VAUX */
241 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
242 sky2_write8(hw, B0_POWER_CTRL,
243 (PC_VAUX_ENA | PC_VCC_ENA |
244 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 245}
246
d3bcfbeb 247static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 248{
249 u16 reg;
250
251 /* disable all GMAC IRQ's */
252 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
253 /* disable PHY IRQs */
254 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 255
cd28ab6a
SH		 256 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
257 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
258 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
259 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
260
261 reg = gma_read16(hw, port, GM_RX_CTRL);
262 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
263 gma_write16(hw, port, GM_RX_CTRL, reg);
264}
265
16ad91e1
SH		 266/* flow control to advertise bits */
267static const u16 copper_fc_adv[] = {
268 [FC_NONE] = 0,
269 [FC_TX] = PHY_M_AN_ASP,
270 [FC_RX] = PHY_M_AN_PC,
271 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
272};
273
274/* flow control to advertise bits when using 1000BaseX */
275static const u16 fiber_fc_adv[] = {
276 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
277 [FC_TX] = PHY_M_P_ASYM_MD_X,
278 [FC_RX] = PHY_M_P_SYM_MD_X,
279 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
280};
281
282/* flow control to GMA disable bits */
283static const u16 gm_fc_disable[] = {
284 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
285 [FC_TX] = GM_GPCR_FC_RX_DIS,
286 [FC_RX] = GM_GPCR_FC_TX_DIS,
287 [FC_BOTH] = 0,
288};
289
290
cd28ab6a
SH		 291static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
292{
293 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 294 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 295
93745494
SH		 296 if (sky2->autoneg == AUTONEG_ENABLE
297 && !(hw->chip_id == CHIP_ID_YUKON_XL
298 || hw->chip_id == CHIP_ID_YUKON_EC_U
299 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 300 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
301
302 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 303 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 304 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
305
306 if (hw->chip_id == CHIP_ID_YUKON_EC)
307 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
308 else
309 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
310
311 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
312 }
313
314 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 315 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 316 if (hw->chip_id == CHIP_ID_YUKON_FE) {
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
319 } else {
320 /* disable energy detect */
321 ctrl &= ~PHY_M_PC_EN_DET_MSK;
322
323 /* enable automatic crossover */
324 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
325
93745494
SH		 326 if (sky2->autoneg == AUTONEG_ENABLE
327 && (hw->chip_id == CHIP_ID_YUKON_XL
328 || hw->chip_id == CHIP_ID_YUKON_EC_U
329 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 330 ctrl &= ~PHY_M_PC_DSC_MSK;
331 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
332 }
333 }
cd28ab6a
SH		 334 } else {
335 /* workaround for deviation #4.88 (CRC errors) */
336 /* disable Automatic Crossover */
337
338 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 339 }
cd28ab6a 340
b89165f2
SH		 341 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
342
343 /* special setup for PHY 88E1112 Fiber */
344 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
345 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 346
b89165f2
SH		 347 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
349 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
350 ctrl &= ~PHY_M_MAC_MD_MSK;
351 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
352 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
353
354 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 355 /* select page 1 to access Fiber registers */
356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 357
358 /* for SFP-module set SIGDET polarity to low */
359 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
360 ctrl |= PHY_M_FIB_SIGD_POL;
361 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 362 }
b89165f2
SH		 363
364 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 365 }
366
7800fddc 367 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 368 ct1000 = 0;
369 adv = PHY_AN_CSMA;
2eaba1a2 370 reg = 0;
cd28ab6a
SH		 371
372 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 373 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 374 if (sky2->advertising & ADVERTISED_1000baseT_Full)
375 ct1000 |= PHY_M_1000C_AFD;
376 if (sky2->advertising & ADVERTISED_1000baseT_Half)
377 ct1000 |= PHY_M_1000C_AHD;
378 if (sky2->advertising & ADVERTISED_100baseT_Full)
379 adv |= PHY_M_AN_100_FD;
380 if (sky2->advertising & ADVERTISED_100baseT_Half)
381 adv |= PHY_M_AN_100_HD;
382 if (sky2->advertising & ADVERTISED_10baseT_Full)
383 adv |= PHY_M_AN_10_FD;
384 if (sky2->advertising & ADVERTISED_10baseT_Half)
385 adv |= PHY_M_AN_10_HD;
709c6e7b 386
16ad91e1 387 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 388 } else { /* special defines for FIBER (88E1040S only) */
389 if (sky2->advertising & ADVERTISED_1000baseT_Full)
390 adv |= PHY_M_AN_1000X_AFD;
391 if (sky2->advertising & ADVERTISED_1000baseT_Half)
392 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 393
16ad91e1 394 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 395 }
cd28ab6a
SH		 396
397 /* Restart Auto-negotiation */
398 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
399 } else {
400 /* forced speed/duplex settings */
401 ct1000 = PHY_M_1000C_MSE;
402
2eaba1a2
SH		 403 /* Disable auto update for duplex flow control and speed */
404 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 405
406 switch (sky2->speed) {
407 case SPEED_1000:
408 ctrl |= PHY_CT_SP1000;
2eaba1a2 409 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 410 break;
411 case SPEED_100:
412 ctrl |= PHY_CT_SP100;
2eaba1a2 413 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 414 break;
415 }
416
2eaba1a2
SH		 417 if (sky2->duplex == DUPLEX_FULL) {
418 reg |= GM_GPCR_DUP_FULL;
419 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 420 } else if (sky2->speed < SPEED_1000)
421 sky2->flow_mode = FC_NONE;
2eaba1a2 422
2eaba1a2 423
16ad91e1 424 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 425
426 /* Forward pause packets to GMAC? */
16ad91e1 427 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 428 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
429 else
430 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 431 }
432
2eaba1a2
SH		 433 gma_write16(hw, port, GM_GP_CTRL, reg);
434
cd28ab6a
SH		 435 if (hw->chip_id != CHIP_ID_YUKON_FE)
436 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
437
438 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
439 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
440
441 /* Setup Phy LED's */
442 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
443 ledover = 0;
444
445 switch (hw->chip_id) {
446 case CHIP_ID_YUKON_FE:
447 /* on 88E3082 these bits are at 11..9 (shifted left) */
448 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
449
450 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
451
452 /* delete ACT LED control bits */
453 ctrl &= ~PHY_M_FELP_LED1_MSK;
454 /* change ACT LED control to blink mode */
455 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
456 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
457 break;
458
459 case CHIP_ID_YUKON_XL:
793b883e 460 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 461
462 /* select page 3 to access LED control register */
463 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
464
465 /* set LED Function Control register */
ed6d32c7
SH		 466 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
467 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
468 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
469 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
470 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 471
472 /* set Polarity Control register */
473 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 474 (PHY_M_POLC_LS1_P_MIX(4) |
475 PHY_M_POLC_IS0_P_MIX(4) |
476 PHY_M_POLC_LOS_CTRL(2) |
477 PHY_M_POLC_INIT_CTRL(2) |
478 PHY_M_POLC_STA1_CTRL(2) |
479 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 480
481 /* restore page register */
793b883e 482 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 483 break;
93745494 484
ed6d32c7 485 case CHIP_ID_YUKON_EC_U:
93745494 486 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 487 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
488
489 /* select page 3 to access LED control register */
490 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
491
492 /* set LED Function Control register */
493 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
494 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
495 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
496 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
497 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
498
499 /* set Blink Rate in LED Timer Control Register */
500 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
501 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
502 /* restore page register */
503 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
504 break;
cd28ab6a
SH		 505
506 default:
507 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
508 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
509 /* turn off the Rx LED (LED_RX) */
0efdf262 510 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 511 }
512
ed6d32c7 513 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 514 /* apply fixes in PHY AFE */
ed6d32c7
SH		 515 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
516 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
517
977bdf06 518 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 519 gm_phy_write(hw, port, 0x18, 0xaa99);
520 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 521
977bdf06 522 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 523 gm_phy_write(hw, port, 0x18, 0xa204);
524 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 525
526 /* set page register to 0 */
ed6d32c7 527 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
93745494 528 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 529 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 530
977bdf06
SH		 531 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
532 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 533 ledover |= PHY_M_LED_MO_100;
977bdf06 534 }
cd28ab6a 535
977bdf06
SH		 536 if (ledover)
537 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
538
539 }
2eaba1a2 540
d571b694 541 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 542 if (sky2->autoneg == AUTONEG_ENABLE)
543 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
544 else
545 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
546}
547
d3bcfbeb
SH		 548static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
549{
550 u32 reg1;
551 static const u32 phy_power[]
552 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
553
554 /* looks like this XL is back asswards .. */
555 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
556 onoff = !onoff;
557
aed2cec4 558 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 559 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 560 if (onoff)
561 /* Turn off phy power saving */
562 reg1 &= ~phy_power[port];
563 else
564 reg1 |= phy_power[port];
565
566 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 567 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 568 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 569 udelay(100);
570}
571
1b537565
SH		 572/* Force a renegotiation */
573static void sky2_phy_reinit(struct sky2_port *sky2)
574{
e07b1aa8 575 spin_lock_bh(&sky2->phy_lock);
1b537565 576 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 577 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 578}
579
e3173832
SH		 580/* Put device in state to listen for Wake On Lan */
581static void sky2_wol_init(struct sky2_port *sky2)
582{
583 struct sky2_hw *hw = sky2->hw;
584 unsigned port = sky2->port;
585 enum flow_control save_mode;
586 u16 ctrl;
587 u32 reg1;
588
589 /* Bring hardware out of reset */
590 sky2_write16(hw, B0_CTST, CS_RST_CLR);
591 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
592
593 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
594 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
595
596 /* Force to 10/100
597 * sky2_reset will re-enable on resume
598 */
599 save_mode = sky2->flow_mode;
600 ctrl = sky2->advertising;
601
602 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
603 sky2->flow_mode = FC_NONE;
604 sky2_phy_power(hw, port, 1);
605 sky2_phy_reinit(sky2);
606
607 sky2->flow_mode = save_mode;
608 sky2->advertising = ctrl;
609
610 /* Set GMAC to no flow control and auto update for speed/duplex */
611 gma_write16(hw, port, GM_GP_CTRL,
612 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
613 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
614
615 /* Set WOL address */
616 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
617 sky2->netdev->dev_addr, ETH_ALEN);
618
619 /* Turn on appropriate WOL control bits */
620 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
621 ctrl = 0;
622 if (sky2->wol & WAKE_PHY)
623 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
624 else
625 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
626
627 if (sky2->wol & WAKE_MAGIC)
628 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
629 else
630 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
631
632 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
633 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
634
635 /* Turn on legacy PCI-Express PME mode */
636 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
637 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
638 reg1 |= PCI_Y2_PME_LEGACY;
639 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
640 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
641
642 /* block receiver */
643 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
644
645}
646
cd28ab6a
SH		 647static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
648{
649 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
650 u16 reg;
651 int i;
652 const u8 *addr = hw->dev[port]->dev_addr;
653
42eeea01
SH		 654 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
655 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 656
657 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
658
793b883e 659 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 660 /* WA DEV_472 -- looks like crossed wires on port 2 */
661 /* clear GMAC 1 Control reset */
662 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
663 do {
664 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
665 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
666 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
667 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
668 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
669 }
670
793b883e 671 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 672
2eaba1a2
SH		 673 /* Enable Transmit FIFO Underrun */
674 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
675
e07b1aa8 676 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 677 sky2_phy_init(hw, port);
e07b1aa8 678 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 679
680 /* MIB clear */
681 reg = gma_read16(hw, port, GM_PHY_ADDR);
682 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
683
43f2f104
SH		 684 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
685 gma_read16(hw, port, i);
cd28ab6a
SH		 686 gma_write16(hw, port, GM_PHY_ADDR, reg);
687
688 /* transmit control */
689 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
690
691 /* receive control reg: unicast + multicast + no FCS */
692 gma_write16(hw, port, GM_RX_CTRL,
793b883e 693 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 694
695 /* transmit flow control */
696 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
697
698 /* transmit parameter */
699 gma_write16(hw, port, GM_TX_PARAM,
700 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
701 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
702 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
703 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
704
705 /* serial mode register */
706 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 707 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 708
6b1a3aef 709 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 710 reg |= GM_SMOD_JUMBO_ENA;
711
712 gma_write16(hw, port, GM_SERIAL_MODE, reg);
713
cd28ab6a
SH		 714 /* virtual address for data */
715 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
716
793b883e
SH		 717 /* physical address: used for pause frames */
718 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
719
720 /* ignore counter overflows */
cd28ab6a
SH		 721 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
722 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
723 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
724
725 /* Configure Rx MAC FIFO */
726 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 727 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
728 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 729
d571b694 730 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 731 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 732
8df9a876
SH		 733 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
734 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 735
736 /* Configure Tx MAC FIFO */
737 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
738 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 739
93745494 740 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 741 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0
SH		 742 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
743 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
744 /* set Tx GMAC FIFO Almost Empty Threshold */
745 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
746 /* Disable Store & Forward mode for TX */
747 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
748 }
749 }
750
cd28ab6a
SH		 751}
752
67712901
SH		 753/* Assign Ram Buffer allocation to queue */
754static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 755{
67712901
SH		 756 u32 end;
757
758 /* convert from K bytes to qwords used for hw register */
759 start *= 1024/8;
760 space *= 1024/8;
761 end = start + space - 1;
793b883e 762
cd28ab6a
SH		 763 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
764 sky2_write32(hw, RB_ADDR(q, RB_START), start);
765 sky2_write32(hw, RB_ADDR(q, RB_END), end);
766 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
767 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
768
769 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 770 u32 tp = space - space/4;
793b883e 771
1c28f6ba
SH		 772 /* On receive queue's set the thresholds
773 * give receiver priority when > 3/4 full
774 * send pause when down to 2K
775 */
776 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
777 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 778
1c28f6ba
SH		 779 tp = space - 2048/8;
780 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
781 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 782 } else {
783 /* Enable store & forward on Tx queue's because
784 * Tx FIFO is only 1K on Yukon
785 */
786 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
787 }
788
789 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 790 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 791}
792
cd28ab6a 793/* Setup Bus Memory Interface */
af4ed7e6 794static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 795{
796 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
797 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
798 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 799 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 800}
801
cd28ab6a
SH		 802/* Setup prefetch unit registers. This is the interface between
803 * hardware and driver list elements
804 */
8cc048e3 805static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 806 u64 addr, u32 last)
807{
cd28ab6a
SH		 808 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
809 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
810 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
811 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
812 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
813 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 814
815 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 816}
817
793b883e
SH		 818static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
819{
820 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
821
cb5d9547 822 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 823 le->ctrl = 0;
793b883e
SH		 824 return le;
825}
cd28ab6a 826
291ea614
SH		 827static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
828 struct sky2_tx_le *le)
829{
830 return sky2->tx_ring + (le - sky2->tx_le);
831}
832
290d4de5
SH		 833/* Update chip's next pointer */
834static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 835{
98232f85 836 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 837 wmb();
98232f85
SH		 838 sky2_write16(hw, q, idx);
839 sky2_read16(hw, q);
cd28ab6a
SH		 840}
841
793b883e 842
cd28ab6a
SH		 843static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
844{
845 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 846 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 847 le->ctrl = 0;
cd28ab6a
SH		 848 return le;
849}
850
a018e330
SH		 851/* Return high part of DMA address (could be 32 or 64 bit) */
852static inline u32 high32(dma_addr_t a)
853{
a036119f 854 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 855}
856
14d0263f
SH		 857/* Build description to hardware for one receive segment */
858static void sky2_rx_add(struct sky2_port *sky2, u8 op,
859 dma_addr_t map, unsigned len)
cd28ab6a
SH		 860{
861 struct sky2_rx_le *le;
734d1868 862 u32 hi = high32(map);
cd28ab6a 863
793b883e 864 if (sky2->rx_addr64 != hi) {
cd28ab6a 865 le = sky2_next_rx(sky2);
793b883e 866 le->addr = cpu_to_le32(hi);
cd28ab6a 867 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 868 sky2->rx_addr64 = high32(map + len);
cd28ab6a 869 }
793b883e 870
cd28ab6a 871 le = sky2_next_rx(sky2);
734d1868
SH		 872 le->addr = cpu_to_le32((u32) map);
873 le->length = cpu_to_le16(len);
14d0263f 874 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 875}
876
14d0263f
SH		 877/* Build description to hardware for one possibly fragmented skb */
878static void sky2_rx_submit(struct sky2_port *sky2,
879 const struct rx_ring_info *re)
880{
881 int i;
882
883 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
884
885 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
886 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
887}
888
889
890static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
891 unsigned size)
892{
893 struct sk_buff *skb = re->skb;
894 int i;
895
896 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
897 pci_unmap_len_set(re, data_size, size);
898
899 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
900 re->frag_addr[i] = pci_map_page(pdev,
901 skb_shinfo(skb)->frags[i].page,
902 skb_shinfo(skb)->frags[i].page_offset,
903 skb_shinfo(skb)->frags[i].size,
904 PCI_DMA_FROMDEVICE);
905}
906
907static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
908{
909 struct sk_buff *skb = re->skb;
910 int i;
911
912 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
913 PCI_DMA_FROMDEVICE);
914
915 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
916 pci_unmap_page(pdev, re->frag_addr[i],
917 skb_shinfo(skb)->frags[i].size,
918 PCI_DMA_FROMDEVICE);
919}
793b883e 920
cd28ab6a
SH		 921/* Tell chip where to start receive checksum.
922 * Actually has two checksums, but set both same to avoid possible byte
923 * order problems.
924 */
793b883e 925static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 926{
927 struct sky2_rx_le *le;
928
cd28ab6a 929 le = sky2_next_rx(sky2);
f65b138c 930 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 931 le->ctrl = 0;
932 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 933
793b883e
SH		 934 sky2_write32(sky2->hw,
935 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
936 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 937
938}
939
6b1a3aef
SH		 940/*
941 * The RX Stop command will not work for Yukon-2 if the BMU does not
942 * reach the end of packet and since we can't make sure that we have
943 * incoming data, we must reset the BMU while it is not doing a DMA
944 * transfer. Since it is possible that the RX path is still active,
945 * the RX RAM buffer will be stopped first, so any possible incoming
946 * data will not trigger a DMA. After the RAM buffer is stopped, the
947 * BMU is polled until any DMA in progress is ended and only then it
948 * will be reset.
949 */
950static void sky2_rx_stop(struct sky2_port *sky2)
951{
952 struct sky2_hw *hw = sky2->hw;
953 unsigned rxq = rxqaddr[sky2->port];
954 int i;
955
956 /* disable the RAM Buffer receive queue */
957 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
958
959 for (i = 0; i < 0xffff; i++)
960 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
961 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
962 goto stopped;
963
964 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
965 sky2->netdev->name);
966stopped:
967 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
968
969 /* reset the Rx prefetch unit */
970 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
971}
793b883e 972
d571b694 973/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 974static void sky2_rx_clean(struct sky2_port *sky2)
975{
976 unsigned i;
977
978 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 979 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 980 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 981
982 if (re->skb) {
14d0263f 983 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 984 kfree_skb(re->skb);
985 re->skb = NULL;
986 }
987 }
988}
989
ef743d33
SH		 990/* Basic MII support */
991static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
992{
993 struct mii_ioctl_data *data = if_mii(ifr);
994 struct sky2_port *sky2 = netdev_priv(dev);
995 struct sky2_hw *hw = sky2->hw;
996 int err = -EOPNOTSUPP;
997
998 if (!netif_running(dev))
999 return -ENODEV; /* Phy still in reset */
1000
d89e1343 1001 switch (cmd) {
ef743d33
SH		 1002 case SIOCGMIIPHY:
1003 data->phy_id = PHY_ADDR_MARV;
1004
1005 /* fallthru */
1006 case SIOCGMIIREG: {
1007 u16 val = 0;
91c86df5 1008
e07b1aa8 1009 spin_lock_bh(&sky2->phy_lock);
ef743d33 1010 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1011 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1012
ef743d33
SH		 1013 data->val_out = val;
1014 break;
1015 }
1016
1017 case SIOCSMIIREG:
1018 if (!capable(CAP_NET_ADMIN))
1019 return -EPERM;
1020
e07b1aa8 1021 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1022 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1023 data->val_in);
e07b1aa8 1024 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1025 break;
1026 }
1027 return err;
1028}
1029
d1f13708
SH		 1030#ifdef SKY2_VLAN_TAG_USED
1031static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1032{
1033 struct sky2_port *sky2 = netdev_priv(dev);
1034 struct sky2_hw *hw = sky2->hw;
1035 u16 port = sky2->port;
d1f13708 1036
2bb8c262 1037 netif_tx_lock_bh(dev);
d1f13708
SH		 1038
1039 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1040 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1041 sky2->vlgrp = grp;
1042
2bb8c262 1043 netif_tx_unlock_bh(dev);
d1f13708
SH		 1044}
1045
1046static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1047{
1048 struct sky2_port *sky2 = netdev_priv(dev);
1049 struct sky2_hw *hw = sky2->hw;
1050 u16 port = sky2->port;
d1f13708 1051
2bb8c262 1052 netif_tx_lock_bh(dev);
d1f13708
SH		 1053
1054 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1055 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
5c15bdec 1056 vlan_group_set_device(sky2->vlgrp, vid, NULL);
d1f13708 1057
2bb8c262 1058 netif_tx_unlock_bh(dev);
d1f13708
SH		 1059}
1060#endif
1061
82788c7a 1062/*
14d0263f
SH		 1063 * Allocate an skb for receiving. If the MTU is large enough
1064 * make the skb non-linear with a fragment list of pages.
1065 *
82788c7a
SH		 1066 * It appears the hardware has a bug in the FIFO logic that
1067 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1068 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1069 * aligned except if slab debugging is enabled.
82788c7a 1070 */
14d0263f 1071static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1072{
1073 struct sk_buff *skb;
14d0263f
SH		 1074 unsigned long p;
1075 int i;
82788c7a 1076
14d0263f
SH		 1077 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1078 if (!skb)
1079 goto nomem;
1080
1081 p = (unsigned long) skb->data;
1082 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1083
1084 for (i = 0; i < sky2->rx_nfrags; i++) {
1085 struct page *page = alloc_page(GFP_ATOMIC);
1086
1087 if (!page)
1088 goto free_partial;
1089 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1090 }
1091
1092 return skb;
14d0263f
SH		 1093free_partial:
1094 kfree_skb(skb);
1095nomem:
1096 return NULL;
82788c7a
SH		 1097}
1098
cd28ab6a
SH		 1099/*
1100 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1101 * Normal case this ends up creating one list element for skb
1102 * in the receive ring. Worst case if using large MTU and each
1103 * allocation falls on a different 64 bit region, that results
1104 * in 6 list elements per ring entry.
1105 * One element is used for checksum enable/disable, and one
1106 * extra to avoid wrap.
cd28ab6a 1107 */
6b1a3aef 1108static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1109{
6b1a3aef 1110 struct sky2_hw *hw = sky2->hw;
14d0263f 1111 struct rx_ring_info *re;
6b1a3aef 1112 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1113 unsigned i, size, space, thresh;
cd28ab6a 1114
6b1a3aef 1115 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1116 sky2_qset(hw, rxq);
977bdf06 1117
c3905bc4
SH		 1118 /* On PCI express lowering the watermark gives better performance */
1119 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1120 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1121
1122 /* These chips have no ram buffer?
1123 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1124 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1125 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1126 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
977bdf06 1127 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
977bdf06 1128
6b1a3aef
SH		 1129 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1130
1131 rx_set_checksum(sky2);
14d0263f
SH		 1132
1133 /* Space needed for frame data + headers rounded up */
1134 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1135 + 8;
1136
1137 /* Stopping point for hardware truncation */
1138 thresh = (size - 8) / sizeof(u32);
1139
1140 /* Account for overhead of skb - to avoid order > 0 allocation */
1141 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1142 + sizeof(struct skb_shared_info);
1143
1144 sky2->rx_nfrags = space >> PAGE_SHIFT;
1145 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1146
1147 if (sky2->rx_nfrags != 0) {
1148 /* Compute residue after pages */
1149 space = sky2->rx_nfrags << PAGE_SHIFT;
1150
1151 if (space < size)
1152 size -= space;
1153 else
1154 size = 0;
1155
1156 /* Optimize to handle small packets and headers */
1157 if (size < copybreak)
1158 size = copybreak;
1159 if (size < ETH_HLEN)
1160 size = ETH_HLEN;
1161 }
1162 sky2->rx_data_size = size;
1163
1164 /* Fill Rx ring */
793b883e 1165 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1166 re = sky2->rx_ring + i;
cd28ab6a 1167
14d0263f 1168 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1169 if (!re->skb)
1170 goto nomem;
1171
14d0263f
SH		 1172 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1173 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1174 }
1175
a1433ac4
SH		 1176 /*
1177 * The receiver hangs if it receives frames larger than the
1178 * packet buffer. As a workaround, truncate oversize frames, but
1179 * the register is limited to 9 bits, so if you do frames > 2052
1180 * you better get the MTU right!
1181 */
a1433ac4
SH		 1182 if (thresh > 0x1ff)
1183 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1184 else {
1185 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1186 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1187 }
1188
6b1a3aef
SH		 1189 /* Tell chip about available buffers */
1190 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1191 return 0;
1192nomem:
1193 sky2_rx_clean(sky2);
1194 return -ENOMEM;
1195}
1196
1197/* Bring up network interface. */
1198static int sky2_up(struct net_device *dev)
1199{
1200 struct sky2_port *sky2 = netdev_priv(dev);
1201 struct sky2_hw *hw = sky2->hw;
1202 unsigned port = sky2->port;
67712901 1203 u32 ramsize, imask;
ee7abb04 1204 int cap, err = -ENOMEM;
843a46f4 1205 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1206
ee7abb04
SH		 1207 /*
1208 * On dual port PCI-X card, there is an problem where status
1209 * can be received out of order due to split transactions
843a46f4 1210 */
ee7abb04
SH		 1211 if (otherdev && netif_running(otherdev) &&
1212 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1213 struct sky2_port *osky2 = netdev_priv(otherdev);
1214 u16 cmd;
1215
1216 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1217 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1218 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1219
1220 sky2->rx_csum = 0;
1221 osky2->rx_csum = 0;
1222 }
843a46f4 1223
cd28ab6a
SH		 1224 if (netif_msg_ifup(sky2))
1225 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1226
1227 /* must be power of 2 */
1228 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1229 TX_RING_SIZE *
1230 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1231 &sky2->tx_le_map);
1232 if (!sky2->tx_le)
1233 goto err_out;
1234
6cdbbdf3 1235 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1236 GFP_KERNEL);
1237 if (!sky2->tx_ring)
1238 goto err_out;
1239 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1240
1241 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1242 &sky2->rx_le_map);
1243 if (!sky2->rx_le)
1244 goto err_out;
1245 memset(sky2->rx_le, 0, RX_LE_BYTES);
1246
291ea614 1247 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1248 GFP_KERNEL);
1249 if (!sky2->rx_ring)
1250 goto err_out;
1251
d3bcfbeb
SH		 1252 sky2_phy_power(hw, port, 1);
1253
cd28ab6a
SH		 1254 sky2_mac_init(hw, port);
1255
67712901
SH		 1256 /* Register is number of 4K blocks on internal RAM buffer. */
1257 ramsize = sky2_read8(hw, B2_E_0) * 4;
1258 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1259
67712901
SH		 1260 if (ramsize > 0) {
1261 u32 rxspace;
cd28ab6a 1262
67712901
SH		 1263 if (ramsize < 16)
1264 rxspace = ramsize / 2;
1265 else
1266 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1267
67712901
SH		 1268 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1269 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1270
1271 /* Make sure SyncQ is disabled */
1272 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1273 RB_RST_SET);
1274 }
793b883e 1275
af4ed7e6 1276 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1277
977bdf06 1278 /* Set almost empty threshold */
c2716fb4
SH		 1279 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1280 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1281 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1282
6b1a3aef
SH		 1283 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1284 TX_RING_SIZE - 1);
cd28ab6a 1285
6b1a3aef 1286 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1287 if (err)
1288 goto err_out;
1289
cd28ab6a 1290 /* Enable interrupts from phy/mac for port */
e07b1aa8 1291 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1292 imask |= portirq_msk[port];
e07b1aa8
SH		 1293 sky2_write32(hw, B0_IMSK, imask);
1294
cd28ab6a
SH		 1295 return 0;
1296
1297err_out:
1b537565 1298 if (sky2->rx_le) {
cd28ab6a
SH		 1299 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1300 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1301 sky2->rx_le = NULL;
1302 }
1303 if (sky2->tx_le) {
cd28ab6a
SH		 1304 pci_free_consistent(hw->pdev,
1305 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1306 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1307 sky2->tx_le = NULL;
1308 }
1309 kfree(sky2->tx_ring);
1310 kfree(sky2->rx_ring);
cd28ab6a 1311
1b537565
SH		 1312 sky2->tx_ring = NULL;
1313 sky2->rx_ring = NULL;
cd28ab6a
SH		 1314 return err;
1315}
1316
793b883e
SH		 1317/* Modular subtraction in ring */
1318static inline int tx_dist(unsigned tail, unsigned head)
1319{
cb5d9547 1320 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1321}
cd28ab6a 1322
793b883e
SH		 1323/* Number of list elements available for next tx */
1324static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1325{
793b883e 1326 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1327}
1328
793b883e 1329/* Estimate of number of transmit list elements required */
28bd181a 1330static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1331{
793b883e
SH		 1332 unsigned count;
1333
1334 count = sizeof(dma_addr_t) / sizeof(u32);
1335 count += skb_shinfo(skb)->nr_frags * count;
1336
89114afd 1337 if (skb_is_gso(skb))
793b883e
SH		 1338 ++count;
1339
84fa7933 1340 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1341 ++count;
1342
1343 return count;
cd28ab6a
SH		 1344}
1345
793b883e
SH		 1346/*
1347 * Put one packet in ring for transmit.
1348 * A single packet can generate multiple list elements, and
1349 * the number of ring elements will probably be less than the number
1350 * of list elements used.
1351 */
cd28ab6a
SH		 1352static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1353{
1354 struct sky2_port *sky2 = netdev_priv(dev);
1355 struct sky2_hw *hw = sky2->hw;
d1f13708 1356 struct sky2_tx_le *le = NULL;
6cdbbdf3 1357 struct tx_ring_info *re;
cd28ab6a
SH		 1358 unsigned i, len;
1359 dma_addr_t mapping;
1360 u32 addr64;
1361 u16 mss;
1362 u8 ctrl;
1363
2bb8c262
SH		 1364 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1365 return NETDEV_TX_BUSY;
cd28ab6a 1366
793b883e 1367 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1368 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1369 dev->name, sky2->tx_prod, skb->len);
1370
cd28ab6a
SH		 1371 len = skb_headlen(skb);
1372 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1373 addr64 = high32(mapping);
793b883e 1374
a018e330
SH		 1375 /* Send high bits if changed or crosses boundary */
1376 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1377 le = get_tx_le(sky2);
f65b138c 1378 le->addr = cpu_to_le32(addr64);
793b883e 1379 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1380 sky2->tx_addr64 = high32(mapping + len);
793b883e 1381 }
cd28ab6a
SH		 1382
1383 /* Check for TCP Segmentation Offload */
7967168c 1384 mss = skb_shinfo(skb)->gso_size;
793b883e 1385 if (mss != 0) {
cd28ab6a
SH		 1386 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1387 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1388 mss += ETH_HLEN;
1389
e07560cd
SH		 1390 if (mss != sky2->tx_last_mss) {
1391 le = get_tx_le(sky2);
f65b138c 1392 le->addr = cpu_to_le32(mss);
e07560cd 1393 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1394 sky2->tx_last_mss = mss;
1395 }
cd28ab6a
SH		 1396 }
1397
cd28ab6a 1398 ctrl = 0;
d1f13708
SH		 1399#ifdef SKY2_VLAN_TAG_USED
1400 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1401 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1402 if (!le) {
1403 le = get_tx_le(sky2);
f65b138c 1404 le->addr = 0;
d1f13708 1405 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1406 } else
1407 le->opcode |= OP_VLAN;
1408 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1409 ctrl |= INS_VLAN;
1410 }
1411#endif
1412
1413 /* Handle TCP checksum offload */
84fa7933 1414 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1415 unsigned offset = skb->h.raw - skb->data;
1416 u32 tcpsum;
1417
1418 tcpsum = offset << 16; /* sum start */
ff1dcadb 1419 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a
SH		 1420
1421 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1422 if (skb->nh.iph->protocol == IPPROTO_UDP)
1423 ctrl |= UDPTCP;
1424
f65b138c
SH		 1425 if (tcpsum != sky2->tx_tcpsum) {
1426 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1427
1428 le = get_tx_le(sky2);
f65b138c 1429 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1430 le->length = 0; /* initial checksum value */
1431 le->ctrl = 1; /* one packet */
1432 le->opcode = OP_TCPLISW | HW_OWNER;
1433 }
cd28ab6a
SH		 1434 }
1435
1436 le = get_tx_le(sky2);
f65b138c 1437 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1438 le->length = cpu_to_le16(len);
1439 le->ctrl = ctrl;
793b883e 1440 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1441
291ea614 1442 re = tx_le_re(sky2, le);
cd28ab6a 1443 re->skb = skb;
6cdbbdf3 1444 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1445 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1446
1447 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1448 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1449
1450 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1451 frag->size, PCI_DMA_TODEVICE);
a036119f 1452 addr64 = high32(mapping);
793b883e
SH		 1453 if (addr64 != sky2->tx_addr64) {
1454 le = get_tx_le(sky2);
f65b138c 1455 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1456 le->ctrl = 0;
1457 le->opcode = OP_ADDR64 | HW_OWNER;
1458 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1459 }
1460
1461 le = get_tx_le(sky2);
f65b138c 1462 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1463 le->length = cpu_to_le16(frag->size);
1464 le->ctrl = ctrl;
793b883e 1465 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1466
291ea614
SH		 1467 re = tx_le_re(sky2, le);
1468 re->skb = skb;
1469 pci_unmap_addr_set(re, mapaddr, mapping);
1470 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1471 }
6cdbbdf3 1472
cd28ab6a
SH		 1473 le->ctrl |= EOP;
1474
97bda706
SH		 1475 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1476 netif_stop_queue(dev);
b19666d9 1477
290d4de5 1478 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1479
cd28ab6a
SH		 1480 dev->trans_start = jiffies;
1481 return NETDEV_TX_OK;
1482}
1483
cd28ab6a 1484/*
793b883e
SH		 1485 * Free ring elements from starting at tx_cons until "done"
1486 *
1487 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1488 * buffers so make sure not to free skb to early.
cd28ab6a 1489 */
d11c13e7 1490static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1491{
d11c13e7 1492 struct net_device *dev = sky2->netdev;
af2a58ac 1493 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1494 unsigned idx;
cd28ab6a 1495
0e3ff6aa 1496 BUG_ON(done >= TX_RING_SIZE);
2224795d 1497
291ea614
SH		 1498 for (idx = sky2->tx_cons; idx != done;
1499 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1500 struct sky2_tx_le *le = sky2->tx_le + idx;
1501 struct tx_ring_info *re = sky2->tx_ring + idx;
1502
1503 switch(le->opcode & ~HW_OWNER) {
1504 case OP_LARGESEND:
1505 case OP_PACKET:
1506 pci_unmap_single(pdev,
1507 pci_unmap_addr(re, mapaddr),
1508 pci_unmap_len(re, maplen),
1509 PCI_DMA_TODEVICE);
af2a58ac 1510 break;
291ea614
SH		 1511 case OP_BUFFER:
1512 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1513 pci_unmap_len(re, maplen),
734d1868 1514 PCI_DMA_TODEVICE);
291ea614
SH		 1515 break;
1516 }
1517
1518 if (le->ctrl & EOP) {
1519 if (unlikely(netif_msg_tx_done(sky2)))
1520 printk(KERN_DEBUG "%s: tx done %u\n",
1521 dev->name, idx);
2bf56fe2 1522 sky2->net_stats.tx_packets++;
1523 sky2->net_stats.tx_bytes += re->skb->len;
1524
794b2bd2 1525 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1526 }
1527
291ea614 1528 le->opcode = 0; /* paranoia */
793b883e 1529 }
793b883e 1530
291ea614 1531 sky2->tx_cons = idx;
22e11703 1532 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1533 netif_wake_queue(dev);
cd28ab6a
SH		 1534}
1535
1536/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1537static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1538{
2bb8c262
SH		 1539 struct sky2_port *sky2 = netdev_priv(dev);
1540
1541 netif_tx_lock_bh(dev);
d11c13e7 1542 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1543 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1544}
1545
1546/* Network shutdown */
1547static int sky2_down(struct net_device *dev)
1548{
1549 struct sky2_port *sky2 = netdev_priv(dev);
1550 struct sky2_hw *hw = sky2->hw;
1551 unsigned port = sky2->port;
1552 u16 ctrl;
e07b1aa8 1553 u32 imask;
cd28ab6a 1554
1b537565
SH		 1555 /* Never really got started! */
1556 if (!sky2->tx_le)
1557 return 0;
1558
cd28ab6a
SH		 1559 if (netif_msg_ifdown(sky2))
1560 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1561
018d1c66 1562 /* Stop more packets from being queued */
cd28ab6a 1563 netif_stop_queue(dev);
9a87240c 1564 netif_carrier_off(dev);
cd28ab6a 1565
ebc646f6
SH		 1566 /* Disable port IRQ */
1567 imask = sky2_read32(hw, B0_IMSK);
1568 imask &= ~portirq_msk[port];
1569 sky2_write32(hw, B0_IMSK, imask);
1570
25d82d7a
SH		 1571 /*
1572 * Both ports share the NAPI poll on port 0, so if necessary undo the
1573 * the disable that is done in dev_close.
1574 */
1575 if (sky2->port == 0 && hw->ports > 1)
1576 netif_poll_enable(dev);
1577
d3bcfbeb 1578 sky2_gmac_reset(hw, port);
793b883e 1579
cd28ab6a
SH		 1580 /* Stop transmitter */
1581 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1582 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1583
1584 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1585 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1586
c2716fb4
SH		 1587 /* WA for dev. #4.209 */
1588 if (hw->chip_id == CHIP_ID_YUKON_EC_U
8df9a876 1589 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
c2716fb4
SH		 1590 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1591 sky2->speed != SPEED_1000 ?
1592 TX_STFW_ENA : TX_STFW_DIS);
1593
cd28ab6a 1594 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1595 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1596 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1597
1598 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1599
1600 /* Workaround shared GMAC reset */
793b883e
SH		 1601 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1602 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1603 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1604
1605 /* Disable Force Sync bit and Enable Alloc bit */
1606 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1607 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1608
1609 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1610 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1611 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1612
1613 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1614 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1615 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1616
1617 /* Reset the Tx prefetch units */
1618 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1619 PREF_UNIT_RST_SET);
1620
1621 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1622
6b1a3aef 1623 sky2_rx_stop(sky2);
cd28ab6a
SH		 1624
1625 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1626 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1627
d3bcfbeb
SH		 1628 sky2_phy_power(hw, port, 0);
1629
d571b694 1630 /* turn off LED's */
cd28ab6a
SH		 1631 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1632
018d1c66
SH		 1633 synchronize_irq(hw->pdev->irq);
1634
2bb8c262 1635 sky2_tx_clean(dev);
cd28ab6a
SH		 1636 sky2_rx_clean(sky2);
1637
1638 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1639 sky2->rx_le, sky2->rx_le_map);
1640 kfree(sky2->rx_ring);
1641
1642 pci_free_consistent(hw->pdev,
1643 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1644 sky2->tx_le, sky2->tx_le_map);
1645 kfree(sky2->tx_ring);
1646
1b537565
SH		 1647 sky2->tx_le = NULL;
1648 sky2->rx_le = NULL;
1649
1650 sky2->rx_ring = NULL;
1651 sky2->tx_ring = NULL;
1652
cd28ab6a
SH		 1653 return 0;
1654}
1655
1656static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1657{
b89165f2 1658 if (!sky2_is_copper(hw))
793b883e
SH		 1659 return SPEED_1000;
1660
cd28ab6a
SH		 1661 if (hw->chip_id == CHIP_ID_YUKON_FE)
1662 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1663
1664 switch (aux & PHY_M_PS_SPEED_MSK) {
1665 case PHY_M_PS_SPEED_1000:
1666 return SPEED_1000;
1667 case PHY_M_PS_SPEED_100:
1668 return SPEED_100;
1669 default:
1670 return SPEED_10;
1671 }
1672}
1673
1674static void sky2_link_up(struct sky2_port *sky2)
1675{
1676 struct sky2_hw *hw = sky2->hw;
1677 unsigned port = sky2->port;
1678 u16 reg;
16ad91e1
SH		 1679 static const char *fc_name[] = {
1680 [FC_NONE] = "none",
1681 [FC_TX] = "tx",
1682 [FC_RX] = "rx",
1683 [FC_BOTH] = "both",
1684 };
cd28ab6a 1685
cd28ab6a 1686 /* enable Rx/Tx */
2eaba1a2 1687 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1688 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1689 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1690
1691 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1692
1693 netif_carrier_on(sky2->netdev);
1694 netif_wake_queue(sky2->netdev);
1695
1696 /* Turn on link LED */
793b883e 1697 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1698 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1699
93745494
SH		 1700 if (hw->chip_id == CHIP_ID_YUKON_XL
1701 || hw->chip_id == CHIP_ID_YUKON_EC_U
1702 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1703 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1704 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1705
1706 switch(sky2->speed) {
1707 case SPEED_10:
1708 led |= PHY_M_LEDC_INIT_CTRL(7);
1709 break;
1710
1711 case SPEED_100:
1712 led |= PHY_M_LEDC_STA1_CTRL(7);
1713 break;
1714
1715 case SPEED_1000:
1716 led |= PHY_M_LEDC_STA0_CTRL(7);
1717 break;
1718 }
793b883e
SH		 1719
1720 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1721 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1722 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1723 }
1724
cd28ab6a
SH		 1725 if (netif_msg_link(sky2))
1726 printk(KERN_INFO PFX
d571b694 1727 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1728 sky2->netdev->name, sky2->speed,
1729 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1730 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1731}
1732
1733static void sky2_link_down(struct sky2_port *sky2)
1734{
1735 struct sky2_hw *hw = sky2->hw;
1736 unsigned port = sky2->port;
1737 u16 reg;
1738
1739 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1740
1741 reg = gma_read16(hw, port, GM_GP_CTRL);
1742 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1743 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1744
cd28ab6a
SH		 1745 netif_carrier_off(sky2->netdev);
1746 netif_stop_queue(sky2->netdev);
1747
1748 /* Turn on link LED */
1749 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1750
1751 if (netif_msg_link(sky2))
1752 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1753
cd28ab6a
SH		 1754 sky2_phy_init(hw, port);
1755}
1756
16ad91e1
SH		 1757static enum flow_control sky2_flow(int rx, int tx)
1758{
1759 if (rx)
1760 return tx ? FC_BOTH : FC_RX;
1761 else
1762 return tx ? FC_TX : FC_NONE;
1763}
1764
793b883e
SH		 1765static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1766{
1767 struct sky2_hw *hw = sky2->hw;
1768 unsigned port = sky2->port;
da4c1ff4 1769 u16 advert, lpa;
793b883e 1770
da4c1ff4 1771 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1772 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1773 if (lpa & PHY_M_AN_RF) {
1774 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1775 return -1;
1776 }
1777
793b883e
SH		 1778 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1779 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1780 sky2->netdev->name);
1781 return -1;
1782 }
1783
793b883e 1784 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1785 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1786
da4c1ff4
SH		 1787 /* Since the pause result bits seem to in different positions on
1788 * different chips. look at registers.
1789 */
1790 if (!sky2_is_copper(hw)) {
1791 /* Shift for bits in fiber PHY */
1792 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1793 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1794
1795 if (advert & ADVERTISE_1000XPAUSE)
1796 advert |= ADVERTISE_PAUSE_CAP;
1797 if (advert & ADVERTISE_1000XPSE_ASYM)
1798 advert |= ADVERTISE_PAUSE_ASYM;
1799 if (lpa & LPA_1000XPAUSE)
1800 lpa |= LPA_PAUSE_CAP;
1801 if (lpa & LPA_1000XPAUSE_ASYM)
1802 lpa |= LPA_PAUSE_ASYM;
1803 }
793b883e 1804
da4c1ff4
SH		 1805 sky2->flow_status = FC_NONE;
1806 if (advert & ADVERTISE_PAUSE_CAP) {
1807 if (lpa & LPA_PAUSE_CAP)
1808 sky2->flow_status = FC_BOTH;
1809 else if (advert & ADVERTISE_PAUSE_ASYM)
1810 sky2->flow_status = FC_RX;
1811 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1812 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1813 sky2->flow_status = FC_TX;
1814 }
793b883e 1815
16ad91e1 1816 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1817 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1818 sky2->flow_status = FC_NONE;
2eaba1a2 1819
da4c1ff4 1820 if (sky2->flow_status & FC_TX)
793b883e
SH		 1821 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1822 else
1823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1824
1825 return 0;
1826}
cd28ab6a 1827
e07b1aa8
SH		 1828/* Interrupt from PHY */
1829static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1830{
e07b1aa8
SH		 1831 struct net_device *dev = hw->dev[port];
1832 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1833 u16 istatus, phystat;
1834
ebc646f6
SH		 1835 if (!netif_running(dev))
1836 return;
1837
e07b1aa8
SH		 1838 spin_lock(&sky2->phy_lock);
1839 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1840 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1841
cd28ab6a
SH		 1842 if (netif_msg_intr(sky2))
1843 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1844 sky2->netdev->name, istatus, phystat);
1845
2eaba1a2 1846 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1847 if (sky2_autoneg_done(sky2, phystat) == 0)
1848 sky2_link_up(sky2);
1849 goto out;
1850 }
cd28ab6a 1851
793b883e
SH		 1852 if (istatus & PHY_M_IS_LSP_CHANGE)
1853 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1854
793b883e
SH		 1855 if (istatus & PHY_M_IS_DUP_CHANGE)
1856 sky2->duplex =
1857 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1858
793b883e
SH		 1859 if (istatus & PHY_M_IS_LST_CHANGE) {
1860 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1861 sky2_link_up(sky2);
793b883e
SH		 1862 else
1863 sky2_link_down(sky2);
cd28ab6a 1864 }
793b883e 1865out:
e07b1aa8 1866 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1867}
1868
62335ab0 1869/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1870 * and tx queue is full (stopped).
1871 */
cd28ab6a
SH		 1872static void sky2_tx_timeout(struct net_device *dev)
1873{
1874 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1875 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1876
1877 if (netif_msg_timer(sky2))
1878 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1879
8f24664d 1880 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1881 dev->name, sky2->tx_cons, sky2->tx_prod,
1882 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1883 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1884
81906791
SH		 1885 /* can't restart safely under softirq */
1886 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1887}
1888
1889static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1890{
6b1a3aef
SH		 1891 struct sky2_port *sky2 = netdev_priv(dev);
1892 struct sky2_hw *hw = sky2->hw;
1893 int err;
1894 u16 ctl, mode;
e07b1aa8 1895 u32 imask;
cd28ab6a
SH		 1896
1897 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1898 return -EINVAL;
1899
4a50a876 1900 /* TSO on Yukon Ultra and MTU > 1500 not supported */
5a5b1ea0 1901 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
4a50a876 1902 dev->features &= ~NETIF_F_TSO;
5a5b1ea0 1903
6b1a3aef
SH		 1904 if (!netif_running(dev)) {
1905 dev->mtu = new_mtu;
1906 return 0;
1907 }
1908
e07b1aa8 1909 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1910 sky2_write32(hw, B0_IMSK, 0);
1911
018d1c66
SH		 1912 dev->trans_start = jiffies; /* prevent tx timeout */
1913 netif_stop_queue(dev);
1914 netif_poll_disable(hw->dev[0]);
1915
e07b1aa8
SH		 1916 synchronize_irq(hw->pdev->irq);
1917
6b1a3aef
SH		 1918 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1919 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1920 sky2_rx_stop(sky2);
1921 sky2_rx_clean(sky2);
cd28ab6a
SH		 1922
1923 dev->mtu = new_mtu;
14d0263f 1924
6b1a3aef
SH		 1925 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1926 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1927
1928 if (dev->mtu > ETH_DATA_LEN)
1929 mode |= GM_SMOD_JUMBO_ENA;
1930
1931 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1932
6b1a3aef 1933 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1934
6b1a3aef 1935 err = sky2_rx_start(sky2);
e07b1aa8 1936 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1937
1b537565
SH		 1938 if (err)
1939 dev_close(dev);
1940 else {
1941 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1942
1943 netif_poll_enable(hw->dev[0]);
1944 netif_wake_queue(dev);
1945 }
1946
cd28ab6a
SH		 1947 return err;
1948}
1949
14d0263f
SH		 1950/* For small just reuse existing skb for next receive */
1951static struct sk_buff *receive_copy(struct sky2_port *sky2,
1952 const struct rx_ring_info *re,
1953 unsigned length)
1954{
1955 struct sk_buff *skb;
1956
1957 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1958 if (likely(skb)) {
1959 skb_reserve(skb, 2);
1960 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1961 length, PCI_DMA_FROMDEVICE);
1962 memcpy(skb->data, re->skb->data, length);
1963 skb->ip_summed = re->skb->ip_summed;
1964 skb->csum = re->skb->csum;
1965 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1966 length, PCI_DMA_FROMDEVICE);
1967 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1968 skb_put(skb, length);
14d0263f
SH		 1969 }
1970 return skb;
1971}
1972
1973/* Adjust length of skb with fragments to match received data */
1974static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1975 unsigned int length)
1976{
1977 int i, num_frags;
1978 unsigned int size;
1979
1980 /* put header into skb */
1981 size = min(length, hdr_space);
1982 skb->tail += size;
1983 skb->len += size;
1984 length -= size;
1985
1986 num_frags = skb_shinfo(skb)->nr_frags;
1987 for (i = 0; i < num_frags; i++) {
1988 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1989
1990 if (length == 0) {
1991 /* don't need this page */
1992 __free_page(frag->page);
1993 --skb_shinfo(skb)->nr_frags;
1994 } else {
1995 size = min(length, (unsigned) PAGE_SIZE);
1996
1997 frag->size = size;
1998 skb->data_len += size;
1999 skb->truesize += size;
2000 skb->len += size;
2001 length -= size;
2002 }
2003 }
2004}
2005
2006/* Normal packet - take skb from ring element and put in a new one */
2007static struct sk_buff *receive_new(struct sky2_port *sky2,
2008 struct rx_ring_info *re,
2009 unsigned int length)
2010{
2011 struct sk_buff *skb, *nskb;
2012 unsigned hdr_space = sky2->rx_data_size;
2013
2014 pr_debug(PFX "receive new length=%d\n", length);
2015
2016 /* Don't be tricky about reusing pages (yet) */
2017 nskb = sky2_rx_alloc(sky2);
2018 if (unlikely(!nskb))
2019 return NULL;
2020
2021 skb = re->skb;
2022 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2023
2024 prefetch(skb->data);
2025 re->skb = nskb;
2026 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2027
2028 if (skb_shinfo(skb)->nr_frags)
2029 skb_put_frags(skb, hdr_space, length);
2030 else
489b10c1 2031 skb_put(skb, length);
14d0263f
SH		 2032 return skb;
2033}
2034
cd28ab6a
SH		 2035/*
2036 * Receive one packet.
d571b694 2037 * For larger packets, get new buffer.
cd28ab6a 2038 */
497d7c86 2039static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2040 u16 length, u32 status)
2041{
497d7c86 2042 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2043 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2044 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2045
2046 if (unlikely(netif_msg_rx_status(sky2)))
2047 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2048 dev->name, sky2->rx_next, status, length);
cd28ab6a 2049
793b883e 2050 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2051 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2052
42eeea01 2053 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2054 goto error;
2055
42eeea01
SH		 2056 if (!(status & GMR_FS_RX_OK))
2057 goto resubmit;
2058
14d0263f
SH		 2059 if (length < copybreak)
2060 skb = receive_copy(sky2, re, length);
2061 else
2062 skb = receive_new(sky2, re, length);
793b883e 2063resubmit:
14d0263f 2064 sky2_rx_submit(sky2, re);
79e57d32 2065
cd28ab6a
SH		 2066 return skb;
2067
2068error:
6e15b712 2069 ++sky2->net_stats.rx_errors;
b6d77734 2070 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2071 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2072 goto resubmit;
2073 }
6e15b712 2074
3be92a70 2075 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2076 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2077 dev->name, status, length);
793b883e
SH		 2078
2079 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2080 sky2->net_stats.rx_length_errors++;
2081 if (status & GMR_FS_FRAGMENT)
2082 sky2->net_stats.rx_frame_errors++;
2083 if (status & GMR_FS_CRC_ERR)
2084 sky2->net_stats.rx_crc_errors++;
79e57d32 2085
793b883e 2086 goto resubmit;
cd28ab6a
SH		 2087}
2088
e07b1aa8
SH		 2089/* Transmit complete */
2090static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2091{
e07b1aa8 2092 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2093
e07b1aa8 2094 if (netif_running(dev)) {
2bb8c262 2095 netif_tx_lock(dev);
e07b1aa8 2096 sky2_tx_complete(sky2, last);
2bb8c262 2097 netif_tx_unlock(dev);
2224795d 2098 }
cd28ab6a
SH		 2099}
2100
e07b1aa8
SH		 2101/* Process status response ring */
2102static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2103{
22e11703 2104 struct sky2_port *sky2;
e07b1aa8 2105 int work_done = 0;
22e11703 2106 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2107 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2108
af2a58ac 2109 rmb();
bea86103 2110
e71ebd73 2111 while (hw->st_idx != hwidx) {
13210ce5
SH		 2112 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2113 struct net_device *dev;
cd28ab6a 2114 struct sk_buff *skb;
cd28ab6a
SH		 2115 u32 status;
2116 u16 length;
2117
cb5d9547 2118 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2119
e71ebd73
SH		 2120 BUG_ON(le->link >= 2);
2121 dev = hw->dev[le->link];
13210ce5
SH		 2122
2123 sky2 = netdev_priv(dev);
f65b138c
SH		 2124 length = le16_to_cpu(le->length);
2125 status = le32_to_cpu(le->status);
cd28ab6a 2126
e71ebd73 2127 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2128 case OP_RXSTAT:
497d7c86 2129 skb = sky2_receive(dev, length, status);
d1f13708 2130 if (!skb)
5df79111 2131 goto force_update;
13210ce5 2132
13210ce5 2133 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2134 sky2->net_stats.rx_packets++;
2135 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2136 dev->last_rx = jiffies;
2137
d1f13708
SH		 2138#ifdef SKY2_VLAN_TAG_USED
2139 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2140 vlan_hwaccel_receive_skb(skb,
2141 sky2->vlgrp,
2142 be16_to_cpu(sky2->rx_tag));
2143 } else
2144#endif
cd28ab6a 2145 netif_receive_skb(skb);
13210ce5 2146
22e11703
SH		 2147 /* Update receiver after 16 frames */
2148 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2149force_update:
2150 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2151 buf_write[le->link] = 0;
2152 }
2153
2154 /* Stop after net poll weight */
13210ce5
SH		 2155 if (++work_done >= to_do)
2156 goto exit_loop;
cd28ab6a
SH		 2157 break;
2158
d1f13708
SH		 2159#ifdef SKY2_VLAN_TAG_USED
2160 case OP_RXVLAN:
2161 sky2->rx_tag = length;
2162 break;
2163
2164 case OP_RXCHKSVLAN:
2165 sky2->rx_tag = length;
2166 /* fall through */
2167#endif
cd28ab6a 2168 case OP_RXCHKS:
87418307
SH		 2169 if (!sky2->rx_csum)
2170 break;
2171
2172 /* Both checksum counters are programmed to start at
2173 * the same offset, so unless there is a problem they
2174 * should match. This failure is an early indication that
2175 * hardware receive checksumming won't work.
2176 */
2177 if (likely(status >> 16 == (status & 0xffff))) {
2178 skb = sky2->rx_ring[sky2->rx_next].skb;
2179 skb->ip_summed = CHECKSUM_COMPLETE;
2180 skb->csum = status & 0xffff;
2181 } else {
2182 printk(KERN_NOTICE PFX "%s: hardware receive "
2183 "checksum problem (status = %#x)\n",
2184 dev->name, status);
2185 sky2->rx_csum = 0;
2186 sky2_write32(sky2->hw,
2187 Q_ADDR(rxqaddr[le->link], Q_CSR),
2188 BMU_DIS_RX_CHKSUM);
2189 }
cd28ab6a
SH		 2190 break;
2191
2192 case OP_TXINDEXLE:
13b97b74 2193 /* TX index reports status for both ports */
f55925d7
SH		 2194 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2195 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2196 if (hw->dev[1])
2197 sky2_tx_done(hw->dev[1],
2198 ((status >> 24) & 0xff)
2199 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2200 break;
2201
cd28ab6a
SH		 2202 default:
2203 if (net_ratelimit())
793b883e 2204 printk(KERN_WARNING PFX
e71ebd73
SH		 2205 "unknown status opcode 0x%x\n", le->opcode);
2206 goto exit_loop;
cd28ab6a 2207 }
13210ce5 2208 }
cd28ab6a 2209
fe2a24df
SH		 2210 /* Fully processed status ring so clear irq */
2211 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2212
13210ce5 2213exit_loop:
22e11703
SH		 2214 if (buf_write[0]) {
2215 sky2 = netdev_priv(hw->dev[0]);
2216 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2217 }
2218
2219 if (buf_write[1]) {
2220 sky2 = netdev_priv(hw->dev[1]);
2221 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2222 }
2223
e07b1aa8 2224 return work_done;
cd28ab6a
SH		 2225}
2226
2227static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2228{
2229 struct net_device *dev = hw->dev[port];
2230
3be92a70
SH		 2231 if (net_ratelimit())
2232 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2233 dev->name, status);
cd28ab6a
SH		 2234
2235 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2236 if (net_ratelimit())
2237 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2238 dev->name);
cd28ab6a
SH		 2239 /* Clear IRQ */
2240 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2241 }
2242
2243 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2244 if (net_ratelimit())
2245 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2246 dev->name);
cd28ab6a
SH		 2247
2248 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2249 }
2250
2251 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2252 if (net_ratelimit())
2253 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2254 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2255 }
2256
2257 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2258 if (net_ratelimit())
2259 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2260 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2261 }
2262
2263 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2264 if (net_ratelimit())
2265 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2266 dev->name);
cd28ab6a
SH		 2267 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2268 }
2269}
2270
2271static void sky2_hw_intr(struct sky2_hw *hw)
2272{
2273 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2274
793b883e 2275 if (status & Y2_IS_TIST_OV)
cd28ab6a 2276 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2277
2278 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2279 u16 pci_err;
2280
56a645cc 2281 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2282 if (net_ratelimit())
b02a9258
SH		 2283 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2284 pci_err);
cd28ab6a
SH		 2285
2286 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2287 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2288 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2289 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2290 }
2291
2292 if (status & Y2_IS_PCI_EXP) {
d571b694 2293 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2294 u32 pex_err;
2295
7bd656d1 2296 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2297
3be92a70 2298 if (net_ratelimit())
b02a9258
SH		 2299 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2300 pex_err);
cd28ab6a
SH		 2301
2302 /* clear the interrupt */
2303 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2304 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2305 0xffffffffUL);
cd28ab6a
SH		 2306 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2307
7bd656d1 2308 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2309 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2310 hwmsk &= ~Y2_IS_PCI_EXP;
2311 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2312 }
2313 }
2314
2315 if (status & Y2_HWE_L1_MASK)
2316 sky2_hw_error(hw, 0, status);
2317 status >>= 8;
2318 if (status & Y2_HWE_L1_MASK)
2319 sky2_hw_error(hw, 1, status);
2320}
2321
2322static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2323{
2324 struct net_device *dev = hw->dev[port];
2325 struct sky2_port *sky2 = netdev_priv(dev);
2326 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2327
2328 if (netif_msg_intr(sky2))
2329 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2330 dev->name, status);
2331
2332 if (status & GM_IS_RX_FF_OR) {
2333 ++sky2->net_stats.rx_fifo_errors;
2334 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2335 }
2336
2337 if (status & GM_IS_TX_FF_UR) {
2338 ++sky2->net_stats.tx_fifo_errors;
2339 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2340 }
cd28ab6a
SH		 2341}
2342
d257924e
SH		 2343/* This should never happen it is a fatal situation */
2344static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2345 const char *rxtx, u32 mask)
2346{
2347 struct net_device *dev = hw->dev[port];
2348 struct sky2_port *sky2 = netdev_priv(dev);
2349 u32 imask;
2350
2351 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2352 dev ? dev->name : "<not registered>", rxtx);
2353
2354 imask = sky2_read32(hw, B0_IMSK);
2355 imask &= ~mask;
2356 sky2_write32(hw, B0_IMSK, imask);
2357
2358 if (dev) {
2359 spin_lock(&sky2->phy_lock);
2360 sky2_link_down(sky2);
2361 spin_unlock(&sky2->phy_lock);
2362 }
2363}
cd28ab6a 2364
d27ed387
SH		 2365/* If idle then force a fake soft NAPI poll once a second
2366 * to work around cases where sharing an edge triggered interrupt.
2367 */
eb35cf60
SH		 2368static inline void sky2_idle_start(struct sky2_hw *hw)
2369{
2370 if (idle_timeout > 0)
2371 mod_timer(&hw->idle_timer,
2372 jiffies + msecs_to_jiffies(idle_timeout));
2373}
2374
d27ed387
SH		 2375static void sky2_idle(unsigned long arg)
2376{
01bd7564
SH		 2377 struct sky2_hw *hw = (struct sky2_hw *) arg;
2378 struct net_device *dev = hw->dev[0];
d27ed387 2379
d27ed387
SH		 2380 if (__netif_rx_schedule_prep(dev))
2381 __netif_rx_schedule(dev);
01bd7564
SH		 2382
2383 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2384}
2385
2386
e07b1aa8 2387static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2388{
e07b1aa8
SH		 2389 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2390 int work_limit = min(dev0->quota, *budget);
2391 int work_done = 0;
fb2690a9 2392 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2393
1e5f1283
SH		 2394 if (status & Y2_IS_HW_ERR)
2395 sky2_hw_intr(hw);
d257924e 2396
1e5f1283
SH		 2397 if (status & Y2_IS_IRQ_PHY1)
2398 sky2_phy_intr(hw, 0);
cd28ab6a 2399
1e5f1283
SH		 2400 if (status & Y2_IS_IRQ_PHY2)
2401 sky2_phy_intr(hw, 1);
cd28ab6a 2402
1e5f1283
SH		 2403 if (status & Y2_IS_IRQ_MAC1)
2404 sky2_mac_intr(hw, 0);
cd28ab6a 2405
1e5f1283
SH		 2406 if (status & Y2_IS_IRQ_MAC2)
2407 sky2_mac_intr(hw, 1);
cd28ab6a 2408
1e5f1283
SH		 2409 if (status & Y2_IS_CHK_RX1)
2410 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2411
1e5f1283
SH		 2412 if (status & Y2_IS_CHK_RX2)
2413 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2414
1e5f1283
SH		 2415 if (status & Y2_IS_CHK_TXA1)
2416 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2417
1e5f1283
SH		 2418 if (status & Y2_IS_CHK_TXA2)
2419 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2420
1e5f1283 2421 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2422 if (work_done < work_limit) {
2423 netif_rx_complete(dev0);
86fba634 2424
fe2a24df
SH		 2425 sky2_read32(hw, B0_Y2_SP_LISR);
2426 return 0;
2427 } else {
2428 *budget -= work_done;
2429 dev0->quota -= work_done;
1e5f1283 2430 return 1;
fe2a24df 2431 }
e07b1aa8
SH		 2432}
2433
7d12e780 2434static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2435{
2436 struct sky2_hw *hw = dev_id;
2437 struct net_device *dev0 = hw->dev[0];
2438 u32 status;
2439
2440 /* Reading this mask interrupts as side effect */
2441 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2442 if (status == 0 || status == ~0)
2443 return IRQ_NONE;
793b883e 2444
e07b1aa8
SH		 2445 prefetch(&hw->st_le[hw->st_idx]);
2446 if (likely(__netif_rx_schedule_prep(dev0)))
2447 __netif_rx_schedule(dev0);
793b883e 2448
cd28ab6a
SH		 2449 return IRQ_HANDLED;
2450}
2451
2452#ifdef CONFIG_NET_POLL_CONTROLLER
2453static void sky2_netpoll(struct net_device *dev)
2454{
2455 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2456 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2457
88d11360
SH		 2458 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2459 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2460}
2461#endif
2462
2463/* Chip internal frequency for clock calculations */
fb17358f 2464static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2465{
793b883e 2466 switch (hw->chip_id) {
cd28ab6a 2467 case CHIP_ID_YUKON_EC:
5a5b1ea0 2468 case CHIP_ID_YUKON_EC_U:
93745494 2469 case CHIP_ID_YUKON_EX:
fb17358f 2470 return 125; /* 125 Mhz */
cd28ab6a 2471 case CHIP_ID_YUKON_FE:
fb17358f 2472 return 100; /* 100 Mhz */
793b883e 2473 default: /* YUKON_XL */
fb17358f 2474 return 156; /* 156 Mhz */
cd28ab6a
SH		 2475 }
2476}
2477
fb17358f 2478static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2479{
fb17358f 2480 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2481}
2482
fb17358f 2483static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2484{
fb17358f 2485 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2486}
2487
fb17358f 2488
e3173832 2489static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2490{
b89165f2 2491 u8 t8;
cd28ab6a 2492
cd28ab6a 2493 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2494
cd28ab6a
SH		 2495 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2496 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2497 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2498 hw->chip_id);
cd28ab6a
SH		 2499 return -EOPNOTSUPP;
2500 }
2501
93745494
SH		 2502 if (hw->chip_id == CHIP_ID_YUKON_EX)
2503 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2504 "Please report success or failure to <netdev@vger.kernel.org>\n");
2505
2506 /* Make sure and enable all clocks */
2507 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2508 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2509
290d4de5
SH		 2510 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2511
2512 /* This rev is really old, and requires untested workarounds */
2513 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2514 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2515 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2516 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2517 return -EOPNOTSUPP;
2518 }
2519
e3173832
SH		 2520 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2521 hw->ports = 1;
2522 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2523 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2524 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2525 ++hw->ports;
2526 }
2527
2528 return 0;
2529}
2530
2531static void sky2_reset(struct sky2_hw *hw)
2532{
2533 u16 status;
2534 int i;
2535
cd28ab6a
SH		 2536 /* disable ASF */
2537 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
93745494
SH		 2538 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2539 status = sky2_read16(hw, HCU_CCSR);
2540 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2541 HCU_CCSR_UC_STATE_MSK);
2542 sky2_write16(hw, HCU_CCSR, status);
2543 } else
2544 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
cd28ab6a
SH		 2545 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2546 }
2547
2548 /* do a SW reset */
2549 sky2_write8(hw, B0_CTST, CS_RST_SET);
2550 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2551
2552 /* clear PCI errors, if any */
56a645cc 2553 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2554
cd28ab6a 2555 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2556 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2557
cd28ab6a
SH		 2558
2559 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2560
2561 /* clear any PEX errors */
7bd656d1
SH		 2562 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2563 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2564
cd28ab6a 2565
ae306cca 2566 sky2_power_on(hw);
cd28ab6a
SH		 2567
2568 for (i = 0; i < hw->ports; i++) {
2569 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2570 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2571 }
2572
2573 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2574
793b883e
SH		 2575 /* Clear I2C IRQ noise */
2576 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2577
2578 /* turn off hardware timer (unused) */
2579 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2580 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2581
cd28ab6a
SH		 2582 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2583
69634ee7
SH		 2584 /* Turn off descriptor polling */
2585 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2586
2587 /* Turn off receive timestamp */
2588 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2589 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2590
2591 /* enable the Tx Arbiters */
2592 for (i = 0; i < hw->ports; i++)
2593 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2594
2595 /* Initialize ram interface */
2596 for (i = 0; i < hw->ports; i++) {
793b883e 2597 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2598
2599 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2600 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2601 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2602 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2603 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2604 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2605 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2606 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2607 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2608 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2609 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2610 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2611 }
2612
7bd656d1 2613 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2614
cd28ab6a 2615 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2616 sky2_gmac_reset(hw, i);
cd28ab6a 2617
cd28ab6a
SH		 2618 memset(hw->st_le, 0, STATUS_LE_BYTES);
2619 hw->st_idx = 0;
2620
2621 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2622 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2623
2624 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2625 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2626
2627 /* Set the list last index */
793b883e 2628 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2629
290d4de5
SH		 2630 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2631 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2632
290d4de5
SH		 2633 /* set Status-FIFO ISR watermark */
2634 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2635 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2636 else
2637 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2638
290d4de5 2639 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2640 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2641 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2642
793b883e 2643 /* enable status unit */
cd28ab6a
SH		 2644 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2645
2646 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2647 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2648 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2649}
2650
81906791
SH		 2651static void sky2_restart(struct work_struct *work)
2652{
2653 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2654 struct net_device *dev;
2655 int i, err;
2656
2657 dev_dbg(&hw->pdev->dev, "restarting\n");
2658
2659 del_timer_sync(&hw->idle_timer);
2660
2661 rtnl_lock();
2662 sky2_write32(hw, B0_IMSK, 0);
2663 sky2_read32(hw, B0_IMSK);
2664
2665 netif_poll_disable(hw->dev[0]);
2666
2667 for (i = 0; i < hw->ports; i++) {
2668 dev = hw->dev[i];
2669 if (netif_running(dev))
2670 sky2_down(dev);
2671 }
2672
2673 sky2_reset(hw);
2674 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2675 netif_poll_enable(hw->dev[0]);
2676
2677 for (i = 0; i < hw->ports; i++) {
2678 dev = hw->dev[i];
2679 if (netif_running(dev)) {
2680 err = sky2_up(dev);
2681 if (err) {
2682 printk(KERN_INFO PFX "%s: could not restart %d\n",
2683 dev->name, err);
2684 dev_close(dev);
2685 }
2686 }
2687 }
2688
2689 sky2_idle_start(hw);
2690
2691 rtnl_unlock();
2692}
2693
e3173832
SH		 2694static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2695{
2696 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2697}
2698
2699static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2700{
2701 const struct sky2_port *sky2 = netdev_priv(dev);
2702
2703 wol->supported = sky2_wol_supported(sky2->hw);
2704 wol->wolopts = sky2->wol;
2705}
2706
2707static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2708{
2709 struct sky2_port *sky2 = netdev_priv(dev);
2710 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2711
e3173832
SH		 2712 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2713 return -EOPNOTSUPP;
2714
2715 sky2->wol = wol->wolopts;
2716
2717 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2718 sky2_write32(hw, B0_CTST, sky2->wol
2719 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2720
2721 if (!netif_running(dev))
2722 sky2_wol_init(sky2);
cd28ab6a
SH		 2723 return 0;
2724}
2725
28bd181a 2726static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2727{
b89165f2
SH		 2728 if (sky2_is_copper(hw)) {
2729 u32 modes = SUPPORTED_10baseT_Half
2730 | SUPPORTED_10baseT_Full
2731 | SUPPORTED_100baseT_Half
2732 | SUPPORTED_100baseT_Full
2733 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2734
2735 if (hw->chip_id != CHIP_ID_YUKON_FE)
2736 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2737 | SUPPORTED_1000baseT_Full;
2738 return modes;
cd28ab6a 2739 } else
b89165f2
SH		 2740 return SUPPORTED_1000baseT_Half
2741 | SUPPORTED_1000baseT_Full
2742 | SUPPORTED_Autoneg
2743 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2744}
2745
793b883e 2746static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2747{
2748 struct sky2_port *sky2 = netdev_priv(dev);
2749 struct sky2_hw *hw = sky2->hw;
2750
2751 ecmd->transceiver = XCVR_INTERNAL;
2752 ecmd->supported = sky2_supported_modes(hw);
2753 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2754 if (sky2_is_copper(hw)) {
cd28ab6a 2755 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2756 | SUPPORTED_10baseT_Full
2757 | SUPPORTED_100baseT_Half
2758 | SUPPORTED_100baseT_Full
2759 | SUPPORTED_1000baseT_Half
2760 | SUPPORTED_1000baseT_Full
2761 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2762 ecmd->port = PORT_TP;
b89165f2
SH		 2763 ecmd->speed = sky2->speed;
2764 } else {
2765 ecmd->speed = SPEED_1000;
cd28ab6a 2766 ecmd->port = PORT_FIBRE;
b89165f2 2767 }
cd28ab6a
SH		 2768
2769 ecmd->advertising = sky2->advertising;
2770 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2771 ecmd->duplex = sky2->duplex;
2772 return 0;
2773}
2774
2775static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2776{
2777 struct sky2_port *sky2 = netdev_priv(dev);
2778 const struct sky2_hw *hw = sky2->hw;
2779 u32 supported = sky2_supported_modes(hw);
2780
2781 if (ecmd->autoneg == AUTONEG_ENABLE) {
2782 ecmd->advertising = supported;
2783 sky2->duplex = -1;
2784 sky2->speed = -1;
2785 } else {
2786 u32 setting;
2787
793b883e 2788 switch (ecmd->speed) {
cd28ab6a
SH		 2789 case SPEED_1000:
2790 if (ecmd->duplex == DUPLEX_FULL)
2791 setting = SUPPORTED_1000baseT_Full;
2792 else if (ecmd->duplex == DUPLEX_HALF)
2793 setting = SUPPORTED_1000baseT_Half;
2794 else
2795 return -EINVAL;
2796 break;
2797 case SPEED_100:
2798 if (ecmd->duplex == DUPLEX_FULL)
2799 setting = SUPPORTED_100baseT_Full;
2800 else if (ecmd->duplex == DUPLEX_HALF)
2801 setting = SUPPORTED_100baseT_Half;
2802 else
2803 return -EINVAL;
2804 break;
2805
2806 case SPEED_10:
2807 if (ecmd->duplex == DUPLEX_FULL)
2808 setting = SUPPORTED_10baseT_Full;
2809 else if (ecmd->duplex == DUPLEX_HALF)
2810 setting = SUPPORTED_10baseT_Half;
2811 else
2812 return -EINVAL;
2813 break;
2814 default:
2815 return -EINVAL;
2816 }
2817
2818 if ((setting & supported) == 0)
2819 return -EINVAL;
2820
2821 sky2->speed = ecmd->speed;
2822 sky2->duplex = ecmd->duplex;
2823 }
2824
2825 sky2->autoneg = ecmd->autoneg;
2826 sky2->advertising = ecmd->advertising;
2827
1b537565
SH		 2828 if (netif_running(dev))
2829 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2830
2831 return 0;
2832}
2833
2834static void sky2_get_drvinfo(struct net_device *dev,
2835 struct ethtool_drvinfo *info)
2836{
2837 struct sky2_port *sky2 = netdev_priv(dev);
2838
2839 strcpy(info->driver, DRV_NAME);
2840 strcpy(info->version, DRV_VERSION);
2841 strcpy(info->fw_version, "N/A");
2842 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2843}
2844
2845static const struct sky2_stat {
793b883e
SH		 2846 char name[ETH_GSTRING_LEN];
2847 u16 offset;
cd28ab6a
SH		 2848} sky2_stats[] = {
2849 { "tx_bytes", GM_TXO_OK_HI },
2850 { "rx_bytes", GM_RXO_OK_HI },
2851 { "tx_broadcast", GM_TXF_BC_OK },
2852 { "rx_broadcast", GM_RXF_BC_OK },
2853 { "tx_multicast", GM_TXF_MC_OK },
2854 { "rx_multicast", GM_RXF_MC_OK },
2855 { "tx_unicast", GM_TXF_UC_OK },
2856 { "rx_unicast", GM_RXF_UC_OK },
2857 { "tx_mac_pause", GM_TXF_MPAUSE },
2858 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2859 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2860 { "late_collision",GM_TXF_LAT_COL },
2861 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2862 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2863 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2864
d2604540 2865 { "rx_short", GM_RXF_SHT },
cd28ab6a 2866 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2867 { "rx_64_byte_packets", GM_RXF_64B },
2868 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2869 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2870 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2871 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2872 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2873 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2874 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2875 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2876 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2877 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2878
2879 { "tx_64_byte_packets", GM_TXF_64B },
2880 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2881 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2882 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2883 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2884 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2885 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2886 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2887};
2888
cd28ab6a
SH		 2889static u32 sky2_get_rx_csum(struct net_device *dev)
2890{
2891 struct sky2_port *sky2 = netdev_priv(dev);
2892
2893 return sky2->rx_csum;
2894}
2895
2896static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2897{
2898 struct sky2_port *sky2 = netdev_priv(dev);
2899
2900 sky2->rx_csum = data;
793b883e 2901
cd28ab6a
SH		 2902 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2903 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2904
2905 return 0;
2906}
2907
2908static u32 sky2_get_msglevel(struct net_device *netdev)
2909{
2910 struct sky2_port *sky2 = netdev_priv(netdev);
2911 return sky2->msg_enable;
2912}
2913
9a7ae0a9
SH		 2914static int sky2_nway_reset(struct net_device *dev)
2915{
2916 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2917
16ad91e1 2918 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2919 return -EINVAL;
2920
1b537565 2921 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2922
2923 return 0;
2924}
2925
793b883e 2926static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2927{
2928 struct sky2_hw *hw = sky2->hw;
2929 unsigned port = sky2->port;
2930 int i;
2931
2932 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2933 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2934 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2935 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2936
793b883e 2937 for (i = 2; i < count; i++)
cd28ab6a
SH		 2938 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2939}
2940
cd28ab6a
SH		 2941static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2942{
2943 struct sky2_port *sky2 = netdev_priv(netdev);
2944 sky2->msg_enable = value;
2945}
2946
2947static int sky2_get_stats_count(struct net_device *dev)
2948{
2949 return ARRAY_SIZE(sky2_stats);
2950}
2951
2952static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2953 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2954{
2955 struct sky2_port *sky2 = netdev_priv(dev);
2956
793b883e 2957 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2958}
2959
793b883e 2960static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2961{
2962 int i;
2963
2964 switch (stringset) {
2965 case ETH_SS_STATS:
2966 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2967 memcpy(data + i * ETH_GSTRING_LEN,
2968 sky2_stats[i].name, ETH_GSTRING_LEN);
2969 break;
2970 }
2971}
2972
cd28ab6a
SH		 2973static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2974{
2975 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2976 return &sky2->net_stats;
2977}
2978
2979static int sky2_set_mac_address(struct net_device *dev, void *p)
2980{
2981 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2982 struct sky2_hw *hw = sky2->hw;
2983 unsigned port = sky2->port;
2984 const struct sockaddr *addr = p;
cd28ab6a
SH		 2985
2986 if (!is_valid_ether_addr(addr->sa_data))
2987 return -EADDRNOTAVAIL;
2988
cd28ab6a 2989 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2990 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2991 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2992 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2993 dev->dev_addr, ETH_ALEN);
1b537565 2994
a8ab1ec0
SH		 2995 /* virtual address for data */
2996 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2997
2998 /* physical address: used for pause frames */
2999 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3000
3001 return 0;
cd28ab6a
SH		 3002}
3003
a052b52f
SH		 3004static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3005{
3006 u32 bit;
3007
3008 bit = ether_crc(ETH_ALEN, addr) & 63;
3009 filter[bit >> 3] |= 1 << (bit & 7);
3010}
3011
cd28ab6a
SH		 3012static void sky2_set_multicast(struct net_device *dev)
3013{
3014 struct sky2_port *sky2 = netdev_priv(dev);
3015 struct sky2_hw *hw = sky2->hw;
3016 unsigned port = sky2->port;
3017 struct dev_mc_list *list = dev->mc_list;
3018 u16 reg;
3019 u8 filter[8];
a052b52f
SH		 3020 int rx_pause;
3021 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3022
a052b52f 3023 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3024 memset(filter, 0, sizeof(filter));
3025
3026 reg = gma_read16(hw, port, GM_RX_CTRL);
3027 reg |= GM_RXCR_UCF_ENA;
3028
d571b694 3029 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3030 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3031 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3032 memset(filter, 0xff, sizeof(filter));
a052b52f 3033 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3034 reg &= ~GM_RXCR_MCF_ENA;
3035 else {
3036 int i;
3037 reg |= GM_RXCR_MCF_ENA;
3038
a052b52f
SH		 3039 if (rx_pause)
3040 sky2_add_filter(filter, pause_mc_addr);
3041
3042 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3043 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3044 }
3045
cd28ab6a 3046 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3047 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3048 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3049 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3050 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3051 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3052 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3053 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3054
3055 gma_write16(hw, port, GM_RX_CTRL, reg);
3056}
3057
3058/* Can have one global because blinking is controlled by
3059 * ethtool and that is always under RTNL mutex
3060 */
91c86df5 3061static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3062{
793b883e
SH		 3063 u16 pg;
3064
793b883e
SH		 3065 switch (hw->chip_id) {
3066 case CHIP_ID_YUKON_XL:
3067 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3068 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3069 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3070 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3071 PHY_M_LEDC_INIT_CTRL(7) |
3072 PHY_M_LEDC_STA1_CTRL(7) |
3073 PHY_M_LEDC_STA0_CTRL(7))
3074 : 0);
3075
3076 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3077 break;
3078
3079 default:
3080 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3081 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3082 on ? PHY_M_LED_ALL : 0);
793b883e 3083 }
cd28ab6a
SH		 3084}
3085
3086/* blink LED's for finding board */
3087static int sky2_phys_id(struct net_device *dev, u32 data)
3088{
3089 struct sky2_port *sky2 = netdev_priv(dev);
3090 struct sky2_hw *hw = sky2->hw;
3091 unsigned port = sky2->port;
793b883e 3092 u16 ledctrl, ledover = 0;
cd28ab6a 3093 long ms;
91c86df5 3094 int interrupted;
cd28ab6a
SH		 3095 int onoff = 1;
3096
793b883e 3097 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3098 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3099 else
3100 ms = data * 1000;
3101
3102 /* save initial values */
e07b1aa8 3103 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3104 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3105 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3106 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3107 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3108 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3109 } else {
3110 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3111 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3112 }
cd28ab6a 3113
91c86df5
SH		 3114 interrupted = 0;
3115 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3116 sky2_led(hw, port, onoff);
3117 onoff = !onoff;
3118
e07b1aa8 3119 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3120 interrupted = msleep_interruptible(250);
e07b1aa8 3121 spin_lock_bh(&sky2->phy_lock);
91c86df5 3122
cd28ab6a
SH		 3123 ms -= 250;
3124 }
3125
3126 /* resume regularly scheduled programming */
793b883e
SH		 3127 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3128 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3129 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3130 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3131 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3132 } else {
3133 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3134 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3135 }
e07b1aa8 3136 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3137
3138 return 0;
3139}
3140
3141static void sky2_get_pauseparam(struct net_device *dev,
3142 struct ethtool_pauseparam *ecmd)
3143{
3144 struct sky2_port *sky2 = netdev_priv(dev);
3145
16ad91e1
SH		 3146 switch (sky2->flow_mode) {
3147 case FC_NONE:
3148 ecmd->tx_pause = ecmd->rx_pause = 0;
3149 break;
3150 case FC_TX:
3151 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3152 break;
3153 case FC_RX:
3154 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3155 break;
3156 case FC_BOTH:
3157 ecmd->tx_pause = ecmd->rx_pause = 1;
3158 }
3159
cd28ab6a
SH		 3160 ecmd->autoneg = sky2->autoneg;
3161}
3162
3163static int sky2_set_pauseparam(struct net_device *dev,
3164 struct ethtool_pauseparam *ecmd)
3165{
3166 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3167
3168 sky2->autoneg = ecmd->autoneg;
16ad91e1 3169 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3170
16ad91e1
SH		 3171 if (netif_running(dev))
3172 sky2_phy_reinit(sky2);
cd28ab6a 3173
2eaba1a2 3174 return 0;
cd28ab6a
SH		 3175}
3176
fb17358f
SH		 3177static int sky2_get_coalesce(struct net_device *dev,
3178 struct ethtool_coalesce *ecmd)
3179{
3180 struct sky2_port *sky2 = netdev_priv(dev);
3181 struct sky2_hw *hw = sky2->hw;
3182
3183 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3184 ecmd->tx_coalesce_usecs = 0;
3185 else {
3186 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3187 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3188 }
3189 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3190
3191 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3192 ecmd->rx_coalesce_usecs = 0;
3193 else {
3194 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3195 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3196 }
3197 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3198
3199 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3200 ecmd->rx_coalesce_usecs_irq = 0;
3201 else {
3202 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3203 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3204 }
3205
3206 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3207
3208 return 0;
3209}
3210
3211/* Note: this affect both ports */
3212static int sky2_set_coalesce(struct net_device *dev,
3213 struct ethtool_coalesce *ecmd)
3214{
3215 struct sky2_port *sky2 = netdev_priv(dev);
3216 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3217 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3218
77b3d6a2
SH		 3219 if (ecmd->tx_coalesce_usecs > tmax ||
3220 ecmd->rx_coalesce_usecs > tmax ||
3221 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3222 return -EINVAL;
3223
ff81fbbe 3224 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3225 return -EINVAL;
ff81fbbe 3226 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3227 return -EINVAL;
ff81fbbe 3228 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3229 return -EINVAL;
3230
3231 if (ecmd->tx_coalesce_usecs == 0)
3232 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3233 else {
3234 sky2_write32(hw, STAT_TX_TIMER_INI,
3235 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3236 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3237 }
3238 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3239
3240 if (ecmd->rx_coalesce_usecs == 0)
3241 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3242 else {
3243 sky2_write32(hw, STAT_LEV_TIMER_INI,
3244 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3245 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3246 }
3247 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3248
3249 if (ecmd->rx_coalesce_usecs_irq == 0)
3250 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3251 else {
d28d4870 3252 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3253 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3254 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3255 }
3256 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3257 return 0;
3258}
3259
793b883e
SH		 3260static void sky2_get_ringparam(struct net_device *dev,
3261 struct ethtool_ringparam *ering)
3262{
3263 struct sky2_port *sky2 = netdev_priv(dev);
3264
3265 ering->rx_max_pending = RX_MAX_PENDING;
3266 ering->rx_mini_max_pending = 0;
3267 ering->rx_jumbo_max_pending = 0;
3268 ering->tx_max_pending = TX_RING_SIZE - 1;
3269
3270 ering->rx_pending = sky2->rx_pending;
3271 ering->rx_mini_pending = 0;
3272 ering->rx_jumbo_pending = 0;
3273 ering->tx_pending = sky2->tx_pending;
3274}
3275
3276static int sky2_set_ringparam(struct net_device *dev,
3277 struct ethtool_ringparam *ering)
3278{
3279 struct sky2_port *sky2 = netdev_priv(dev);
3280 int err = 0;
3281
3282 if (ering->rx_pending > RX_MAX_PENDING ||
3283 ering->rx_pending < 8 ||
3284 ering->tx_pending < MAX_SKB_TX_LE ||
3285 ering->tx_pending > TX_RING_SIZE - 1)
3286 return -EINVAL;
3287
3288 if (netif_running(dev))
3289 sky2_down(dev);
3290
3291 sky2->rx_pending = ering->rx_pending;
3292 sky2->tx_pending = ering->tx_pending;
3293
1b537565 3294 if (netif_running(dev)) {
793b883e 3295 err = sky2_up(dev);
1b537565
SH		 3296 if (err)
3297 dev_close(dev);
6ed995bb
SH		 3298 else
3299 sky2_set_multicast(dev);
1b537565 3300 }
793b883e
SH		 3301
3302 return err;
3303}
3304
793b883e
SH		 3305static int sky2_get_regs_len(struct net_device *dev)
3306{
6e4cbb34 3307 return 0x4000;
793b883e
SH		 3308}
3309
3310/*
3311 * Returns copy of control register region
6e4cbb34 3312 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3313 */
3314static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3315 void *p)
3316{
3317 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3318 const void __iomem *io = sky2->hw->regs;
793b883e 3319
6e4cbb34 3320 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3321 regs->version = 1;
6e4cbb34 3322 memset(p, 0, regs->len);
793b883e 3323
6e4cbb34
SH		 3324 memcpy_fromio(p, io, B3_RAM_ADDR);
3325
3326 memcpy_fromio(p + B3_RI_WTO_R1,
3327 io + B3_RI_WTO_R1,
3328 regs->len - B3_RI_WTO_R1);
793b883e 3329}
cd28ab6a 3330
7282d491 3331static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3332 .get_settings = sky2_get_settings,
3333 .set_settings = sky2_set_settings,
e3173832
SH		 3334 .get_drvinfo = sky2_get_drvinfo,
3335 .get_wol = sky2_get_wol,
3336 .set_wol = sky2_set_wol,
793b883e
SH		 3337 .get_msglevel = sky2_get_msglevel,
3338 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3339 .nway_reset = sky2_nway_reset,
793b883e
SH		 3340 .get_regs_len = sky2_get_regs_len,
3341 .get_regs = sky2_get_regs,
3342 .get_link = ethtool_op_get_link,
3343 .get_sg = ethtool_op_get_sg,
3344 .set_sg = ethtool_op_set_sg,
3345 .get_tx_csum = ethtool_op_get_tx_csum,
3346 .set_tx_csum = ethtool_op_set_tx_csum,
3347 .get_tso = ethtool_op_get_tso,
3348 .set_tso = ethtool_op_set_tso,
3349 .get_rx_csum = sky2_get_rx_csum,
3350 .set_rx_csum = sky2_set_rx_csum,
3351 .get_strings = sky2_get_strings,
fb17358f
SH		 3352 .get_coalesce = sky2_get_coalesce,
3353 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3354 .get_ringparam = sky2_get_ringparam,
3355 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3356 .get_pauseparam = sky2_get_pauseparam,
3357 .set_pauseparam = sky2_set_pauseparam,
793b883e 3358 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3359 .get_stats_count = sky2_get_stats_count,
3360 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3361 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3362};
3363
3364/* Initialize network device */
3365static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3366 unsigned port,
3367 int highmem, int wol)
cd28ab6a
SH		 3368{
3369 struct sky2_port *sky2;
3370 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3371
3372 if (!dev) {
b02a9258 3373 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3374 return NULL;
3375 }
3376
3377 SET_MODULE_OWNER(dev);
3378 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3379 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3380 dev->open = sky2_up;
3381 dev->stop = sky2_down;
ef743d33 3382 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3383 dev->hard_start_xmit = sky2_xmit_frame;
3384 dev->get_stats = sky2_get_stats;
3385 dev->set_multicast_list = sky2_set_multicast;
3386 dev->set_mac_address = sky2_set_mac_address;
3387 dev->change_mtu = sky2_change_mtu;
3388 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3389 dev->tx_timeout = sky2_tx_timeout;
3390 dev->watchdog_timeo = TX_WATCHDOG;
3391 if (port == 0)
3392 dev->poll = sky2_poll;
3393 dev->weight = NAPI_WEIGHT;
3394#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3395 /* Network console (only works on port 0)
3396 * because netpoll makes assumptions about NAPI
3397 */
3398 if (port == 0)
3399 dev->poll_controller = sky2_netpoll;
cd28ab6a 3400#endif
cd28ab6a
SH		 3401
3402 sky2 = netdev_priv(dev);
3403 sky2->netdev = dev;
3404 sky2->hw = hw;
3405 sky2->msg_enable = netif_msg_init(debug, default_msg);
3406
cd28ab6a
SH		 3407 /* Auto speed and flow control */
3408 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3409 sky2->flow_mode = FC_BOTH;
3410
cd28ab6a
SH		 3411 sky2->duplex = -1;
3412 sky2->speed = -1;
3413 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3414 sky2->rx_csum = 1;
e3173832 3415 sky2->wol = wol;
75d070c5 3416
e07b1aa8 3417 spin_lock_init(&sky2->phy_lock);
793b883e 3418 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3419 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3420
3421 hw->dev[port] = dev;
3422
3423 sky2->port = port;
3424
4a50a876 3425 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3426 if (highmem)
3427 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3428
d1f13708
SH		 3429#ifdef SKY2_VLAN_TAG_USED
3430 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3431 dev->vlan_rx_register = sky2_vlan_rx_register;
3432 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3433#endif
3434
cd28ab6a 3435 /* read the mac address */
793b883e 3436 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3437 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3438
3439 /* device is off until link detection */
3440 netif_carrier_off(dev);
3441 netif_stop_queue(dev);
3442
3443 return dev;
3444}
3445
28bd181a 3446static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3447{
3448 const struct sky2_port *sky2 = netdev_priv(dev);
3449
3450 if (netif_msg_probe(sky2))
3451 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3452 dev->name,
3453 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3454 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3455}
3456
fb2690a9 3457/* Handle software interrupt used during MSI test */
7d12e780 3458static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3459{
3460 struct sky2_hw *hw = dev_id;
3461 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3462
3463 if (status == 0)
3464 return IRQ_NONE;
3465
3466 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3467 hw->msi = 1;
fb2690a9
SH		 3468 wake_up(&hw->msi_wait);
3469 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3470 }
3471 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3472
3473 return IRQ_HANDLED;
3474}
3475
3476/* Test interrupt path by forcing a a software IRQ */
3477static int __devinit sky2_test_msi(struct sky2_hw *hw)
3478{
3479 struct pci_dev *pdev = hw->pdev;
3480 int err;
3481
bb507fe1
SH		 3482 init_waitqueue_head (&hw->msi_wait);
3483
fb2690a9
SH		 3484 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3485
b0a20ded 3486 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3487 if (err) {
b02a9258 3488 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3489 return err;
3490 }
3491
fb2690a9 3492 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3493 sky2_read8(hw, B0_CTST);
fb2690a9 3494
b0a20ded 3495 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3496
b0a20ded 3497 if (!hw->msi) {
fb2690a9 3498 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3499 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3500 "switching to INTx mode.\n");
fb2690a9
SH		 3501
3502 err = -EOPNOTSUPP;
3503 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3504 }
3505
3506 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3507 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3508
3509 free_irq(pdev->irq, hw);
3510
3511 return err;
3512}
3513
e3173832
SH		 3514static int __devinit pci_wake_enabled(struct pci_dev *dev)
3515{
3516 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3517 u16 value;
3518
3519 if (!pm)
3520 return 0;
3521 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3522 return 0;
3523 return value & PCI_PM_CTRL_PME_ENABLE;
3524}
3525
cd28ab6a
SH		 3526static int __devinit sky2_probe(struct pci_dev *pdev,
3527 const struct pci_device_id *ent)
3528{
7f60c64b 3529 struct net_device *dev;
cd28ab6a 3530 struct sky2_hw *hw;
e3173832 3531 int err, using_dac = 0, wol_default;
cd28ab6a 3532
793b883e
SH		 3533 err = pci_enable_device(pdev);
3534 if (err) {
b02a9258 3535 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3536 goto err_out;
3537 }
3538
793b883e
SH		 3539 err = pci_request_regions(pdev, DRV_NAME);
3540 if (err) {
b02a9258 3541 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
793b883e 3542 goto err_out;
cd28ab6a
SH		 3543 }
3544
3545 pci_set_master(pdev);
3546
d1f3d4dd
SH		 3547 if (sizeof(dma_addr_t) > sizeof(u32) &&
3548 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3549 using_dac = 1;
3550 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3551 if (err < 0) {
b02a9258
SH		 3552 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3553 "for consistent allocations\n");
d1f3d4dd
SH		 3554 goto err_out_free_regions;
3555 }
d1f3d4dd 3556 } else {
cd28ab6a
SH		 3557 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3558 if (err) {
b02a9258 3559 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3560 goto err_out_free_regions;
3561 }
3562 }
d1f3d4dd 3563
e3173832
SH		 3564 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3565
cd28ab6a 3566 err = -ENOMEM;
6aad85d6 3567 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3568 if (!hw) {
b02a9258 3569 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3570 goto err_out_free_regions;
3571 }
3572
cd28ab6a 3573 hw->pdev = pdev;
cd28ab6a
SH		 3574
3575 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3576 if (!hw->regs) {
b02a9258 3577 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3578 goto err_out_free_hw;
3579 }
3580
56a645cc 3581#ifdef __BIG_ENDIAN
f65b138c
SH		 3582 /* The sk98lin vendor driver uses hardware byte swapping but
3583 * this driver uses software swapping.
3584 */
56a645cc
SH		 3585 {
3586 u32 reg;
56a645cc 3587 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3588 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3589 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3590 }
3591#endif
3592
08c06d8a
SH		 3593 /* ring for status responses */
3594 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3595 &hw->st_dma);
3596 if (!hw->st_le)
3597 goto err_out_iounmap;
3598
e3173832 3599 err = sky2_init(hw);
cd28ab6a 3600 if (err)
793b883e 3601 goto err_out_iounmap;
cd28ab6a 3602
b02a9258 3603 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3604 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3605 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3606 hw->chip_id, hw->chip_rev);
cd28ab6a 3607
e3173832
SH		 3608 sky2_reset(hw);
3609
3610 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3611 if (!dev) {
3612 err = -ENOMEM;
cd28ab6a 3613 goto err_out_free_pci;
7f60c64b 3614 }
cd28ab6a 3615
9fa1b1f3
SH		 3616 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3617 err = sky2_test_msi(hw);
3618 if (err == -EOPNOTSUPP)
3619 pci_disable_msi(pdev);
3620 else if (err)
3621 goto err_out_free_netdev;
3622 }
3623
793b883e
SH		 3624 err = register_netdev(dev);
3625 if (err) {
b02a9258 3626 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 3627 goto err_out_free_netdev;
3628 }
3629
b0a20ded
SH		 3630 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3631 dev->name, hw);
9fa1b1f3 3632 if (err) {
b02a9258 3633 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 3634 goto err_out_unregister;
3635 }
3636 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3637
cd28ab6a
SH		 3638 sky2_show_addr(dev);
3639
7f60c64b 3640 if (hw->ports > 1) {
3641 struct net_device *dev1;
3642
e3173832 3643 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 3644 if (!dev1)
3645 dev_warn(&pdev->dev, "allocation for second device failed\n");
3646 else if ((err = register_netdev(dev1))) {
3647 dev_warn(&pdev->dev,
3648 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 3649 hw->dev[1] = NULL;
3650 free_netdev(dev1);
b02a9258
SH		 3651 } else
3652 sky2_show_addr(dev1);
cd28ab6a
SH		 3653 }
3654
01bd7564 3655 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
81906791
SH		 3656 INIT_WORK(&hw->restart_work, sky2_restart);
3657
eb35cf60 3658 sky2_idle_start(hw);
d27ed387 3659
793b883e
SH		 3660 pci_set_drvdata(pdev, hw);
3661
cd28ab6a
SH		 3662 return 0;
3663
793b883e 3664err_out_unregister:
b0a20ded
SH		 3665 if (hw->msi)
3666 pci_disable_msi(pdev);
793b883e 3667 unregister_netdev(dev);
cd28ab6a
SH		 3668err_out_free_netdev:
3669 free_netdev(dev);
cd28ab6a 3670err_out_free_pci:
793b883e 3671 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3672 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3673err_out_iounmap:
3674 iounmap(hw->regs);
3675err_out_free_hw:
3676 kfree(hw);
3677err_out_free_regions:
3678 pci_release_regions(pdev);
cd28ab6a 3679 pci_disable_device(pdev);
cd28ab6a
SH		 3680err_out:
3681 return err;
3682}
3683
3684static void __devexit sky2_remove(struct pci_dev *pdev)
3685{
793b883e 3686 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3687 struct net_device *dev0, *dev1;
3688
793b883e 3689 if (!hw)
cd28ab6a
SH		 3690 return;
3691
d27ed387
SH		 3692 del_timer_sync(&hw->idle_timer);
3693
81906791
SH		 3694 flush_scheduled_work();
3695
d27ed387 3696 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3697 synchronize_irq(hw->pdev->irq);
3698
cd28ab6a 3699 dev0 = hw->dev[0];
793b883e
SH		 3700 dev1 = hw->dev[1];
3701 if (dev1)
3702 unregister_netdev(dev1);
cd28ab6a
SH		 3703 unregister_netdev(dev0);
3704
ae306cca
SH		 3705 sky2_power_aux(hw);
3706
cd28ab6a 3707 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3708 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3709 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3710
3711 free_irq(pdev->irq, hw);
b0a20ded
SH		 3712 if (hw->msi)
3713 pci_disable_msi(pdev);
793b883e 3714 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3715 pci_release_regions(pdev);
3716 pci_disable_device(pdev);
793b883e 3717
cd28ab6a
SH		 3718 if (dev1)
3719 free_netdev(dev1);
3720 free_netdev(dev0);
3721 iounmap(hw->regs);
3722 kfree(hw);
5afa0a9c 3723
cd28ab6a
SH		 3724 pci_set_drvdata(pdev, NULL);
3725}
3726
3727#ifdef CONFIG_PM
3728static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3729{
793b883e 3730 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 3731 int i, wol = 0;
cd28ab6a 3732
eb35cf60 3733 del_timer_sync(&hw->idle_timer);
6a5706b9 3734 netif_poll_disable(hw->dev[0]);
eb35cf60 3735
f05267e7 3736 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3737 struct net_device *dev = hw->dev[i];
e3173832 3738 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3739
e3173832 3740 if (netif_running(dev))
5afa0a9c 3741 sky2_down(dev);
e3173832
SH		 3742
3743 if (sky2->wol)
3744 sky2_wol_init(sky2);
3745
3746 wol |= sky2->wol;
cd28ab6a
SH		 3747 }
3748
8ab8fca2 3749 sky2_write32(hw, B0_IMSK, 0);
ae306cca 3750 sky2_power_aux(hw);
e3173832 3751
d374c1c1 3752 pci_save_state(pdev);
e3173832 3753 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 3754 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3755
2ccc99b7 3756 return 0;
cd28ab6a
SH		 3757}
3758
3759static int sky2_resume(struct pci_dev *pdev)
3760{
793b883e 3761 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3762 int i, err;
cd28ab6a 3763
ae306cca
SH		 3764 err = pci_set_power_state(pdev, PCI_D0);
3765 if (err)
3766 goto out;
3767
3768 err = pci_restore_state(pdev);
3769 if (err)
3770 goto out;
3771
cd28ab6a 3772 pci_enable_wake(pdev, PCI_D0, 0);
e3173832 3773 sky2_reset(hw);
cd28ab6a 3774
8ab8fca2
SH		 3775 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3776
f05267e7 3777 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3778 struct net_device *dev = hw->dev[i];
6a5706b9 3779 if (netif_running(dev)) {
08c06d8a
SH		 3780 err = sky2_up(dev);
3781 if (err) {
3782 printk(KERN_ERR PFX "%s: could not up: %d\n",
3783 dev->name, err);
3784 dev_close(dev);
eb35cf60 3785 goto out;
5afa0a9c 3786 }
cd28ab6a
SH		 3787 }
3788 }
eb35cf60 3789
6a5706b9 3790 netif_poll_enable(hw->dev[0]);
eb35cf60 3791 sky2_idle_start(hw);
ae306cca 3792 return 0;
08c06d8a 3793out:
b02a9258 3794 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 3795 pci_disable_device(pdev);
08c06d8a 3796 return err;
cd28ab6a
SH		 3797}
3798#endif
3799
e3173832
SH		 3800static void sky2_shutdown(struct pci_dev *pdev)
3801{
3802 struct sky2_hw *hw = pci_get_drvdata(pdev);
3803 int i, wol = 0;
3804
3805 del_timer_sync(&hw->idle_timer);
3806 netif_poll_disable(hw->dev[0]);
3807
3808 for (i = 0; i < hw->ports; i++) {
3809 struct net_device *dev = hw->dev[i];
3810 struct sky2_port *sky2 = netdev_priv(dev);
3811
3812 if (sky2->wol) {
3813 wol = 1;
3814 sky2_wol_init(sky2);
3815 }
3816 }
3817
3818 if (wol)
3819 sky2_power_aux(hw);
3820
3821 pci_enable_wake(pdev, PCI_D3hot, wol);
3822 pci_enable_wake(pdev, PCI_D3cold, wol);
3823
3824 pci_disable_device(pdev);
3825 pci_set_power_state(pdev, PCI_D3hot);
3826
3827}
3828
cd28ab6a 3829static struct pci_driver sky2_driver = {
793b883e
SH		 3830 .name = DRV_NAME,
3831 .id_table = sky2_id_table,
3832 .probe = sky2_probe,
3833 .remove = __devexit_p(sky2_remove),
cd28ab6a 3834#ifdef CONFIG_PM
793b883e
SH		 3835 .suspend = sky2_suspend,
3836 .resume = sky2_resume,
cd28ab6a 3837#endif
e3173832 3838 .shutdown = sky2_shutdown,
cd28ab6a
SH		 3839};
3840
3841static int __init sky2_init_module(void)
3842{
50241c4c 3843 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3844}
3845
3846static void __exit sky2_cleanup_module(void)
3847{
3848 pci_unregister_driver(&sky2_driver);
3849}
3850
3851module_init(sky2_init_module);
3852module_exit(sky2_cleanup_module);
3853
3854MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 3855MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 3856MODULE_LICENSE("GPL");
5f4f9dc1 3857MODULE_VERSION(DRV_VERSION);
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