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sky2: Yukon Extreme support
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
ef743d33 41#include <linux/mii.h>
cd28ab6a
SH		 42
43#include <asm/irq.h>
44
d1f13708
SH		 45#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46#define SKY2_VLAN_TAG_USED 1
47#endif
48
cd28ab6a
SH		 49#include "sky2.h"
50
51#define DRV_NAME "sky2"
285e6ddd 52#define DRV_VERSION "1.11.1"
cd28ab6a
SH		 53#define PFX DRV_NAME " "
54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
14d0263f 58 * similar to Tigon3.
cd28ab6a
SH		 59 */
60
14d0263f 61#define RX_LE_SIZE 1024
cd28ab6a 62#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 63#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 64#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 65#define RX_SKB_ALIGN 8
22e11703 66#define RX_BUF_WRITE 16
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
cb5d9547
SH		 79#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80
cd28ab6a 81static const u32 default_msg =
793b883e
SH		 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 85
793b883e 86static int debug = -1; /* defaults above */
cd28ab6a
SH		 87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
14d0263f 90static int copybreak __read_mostly = 128;
bdb5c58e
SH		 91module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
fb2690a9
SH		 94static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
e561a83b 98static int idle_timeout = 0;
01bd7564 99module_param(idle_timeout, int, 0);
e561a83b 100MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
cd28ab6a
SH		 129 { 0 }
130};
793b883e 131
cd28ab6a
SH		 132MODULE_DEVICE_TABLE(pci, sky2_id_table);
133
134/* Avoid conditionals by using array */
135static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
136static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 137static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 138
92f965e8
SH		 139/* This driver supports yukon2 chipset only */
140static const char *yukon2_name[] = {
141 "XL", /* 0xb3 */
142 "EC Ultra", /* 0xb4 */
93745494 143 "Extreme", /* 0xb5 */
92f965e8
SH		 144 "EC", /* 0xb6 */
145 "FE", /* 0xb7 */
793b883e
SH		 146};
147
793b883e 148/* Access to external PHY */
ef743d33 149static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 150{
151 int i;
152
153 gma_write16(hw, port, GM_SMI_DATA, val);
154 gma_write16(hw, port, GM_SMI_CTRL,
155 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
156
157 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 158 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 159 return 0;
793b883e 160 udelay(1);
cd28ab6a 161 }
ef743d33 162
793b883e 163 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 164 return -ETIMEDOUT;
cd28ab6a
SH		 165}
166
ef743d33 167static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 168{
169 int i;
170
793b883e 171 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 172 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
173
174 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 175 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
176 *val = gma_read16(hw, port, GM_SMI_DATA);
177 return 0;
178 }
179
793b883e 180 udelay(1);
cd28ab6a
SH		 181 }
182
ef743d33
SH		 183 return -ETIMEDOUT;
184}
185
186static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
187{
188 u16 v;
189
190 if (__gm_phy_read(hw, port, reg, &v) != 0)
191 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
192 return v;
cd28ab6a
SH		 193}
194
5afa0a9c 195
ae306cca
SH		 196static void sky2_power_on(struct sky2_hw *hw)
197{
198 /* switch power to VCC (WA for VAUX problem) */
199 sky2_write8(hw, B0_POWER_CTRL,
200 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 201
ae306cca
SH		 202 /* disable Core Clock Division, */
203 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 204
ae306cca
SH		 205 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
206 /* enable bits are inverted */
207 sky2_write8(hw, B2_Y2_CLK_GATE,
208 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
209 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
210 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
211 else
212 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 213
93745494 214 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
ae306cca 215 u32 reg1;
5afa0a9c 216
ae306cca
SH		 217 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
218 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
219 reg1 &= P_ASPM_CONTROL_MSK;
220 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
221 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
5afa0a9c 222 }
ae306cca 223}
5afa0a9c 224
ae306cca
SH		 225static void sky2_power_aux(struct sky2_hw *hw)
226{
227 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
228 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
229 else
230 /* enable bits are inverted */
231 sky2_write8(hw, B2_Y2_CLK_GATE,
232 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
233 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
234 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
235
236 /* switch power to VAUX */
237 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
238 sky2_write8(hw, B0_POWER_CTRL,
239 (PC_VAUX_ENA | PC_VCC_ENA |
240 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 241}
242
d3bcfbeb 243static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 244{
245 u16 reg;
246
247 /* disable all GMAC IRQ's */
248 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
249 /* disable PHY IRQs */
250 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 251
cd28ab6a
SH		 252 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
253 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
254 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
255 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
256
257 reg = gma_read16(hw, port, GM_RX_CTRL);
258 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
259 gma_write16(hw, port, GM_RX_CTRL, reg);
260}
261
16ad91e1
SH		 262/* flow control to advertise bits */
263static const u16 copper_fc_adv[] = {
264 [FC_NONE] = 0,
265 [FC_TX] = PHY_M_AN_ASP,
266 [FC_RX] = PHY_M_AN_PC,
267 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
268};
269
270/* flow control to advertise bits when using 1000BaseX */
271static const u16 fiber_fc_adv[] = {
272 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
273 [FC_TX] = PHY_M_P_ASYM_MD_X,
274 [FC_RX] = PHY_M_P_SYM_MD_X,
275 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
276};
277
278/* flow control to GMA disable bits */
279static const u16 gm_fc_disable[] = {
280 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
281 [FC_TX] = GM_GPCR_FC_RX_DIS,
282 [FC_RX] = GM_GPCR_FC_TX_DIS,
283 [FC_BOTH] = 0,
284};
285
286
cd28ab6a
SH		 287static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
288{
289 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 290 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 291
93745494
SH		 292 if (sky2->autoneg == AUTONEG_ENABLE
293 && !(hw->chip_id == CHIP_ID_YUKON_XL
294 || hw->chip_id == CHIP_ID_YUKON_EC_U
295 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 296 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
297
298 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 299 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 300 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
301
302 if (hw->chip_id == CHIP_ID_YUKON_EC)
303 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
304 else
305 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
306
307 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
308 }
309
310 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 311 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 312 if (hw->chip_id == CHIP_ID_YUKON_FE) {
313 /* enable automatic crossover */
314 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
315 } else {
316 /* disable energy detect */
317 ctrl &= ~PHY_M_PC_EN_DET_MSK;
318
319 /* enable automatic crossover */
320 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
321
93745494
SH		 322 if (sky2->autoneg == AUTONEG_ENABLE
323 && (hw->chip_id == CHIP_ID_YUKON_XL
324 || hw->chip_id == CHIP_ID_YUKON_EC_U
325 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 326 ctrl &= ~PHY_M_PC_DSC_MSK;
327 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
328 }
329 }
cd28ab6a
SH		 330 } else {
331 /* workaround for deviation #4.88 (CRC errors) */
332 /* disable Automatic Crossover */
333
334 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 335 }
cd28ab6a 336
b89165f2
SH		 337 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
338
339 /* special setup for PHY 88E1112 Fiber */
340 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
341 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 342
b89165f2
SH		 343 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
344 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
345 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
346 ctrl &= ~PHY_M_MAC_MD_MSK;
347 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
348 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
349
350 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 351 /* select page 1 to access Fiber registers */
352 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 353
354 /* for SFP-module set SIGDET polarity to low */
355 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
356 ctrl |= PHY_M_FIB_SIGD_POL;
357 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 358 }
b89165f2
SH		 359
360 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 361 }
362
7800fddc 363 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 364 ct1000 = 0;
365 adv = PHY_AN_CSMA;
2eaba1a2 366 reg = 0;
cd28ab6a
SH		 367
368 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 369 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 370 if (sky2->advertising & ADVERTISED_1000baseT_Full)
371 ct1000 |= PHY_M_1000C_AFD;
372 if (sky2->advertising & ADVERTISED_1000baseT_Half)
373 ct1000 |= PHY_M_1000C_AHD;
374 if (sky2->advertising & ADVERTISED_100baseT_Full)
375 adv |= PHY_M_AN_100_FD;
376 if (sky2->advertising & ADVERTISED_100baseT_Half)
377 adv |= PHY_M_AN_100_HD;
378 if (sky2->advertising & ADVERTISED_10baseT_Full)
379 adv |= PHY_M_AN_10_FD;
380 if (sky2->advertising & ADVERTISED_10baseT_Half)
381 adv |= PHY_M_AN_10_HD;
709c6e7b 382
16ad91e1 383 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 384 } else { /* special defines for FIBER (88E1040S only) */
385 if (sky2->advertising & ADVERTISED_1000baseT_Full)
386 adv |= PHY_M_AN_1000X_AFD;
387 if (sky2->advertising & ADVERTISED_1000baseT_Half)
388 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 389
16ad91e1 390 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 391 }
cd28ab6a
SH		 392
393 /* Restart Auto-negotiation */
394 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
395 } else {
396 /* forced speed/duplex settings */
397 ct1000 = PHY_M_1000C_MSE;
398
2eaba1a2
SH		 399 /* Disable auto update for duplex flow control and speed */
400 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 401
402 switch (sky2->speed) {
403 case SPEED_1000:
404 ctrl |= PHY_CT_SP1000;
2eaba1a2 405 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 406 break;
407 case SPEED_100:
408 ctrl |= PHY_CT_SP100;
2eaba1a2 409 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 410 break;
411 }
412
2eaba1a2
SH		 413 if (sky2->duplex == DUPLEX_FULL) {
414 reg |= GM_GPCR_DUP_FULL;
415 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 416 } else if (sky2->speed < SPEED_1000)
417 sky2->flow_mode = FC_NONE;
2eaba1a2 418
2eaba1a2 419
16ad91e1 420 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 421
422 /* Forward pause packets to GMAC? */
16ad91e1 423 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 424 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
425 else
426 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 427 }
428
2eaba1a2
SH		 429 gma_write16(hw, port, GM_GP_CTRL, reg);
430
cd28ab6a
SH		 431 if (hw->chip_id != CHIP_ID_YUKON_FE)
432 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
433
434 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
435 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
436
437 /* Setup Phy LED's */
438 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
439 ledover = 0;
440
441 switch (hw->chip_id) {
442 case CHIP_ID_YUKON_FE:
443 /* on 88E3082 these bits are at 11..9 (shifted left) */
444 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
445
446 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
447
448 /* delete ACT LED control bits */
449 ctrl &= ~PHY_M_FELP_LED1_MSK;
450 /* change ACT LED control to blink mode */
451 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
452 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
453 break;
454
455 case CHIP_ID_YUKON_XL:
793b883e 456 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 457
458 /* select page 3 to access LED control register */
459 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
460
461 /* set LED Function Control register */
ed6d32c7
SH		 462 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
463 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
464 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
465 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
466 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 467
468 /* set Polarity Control register */
469 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 470 (PHY_M_POLC_LS1_P_MIX(4) |
471 PHY_M_POLC_IS0_P_MIX(4) |
472 PHY_M_POLC_LOS_CTRL(2) |
473 PHY_M_POLC_INIT_CTRL(2) |
474 PHY_M_POLC_STA1_CTRL(2) |
475 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 476
477 /* restore page register */
793b883e 478 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 479 break;
93745494 480
ed6d32c7 481 case CHIP_ID_YUKON_EC_U:
93745494 482 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 483 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
484
485 /* select page 3 to access LED control register */
486 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
487
488 /* set LED Function Control register */
489 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
490 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
491 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
492 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
493 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
494
495 /* set Blink Rate in LED Timer Control Register */
496 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
497 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
498 /* restore page register */
499 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
500 break;
cd28ab6a
SH		 501
502 default:
503 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
504 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
505 /* turn off the Rx LED (LED_RX) */
0efdf262 506 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 507 }
508
ed6d32c7 509 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 510 /* apply fixes in PHY AFE */
ed6d32c7
SH		 511 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
512 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
513
977bdf06 514 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 515 gm_phy_write(hw, port, 0x18, 0xaa99);
516 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 517
977bdf06 518 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 519 gm_phy_write(hw, port, 0x18, 0xa204);
520 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 521
522 /* set page register to 0 */
ed6d32c7 523 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
93745494 524 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 525 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 526
977bdf06
SH		 527 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
528 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 529 ledover |= PHY_M_LED_MO_100;
977bdf06 530 }
cd28ab6a 531
977bdf06
SH		 532 if (ledover)
533 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
534
535 }
2eaba1a2 536
d571b694 537 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 538 if (sky2->autoneg == AUTONEG_ENABLE)
539 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
540 else
541 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
542}
543
d3bcfbeb
SH		 544static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
545{
546 u32 reg1;
547 static const u32 phy_power[]
548 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
549
550 /* looks like this XL is back asswards .. */
551 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
552 onoff = !onoff;
553
aed2cec4 554 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 555 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 556 if (onoff)
557 /* Turn off phy power saving */
558 reg1 &= ~phy_power[port];
559 else
560 reg1 |= phy_power[port];
561
562 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 563 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 564 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 565 udelay(100);
566}
567
1b537565
SH		 568/* Force a renegotiation */
569static void sky2_phy_reinit(struct sky2_port *sky2)
570{
e07b1aa8 571 spin_lock_bh(&sky2->phy_lock);
1b537565 572 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 573 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 574}
575
e3173832
SH		 576/* Put device in state to listen for Wake On Lan */
577static void sky2_wol_init(struct sky2_port *sky2)
578{
579 struct sky2_hw *hw = sky2->hw;
580 unsigned port = sky2->port;
581 enum flow_control save_mode;
582 u16 ctrl;
583 u32 reg1;
584
585 /* Bring hardware out of reset */
586 sky2_write16(hw, B0_CTST, CS_RST_CLR);
587 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
588
589 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
590 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
591
592 /* Force to 10/100
593 * sky2_reset will re-enable on resume
594 */
595 save_mode = sky2->flow_mode;
596 ctrl = sky2->advertising;
597
598 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
599 sky2->flow_mode = FC_NONE;
600 sky2_phy_power(hw, port, 1);
601 sky2_phy_reinit(sky2);
602
603 sky2->flow_mode = save_mode;
604 sky2->advertising = ctrl;
605
606 /* Set GMAC to no flow control and auto update for speed/duplex */
607 gma_write16(hw, port, GM_GP_CTRL,
608 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
609 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
610
611 /* Set WOL address */
612 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
613 sky2->netdev->dev_addr, ETH_ALEN);
614
615 /* Turn on appropriate WOL control bits */
616 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
617 ctrl = 0;
618 if (sky2->wol & WAKE_PHY)
619 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
620 else
621 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
622
623 if (sky2->wol & WAKE_MAGIC)
624 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
625 else
626 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
627
628 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
629 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
630
631 /* Turn on legacy PCI-Express PME mode */
632 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
633 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
634 reg1 |= PCI_Y2_PME_LEGACY;
635 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
636 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
637
638 /* block receiver */
639 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
640
641}
642
cd28ab6a
SH		 643static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
644{
645 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
646 u16 reg;
647 int i;
648 const u8 *addr = hw->dev[port]->dev_addr;
649
42eeea01
SH		 650 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
651 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 652
653 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
654
793b883e 655 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 656 /* WA DEV_472 -- looks like crossed wires on port 2 */
657 /* clear GMAC 1 Control reset */
658 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
659 do {
660 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
661 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
662 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
663 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
664 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
665 }
666
793b883e 667 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 668
2eaba1a2
SH		 669 /* Enable Transmit FIFO Underrun */
670 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
671
e07b1aa8 672 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 673 sky2_phy_init(hw, port);
e07b1aa8 674 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 675
676 /* MIB clear */
677 reg = gma_read16(hw, port, GM_PHY_ADDR);
678 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
679
43f2f104
SH		 680 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
681 gma_read16(hw, port, i);
cd28ab6a
SH		 682 gma_write16(hw, port, GM_PHY_ADDR, reg);
683
684 /* transmit control */
685 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
686
687 /* receive control reg: unicast + multicast + no FCS */
688 gma_write16(hw, port, GM_RX_CTRL,
793b883e 689 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 690
691 /* transmit flow control */
692 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
693
694 /* transmit parameter */
695 gma_write16(hw, port, GM_TX_PARAM,
696 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
697 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
698 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
699 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
700
701 /* serial mode register */
702 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 703 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 704
6b1a3aef 705 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 706 reg |= GM_SMOD_JUMBO_ENA;
707
708 gma_write16(hw, port, GM_SERIAL_MODE, reg);
709
cd28ab6a
SH		 710 /* virtual address for data */
711 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
712
793b883e
SH		 713 /* physical address: used for pause frames */
714 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
715
716 /* ignore counter overflows */
cd28ab6a
SH		 717 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
718 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
719 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
720
721 /* Configure Rx MAC FIFO */
722 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 723 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
724 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 725
d571b694 726 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 727 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 728
8df9a876
SH		 729 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
730 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 731
732 /* Configure Tx MAC FIFO */
733 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
734 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 735
93745494 736 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 737 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0
SH		 738 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
739 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
740 /* set Tx GMAC FIFO Almost Empty Threshold */
741 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
742 /* Disable Store & Forward mode for TX */
743 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
744 }
745 }
746
cd28ab6a
SH		 747}
748
67712901
SH		 749/* Assign Ram Buffer allocation to queue */
750static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 751{
67712901
SH		 752 u32 end;
753
754 /* convert from K bytes to qwords used for hw register */
755 start *= 1024/8;
756 space *= 1024/8;
757 end = start + space - 1;
793b883e 758
cd28ab6a
SH		 759 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
760 sky2_write32(hw, RB_ADDR(q, RB_START), start);
761 sky2_write32(hw, RB_ADDR(q, RB_END), end);
762 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
763 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
764
765 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 766 u32 tp = space - space/4;
793b883e 767
1c28f6ba
SH		 768 /* On receive queue's set the thresholds
769 * give receiver priority when > 3/4 full
770 * send pause when down to 2K
771 */
772 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
773 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 774
1c28f6ba
SH		 775 tp = space - 2048/8;
776 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
777 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 778 } else {
779 /* Enable store & forward on Tx queue's because
780 * Tx FIFO is only 1K on Yukon
781 */
782 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
783 }
784
785 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 786 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 787}
788
cd28ab6a 789/* Setup Bus Memory Interface */
af4ed7e6 790static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 791{
792 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
793 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
794 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 795 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 796}
797
cd28ab6a
SH		 798/* Setup prefetch unit registers. This is the interface between
799 * hardware and driver list elements
800 */
8cc048e3 801static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 802 u64 addr, u32 last)
803{
cd28ab6a
SH		 804 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
805 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
806 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
807 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
808 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
809 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 810
811 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 812}
813
793b883e
SH		 814static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
815{
816 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
817
cb5d9547 818 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 819 le->ctrl = 0;
793b883e
SH		 820 return le;
821}
cd28ab6a 822
291ea614
SH		 823static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
824 struct sky2_tx_le *le)
825{
826 return sky2->tx_ring + (le - sky2->tx_le);
827}
828
290d4de5
SH		 829/* Update chip's next pointer */
830static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 831{
98232f85 832 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 833 wmb();
98232f85
SH		 834 sky2_write16(hw, q, idx);
835 sky2_read16(hw, q);
cd28ab6a
SH		 836}
837
793b883e 838
cd28ab6a
SH		 839static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
840{
841 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 842 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 843 le->ctrl = 0;
cd28ab6a
SH		 844 return le;
845}
846
a018e330
SH		 847/* Return high part of DMA address (could be 32 or 64 bit) */
848static inline u32 high32(dma_addr_t a)
849{
a036119f 850 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 851}
852
14d0263f
SH		 853/* Build description to hardware for one receive segment */
854static void sky2_rx_add(struct sky2_port *sky2, u8 op,
855 dma_addr_t map, unsigned len)
cd28ab6a
SH		 856{
857 struct sky2_rx_le *le;
734d1868 858 u32 hi = high32(map);
cd28ab6a 859
793b883e 860 if (sky2->rx_addr64 != hi) {
cd28ab6a 861 le = sky2_next_rx(sky2);
793b883e 862 le->addr = cpu_to_le32(hi);
cd28ab6a 863 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 864 sky2->rx_addr64 = high32(map + len);
cd28ab6a 865 }
793b883e 866
cd28ab6a 867 le = sky2_next_rx(sky2);
734d1868
SH		 868 le->addr = cpu_to_le32((u32) map);
869 le->length = cpu_to_le16(len);
14d0263f 870 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 871}
872
14d0263f
SH		 873/* Build description to hardware for one possibly fragmented skb */
874static void sky2_rx_submit(struct sky2_port *sky2,
875 const struct rx_ring_info *re)
876{
877 int i;
878
879 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
880
881 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
882 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
883}
884
885
886static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
887 unsigned size)
888{
889 struct sk_buff *skb = re->skb;
890 int i;
891
892 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
893 pci_unmap_len_set(re, data_size, size);
894
895 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
896 re->frag_addr[i] = pci_map_page(pdev,
897 skb_shinfo(skb)->frags[i].page,
898 skb_shinfo(skb)->frags[i].page_offset,
899 skb_shinfo(skb)->frags[i].size,
900 PCI_DMA_FROMDEVICE);
901}
902
903static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
904{
905 struct sk_buff *skb = re->skb;
906 int i;
907
908 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
909 PCI_DMA_FROMDEVICE);
910
911 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
912 pci_unmap_page(pdev, re->frag_addr[i],
913 skb_shinfo(skb)->frags[i].size,
914 PCI_DMA_FROMDEVICE);
915}
793b883e 916
cd28ab6a
SH		 917/* Tell chip where to start receive checksum.
918 * Actually has two checksums, but set both same to avoid possible byte
919 * order problems.
920 */
793b883e 921static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 922{
923 struct sky2_rx_le *le;
924
cd28ab6a 925 le = sky2_next_rx(sky2);
f65b138c 926 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 927 le->ctrl = 0;
928 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 929
793b883e
SH		 930 sky2_write32(sky2->hw,
931 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
932 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 933
934}
935
6b1a3aef
SH		 936/*
937 * The RX Stop command will not work for Yukon-2 if the BMU does not
938 * reach the end of packet and since we can't make sure that we have
939 * incoming data, we must reset the BMU while it is not doing a DMA
940 * transfer. Since it is possible that the RX path is still active,
941 * the RX RAM buffer will be stopped first, so any possible incoming
942 * data will not trigger a DMA. After the RAM buffer is stopped, the
943 * BMU is polled until any DMA in progress is ended and only then it
944 * will be reset.
945 */
946static void sky2_rx_stop(struct sky2_port *sky2)
947{
948 struct sky2_hw *hw = sky2->hw;
949 unsigned rxq = rxqaddr[sky2->port];
950 int i;
951
952 /* disable the RAM Buffer receive queue */
953 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
954
955 for (i = 0; i < 0xffff; i++)
956 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
957 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
958 goto stopped;
959
960 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
961 sky2->netdev->name);
962stopped:
963 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
964
965 /* reset the Rx prefetch unit */
966 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
967}
793b883e 968
d571b694 969/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 970static void sky2_rx_clean(struct sky2_port *sky2)
971{
972 unsigned i;
973
974 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 975 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 976 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 977
978 if (re->skb) {
14d0263f 979 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 980 kfree_skb(re->skb);
981 re->skb = NULL;
982 }
983 }
984}
985
ef743d33
SH		 986/* Basic MII support */
987static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
988{
989 struct mii_ioctl_data *data = if_mii(ifr);
990 struct sky2_port *sky2 = netdev_priv(dev);
991 struct sky2_hw *hw = sky2->hw;
992 int err = -EOPNOTSUPP;
993
994 if (!netif_running(dev))
995 return -ENODEV; /* Phy still in reset */
996
d89e1343 997 switch (cmd) {
ef743d33
SH		 998 case SIOCGMIIPHY:
999 data->phy_id = PHY_ADDR_MARV;
1000
1001 /* fallthru */
1002 case SIOCGMIIREG: {
1003 u16 val = 0;
91c86df5 1004
e07b1aa8 1005 spin_lock_bh(&sky2->phy_lock);
ef743d33 1006 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1007 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1008
ef743d33
SH		 1009 data->val_out = val;
1010 break;
1011 }
1012
1013 case SIOCSMIIREG:
1014 if (!capable(CAP_NET_ADMIN))
1015 return -EPERM;
1016
e07b1aa8 1017 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1018 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1019 data->val_in);
e07b1aa8 1020 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1021 break;
1022 }
1023 return err;
1024}
1025
d1f13708
SH		 1026#ifdef SKY2_VLAN_TAG_USED
1027static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1028{
1029 struct sky2_port *sky2 = netdev_priv(dev);
1030 struct sky2_hw *hw = sky2->hw;
1031 u16 port = sky2->port;
d1f13708 1032
2bb8c262 1033 netif_tx_lock_bh(dev);
d1f13708
SH		 1034
1035 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1036 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1037 sky2->vlgrp = grp;
1038
2bb8c262 1039 netif_tx_unlock_bh(dev);
d1f13708
SH		 1040}
1041
1042static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1043{
1044 struct sky2_port *sky2 = netdev_priv(dev);
1045 struct sky2_hw *hw = sky2->hw;
1046 u16 port = sky2->port;
d1f13708 1047
2bb8c262 1048 netif_tx_lock_bh(dev);
d1f13708
SH		 1049
1050 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1051 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1052 if (sky2->vlgrp)
1053 sky2->vlgrp->vlan_devices[vid] = NULL;
1054
2bb8c262 1055 netif_tx_unlock_bh(dev);
d1f13708
SH		 1056}
1057#endif
1058
82788c7a 1059/*
14d0263f
SH		 1060 * Allocate an skb for receiving. If the MTU is large enough
1061 * make the skb non-linear with a fragment list of pages.
1062 *
82788c7a
SH		 1063 * It appears the hardware has a bug in the FIFO logic that
1064 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1065 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1066 * aligned except if slab debugging is enabled.
82788c7a 1067 */
14d0263f 1068static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1069{
1070 struct sk_buff *skb;
14d0263f
SH		 1071 unsigned long p;
1072 int i;
82788c7a 1073
14d0263f
SH		 1074 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1075 if (!skb)
1076 goto nomem;
1077
1078 p = (unsigned long) skb->data;
1079 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1080
1081 for (i = 0; i < sky2->rx_nfrags; i++) {
1082 struct page *page = alloc_page(GFP_ATOMIC);
1083
1084 if (!page)
1085 goto free_partial;
1086 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1087 }
1088
1089 return skb;
14d0263f
SH		 1090free_partial:
1091 kfree_skb(skb);
1092nomem:
1093 return NULL;
82788c7a
SH		 1094}
1095
cd28ab6a
SH		 1096/*
1097 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1098 * Normal case this ends up creating one list element for skb
1099 * in the receive ring. Worst case if using large MTU and each
1100 * allocation falls on a different 64 bit region, that results
1101 * in 6 list elements per ring entry.
1102 * One element is used for checksum enable/disable, and one
1103 * extra to avoid wrap.
cd28ab6a 1104 */
6b1a3aef 1105static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1106{
6b1a3aef 1107 struct sky2_hw *hw = sky2->hw;
14d0263f 1108 struct rx_ring_info *re;
6b1a3aef 1109 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1110 unsigned i, size, space, thresh;
cd28ab6a 1111
6b1a3aef 1112 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1113 sky2_qset(hw, rxq);
977bdf06 1114
c3905bc4
SH		 1115 /* On PCI express lowering the watermark gives better performance */
1116 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1117 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1118
1119 /* These chips have no ram buffer?
1120 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1121 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1122 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1123 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
977bdf06 1124 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
977bdf06 1125
6b1a3aef
SH		 1126 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1127
1128 rx_set_checksum(sky2);
14d0263f
SH		 1129
1130 /* Space needed for frame data + headers rounded up */
1131 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1132 + 8;
1133
1134 /* Stopping point for hardware truncation */
1135 thresh = (size - 8) / sizeof(u32);
1136
1137 /* Account for overhead of skb - to avoid order > 0 allocation */
1138 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1139 + sizeof(struct skb_shared_info);
1140
1141 sky2->rx_nfrags = space >> PAGE_SHIFT;
1142 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1143
1144 if (sky2->rx_nfrags != 0) {
1145 /* Compute residue after pages */
1146 space = sky2->rx_nfrags << PAGE_SHIFT;
1147
1148 if (space < size)
1149 size -= space;
1150 else
1151 size = 0;
1152
1153 /* Optimize to handle small packets and headers */
1154 if (size < copybreak)
1155 size = copybreak;
1156 if (size < ETH_HLEN)
1157 size = ETH_HLEN;
1158 }
1159 sky2->rx_data_size = size;
1160
1161 /* Fill Rx ring */
793b883e 1162 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1163 re = sky2->rx_ring + i;
cd28ab6a 1164
14d0263f 1165 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1166 if (!re->skb)
1167 goto nomem;
1168
14d0263f
SH		 1169 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1170 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1171 }
1172
a1433ac4
SH		 1173 /*
1174 * The receiver hangs if it receives frames larger than the
1175 * packet buffer. As a workaround, truncate oversize frames, but
1176 * the register is limited to 9 bits, so if you do frames > 2052
1177 * you better get the MTU right!
1178 */
a1433ac4
SH		 1179 if (thresh > 0x1ff)
1180 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1181 else {
1182 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1183 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1184 }
1185
6b1a3aef
SH		 1186 /* Tell chip about available buffers */
1187 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1188 return 0;
1189nomem:
1190 sky2_rx_clean(sky2);
1191 return -ENOMEM;
1192}
1193
1194/* Bring up network interface. */
1195static int sky2_up(struct net_device *dev)
1196{
1197 struct sky2_port *sky2 = netdev_priv(dev);
1198 struct sky2_hw *hw = sky2->hw;
1199 unsigned port = sky2->port;
67712901 1200 u32 ramsize, imask;
ee7abb04 1201 int cap, err = -ENOMEM;
843a46f4 1202 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1203
ee7abb04
SH		 1204 /*
1205 * On dual port PCI-X card, there is an problem where status
1206 * can be received out of order due to split transactions
843a46f4 1207 */
ee7abb04
SH		 1208 if (otherdev && netif_running(otherdev) &&
1209 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1210 struct sky2_port *osky2 = netdev_priv(otherdev);
1211 u16 cmd;
1212
1213 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1214 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1215 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1216
1217 sky2->rx_csum = 0;
1218 osky2->rx_csum = 0;
1219 }
843a46f4 1220
cd28ab6a
SH		 1221 if (netif_msg_ifup(sky2))
1222 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1223
1224 /* must be power of 2 */
1225 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1226 TX_RING_SIZE *
1227 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1228 &sky2->tx_le_map);
1229 if (!sky2->tx_le)
1230 goto err_out;
1231
6cdbbdf3 1232 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1233 GFP_KERNEL);
1234 if (!sky2->tx_ring)
1235 goto err_out;
1236 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1237
1238 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1239 &sky2->rx_le_map);
1240 if (!sky2->rx_le)
1241 goto err_out;
1242 memset(sky2->rx_le, 0, RX_LE_BYTES);
1243
291ea614 1244 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1245 GFP_KERNEL);
1246 if (!sky2->rx_ring)
1247 goto err_out;
1248
d3bcfbeb
SH		 1249 sky2_phy_power(hw, port, 1);
1250
cd28ab6a
SH		 1251 sky2_mac_init(hw, port);
1252
67712901
SH		 1253 /* Register is number of 4K blocks on internal RAM buffer. */
1254 ramsize = sky2_read8(hw, B2_E_0) * 4;
1255 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1256
67712901
SH		 1257 if (ramsize > 0) {
1258 u32 rxspace;
cd28ab6a 1259
67712901
SH		 1260 if (ramsize < 16)
1261 rxspace = ramsize / 2;
1262 else
1263 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1264
67712901
SH		 1265 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1266 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1267
1268 /* Make sure SyncQ is disabled */
1269 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1270 RB_RST_SET);
1271 }
793b883e 1272
af4ed7e6 1273 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1274
977bdf06 1275 /* Set almost empty threshold */
c2716fb4
SH		 1276 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1277 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1278 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1279
6b1a3aef
SH		 1280 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1281 TX_RING_SIZE - 1);
cd28ab6a 1282
6b1a3aef 1283 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1284 if (err)
1285 goto err_out;
1286
cd28ab6a 1287 /* Enable interrupts from phy/mac for port */
e07b1aa8 1288 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1289 imask |= portirq_msk[port];
e07b1aa8
SH		 1290 sky2_write32(hw, B0_IMSK, imask);
1291
cd28ab6a
SH		 1292 return 0;
1293
1294err_out:
1b537565 1295 if (sky2->rx_le) {
cd28ab6a
SH		 1296 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1297 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1298 sky2->rx_le = NULL;
1299 }
1300 if (sky2->tx_le) {
cd28ab6a
SH		 1301 pci_free_consistent(hw->pdev,
1302 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1303 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1304 sky2->tx_le = NULL;
1305 }
1306 kfree(sky2->tx_ring);
1307 kfree(sky2->rx_ring);
cd28ab6a 1308
1b537565
SH		 1309 sky2->tx_ring = NULL;
1310 sky2->rx_ring = NULL;
cd28ab6a
SH		 1311 return err;
1312}
1313
793b883e
SH		 1314/* Modular subtraction in ring */
1315static inline int tx_dist(unsigned tail, unsigned head)
1316{
cb5d9547 1317 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1318}
cd28ab6a 1319
793b883e
SH		 1320/* Number of list elements available for next tx */
1321static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1322{
793b883e 1323 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1324}
1325
793b883e 1326/* Estimate of number of transmit list elements required */
28bd181a 1327static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1328{
793b883e
SH		 1329 unsigned count;
1330
1331 count = sizeof(dma_addr_t) / sizeof(u32);
1332 count += skb_shinfo(skb)->nr_frags * count;
1333
89114afd 1334 if (skb_is_gso(skb))
793b883e
SH		 1335 ++count;
1336
84fa7933 1337 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1338 ++count;
1339
1340 return count;
cd28ab6a
SH		 1341}
1342
793b883e
SH		 1343/*
1344 * Put one packet in ring for transmit.
1345 * A single packet can generate multiple list elements, and
1346 * the number of ring elements will probably be less than the number
1347 * of list elements used.
1348 */
cd28ab6a
SH		 1349static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1350{
1351 struct sky2_port *sky2 = netdev_priv(dev);
1352 struct sky2_hw *hw = sky2->hw;
d1f13708 1353 struct sky2_tx_le *le = NULL;
6cdbbdf3 1354 struct tx_ring_info *re;
cd28ab6a
SH		 1355 unsigned i, len;
1356 dma_addr_t mapping;
1357 u32 addr64;
1358 u16 mss;
1359 u8 ctrl;
1360
2bb8c262
SH		 1361 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1362 return NETDEV_TX_BUSY;
cd28ab6a 1363
793b883e 1364 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1365 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1366 dev->name, sky2->tx_prod, skb->len);
1367
cd28ab6a
SH		 1368 len = skb_headlen(skb);
1369 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1370 addr64 = high32(mapping);
793b883e 1371
a018e330
SH		 1372 /* Send high bits if changed or crosses boundary */
1373 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1374 le = get_tx_le(sky2);
f65b138c 1375 le->addr = cpu_to_le32(addr64);
793b883e 1376 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1377 sky2->tx_addr64 = high32(mapping + len);
793b883e 1378 }
cd28ab6a
SH		 1379
1380 /* Check for TCP Segmentation Offload */
7967168c 1381 mss = skb_shinfo(skb)->gso_size;
793b883e 1382 if (mss != 0) {
cd28ab6a
SH		 1383 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1384 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1385 mss += ETH_HLEN;
1386
e07560cd
SH		 1387 if (mss != sky2->tx_last_mss) {
1388 le = get_tx_le(sky2);
f65b138c 1389 le->addr = cpu_to_le32(mss);
e07560cd 1390 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1391 sky2->tx_last_mss = mss;
1392 }
cd28ab6a
SH		 1393 }
1394
cd28ab6a 1395 ctrl = 0;
d1f13708
SH		 1396#ifdef SKY2_VLAN_TAG_USED
1397 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1398 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1399 if (!le) {
1400 le = get_tx_le(sky2);
f65b138c 1401 le->addr = 0;
d1f13708 1402 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1403 } else
1404 le->opcode |= OP_VLAN;
1405 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1406 ctrl |= INS_VLAN;
1407 }
1408#endif
1409
1410 /* Handle TCP checksum offload */
84fa7933 1411 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1412 unsigned offset = skb->h.raw - skb->data;
1413 u32 tcpsum;
1414
1415 tcpsum = offset << 16; /* sum start */
ff1dcadb 1416 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a
SH		 1417
1418 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1419 if (skb->nh.iph->protocol == IPPROTO_UDP)
1420 ctrl |= UDPTCP;
1421
f65b138c
SH		 1422 if (tcpsum != sky2->tx_tcpsum) {
1423 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1424
1425 le = get_tx_le(sky2);
f65b138c 1426 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1427 le->length = 0; /* initial checksum value */
1428 le->ctrl = 1; /* one packet */
1429 le->opcode = OP_TCPLISW | HW_OWNER;
1430 }
cd28ab6a
SH		 1431 }
1432
1433 le = get_tx_le(sky2);
f65b138c 1434 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1435 le->length = cpu_to_le16(len);
1436 le->ctrl = ctrl;
793b883e 1437 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1438
291ea614 1439 re = tx_le_re(sky2, le);
cd28ab6a 1440 re->skb = skb;
6cdbbdf3 1441 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1442 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1443
1444 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1445 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1446
1447 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1448 frag->size, PCI_DMA_TODEVICE);
a036119f 1449 addr64 = high32(mapping);
793b883e
SH		 1450 if (addr64 != sky2->tx_addr64) {
1451 le = get_tx_le(sky2);
f65b138c 1452 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1453 le->ctrl = 0;
1454 le->opcode = OP_ADDR64 | HW_OWNER;
1455 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1456 }
1457
1458 le = get_tx_le(sky2);
f65b138c 1459 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1460 le->length = cpu_to_le16(frag->size);
1461 le->ctrl = ctrl;
793b883e 1462 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1463
291ea614
SH		 1464 re = tx_le_re(sky2, le);
1465 re->skb = skb;
1466 pci_unmap_addr_set(re, mapaddr, mapping);
1467 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1468 }
6cdbbdf3 1469
cd28ab6a
SH		 1470 le->ctrl |= EOP;
1471
97bda706
SH		 1472 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1473 netif_stop_queue(dev);
b19666d9 1474
290d4de5 1475 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1476
cd28ab6a
SH		 1477 dev->trans_start = jiffies;
1478 return NETDEV_TX_OK;
1479}
1480
cd28ab6a 1481/*
793b883e
SH		 1482 * Free ring elements from starting at tx_cons until "done"
1483 *
1484 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1485 * buffers so make sure not to free skb to early.
cd28ab6a 1486 */
d11c13e7 1487static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1488{
d11c13e7 1489 struct net_device *dev = sky2->netdev;
af2a58ac 1490 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1491 unsigned idx;
cd28ab6a 1492
0e3ff6aa 1493 BUG_ON(done >= TX_RING_SIZE);
2224795d 1494
291ea614
SH		 1495 for (idx = sky2->tx_cons; idx != done;
1496 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1497 struct sky2_tx_le *le = sky2->tx_le + idx;
1498 struct tx_ring_info *re = sky2->tx_ring + idx;
1499
1500 switch(le->opcode & ~HW_OWNER) {
1501 case OP_LARGESEND:
1502 case OP_PACKET:
1503 pci_unmap_single(pdev,
1504 pci_unmap_addr(re, mapaddr),
1505 pci_unmap_len(re, maplen),
1506 PCI_DMA_TODEVICE);
af2a58ac 1507 break;
291ea614
SH		 1508 case OP_BUFFER:
1509 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1510 pci_unmap_len(re, maplen),
734d1868 1511 PCI_DMA_TODEVICE);
291ea614
SH		 1512 break;
1513 }
1514
1515 if (le->ctrl & EOP) {
1516 if (unlikely(netif_msg_tx_done(sky2)))
1517 printk(KERN_DEBUG "%s: tx done %u\n",
1518 dev->name, idx);
2bf56fe2 1519 sky2->net_stats.tx_packets++;
1520 sky2->net_stats.tx_bytes += re->skb->len;
1521
794b2bd2 1522 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1523 }
1524
291ea614 1525 le->opcode = 0; /* paranoia */
793b883e 1526 }
793b883e 1527
291ea614 1528 sky2->tx_cons = idx;
22e11703 1529 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1530 netif_wake_queue(dev);
cd28ab6a
SH		 1531}
1532
1533/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1534static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1535{
2bb8c262
SH		 1536 struct sky2_port *sky2 = netdev_priv(dev);
1537
1538 netif_tx_lock_bh(dev);
d11c13e7 1539 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1540 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1541}
1542
1543/* Network shutdown */
1544static int sky2_down(struct net_device *dev)
1545{
1546 struct sky2_port *sky2 = netdev_priv(dev);
1547 struct sky2_hw *hw = sky2->hw;
1548 unsigned port = sky2->port;
1549 u16 ctrl;
e07b1aa8 1550 u32 imask;
cd28ab6a 1551
1b537565
SH		 1552 /* Never really got started! */
1553 if (!sky2->tx_le)
1554 return 0;
1555
cd28ab6a
SH		 1556 if (netif_msg_ifdown(sky2))
1557 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1558
018d1c66 1559 /* Stop more packets from being queued */
cd28ab6a
SH		 1560 netif_stop_queue(dev);
1561
ebc646f6
SH		 1562 /* Disable port IRQ */
1563 imask = sky2_read32(hw, B0_IMSK);
1564 imask &= ~portirq_msk[port];
1565 sky2_write32(hw, B0_IMSK, imask);
1566
25d82d7a
SH		 1567 /*
1568 * Both ports share the NAPI poll on port 0, so if necessary undo the
1569 * the disable that is done in dev_close.
1570 */
1571 if (sky2->port == 0 && hw->ports > 1)
1572 netif_poll_enable(dev);
1573
d3bcfbeb 1574 sky2_gmac_reset(hw, port);
793b883e 1575
cd28ab6a
SH		 1576 /* Stop transmitter */
1577 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1578 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1579
1580 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1581 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1582
c2716fb4
SH		 1583 /* WA for dev. #4.209 */
1584 if (hw->chip_id == CHIP_ID_YUKON_EC_U
8df9a876 1585 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
c2716fb4
SH		 1586 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1587 sky2->speed != SPEED_1000 ?
1588 TX_STFW_ENA : TX_STFW_DIS);
1589
cd28ab6a 1590 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1591 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1592 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1593
1594 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1595
1596 /* Workaround shared GMAC reset */
793b883e
SH		 1597 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1598 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1599 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1600
1601 /* Disable Force Sync bit and Enable Alloc bit */
1602 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1603 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1604
1605 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1606 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1607 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1608
1609 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1610 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1611 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1612
1613 /* Reset the Tx prefetch units */
1614 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1615 PREF_UNIT_RST_SET);
1616
1617 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1618
6b1a3aef 1619 sky2_rx_stop(sky2);
cd28ab6a
SH		 1620
1621 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1622 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1623
d3bcfbeb
SH		 1624 sky2_phy_power(hw, port, 0);
1625
d571b694 1626 /* turn off LED's */
cd28ab6a
SH		 1627 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1628
018d1c66
SH		 1629 synchronize_irq(hw->pdev->irq);
1630
2bb8c262 1631 sky2_tx_clean(dev);
cd28ab6a
SH		 1632 sky2_rx_clean(sky2);
1633
1634 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1635 sky2->rx_le, sky2->rx_le_map);
1636 kfree(sky2->rx_ring);
1637
1638 pci_free_consistent(hw->pdev,
1639 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1640 sky2->tx_le, sky2->tx_le_map);
1641 kfree(sky2->tx_ring);
1642
1b537565
SH		 1643 sky2->tx_le = NULL;
1644 sky2->rx_le = NULL;
1645
1646 sky2->rx_ring = NULL;
1647 sky2->tx_ring = NULL;
1648
cd28ab6a
SH		 1649 return 0;
1650}
1651
1652static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1653{
b89165f2 1654 if (!sky2_is_copper(hw))
793b883e
SH		 1655 return SPEED_1000;
1656
cd28ab6a
SH		 1657 if (hw->chip_id == CHIP_ID_YUKON_FE)
1658 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1659
1660 switch (aux & PHY_M_PS_SPEED_MSK) {
1661 case PHY_M_PS_SPEED_1000:
1662 return SPEED_1000;
1663 case PHY_M_PS_SPEED_100:
1664 return SPEED_100;
1665 default:
1666 return SPEED_10;
1667 }
1668}
1669
1670static void sky2_link_up(struct sky2_port *sky2)
1671{
1672 struct sky2_hw *hw = sky2->hw;
1673 unsigned port = sky2->port;
1674 u16 reg;
16ad91e1
SH		 1675 static const char *fc_name[] = {
1676 [FC_NONE] = "none",
1677 [FC_TX] = "tx",
1678 [FC_RX] = "rx",
1679 [FC_BOTH] = "both",
1680 };
cd28ab6a 1681
cd28ab6a 1682 /* enable Rx/Tx */
2eaba1a2 1683 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1684 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1685 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1686
1687 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1688
1689 netif_carrier_on(sky2->netdev);
1690 netif_wake_queue(sky2->netdev);
1691
1692 /* Turn on link LED */
793b883e 1693 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1694 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1695
93745494
SH		 1696 if (hw->chip_id == CHIP_ID_YUKON_XL
1697 || hw->chip_id == CHIP_ID_YUKON_EC_U
1698 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1699 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1700 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1701
1702 switch(sky2->speed) {
1703 case SPEED_10:
1704 led |= PHY_M_LEDC_INIT_CTRL(7);
1705 break;
1706
1707 case SPEED_100:
1708 led |= PHY_M_LEDC_STA1_CTRL(7);
1709 break;
1710
1711 case SPEED_1000:
1712 led |= PHY_M_LEDC_STA0_CTRL(7);
1713 break;
1714 }
793b883e
SH		 1715
1716 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1717 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1718 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1719 }
1720
cd28ab6a
SH		 1721 if (netif_msg_link(sky2))
1722 printk(KERN_INFO PFX
d571b694 1723 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1724 sky2->netdev->name, sky2->speed,
1725 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1726 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1727}
1728
1729static void sky2_link_down(struct sky2_port *sky2)
1730{
1731 struct sky2_hw *hw = sky2->hw;
1732 unsigned port = sky2->port;
1733 u16 reg;
1734
1735 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1736
1737 reg = gma_read16(hw, port, GM_GP_CTRL);
1738 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1739 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1740
16ad91e1 1741 if (sky2->flow_status == FC_RX) {
cd28ab6a
SH		 1742 /* restore Asymmetric Pause bit */
1743 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1744 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1745 | PHY_M_AN_ASP);
cd28ab6a
SH		 1746 }
1747
cd28ab6a
SH		 1748 netif_carrier_off(sky2->netdev);
1749 netif_stop_queue(sky2->netdev);
1750
1751 /* Turn on link LED */
1752 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1753
1754 if (netif_msg_link(sky2))
1755 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1756
cd28ab6a
SH		 1757 sky2_phy_init(hw, port);
1758}
1759
16ad91e1
SH		 1760static enum flow_control sky2_flow(int rx, int tx)
1761{
1762 if (rx)
1763 return tx ? FC_BOTH : FC_RX;
1764 else
1765 return tx ? FC_TX : FC_NONE;
1766}
1767
793b883e
SH		 1768static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1769{
1770 struct sky2_hw *hw = sky2->hw;
1771 unsigned port = sky2->port;
1772 u16 lpa;
1773
1774 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1775
1776 if (lpa & PHY_M_AN_RF) {
1777 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1778 return -1;
1779 }
1780
793b883e
SH		 1781 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1782 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1783 sky2->netdev->name);
1784 return -1;
1785 }
1786
793b883e 1787 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1788 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e
SH		 1789
1790 /* Pause bits are offset (9..8) */
93745494
SH		 1791 if (hw->chip_id == CHIP_ID_YUKON_XL
1792 || hw->chip_id == CHIP_ID_YUKON_EC_U
1793 || hw->chip_id == CHIP_ID_YUKON_EX)
793b883e
SH		 1794 aux >>= 6;
1795
16ad91e1
SH		 1796 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1797 aux & PHY_M_PS_TX_P_EN);
793b883e 1798
16ad91e1 1799 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1800 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1801 sky2->flow_status = FC_NONE;
2eaba1a2 1802
16ad91e1 1803 if (aux & PHY_M_PS_RX_P_EN)
793b883e
SH		 1804 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1805 else
1806 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1807
1808 return 0;
1809}
cd28ab6a 1810
e07b1aa8
SH		 1811/* Interrupt from PHY */
1812static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1813{
e07b1aa8
SH		 1814 struct net_device *dev = hw->dev[port];
1815 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1816 u16 istatus, phystat;
1817
ebc646f6
SH		 1818 if (!netif_running(dev))
1819 return;
1820
e07b1aa8
SH		 1821 spin_lock(&sky2->phy_lock);
1822 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1823 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1824
cd28ab6a
SH		 1825 if (netif_msg_intr(sky2))
1826 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1827 sky2->netdev->name, istatus, phystat);
1828
2eaba1a2 1829 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1830 if (sky2_autoneg_done(sky2, phystat) == 0)
1831 sky2_link_up(sky2);
1832 goto out;
1833 }
cd28ab6a 1834
793b883e
SH		 1835 if (istatus & PHY_M_IS_LSP_CHANGE)
1836 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1837
793b883e
SH		 1838 if (istatus & PHY_M_IS_DUP_CHANGE)
1839 sky2->duplex =
1840 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1841
793b883e
SH		 1842 if (istatus & PHY_M_IS_LST_CHANGE) {
1843 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1844 sky2_link_up(sky2);
793b883e
SH		 1845 else
1846 sky2_link_down(sky2);
cd28ab6a 1847 }
793b883e 1848out:
e07b1aa8 1849 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1850}
1851
302d1252 1852
62335ab0 1853/* Transmit timeout is only called if we are running, carrier is up
302d1252 1854 * and tx queue is full (stopped).
62335ab0 1855 * Called with netif_tx_lock held.
302d1252 1856 */
cd28ab6a
SH		 1857static void sky2_tx_timeout(struct net_device *dev)
1858{
1859 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1860 struct sky2_hw *hw = sky2->hw;
62335ab0 1861 u32 imask;
cd28ab6a
SH		 1862
1863 if (netif_msg_timer(sky2))
1864 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1865
8f24664d 1866 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1867 dev->name, sky2->tx_cons, sky2->tx_prod,
1868 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1869 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1870
62335ab0
SH		 1871 imask = sky2_read32(hw, B0_IMSK); /* block IRQ in hw */
1872 sky2_write32(hw, B0_IMSK, 0);
1873 sky2_read32(hw, B0_IMSK);
8f24664d 1874
62335ab0
SH		 1875 netif_poll_disable(hw->dev[0]); /* stop NAPI poll */
1876 synchronize_irq(hw->pdev->irq);
8cc048e3 1877
62335ab0
SH		 1878 netif_start_queue(dev); /* don't wakeup during flush */
1879 sky2_tx_complete(sky2, sky2->tx_prod); /* Flush transmit queue */
8f24664d 1880
62335ab0 1881 sky2_write32(hw, B0_IMSK, imask);
8f24664d 1882
62335ab0 1883 sky2_phy_reinit(sky2); /* this clears flow control etc */
cd28ab6a
SH		 1884}
1885
1886static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1887{
6b1a3aef
SH		 1888 struct sky2_port *sky2 = netdev_priv(dev);
1889 struct sky2_hw *hw = sky2->hw;
1890 int err;
1891 u16 ctl, mode;
e07b1aa8 1892 u32 imask;
cd28ab6a
SH		 1893
1894 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1895 return -EINVAL;
1896
4a50a876 1897 /* TSO on Yukon Ultra and MTU > 1500 not supported */
5a5b1ea0 1898 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
4a50a876 1899 dev->features &= ~NETIF_F_TSO;
5a5b1ea0 1900
6b1a3aef
SH		 1901 if (!netif_running(dev)) {
1902 dev->mtu = new_mtu;
1903 return 0;
1904 }
1905
e07b1aa8 1906 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1907 sky2_write32(hw, B0_IMSK, 0);
1908
018d1c66
SH		 1909 dev->trans_start = jiffies; /* prevent tx timeout */
1910 netif_stop_queue(dev);
1911 netif_poll_disable(hw->dev[0]);
1912
e07b1aa8
SH		 1913 synchronize_irq(hw->pdev->irq);
1914
6b1a3aef
SH		 1915 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1916 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1917 sky2_rx_stop(sky2);
1918 sky2_rx_clean(sky2);
cd28ab6a
SH		 1919
1920 dev->mtu = new_mtu;
14d0263f 1921
6b1a3aef
SH		 1922 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1923 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1924
1925 if (dev->mtu > ETH_DATA_LEN)
1926 mode |= GM_SMOD_JUMBO_ENA;
1927
1928 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1929
6b1a3aef 1930 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1931
6b1a3aef 1932 err = sky2_rx_start(sky2);
e07b1aa8 1933 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1934
1b537565
SH		 1935 if (err)
1936 dev_close(dev);
1937 else {
1938 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1939
1940 netif_poll_enable(hw->dev[0]);
1941 netif_wake_queue(dev);
1942 }
1943
cd28ab6a
SH		 1944 return err;
1945}
1946
14d0263f
SH		 1947/* For small just reuse existing skb for next receive */
1948static struct sk_buff *receive_copy(struct sky2_port *sky2,
1949 const struct rx_ring_info *re,
1950 unsigned length)
1951{
1952 struct sk_buff *skb;
1953
1954 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1955 if (likely(skb)) {
1956 skb_reserve(skb, 2);
1957 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1958 length, PCI_DMA_FROMDEVICE);
1959 memcpy(skb->data, re->skb->data, length);
1960 skb->ip_summed = re->skb->ip_summed;
1961 skb->csum = re->skb->csum;
1962 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1963 length, PCI_DMA_FROMDEVICE);
1964 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1965 skb_put(skb, length);
14d0263f
SH		 1966 }
1967 return skb;
1968}
1969
1970/* Adjust length of skb with fragments to match received data */
1971static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1972 unsigned int length)
1973{
1974 int i, num_frags;
1975 unsigned int size;
1976
1977 /* put header into skb */
1978 size = min(length, hdr_space);
1979 skb->tail += size;
1980 skb->len += size;
1981 length -= size;
1982
1983 num_frags = skb_shinfo(skb)->nr_frags;
1984 for (i = 0; i < num_frags; i++) {
1985 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1986
1987 if (length == 0) {
1988 /* don't need this page */
1989 __free_page(frag->page);
1990 --skb_shinfo(skb)->nr_frags;
1991 } else {
1992 size = min(length, (unsigned) PAGE_SIZE);
1993
1994 frag->size = size;
1995 skb->data_len += size;
1996 skb->truesize += size;
1997 skb->len += size;
1998 length -= size;
1999 }
2000 }
2001}
2002
2003/* Normal packet - take skb from ring element and put in a new one */
2004static struct sk_buff *receive_new(struct sky2_port *sky2,
2005 struct rx_ring_info *re,
2006 unsigned int length)
2007{
2008 struct sk_buff *skb, *nskb;
2009 unsigned hdr_space = sky2->rx_data_size;
2010
2011 pr_debug(PFX "receive new length=%d\n", length);
2012
2013 /* Don't be tricky about reusing pages (yet) */
2014 nskb = sky2_rx_alloc(sky2);
2015 if (unlikely(!nskb))
2016 return NULL;
2017
2018 skb = re->skb;
2019 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2020
2021 prefetch(skb->data);
2022 re->skb = nskb;
2023 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2024
2025 if (skb_shinfo(skb)->nr_frags)
2026 skb_put_frags(skb, hdr_space, length);
2027 else
489b10c1 2028 skb_put(skb, length);
14d0263f
SH		 2029 return skb;
2030}
2031
cd28ab6a
SH		 2032/*
2033 * Receive one packet.
d571b694 2034 * For larger packets, get new buffer.
cd28ab6a 2035 */
497d7c86 2036static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2037 u16 length, u32 status)
2038{
497d7c86 2039 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2040 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2041 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2042
2043 if (unlikely(netif_msg_rx_status(sky2)))
2044 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2045 dev->name, sky2->rx_next, status, length);
cd28ab6a 2046
793b883e 2047 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2048 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2049
42eeea01 2050 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2051 goto error;
2052
42eeea01
SH		 2053 if (!(status & GMR_FS_RX_OK))
2054 goto resubmit;
2055
497d7c86 2056 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 2057 goto oversize;
2058
14d0263f
SH		 2059 if (length < copybreak)
2060 skb = receive_copy(sky2, re, length);
2061 else
2062 skb = receive_new(sky2, re, length);
793b883e 2063resubmit:
14d0263f 2064 sky2_rx_submit(sky2, re);
79e57d32 2065
cd28ab6a
SH		 2066 return skb;
2067
6e15b712
SH		 2068oversize:
2069 ++sky2->net_stats.rx_over_errors;
2070 goto resubmit;
2071
cd28ab6a 2072error:
6e15b712 2073 ++sky2->net_stats.rx_errors;
b6d77734
SH		 2074 if (status & GMR_FS_RX_FF_OV) {
2075 sky2->net_stats.rx_fifo_errors++;
2076 goto resubmit;
2077 }
6e15b712 2078
3be92a70 2079 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2080 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2081 dev->name, status, length);
793b883e
SH		 2082
2083 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2084 sky2->net_stats.rx_length_errors++;
2085 if (status & GMR_FS_FRAGMENT)
2086 sky2->net_stats.rx_frame_errors++;
2087 if (status & GMR_FS_CRC_ERR)
2088 sky2->net_stats.rx_crc_errors++;
79e57d32 2089
793b883e 2090 goto resubmit;
cd28ab6a
SH		 2091}
2092
e07b1aa8
SH		 2093/* Transmit complete */
2094static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2095{
e07b1aa8 2096 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2097
e07b1aa8 2098 if (netif_running(dev)) {
2bb8c262 2099 netif_tx_lock(dev);
e07b1aa8 2100 sky2_tx_complete(sky2, last);
2bb8c262 2101 netif_tx_unlock(dev);
2224795d 2102 }
cd28ab6a
SH		 2103}
2104
e07b1aa8
SH		 2105/* Process status response ring */
2106static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2107{
22e11703 2108 struct sky2_port *sky2;
e07b1aa8 2109 int work_done = 0;
22e11703 2110 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2111 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2112
af2a58ac 2113 rmb();
bea86103 2114
e71ebd73 2115 while (hw->st_idx != hwidx) {
13210ce5
SH		 2116 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2117 struct net_device *dev;
cd28ab6a 2118 struct sk_buff *skb;
cd28ab6a
SH		 2119 u32 status;
2120 u16 length;
2121
cb5d9547 2122 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2123
e71ebd73
SH		 2124 BUG_ON(le->link >= 2);
2125 dev = hw->dev[le->link];
13210ce5
SH		 2126
2127 sky2 = netdev_priv(dev);
f65b138c
SH		 2128 length = le16_to_cpu(le->length);
2129 status = le32_to_cpu(le->status);
cd28ab6a 2130
e71ebd73 2131 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2132 case OP_RXSTAT:
497d7c86 2133 skb = sky2_receive(dev, length, status);
d1f13708 2134 if (!skb)
5df79111 2135 goto force_update;
13210ce5 2136
13210ce5 2137 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2138 sky2->net_stats.rx_packets++;
2139 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2140 dev->last_rx = jiffies;
2141
d1f13708
SH		 2142#ifdef SKY2_VLAN_TAG_USED
2143 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2144 vlan_hwaccel_receive_skb(skb,
2145 sky2->vlgrp,
2146 be16_to_cpu(sky2->rx_tag));
2147 } else
2148#endif
cd28ab6a 2149 netif_receive_skb(skb);
13210ce5 2150
22e11703
SH		 2151 /* Update receiver after 16 frames */
2152 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2153force_update:
2154 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2155 buf_write[le->link] = 0;
2156 }
2157
2158 /* Stop after net poll weight */
13210ce5
SH		 2159 if (++work_done >= to_do)
2160 goto exit_loop;
cd28ab6a
SH		 2161 break;
2162
d1f13708
SH		 2163#ifdef SKY2_VLAN_TAG_USED
2164 case OP_RXVLAN:
2165 sky2->rx_tag = length;
2166 break;
2167
2168 case OP_RXCHKSVLAN:
2169 sky2->rx_tag = length;
2170 /* fall through */
2171#endif
cd28ab6a 2172 case OP_RXCHKS:
d11c13e7 2173 skb = sky2->rx_ring[sky2->rx_next].skb;
84fa7933 2174 skb->ip_summed = CHECKSUM_COMPLETE;
f65b138c 2175 skb->csum = status & 0xffff;
cd28ab6a
SH		 2176 break;
2177
2178 case OP_TXINDEXLE:
13b97b74 2179 /* TX index reports status for both ports */
f55925d7
SH		 2180 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2181 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2182 if (hw->dev[1])
2183 sky2_tx_done(hw->dev[1],
2184 ((status >> 24) & 0xff)
2185 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2186 break;
2187
cd28ab6a
SH		 2188 default:
2189 if (net_ratelimit())
793b883e 2190 printk(KERN_WARNING PFX
e71ebd73
SH		 2191 "unknown status opcode 0x%x\n", le->opcode);
2192 goto exit_loop;
cd28ab6a 2193 }
13210ce5 2194 }
cd28ab6a 2195
fe2a24df
SH		 2196 /* Fully processed status ring so clear irq */
2197 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2198
13210ce5 2199exit_loop:
22e11703
SH		 2200 if (buf_write[0]) {
2201 sky2 = netdev_priv(hw->dev[0]);
2202 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2203 }
2204
2205 if (buf_write[1]) {
2206 sky2 = netdev_priv(hw->dev[1]);
2207 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2208 }
2209
e07b1aa8 2210 return work_done;
cd28ab6a
SH		 2211}
2212
2213static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2214{
2215 struct net_device *dev = hw->dev[port];
2216
3be92a70
SH		 2217 if (net_ratelimit())
2218 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2219 dev->name, status);
cd28ab6a
SH		 2220
2221 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2222 if (net_ratelimit())
2223 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2224 dev->name);
cd28ab6a
SH		 2225 /* Clear IRQ */
2226 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2227 }
2228
2229 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2230 if (net_ratelimit())
2231 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2232 dev->name);
cd28ab6a
SH		 2233
2234 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2235 }
2236
2237 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2238 if (net_ratelimit())
2239 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2240 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2241 }
2242
2243 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2244 if (net_ratelimit())
2245 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2246 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2247 }
2248
2249 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2250 if (net_ratelimit())
2251 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2252 dev->name);
cd28ab6a
SH		 2253 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2254 }
2255}
2256
2257static void sky2_hw_intr(struct sky2_hw *hw)
2258{
2259 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2260
793b883e 2261 if (status & Y2_IS_TIST_OV)
cd28ab6a 2262 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2263
2264 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2265 u16 pci_err;
2266
56a645cc 2267 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2268 if (net_ratelimit())
b02a9258
SH		 2269 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2270 pci_err);
cd28ab6a
SH		 2271
2272 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2273 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2274 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2275 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2276 }
2277
2278 if (status & Y2_IS_PCI_EXP) {
d571b694 2279 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2280 u32 pex_err;
2281
7bd656d1 2282 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2283
3be92a70 2284 if (net_ratelimit())
b02a9258
SH		 2285 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2286 pex_err);
cd28ab6a
SH		 2287
2288 /* clear the interrupt */
2289 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2290 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2291 0xffffffffUL);
cd28ab6a
SH		 2292 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2293
7bd656d1 2294 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2295 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2296 hwmsk &= ~Y2_IS_PCI_EXP;
2297 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2298 }
2299 }
2300
2301 if (status & Y2_HWE_L1_MASK)
2302 sky2_hw_error(hw, 0, status);
2303 status >>= 8;
2304 if (status & Y2_HWE_L1_MASK)
2305 sky2_hw_error(hw, 1, status);
2306}
2307
2308static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2309{
2310 struct net_device *dev = hw->dev[port];
2311 struct sky2_port *sky2 = netdev_priv(dev);
2312 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2313
2314 if (netif_msg_intr(sky2))
2315 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2316 dev->name, status);
2317
2318 if (status & GM_IS_RX_FF_OR) {
2319 ++sky2->net_stats.rx_fifo_errors;
2320 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2321 }
2322
2323 if (status & GM_IS_TX_FF_UR) {
2324 ++sky2->net_stats.tx_fifo_errors;
2325 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2326 }
cd28ab6a
SH		 2327}
2328
d257924e
SH		 2329/* This should never happen it is a fatal situation */
2330static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2331 const char *rxtx, u32 mask)
2332{
2333 struct net_device *dev = hw->dev[port];
2334 struct sky2_port *sky2 = netdev_priv(dev);
2335 u32 imask;
2336
2337 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2338 dev ? dev->name : "<not registered>", rxtx);
2339
2340 imask = sky2_read32(hw, B0_IMSK);
2341 imask &= ~mask;
2342 sky2_write32(hw, B0_IMSK, imask);
2343
2344 if (dev) {
2345 spin_lock(&sky2->phy_lock);
2346 sky2_link_down(sky2);
2347 spin_unlock(&sky2->phy_lock);
2348 }
2349}
cd28ab6a 2350
d27ed387
SH		 2351/* If idle then force a fake soft NAPI poll once a second
2352 * to work around cases where sharing an edge triggered interrupt.
2353 */
eb35cf60
SH		 2354static inline void sky2_idle_start(struct sky2_hw *hw)
2355{
2356 if (idle_timeout > 0)
2357 mod_timer(&hw->idle_timer,
2358 jiffies + msecs_to_jiffies(idle_timeout));
2359}
2360
d27ed387
SH		 2361static void sky2_idle(unsigned long arg)
2362{
01bd7564
SH		 2363 struct sky2_hw *hw = (struct sky2_hw *) arg;
2364 struct net_device *dev = hw->dev[0];
d27ed387 2365
d27ed387
SH		 2366 if (__netif_rx_schedule_prep(dev))
2367 __netif_rx_schedule(dev);
01bd7564
SH		 2368
2369 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2370}
2371
2372
e07b1aa8 2373static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2374{
e07b1aa8
SH		 2375 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2376 int work_limit = min(dev0->quota, *budget);
2377 int work_done = 0;
fb2690a9 2378 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2379
1e5f1283
SH		 2380 if (status & Y2_IS_HW_ERR)
2381 sky2_hw_intr(hw);
d257924e 2382
1e5f1283
SH		 2383 if (status & Y2_IS_IRQ_PHY1)
2384 sky2_phy_intr(hw, 0);
cd28ab6a 2385
1e5f1283
SH		 2386 if (status & Y2_IS_IRQ_PHY2)
2387 sky2_phy_intr(hw, 1);
cd28ab6a 2388
1e5f1283
SH		 2389 if (status & Y2_IS_IRQ_MAC1)
2390 sky2_mac_intr(hw, 0);
cd28ab6a 2391
1e5f1283
SH		 2392 if (status & Y2_IS_IRQ_MAC2)
2393 sky2_mac_intr(hw, 1);
cd28ab6a 2394
1e5f1283
SH		 2395 if (status & Y2_IS_CHK_RX1)
2396 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2397
1e5f1283
SH		 2398 if (status & Y2_IS_CHK_RX2)
2399 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2400
1e5f1283
SH		 2401 if (status & Y2_IS_CHK_TXA1)
2402 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2403
1e5f1283
SH		 2404 if (status & Y2_IS_CHK_TXA2)
2405 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2406
1e5f1283 2407 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2408 if (work_done < work_limit) {
2409 netif_rx_complete(dev0);
86fba634 2410
fe2a24df
SH		 2411 sky2_read32(hw, B0_Y2_SP_LISR);
2412 return 0;
2413 } else {
2414 *budget -= work_done;
2415 dev0->quota -= work_done;
1e5f1283 2416 return 1;
fe2a24df 2417 }
e07b1aa8
SH		 2418}
2419
7d12e780 2420static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2421{
2422 struct sky2_hw *hw = dev_id;
2423 struct net_device *dev0 = hw->dev[0];
2424 u32 status;
2425
2426 /* Reading this mask interrupts as side effect */
2427 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2428 if (status == 0 || status == ~0)
2429 return IRQ_NONE;
793b883e 2430
e07b1aa8
SH		 2431 prefetch(&hw->st_le[hw->st_idx]);
2432 if (likely(__netif_rx_schedule_prep(dev0)))
2433 __netif_rx_schedule(dev0);
793b883e 2434
cd28ab6a
SH		 2435 return IRQ_HANDLED;
2436}
2437
2438#ifdef CONFIG_NET_POLL_CONTROLLER
2439static void sky2_netpoll(struct net_device *dev)
2440{
2441 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2442 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2443
88d11360
SH		 2444 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2445 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2446}
2447#endif
2448
2449/* Chip internal frequency for clock calculations */
fb17358f 2450static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2451{
793b883e 2452 switch (hw->chip_id) {
cd28ab6a 2453 case CHIP_ID_YUKON_EC:
5a5b1ea0 2454 case CHIP_ID_YUKON_EC_U:
93745494 2455 case CHIP_ID_YUKON_EX:
fb17358f 2456 return 125; /* 125 Mhz */
cd28ab6a 2457 case CHIP_ID_YUKON_FE:
fb17358f 2458 return 100; /* 100 Mhz */
793b883e 2459 default: /* YUKON_XL */
fb17358f 2460 return 156; /* 156 Mhz */
cd28ab6a
SH		 2461 }
2462}
2463
fb17358f 2464static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2465{
fb17358f 2466 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2467}
2468
fb17358f 2469static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2470{
fb17358f 2471 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2472}
2473
fb17358f 2474
e3173832 2475static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2476{
b89165f2 2477 u8 t8;
cd28ab6a 2478
cd28ab6a 2479 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2480
cd28ab6a
SH		 2481 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2482 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2483 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2484 hw->chip_id);
cd28ab6a
SH		 2485 return -EOPNOTSUPP;
2486 }
2487
93745494
SH		 2488 if (hw->chip_id == CHIP_ID_YUKON_EX)
2489 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2490 "Please report success or failure to <netdev@vger.kernel.org>\n");
2491
2492 /* Make sure and enable all clocks */
2493 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2494 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2495
290d4de5
SH		 2496 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2497
2498 /* This rev is really old, and requires untested workarounds */
2499 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2500 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2501 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2502 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2503 return -EOPNOTSUPP;
2504 }
2505
e3173832
SH		 2506 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2507 hw->ports = 1;
2508 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2509 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2510 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2511 ++hw->ports;
2512 }
2513
2514 return 0;
2515}
2516
2517static void sky2_reset(struct sky2_hw *hw)
2518{
2519 u16 status;
2520 int i;
2521
cd28ab6a
SH		 2522 /* disable ASF */
2523 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
93745494
SH		 2524 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2525 status = sky2_read16(hw, HCU_CCSR);
2526 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2527 HCU_CCSR_UC_STATE_MSK);
2528 sky2_write16(hw, HCU_CCSR, status);
2529 } else
2530 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
cd28ab6a
SH		 2531 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2532 }
2533
2534 /* do a SW reset */
2535 sky2_write8(hw, B0_CTST, CS_RST_SET);
2536 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2537
2538 /* clear PCI errors, if any */
56a645cc 2539 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2540
cd28ab6a 2541 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2542 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2543
cd28ab6a
SH		 2544
2545 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2546
2547 /* clear any PEX errors */
7bd656d1
SH		 2548 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2549 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2550
cd28ab6a 2551
ae306cca 2552 sky2_power_on(hw);
cd28ab6a
SH		 2553
2554 for (i = 0; i < hw->ports; i++) {
2555 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2556 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2557 }
2558
2559 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2560
793b883e
SH		 2561 /* Clear I2C IRQ noise */
2562 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2563
2564 /* turn off hardware timer (unused) */
2565 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2566 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2567
cd28ab6a
SH		 2568 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2569
69634ee7
SH		 2570 /* Turn off descriptor polling */
2571 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2572
2573 /* Turn off receive timestamp */
2574 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2575 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2576
2577 /* enable the Tx Arbiters */
2578 for (i = 0; i < hw->ports; i++)
2579 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2580
2581 /* Initialize ram interface */
2582 for (i = 0; i < hw->ports; i++) {
793b883e 2583 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2584
2585 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2586 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2587 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2588 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2589 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2590 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2591 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2592 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2593 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2594 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2595 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2596 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2597 }
2598
7bd656d1 2599 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2600
cd28ab6a 2601 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2602 sky2_gmac_reset(hw, i);
cd28ab6a 2603
cd28ab6a
SH		 2604 memset(hw->st_le, 0, STATUS_LE_BYTES);
2605 hw->st_idx = 0;
2606
2607 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2608 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2609
2610 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2611 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2612
2613 /* Set the list last index */
793b883e 2614 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2615
290d4de5
SH		 2616 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2617 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2618
290d4de5
SH		 2619 /* set Status-FIFO ISR watermark */
2620 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2621 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2622 else
2623 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2624
290d4de5 2625 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2626 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2627 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2628
793b883e 2629 /* enable status unit */
cd28ab6a
SH		 2630 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2631
2632 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2633 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2634 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2635}
2636
2637static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2638{
2639 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2640}
2641
2642static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2643{
2644 const struct sky2_port *sky2 = netdev_priv(dev);
2645
2646 wol->supported = sky2_wol_supported(sky2->hw);
2647 wol->wolopts = sky2->wol;
2648}
2649
2650static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2651{
2652 struct sky2_port *sky2 = netdev_priv(dev);
2653 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2654
e3173832
SH		 2655 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2656 return -EOPNOTSUPP;
2657
2658 sky2->wol = wol->wolopts;
2659
2660 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2661 sky2_write32(hw, B0_CTST, sky2->wol
2662 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2663
2664 if (!netif_running(dev))
2665 sky2_wol_init(sky2);
cd28ab6a
SH		 2666 return 0;
2667}
2668
28bd181a 2669static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2670{
b89165f2
SH		 2671 if (sky2_is_copper(hw)) {
2672 u32 modes = SUPPORTED_10baseT_Half
2673 | SUPPORTED_10baseT_Full
2674 | SUPPORTED_100baseT_Half
2675 | SUPPORTED_100baseT_Full
2676 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2677
2678 if (hw->chip_id != CHIP_ID_YUKON_FE)
2679 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2680 | SUPPORTED_1000baseT_Full;
2681 return modes;
cd28ab6a 2682 } else
b89165f2
SH		 2683 return SUPPORTED_1000baseT_Half
2684 | SUPPORTED_1000baseT_Full
2685 | SUPPORTED_Autoneg
2686 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2687}
2688
793b883e 2689static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2690{
2691 struct sky2_port *sky2 = netdev_priv(dev);
2692 struct sky2_hw *hw = sky2->hw;
2693
2694 ecmd->transceiver = XCVR_INTERNAL;
2695 ecmd->supported = sky2_supported_modes(hw);
2696 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2697 if (sky2_is_copper(hw)) {
cd28ab6a 2698 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2699 | SUPPORTED_10baseT_Full
2700 | SUPPORTED_100baseT_Half
2701 | SUPPORTED_100baseT_Full
2702 | SUPPORTED_1000baseT_Half
2703 | SUPPORTED_1000baseT_Full
2704 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2705 ecmd->port = PORT_TP;
b89165f2
SH		 2706 ecmd->speed = sky2->speed;
2707 } else {
2708 ecmd->speed = SPEED_1000;
cd28ab6a 2709 ecmd->port = PORT_FIBRE;
b89165f2 2710 }
cd28ab6a
SH		 2711
2712 ecmd->advertising = sky2->advertising;
2713 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2714 ecmd->duplex = sky2->duplex;
2715 return 0;
2716}
2717
2718static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2719{
2720 struct sky2_port *sky2 = netdev_priv(dev);
2721 const struct sky2_hw *hw = sky2->hw;
2722 u32 supported = sky2_supported_modes(hw);
2723
2724 if (ecmd->autoneg == AUTONEG_ENABLE) {
2725 ecmd->advertising = supported;
2726 sky2->duplex = -1;
2727 sky2->speed = -1;
2728 } else {
2729 u32 setting;
2730
793b883e 2731 switch (ecmd->speed) {
cd28ab6a
SH		 2732 case SPEED_1000:
2733 if (ecmd->duplex == DUPLEX_FULL)
2734 setting = SUPPORTED_1000baseT_Full;
2735 else if (ecmd->duplex == DUPLEX_HALF)
2736 setting = SUPPORTED_1000baseT_Half;
2737 else
2738 return -EINVAL;
2739 break;
2740 case SPEED_100:
2741 if (ecmd->duplex == DUPLEX_FULL)
2742 setting = SUPPORTED_100baseT_Full;
2743 else if (ecmd->duplex == DUPLEX_HALF)
2744 setting = SUPPORTED_100baseT_Half;
2745 else
2746 return -EINVAL;
2747 break;
2748
2749 case SPEED_10:
2750 if (ecmd->duplex == DUPLEX_FULL)
2751 setting = SUPPORTED_10baseT_Full;
2752 else if (ecmd->duplex == DUPLEX_HALF)
2753 setting = SUPPORTED_10baseT_Half;
2754 else
2755 return -EINVAL;
2756 break;
2757 default:
2758 return -EINVAL;
2759 }
2760
2761 if ((setting & supported) == 0)
2762 return -EINVAL;
2763
2764 sky2->speed = ecmd->speed;
2765 sky2->duplex = ecmd->duplex;
2766 }
2767
2768 sky2->autoneg = ecmd->autoneg;
2769 sky2->advertising = ecmd->advertising;
2770
1b537565
SH		 2771 if (netif_running(dev))
2772 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2773
2774 return 0;
2775}
2776
2777static void sky2_get_drvinfo(struct net_device *dev,
2778 struct ethtool_drvinfo *info)
2779{
2780 struct sky2_port *sky2 = netdev_priv(dev);
2781
2782 strcpy(info->driver, DRV_NAME);
2783 strcpy(info->version, DRV_VERSION);
2784 strcpy(info->fw_version, "N/A");
2785 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2786}
2787
2788static const struct sky2_stat {
793b883e
SH		 2789 char name[ETH_GSTRING_LEN];
2790 u16 offset;
cd28ab6a
SH		 2791} sky2_stats[] = {
2792 { "tx_bytes", GM_TXO_OK_HI },
2793 { "rx_bytes", GM_RXO_OK_HI },
2794 { "tx_broadcast", GM_TXF_BC_OK },
2795 { "rx_broadcast", GM_RXF_BC_OK },
2796 { "tx_multicast", GM_TXF_MC_OK },
2797 { "rx_multicast", GM_RXF_MC_OK },
2798 { "tx_unicast", GM_TXF_UC_OK },
2799 { "rx_unicast", GM_RXF_UC_OK },
2800 { "tx_mac_pause", GM_TXF_MPAUSE },
2801 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2802 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2803 { "late_collision",GM_TXF_LAT_COL },
2804 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2805 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2806 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2807
d2604540 2808 { "rx_short", GM_RXF_SHT },
cd28ab6a 2809 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2810 { "rx_64_byte_packets", GM_RXF_64B },
2811 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2812 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2813 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2814 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2815 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2816 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2817 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2818 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2819 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2820 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2821
2822 { "tx_64_byte_packets", GM_TXF_64B },
2823 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2824 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2825 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2826 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2827 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2828 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2829 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2830};
2831
cd28ab6a
SH		 2832static u32 sky2_get_rx_csum(struct net_device *dev)
2833{
2834 struct sky2_port *sky2 = netdev_priv(dev);
2835
2836 return sky2->rx_csum;
2837}
2838
2839static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2840{
2841 struct sky2_port *sky2 = netdev_priv(dev);
2842
2843 sky2->rx_csum = data;
793b883e 2844
cd28ab6a
SH		 2845 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2846 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2847
2848 return 0;
2849}
2850
2851static u32 sky2_get_msglevel(struct net_device *netdev)
2852{
2853 struct sky2_port *sky2 = netdev_priv(netdev);
2854 return sky2->msg_enable;
2855}
2856
9a7ae0a9
SH		 2857static int sky2_nway_reset(struct net_device *dev)
2858{
2859 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2860
16ad91e1 2861 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2862 return -EINVAL;
2863
1b537565 2864 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2865
2866 return 0;
2867}
2868
793b883e 2869static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2870{
2871 struct sky2_hw *hw = sky2->hw;
2872 unsigned port = sky2->port;
2873 int i;
2874
2875 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2876 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2877 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2878 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2879
793b883e 2880 for (i = 2; i < count; i++)
cd28ab6a
SH		 2881 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2882}
2883
cd28ab6a
SH		 2884static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2885{
2886 struct sky2_port *sky2 = netdev_priv(netdev);
2887 sky2->msg_enable = value;
2888}
2889
2890static int sky2_get_stats_count(struct net_device *dev)
2891{
2892 return ARRAY_SIZE(sky2_stats);
2893}
2894
2895static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2896 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2897{
2898 struct sky2_port *sky2 = netdev_priv(dev);
2899
793b883e 2900 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2901}
2902
793b883e 2903static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2904{
2905 int i;
2906
2907 switch (stringset) {
2908 case ETH_SS_STATS:
2909 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2910 memcpy(data + i * ETH_GSTRING_LEN,
2911 sky2_stats[i].name, ETH_GSTRING_LEN);
2912 break;
2913 }
2914}
2915
cd28ab6a
SH		 2916static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2917{
2918 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2919 return &sky2->net_stats;
2920}
2921
2922static int sky2_set_mac_address(struct net_device *dev, void *p)
2923{
2924 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2925 struct sky2_hw *hw = sky2->hw;
2926 unsigned port = sky2->port;
2927 const struct sockaddr *addr = p;
cd28ab6a
SH		 2928
2929 if (!is_valid_ether_addr(addr->sa_data))
2930 return -EADDRNOTAVAIL;
2931
cd28ab6a 2932 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2933 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2934 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2935 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2936 dev->dev_addr, ETH_ALEN);
1b537565 2937
a8ab1ec0
SH		 2938 /* virtual address for data */
2939 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2940
2941 /* physical address: used for pause frames */
2942 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2943
2944 return 0;
cd28ab6a
SH		 2945}
2946
a052b52f
SH		 2947static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2948{
2949 u32 bit;
2950
2951 bit = ether_crc(ETH_ALEN, addr) & 63;
2952 filter[bit >> 3] |= 1 << (bit & 7);
2953}
2954
cd28ab6a
SH		 2955static void sky2_set_multicast(struct net_device *dev)
2956{
2957 struct sky2_port *sky2 = netdev_priv(dev);
2958 struct sky2_hw *hw = sky2->hw;
2959 unsigned port = sky2->port;
2960 struct dev_mc_list *list = dev->mc_list;
2961 u16 reg;
2962 u8 filter[8];
a052b52f
SH		 2963 int rx_pause;
2964 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 2965
a052b52f 2966 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 2967 memset(filter, 0, sizeof(filter));
2968
2969 reg = gma_read16(hw, port, GM_RX_CTRL);
2970 reg |= GM_RXCR_UCF_ENA;
2971
d571b694 2972 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2973 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 2974 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 2975 memset(filter, 0xff, sizeof(filter));
a052b52f 2976 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 2977 reg &= ~GM_RXCR_MCF_ENA;
2978 else {
2979 int i;
2980 reg |= GM_RXCR_MCF_ENA;
2981
a052b52f
SH		 2982 if (rx_pause)
2983 sky2_add_filter(filter, pause_mc_addr);
2984
2985 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2986 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 2987 }
2988
cd28ab6a 2989 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2990 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2991 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2992 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2993 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2994 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2995 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2996 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2997
2998 gma_write16(hw, port, GM_RX_CTRL, reg);
2999}
3000
3001/* Can have one global because blinking is controlled by
3002 * ethtool and that is always under RTNL mutex
3003 */
91c86df5 3004static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3005{
793b883e
SH		 3006 u16 pg;
3007
793b883e
SH		 3008 switch (hw->chip_id) {
3009 case CHIP_ID_YUKON_XL:
3010 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3011 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3012 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3013 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3014 PHY_M_LEDC_INIT_CTRL(7) |
3015 PHY_M_LEDC_STA1_CTRL(7) |
3016 PHY_M_LEDC_STA0_CTRL(7))
3017 : 0);
3018
3019 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3020 break;
3021
3022 default:
3023 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3024 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3025 on ? PHY_M_LED_ALL : 0);
793b883e 3026 }
cd28ab6a
SH		 3027}
3028
3029/* blink LED's for finding board */
3030static int sky2_phys_id(struct net_device *dev, u32 data)
3031{
3032 struct sky2_port *sky2 = netdev_priv(dev);
3033 struct sky2_hw *hw = sky2->hw;
3034 unsigned port = sky2->port;
793b883e 3035 u16 ledctrl, ledover = 0;
cd28ab6a 3036 long ms;
91c86df5 3037 int interrupted;
cd28ab6a
SH		 3038 int onoff = 1;
3039
793b883e 3040 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3041 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3042 else
3043 ms = data * 1000;
3044
3045 /* save initial values */
e07b1aa8 3046 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3047 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3048 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3049 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3050 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3051 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3052 } else {
3053 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3054 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3055 }
cd28ab6a 3056
91c86df5
SH		 3057 interrupted = 0;
3058 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3059 sky2_led(hw, port, onoff);
3060 onoff = !onoff;
3061
e07b1aa8 3062 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3063 interrupted = msleep_interruptible(250);
e07b1aa8 3064 spin_lock_bh(&sky2->phy_lock);
91c86df5 3065
cd28ab6a
SH		 3066 ms -= 250;
3067 }
3068
3069 /* resume regularly scheduled programming */
793b883e
SH		 3070 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3071 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3072 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3073 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3074 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3075 } else {
3076 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3077 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3078 }
e07b1aa8 3079 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3080
3081 return 0;
3082}
3083
3084static void sky2_get_pauseparam(struct net_device *dev,
3085 struct ethtool_pauseparam *ecmd)
3086{
3087 struct sky2_port *sky2 = netdev_priv(dev);
3088
16ad91e1
SH		 3089 switch (sky2->flow_mode) {
3090 case FC_NONE:
3091 ecmd->tx_pause = ecmd->rx_pause = 0;
3092 break;
3093 case FC_TX:
3094 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3095 break;
3096 case FC_RX:
3097 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3098 break;
3099 case FC_BOTH:
3100 ecmd->tx_pause = ecmd->rx_pause = 1;
3101 }
3102
cd28ab6a
SH		 3103 ecmd->autoneg = sky2->autoneg;
3104}
3105
3106static int sky2_set_pauseparam(struct net_device *dev,
3107 struct ethtool_pauseparam *ecmd)
3108{
3109 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3110
3111 sky2->autoneg = ecmd->autoneg;
16ad91e1 3112 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3113
16ad91e1
SH		 3114 if (netif_running(dev))
3115 sky2_phy_reinit(sky2);
cd28ab6a 3116
2eaba1a2 3117 return 0;
cd28ab6a
SH		 3118}
3119
fb17358f
SH		 3120static int sky2_get_coalesce(struct net_device *dev,
3121 struct ethtool_coalesce *ecmd)
3122{
3123 struct sky2_port *sky2 = netdev_priv(dev);
3124 struct sky2_hw *hw = sky2->hw;
3125
3126 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3127 ecmd->tx_coalesce_usecs = 0;
3128 else {
3129 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3130 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3131 }
3132 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3133
3134 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3135 ecmd->rx_coalesce_usecs = 0;
3136 else {
3137 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3138 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3139 }
3140 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3141
3142 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3143 ecmd->rx_coalesce_usecs_irq = 0;
3144 else {
3145 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3146 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3147 }
3148
3149 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3150
3151 return 0;
3152}
3153
3154/* Note: this affect both ports */
3155static int sky2_set_coalesce(struct net_device *dev,
3156 struct ethtool_coalesce *ecmd)
3157{
3158 struct sky2_port *sky2 = netdev_priv(dev);
3159 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3160 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3161
77b3d6a2
SH		 3162 if (ecmd->tx_coalesce_usecs > tmax ||
3163 ecmd->rx_coalesce_usecs > tmax ||
3164 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3165 return -EINVAL;
3166
ff81fbbe 3167 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3168 return -EINVAL;
ff81fbbe 3169 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3170 return -EINVAL;
ff81fbbe 3171 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3172 return -EINVAL;
3173
3174 if (ecmd->tx_coalesce_usecs == 0)
3175 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3176 else {
3177 sky2_write32(hw, STAT_TX_TIMER_INI,
3178 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3179 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3180 }
3181 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3182
3183 if (ecmd->rx_coalesce_usecs == 0)
3184 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3185 else {
3186 sky2_write32(hw, STAT_LEV_TIMER_INI,
3187 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3188 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3189 }
3190 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3191
3192 if (ecmd->rx_coalesce_usecs_irq == 0)
3193 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3194 else {
d28d4870 3195 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3196 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3197 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3198 }
3199 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3200 return 0;
3201}
3202
793b883e
SH		 3203static void sky2_get_ringparam(struct net_device *dev,
3204 struct ethtool_ringparam *ering)
3205{
3206 struct sky2_port *sky2 = netdev_priv(dev);
3207
3208 ering->rx_max_pending = RX_MAX_PENDING;
3209 ering->rx_mini_max_pending = 0;
3210 ering->rx_jumbo_max_pending = 0;
3211 ering->tx_max_pending = TX_RING_SIZE - 1;
3212
3213 ering->rx_pending = sky2->rx_pending;
3214 ering->rx_mini_pending = 0;
3215 ering->rx_jumbo_pending = 0;
3216 ering->tx_pending = sky2->tx_pending;
3217}
3218
3219static int sky2_set_ringparam(struct net_device *dev,
3220 struct ethtool_ringparam *ering)
3221{
3222 struct sky2_port *sky2 = netdev_priv(dev);
3223 int err = 0;
3224
3225 if (ering->rx_pending > RX_MAX_PENDING ||
3226 ering->rx_pending < 8 ||
3227 ering->tx_pending < MAX_SKB_TX_LE ||
3228 ering->tx_pending > TX_RING_SIZE - 1)
3229 return -EINVAL;
3230
3231 if (netif_running(dev))
3232 sky2_down(dev);
3233
3234 sky2->rx_pending = ering->rx_pending;
3235 sky2->tx_pending = ering->tx_pending;
3236
1b537565 3237 if (netif_running(dev)) {
793b883e 3238 err = sky2_up(dev);
1b537565
SH		 3239 if (err)
3240 dev_close(dev);
6ed995bb
SH		 3241 else
3242 sky2_set_multicast(dev);
1b537565 3243 }
793b883e
SH		 3244
3245 return err;
3246}
3247
793b883e
SH		 3248static int sky2_get_regs_len(struct net_device *dev)
3249{
6e4cbb34 3250 return 0x4000;
793b883e
SH		 3251}
3252
3253/*
3254 * Returns copy of control register region
6e4cbb34 3255 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3256 */
3257static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3258 void *p)
3259{
3260 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3261 const void __iomem *io = sky2->hw->regs;
793b883e 3262
6e4cbb34 3263 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3264 regs->version = 1;
6e4cbb34 3265 memset(p, 0, regs->len);
793b883e 3266
6e4cbb34
SH		 3267 memcpy_fromio(p, io, B3_RAM_ADDR);
3268
3269 memcpy_fromio(p + B3_RI_WTO_R1,
3270 io + B3_RI_WTO_R1,
3271 regs->len - B3_RI_WTO_R1);
793b883e 3272}
cd28ab6a 3273
7282d491 3274static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3275 .get_settings = sky2_get_settings,
3276 .set_settings = sky2_set_settings,
e3173832
SH		 3277 .get_drvinfo = sky2_get_drvinfo,
3278 .get_wol = sky2_get_wol,
3279 .set_wol = sky2_set_wol,
793b883e
SH		 3280 .get_msglevel = sky2_get_msglevel,
3281 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3282 .nway_reset = sky2_nway_reset,
793b883e
SH		 3283 .get_regs_len = sky2_get_regs_len,
3284 .get_regs = sky2_get_regs,
3285 .get_link = ethtool_op_get_link,
3286 .get_sg = ethtool_op_get_sg,
3287 .set_sg = ethtool_op_set_sg,
3288 .get_tx_csum = ethtool_op_get_tx_csum,
3289 .set_tx_csum = ethtool_op_set_tx_csum,
3290 .get_tso = ethtool_op_get_tso,
3291 .set_tso = ethtool_op_set_tso,
3292 .get_rx_csum = sky2_get_rx_csum,
3293 .set_rx_csum = sky2_set_rx_csum,
3294 .get_strings = sky2_get_strings,
fb17358f
SH		 3295 .get_coalesce = sky2_get_coalesce,
3296 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3297 .get_ringparam = sky2_get_ringparam,
3298 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3299 .get_pauseparam = sky2_get_pauseparam,
3300 .set_pauseparam = sky2_set_pauseparam,
793b883e 3301 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3302 .get_stats_count = sky2_get_stats_count,
3303 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3304 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3305};
3306
3307/* Initialize network device */
3308static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3309 unsigned port,
3310 int highmem, int wol)
cd28ab6a
SH		 3311{
3312 struct sky2_port *sky2;
3313 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3314
3315 if (!dev) {
b02a9258 3316 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3317 return NULL;
3318 }
3319
3320 SET_MODULE_OWNER(dev);
3321 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3322 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3323 dev->open = sky2_up;
3324 dev->stop = sky2_down;
ef743d33 3325 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3326 dev->hard_start_xmit = sky2_xmit_frame;
3327 dev->get_stats = sky2_get_stats;
3328 dev->set_multicast_list = sky2_set_multicast;
3329 dev->set_mac_address = sky2_set_mac_address;
3330 dev->change_mtu = sky2_change_mtu;
3331 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3332 dev->tx_timeout = sky2_tx_timeout;
3333 dev->watchdog_timeo = TX_WATCHDOG;
3334 if (port == 0)
3335 dev->poll = sky2_poll;
3336 dev->weight = NAPI_WEIGHT;
3337#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3338 /* Network console (only works on port 0)
3339 * because netpoll makes assumptions about NAPI
3340 */
3341 if (port == 0)
3342 dev->poll_controller = sky2_netpoll;
cd28ab6a 3343#endif
cd28ab6a
SH		 3344
3345 sky2 = netdev_priv(dev);
3346 sky2->netdev = dev;
3347 sky2->hw = hw;
3348 sky2->msg_enable = netif_msg_init(debug, default_msg);
3349
cd28ab6a
SH		 3350 /* Auto speed and flow control */
3351 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3352 sky2->flow_mode = FC_BOTH;
3353
cd28ab6a
SH		 3354 sky2->duplex = -1;
3355 sky2->speed = -1;
3356 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3357 sky2->rx_csum = 1;
e3173832 3358 sky2->wol = wol;
75d070c5 3359
e07b1aa8 3360 spin_lock_init(&sky2->phy_lock);
793b883e 3361 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3362 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3363
3364 hw->dev[port] = dev;
3365
3366 sky2->port = port;
3367
4a50a876 3368 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3369 if (highmem)
3370 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3371
d1f13708
SH		 3372#ifdef SKY2_VLAN_TAG_USED
3373 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3374 dev->vlan_rx_register = sky2_vlan_rx_register;
3375 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3376#endif
3377
cd28ab6a 3378 /* read the mac address */
793b883e 3379 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3380 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3381
3382 /* device is off until link detection */
3383 netif_carrier_off(dev);
3384 netif_stop_queue(dev);
3385
3386 return dev;
3387}
3388
28bd181a 3389static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3390{
3391 const struct sky2_port *sky2 = netdev_priv(dev);
3392
3393 if (netif_msg_probe(sky2))
3394 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3395 dev->name,
3396 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3397 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3398}
3399
fb2690a9 3400/* Handle software interrupt used during MSI test */
7d12e780 3401static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3402{
3403 struct sky2_hw *hw = dev_id;
3404 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3405
3406 if (status == 0)
3407 return IRQ_NONE;
3408
3409 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3410 hw->msi = 1;
fb2690a9
SH		 3411 wake_up(&hw->msi_wait);
3412 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3413 }
3414 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3415
3416 return IRQ_HANDLED;
3417}
3418
3419/* Test interrupt path by forcing a a software IRQ */
3420static int __devinit sky2_test_msi(struct sky2_hw *hw)
3421{
3422 struct pci_dev *pdev = hw->pdev;
3423 int err;
3424
bb507fe1
SH		 3425 init_waitqueue_head (&hw->msi_wait);
3426
fb2690a9
SH		 3427 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3428
b0a20ded 3429 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3430 if (err) {
b02a9258 3431 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3432 return err;
3433 }
3434
fb2690a9 3435 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3436 sky2_read8(hw, B0_CTST);
fb2690a9 3437
b0a20ded 3438 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3439
b0a20ded 3440 if (!hw->msi) {
fb2690a9 3441 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3442 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3443 "switching to INTx mode.\n");
fb2690a9
SH		 3444
3445 err = -EOPNOTSUPP;
3446 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3447 }
3448
3449 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3450 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3451
3452 free_irq(pdev->irq, hw);
3453
3454 return err;
3455}
3456
e3173832
SH		 3457static int __devinit pci_wake_enabled(struct pci_dev *dev)
3458{
3459 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3460 u16 value;
3461
3462 if (!pm)
3463 return 0;
3464 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3465 return 0;
3466 return value & PCI_PM_CTRL_PME_ENABLE;
3467}
3468
cd28ab6a
SH		 3469static int __devinit sky2_probe(struct pci_dev *pdev,
3470 const struct pci_device_id *ent)
3471{
7f60c64b 3472 struct net_device *dev;
cd28ab6a 3473 struct sky2_hw *hw;
e3173832 3474 int err, using_dac = 0, wol_default;
cd28ab6a 3475
793b883e
SH		 3476 err = pci_enable_device(pdev);
3477 if (err) {
b02a9258 3478 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3479 goto err_out;
3480 }
3481
793b883e
SH		 3482 err = pci_request_regions(pdev, DRV_NAME);
3483 if (err) {
b02a9258 3484 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
793b883e 3485 goto err_out;
cd28ab6a
SH		 3486 }
3487
3488 pci_set_master(pdev);
3489
d1f3d4dd
SH		 3490 if (sizeof(dma_addr_t) > sizeof(u32) &&
3491 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3492 using_dac = 1;
3493 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3494 if (err < 0) {
b02a9258
SH		 3495 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3496 "for consistent allocations\n");
d1f3d4dd
SH		 3497 goto err_out_free_regions;
3498 }
d1f3d4dd 3499 } else {
cd28ab6a
SH		 3500 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3501 if (err) {
b02a9258 3502 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3503 goto err_out_free_regions;
3504 }
3505 }
d1f3d4dd 3506
e3173832
SH		 3507 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3508
cd28ab6a 3509 err = -ENOMEM;
6aad85d6 3510 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3511 if (!hw) {
b02a9258 3512 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3513 goto err_out_free_regions;
3514 }
3515
cd28ab6a 3516 hw->pdev = pdev;
cd28ab6a
SH		 3517
3518 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3519 if (!hw->regs) {
b02a9258 3520 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3521 goto err_out_free_hw;
3522 }
3523
56a645cc 3524#ifdef __BIG_ENDIAN
f65b138c
SH		 3525 /* The sk98lin vendor driver uses hardware byte swapping but
3526 * this driver uses software swapping.
3527 */
56a645cc
SH		 3528 {
3529 u32 reg;
56a645cc 3530 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3531 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3532 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3533 }
3534#endif
3535
08c06d8a
SH		 3536 /* ring for status responses */
3537 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3538 &hw->st_dma);
3539 if (!hw->st_le)
3540 goto err_out_iounmap;
3541
e3173832 3542 err = sky2_init(hw);
cd28ab6a 3543 if (err)
793b883e 3544 goto err_out_iounmap;
cd28ab6a 3545
b02a9258 3546 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3547 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3548 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3549 hw->chip_id, hw->chip_rev);
cd28ab6a 3550
e3173832
SH		 3551 sky2_reset(hw);
3552
3553 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3554 if (!dev) {
3555 err = -ENOMEM;
cd28ab6a 3556 goto err_out_free_pci;
7f60c64b 3557 }
cd28ab6a 3558
9fa1b1f3
SH		 3559 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3560 err = sky2_test_msi(hw);
3561 if (err == -EOPNOTSUPP)
3562 pci_disable_msi(pdev);
3563 else if (err)
3564 goto err_out_free_netdev;
3565 }
3566
793b883e
SH		 3567 err = register_netdev(dev);
3568 if (err) {
b02a9258 3569 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 3570 goto err_out_free_netdev;
3571 }
3572
b0a20ded
SH		 3573 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3574 dev->name, hw);
9fa1b1f3 3575 if (err) {
b02a9258 3576 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 3577 goto err_out_unregister;
3578 }
3579 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3580
cd28ab6a
SH		 3581 sky2_show_addr(dev);
3582
7f60c64b 3583 if (hw->ports > 1) {
3584 struct net_device *dev1;
3585
e3173832 3586 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 3587 if (!dev1)
3588 dev_warn(&pdev->dev, "allocation for second device failed\n");
3589 else if ((err = register_netdev(dev1))) {
3590 dev_warn(&pdev->dev,
3591 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 3592 hw->dev[1] = NULL;
3593 free_netdev(dev1);
b02a9258
SH		 3594 } else
3595 sky2_show_addr(dev1);
cd28ab6a
SH		 3596 }
3597
01bd7564 3598 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3599 sky2_idle_start(hw);
d27ed387 3600
793b883e
SH		 3601 pci_set_drvdata(pdev, hw);
3602
cd28ab6a
SH		 3603 return 0;
3604
793b883e 3605err_out_unregister:
b0a20ded
SH		 3606 if (hw->msi)
3607 pci_disable_msi(pdev);
793b883e 3608 unregister_netdev(dev);
cd28ab6a
SH		 3609err_out_free_netdev:
3610 free_netdev(dev);
cd28ab6a 3611err_out_free_pci:
793b883e 3612 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3613 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3614err_out_iounmap:
3615 iounmap(hw->regs);
3616err_out_free_hw:
3617 kfree(hw);
3618err_out_free_regions:
3619 pci_release_regions(pdev);
cd28ab6a 3620 pci_disable_device(pdev);
cd28ab6a
SH		 3621err_out:
3622 return err;
3623}
3624
3625static void __devexit sky2_remove(struct pci_dev *pdev)
3626{
793b883e 3627 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3628 struct net_device *dev0, *dev1;
3629
793b883e 3630 if (!hw)
cd28ab6a
SH		 3631 return;
3632
d27ed387
SH		 3633 del_timer_sync(&hw->idle_timer);
3634
3635 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3636 synchronize_irq(hw->pdev->irq);
3637
cd28ab6a 3638 dev0 = hw->dev[0];
793b883e
SH		 3639 dev1 = hw->dev[1];
3640 if (dev1)
3641 unregister_netdev(dev1);
cd28ab6a
SH		 3642 unregister_netdev(dev0);
3643
ae306cca
SH		 3644 sky2_power_aux(hw);
3645
cd28ab6a 3646 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3647 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3648 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3649
3650 free_irq(pdev->irq, hw);
b0a20ded
SH		 3651 if (hw->msi)
3652 pci_disable_msi(pdev);
793b883e 3653 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3654 pci_release_regions(pdev);
3655 pci_disable_device(pdev);
793b883e 3656
cd28ab6a
SH		 3657 if (dev1)
3658 free_netdev(dev1);
3659 free_netdev(dev0);
3660 iounmap(hw->regs);
3661 kfree(hw);
5afa0a9c 3662
cd28ab6a
SH		 3663 pci_set_drvdata(pdev, NULL);
3664}
3665
3666#ifdef CONFIG_PM
3667static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3668{
793b883e 3669 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 3670 int i, wol = 0;
cd28ab6a 3671
eb35cf60 3672 del_timer_sync(&hw->idle_timer);
6a5706b9 3673 netif_poll_disable(hw->dev[0]);
eb35cf60 3674
f05267e7 3675 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3676 struct net_device *dev = hw->dev[i];
e3173832 3677 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3678
e3173832 3679 if (netif_running(dev))
5afa0a9c 3680 sky2_down(dev);
e3173832
SH		 3681
3682 if (sky2->wol)
3683 sky2_wol_init(sky2);
3684
3685 wol |= sky2->wol;
cd28ab6a
SH		 3686 }
3687
8ab8fca2 3688 sky2_write32(hw, B0_IMSK, 0);
ae306cca 3689 sky2_power_aux(hw);
e3173832 3690
d374c1c1 3691 pci_save_state(pdev);
e3173832 3692 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 3693 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3694
2ccc99b7 3695 return 0;
cd28ab6a
SH		 3696}
3697
3698static int sky2_resume(struct pci_dev *pdev)
3699{
793b883e 3700 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3701 int i, err;
cd28ab6a 3702
ae306cca
SH		 3703 err = pci_set_power_state(pdev, PCI_D0);
3704 if (err)
3705 goto out;
3706
3707 err = pci_restore_state(pdev);
3708 if (err)
3709 goto out;
3710
cd28ab6a 3711 pci_enable_wake(pdev, PCI_D0, 0);
e3173832 3712 sky2_reset(hw);
cd28ab6a 3713
8ab8fca2
SH		 3714 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3715
f05267e7 3716 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3717 struct net_device *dev = hw->dev[i];
6a5706b9 3718 if (netif_running(dev)) {
08c06d8a
SH		 3719 err = sky2_up(dev);
3720 if (err) {
3721 printk(KERN_ERR PFX "%s: could not up: %d\n",
3722 dev->name, err);
3723 dev_close(dev);
eb35cf60 3724 goto out;
5afa0a9c 3725 }
cd28ab6a
SH		 3726 }
3727 }
eb35cf60 3728
6a5706b9 3729 netif_poll_enable(hw->dev[0]);
eb35cf60 3730 sky2_idle_start(hw);
ae306cca 3731 return 0;
08c06d8a 3732out:
b02a9258 3733 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 3734 pci_disable_device(pdev);
08c06d8a 3735 return err;
cd28ab6a
SH		 3736}
3737#endif
3738
e3173832
SH		 3739static void sky2_shutdown(struct pci_dev *pdev)
3740{
3741 struct sky2_hw *hw = pci_get_drvdata(pdev);
3742 int i, wol = 0;
3743
3744 del_timer_sync(&hw->idle_timer);
3745 netif_poll_disable(hw->dev[0]);
3746
3747 for (i = 0; i < hw->ports; i++) {
3748 struct net_device *dev = hw->dev[i];
3749 struct sky2_port *sky2 = netdev_priv(dev);
3750
3751 if (sky2->wol) {
3752 wol = 1;
3753 sky2_wol_init(sky2);
3754 }
3755 }
3756
3757 if (wol)
3758 sky2_power_aux(hw);
3759
3760 pci_enable_wake(pdev, PCI_D3hot, wol);
3761 pci_enable_wake(pdev, PCI_D3cold, wol);
3762
3763 pci_disable_device(pdev);
3764 pci_set_power_state(pdev, PCI_D3hot);
3765
3766}
3767
cd28ab6a 3768static struct pci_driver sky2_driver = {
793b883e
SH		 3769 .name = DRV_NAME,
3770 .id_table = sky2_id_table,
3771 .probe = sky2_probe,
3772 .remove = __devexit_p(sky2_remove),
cd28ab6a 3773#ifdef CONFIG_PM
793b883e
SH		 3774 .suspend = sky2_suspend,
3775 .resume = sky2_resume,
cd28ab6a 3776#endif
e3173832 3777 .shutdown = sky2_shutdown,
cd28ab6a
SH		 3778};
3779
3780static int __init sky2_init_module(void)
3781{
50241c4c 3782 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3783}
3784
3785static void __exit sky2_cleanup_module(void)
3786{
3787 pci_unregister_driver(&sky2_driver);
3788}
3789
3790module_init(sky2_init_module);
3791module_exit(sky2_cleanup_module);
3792
3793MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 3794MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 3795MODULE_LICENSE("GPL");
5f4f9dc1 3796MODULE_VERSION(DRV_VERSION);
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