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MIPS: Drop unnecessary CONFIG_ISA from RBTX49XX
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
93cd791e 53#define DRV_VERSION "1.14"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 66#define RX_SKB_ALIGN 8
22e11703 67#define RX_BUF_WRITE 16
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
cb5d9547
SH		 80#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
cd28ab6a 82static const u32 default_msg =
793b883e
SH		 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 86
793b883e 87static int debug = -1; /* defaults above */
cd28ab6a
SH		 88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
14d0263f 91static int copybreak __read_mostly = 128;
bdb5c58e
SH		 92module_param(copybreak, int, 0);
93MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
fb2690a9
SH		 95static int disable_msi = 0;
96module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
e561a83b 99static int idle_timeout = 0;
01bd7564 100module_param(idle_timeout, int, 0);
e561a83b 101MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 102
cd28ab6a 103static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
0a17e4c2
SH		 127#ifdef broken
128 /* This device causes data corruption problems that are not resolved */
e5b74c7d 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
0a17e4c2 130#endif
e5b74c7d
SH		 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 137 { 0 }
138};
793b883e 139
cd28ab6a
SH		 140MODULE_DEVICE_TABLE(pci, sky2_id_table);
141
142/* Avoid conditionals by using array */
143static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
144static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 145static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 146
92f965e8
SH		 147/* This driver supports yukon2 chipset only */
148static const char *yukon2_name[] = {
149 "XL", /* 0xb3 */
150 "EC Ultra", /* 0xb4 */
93745494 151 "Extreme", /* 0xb5 */
92f965e8
SH		 152 "EC", /* 0xb6 */
153 "FE", /* 0xb7 */
793b883e
SH		 154};
155
793b883e 156/* Access to external PHY */
ef743d33 157static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 158{
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 166 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
793b883e 168 udelay(1);
cd28ab6a 169 }
ef743d33 170
793b883e 171 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 172 return -ETIMEDOUT;
cd28ab6a
SH		 173}
174
ef743d33 175static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 176{
177 int i;
178
793b883e 179 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 180 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
181
182 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 183 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
184 *val = gma_read16(hw, port, GM_SMI_DATA);
185 return 0;
186 }
187
793b883e 188 udelay(1);
cd28ab6a
SH		 189 }
190
ef743d33
SH		 191 return -ETIMEDOUT;
192}
193
194static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
195{
196 u16 v;
197
198 if (__gm_phy_read(hw, port, reg, &v) != 0)
199 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
200 return v;
cd28ab6a
SH		 201}
202
5afa0a9c 203
ae306cca
SH		 204static void sky2_power_on(struct sky2_hw *hw)
205{
206 /* switch power to VCC (WA for VAUX problem) */
207 sky2_write8(hw, B0_POWER_CTRL,
208 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 209
ae306cca
SH		 210 /* disable Core Clock Division, */
211 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 212
ae306cca
SH		 213 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
214 /* enable bits are inverted */
215 sky2_write8(hw, B2_Y2_CLK_GATE,
216 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
217 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
218 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
219 else
220 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 221
93745494 222 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
ae306cca 223 u32 reg1;
5afa0a9c 224
ae306cca
SH		 225 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
226 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
227 reg1 &= P_ASPM_CONTROL_MSK;
228 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
229 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
5afa0a9c 230 }
ae306cca 231}
5afa0a9c 232
ae306cca
SH		 233static void sky2_power_aux(struct sky2_hw *hw)
234{
235 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
236 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
237 else
238 /* enable bits are inverted */
239 sky2_write8(hw, B2_Y2_CLK_GATE,
240 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
241 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
242 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
243
244 /* switch power to VAUX */
245 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
246 sky2_write8(hw, B0_POWER_CTRL,
247 (PC_VAUX_ENA | PC_VCC_ENA |
248 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 249}
250
d3bcfbeb 251static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 252{
253 u16 reg;
254
255 /* disable all GMAC IRQ's */
256 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
257 /* disable PHY IRQs */
258 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 259
cd28ab6a
SH		 260 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
261 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
262 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
263 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
264
265 reg = gma_read16(hw, port, GM_RX_CTRL);
266 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
267 gma_write16(hw, port, GM_RX_CTRL, reg);
268}
269
16ad91e1
SH		 270/* flow control to advertise bits */
271static const u16 copper_fc_adv[] = {
272 [FC_NONE] = 0,
273 [FC_TX] = PHY_M_AN_ASP,
274 [FC_RX] = PHY_M_AN_PC,
275 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
276};
277
278/* flow control to advertise bits when using 1000BaseX */
279static const u16 fiber_fc_adv[] = {
280 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
281 [FC_TX] = PHY_M_P_ASYM_MD_X,
282 [FC_RX] = PHY_M_P_SYM_MD_X,
283 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
284};
285
286/* flow control to GMA disable bits */
287static const u16 gm_fc_disable[] = {
288 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
289 [FC_TX] = GM_GPCR_FC_RX_DIS,
290 [FC_RX] = GM_GPCR_FC_TX_DIS,
291 [FC_BOTH] = 0,
292};
293
294
cd28ab6a
SH		 295static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
296{
297 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 298 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 299
93745494
SH		 300 if (sky2->autoneg == AUTONEG_ENABLE
301 && !(hw->chip_id == CHIP_ID_YUKON_XL
302 || hw->chip_id == CHIP_ID_YUKON_EC_U
303 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 304 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
305
306 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 307 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 308 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
309
310 if (hw->chip_id == CHIP_ID_YUKON_EC)
311 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
312 else
313 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
314
315 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
316 }
317
318 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 319 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 320 if (hw->chip_id == CHIP_ID_YUKON_FE) {
321 /* enable automatic crossover */
322 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
323 } else {
324 /* disable energy detect */
325 ctrl &= ~PHY_M_PC_EN_DET_MSK;
326
327 /* enable automatic crossover */
328 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
329
93745494
SH		 330 if (sky2->autoneg == AUTONEG_ENABLE
331 && (hw->chip_id == CHIP_ID_YUKON_XL
332 || hw->chip_id == CHIP_ID_YUKON_EC_U
333 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 334 ctrl &= ~PHY_M_PC_DSC_MSK;
335 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
336 }
337 }
cd28ab6a
SH		 338 } else {
339 /* workaround for deviation #4.88 (CRC errors) */
340 /* disable Automatic Crossover */
341
342 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 343 }
cd28ab6a 344
b89165f2
SH		 345 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
346
347 /* special setup for PHY 88E1112 Fiber */
348 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
349 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 350
b89165f2
SH		 351 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
352 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
354 ctrl &= ~PHY_M_MAC_MD_MSK;
355 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
356 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
357
358 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 359 /* select page 1 to access Fiber registers */
360 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 361
362 /* for SFP-module set SIGDET polarity to low */
363 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
364 ctrl |= PHY_M_FIB_SIGD_POL;
365 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 366 }
b89165f2
SH		 367
368 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 369 }
370
7800fddc 371 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 372 ct1000 = 0;
373 adv = PHY_AN_CSMA;
2eaba1a2 374 reg = 0;
cd28ab6a
SH		 375
376 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 377 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 378 if (sky2->advertising & ADVERTISED_1000baseT_Full)
379 ct1000 |= PHY_M_1000C_AFD;
380 if (sky2->advertising & ADVERTISED_1000baseT_Half)
381 ct1000 |= PHY_M_1000C_AHD;
382 if (sky2->advertising & ADVERTISED_100baseT_Full)
383 adv |= PHY_M_AN_100_FD;
384 if (sky2->advertising & ADVERTISED_100baseT_Half)
385 adv |= PHY_M_AN_100_HD;
386 if (sky2->advertising & ADVERTISED_10baseT_Full)
387 adv |= PHY_M_AN_10_FD;
388 if (sky2->advertising & ADVERTISED_10baseT_Half)
389 adv |= PHY_M_AN_10_HD;
709c6e7b 390
16ad91e1 391 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 392 } else { /* special defines for FIBER (88E1040S only) */
393 if (sky2->advertising & ADVERTISED_1000baseT_Full)
394 adv |= PHY_M_AN_1000X_AFD;
395 if (sky2->advertising & ADVERTISED_1000baseT_Half)
396 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 397
16ad91e1 398 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 399 }
cd28ab6a
SH		 400
401 /* Restart Auto-negotiation */
402 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
403 } else {
404 /* forced speed/duplex settings */
405 ct1000 = PHY_M_1000C_MSE;
406
2eaba1a2
SH		 407 /* Disable auto update for duplex flow control and speed */
408 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 409
410 switch (sky2->speed) {
411 case SPEED_1000:
412 ctrl |= PHY_CT_SP1000;
2eaba1a2 413 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 414 break;
415 case SPEED_100:
416 ctrl |= PHY_CT_SP100;
2eaba1a2 417 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 418 break;
419 }
420
2eaba1a2
SH		 421 if (sky2->duplex == DUPLEX_FULL) {
422 reg |= GM_GPCR_DUP_FULL;
423 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 424 } else if (sky2->speed < SPEED_1000)
425 sky2->flow_mode = FC_NONE;
2eaba1a2 426
2eaba1a2 427
16ad91e1 428 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 429
430 /* Forward pause packets to GMAC? */
16ad91e1 431 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 432 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
433 else
434 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 435 }
436
2eaba1a2
SH		 437 gma_write16(hw, port, GM_GP_CTRL, reg);
438
cd28ab6a
SH		 439 if (hw->chip_id != CHIP_ID_YUKON_FE)
440 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
441
442 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
443 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
444
445 /* Setup Phy LED's */
446 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
447 ledover = 0;
448
449 switch (hw->chip_id) {
450 case CHIP_ID_YUKON_FE:
451 /* on 88E3082 these bits are at 11..9 (shifted left) */
452 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
453
454 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
455
456 /* delete ACT LED control bits */
457 ctrl &= ~PHY_M_FELP_LED1_MSK;
458 /* change ACT LED control to blink mode */
459 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
460 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
461 break;
462
463 case CHIP_ID_YUKON_XL:
793b883e 464 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 465
466 /* select page 3 to access LED control register */
467 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
468
469 /* set LED Function Control register */
ed6d32c7
SH		 470 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
471 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
472 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
473 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
474 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 475
476 /* set Polarity Control register */
477 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 478 (PHY_M_POLC_LS1_P_MIX(4) |
479 PHY_M_POLC_IS0_P_MIX(4) |
480 PHY_M_POLC_LOS_CTRL(2) |
481 PHY_M_POLC_INIT_CTRL(2) |
482 PHY_M_POLC_STA1_CTRL(2) |
483 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 484
485 /* restore page register */
793b883e 486 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 487 break;
93745494 488
ed6d32c7 489 case CHIP_ID_YUKON_EC_U:
93745494 490 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 491 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
492
493 /* select page 3 to access LED control register */
494 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
495
496 /* set LED Function Control register */
497 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
498 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
499 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
500 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
501 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
502
503 /* set Blink Rate in LED Timer Control Register */
504 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
505 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
506 /* restore page register */
507 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
508 break;
cd28ab6a
SH		 509
510 default:
511 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
512 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
513 /* turn off the Rx LED (LED_RX) */
0efdf262 514 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 515 }
516
9467a8fc
SH		 517 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
518 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 519 /* apply fixes in PHY AFE */
ed6d32c7
SH		 520 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
521
977bdf06 522 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 523 gm_phy_write(hw, port, 0x18, 0xaa99);
524 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 525
977bdf06 526 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 527 gm_phy_write(hw, port, 0x18, 0xa204);
528 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 529
530 /* set page register to 0 */
9467a8fc 531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
93745494 532 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 533 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 534
977bdf06
SH		 535 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
536 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 537 ledover |= PHY_M_LED_MO_100;
977bdf06 538 }
cd28ab6a 539
977bdf06
SH		 540 if (ledover)
541 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
542
543 }
2eaba1a2 544
d571b694 545 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 546 if (sky2->autoneg == AUTONEG_ENABLE)
547 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
548 else
549 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
550}
551
d3bcfbeb
SH		 552static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
553{
554 u32 reg1;
555 static const u32 phy_power[]
556 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
557
558 /* looks like this XL is back asswards .. */
559 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
560 onoff = !onoff;
561
aed2cec4 562 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 563 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 564 if (onoff)
565 /* Turn off phy power saving */
566 reg1 &= ~phy_power[port];
567 else
568 reg1 |= phy_power[port];
569
570 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 571 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 572 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 573 udelay(100);
574}
575
1b537565
SH		 576/* Force a renegotiation */
577static void sky2_phy_reinit(struct sky2_port *sky2)
578{
e07b1aa8 579 spin_lock_bh(&sky2->phy_lock);
1b537565 580 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 581 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 582}
583
e3173832
SH		 584/* Put device in state to listen for Wake On Lan */
585static void sky2_wol_init(struct sky2_port *sky2)
586{
587 struct sky2_hw *hw = sky2->hw;
588 unsigned port = sky2->port;
589 enum flow_control save_mode;
590 u16 ctrl;
591 u32 reg1;
592
593 /* Bring hardware out of reset */
594 sky2_write16(hw, B0_CTST, CS_RST_CLR);
595 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
596
597 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
598 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
599
600 /* Force to 10/100
601 * sky2_reset will re-enable on resume
602 */
603 save_mode = sky2->flow_mode;
604 ctrl = sky2->advertising;
605
606 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
607 sky2->flow_mode = FC_NONE;
608 sky2_phy_power(hw, port, 1);
609 sky2_phy_reinit(sky2);
610
611 sky2->flow_mode = save_mode;
612 sky2->advertising = ctrl;
613
614 /* Set GMAC to no flow control and auto update for speed/duplex */
615 gma_write16(hw, port, GM_GP_CTRL,
616 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
617 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
618
619 /* Set WOL address */
620 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
621 sky2->netdev->dev_addr, ETH_ALEN);
622
623 /* Turn on appropriate WOL control bits */
624 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
625 ctrl = 0;
626 if (sky2->wol & WAKE_PHY)
627 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
628 else
629 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
630
631 if (sky2->wol & WAKE_MAGIC)
632 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
633 else
634 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
635
636 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
637 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
638
639 /* Turn on legacy PCI-Express PME mode */
640 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
641 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
642 reg1 |= PCI_Y2_PME_LEGACY;
643 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
644 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
645
646 /* block receiver */
647 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
648
649}
650
cd28ab6a
SH		 651static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
652{
653 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
654 u16 reg;
655 int i;
656 const u8 *addr = hw->dev[port]->dev_addr;
657
42eeea01
SH		 658 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
659 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 660
661 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
662
793b883e 663 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 664 /* WA DEV_472 -- looks like crossed wires on port 2 */
665 /* clear GMAC 1 Control reset */
666 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
667 do {
668 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
669 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
670 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
671 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
672 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
673 }
674
793b883e 675 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 676
2eaba1a2
SH		 677 /* Enable Transmit FIFO Underrun */
678 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
679
e07b1aa8 680 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 681 sky2_phy_init(hw, port);
e07b1aa8 682 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 683
684 /* MIB clear */
685 reg = gma_read16(hw, port, GM_PHY_ADDR);
686 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
687
43f2f104
SH		 688 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
689 gma_read16(hw, port, i);
cd28ab6a
SH		 690 gma_write16(hw, port, GM_PHY_ADDR, reg);
691
692 /* transmit control */
693 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
694
695 /* receive control reg: unicast + multicast + no FCS */
696 gma_write16(hw, port, GM_RX_CTRL,
793b883e 697 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 698
699 /* transmit flow control */
700 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
701
702 /* transmit parameter */
703 gma_write16(hw, port, GM_TX_PARAM,
704 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
705 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
706 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
707 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
708
709 /* serial mode register */
710 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 711 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 712
6b1a3aef 713 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 714 reg |= GM_SMOD_JUMBO_ENA;
715
716 gma_write16(hw, port, GM_SERIAL_MODE, reg);
717
cd28ab6a
SH		 718 /* virtual address for data */
719 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
720
793b883e
SH		 721 /* physical address: used for pause frames */
722 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
723
724 /* ignore counter overflows */
cd28ab6a
SH		 725 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
726 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
727 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
728
729 /* Configure Rx MAC FIFO */
730 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 731 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
732 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 733
d571b694 734 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 735 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 736
8df9a876
SH		 737 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
738 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 739
740 /* Configure Tx MAC FIFO */
741 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
742 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 743
93745494 744 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 745 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 746 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98
SH		 747
748 /* set Tx GMAC FIFO Almost Empty Threshold */
749 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
750 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
751
752 if (hw->dev[port]->mtu > ETH_DATA_LEN)
753 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
754 TX_JUMBO_ENA | TX_STFW_DIS);
755 else
756 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
757 TX_JUMBO_DIS | TX_STFW_ENA);
5a5b1ea0
SH		 758 }
759
cd28ab6a
SH		 760}
761
67712901
SH		 762/* Assign Ram Buffer allocation to queue */
763static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 764{
67712901
SH		 765 u32 end;
766
767 /* convert from K bytes to qwords used for hw register */
768 start *= 1024/8;
769 space *= 1024/8;
770 end = start + space - 1;
793b883e 771
cd28ab6a
SH		 772 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
773 sky2_write32(hw, RB_ADDR(q, RB_START), start);
774 sky2_write32(hw, RB_ADDR(q, RB_END), end);
775 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
776 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
777
778 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 779 u32 tp = space - space/4;
793b883e 780
1c28f6ba
SH		 781 /* On receive queue's set the thresholds
782 * give receiver priority when > 3/4 full
783 * send pause when down to 2K
784 */
785 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
786 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 787
1c28f6ba
SH		 788 tp = space - 2048/8;
789 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
790 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 791 } else {
792 /* Enable store & forward on Tx queue's because
793 * Tx FIFO is only 1K on Yukon
794 */
795 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
796 }
797
798 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 799 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 800}
801
cd28ab6a 802/* Setup Bus Memory Interface */
af4ed7e6 803static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 804{
805 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
806 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
807 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 808 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 809}
810
cd28ab6a
SH		 811/* Setup prefetch unit registers. This is the interface between
812 * hardware and driver list elements
813 */
8cc048e3 814static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 815 u64 addr, u32 last)
816{
cd28ab6a
SH		 817 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
818 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
819 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
820 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
821 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
822 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 823
824 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 825}
826
793b883e
SH		 827static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
828{
829 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
830
cb5d9547 831 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 832 le->ctrl = 0;
793b883e
SH		 833 return le;
834}
cd28ab6a 835
291ea614
SH		 836static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
837 struct sky2_tx_le *le)
838{
839 return sky2->tx_ring + (le - sky2->tx_le);
840}
841
290d4de5
SH		 842/* Update chip's next pointer */
843static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 844{
98232f85 845 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 846 wmb();
98232f85
SH		 847 sky2_write16(hw, q, idx);
848 sky2_read16(hw, q);
cd28ab6a
SH		 849}
850
793b883e 851
cd28ab6a
SH		 852static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
853{
854 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 855 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 856 le->ctrl = 0;
cd28ab6a
SH		 857 return le;
858}
859
a018e330
SH		 860/* Return high part of DMA address (could be 32 or 64 bit) */
861static inline u32 high32(dma_addr_t a)
862{
a036119f 863 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 864}
865
14d0263f
SH		 866/* Build description to hardware for one receive segment */
867static void sky2_rx_add(struct sky2_port *sky2, u8 op,
868 dma_addr_t map, unsigned len)
cd28ab6a
SH		 869{
870 struct sky2_rx_le *le;
734d1868 871 u32 hi = high32(map);
cd28ab6a 872
793b883e 873 if (sky2->rx_addr64 != hi) {
cd28ab6a 874 le = sky2_next_rx(sky2);
793b883e 875 le->addr = cpu_to_le32(hi);
cd28ab6a 876 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 877 sky2->rx_addr64 = high32(map + len);
cd28ab6a 878 }
793b883e 879
cd28ab6a 880 le = sky2_next_rx(sky2);
734d1868
SH		 881 le->addr = cpu_to_le32((u32) map);
882 le->length = cpu_to_le16(len);
14d0263f 883 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 884}
885
14d0263f
SH		 886/* Build description to hardware for one possibly fragmented skb */
887static void sky2_rx_submit(struct sky2_port *sky2,
888 const struct rx_ring_info *re)
889{
890 int i;
891
892 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
893
894 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
895 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
896}
897
898
899static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
900 unsigned size)
901{
902 struct sk_buff *skb = re->skb;
903 int i;
904
905 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
906 pci_unmap_len_set(re, data_size, size);
907
908 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
909 re->frag_addr[i] = pci_map_page(pdev,
910 skb_shinfo(skb)->frags[i].page,
911 skb_shinfo(skb)->frags[i].page_offset,
912 skb_shinfo(skb)->frags[i].size,
913 PCI_DMA_FROMDEVICE);
914}
915
916static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
917{
918 struct sk_buff *skb = re->skb;
919 int i;
920
921 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
922 PCI_DMA_FROMDEVICE);
923
924 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
925 pci_unmap_page(pdev, re->frag_addr[i],
926 skb_shinfo(skb)->frags[i].size,
927 PCI_DMA_FROMDEVICE);
928}
793b883e 929
cd28ab6a
SH		 930/* Tell chip where to start receive checksum.
931 * Actually has two checksums, but set both same to avoid possible byte
932 * order problems.
933 */
793b883e 934static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 935{
936 struct sky2_rx_le *le;
937
cd28ab6a 938 le = sky2_next_rx(sky2);
f65b138c 939 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 940 le->ctrl = 0;
941 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 942
793b883e
SH		 943 sky2_write32(sky2->hw,
944 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
945 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 946
947}
948
6b1a3aef
SH		 949/*
950 * The RX Stop command will not work for Yukon-2 if the BMU does not
951 * reach the end of packet and since we can't make sure that we have
952 * incoming data, we must reset the BMU while it is not doing a DMA
953 * transfer. Since it is possible that the RX path is still active,
954 * the RX RAM buffer will be stopped first, so any possible incoming
955 * data will not trigger a DMA. After the RAM buffer is stopped, the
956 * BMU is polled until any DMA in progress is ended and only then it
957 * will be reset.
958 */
959static void sky2_rx_stop(struct sky2_port *sky2)
960{
961 struct sky2_hw *hw = sky2->hw;
962 unsigned rxq = rxqaddr[sky2->port];
963 int i;
964
965 /* disable the RAM Buffer receive queue */
966 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
967
968 for (i = 0; i < 0xffff; i++)
969 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
970 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
971 goto stopped;
972
973 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
974 sky2->netdev->name);
975stopped:
976 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
977
978 /* reset the Rx prefetch unit */
979 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
980}
793b883e 981
d571b694 982/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 983static void sky2_rx_clean(struct sky2_port *sky2)
984{
985 unsigned i;
986
987 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 988 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 989 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 990
991 if (re->skb) {
14d0263f 992 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 993 kfree_skb(re->skb);
994 re->skb = NULL;
995 }
996 }
997}
998
ef743d33
SH		 999/* Basic MII support */
1000static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1001{
1002 struct mii_ioctl_data *data = if_mii(ifr);
1003 struct sky2_port *sky2 = netdev_priv(dev);
1004 struct sky2_hw *hw = sky2->hw;
1005 int err = -EOPNOTSUPP;
1006
1007 if (!netif_running(dev))
1008 return -ENODEV; /* Phy still in reset */
1009
d89e1343 1010 switch (cmd) {
ef743d33
SH		 1011 case SIOCGMIIPHY:
1012 data->phy_id = PHY_ADDR_MARV;
1013
1014 /* fallthru */
1015 case SIOCGMIIREG: {
1016 u16 val = 0;
91c86df5 1017
e07b1aa8 1018 spin_lock_bh(&sky2->phy_lock);
ef743d33 1019 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1020 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1021
ef743d33
SH		 1022 data->val_out = val;
1023 break;
1024 }
1025
1026 case SIOCSMIIREG:
1027 if (!capable(CAP_NET_ADMIN))
1028 return -EPERM;
1029
e07b1aa8 1030 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1031 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1032 data->val_in);
e07b1aa8 1033 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1034 break;
1035 }
1036 return err;
1037}
1038
d1f13708
SH		 1039#ifdef SKY2_VLAN_TAG_USED
1040static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1041{
1042 struct sky2_port *sky2 = netdev_priv(dev);
1043 struct sky2_hw *hw = sky2->hw;
1044 u16 port = sky2->port;
d1f13708 1045
2bb8c262 1046 netif_tx_lock_bh(dev);
d1f13708
SH		 1047
1048 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1049 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1050 sky2->vlgrp = grp;
1051
2bb8c262 1052 netif_tx_unlock_bh(dev);
d1f13708
SH		 1053}
1054
1055static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1056{
1057 struct sky2_port *sky2 = netdev_priv(dev);
1058 struct sky2_hw *hw = sky2->hw;
1059 u16 port = sky2->port;
d1f13708 1060
2bb8c262 1061 netif_tx_lock_bh(dev);
d1f13708
SH		 1062
1063 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1064 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
5c15bdec 1065 vlan_group_set_device(sky2->vlgrp, vid, NULL);
d1f13708 1066
2bb8c262 1067 netif_tx_unlock_bh(dev);
d1f13708
SH		 1068}
1069#endif
1070
82788c7a 1071/*
14d0263f
SH		 1072 * Allocate an skb for receiving. If the MTU is large enough
1073 * make the skb non-linear with a fragment list of pages.
1074 *
82788c7a
SH		 1075 * It appears the hardware has a bug in the FIFO logic that
1076 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1077 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1078 * aligned except if slab debugging is enabled.
82788c7a 1079 */
14d0263f 1080static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1081{
1082 struct sk_buff *skb;
14d0263f
SH		 1083 unsigned long p;
1084 int i;
82788c7a 1085
14d0263f
SH		 1086 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1087 if (!skb)
1088 goto nomem;
1089
1090 p = (unsigned long) skb->data;
1091 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1092
1093 for (i = 0; i < sky2->rx_nfrags; i++) {
1094 struct page *page = alloc_page(GFP_ATOMIC);
1095
1096 if (!page)
1097 goto free_partial;
1098 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1099 }
1100
1101 return skb;
14d0263f
SH		 1102free_partial:
1103 kfree_skb(skb);
1104nomem:
1105 return NULL;
82788c7a
SH		 1106}
1107
cd28ab6a
SH		 1108/*
1109 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1110 * Normal case this ends up creating one list element for skb
1111 * in the receive ring. Worst case if using large MTU and each
1112 * allocation falls on a different 64 bit region, that results
1113 * in 6 list elements per ring entry.
1114 * One element is used for checksum enable/disable, and one
1115 * extra to avoid wrap.
cd28ab6a 1116 */
6b1a3aef 1117static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1118{
6b1a3aef 1119 struct sky2_hw *hw = sky2->hw;
14d0263f 1120 struct rx_ring_info *re;
6b1a3aef 1121 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1122 unsigned i, size, space, thresh;
cd28ab6a 1123
6b1a3aef 1124 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1125 sky2_qset(hw, rxq);
977bdf06 1126
c3905bc4
SH		 1127 /* On PCI express lowering the watermark gives better performance */
1128 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1129 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1130
1131 /* These chips have no ram buffer?
1132 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1133 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1134 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1135 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
977bdf06 1136 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
977bdf06 1137
6b1a3aef
SH		 1138 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1139
1140 rx_set_checksum(sky2);
14d0263f
SH		 1141
1142 /* Space needed for frame data + headers rounded up */
1143 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1144 + 8;
1145
1146 /* Stopping point for hardware truncation */
1147 thresh = (size - 8) / sizeof(u32);
1148
1149 /* Account for overhead of skb - to avoid order > 0 allocation */
1150 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1151 + sizeof(struct skb_shared_info);
1152
1153 sky2->rx_nfrags = space >> PAGE_SHIFT;
1154 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1155
1156 if (sky2->rx_nfrags != 0) {
1157 /* Compute residue after pages */
1158 space = sky2->rx_nfrags << PAGE_SHIFT;
1159
1160 if (space < size)
1161 size -= space;
1162 else
1163 size = 0;
1164
1165 /* Optimize to handle small packets and headers */
1166 if (size < copybreak)
1167 size = copybreak;
1168 if (size < ETH_HLEN)
1169 size = ETH_HLEN;
1170 }
1171 sky2->rx_data_size = size;
1172
1173 /* Fill Rx ring */
793b883e 1174 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1175 re = sky2->rx_ring + i;
cd28ab6a 1176
14d0263f 1177 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1178 if (!re->skb)
1179 goto nomem;
1180
14d0263f
SH		 1181 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1182 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1183 }
1184
a1433ac4
SH		 1185 /*
1186 * The receiver hangs if it receives frames larger than the
1187 * packet buffer. As a workaround, truncate oversize frames, but
1188 * the register is limited to 9 bits, so if you do frames > 2052
1189 * you better get the MTU right!
1190 */
a1433ac4
SH		 1191 if (thresh > 0x1ff)
1192 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1193 else {
1194 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1195 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1196 }
1197
6b1a3aef
SH		 1198 /* Tell chip about available buffers */
1199 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1200 return 0;
1201nomem:
1202 sky2_rx_clean(sky2);
1203 return -ENOMEM;
1204}
1205
1206/* Bring up network interface. */
1207static int sky2_up(struct net_device *dev)
1208{
1209 struct sky2_port *sky2 = netdev_priv(dev);
1210 struct sky2_hw *hw = sky2->hw;
1211 unsigned port = sky2->port;
67712901 1212 u32 ramsize, imask;
ee7abb04 1213 int cap, err = -ENOMEM;
843a46f4 1214 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1215
ee7abb04
SH		 1216 /*
1217 * On dual port PCI-X card, there is an problem where status
1218 * can be received out of order due to split transactions
843a46f4 1219 */
ee7abb04
SH		 1220 if (otherdev && netif_running(otherdev) &&
1221 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1222 struct sky2_port *osky2 = netdev_priv(otherdev);
1223 u16 cmd;
1224
1225 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1226 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1227 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1228
1229 sky2->rx_csum = 0;
1230 osky2->rx_csum = 0;
1231 }
843a46f4 1232
cd28ab6a
SH		 1233 if (netif_msg_ifup(sky2))
1234 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1235
1236 /* must be power of 2 */
1237 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1238 TX_RING_SIZE *
1239 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1240 &sky2->tx_le_map);
1241 if (!sky2->tx_le)
1242 goto err_out;
1243
6cdbbdf3 1244 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1245 GFP_KERNEL);
1246 if (!sky2->tx_ring)
1247 goto err_out;
1248 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1249
1250 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1251 &sky2->rx_le_map);
1252 if (!sky2->rx_le)
1253 goto err_out;
1254 memset(sky2->rx_le, 0, RX_LE_BYTES);
1255
291ea614 1256 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1257 GFP_KERNEL);
1258 if (!sky2->rx_ring)
1259 goto err_out;
1260
d3bcfbeb
SH		 1261 sky2_phy_power(hw, port, 1);
1262
cd28ab6a
SH		 1263 sky2_mac_init(hw, port);
1264
67712901
SH		 1265 /* Register is number of 4K blocks on internal RAM buffer. */
1266 ramsize = sky2_read8(hw, B2_E_0) * 4;
1267 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1268
67712901
SH		 1269 if (ramsize > 0) {
1270 u32 rxspace;
cd28ab6a 1271
67712901
SH		 1272 if (ramsize < 16)
1273 rxspace = ramsize / 2;
1274 else
1275 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1276
67712901
SH		 1277 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1278 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1279
1280 /* Make sure SyncQ is disabled */
1281 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1282 RB_RST_SET);
1283 }
793b883e 1284
af4ed7e6 1285 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1286
977bdf06 1287 /* Set almost empty threshold */
c2716fb4
SH		 1288 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1289 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1290 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1291
6b1a3aef
SH		 1292 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1293 TX_RING_SIZE - 1);
cd28ab6a 1294
6b1a3aef 1295 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1296 if (err)
1297 goto err_out;
1298
cd28ab6a 1299 /* Enable interrupts from phy/mac for port */
e07b1aa8 1300 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1301 imask |= portirq_msk[port];
e07b1aa8
SH		 1302 sky2_write32(hw, B0_IMSK, imask);
1303
cd28ab6a
SH		 1304 return 0;
1305
1306err_out:
1b537565 1307 if (sky2->rx_le) {
cd28ab6a
SH		 1308 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1309 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1310 sky2->rx_le = NULL;
1311 }
1312 if (sky2->tx_le) {
cd28ab6a
SH		 1313 pci_free_consistent(hw->pdev,
1314 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1315 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1316 sky2->tx_le = NULL;
1317 }
1318 kfree(sky2->tx_ring);
1319 kfree(sky2->rx_ring);
cd28ab6a 1320
1b537565
SH		 1321 sky2->tx_ring = NULL;
1322 sky2->rx_ring = NULL;
cd28ab6a
SH		 1323 return err;
1324}
1325
793b883e
SH		 1326/* Modular subtraction in ring */
1327static inline int tx_dist(unsigned tail, unsigned head)
1328{
cb5d9547 1329 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1330}
cd28ab6a 1331
793b883e
SH		 1332/* Number of list elements available for next tx */
1333static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1334{
793b883e 1335 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1336}
1337
793b883e 1338/* Estimate of number of transmit list elements required */
28bd181a 1339static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1340{
793b883e
SH		 1341 unsigned count;
1342
1343 count = sizeof(dma_addr_t) / sizeof(u32);
1344 count += skb_shinfo(skb)->nr_frags * count;
1345
89114afd 1346 if (skb_is_gso(skb))
793b883e
SH		 1347 ++count;
1348
84fa7933 1349 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1350 ++count;
1351
1352 return count;
cd28ab6a
SH		 1353}
1354
793b883e
SH		 1355/*
1356 * Put one packet in ring for transmit.
1357 * A single packet can generate multiple list elements, and
1358 * the number of ring elements will probably be less than the number
1359 * of list elements used.
1360 */
cd28ab6a
SH		 1361static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1362{
1363 struct sky2_port *sky2 = netdev_priv(dev);
1364 struct sky2_hw *hw = sky2->hw;
d1f13708 1365 struct sky2_tx_le *le = NULL;
6cdbbdf3 1366 struct tx_ring_info *re;
cd28ab6a
SH		 1367 unsigned i, len;
1368 dma_addr_t mapping;
1369 u32 addr64;
1370 u16 mss;
1371 u8 ctrl;
1372
2bb8c262
SH		 1373 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1374 return NETDEV_TX_BUSY;
cd28ab6a 1375
793b883e 1376 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1377 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1378 dev->name, sky2->tx_prod, skb->len);
1379
cd28ab6a
SH		 1380 len = skb_headlen(skb);
1381 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1382 addr64 = high32(mapping);
793b883e 1383
a018e330
SH		 1384 /* Send high bits if changed or crosses boundary */
1385 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1386 le = get_tx_le(sky2);
f65b138c 1387 le->addr = cpu_to_le32(addr64);
793b883e 1388 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1389 sky2->tx_addr64 = high32(mapping + len);
793b883e 1390 }
cd28ab6a
SH		 1391
1392 /* Check for TCP Segmentation Offload */
7967168c 1393 mss = skb_shinfo(skb)->gso_size;
793b883e 1394 if (mss != 0) {
ab6a5bb6 1395 mss += tcp_optlen(skb); /* TCP options */
c9bdd4b5 1396 mss += ip_hdrlen(skb) + sizeof(struct tcphdr);
cd28ab6a
SH		 1397 mss += ETH_HLEN;
1398
e07560cd
SH		 1399 if (mss != sky2->tx_last_mss) {
1400 le = get_tx_le(sky2);
f65b138c 1401 le->addr = cpu_to_le32(mss);
e07560cd 1402 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1403 sky2->tx_last_mss = mss;
1404 }
cd28ab6a
SH		 1405 }
1406
cd28ab6a 1407 ctrl = 0;
d1f13708
SH		 1408#ifdef SKY2_VLAN_TAG_USED
1409 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1410 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1411 if (!le) {
1412 le = get_tx_le(sky2);
f65b138c 1413 le->addr = 0;
d1f13708 1414 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1415 } else
1416 le->opcode |= OP_VLAN;
1417 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1418 ctrl |= INS_VLAN;
1419 }
1420#endif
1421
1422 /* Handle TCP checksum offload */
84fa7933 1423 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d 1424 const unsigned offset = skb_transport_offset(skb);
f65b138c
SH		 1425 u32 tcpsum;
1426
1427 tcpsum = offset << 16; /* sum start */
ff1dcadb 1428 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a
SH		 1429
1430 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
eddc9ec5 1431 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
cd28ab6a
SH		 1432 ctrl |= UDPTCP;
1433
f65b138c
SH		 1434 if (tcpsum != sky2->tx_tcpsum) {
1435 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1436
1437 le = get_tx_le(sky2);
f65b138c 1438 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1439 le->length = 0; /* initial checksum value */
1440 le->ctrl = 1; /* one packet */
1441 le->opcode = OP_TCPLISW | HW_OWNER;
1442 }
cd28ab6a
SH		 1443 }
1444
1445 le = get_tx_le(sky2);
f65b138c 1446 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1447 le->length = cpu_to_le16(len);
1448 le->ctrl = ctrl;
793b883e 1449 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1450
291ea614 1451 re = tx_le_re(sky2, le);
cd28ab6a 1452 re->skb = skb;
6cdbbdf3 1453 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1454 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1455
1456 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1457 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1458
1459 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1460 frag->size, PCI_DMA_TODEVICE);
a036119f 1461 addr64 = high32(mapping);
793b883e
SH		 1462 if (addr64 != sky2->tx_addr64) {
1463 le = get_tx_le(sky2);
f65b138c 1464 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1465 le->ctrl = 0;
1466 le->opcode = OP_ADDR64 | HW_OWNER;
1467 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1468 }
1469
1470 le = get_tx_le(sky2);
f65b138c 1471 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1472 le->length = cpu_to_le16(frag->size);
1473 le->ctrl = ctrl;
793b883e 1474 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1475
291ea614
SH		 1476 re = tx_le_re(sky2, le);
1477 re->skb = skb;
1478 pci_unmap_addr_set(re, mapaddr, mapping);
1479 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1480 }
6cdbbdf3 1481
cd28ab6a
SH		 1482 le->ctrl |= EOP;
1483
97bda706
SH		 1484 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1485 netif_stop_queue(dev);
b19666d9 1486
290d4de5 1487 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1488
cd28ab6a
SH		 1489 dev->trans_start = jiffies;
1490 return NETDEV_TX_OK;
1491}
1492
cd28ab6a 1493/*
793b883e
SH		 1494 * Free ring elements from starting at tx_cons until "done"
1495 *
1496 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1497 * buffers so make sure not to free skb to early.
cd28ab6a 1498 */
d11c13e7 1499static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1500{
d11c13e7 1501 struct net_device *dev = sky2->netdev;
af2a58ac 1502 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1503 unsigned idx;
cd28ab6a 1504
0e3ff6aa 1505 BUG_ON(done >= TX_RING_SIZE);
2224795d 1506
291ea614
SH		 1507 for (idx = sky2->tx_cons; idx != done;
1508 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1509 struct sky2_tx_le *le = sky2->tx_le + idx;
1510 struct tx_ring_info *re = sky2->tx_ring + idx;
1511
1512 switch(le->opcode & ~HW_OWNER) {
1513 case OP_LARGESEND:
1514 case OP_PACKET:
1515 pci_unmap_single(pdev,
1516 pci_unmap_addr(re, mapaddr),
1517 pci_unmap_len(re, maplen),
1518 PCI_DMA_TODEVICE);
af2a58ac 1519 break;
291ea614
SH		 1520 case OP_BUFFER:
1521 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1522 pci_unmap_len(re, maplen),
734d1868 1523 PCI_DMA_TODEVICE);
291ea614
SH		 1524 break;
1525 }
1526
1527 if (le->ctrl & EOP) {
1528 if (unlikely(netif_msg_tx_done(sky2)))
1529 printk(KERN_DEBUG "%s: tx done %u\n",
1530 dev->name, idx);
2bf56fe2 1531 sky2->net_stats.tx_packets++;
1532 sky2->net_stats.tx_bytes += re->skb->len;
1533
794b2bd2 1534 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1535 }
1536
291ea614 1537 le->opcode = 0; /* paranoia */
793b883e 1538 }
793b883e 1539
291ea614 1540 sky2->tx_cons = idx;
22e11703 1541 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1542 netif_wake_queue(dev);
cd28ab6a
SH		 1543}
1544
1545/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1546static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1547{
2bb8c262
SH		 1548 struct sky2_port *sky2 = netdev_priv(dev);
1549
1550 netif_tx_lock_bh(dev);
d11c13e7 1551 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1552 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1553}
1554
1555/* Network shutdown */
1556static int sky2_down(struct net_device *dev)
1557{
1558 struct sky2_port *sky2 = netdev_priv(dev);
1559 struct sky2_hw *hw = sky2->hw;
1560 unsigned port = sky2->port;
1561 u16 ctrl;
e07b1aa8 1562 u32 imask;
cd28ab6a 1563
1b537565
SH		 1564 /* Never really got started! */
1565 if (!sky2->tx_le)
1566 return 0;
1567
cd28ab6a
SH		 1568 if (netif_msg_ifdown(sky2))
1569 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1570
018d1c66 1571 /* Stop more packets from being queued */
cd28ab6a 1572 netif_stop_queue(dev);
9a87240c 1573 netif_carrier_off(dev);
cd28ab6a 1574
ebc646f6
SH		 1575 /* Disable port IRQ */
1576 imask = sky2_read32(hw, B0_IMSK);
1577 imask &= ~portirq_msk[port];
1578 sky2_write32(hw, B0_IMSK, imask);
1579
25d82d7a
SH		 1580 /*
1581 * Both ports share the NAPI poll on port 0, so if necessary undo the
1582 * the disable that is done in dev_close.
1583 */
1584 if (sky2->port == 0 && hw->ports > 1)
1585 netif_poll_enable(dev);
1586
d3bcfbeb 1587 sky2_gmac_reset(hw, port);
793b883e 1588
cd28ab6a
SH		 1589 /* Stop transmitter */
1590 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1591 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1592
1593 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1594 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1595
1596 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1597 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1598 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1599
1600 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1601
1602 /* Workaround shared GMAC reset */
793b883e
SH		 1603 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1604 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1605 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1606
1607 /* Disable Force Sync bit and Enable Alloc bit */
1608 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1609 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1610
1611 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1612 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1613 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1614
1615 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1616 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1617 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1618
1619 /* Reset the Tx prefetch units */
1620 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1621 PREF_UNIT_RST_SET);
1622
1623 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1624
6b1a3aef 1625 sky2_rx_stop(sky2);
cd28ab6a
SH		 1626
1627 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1628 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1629
d3bcfbeb
SH		 1630 sky2_phy_power(hw, port, 0);
1631
d571b694 1632 /* turn off LED's */
cd28ab6a
SH		 1633 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1634
018d1c66
SH		 1635 synchronize_irq(hw->pdev->irq);
1636
2bb8c262 1637 sky2_tx_clean(dev);
cd28ab6a
SH		 1638 sky2_rx_clean(sky2);
1639
1640 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1641 sky2->rx_le, sky2->rx_le_map);
1642 kfree(sky2->rx_ring);
1643
1644 pci_free_consistent(hw->pdev,
1645 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1646 sky2->tx_le, sky2->tx_le_map);
1647 kfree(sky2->tx_ring);
1648
1b537565
SH		 1649 sky2->tx_le = NULL;
1650 sky2->rx_le = NULL;
1651
1652 sky2->rx_ring = NULL;
1653 sky2->tx_ring = NULL;
1654
cd28ab6a
SH		 1655 return 0;
1656}
1657
1658static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1659{
b89165f2 1660 if (!sky2_is_copper(hw))
793b883e
SH		 1661 return SPEED_1000;
1662
cd28ab6a
SH		 1663 if (hw->chip_id == CHIP_ID_YUKON_FE)
1664 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1665
1666 switch (aux & PHY_M_PS_SPEED_MSK) {
1667 case PHY_M_PS_SPEED_1000:
1668 return SPEED_1000;
1669 case PHY_M_PS_SPEED_100:
1670 return SPEED_100;
1671 default:
1672 return SPEED_10;
1673 }
1674}
1675
1676static void sky2_link_up(struct sky2_port *sky2)
1677{
1678 struct sky2_hw *hw = sky2->hw;
1679 unsigned port = sky2->port;
1680 u16 reg;
16ad91e1
SH		 1681 static const char *fc_name[] = {
1682 [FC_NONE] = "none",
1683 [FC_TX] = "tx",
1684 [FC_RX] = "rx",
1685 [FC_BOTH] = "both",
1686 };
cd28ab6a 1687
cd28ab6a 1688 /* enable Rx/Tx */
2eaba1a2 1689 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1690 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1691 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1692
1693 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1694
1695 netif_carrier_on(sky2->netdev);
1696 netif_wake_queue(sky2->netdev);
1697
1698 /* Turn on link LED */
793b883e 1699 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1700 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1701
93745494
SH		 1702 if (hw->chip_id == CHIP_ID_YUKON_XL
1703 || hw->chip_id == CHIP_ID_YUKON_EC_U
1704 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1705 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1706 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1707
1708 switch(sky2->speed) {
1709 case SPEED_10:
1710 led |= PHY_M_LEDC_INIT_CTRL(7);
1711 break;
1712
1713 case SPEED_100:
1714 led |= PHY_M_LEDC_STA1_CTRL(7);
1715 break;
1716
1717 case SPEED_1000:
1718 led |= PHY_M_LEDC_STA0_CTRL(7);
1719 break;
1720 }
793b883e
SH		 1721
1722 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1723 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1724 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1725 }
1726
cd28ab6a
SH		 1727 if (netif_msg_link(sky2))
1728 printk(KERN_INFO PFX
d571b694 1729 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1730 sky2->netdev->name, sky2->speed,
1731 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1732 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1733}
1734
1735static void sky2_link_down(struct sky2_port *sky2)
1736{
1737 struct sky2_hw *hw = sky2->hw;
1738 unsigned port = sky2->port;
1739 u16 reg;
1740
1741 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1742
1743 reg = gma_read16(hw, port, GM_GP_CTRL);
1744 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1745 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1746
cd28ab6a
SH		 1747 netif_carrier_off(sky2->netdev);
1748 netif_stop_queue(sky2->netdev);
1749
1750 /* Turn on link LED */
1751 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1752
1753 if (netif_msg_link(sky2))
1754 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1755
cd28ab6a
SH		 1756 sky2_phy_init(hw, port);
1757}
1758
16ad91e1
SH		 1759static enum flow_control sky2_flow(int rx, int tx)
1760{
1761 if (rx)
1762 return tx ? FC_BOTH : FC_RX;
1763 else
1764 return tx ? FC_TX : FC_NONE;
1765}
1766
793b883e
SH		 1767static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1768{
1769 struct sky2_hw *hw = sky2->hw;
1770 unsigned port = sky2->port;
da4c1ff4 1771 u16 advert, lpa;
793b883e 1772
da4c1ff4 1773 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1774 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1775 if (lpa & PHY_M_AN_RF) {
1776 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1777 return -1;
1778 }
1779
793b883e
SH		 1780 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1781 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1782 sky2->netdev->name);
1783 return -1;
1784 }
1785
793b883e 1786 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1787 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1788
da4c1ff4
SH		 1789 /* Since the pause result bits seem to in different positions on
1790 * different chips. look at registers.
1791 */
1792 if (!sky2_is_copper(hw)) {
1793 /* Shift for bits in fiber PHY */
1794 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1795 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1796
1797 if (advert & ADVERTISE_1000XPAUSE)
1798 advert |= ADVERTISE_PAUSE_CAP;
1799 if (advert & ADVERTISE_1000XPSE_ASYM)
1800 advert |= ADVERTISE_PAUSE_ASYM;
1801 if (lpa & LPA_1000XPAUSE)
1802 lpa |= LPA_PAUSE_CAP;
1803 if (lpa & LPA_1000XPAUSE_ASYM)
1804 lpa |= LPA_PAUSE_ASYM;
1805 }
793b883e 1806
da4c1ff4
SH		 1807 sky2->flow_status = FC_NONE;
1808 if (advert & ADVERTISE_PAUSE_CAP) {
1809 if (lpa & LPA_PAUSE_CAP)
1810 sky2->flow_status = FC_BOTH;
1811 else if (advert & ADVERTISE_PAUSE_ASYM)
1812 sky2->flow_status = FC_RX;
1813 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1814 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1815 sky2->flow_status = FC_TX;
1816 }
793b883e 1817
16ad91e1 1818 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1819 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1820 sky2->flow_status = FC_NONE;
2eaba1a2 1821
da4c1ff4 1822 if (sky2->flow_status & FC_TX)
793b883e
SH		 1823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1824 else
1825 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1826
1827 return 0;
1828}
cd28ab6a 1829
e07b1aa8
SH		 1830/* Interrupt from PHY */
1831static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1832{
e07b1aa8
SH		 1833 struct net_device *dev = hw->dev[port];
1834 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1835 u16 istatus, phystat;
1836
ebc646f6
SH		 1837 if (!netif_running(dev))
1838 return;
1839
e07b1aa8
SH		 1840 spin_lock(&sky2->phy_lock);
1841 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1842 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1843
cd28ab6a
SH		 1844 if (netif_msg_intr(sky2))
1845 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1846 sky2->netdev->name, istatus, phystat);
1847
2eaba1a2 1848 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1849 if (sky2_autoneg_done(sky2, phystat) == 0)
1850 sky2_link_up(sky2);
1851 goto out;
1852 }
cd28ab6a 1853
793b883e
SH		 1854 if (istatus & PHY_M_IS_LSP_CHANGE)
1855 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1856
793b883e
SH		 1857 if (istatus & PHY_M_IS_DUP_CHANGE)
1858 sky2->duplex =
1859 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1860
793b883e
SH		 1861 if (istatus & PHY_M_IS_LST_CHANGE) {
1862 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1863 sky2_link_up(sky2);
793b883e
SH		 1864 else
1865 sky2_link_down(sky2);
cd28ab6a 1866 }
793b883e 1867out:
e07b1aa8 1868 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1869}
1870
62335ab0 1871/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1872 * and tx queue is full (stopped).
1873 */
cd28ab6a
SH		 1874static void sky2_tx_timeout(struct net_device *dev)
1875{
1876 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1877 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1878
1879 if (netif_msg_timer(sky2))
1880 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1881
8f24664d 1882 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1883 dev->name, sky2->tx_cons, sky2->tx_prod,
1884 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1885 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1886
81906791
SH		 1887 /* can't restart safely under softirq */
1888 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1889}
1890
1891static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1892{
6b1a3aef
SH		 1893 struct sky2_port *sky2 = netdev_priv(dev);
1894 struct sky2_hw *hw = sky2->hw;
b628ed98 1895 unsigned port = sky2->port;
6b1a3aef
SH		 1896 int err;
1897 u16 ctl, mode;
e07b1aa8 1898 u32 imask;
cd28ab6a
SH		 1899
1900 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1901 return -EINVAL;
1902
d2adf4f6
SH		 1903 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1904 return -EINVAL;
1905
6b1a3aef
SH		 1906 if (!netif_running(dev)) {
1907 dev->mtu = new_mtu;
1908 return 0;
1909 }
1910
e07b1aa8 1911 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1912 sky2_write32(hw, B0_IMSK, 0);
1913
018d1c66
SH		 1914 dev->trans_start = jiffies; /* prevent tx timeout */
1915 netif_stop_queue(dev);
1916 netif_poll_disable(hw->dev[0]);
1917
e07b1aa8
SH		 1918 synchronize_irq(hw->pdev->irq);
1919
b628ed98
SH		 1920 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
1921 if (new_mtu > ETH_DATA_LEN) {
1922 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1923 TX_JUMBO_ENA | TX_STFW_DIS);
1924 dev->features &= NETIF_F_TSO | NETIF_F_SG | NETIF_F_IP_CSUM;
1925 } else
1926 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1927 TX_JUMBO_DIS | TX_STFW_ENA);
1928 }
1929
1930 ctl = gma_read16(hw, port, GM_GP_CTRL);
1931 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 1932 sky2_rx_stop(sky2);
1933 sky2_rx_clean(sky2);
cd28ab6a
SH		 1934
1935 dev->mtu = new_mtu;
14d0263f 1936
6b1a3aef
SH		 1937 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1938 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1939
1940 if (dev->mtu > ETH_DATA_LEN)
1941 mode |= GM_SMOD_JUMBO_ENA;
1942
b628ed98 1943 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 1944
b628ed98 1945 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1946
6b1a3aef 1947 err = sky2_rx_start(sky2);
e07b1aa8 1948 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1949
1b537565
SH		 1950 if (err)
1951 dev_close(dev);
1952 else {
b628ed98 1953 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 1954
1955 netif_poll_enable(hw->dev[0]);
1956 netif_wake_queue(dev);
1957 }
1958
cd28ab6a
SH		 1959 return err;
1960}
1961
14d0263f
SH		 1962/* For small just reuse existing skb for next receive */
1963static struct sk_buff *receive_copy(struct sky2_port *sky2,
1964 const struct rx_ring_info *re,
1965 unsigned length)
1966{
1967 struct sk_buff *skb;
1968
1969 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1970 if (likely(skb)) {
1971 skb_reserve(skb, 2);
1972 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1973 length, PCI_DMA_FROMDEVICE);
d626f62b 1974 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 1975 skb->ip_summed = re->skb->ip_summed;
1976 skb->csum = re->skb->csum;
1977 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1978 length, PCI_DMA_FROMDEVICE);
1979 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1980 skb_put(skb, length);
14d0263f
SH		 1981 }
1982 return skb;
1983}
1984
1985/* Adjust length of skb with fragments to match received data */
1986static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1987 unsigned int length)
1988{
1989 int i, num_frags;
1990 unsigned int size;
1991
1992 /* put header into skb */
1993 size = min(length, hdr_space);
1994 skb->tail += size;
1995 skb->len += size;
1996 length -= size;
1997
1998 num_frags = skb_shinfo(skb)->nr_frags;
1999 for (i = 0; i < num_frags; i++) {
2000 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2001
2002 if (length == 0) {
2003 /* don't need this page */
2004 __free_page(frag->page);
2005 --skb_shinfo(skb)->nr_frags;
2006 } else {
2007 size = min(length, (unsigned) PAGE_SIZE);
2008
2009 frag->size = size;
2010 skb->data_len += size;
2011 skb->truesize += size;
2012 skb->len += size;
2013 length -= size;
2014 }
2015 }
2016}
2017
2018/* Normal packet - take skb from ring element and put in a new one */
2019static struct sk_buff *receive_new(struct sky2_port *sky2,
2020 struct rx_ring_info *re,
2021 unsigned int length)
2022{
2023 struct sk_buff *skb, *nskb;
2024 unsigned hdr_space = sky2->rx_data_size;
2025
2026 pr_debug(PFX "receive new length=%d\n", length);
2027
2028 /* Don't be tricky about reusing pages (yet) */
2029 nskb = sky2_rx_alloc(sky2);
2030 if (unlikely(!nskb))
2031 return NULL;
2032
2033 skb = re->skb;
2034 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2035
2036 prefetch(skb->data);
2037 re->skb = nskb;
2038 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2039
2040 if (skb_shinfo(skb)->nr_frags)
2041 skb_put_frags(skb, hdr_space, length);
2042 else
489b10c1 2043 skb_put(skb, length);
14d0263f
SH		 2044 return skb;
2045}
2046
cd28ab6a
SH		 2047/*
2048 * Receive one packet.
d571b694 2049 * For larger packets, get new buffer.
cd28ab6a 2050 */
497d7c86 2051static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2052 u16 length, u32 status)
2053{
497d7c86 2054 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2055 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2056 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2057
2058 if (unlikely(netif_msg_rx_status(sky2)))
2059 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2060 dev->name, sky2->rx_next, status, length);
cd28ab6a 2061
793b883e 2062 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2063 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2064
42eeea01 2065 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2066 goto error;
2067
42eeea01
SH		 2068 if (!(status & GMR_FS_RX_OK))
2069 goto resubmit;
2070
14d0263f
SH		 2071 if (length < copybreak)
2072 skb = receive_copy(sky2, re, length);
2073 else
2074 skb = receive_new(sky2, re, length);
793b883e 2075resubmit:
14d0263f 2076 sky2_rx_submit(sky2, re);
79e57d32 2077
cd28ab6a
SH		 2078 return skb;
2079
2080error:
6e15b712 2081 ++sky2->net_stats.rx_errors;
b6d77734 2082 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2083 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2084 goto resubmit;
2085 }
6e15b712 2086
3be92a70 2087 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2088 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2089 dev->name, status, length);
793b883e
SH		 2090
2091 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2092 sky2->net_stats.rx_length_errors++;
2093 if (status & GMR_FS_FRAGMENT)
2094 sky2->net_stats.rx_frame_errors++;
2095 if (status & GMR_FS_CRC_ERR)
2096 sky2->net_stats.rx_crc_errors++;
79e57d32 2097
793b883e 2098 goto resubmit;
cd28ab6a
SH		 2099}
2100
e07b1aa8
SH		 2101/* Transmit complete */
2102static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2103{
e07b1aa8 2104 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2105
e07b1aa8 2106 if (netif_running(dev)) {
2bb8c262 2107 netif_tx_lock(dev);
e07b1aa8 2108 sky2_tx_complete(sky2, last);
2bb8c262 2109 netif_tx_unlock(dev);
2224795d 2110 }
cd28ab6a
SH		 2111}
2112
e07b1aa8
SH		 2113/* Process status response ring */
2114static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2115{
22e11703 2116 struct sky2_port *sky2;
e07b1aa8 2117 int work_done = 0;
22e11703 2118 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2119 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2120
af2a58ac 2121 rmb();
bea86103 2122
e71ebd73 2123 while (hw->st_idx != hwidx) {
13210ce5
SH		 2124 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2125 struct net_device *dev;
cd28ab6a 2126 struct sk_buff *skb;
cd28ab6a
SH		 2127 u32 status;
2128 u16 length;
2129
cb5d9547 2130 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2131
e71ebd73
SH		 2132 BUG_ON(le->link >= 2);
2133 dev = hw->dev[le->link];
13210ce5
SH		 2134
2135 sky2 = netdev_priv(dev);
f65b138c
SH		 2136 length = le16_to_cpu(le->length);
2137 status = le32_to_cpu(le->status);
cd28ab6a 2138
e71ebd73 2139 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2140 case OP_RXSTAT:
497d7c86 2141 skb = sky2_receive(dev, length, status);
d1f13708 2142 if (!skb)
5df79111 2143 goto force_update;
13210ce5 2144
13210ce5 2145 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2146 sky2->net_stats.rx_packets++;
2147 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2148 dev->last_rx = jiffies;
2149
d1f13708
SH		 2150#ifdef SKY2_VLAN_TAG_USED
2151 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2152 vlan_hwaccel_receive_skb(skb,
2153 sky2->vlgrp,
2154 be16_to_cpu(sky2->rx_tag));
2155 } else
2156#endif
cd28ab6a 2157 netif_receive_skb(skb);
13210ce5 2158
22e11703
SH		 2159 /* Update receiver after 16 frames */
2160 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2161force_update:
2162 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2163 buf_write[le->link] = 0;
2164 }
2165
2166 /* Stop after net poll weight */
13210ce5
SH		 2167 if (++work_done >= to_do)
2168 goto exit_loop;
cd28ab6a
SH		 2169 break;
2170
d1f13708
SH		 2171#ifdef SKY2_VLAN_TAG_USED
2172 case OP_RXVLAN:
2173 sky2->rx_tag = length;
2174 break;
2175
2176 case OP_RXCHKSVLAN:
2177 sky2->rx_tag = length;
2178 /* fall through */
2179#endif
cd28ab6a 2180 case OP_RXCHKS:
87418307
SH		 2181 if (!sky2->rx_csum)
2182 break;
2183
2184 /* Both checksum counters are programmed to start at
2185 * the same offset, so unless there is a problem they
2186 * should match. This failure is an early indication that
2187 * hardware receive checksumming won't work.
2188 */
2189 if (likely(status >> 16 == (status & 0xffff))) {
2190 skb = sky2->rx_ring[sky2->rx_next].skb;
2191 skb->ip_summed = CHECKSUM_COMPLETE;
2192 skb->csum = status & 0xffff;
2193 } else {
2194 printk(KERN_NOTICE PFX "%s: hardware receive "
2195 "checksum problem (status = %#x)\n",
2196 dev->name, status);
2197 sky2->rx_csum = 0;
2198 sky2_write32(sky2->hw,
2199 Q_ADDR(rxqaddr[le->link], Q_CSR),
2200 BMU_DIS_RX_CHKSUM);
2201 }
cd28ab6a
SH		 2202 break;
2203
2204 case OP_TXINDEXLE:
13b97b74 2205 /* TX index reports status for both ports */
f55925d7
SH		 2206 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2207 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2208 if (hw->dev[1])
2209 sky2_tx_done(hw->dev[1],
2210 ((status >> 24) & 0xff)
2211 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2212 break;
2213
cd28ab6a
SH		 2214 default:
2215 if (net_ratelimit())
793b883e 2216 printk(KERN_WARNING PFX
e71ebd73
SH		 2217 "unknown status opcode 0x%x\n", le->opcode);
2218 goto exit_loop;
cd28ab6a 2219 }
13210ce5 2220 }
cd28ab6a 2221
fe2a24df
SH		 2222 /* Fully processed status ring so clear irq */
2223 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2224
13210ce5 2225exit_loop:
22e11703
SH		 2226 if (buf_write[0]) {
2227 sky2 = netdev_priv(hw->dev[0]);
2228 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2229 }
2230
2231 if (buf_write[1]) {
2232 sky2 = netdev_priv(hw->dev[1]);
2233 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2234 }
2235
e07b1aa8 2236 return work_done;
cd28ab6a
SH		 2237}
2238
2239static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2240{
2241 struct net_device *dev = hw->dev[port];
2242
3be92a70
SH		 2243 if (net_ratelimit())
2244 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2245 dev->name, status);
cd28ab6a
SH		 2246
2247 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2248 if (net_ratelimit())
2249 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2250 dev->name);
cd28ab6a
SH		 2251 /* Clear IRQ */
2252 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2253 }
2254
2255 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2256 if (net_ratelimit())
2257 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2258 dev->name);
cd28ab6a
SH		 2259
2260 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2261 }
2262
2263 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2264 if (net_ratelimit())
2265 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2266 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2267 }
2268
2269 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2270 if (net_ratelimit())
2271 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2272 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2273 }
2274
2275 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2276 if (net_ratelimit())
2277 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2278 dev->name);
cd28ab6a
SH		 2279 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2280 }
2281}
2282
2283static void sky2_hw_intr(struct sky2_hw *hw)
2284{
2285 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2286
793b883e 2287 if (status & Y2_IS_TIST_OV)
cd28ab6a 2288 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2289
2290 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2291 u16 pci_err;
2292
56a645cc 2293 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2294 if (net_ratelimit())
b02a9258
SH		 2295 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2296 pci_err);
cd28ab6a
SH		 2297
2298 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2299 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2300 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2301 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2302 }
2303
2304 if (status & Y2_IS_PCI_EXP) {
d571b694 2305 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2306 u32 pex_err;
2307
7bd656d1 2308 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2309
3be92a70 2310 if (net_ratelimit())
b02a9258
SH		 2311 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2312 pex_err);
cd28ab6a
SH		 2313
2314 /* clear the interrupt */
2315 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2316 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2317 0xffffffffUL);
cd28ab6a
SH		 2318 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2319
7bd656d1 2320 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2321 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2322 hwmsk &= ~Y2_IS_PCI_EXP;
2323 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2324 }
2325 }
2326
2327 if (status & Y2_HWE_L1_MASK)
2328 sky2_hw_error(hw, 0, status);
2329 status >>= 8;
2330 if (status & Y2_HWE_L1_MASK)
2331 sky2_hw_error(hw, 1, status);
2332}
2333
2334static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2335{
2336 struct net_device *dev = hw->dev[port];
2337 struct sky2_port *sky2 = netdev_priv(dev);
2338 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2339
2340 if (netif_msg_intr(sky2))
2341 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2342 dev->name, status);
2343
2344 if (status & GM_IS_RX_FF_OR) {
2345 ++sky2->net_stats.rx_fifo_errors;
2346 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2347 }
2348
2349 if (status & GM_IS_TX_FF_UR) {
2350 ++sky2->net_stats.tx_fifo_errors;
2351 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2352 }
cd28ab6a
SH		 2353}
2354
40b01727
SH		 2355/* This should never happen it is a bug. */
2356static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2357 u16 q, unsigned ring_size)
d257924e
SH		 2358{
2359 struct net_device *dev = hw->dev[port];
2360 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2361 unsigned idx;
2362 const u64 *le = (q == Q_R1 || q == Q_R2)
2363 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2364
40b01727
SH		 2365 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2366 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2367 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2368 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2369
40b01727 2370 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2371}
cd28ab6a 2372
d27ed387
SH		 2373/* If idle then force a fake soft NAPI poll once a second
2374 * to work around cases where sharing an edge triggered interrupt.
2375 */
eb35cf60
SH		 2376static inline void sky2_idle_start(struct sky2_hw *hw)
2377{
2378 if (idle_timeout > 0)
2379 mod_timer(&hw->idle_timer,
2380 jiffies + msecs_to_jiffies(idle_timeout));
2381}
2382
d27ed387
SH		 2383static void sky2_idle(unsigned long arg)
2384{
01bd7564
SH		 2385 struct sky2_hw *hw = (struct sky2_hw *) arg;
2386 struct net_device *dev = hw->dev[0];
d27ed387 2387
d27ed387
SH		 2388 if (__netif_rx_schedule_prep(dev))
2389 __netif_rx_schedule(dev);
01bd7564
SH		 2390
2391 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2392}
2393
40b01727
SH		 2394/* Hardware/software error handling */
2395static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2396{
40b01727
SH		 2397 if (net_ratelimit())
2398 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2399
1e5f1283
SH		 2400 if (status & Y2_IS_HW_ERR)
2401 sky2_hw_intr(hw);
d257924e 2402
1e5f1283
SH		 2403 if (status & Y2_IS_IRQ_MAC1)
2404 sky2_mac_intr(hw, 0);
cd28ab6a 2405
1e5f1283
SH		 2406 if (status & Y2_IS_IRQ_MAC2)
2407 sky2_mac_intr(hw, 1);
cd28ab6a 2408
1e5f1283 2409 if (status & Y2_IS_CHK_RX1)
40b01727 2410 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2411
1e5f1283 2412 if (status & Y2_IS_CHK_RX2)
40b01727 2413 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2414
1e5f1283 2415 if (status & Y2_IS_CHK_TXA1)
40b01727 2416 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2417
1e5f1283 2418 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2419 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2420}
2421
2422static int sky2_poll(struct net_device *dev0, int *budget)
2423{
2424 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2425 int work_limit = min(dev0->quota, *budget);
2426 int work_done = 0;
2427 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2428
2429 if (unlikely(status & Y2_IS_ERROR))
2430 sky2_err_intr(hw, status);
2431
2432 if (status & Y2_IS_IRQ_PHY1)
2433 sky2_phy_intr(hw, 0);
2434
2435 if (status & Y2_IS_IRQ_PHY2)
2436 sky2_phy_intr(hw, 1);
cd28ab6a 2437
1e5f1283 2438 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2439 if (work_done < work_limit) {
2440 netif_rx_complete(dev0);
86fba634 2441
fe2a24df
SH		 2442 sky2_read32(hw, B0_Y2_SP_LISR);
2443 return 0;
2444 } else {
2445 *budget -= work_done;
2446 dev0->quota -= work_done;
1e5f1283 2447 return 1;
fe2a24df 2448 }
e07b1aa8
SH		 2449}
2450
7d12e780 2451static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2452{
2453 struct sky2_hw *hw = dev_id;
2454 struct net_device *dev0 = hw->dev[0];
2455 u32 status;
2456
2457 /* Reading this mask interrupts as side effect */
2458 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2459 if (status == 0 || status == ~0)
2460 return IRQ_NONE;
793b883e 2461
e07b1aa8
SH		 2462 prefetch(&hw->st_le[hw->st_idx]);
2463 if (likely(__netif_rx_schedule_prep(dev0)))
2464 __netif_rx_schedule(dev0);
793b883e 2465
cd28ab6a
SH		 2466 return IRQ_HANDLED;
2467}
2468
2469#ifdef CONFIG_NET_POLL_CONTROLLER
2470static void sky2_netpoll(struct net_device *dev)
2471{
2472 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2473 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2474
88d11360
SH		 2475 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2476 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2477}
2478#endif
2479
2480/* Chip internal frequency for clock calculations */
fb17358f 2481static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2482{
793b883e 2483 switch (hw->chip_id) {
cd28ab6a 2484 case CHIP_ID_YUKON_EC:
5a5b1ea0 2485 case CHIP_ID_YUKON_EC_U:
93745494 2486 case CHIP_ID_YUKON_EX:
fb17358f 2487 return 125; /* 125 Mhz */
cd28ab6a 2488 case CHIP_ID_YUKON_FE:
fb17358f 2489 return 100; /* 100 Mhz */
793b883e 2490 default: /* YUKON_XL */
fb17358f 2491 return 156; /* 156 Mhz */
cd28ab6a
SH		 2492 }
2493}
2494
fb17358f 2495static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2496{
fb17358f 2497 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2498}
2499
fb17358f 2500static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2501{
fb17358f 2502 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2503}
2504
fb17358f 2505
e3173832 2506static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2507{
b89165f2 2508 u8 t8;
cd28ab6a 2509
cd28ab6a 2510 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2511
cd28ab6a
SH		 2512 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2513 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2514 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2515 hw->chip_id);
cd28ab6a
SH		 2516 return -EOPNOTSUPP;
2517 }
2518
93745494
SH		 2519 if (hw->chip_id == CHIP_ID_YUKON_EX)
2520 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2521 "Please report success or failure to <netdev@vger.kernel.org>\n");
2522
2523 /* Make sure and enable all clocks */
2524 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2525 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2526
290d4de5
SH		 2527 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2528
2529 /* This rev is really old, and requires untested workarounds */
2530 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2531 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2532 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2533 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2534 return -EOPNOTSUPP;
2535 }
2536
e3173832
SH		 2537 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2538 hw->ports = 1;
2539 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2540 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2541 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2542 ++hw->ports;
2543 }
2544
2545 return 0;
2546}
2547
2548static void sky2_reset(struct sky2_hw *hw)
2549{
2550 u16 status;
2551 int i;
2552
cd28ab6a 2553 /* disable ASF */
4f44d8ba
SH		 2554 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2555 status = sky2_read16(hw, HCU_CCSR);
2556 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2557 HCU_CCSR_UC_STATE_MSK);
2558 sky2_write16(hw, HCU_CCSR, status);
2559 } else
2560 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2561 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2562
2563 /* do a SW reset */
2564 sky2_write8(hw, B0_CTST, CS_RST_SET);
2565 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2566
2567 /* clear PCI errors, if any */
56a645cc 2568 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2569
cd28ab6a 2570 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2571 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2572
cd28ab6a
SH		 2573
2574 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2575
2576 /* clear any PEX errors */
7bd656d1
SH		 2577 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2578 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2579
cd28ab6a 2580
ae306cca 2581 sky2_power_on(hw);
cd28ab6a
SH		 2582
2583 for (i = 0; i < hw->ports; i++) {
2584 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2585 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2586 }
2587
2588 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2589
793b883e
SH		 2590 /* Clear I2C IRQ noise */
2591 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2592
2593 /* turn off hardware timer (unused) */
2594 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2595 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2596
cd28ab6a
SH		 2597 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2598
69634ee7
SH		 2599 /* Turn off descriptor polling */
2600 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2601
2602 /* Turn off receive timestamp */
2603 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2604 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2605
2606 /* enable the Tx Arbiters */
2607 for (i = 0; i < hw->ports; i++)
2608 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2609
2610 /* Initialize ram interface */
2611 for (i = 0; i < hw->ports; i++) {
793b883e 2612 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2613
2614 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2615 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2616 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2617 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2618 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2619 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2620 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2621 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2622 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2623 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2624 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2625 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2626 }
2627
7bd656d1 2628 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2629
cd28ab6a 2630 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2631 sky2_gmac_reset(hw, i);
cd28ab6a 2632
cd28ab6a
SH		 2633 memset(hw->st_le, 0, STATUS_LE_BYTES);
2634 hw->st_idx = 0;
2635
2636 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2637 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2638
2639 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2640 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2641
2642 /* Set the list last index */
793b883e 2643 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2644
290d4de5
SH		 2645 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2646 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2647
290d4de5
SH		 2648 /* set Status-FIFO ISR watermark */
2649 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2650 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2651 else
2652 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2653
290d4de5 2654 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2655 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2656 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2657
793b883e 2658 /* enable status unit */
cd28ab6a
SH		 2659 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2660
2661 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2662 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2663 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2664}
2665
81906791
SH		 2666static void sky2_restart(struct work_struct *work)
2667{
2668 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2669 struct net_device *dev;
2670 int i, err;
2671
2672 dev_dbg(&hw->pdev->dev, "restarting\n");
2673
2674 del_timer_sync(&hw->idle_timer);
2675
2676 rtnl_lock();
2677 sky2_write32(hw, B0_IMSK, 0);
2678 sky2_read32(hw, B0_IMSK);
2679
2680 netif_poll_disable(hw->dev[0]);
2681
2682 for (i = 0; i < hw->ports; i++) {
2683 dev = hw->dev[i];
2684 if (netif_running(dev))
2685 sky2_down(dev);
2686 }
2687
2688 sky2_reset(hw);
2689 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2690 netif_poll_enable(hw->dev[0]);
2691
2692 for (i = 0; i < hw->ports; i++) {
2693 dev = hw->dev[i];
2694 if (netif_running(dev)) {
2695 err = sky2_up(dev);
2696 if (err) {
2697 printk(KERN_INFO PFX "%s: could not restart %d\n",
2698 dev->name, err);
2699 dev_close(dev);
2700 }
2701 }
2702 }
2703
2704 sky2_idle_start(hw);
2705
2706 rtnl_unlock();
2707}
2708
e3173832
SH		 2709static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2710{
2711 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2712}
2713
2714static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2715{
2716 const struct sky2_port *sky2 = netdev_priv(dev);
2717
2718 wol->supported = sky2_wol_supported(sky2->hw);
2719 wol->wolopts = sky2->wol;
2720}
2721
2722static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2723{
2724 struct sky2_port *sky2 = netdev_priv(dev);
2725 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2726
e3173832
SH		 2727 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2728 return -EOPNOTSUPP;
2729
2730 sky2->wol = wol->wolopts;
2731
2732 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2733 sky2_write32(hw, B0_CTST, sky2->wol
2734 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2735
2736 if (!netif_running(dev))
2737 sky2_wol_init(sky2);
cd28ab6a
SH		 2738 return 0;
2739}
2740
28bd181a 2741static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2742{
b89165f2
SH		 2743 if (sky2_is_copper(hw)) {
2744 u32 modes = SUPPORTED_10baseT_Half
2745 | SUPPORTED_10baseT_Full
2746 | SUPPORTED_100baseT_Half
2747 | SUPPORTED_100baseT_Full
2748 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2749
2750 if (hw->chip_id != CHIP_ID_YUKON_FE)
2751 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2752 | SUPPORTED_1000baseT_Full;
2753 return modes;
cd28ab6a 2754 } else
b89165f2
SH		 2755 return SUPPORTED_1000baseT_Half
2756 | SUPPORTED_1000baseT_Full
2757 | SUPPORTED_Autoneg
2758 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2759}
2760
793b883e 2761static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2762{
2763 struct sky2_port *sky2 = netdev_priv(dev);
2764 struct sky2_hw *hw = sky2->hw;
2765
2766 ecmd->transceiver = XCVR_INTERNAL;
2767 ecmd->supported = sky2_supported_modes(hw);
2768 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2769 if (sky2_is_copper(hw)) {
cd28ab6a 2770 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2771 | SUPPORTED_10baseT_Full
2772 | SUPPORTED_100baseT_Half
2773 | SUPPORTED_100baseT_Full
2774 | SUPPORTED_1000baseT_Half
2775 | SUPPORTED_1000baseT_Full
2776 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2777 ecmd->port = PORT_TP;
b89165f2
SH		 2778 ecmd->speed = sky2->speed;
2779 } else {
2780 ecmd->speed = SPEED_1000;
cd28ab6a 2781 ecmd->port = PORT_FIBRE;
b89165f2 2782 }
cd28ab6a
SH		 2783
2784 ecmd->advertising = sky2->advertising;
2785 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2786 ecmd->duplex = sky2->duplex;
2787 return 0;
2788}
2789
2790static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2791{
2792 struct sky2_port *sky2 = netdev_priv(dev);
2793 const struct sky2_hw *hw = sky2->hw;
2794 u32 supported = sky2_supported_modes(hw);
2795
2796 if (ecmd->autoneg == AUTONEG_ENABLE) {
2797 ecmd->advertising = supported;
2798 sky2->duplex = -1;
2799 sky2->speed = -1;
2800 } else {
2801 u32 setting;
2802
793b883e 2803 switch (ecmd->speed) {
cd28ab6a
SH		 2804 case SPEED_1000:
2805 if (ecmd->duplex == DUPLEX_FULL)
2806 setting = SUPPORTED_1000baseT_Full;
2807 else if (ecmd->duplex == DUPLEX_HALF)
2808 setting = SUPPORTED_1000baseT_Half;
2809 else
2810 return -EINVAL;
2811 break;
2812 case SPEED_100:
2813 if (ecmd->duplex == DUPLEX_FULL)
2814 setting = SUPPORTED_100baseT_Full;
2815 else if (ecmd->duplex == DUPLEX_HALF)
2816 setting = SUPPORTED_100baseT_Half;
2817 else
2818 return -EINVAL;
2819 break;
2820
2821 case SPEED_10:
2822 if (ecmd->duplex == DUPLEX_FULL)
2823 setting = SUPPORTED_10baseT_Full;
2824 else if (ecmd->duplex == DUPLEX_HALF)
2825 setting = SUPPORTED_10baseT_Half;
2826 else
2827 return -EINVAL;
2828 break;
2829 default:
2830 return -EINVAL;
2831 }
2832
2833 if ((setting & supported) == 0)
2834 return -EINVAL;
2835
2836 sky2->speed = ecmd->speed;
2837 sky2->duplex = ecmd->duplex;
2838 }
2839
2840 sky2->autoneg = ecmd->autoneg;
2841 sky2->advertising = ecmd->advertising;
2842
1b537565
SH		 2843 if (netif_running(dev))
2844 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2845
2846 return 0;
2847}
2848
2849static void sky2_get_drvinfo(struct net_device *dev,
2850 struct ethtool_drvinfo *info)
2851{
2852 struct sky2_port *sky2 = netdev_priv(dev);
2853
2854 strcpy(info->driver, DRV_NAME);
2855 strcpy(info->version, DRV_VERSION);
2856 strcpy(info->fw_version, "N/A");
2857 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2858}
2859
2860static const struct sky2_stat {
793b883e
SH		 2861 char name[ETH_GSTRING_LEN];
2862 u16 offset;
cd28ab6a
SH		 2863} sky2_stats[] = {
2864 { "tx_bytes", GM_TXO_OK_HI },
2865 { "rx_bytes", GM_RXO_OK_HI },
2866 { "tx_broadcast", GM_TXF_BC_OK },
2867 { "rx_broadcast", GM_RXF_BC_OK },
2868 { "tx_multicast", GM_TXF_MC_OK },
2869 { "rx_multicast", GM_RXF_MC_OK },
2870 { "tx_unicast", GM_TXF_UC_OK },
2871 { "rx_unicast", GM_RXF_UC_OK },
2872 { "tx_mac_pause", GM_TXF_MPAUSE },
2873 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2874 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2875 { "late_collision",GM_TXF_LAT_COL },
2876 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2877 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2878 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2879
d2604540 2880 { "rx_short", GM_RXF_SHT },
cd28ab6a 2881 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2882 { "rx_64_byte_packets", GM_RXF_64B },
2883 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2884 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2885 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2886 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2887 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2888 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2889 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2890 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2891 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2892 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2893
2894 { "tx_64_byte_packets", GM_TXF_64B },
2895 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2896 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2897 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2898 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2899 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2900 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2901 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2902};
2903
cd28ab6a
SH		 2904static u32 sky2_get_rx_csum(struct net_device *dev)
2905{
2906 struct sky2_port *sky2 = netdev_priv(dev);
2907
2908 return sky2->rx_csum;
2909}
2910
2911static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2912{
2913 struct sky2_port *sky2 = netdev_priv(dev);
2914
2915 sky2->rx_csum = data;
793b883e 2916
cd28ab6a
SH		 2917 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2918 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2919
2920 return 0;
2921}
2922
2923static u32 sky2_get_msglevel(struct net_device *netdev)
2924{
2925 struct sky2_port *sky2 = netdev_priv(netdev);
2926 return sky2->msg_enable;
2927}
2928
9a7ae0a9
SH		 2929static int sky2_nway_reset(struct net_device *dev)
2930{
2931 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2932
16ad91e1 2933 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2934 return -EINVAL;
2935
1b537565 2936 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2937
2938 return 0;
2939}
2940
793b883e 2941static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2942{
2943 struct sky2_hw *hw = sky2->hw;
2944 unsigned port = sky2->port;
2945 int i;
2946
2947 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2948 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2949 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2950 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2951
793b883e 2952 for (i = 2; i < count; i++)
cd28ab6a
SH		 2953 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2954}
2955
cd28ab6a
SH		 2956static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2957{
2958 struct sky2_port *sky2 = netdev_priv(netdev);
2959 sky2->msg_enable = value;
2960}
2961
2962static int sky2_get_stats_count(struct net_device *dev)
2963{
2964 return ARRAY_SIZE(sky2_stats);
2965}
2966
2967static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2968 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2969{
2970 struct sky2_port *sky2 = netdev_priv(dev);
2971
793b883e 2972 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2973}
2974
793b883e 2975static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2976{
2977 int i;
2978
2979 switch (stringset) {
2980 case ETH_SS_STATS:
2981 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2982 memcpy(data + i * ETH_GSTRING_LEN,
2983 sky2_stats[i].name, ETH_GSTRING_LEN);
2984 break;
2985 }
2986}
2987
cd28ab6a
SH		 2988static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2989{
2990 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2991 return &sky2->net_stats;
2992}
2993
2994static int sky2_set_mac_address(struct net_device *dev, void *p)
2995{
2996 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2997 struct sky2_hw *hw = sky2->hw;
2998 unsigned port = sky2->port;
2999 const struct sockaddr *addr = p;
cd28ab6a
SH		 3000
3001 if (!is_valid_ether_addr(addr->sa_data))
3002 return -EADDRNOTAVAIL;
3003
cd28ab6a 3004 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3005 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3006 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3007 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3008 dev->dev_addr, ETH_ALEN);
1b537565 3009
a8ab1ec0
SH		 3010 /* virtual address for data */
3011 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3012
3013 /* physical address: used for pause frames */
3014 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3015
3016 return 0;
cd28ab6a
SH		 3017}
3018
a052b52f
SH		 3019static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3020{
3021 u32 bit;
3022
3023 bit = ether_crc(ETH_ALEN, addr) & 63;
3024 filter[bit >> 3] |= 1 << (bit & 7);
3025}
3026
cd28ab6a
SH		 3027static void sky2_set_multicast(struct net_device *dev)
3028{
3029 struct sky2_port *sky2 = netdev_priv(dev);
3030 struct sky2_hw *hw = sky2->hw;
3031 unsigned port = sky2->port;
3032 struct dev_mc_list *list = dev->mc_list;
3033 u16 reg;
3034 u8 filter[8];
a052b52f
SH		 3035 int rx_pause;
3036 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3037
a052b52f 3038 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3039 memset(filter, 0, sizeof(filter));
3040
3041 reg = gma_read16(hw, port, GM_RX_CTRL);
3042 reg |= GM_RXCR_UCF_ENA;
3043
d571b694 3044 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3045 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3046 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3047 memset(filter, 0xff, sizeof(filter));
a052b52f 3048 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3049 reg &= ~GM_RXCR_MCF_ENA;
3050 else {
3051 int i;
3052 reg |= GM_RXCR_MCF_ENA;
3053
a052b52f
SH		 3054 if (rx_pause)
3055 sky2_add_filter(filter, pause_mc_addr);
3056
3057 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3058 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3059 }
3060
cd28ab6a 3061 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3062 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3063 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3064 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3065 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3066 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3067 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3068 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3069
3070 gma_write16(hw, port, GM_RX_CTRL, reg);
3071}
3072
3073/* Can have one global because blinking is controlled by
3074 * ethtool and that is always under RTNL mutex
3075 */
91c86df5 3076static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3077{
793b883e
SH		 3078 u16 pg;
3079
793b883e
SH		 3080 switch (hw->chip_id) {
3081 case CHIP_ID_YUKON_XL:
3082 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3083 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3084 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3085 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3086 PHY_M_LEDC_INIT_CTRL(7) |
3087 PHY_M_LEDC_STA1_CTRL(7) |
3088 PHY_M_LEDC_STA0_CTRL(7))
3089 : 0);
3090
3091 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3092 break;
3093
3094 default:
3095 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3096 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3097 on ? PHY_M_LED_ALL : 0);
793b883e 3098 }
cd28ab6a
SH		 3099}
3100
3101/* blink LED's for finding board */
3102static int sky2_phys_id(struct net_device *dev, u32 data)
3103{
3104 struct sky2_port *sky2 = netdev_priv(dev);
3105 struct sky2_hw *hw = sky2->hw;
3106 unsigned port = sky2->port;
793b883e 3107 u16 ledctrl, ledover = 0;
cd28ab6a 3108 long ms;
91c86df5 3109 int interrupted;
cd28ab6a
SH		 3110 int onoff = 1;
3111
793b883e 3112 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3113 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3114 else
3115 ms = data * 1000;
3116
3117 /* save initial values */
e07b1aa8 3118 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3119 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3120 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3121 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3122 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3123 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3124 } else {
3125 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3126 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3127 }
cd28ab6a 3128
91c86df5
SH		 3129 interrupted = 0;
3130 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3131 sky2_led(hw, port, onoff);
3132 onoff = !onoff;
3133
e07b1aa8 3134 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3135 interrupted = msleep_interruptible(250);
e07b1aa8 3136 spin_lock_bh(&sky2->phy_lock);
91c86df5 3137
cd28ab6a
SH		 3138 ms -= 250;
3139 }
3140
3141 /* resume regularly scheduled programming */
793b883e
SH		 3142 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3143 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3144 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3145 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3146 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3147 } else {
3148 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3149 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3150 }
e07b1aa8 3151 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3152
3153 return 0;
3154}
3155
3156static void sky2_get_pauseparam(struct net_device *dev,
3157 struct ethtool_pauseparam *ecmd)
3158{
3159 struct sky2_port *sky2 = netdev_priv(dev);
3160
16ad91e1
SH		 3161 switch (sky2->flow_mode) {
3162 case FC_NONE:
3163 ecmd->tx_pause = ecmd->rx_pause = 0;
3164 break;
3165 case FC_TX:
3166 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3167 break;
3168 case FC_RX:
3169 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3170 break;
3171 case FC_BOTH:
3172 ecmd->tx_pause = ecmd->rx_pause = 1;
3173 }
3174
cd28ab6a
SH		 3175 ecmd->autoneg = sky2->autoneg;
3176}
3177
3178static int sky2_set_pauseparam(struct net_device *dev,
3179 struct ethtool_pauseparam *ecmd)
3180{
3181 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3182
3183 sky2->autoneg = ecmd->autoneg;
16ad91e1 3184 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3185
16ad91e1
SH		 3186 if (netif_running(dev))
3187 sky2_phy_reinit(sky2);
cd28ab6a 3188
2eaba1a2 3189 return 0;
cd28ab6a
SH		 3190}
3191
fb17358f
SH		 3192static int sky2_get_coalesce(struct net_device *dev,
3193 struct ethtool_coalesce *ecmd)
3194{
3195 struct sky2_port *sky2 = netdev_priv(dev);
3196 struct sky2_hw *hw = sky2->hw;
3197
3198 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3199 ecmd->tx_coalesce_usecs = 0;
3200 else {
3201 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3202 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3203 }
3204 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3205
3206 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3207 ecmd->rx_coalesce_usecs = 0;
3208 else {
3209 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3210 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3211 }
3212 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3213
3214 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3215 ecmd->rx_coalesce_usecs_irq = 0;
3216 else {
3217 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3218 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3219 }
3220
3221 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3222
3223 return 0;
3224}
3225
3226/* Note: this affect both ports */
3227static int sky2_set_coalesce(struct net_device *dev,
3228 struct ethtool_coalesce *ecmd)
3229{
3230 struct sky2_port *sky2 = netdev_priv(dev);
3231 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3232 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3233
77b3d6a2
SH		 3234 if (ecmd->tx_coalesce_usecs > tmax ||
3235 ecmd->rx_coalesce_usecs > tmax ||
3236 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3237 return -EINVAL;
3238
ff81fbbe 3239 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3240 return -EINVAL;
ff81fbbe 3241 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3242 return -EINVAL;
ff81fbbe 3243 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3244 return -EINVAL;
3245
3246 if (ecmd->tx_coalesce_usecs == 0)
3247 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3248 else {
3249 sky2_write32(hw, STAT_TX_TIMER_INI,
3250 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3251 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3252 }
3253 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3254
3255 if (ecmd->rx_coalesce_usecs == 0)
3256 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3257 else {
3258 sky2_write32(hw, STAT_LEV_TIMER_INI,
3259 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3260 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3261 }
3262 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3263
3264 if (ecmd->rx_coalesce_usecs_irq == 0)
3265 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3266 else {
d28d4870 3267 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3268 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3269 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3270 }
3271 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3272 return 0;
3273}
3274
793b883e
SH		 3275static void sky2_get_ringparam(struct net_device *dev,
3276 struct ethtool_ringparam *ering)
3277{
3278 struct sky2_port *sky2 = netdev_priv(dev);
3279
3280 ering->rx_max_pending = RX_MAX_PENDING;
3281 ering->rx_mini_max_pending = 0;
3282 ering->rx_jumbo_max_pending = 0;
3283 ering->tx_max_pending = TX_RING_SIZE - 1;
3284
3285 ering->rx_pending = sky2->rx_pending;
3286 ering->rx_mini_pending = 0;
3287 ering->rx_jumbo_pending = 0;
3288 ering->tx_pending = sky2->tx_pending;
3289}
3290
3291static int sky2_set_ringparam(struct net_device *dev,
3292 struct ethtool_ringparam *ering)
3293{
3294 struct sky2_port *sky2 = netdev_priv(dev);
3295 int err = 0;
3296
3297 if (ering->rx_pending > RX_MAX_PENDING ||
3298 ering->rx_pending < 8 ||
3299 ering->tx_pending < MAX_SKB_TX_LE ||
3300 ering->tx_pending > TX_RING_SIZE - 1)
3301 return -EINVAL;
3302
3303 if (netif_running(dev))
3304 sky2_down(dev);
3305
3306 sky2->rx_pending = ering->rx_pending;
3307 sky2->tx_pending = ering->tx_pending;
3308
1b537565 3309 if (netif_running(dev)) {
793b883e 3310 err = sky2_up(dev);
1b537565
SH		 3311 if (err)
3312 dev_close(dev);
6ed995bb
SH		 3313 else
3314 sky2_set_multicast(dev);
1b537565 3315 }
793b883e
SH		 3316
3317 return err;
3318}
3319
793b883e
SH		 3320static int sky2_get_regs_len(struct net_device *dev)
3321{
6e4cbb34 3322 return 0x4000;
793b883e
SH		 3323}
3324
3325/*
3326 * Returns copy of control register region
6e4cbb34 3327 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3328 */
3329static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3330 void *p)
3331{
3332 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3333 const void __iomem *io = sky2->hw->regs;
793b883e 3334
6e4cbb34 3335 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3336 regs->version = 1;
6e4cbb34 3337 memset(p, 0, regs->len);
793b883e 3338
6e4cbb34
SH		 3339 memcpy_fromio(p, io, B3_RAM_ADDR);
3340
3341 memcpy_fromio(p + B3_RI_WTO_R1,
3342 io + B3_RI_WTO_R1,
3343 regs->len - B3_RI_WTO_R1);
793b883e 3344}
cd28ab6a 3345
b628ed98
SH		 3346/* In order to do Jumbo packets on these chips, need to turn off the
3347 * transmit store/forward. Therefore checksum offload won't work.
3348 */
3349static int no_tx_offload(struct net_device *dev)
3350{
3351 const struct sky2_port *sky2 = netdev_priv(dev);
3352 const struct sky2_hw *hw = sky2->hw;
3353
3354 return dev->mtu > ETH_DATA_LEN &&
3355 (hw->chip_id == CHIP_ID_YUKON_EX
3356 || hw->chip_id == CHIP_ID_YUKON_EC_U);
3357}
3358
3359static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3360{
3361 if (data && no_tx_offload(dev))
3362 return -EINVAL;
3363
3364 return ethtool_op_set_tx_csum(dev, data);
3365}
3366
3367
3368static int sky2_set_tso(struct net_device *dev, u32 data)
3369{
3370 if (data && no_tx_offload(dev))
3371 return -EINVAL;
3372
3373 return ethtool_op_set_tso(dev, data);
3374}
3375
7282d491 3376static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3377 .get_settings = sky2_get_settings,
3378 .set_settings = sky2_set_settings,
e3173832
SH		 3379 .get_drvinfo = sky2_get_drvinfo,
3380 .get_wol = sky2_get_wol,
3381 .set_wol = sky2_set_wol,
793b883e
SH		 3382 .get_msglevel = sky2_get_msglevel,
3383 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3384 .nway_reset = sky2_nway_reset,
793b883e
SH		 3385 .get_regs_len = sky2_get_regs_len,
3386 .get_regs = sky2_get_regs,
3387 .get_link = ethtool_op_get_link,
3388 .get_sg = ethtool_op_get_sg,
3389 .set_sg = ethtool_op_set_sg,
3390 .get_tx_csum = ethtool_op_get_tx_csum,
b628ed98 3391 .set_tx_csum = sky2_set_tx_csum,
793b883e 3392 .get_tso = ethtool_op_get_tso,
b628ed98 3393 .set_tso = sky2_set_tso,
793b883e
SH		 3394 .get_rx_csum = sky2_get_rx_csum,
3395 .set_rx_csum = sky2_set_rx_csum,
3396 .get_strings = sky2_get_strings,
fb17358f
SH		 3397 .get_coalesce = sky2_get_coalesce,
3398 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3399 .get_ringparam = sky2_get_ringparam,
3400 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3401 .get_pauseparam = sky2_get_pauseparam,
3402 .set_pauseparam = sky2_set_pauseparam,
793b883e 3403 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3404 .get_stats_count = sky2_get_stats_count,
3405 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3406 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3407};
3408
3409/* Initialize network device */
3410static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3411 unsigned port,
3412 int highmem, int wol)
cd28ab6a
SH		 3413{
3414 struct sky2_port *sky2;
3415 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3416
3417 if (!dev) {
b02a9258 3418 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3419 return NULL;
3420 }
3421
3422 SET_MODULE_OWNER(dev);
3423 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3424 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3425 dev->open = sky2_up;
3426 dev->stop = sky2_down;
ef743d33 3427 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3428 dev->hard_start_xmit = sky2_xmit_frame;
3429 dev->get_stats = sky2_get_stats;
3430 dev->set_multicast_list = sky2_set_multicast;
3431 dev->set_mac_address = sky2_set_mac_address;
3432 dev->change_mtu = sky2_change_mtu;
3433 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3434 dev->tx_timeout = sky2_tx_timeout;
3435 dev->watchdog_timeo = TX_WATCHDOG;
3436 if (port == 0)
3437 dev->poll = sky2_poll;
3438 dev->weight = NAPI_WEIGHT;
3439#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3440 /* Network console (only works on port 0)
3441 * because netpoll makes assumptions about NAPI
3442 */
3443 if (port == 0)
3444 dev->poll_controller = sky2_netpoll;
cd28ab6a 3445#endif
cd28ab6a
SH		 3446
3447 sky2 = netdev_priv(dev);
3448 sky2->netdev = dev;
3449 sky2->hw = hw;
3450 sky2->msg_enable = netif_msg_init(debug, default_msg);
3451
cd28ab6a
SH		 3452 /* Auto speed and flow control */
3453 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3454 sky2->flow_mode = FC_BOTH;
3455
cd28ab6a
SH		 3456 sky2->duplex = -1;
3457 sky2->speed = -1;
3458 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3459 sky2->rx_csum = 1;
e3173832 3460 sky2->wol = wol;
75d070c5 3461
e07b1aa8 3462 spin_lock_init(&sky2->phy_lock);
793b883e 3463 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3464 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3465
3466 hw->dev[port] = dev;
3467
3468 sky2->port = port;
3469
4a50a876 3470 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3471 if (highmem)
3472 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3473
d1f13708
SH		 3474#ifdef SKY2_VLAN_TAG_USED
3475 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3476 dev->vlan_rx_register = sky2_vlan_rx_register;
3477 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3478#endif
3479
cd28ab6a 3480 /* read the mac address */
793b883e 3481 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3482 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3483
3484 /* device is off until link detection */
3485 netif_carrier_off(dev);
3486 netif_stop_queue(dev);
3487
3488 return dev;
3489}
3490
28bd181a 3491static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3492{
3493 const struct sky2_port *sky2 = netdev_priv(dev);
3494
3495 if (netif_msg_probe(sky2))
3496 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3497 dev->name,
3498 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3499 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3500}
3501
fb2690a9 3502/* Handle software interrupt used during MSI test */
7d12e780 3503static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3504{
3505 struct sky2_hw *hw = dev_id;
3506 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3507
3508 if (status == 0)
3509 return IRQ_NONE;
3510
3511 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3512 hw->msi = 1;
fb2690a9
SH		 3513 wake_up(&hw->msi_wait);
3514 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3515 }
3516 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3517
3518 return IRQ_HANDLED;
3519}
3520
3521/* Test interrupt path by forcing a a software IRQ */
3522static int __devinit sky2_test_msi(struct sky2_hw *hw)
3523{
3524 struct pci_dev *pdev = hw->pdev;
3525 int err;
3526
bb507fe1
SH		 3527 init_waitqueue_head (&hw->msi_wait);
3528
fb2690a9
SH		 3529 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3530
b0a20ded 3531 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3532 if (err) {
b02a9258 3533 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3534 return err;
3535 }
3536
fb2690a9 3537 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3538 sky2_read8(hw, B0_CTST);
fb2690a9 3539
b0a20ded 3540 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3541
b0a20ded 3542 if (!hw->msi) {
fb2690a9 3543 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3544 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3545 "switching to INTx mode.\n");
fb2690a9
SH		 3546
3547 err = -EOPNOTSUPP;
3548 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3549 }
3550
3551 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3552 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3553
3554 free_irq(pdev->irq, hw);
3555
3556 return err;
3557}
3558
e3173832
SH		 3559static int __devinit pci_wake_enabled(struct pci_dev *dev)
3560{
3561 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3562 u16 value;
3563
3564 if (!pm)
3565 return 0;
3566 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3567 return 0;
3568 return value & PCI_PM_CTRL_PME_ENABLE;
3569}
3570
cd28ab6a
SH		 3571static int __devinit sky2_probe(struct pci_dev *pdev,
3572 const struct pci_device_id *ent)
3573{
7f60c64b 3574 struct net_device *dev;
cd28ab6a 3575 struct sky2_hw *hw;
e3173832 3576 int err, using_dac = 0, wol_default;
cd28ab6a 3577
793b883e
SH		 3578 err = pci_enable_device(pdev);
3579 if (err) {
b02a9258 3580 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3581 goto err_out;
3582 }
3583
793b883e
SH		 3584 err = pci_request_regions(pdev, DRV_NAME);
3585 if (err) {
b02a9258 3586 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
793b883e 3587 goto err_out;
cd28ab6a
SH		 3588 }
3589
3590 pci_set_master(pdev);
3591
d1f3d4dd
SH		 3592 if (sizeof(dma_addr_t) > sizeof(u32) &&
3593 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3594 using_dac = 1;
3595 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3596 if (err < 0) {
b02a9258
SH		 3597 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3598 "for consistent allocations\n");
d1f3d4dd
SH		 3599 goto err_out_free_regions;
3600 }
d1f3d4dd 3601 } else {
cd28ab6a
SH		 3602 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3603 if (err) {
b02a9258 3604 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3605 goto err_out_free_regions;
3606 }
3607 }
d1f3d4dd 3608
e3173832
SH		 3609 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3610
cd28ab6a 3611 err = -ENOMEM;
6aad85d6 3612 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3613 if (!hw) {
b02a9258 3614 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3615 goto err_out_free_regions;
3616 }
3617
cd28ab6a 3618 hw->pdev = pdev;
cd28ab6a
SH		 3619
3620 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3621 if (!hw->regs) {
b02a9258 3622 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3623 goto err_out_free_hw;
3624 }
3625
56a645cc 3626#ifdef __BIG_ENDIAN
f65b138c
SH		 3627 /* The sk98lin vendor driver uses hardware byte swapping but
3628 * this driver uses software swapping.
3629 */
56a645cc
SH		 3630 {
3631 u32 reg;
56a645cc 3632 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3633 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3634 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3635 }
3636#endif
3637
08c06d8a
SH		 3638 /* ring for status responses */
3639 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3640 &hw->st_dma);
3641 if (!hw->st_le)
3642 goto err_out_iounmap;
3643
e3173832 3644 err = sky2_init(hw);
cd28ab6a 3645 if (err)
793b883e 3646 goto err_out_iounmap;
cd28ab6a 3647
b02a9258 3648 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3649 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3650 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3651 hw->chip_id, hw->chip_rev);
cd28ab6a 3652
e3173832
SH		 3653 sky2_reset(hw);
3654
3655 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3656 if (!dev) {
3657 err = -ENOMEM;
cd28ab6a 3658 goto err_out_free_pci;
7f60c64b 3659 }
cd28ab6a 3660
9fa1b1f3
SH		 3661 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3662 err = sky2_test_msi(hw);
3663 if (err == -EOPNOTSUPP)
3664 pci_disable_msi(pdev);
3665 else if (err)
3666 goto err_out_free_netdev;
3667 }
3668
793b883e
SH		 3669 err = register_netdev(dev);
3670 if (err) {
b02a9258 3671 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 3672 goto err_out_free_netdev;
3673 }
3674
b0a20ded
SH		 3675 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3676 dev->name, hw);
9fa1b1f3 3677 if (err) {
b02a9258 3678 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 3679 goto err_out_unregister;
3680 }
3681 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3682
cd28ab6a
SH		 3683 sky2_show_addr(dev);
3684
7f60c64b 3685 if (hw->ports > 1) {
3686 struct net_device *dev1;
3687
e3173832 3688 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 3689 if (!dev1)
3690 dev_warn(&pdev->dev, "allocation for second device failed\n");
3691 else if ((err = register_netdev(dev1))) {
3692 dev_warn(&pdev->dev,
3693 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 3694 hw->dev[1] = NULL;
3695 free_netdev(dev1);
b02a9258
SH		 3696 } else
3697 sky2_show_addr(dev1);
cd28ab6a
SH		 3698 }
3699
01bd7564 3700 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
81906791
SH		 3701 INIT_WORK(&hw->restart_work, sky2_restart);
3702
eb35cf60 3703 sky2_idle_start(hw);
d27ed387 3704
793b883e
SH		 3705 pci_set_drvdata(pdev, hw);
3706
cd28ab6a
SH		 3707 return 0;
3708
793b883e 3709err_out_unregister:
b0a20ded
SH		 3710 if (hw->msi)
3711 pci_disable_msi(pdev);
793b883e 3712 unregister_netdev(dev);
cd28ab6a
SH		 3713err_out_free_netdev:
3714 free_netdev(dev);
cd28ab6a 3715err_out_free_pci:
793b883e 3716 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3717 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3718err_out_iounmap:
3719 iounmap(hw->regs);
3720err_out_free_hw:
3721 kfree(hw);
3722err_out_free_regions:
3723 pci_release_regions(pdev);
cd28ab6a 3724 pci_disable_device(pdev);
cd28ab6a
SH		 3725err_out:
3726 return err;
3727}
3728
3729static void __devexit sky2_remove(struct pci_dev *pdev)
3730{
793b883e 3731 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3732 struct net_device *dev0, *dev1;
3733
793b883e 3734 if (!hw)
cd28ab6a
SH		 3735 return;
3736
d27ed387
SH		 3737 del_timer_sync(&hw->idle_timer);
3738
81906791
SH		 3739 flush_scheduled_work();
3740
d27ed387 3741 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3742 synchronize_irq(hw->pdev->irq);
3743
cd28ab6a 3744 dev0 = hw->dev[0];
793b883e
SH		 3745 dev1 = hw->dev[1];
3746 if (dev1)
3747 unregister_netdev(dev1);
cd28ab6a
SH		 3748 unregister_netdev(dev0);
3749
ae306cca
SH		 3750 sky2_power_aux(hw);
3751
cd28ab6a 3752 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3753 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3754 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3755
3756 free_irq(pdev->irq, hw);
b0a20ded
SH		 3757 if (hw->msi)
3758 pci_disable_msi(pdev);
793b883e 3759 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3760 pci_release_regions(pdev);
3761 pci_disable_device(pdev);
793b883e 3762
cd28ab6a
SH		 3763 if (dev1)
3764 free_netdev(dev1);
3765 free_netdev(dev0);
3766 iounmap(hw->regs);
3767 kfree(hw);
5afa0a9c 3768
cd28ab6a
SH		 3769 pci_set_drvdata(pdev, NULL);
3770}
3771
3772#ifdef CONFIG_PM
3773static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3774{
793b883e 3775 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 3776 int i, wol = 0;
cd28ab6a 3777
eb35cf60 3778 del_timer_sync(&hw->idle_timer);
6a5706b9 3779 netif_poll_disable(hw->dev[0]);
eb35cf60 3780
f05267e7 3781 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3782 struct net_device *dev = hw->dev[i];
e3173832 3783 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3784
e3173832 3785 if (netif_running(dev))
5afa0a9c 3786 sky2_down(dev);
e3173832
SH		 3787
3788 if (sky2->wol)
3789 sky2_wol_init(sky2);
3790
3791 wol |= sky2->wol;
cd28ab6a
SH		 3792 }
3793
8ab8fca2 3794 sky2_write32(hw, B0_IMSK, 0);
ae306cca 3795 sky2_power_aux(hw);
e3173832 3796
d374c1c1 3797 pci_save_state(pdev);
e3173832 3798 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 3799 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3800
2ccc99b7 3801 return 0;
cd28ab6a
SH		 3802}
3803
3804static int sky2_resume(struct pci_dev *pdev)
3805{
793b883e 3806 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3807 int i, err;
cd28ab6a 3808
ae306cca
SH		 3809 err = pci_set_power_state(pdev, PCI_D0);
3810 if (err)
3811 goto out;
3812
3813 err = pci_restore_state(pdev);
3814 if (err)
3815 goto out;
3816
cd28ab6a 3817 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 3818
3819 /* Re-enable all clocks */
3820 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3821 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3822
e3173832 3823 sky2_reset(hw);
cd28ab6a 3824
8ab8fca2
SH		 3825 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3826
f05267e7 3827 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3828 struct net_device *dev = hw->dev[i];
6a5706b9 3829 if (netif_running(dev)) {
08c06d8a
SH		 3830 err = sky2_up(dev);
3831 if (err) {
3832 printk(KERN_ERR PFX "%s: could not up: %d\n",
3833 dev->name, err);
3834 dev_close(dev);
eb35cf60 3835 goto out;
5afa0a9c 3836 }
cd28ab6a
SH		 3837 }
3838 }
eb35cf60 3839
6a5706b9 3840 netif_poll_enable(hw->dev[0]);
eb35cf60 3841 sky2_idle_start(hw);
ae306cca 3842 return 0;
08c06d8a 3843out:
b02a9258 3844 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 3845 pci_disable_device(pdev);
08c06d8a 3846 return err;
cd28ab6a
SH		 3847}
3848#endif
3849
e3173832
SH		 3850static void sky2_shutdown(struct pci_dev *pdev)
3851{
3852 struct sky2_hw *hw = pci_get_drvdata(pdev);
3853 int i, wol = 0;
3854
3855 del_timer_sync(&hw->idle_timer);
3856 netif_poll_disable(hw->dev[0]);
3857
3858 for (i = 0; i < hw->ports; i++) {
3859 struct net_device *dev = hw->dev[i];
3860 struct sky2_port *sky2 = netdev_priv(dev);
3861
3862 if (sky2->wol) {
3863 wol = 1;
3864 sky2_wol_init(sky2);
3865 }
3866 }
3867
3868 if (wol)
3869 sky2_power_aux(hw);
3870
3871 pci_enable_wake(pdev, PCI_D3hot, wol);
3872 pci_enable_wake(pdev, PCI_D3cold, wol);
3873
3874 pci_disable_device(pdev);
3875 pci_set_power_state(pdev, PCI_D3hot);
3876
3877}
3878
cd28ab6a 3879static struct pci_driver sky2_driver = {
793b883e
SH		 3880 .name = DRV_NAME,
3881 .id_table = sky2_id_table,
3882 .probe = sky2_probe,
3883 .remove = __devexit_p(sky2_remove),
cd28ab6a 3884#ifdef CONFIG_PM
793b883e
SH		 3885 .suspend = sky2_suspend,
3886 .resume = sky2_resume,
cd28ab6a 3887#endif
e3173832 3888 .shutdown = sky2_shutdown,
cd28ab6a
SH		 3889};
3890
3891static int __init sky2_init_module(void)
3892{
50241c4c 3893 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3894}
3895
3896static void __exit sky2_cleanup_module(void)
3897{
3898 pci_unregister_driver(&sky2_driver);
3899}
3900
3901module_init(sky2_init_module);
3902module_exit(sky2_cleanup_module);
3903
3904MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 3905MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 3906MODULE_LICENSE("GPL");
5f4f9dc1 3907MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree