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[net-next-2.6.git] / drivers / net / sky2.c
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cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
0c3f450b 53#define DRV_VERSION "1.25"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 66
ee5f68fe
SH		 67/* This is the worst case number of transmit list elements for a single skb:
68 VLAN + TSO + CKSUM + Data + skb_frags * DMA */
69#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
ee5f68fe
SH		 71#define TX_MAX_PENDING 4096
72#define TX_DEF_PENDING 127
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
e6cac9ba 102static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
SH		 142 { 0 }
143};
793b883e 144
cd28ab6a
SH		 145MODULE_DEVICE_TABLE(pci, sky2_id_table);
146
147/* Avoid conditionals by using array */
148static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
149static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 150static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 151
d1b139c0
SH		 152static void sky2_set_multicast(struct net_device *dev);
153
af043aa5 154/* Access to PHY via serial interconnect */
ef743d33 155static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 156{
157 int i;
158
159 gma_write16(hw, port, GM_SMI_DATA, val);
160 gma_write16(hw, port, GM_SMI_CTRL,
161 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
162
163 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 164 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
165 if (ctrl == 0xffff)
166 goto io_error;
167
168 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 169 return 0;
af043aa5
SH		 170
171 udelay(10);
cd28ab6a 172 }
ef743d33 173
af043aa5 174 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 175 return -ETIMEDOUT;
af043aa5
SH		 176
177io_error:
178 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
179 return -EIO;
cd28ab6a
SH		 180}
181
ef743d33 182static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 183{
184 int i;
185
793b883e 186 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 187 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
188
189 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 190 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
191 if (ctrl == 0xffff)
192 goto io_error;
193
194 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 195 *val = gma_read16(hw, port, GM_SMI_DATA);
196 return 0;
197 }
198
af043aa5 199 udelay(10);
cd28ab6a
SH		 200 }
201
af043aa5 202 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 203 return -ETIMEDOUT;
af043aa5
SH		 204io_error:
205 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
206 return -EIO;
ef743d33
SH		 207}
208
af043aa5 209static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 210{
211 u16 v;
af043aa5 212 __gm_phy_read(hw, port, reg, &v);
ef743d33 213 return v;
cd28ab6a
SH		 214}
215
5afa0a9c 216
ae306cca
SH		 217static void sky2_power_on(struct sky2_hw *hw)
218{
219 /* switch power to VCC (WA for VAUX problem) */
220 sky2_write8(hw, B0_POWER_CTRL,
221 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 222
ae306cca
SH		 223 /* disable Core Clock Division, */
224 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 225
ae306cca
SH		 226 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
227 /* enable bits are inverted */
228 sky2_write8(hw, B2_Y2_CLK_GATE,
229 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
230 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
231 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
232 else
233 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 234
ea76e635 235 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 236 u32 reg;
5afa0a9c 237
b32f40c4 238 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 239
b32f40c4 240 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 241 /* set all bits to 0 except bits 15..12 and 8 */
242 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 243 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 244
b32f40c4 245 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 246 /* set all bits to 0 except bits 28 & 27 */
247 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 248 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 249
b32f40c4 250 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 251
252 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
253 reg = sky2_read32(hw, B2_GP_IO);
254 reg |= GLB_GPIO_STAT_RACE_DIS;
255 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 256
257 sky2_read32(hw, B2_GP_IO);
5afa0a9c 258 }
ae306cca 259}
5afa0a9c 260
ae306cca
SH		 261static void sky2_power_aux(struct sky2_hw *hw)
262{
263 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
264 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
265 else
266 /* enable bits are inverted */
267 sky2_write8(hw, B2_Y2_CLK_GATE,
268 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
269 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
270 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
271
272 /* switch power to VAUX */
273 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
274 sky2_write8(hw, B0_POWER_CTRL,
275 (PC_VAUX_ENA | PC_VCC_ENA |
276 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 277}
278
d3bcfbeb 279static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 280{
281 u16 reg;
282
283 /* disable all GMAC IRQ's */
284 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 285
cd28ab6a
SH		 286 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
287 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
288 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
289 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
290
291 reg = gma_read16(hw, port, GM_RX_CTRL);
292 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
293 gma_write16(hw, port, GM_RX_CTRL, reg);
294}
295
16ad91e1
SH		 296/* flow control to advertise bits */
297static const u16 copper_fc_adv[] = {
298 [FC_NONE] = 0,
299 [FC_TX] = PHY_M_AN_ASP,
300 [FC_RX] = PHY_M_AN_PC,
301 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
302};
303
304/* flow control to advertise bits when using 1000BaseX */
305static const u16 fiber_fc_adv[] = {
df3fe1f3 306 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 307 [FC_TX] = PHY_M_P_ASYM_MD_X,
308 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 309 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 310};
311
312/* flow control to GMA disable bits */
313static const u16 gm_fc_disable[] = {
314 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
315 [FC_TX] = GM_GPCR_FC_RX_DIS,
316 [FC_RX] = GM_GPCR_FC_TX_DIS,
317 [FC_BOTH] = 0,
318};
319
320
cd28ab6a
SH		 321static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
322{
323 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 324 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 325
0ea065e5 326 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 327 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 328 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
329
330 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 331 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 332 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
333
53419c68 334 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 335 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 336 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 337 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
338 else
53419c68
SH		 339 /* set master & slave downshift counter to 1x */
340 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 341
342 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
343 }
344
345 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 346 if (sky2_is_copper(hw)) {
05745c4a 347 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 348 /* enable automatic crossover */
349 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 350
351 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
352 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
353 u16 spec;
354
355 /* Enable Class A driver for FE+ A0 */
356 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
357 spec |= PHY_M_FESC_SEL_CL_A;
358 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
359 }
cd28ab6a
SH		 360 } else {
361 /* disable energy detect */
362 ctrl &= ~PHY_M_PC_EN_DET_MSK;
363
364 /* enable automatic crossover */
365 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
366
53419c68 367 /* downshift on PHY 88E1112 and 88E1149 is changed */
0ea065e5 368 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED)
ea76e635 369 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 370 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 371 ctrl &= ~PHY_M_PC_DSC_MSK;
372 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
373 }
374 }
cd28ab6a
SH		 375 } else {
376 /* workaround for deviation #4.88 (CRC errors) */
377 /* disable Automatic Crossover */
378
379 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 380 }
cd28ab6a 381
b89165f2
SH		 382 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
383
384 /* special setup for PHY 88E1112 Fiber */
ea76e635 385 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 386 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 387
b89165f2
SH		 388 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
389 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
390 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
391 ctrl &= ~PHY_M_MAC_MD_MSK;
392 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
394
395 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 396 /* select page 1 to access Fiber registers */
397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 398
399 /* for SFP-module set SIGDET polarity to low */
400 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
401 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 402 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 403 }
b89165f2
SH		 404
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 406 }
407
7800fddc 408 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 409 ct1000 = 0;
410 adv = PHY_AN_CSMA;
2eaba1a2 411 reg = 0;
cd28ab6a 412
0ea065e5 413 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 414 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 415 if (sky2->advertising & ADVERTISED_1000baseT_Full)
416 ct1000 |= PHY_M_1000C_AFD;
417 if (sky2->advertising & ADVERTISED_1000baseT_Half)
418 ct1000 |= PHY_M_1000C_AHD;
419 if (sky2->advertising & ADVERTISED_100baseT_Full)
420 adv |= PHY_M_AN_100_FD;
421 if (sky2->advertising & ADVERTISED_100baseT_Half)
422 adv |= PHY_M_AN_100_HD;
423 if (sky2->advertising & ADVERTISED_10baseT_Full)
424 adv |= PHY_M_AN_10_FD;
425 if (sky2->advertising & ADVERTISED_10baseT_Half)
426 adv |= PHY_M_AN_10_HD;
709c6e7b 427
b89165f2
SH		 428 } else { /* special defines for FIBER (88E1040S only) */
429 if (sky2->advertising & ADVERTISED_1000baseT_Full)
430 adv |= PHY_M_AN_1000X_AFD;
431 if (sky2->advertising & ADVERTISED_1000baseT_Half)
432 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 433 }
cd28ab6a
SH		 434
435 /* Restart Auto-negotiation */
436 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
437 } else {
438 /* forced speed/duplex settings */
439 ct1000 = PHY_M_1000C_MSE;
440
0ea065e5
SH		 441 /* Disable auto update for duplex flow control and duplex */
442 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 443
444 switch (sky2->speed) {
445 case SPEED_1000:
446 ctrl |= PHY_CT_SP1000;
2eaba1a2 447 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 448 break;
449 case SPEED_100:
450 ctrl |= PHY_CT_SP100;
2eaba1a2 451 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 452 break;
453 }
454
2eaba1a2
SH		 455 if (sky2->duplex == DUPLEX_FULL) {
456 reg |= GM_GPCR_DUP_FULL;
457 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 458 } else if (sky2->speed < SPEED_1000)
459 sky2->flow_mode = FC_NONE;
0ea065e5 460 }
2eaba1a2 461
0ea065e5
SH		 462 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
463 if (sky2_is_copper(hw))
464 adv |= copper_fc_adv[sky2->flow_mode];
465 else
466 adv |= fiber_fc_adv[sky2->flow_mode];
467 } else {
468 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 469 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 470
471 /* Forward pause packets to GMAC? */
16ad91e1 472 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 473 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
474 else
475 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 476 }
477
2eaba1a2
SH		 478 gma_write16(hw, port, GM_GP_CTRL, reg);
479
05745c4a 480 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 481 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
482
483 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
484 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
485
486 /* Setup Phy LED's */
487 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
488 ledover = 0;
489
490 switch (hw->chip_id) {
491 case CHIP_ID_YUKON_FE:
492 /* on 88E3082 these bits are at 11..9 (shifted left) */
493 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
494
495 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
496
497 /* delete ACT LED control bits */
498 ctrl &= ~PHY_M_FELP_LED1_MSK;
499 /* change ACT LED control to blink mode */
500 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
501 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
502 break;
503
05745c4a
SH		 504 case CHIP_ID_YUKON_FE_P:
505 /* Enable Link Partner Next Page */
506 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
507 ctrl |= PHY_M_PC_ENA_LIP_NP;
508
509 /* disable Energy Detect and enable scrambler */
510 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
511 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
512
513 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
514 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
515 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
516 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
517
518 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
519 break;
520
cd28ab6a 521 case CHIP_ID_YUKON_XL:
793b883e 522 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 523
524 /* select page 3 to access LED control register */
525 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
526
527 /* set LED Function Control register */
ed6d32c7
SH		 528 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
529 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
530 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
531 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
532 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 533
534 /* set Polarity Control register */
535 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 536 (PHY_M_POLC_LS1_P_MIX(4) |
537 PHY_M_POLC_IS0_P_MIX(4) |
538 PHY_M_POLC_LOS_CTRL(2) |
539 PHY_M_POLC_INIT_CTRL(2) |
540 PHY_M_POLC_STA1_CTRL(2) |
541 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 542
543 /* restore page register */
793b883e 544 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 545 break;
93745494 546
ed6d32c7 547 case CHIP_ID_YUKON_EC_U:
93745494 548 case CHIP_ID_YUKON_EX:
ed4d4161 549 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 550 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
551
552 /* select page 3 to access LED control register */
553 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
554
555 /* set LED Function Control register */
556 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
557 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
558 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
559 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
560 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
561
562 /* set Blink Rate in LED Timer Control Register */
563 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
564 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
565 /* restore page register */
566 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
567 break;
cd28ab6a
SH		 568
569 default:
570 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
571 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 572
cd28ab6a 573 /* turn off the Rx LED (LED_RX) */
a84d0a3d 574 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 575 }
576
0ce8b98d 577 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 578 /* apply fixes in PHY AFE */
ed6d32c7
SH		 579 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
580
977bdf06 581 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 582 gm_phy_write(hw, port, 0x18, 0xaa99);
583 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 584
0ce8b98d
SH		 585 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
586 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
587 gm_phy_write(hw, port, 0x18, 0xa204);
588 gm_phy_write(hw, port, 0x17, 0x2002);
589 }
977bdf06
SH		 590
591 /* set page register to 0 */
9467a8fc 592 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 593 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
594 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
595 /* apply workaround for integrated resistors calibration */
596 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
597 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 598 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
599 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 600 /* no effect on Yukon-XL */
977bdf06 601 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 602
0ea065e5
SH		 603 if ( !(sky2->flags & SKY2_FLAG_AUTO_SPEED)
604 || sky2->speed == SPEED_100) {
977bdf06 605 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 606 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 607 }
cd28ab6a 608
977bdf06
SH		 609 if (ledover)
610 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
611
612 }
2eaba1a2 613
d571b694 614 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 615 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 616 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
617 else
618 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
619}
620
b96936da
SH		 621static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
622static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
623
624static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 625{
626 u32 reg1;
d3bcfbeb 627
82637e80 628 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 629 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 630 reg1 &= ~phy_power[port];
d3bcfbeb 631
b96936da 632 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 633 reg1 |= coma_mode[port];
634
b32f40c4 635 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 636 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
637 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 638
639 if (hw->chip_id == CHIP_ID_YUKON_FE)
640 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
641 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
642 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 643}
167f53d0 644
b96936da
SH		 645static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
646{
647 u32 reg1;
db99b988
SH		 648 u16 ctrl;
649
650 /* release GPHY Control reset */
651 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
652
653 /* release GMAC reset */
654 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
655
656 if (hw->flags & SKY2_HW_NEWER_PHY) {
657 /* select page 2 to access MAC control register */
658 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
659
660 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
661 /* allow GMII Power Down */
662 ctrl &= ~PHY_M_MAC_GMIF_PUP;
663 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
664
665 /* set page register back to 0 */
666 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
667 }
668
669 /* setup General Purpose Control Register */
670 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 671 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
672 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
673 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 674
675 if (hw->chip_id != CHIP_ID_YUKON_EC) {
676 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 677 /* select page 2 to access MAC control register */
678 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 679
e484d5f5 680 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 681 /* enable Power Down */
682 ctrl |= PHY_M_PC_POW_D_ENA;
683 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 684
685 /* set page register back to 0 */
686 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 687 }
688
689 /* set IEEE compatible Power Down Mode (dev. #4.99) */
690 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
691 }
b96936da
SH		 692
693 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
694 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 695 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 696 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
697 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 698}
699
1b537565
SH		 700/* Force a renegotiation */
701static void sky2_phy_reinit(struct sky2_port *sky2)
702{
e07b1aa8 703 spin_lock_bh(&sky2->phy_lock);
1b537565 704 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 705 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 706}
707
e3173832
SH		 708/* Put device in state to listen for Wake On Lan */
709static void sky2_wol_init(struct sky2_port *sky2)
710{
711 struct sky2_hw *hw = sky2->hw;
712 unsigned port = sky2->port;
713 enum flow_control save_mode;
714 u16 ctrl;
715 u32 reg1;
716
717 /* Bring hardware out of reset */
718 sky2_write16(hw, B0_CTST, CS_RST_CLR);
719 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
720
721 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
722 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
723
724 /* Force to 10/100
725 * sky2_reset will re-enable on resume
726 */
727 save_mode = sky2->flow_mode;
728 ctrl = sky2->advertising;
729
730 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
731 sky2->flow_mode = FC_NONE;
b96936da
SH		 732
733 spin_lock_bh(&sky2->phy_lock);
734 sky2_phy_power_up(hw, port);
735 sky2_phy_init(hw, port);
736 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 737
738 sky2->flow_mode = save_mode;
739 sky2->advertising = ctrl;
740
741 /* Set GMAC to no flow control and auto update for speed/duplex */
742 gma_write16(hw, port, GM_GP_CTRL,
743 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
744 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
745
746 /* Set WOL address */
747 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
748 sky2->netdev->dev_addr, ETH_ALEN);
749
750 /* Turn on appropriate WOL control bits */
751 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
752 ctrl = 0;
753 if (sky2->wol & WAKE_PHY)
754 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
755 else
756 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
757
758 if (sky2->wol & WAKE_MAGIC)
759 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
760 else
761 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
762
763 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
764 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
765
766 /* Turn on legacy PCI-Express PME mode */
b32f40c4 767 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 768 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 769 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 770
771 /* block receiver */
772 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
773
774}
775
69161611
SH		 776static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
777{
05745c4a
SH		 778 struct net_device *dev = hw->dev[port];
779
ed4d4161
SH		 780 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
781 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
782 hw->chip_id == CHIP_ID_YUKON_FE_P ||
783 hw->chip_id == CHIP_ID_YUKON_SUPR) {
784 /* Yukon-Extreme B0 and further Extreme devices */
785 /* enable Store & Forward mode for TX */
05745c4a 786
ed4d4161
SH		 787 if (dev->mtu <= ETH_DATA_LEN)
788 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
789 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 790
ed4d4161
SH		 791 else
792 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
793 TX_JUMBO_ENA| TX_STFW_ENA);
794 } else {
795 if (dev->mtu <= ETH_DATA_LEN)
796 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
797 else {
798 /* set Tx GMAC FIFO Almost Empty Threshold */
799 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
800 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 801
ed4d4161
SH		 802 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
803
804 /* Can't do offload because of lack of store/forward */
805 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
806 }
69161611
SH		 807 }
808}
809
cd28ab6a
SH		 810static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
811{
812 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
813 u16 reg;
25cccecc 814 u32 rx_reg;
cd28ab6a
SH		 815 int i;
816 const u8 *addr = hw->dev[port]->dev_addr;
817
f350339c
SH		 818 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
819 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 820
821 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
822
793b883e 823 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 824 /* WA DEV_472 -- looks like crossed wires on port 2 */
825 /* clear GMAC 1 Control reset */
826 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
827 do {
828 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
829 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
830 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
831 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
832 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
833 }
834
793b883e 835 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 836
2eaba1a2
SH		 837 /* Enable Transmit FIFO Underrun */
838 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
839
e07b1aa8 840 spin_lock_bh(&sky2->phy_lock);
b96936da 841 sky2_phy_power_up(hw, port);
cd28ab6a 842 sky2_phy_init(hw, port);
e07b1aa8 843 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 844
845 /* MIB clear */
846 reg = gma_read16(hw, port, GM_PHY_ADDR);
847 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
848
43f2f104
SH		 849 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
850 gma_read16(hw, port, i);
cd28ab6a
SH		 851 gma_write16(hw, port, GM_PHY_ADDR, reg);
852
853 /* transmit control */
854 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
855
856 /* receive control reg: unicast + multicast + no FCS */
857 gma_write16(hw, port, GM_RX_CTRL,
793b883e 858 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 859
860 /* transmit flow control */
861 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
862
863 /* transmit parameter */
864 gma_write16(hw, port, GM_TX_PARAM,
865 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
866 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
867 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
868 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
869
870 /* serial mode register */
871 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 872 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 873
6b1a3aef 874 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 875 reg |= GM_SMOD_JUMBO_ENA;
876
877 gma_write16(hw, port, GM_SERIAL_MODE, reg);
878
cd28ab6a
SH		 879 /* virtual address for data */
880 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
881
793b883e
SH		 882 /* physical address: used for pause frames */
883 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
884
885 /* ignore counter overflows */
cd28ab6a
SH		 886 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
887 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
888 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
889
890 /* Configure Rx MAC FIFO */
891 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 892 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 893 if (hw->chip_id == CHIP_ID_YUKON_EX ||
894 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 895 rx_reg |= GMF_RX_OVER_ON;
69161611 896
25cccecc 897 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 898
798fdd07
SH		 899 if (hw->chip_id == CHIP_ID_YUKON_XL) {
900 /* Hardware errata - clear flush mask */
901 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
902 } else {
903 /* Flush Rx MAC FIFO on any flow control or error */
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
905 }
cd28ab6a 906
8df9a876 907 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 908 reg = RX_GMF_FL_THR_DEF + 1;
909 /* Another magic mystery workaround from sk98lin */
910 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
911 hw->chip_rev == CHIP_REV_YU_FE2_A0)
912 reg = 0x178;
913 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 914
915 /* Configure Tx MAC FIFO */
916 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
917 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 918
e0c28116 919 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 920 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 921 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 922 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 923
69161611 924 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 925 }
926
e970d1f8
SH		 927 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
928 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
929 /* disable dynamic watermark */
930 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
931 reg &= ~TX_DYN_WM_ENA;
932 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
933 }
cd28ab6a
SH		 934}
935
67712901
SH		 936/* Assign Ram Buffer allocation to queue */
937static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 938{
67712901
SH		 939 u32 end;
940
941 /* convert from K bytes to qwords used for hw register */
942 start *= 1024/8;
943 space *= 1024/8;
944 end = start + space - 1;
793b883e 945
cd28ab6a
SH		 946 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
947 sky2_write32(hw, RB_ADDR(q, RB_START), start);
948 sky2_write32(hw, RB_ADDR(q, RB_END), end);
949 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
950 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
951
952 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 953 u32 tp = space - space/4;
793b883e 954
1c28f6ba
SH		 955 /* On receive queue's set the thresholds
956 * give receiver priority when > 3/4 full
957 * send pause when down to 2K
958 */
959 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
960 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 961
1c28f6ba
SH		 962 tp = space - 2048/8;
963 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
964 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 965 } else {
966 /* Enable store & forward on Tx queue's because
967 * Tx FIFO is only 1K on Yukon
968 */
969 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
970 }
971
972 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 973 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 974}
975
cd28ab6a 976/* Setup Bus Memory Interface */
af4ed7e6 977static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 978{
979 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
980 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
981 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 982 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 983}
984
cd28ab6a
SH		 985/* Setup prefetch unit registers. This is the interface between
986 * hardware and driver list elements
987 */
8cc048e3 988static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 989 dma_addr_t addr, u32 last)
cd28ab6a 990{
cd28ab6a
SH		 991 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
992 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 993 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
994 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 995 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
996 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 997
998 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 999}
1000
9b289c33 1001static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1002{
9b289c33 1003 struct sky2_tx_le *le = sky2->tx_le + *slot;
6b84daca 1004 struct tx_ring_info *re = sky2->tx_ring + *slot;
793b883e 1005
ee5f68fe 1006 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
6b84daca
SH		 1007 re->flags = 0;
1008 re->skb = NULL;
291ea614 1009 le->ctrl = 0;
793b883e
SH		 1010 return le;
1011}
cd28ab6a 1012
88f5f0ca
SH		 1013static void tx_init(struct sky2_port *sky2)
1014{
1015 struct sky2_tx_le *le;
1016
1017 sky2->tx_prod = sky2->tx_cons = 0;
1018 sky2->tx_tcpsum = 0;
1019 sky2->tx_last_mss = 0;
1020
9b289c33 1021 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1022 le->addr = 0;
1023 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1024 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1025}
1026
290d4de5
SH		 1027/* Update chip's next pointer */
1028static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1029{
50432cb5 1030 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1031 wmb();
50432cb5
SH		 1032 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1033
1034 /* Synchronize I/O on since next processor may write to tail */
1035 mmiowb();
cd28ab6a
SH		 1036}
1037
793b883e 1038
cd28ab6a
SH		 1039static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1040{
1041 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1042 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1043 le->ctrl = 0;
cd28ab6a
SH		 1044 return le;
1045}
1046
14d0263f
SH		 1047/* Build description to hardware for one receive segment */
1048static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1049 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1050{
1051 struct sky2_rx_le *le;
1052
86c6887e 1053 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1054 le = sky2_next_rx(sky2);
86c6887e 1055 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1056 le->opcode = OP_ADDR64 | HW_OWNER;
1057 }
793b883e 1058
cd28ab6a 1059 le = sky2_next_rx(sky2);
d6e74b6b 1060 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1061 le->length = cpu_to_le16(len);
14d0263f 1062 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1063}
1064
14d0263f
SH		 1065/* Build description to hardware for one possibly fragmented skb */
1066static void sky2_rx_submit(struct sky2_port *sky2,
1067 const struct rx_ring_info *re)
1068{
1069 int i;
1070
1071 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1072
1073 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1074 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1075}
1076
1077
454e6cb6 1078static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1079 unsigned size)
1080{
1081 struct sk_buff *skb = re->skb;
1082 int i;
1083
1084 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
454e6cb6
SH		 1085 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1086 return -EIO;
1087
14d0263f
SH		 1088 pci_unmap_len_set(re, data_size, size);
1089
1090 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1091 re->frag_addr[i] = pci_map_page(pdev,
1092 skb_shinfo(skb)->frags[i].page,
1093 skb_shinfo(skb)->frags[i].page_offset,
1094 skb_shinfo(skb)->frags[i].size,
1095 PCI_DMA_FROMDEVICE);
454e6cb6 1096 return 0;
14d0263f
SH		 1097}
1098
1099static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1100{
1101 struct sk_buff *skb = re->skb;
1102 int i;
1103
1104 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1105 PCI_DMA_FROMDEVICE);
1106
1107 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1108 pci_unmap_page(pdev, re->frag_addr[i],
1109 skb_shinfo(skb)->frags[i].size,
1110 PCI_DMA_FROMDEVICE);
1111}
793b883e 1112
cd28ab6a
SH		 1113/* Tell chip where to start receive checksum.
1114 * Actually has two checksums, but set both same to avoid possible byte
1115 * order problems.
1116 */
793b883e 1117static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1118{
ea76e635 1119 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1120
ea76e635
SH		 1121 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1122 le->ctrl = 0;
1123 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1124
ea76e635
SH		 1125 sky2_write32(sky2->hw,
1126 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1127 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1128 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1129}
1130
6b1a3aef
SH		 1131/*
1132 * The RX Stop command will not work for Yukon-2 if the BMU does not
1133 * reach the end of packet and since we can't make sure that we have
1134 * incoming data, we must reset the BMU while it is not doing a DMA
1135 * transfer. Since it is possible that the RX path is still active,
1136 * the RX RAM buffer will be stopped first, so any possible incoming
1137 * data will not trigger a DMA. After the RAM buffer is stopped, the
1138 * BMU is polled until any DMA in progress is ended and only then it
1139 * will be reset.
1140 */
1141static void sky2_rx_stop(struct sky2_port *sky2)
1142{
1143 struct sky2_hw *hw = sky2->hw;
1144 unsigned rxq = rxqaddr[sky2->port];
1145 int i;
1146
1147 /* disable the RAM Buffer receive queue */
1148 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1149
1150 for (i = 0; i < 0xffff; i++)
1151 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1152 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1153 goto stopped;
1154
1155 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1156 sky2->netdev->name);
1157stopped:
1158 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1159
1160 /* reset the Rx prefetch unit */
1161 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1162 mmiowb();
6b1a3aef 1163}
793b883e 1164
d571b694 1165/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1166static void sky2_rx_clean(struct sky2_port *sky2)
1167{
1168 unsigned i;
1169
1170 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1171 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1172 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1173
1174 if (re->skb) {
14d0263f 1175 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1176 kfree_skb(re->skb);
1177 re->skb = NULL;
1178 }
1179 }
1180}
1181
ef743d33
SH		 1182/* Basic MII support */
1183static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1184{
1185 struct mii_ioctl_data *data = if_mii(ifr);
1186 struct sky2_port *sky2 = netdev_priv(dev);
1187 struct sky2_hw *hw = sky2->hw;
1188 int err = -EOPNOTSUPP;
1189
1190 if (!netif_running(dev))
1191 return -ENODEV; /* Phy still in reset */
1192
d89e1343 1193 switch (cmd) {
ef743d33
SH		 1194 case SIOCGMIIPHY:
1195 data->phy_id = PHY_ADDR_MARV;
1196
1197 /* fallthru */
1198 case SIOCGMIIREG: {
1199 u16 val = 0;
91c86df5 1200
e07b1aa8 1201 spin_lock_bh(&sky2->phy_lock);
ef743d33 1202 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1203 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1204
ef743d33
SH		 1205 data->val_out = val;
1206 break;
1207 }
1208
1209 case SIOCSMIIREG:
1210 if (!capable(CAP_NET_ADMIN))
1211 return -EPERM;
1212
e07b1aa8 1213 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1214 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1215 data->val_in);
e07b1aa8 1216 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1217 break;
1218 }
1219 return err;
1220}
1221
d1f13708 1222#ifdef SKY2_VLAN_TAG_USED
d494eacd 1223static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1224{
d494eacd 1225 if (onoff) {
3d4e66f5
SH		 1226 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1227 RX_VLAN_STRIP_ON);
1228 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1229 TX_VLAN_TAG_ON);
1230 } else {
1231 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1232 RX_VLAN_STRIP_OFF);
1233 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1234 TX_VLAN_TAG_OFF);
1235 }
d494eacd
SH		 1236}
1237
1238static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1239{
1240 struct sky2_port *sky2 = netdev_priv(dev);
1241 struct sky2_hw *hw = sky2->hw;
1242 u16 port = sky2->port;
1243
1244 netif_tx_lock_bh(dev);
1245 napi_disable(&hw->napi);
1246
1247 sky2->vlgrp = grp;
1248 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1249
d1d08d12 1250 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1251 napi_enable(&hw->napi);
2bb8c262 1252 netif_tx_unlock_bh(dev);
d1f13708
SH		 1253}
1254#endif
1255
bd1c6869
SH		 1256/* Amount of required worst case padding in rx buffer */
1257static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1258{
1259 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1260}
1261
82788c7a 1262/*
14d0263f
SH		 1263 * Allocate an skb for receiving. If the MTU is large enough
1264 * make the skb non-linear with a fragment list of pages.
82788c7a 1265 */
14d0263f 1266static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1267{
1268 struct sk_buff *skb;
14d0263f 1269 int i;
82788c7a 1270
724b6942
SH		 1271 skb = netdev_alloc_skb(sky2->netdev,
1272 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1273 if (!skb)
1274 goto nomem;
1275
39dbd958 1276 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1277 unsigned char *start;
1278 /*
1279 * Workaround for a bug in FIFO that cause hang
1280 * if the FIFO if the receive buffer is not 64 byte aligned.
1281 * The buffer returned from netdev_alloc_skb is
1282 * aligned except if slab debugging is enabled.
1283 */
f03b8654
SH		 1284 start = PTR_ALIGN(skb->data, 8);
1285 skb_reserve(skb, start - skb->data);
bd1c6869 1286 } else
f03b8654 1287 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1288
1289 for (i = 0; i < sky2->rx_nfrags; i++) {
1290 struct page *page = alloc_page(GFP_ATOMIC);
1291
1292 if (!page)
1293 goto free_partial;
1294 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1295 }
1296
1297 return skb;
14d0263f
SH		 1298free_partial:
1299 kfree_skb(skb);
1300nomem:
1301 return NULL;
82788c7a
SH		 1302}
1303
55c9dd35
SH		 1304static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1305{
1306 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1307}
1308
cd28ab6a
SH		 1309/*
1310 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1311 * Normal case this ends up creating one list element for skb
1312 * in the receive ring. Worst case if using large MTU and each
1313 * allocation falls on a different 64 bit region, that results
1314 * in 6 list elements per ring entry.
1315 * One element is used for checksum enable/disable, and one
1316 * extra to avoid wrap.
cd28ab6a 1317 */
6b1a3aef 1318static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1319{
6b1a3aef 1320 struct sky2_hw *hw = sky2->hw;
14d0263f 1321 struct rx_ring_info *re;
6b1a3aef 1322 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1323 unsigned i, size, thresh;
cd28ab6a 1324
6b1a3aef 1325 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1326 sky2_qset(hw, rxq);
977bdf06 1327
c3905bc4
SH		 1328 /* On PCI express lowering the watermark gives better performance */
1329 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1330 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1331
1332 /* These chips have no ram buffer?
1333 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1334 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1335 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1336 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1337 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1338
6b1a3aef
SH		 1339 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1340
ea76e635
SH		 1341 if (!(hw->flags & SKY2_HW_NEW_LE))
1342 rx_set_checksum(sky2);
14d0263f
SH		 1343
1344 /* Space needed for frame data + headers rounded up */
f957da2a 1345 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1346
1347 /* Stopping point for hardware truncation */
1348 thresh = (size - 8) / sizeof(u32);
1349
5f06eba4 1350 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1351 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1352
5f06eba4
SH		 1353 /* Compute residue after pages */
1354 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1355
5f06eba4
SH		 1356 /* Optimize to handle small packets and headers */
1357 if (size < copybreak)
1358 size = copybreak;
1359 if (size < ETH_HLEN)
1360 size = ETH_HLEN;
14d0263f 1361
14d0263f
SH		 1362 sky2->rx_data_size = size;
1363
1364 /* Fill Rx ring */
793b883e 1365 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1366 re = sky2->rx_ring + i;
cd28ab6a 1367
14d0263f 1368 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1369 if (!re->skb)
1370 goto nomem;
1371
454e6cb6
SH		 1372 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1373 dev_kfree_skb(re->skb);
1374 re->skb = NULL;
1375 goto nomem;
1376 }
1377
14d0263f 1378 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1379 }
1380
a1433ac4
SH		 1381 /*
1382 * The receiver hangs if it receives frames larger than the
1383 * packet buffer. As a workaround, truncate oversize frames, but
1384 * the register is limited to 9 bits, so if you do frames > 2052
1385 * you better get the MTU right!
1386 */
a1433ac4
SH		 1387 if (thresh > 0x1ff)
1388 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1389 else {
1390 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1391 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1392 }
1393
6b1a3aef 1394 /* Tell chip about available buffers */
55c9dd35 1395 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1396 return 0;
1397nomem:
1398 sky2_rx_clean(sky2);
1399 return -ENOMEM;
1400}
1401
1402/* Bring up network interface. */
1403static int sky2_up(struct net_device *dev)
1404{
1405 struct sky2_port *sky2 = netdev_priv(dev);
1406 struct sky2_hw *hw = sky2->hw;
1407 unsigned port = sky2->port;
e0c28116 1408 u32 imask, ramsize;
ee7abb04 1409 int cap, err = -ENOMEM;
843a46f4 1410 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1411
ee7abb04
SH		 1412 /*
1413 * On dual port PCI-X card, there is an problem where status
1414 * can be received out of order due to split transactions
843a46f4 1415 */
ee7abb04
SH		 1416 if (otherdev && netif_running(otherdev) &&
1417 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1418 u16 cmd;
1419
b32f40c4 1420 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1421 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1422 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1423
ee7abb04 1424 }
843a46f4 1425
55d7b4e6
SH		 1426 netif_carrier_off(dev);
1427
cd28ab6a
SH		 1428 /* must be power of 2 */
1429 sky2->tx_le = pci_alloc_consistent(hw->pdev,
ee5f68fe 1430 sky2->tx_ring_size *
793b883e 1431 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1432 &sky2->tx_le_map);
1433 if (!sky2->tx_le)
1434 goto err_out;
1435
ee5f68fe 1436 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1437 GFP_KERNEL);
1438 if (!sky2->tx_ring)
1439 goto err_out;
88f5f0ca
SH		 1440
1441 tx_init(sky2);
cd28ab6a
SH		 1442
1443 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1444 &sky2->rx_le_map);
1445 if (!sky2->rx_le)
1446 goto err_out;
1447 memset(sky2->rx_le, 0, RX_LE_BYTES);
1448
291ea614 1449 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1450 GFP_KERNEL);
1451 if (!sky2->rx_ring)
1452 goto err_out;
1453
1454 sky2_mac_init(hw, port);
1455
e0c28116
SH		 1456 /* Register is number of 4K blocks on internal RAM buffer. */
1457 ramsize = sky2_read8(hw, B2_E_0) * 4;
1458 if (ramsize > 0) {
67712901 1459 u32 rxspace;
cd28ab6a 1460
39dbd958 1461 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1462 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1463 if (ramsize < 16)
1464 rxspace = ramsize / 2;
1465 else
1466 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1467
67712901
SH		 1468 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1469 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1470
1471 /* Make sure SyncQ is disabled */
1472 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1473 RB_RST_SET);
1474 }
793b883e 1475
af4ed7e6 1476 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1477
69161611
SH		 1478 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1479 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1480 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1481
977bdf06 1482 /* Set almost empty threshold */
c2716fb4
SH		 1483 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1484 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1485 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1486
6b1a3aef 1487 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1488 sky2->tx_ring_size - 1);
cd28ab6a 1489
d494eacd
SH		 1490#ifdef SKY2_VLAN_TAG_USED
1491 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1492#endif
1493
6b1a3aef 1494 err = sky2_rx_start(sky2);
6de16237 1495 if (err)
cd28ab6a
SH		 1496 goto err_out;
1497
cd28ab6a 1498 /* Enable interrupts from phy/mac for port */
e07b1aa8 1499 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1500 imask |= portirq_msk[port];
e07b1aa8 1501 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1502 sky2_read32(hw, B0_IMSK);
e07b1aa8 1503
a11da890
AD		 1504 if (netif_msg_ifup(sky2))
1505 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
af18d8b8 1506
cd28ab6a
SH		 1507 return 0;
1508
1509err_out:
1b537565 1510 if (sky2->rx_le) {
cd28ab6a
SH		 1511 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1512 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1513 sky2->rx_le = NULL;
1514 }
1515 if (sky2->tx_le) {
cd28ab6a 1516 pci_free_consistent(hw->pdev,
ee5f68fe 1517 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
cd28ab6a 1518 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1519 sky2->tx_le = NULL;
1520 }
1521 kfree(sky2->tx_ring);
1522 kfree(sky2->rx_ring);
cd28ab6a 1523
1b537565
SH		 1524 sky2->tx_ring = NULL;
1525 sky2->rx_ring = NULL;
cd28ab6a
SH		 1526 return err;
1527}
1528
793b883e 1529/* Modular subtraction in ring */
ee5f68fe 1530static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1531{
ee5f68fe 1532 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1533}
cd28ab6a 1534
793b883e
SH		 1535/* Number of list elements available for next tx */
1536static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1537{
ee5f68fe 1538 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1539}
1540
793b883e 1541/* Estimate of number of transmit list elements required */
28bd181a 1542static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1543{
793b883e
SH		 1544 unsigned count;
1545
1546 count = sizeof(dma_addr_t) / sizeof(u32);
1547 count += skb_shinfo(skb)->nr_frags * count;
1548
89114afd 1549 if (skb_is_gso(skb))
793b883e
SH		 1550 ++count;
1551
84fa7933 1552 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1553 ++count;
1554
1555 return count;
cd28ab6a
SH		 1556}
1557
6b84daca
SH		 1558static void sky2_tx_unmap(struct pci_dev *pdev,
1559 const struct tx_ring_info *re)
1560{
1561 if (re->flags & TX_MAP_SINGLE)
1562 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1563 pci_unmap_len(re, maplen),
1564 PCI_DMA_TODEVICE);
1565 else if (re->flags & TX_MAP_PAGE)
1566 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1567 pci_unmap_len(re, maplen),
1568 PCI_DMA_TODEVICE);
1569}
1570
793b883e
SH		 1571/*
1572 * Put one packet in ring for transmit.
1573 * A single packet can generate multiple list elements, and
1574 * the number of ring elements will probably be less than the number
1575 * of list elements used.
1576 */
61357325
SH		 1577static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1578 struct net_device *dev)
cd28ab6a
SH		 1579{
1580 struct sky2_port *sky2 = netdev_priv(dev);
1581 struct sky2_hw *hw = sky2->hw;
d1f13708 1582 struct sky2_tx_le *le = NULL;
6cdbbdf3 1583 struct tx_ring_info *re;
9b289c33 1584 unsigned i, len;
cd28ab6a 1585 dma_addr_t mapping;
5dce95e5
SH		 1586 u32 upper;
1587 u16 slot;
cd28ab6a
SH		 1588 u16 mss;
1589 u8 ctrl;
1590
2bb8c262
SH		 1591 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1592 return NETDEV_TX_BUSY;
cd28ab6a 1593
cd28ab6a
SH		 1594 len = skb_headlen(skb);
1595 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1596
454e6cb6
SH		 1597 if (pci_dma_mapping_error(hw->pdev, mapping))
1598 goto mapping_error;
1599
9b289c33 1600 slot = sky2->tx_prod;
454e6cb6
SH		 1601 if (unlikely(netif_msg_tx_queued(sky2)))
1602 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
9b289c33 1603 dev->name, slot, skb->len);
454e6cb6 1604
86c6887e 1605 /* Send high bits if needed */
5dce95e5
SH		 1606 upper = upper_32_bits(mapping);
1607 if (upper != sky2->tx_last_upper) {
9b289c33 1608 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1609 le->addr = cpu_to_le32(upper);
1610 sky2->tx_last_upper = upper;
793b883e 1611 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1612 }
cd28ab6a
SH		 1613
1614 /* Check for TCP Segmentation Offload */
7967168c 1615 mss = skb_shinfo(skb)->gso_size;
793b883e 1616 if (mss != 0) {
ea76e635
SH		 1617
1618 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1619 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1620
1621 if (mss != sky2->tx_last_mss) {
9b289c33 1622 le = get_tx_le(sky2, &slot);
69161611 1623 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1624
1625 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1626 le->opcode = OP_MSS | HW_OWNER;
1627 else
1628 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1629 sky2->tx_last_mss = mss;
1630 }
cd28ab6a
SH		 1631 }
1632
cd28ab6a 1633 ctrl = 0;
d1f13708
SH		 1634#ifdef SKY2_VLAN_TAG_USED
1635 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1636 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1637 if (!le) {
9b289c33 1638 le = get_tx_le(sky2, &slot);
f65b138c 1639 le->addr = 0;
d1f13708 1640 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1641 } else
1642 le->opcode |= OP_VLAN;
1643 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1644 ctrl |= INS_VLAN;
1645 }
1646#endif
1647
1648 /* Handle TCP checksum offload */
84fa7933 1649 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1650 /* On Yukon EX (some versions) encoding change. */
ea76e635 1651 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1652 ctrl |= CALSUM; /* auto checksum */
1653 else {
1654 const unsigned offset = skb_transport_offset(skb);
1655 u32 tcpsum;
1656
1657 tcpsum = offset << 16; /* sum start */
1658 tcpsum |= offset + skb->csum_offset; /* sum write */
1659
1660 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1661 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1662 ctrl |= UDPTCP;
1663
1664 if (tcpsum != sky2->tx_tcpsum) {
1665 sky2->tx_tcpsum = tcpsum;
1666
9b289c33 1667 le = get_tx_le(sky2, &slot);
69161611
SH		 1668 le->addr = cpu_to_le32(tcpsum);
1669 le->length = 0; /* initial checksum value */
1670 le->ctrl = 1; /* one packet */
1671 le->opcode = OP_TCPLISW | HW_OWNER;
1672 }
1d179332 1673 }
cd28ab6a
SH		 1674 }
1675
6b84daca
SH		 1676 re = sky2->tx_ring + slot;
1677 re->flags = TX_MAP_SINGLE;
1678 pci_unmap_addr_set(re, mapaddr, mapping);
1679 pci_unmap_len_set(re, maplen, len);
1680
9b289c33 1681 le = get_tx_le(sky2, &slot);
d6e74b6b 1682 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1683 le->length = cpu_to_le16(len);
1684 le->ctrl = ctrl;
793b883e 1685 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1686
cd28ab6a
SH		 1687
1688 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1689 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1690
1691 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1692 frag->size, PCI_DMA_TODEVICE);
86c6887e 1693
454e6cb6
SH		 1694 if (pci_dma_mapping_error(hw->pdev, mapping))
1695 goto mapping_unwind;
1696
5dce95e5
SH		 1697 upper = upper_32_bits(mapping);
1698 if (upper != sky2->tx_last_upper) {
9b289c33 1699 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1700 le->addr = cpu_to_le32(upper);
1701 sky2->tx_last_upper = upper;
793b883e 1702 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1703 }
1704
6b84daca
SH		 1705 re = sky2->tx_ring + slot;
1706 re->flags = TX_MAP_PAGE;
1707 pci_unmap_addr_set(re, mapaddr, mapping);
1708 pci_unmap_len_set(re, maplen, frag->size);
1709
9b289c33 1710 le = get_tx_le(sky2, &slot);
d6e74b6b 1711 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1712 le->length = cpu_to_le16(frag->size);
1713 le->ctrl = ctrl;
793b883e 1714 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1715 }
6cdbbdf3 1716
6b84daca 1717 re->skb = skb;
cd28ab6a
SH		 1718 le->ctrl |= EOP;
1719
9b289c33
MM		 1720 sky2->tx_prod = slot;
1721
97bda706
SH		 1722 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1723 netif_stop_queue(dev);
b19666d9 1724
290d4de5 1725 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1726
cd28ab6a 1727 return NETDEV_TX_OK;
454e6cb6
SH		 1728
1729mapping_unwind:
ee5f68fe 1730 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1731 re = sky2->tx_ring + i;
1732
6b84daca 1733 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1734 }
1735
454e6cb6
SH		 1736mapping_error:
1737 if (net_ratelimit())
1738 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1739 dev_kfree_skb(skb);
1740 return NETDEV_TX_OK;
cd28ab6a
SH		 1741}
1742
cd28ab6a 1743/*
793b883e
SH		 1744 * Free ring elements from starting at tx_cons until "done"
1745 *
481cea4a
SH		 1746 * NB:
1747 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1748 * buffers so make sure not to free skb to early.
481cea4a
SH		 1749 * 2. This may run in parallel start_xmit because the it only
1750 * looks at the tail of the queue of FIFO (tx_cons), not
1751 * the head (tx_prod)
cd28ab6a 1752 */
d11c13e7 1753static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1754{
d11c13e7 1755 struct net_device *dev = sky2->netdev;
291ea614 1756 unsigned idx;
cd28ab6a 1757
ee5f68fe 1758 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1759
291ea614 1760 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1761 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1762 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1763 struct sk_buff *skb = re->skb;
291ea614 1764
6b84daca 1765 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1766
6b84daca 1767 if (skb) {
291ea614
SH		 1768 if (unlikely(netif_msg_tx_done(sky2)))
1769 printk(KERN_DEBUG "%s: tx done %u\n",
1770 dev->name, idx);
3cf26753 1771
7138a0f5 1772 dev->stats.tx_packets++;
bd1c6869
SH		 1773 dev->stats.tx_bytes += skb->len;
1774
724b6942 1775 dev_kfree_skb_any(skb);
2bf56fe2 1776
ee5f68fe 1777 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1778 }
793b883e 1779 }
793b883e 1780
291ea614 1781 sky2->tx_cons = idx;
50432cb5
SH		 1782 smp_mb();
1783
22e11703 1784 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1785 netif_wake_queue(dev);
cd28ab6a
SH		 1786}
1787
264bb4fa 1788static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1789{
a510996b
MM		 1790 /* Disable Force Sync bit and Enable Alloc bit */
1791 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1792 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1793
1794 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1795 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1796 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1797
1798 /* Reset the PCI FIFO of the async Tx queue */
1799 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1800 BMU_RST_SET | BMU_FIFO_RST);
1801
1802 /* Reset the Tx prefetch units */
1803 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1804 PREF_UNIT_RST_SET);
1805
1806 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1807 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1808}
1809
cd28ab6a
SH		 1810/* Network shutdown */
1811static int sky2_down(struct net_device *dev)
1812{
1813 struct sky2_port *sky2 = netdev_priv(dev);
1814 struct sky2_hw *hw = sky2->hw;
1815 unsigned port = sky2->port;
1816 u16 ctrl;
e07b1aa8 1817 u32 imask;
cd28ab6a 1818
1b537565
SH		 1819 /* Never really got started! */
1820 if (!sky2->tx_le)
1821 return 0;
1822
cd28ab6a
SH		 1823 if (netif_msg_ifdown(sky2))
1824 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1825
d104acaf
SH		 1826 /* Force flow control off */
1827 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1828
cd28ab6a
SH		 1829 /* Stop transmitter */
1830 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1831 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1832
1833 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1834 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1835
1836 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1837 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1838 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1839
1840 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1841
1842 /* Workaround shared GMAC reset */
793b883e
SH		 1843 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1844 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1845 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1846
cd28ab6a 1847 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1848
6c83504f
SH		 1849 /* Force any delayed status interrrupt and NAPI */
1850 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1851 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1852 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1853 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1854
a947a39d
MM		 1855 sky2_rx_stop(sky2);
1856
1857 /* Disable port IRQ */
1858 imask = sky2_read32(hw, B0_IMSK);
1859 imask &= ~portirq_msk[port];
1860 sky2_write32(hw, B0_IMSK, imask);
1861 sky2_read32(hw, B0_IMSK);
1862
6c83504f
SH		 1863 synchronize_irq(hw->pdev->irq);
1864 napi_synchronize(&hw->napi);
1865
0da6d7b3 1866 spin_lock_bh(&sky2->phy_lock);
b96936da 1867 sky2_phy_power_down(hw, port);
0da6d7b3 1868 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1869
d571b694 1870 /* turn off LED's */
cd28ab6a
SH		 1871 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1872
264bb4fa
MM		 1873 sky2_tx_reset(hw, port);
1874
481cea4a
SH		 1875 /* Free any pending frames stuck in HW queue */
1876 sky2_tx_complete(sky2, sky2->tx_prod);
1877
cd28ab6a
SH		 1878 sky2_rx_clean(sky2);
1879
1880 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1881 sky2->rx_le, sky2->rx_le_map);
1882 kfree(sky2->rx_ring);
1883
1884 pci_free_consistent(hw->pdev,
ee5f68fe 1885 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1886 sky2->tx_le, sky2->tx_le_map);
1887 kfree(sky2->tx_ring);
1888
1b537565
SH		 1889 sky2->tx_le = NULL;
1890 sky2->rx_le = NULL;
1891
1892 sky2->rx_ring = NULL;
1893 sky2->tx_ring = NULL;
1894
cd28ab6a
SH		 1895 return 0;
1896}
1897
1898static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1899{
ea76e635 1900 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1901 return SPEED_1000;
1902
05745c4a
SH		 1903 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1904 if (aux & PHY_M_PS_SPEED_100)
1905 return SPEED_100;
1906 else
1907 return SPEED_10;
1908 }
cd28ab6a
SH		 1909
1910 switch (aux & PHY_M_PS_SPEED_MSK) {
1911 case PHY_M_PS_SPEED_1000:
1912 return SPEED_1000;
1913 case PHY_M_PS_SPEED_100:
1914 return SPEED_100;
1915 default:
1916 return SPEED_10;
1917 }
1918}
1919
1920static void sky2_link_up(struct sky2_port *sky2)
1921{
1922 struct sky2_hw *hw = sky2->hw;
1923 unsigned port = sky2->port;
1924 u16 reg;
16ad91e1
SH		 1925 static const char *fc_name[] = {
1926 [FC_NONE] = "none",
1927 [FC_TX] = "tx",
1928 [FC_RX] = "rx",
1929 [FC_BOTH] = "both",
1930 };
cd28ab6a 1931
cd28ab6a 1932 /* enable Rx/Tx */
2eaba1a2 1933 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1934 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1935 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1936
1937 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1938
1939 netif_carrier_on(sky2->netdev);
cd28ab6a 1940
75e80683 1941 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1942
cd28ab6a 1943 /* Turn on link LED */
793b883e 1944 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1945 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1946
1947 if (netif_msg_link(sky2))
1948 printk(KERN_INFO PFX
d571b694 1949 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1950 sky2->netdev->name, sky2->speed,
1951 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1952 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1953}
1954
1955static void sky2_link_down(struct sky2_port *sky2)
1956{
1957 struct sky2_hw *hw = sky2->hw;
1958 unsigned port = sky2->port;
1959 u16 reg;
1960
1961 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1962
1963 reg = gma_read16(hw, port, GM_GP_CTRL);
1964 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1965 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1966
cd28ab6a 1967 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1968
1969 /* Turn on link LED */
1970 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1971
1972 if (netif_msg_link(sky2))
1973 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1974
cd28ab6a
SH		 1975 sky2_phy_init(hw, port);
1976}
1977
16ad91e1
SH		 1978static enum flow_control sky2_flow(int rx, int tx)
1979{
1980 if (rx)
1981 return tx ? FC_BOTH : FC_RX;
1982 else
1983 return tx ? FC_TX : FC_NONE;
1984}
1985
793b883e
SH		 1986static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1987{
1988 struct sky2_hw *hw = sky2->hw;
1989 unsigned port = sky2->port;
da4c1ff4 1990 u16 advert, lpa;
793b883e 1991
da4c1ff4 1992 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1993 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1994 if (lpa & PHY_M_AN_RF) {
1995 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1996 return -1;
1997 }
1998
793b883e
SH		 1999 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2000 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2001 sky2->netdev->name);
2002 return -1;
2003 }
2004
793b883e 2005 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2006 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2007
da4c1ff4
SH		 2008 /* Since the pause result bits seem to in different positions on
2009 * different chips. look at registers.
2010 */
ea76e635 2011 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2012 /* Shift for bits in fiber PHY */
2013 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2014 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2015
2016 if (advert & ADVERTISE_1000XPAUSE)
2017 advert |= ADVERTISE_PAUSE_CAP;
2018 if (advert & ADVERTISE_1000XPSE_ASYM)
2019 advert |= ADVERTISE_PAUSE_ASYM;
2020 if (lpa & LPA_1000XPAUSE)
2021 lpa |= LPA_PAUSE_CAP;
2022 if (lpa & LPA_1000XPAUSE_ASYM)
2023 lpa |= LPA_PAUSE_ASYM;
2024 }
793b883e 2025
da4c1ff4
SH		 2026 sky2->flow_status = FC_NONE;
2027 if (advert & ADVERTISE_PAUSE_CAP) {
2028 if (lpa & LPA_PAUSE_CAP)
2029 sky2->flow_status = FC_BOTH;
2030 else if (advert & ADVERTISE_PAUSE_ASYM)
2031 sky2->flow_status = FC_RX;
2032 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2033 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2034 sky2->flow_status = FC_TX;
2035 }
793b883e 2036
16ad91e1 2037 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 2038 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2039 sky2->flow_status = FC_NONE;
2eaba1a2 2040
da4c1ff4 2041 if (sky2->flow_status & FC_TX)
793b883e
SH		 2042 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2043 else
2044 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2045
2046 return 0;
2047}
cd28ab6a 2048
e07b1aa8
SH		 2049/* Interrupt from PHY */
2050static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2051{
e07b1aa8
SH		 2052 struct net_device *dev = hw->dev[port];
2053 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2054 u16 istatus, phystat;
2055
ebc646f6
SH		 2056 if (!netif_running(dev))
2057 return;
2058
e07b1aa8
SH		 2059 spin_lock(&sky2->phy_lock);
2060 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2061 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2062
cd28ab6a
SH		 2063 if (netif_msg_intr(sky2))
2064 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2065 sky2->netdev->name, istatus, phystat);
2066
0ea065e5 2067 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2068 if (sky2_autoneg_done(sky2, phystat) == 0)
2069 sky2_link_up(sky2);
2070 goto out;
2071 }
cd28ab6a 2072
793b883e
SH		 2073 if (istatus & PHY_M_IS_LSP_CHANGE)
2074 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2075
793b883e
SH		 2076 if (istatus & PHY_M_IS_DUP_CHANGE)
2077 sky2->duplex =
2078 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2079
793b883e
SH		 2080 if (istatus & PHY_M_IS_LST_CHANGE) {
2081 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2082 sky2_link_up(sky2);
793b883e
SH		 2083 else
2084 sky2_link_down(sky2);
cd28ab6a 2085 }
793b883e 2086out:
e07b1aa8 2087 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2088}
2089
62335ab0 2090/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2091 * and tx queue is full (stopped).
2092 */
cd28ab6a
SH		 2093static void sky2_tx_timeout(struct net_device *dev)
2094{
2095 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2096 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2097
2098 if (netif_msg_timer(sky2))
2099 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2100
8f24664d 2101 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2102 dev->name, sky2->tx_cons, sky2->tx_prod,
2103 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2104 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2105
81906791
SH		 2106 /* can't restart safely under softirq */
2107 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2108}
2109
2110static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2111{
6b1a3aef
SH		 2112 struct sky2_port *sky2 = netdev_priv(dev);
2113 struct sky2_hw *hw = sky2->hw;
b628ed98 2114 unsigned port = sky2->port;
6b1a3aef
SH		 2115 int err;
2116 u16 ctl, mode;
e07b1aa8 2117 u32 imask;
cd28ab6a
SH		 2118
2119 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2120 return -EINVAL;
2121
05745c4a
SH		 2122 if (new_mtu > ETH_DATA_LEN &&
2123 (hw->chip_id == CHIP_ID_YUKON_FE ||
2124 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2125 return -EINVAL;
2126
6b1a3aef
SH		 2127 if (!netif_running(dev)) {
2128 dev->mtu = new_mtu;
2129 return 0;
2130 }
2131
e07b1aa8 2132 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2133 sky2_write32(hw, B0_IMSK, 0);
2134
018d1c66
SH		 2135 dev->trans_start = jiffies; /* prevent tx timeout */
2136 netif_stop_queue(dev);
bea3348e 2137 napi_disable(&hw->napi);
018d1c66 2138
e07b1aa8
SH		 2139 synchronize_irq(hw->pdev->irq);
2140
39dbd958 2141 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2142 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2143
2144 ctl = gma_read16(hw, port, GM_GP_CTRL);
2145 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2146 sky2_rx_stop(sky2);
2147 sky2_rx_clean(sky2);
cd28ab6a
SH		 2148
2149 dev->mtu = new_mtu;
14d0263f 2150
6b1a3aef
SH		 2151 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2152 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2153
2154 if (dev->mtu > ETH_DATA_LEN)
2155 mode |= GM_SMOD_JUMBO_ENA;
2156
b628ed98 2157 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2158
b628ed98 2159 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2160
6b1a3aef 2161 err = sky2_rx_start(sky2);
e07b1aa8 2162 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2163
d1d08d12 2164 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2165 napi_enable(&hw->napi);
2166
1b537565
SH		 2167 if (err)
2168 dev_close(dev);
2169 else {
b628ed98 2170 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2171
1b537565
SH		 2172 netif_wake_queue(dev);
2173 }
2174
cd28ab6a
SH		 2175 return err;
2176}
2177
14d0263f
SH		 2178/* For small just reuse existing skb for next receive */
2179static struct sk_buff *receive_copy(struct sky2_port *sky2,
2180 const struct rx_ring_info *re,
2181 unsigned length)
2182{
2183 struct sk_buff *skb;
2184
2185 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2186 if (likely(skb)) {
2187 skb_reserve(skb, 2);
2188 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2189 length, PCI_DMA_FROMDEVICE);
d626f62b 2190 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2191 skb->ip_summed = re->skb->ip_summed;
2192 skb->csum = re->skb->csum;
2193 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2194 length, PCI_DMA_FROMDEVICE);
2195 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2196 skb_put(skb, length);
14d0263f
SH		 2197 }
2198 return skb;
2199}
2200
2201/* Adjust length of skb with fragments to match received data */
2202static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2203 unsigned int length)
2204{
2205 int i, num_frags;
2206 unsigned int size;
2207
2208 /* put header into skb */
2209 size = min(length, hdr_space);
2210 skb->tail += size;
2211 skb->len += size;
2212 length -= size;
2213
2214 num_frags = skb_shinfo(skb)->nr_frags;
2215 for (i = 0; i < num_frags; i++) {
2216 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2217
2218 if (length == 0) {
2219 /* don't need this page */
2220 __free_page(frag->page);
2221 --skb_shinfo(skb)->nr_frags;
2222 } else {
2223 size = min(length, (unsigned) PAGE_SIZE);
2224
2225 frag->size = size;
2226 skb->data_len += size;
2227 skb->truesize += size;
2228 skb->len += size;
2229 length -= size;
2230 }
2231 }
2232}
2233
2234/* Normal packet - take skb from ring element and put in a new one */
2235static struct sk_buff *receive_new(struct sky2_port *sky2,
2236 struct rx_ring_info *re,
2237 unsigned int length)
2238{
2239 struct sk_buff *skb, *nskb;
2240 unsigned hdr_space = sky2->rx_data_size;
2241
14d0263f
SH		 2242 /* Don't be tricky about reusing pages (yet) */
2243 nskb = sky2_rx_alloc(sky2);
2244 if (unlikely(!nskb))
2245 return NULL;
2246
2247 skb = re->skb;
2248 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2249
2250 prefetch(skb->data);
2251 re->skb = nskb;
454e6cb6
SH		 2252 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2253 dev_kfree_skb(nskb);
2254 re->skb = skb;
2255 return NULL;
2256 }
14d0263f
SH		 2257
2258 if (skb_shinfo(skb)->nr_frags)
2259 skb_put_frags(skb, hdr_space, length);
2260 else
489b10c1 2261 skb_put(skb, length);
14d0263f
SH		 2262 return skb;
2263}
2264
cd28ab6a
SH		 2265/*
2266 * Receive one packet.
d571b694 2267 * For larger packets, get new buffer.
cd28ab6a 2268 */
497d7c86 2269static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2270 u16 length, u32 status)
2271{
497d7c86 2272 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2273 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2274 struct sk_buff *skb = NULL;
d6532232
SH		 2275 u16 count = (status & GMR_FS_LEN) >> 16;
2276
2277#ifdef SKY2_VLAN_TAG_USED
2278 /* Account for vlan tag */
2279 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2280 count -= VLAN_HLEN;
2281#endif
cd28ab6a
SH		 2282
2283 if (unlikely(netif_msg_rx_status(sky2)))
2284 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2285 dev->name, sky2->rx_next, status, length);
cd28ab6a 2286
793b883e 2287 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2288 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2289
3b12e014
SH		 2290 /* This chip has hardware problems that generates bogus status.
2291 * So do only marginal checking and expect higher level protocols
2292 * to handle crap frames.
2293 */
2294 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2295 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2296 length != count)
2297 goto okay;
2298
42eeea01 2299 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2300 goto error;
2301
42eeea01
SH		 2302 if (!(status & GMR_FS_RX_OK))
2303 goto resubmit;
2304
d6532232
SH		 2305 /* if length reported by DMA does not match PHY, packet was truncated */
2306 if (length != count)
3b12e014 2307 goto len_error;
71749531 2308
3b12e014 2309okay:
14d0263f
SH		 2310 if (length < copybreak)
2311 skb = receive_copy(sky2, re, length);
2312 else
2313 skb = receive_new(sky2, re, length);
793b883e 2314resubmit:
14d0263f 2315 sky2_rx_submit(sky2, re);
79e57d32 2316
cd28ab6a
SH		 2317 return skb;
2318
3b12e014 2319len_error:
71749531
SH		 2320 /* Truncation of overlength packets
2321 causes PHY length to not match MAC length */
7138a0f5 2322 ++dev->stats.rx_length_errors;
d6532232 2323 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2324 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2325 dev->name, status, length);
d6532232 2326 goto resubmit;
71749531 2327
cd28ab6a 2328error:
7138a0f5 2329 ++dev->stats.rx_errors;
b6d77734 2330 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2331 dev->stats.rx_over_errors++;
b6d77734
SH		 2332 goto resubmit;
2333 }
6e15b712 2334
3be92a70 2335 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2336 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2337 dev->name, status, length);
793b883e
SH		 2338
2339 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2340 dev->stats.rx_length_errors++;
cd28ab6a 2341 if (status & GMR_FS_FRAGMENT)
7138a0f5 2342 dev->stats.rx_frame_errors++;
cd28ab6a 2343 if (status & GMR_FS_CRC_ERR)
7138a0f5 2344 dev->stats.rx_crc_errors++;
79e57d32 2345
793b883e 2346 goto resubmit;
cd28ab6a
SH		 2347}
2348
e07b1aa8
SH		 2349/* Transmit complete */
2350static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2351{
e07b1aa8 2352 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2353
49d4b8ba 2354 if (netif_running(dev))
e07b1aa8 2355 sky2_tx_complete(sky2, last);
cd28ab6a
SH		 2356}
2357
37e5a243
SH		 2358static inline void sky2_skb_rx(const struct sky2_port *sky2,
2359 u32 status, struct sk_buff *skb)
2360{
2361#ifdef SKY2_VLAN_TAG_USED
2362 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2363 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2364 if (skb->ip_summed == CHECKSUM_NONE)
2365 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2366 else
2367 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2368 vlan_tag, skb);
2369 return;
2370 }
2371#endif
2372 if (skb->ip_summed == CHECKSUM_NONE)
2373 netif_receive_skb(skb);
2374 else
2375 napi_gro_receive(&sky2->hw->napi, skb);
2376}
2377
bf15fe99
SH		 2378static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2379 unsigned packets, unsigned bytes)
2380{
2381 if (packets) {
2382 struct net_device *dev = hw->dev[port];
2383
2384 dev->stats.rx_packets += packets;
2385 dev->stats.rx_bytes += bytes;
2386 dev->last_rx = jiffies;
2387 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2388 }
2389}
2390
e07b1aa8 2391/* Process status response ring */
26691830 2392static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2393{
e07b1aa8 2394 int work_done = 0;
bf15fe99
SH		 2395 unsigned int total_bytes[2] = { 0 };
2396 unsigned int total_packets[2] = { 0 };
a8fd6266 2397
af2a58ac 2398 rmb();
26691830 2399 do {
55c9dd35 2400 struct sky2_port *sky2;
13210ce5 2401 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2402 unsigned port;
13210ce5 2403 struct net_device *dev;
cd28ab6a 2404 struct sk_buff *skb;
cd28ab6a
SH		 2405 u32 status;
2406 u16 length;
ab5adecb
SH		 2407 u8 opcode = le->opcode;
2408
2409 if (!(opcode & HW_OWNER))
2410 break;
cd28ab6a 2411
cb5d9547 2412 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2413
ab5adecb 2414 port = le->css & CSS_LINK_BIT;
69161611 2415 dev = hw->dev[port];
13210ce5 2416 sky2 = netdev_priv(dev);
f65b138c
SH		 2417 length = le16_to_cpu(le->length);
2418 status = le32_to_cpu(le->status);
cd28ab6a 2419
ab5adecb
SH		 2420 le->opcode = 0;
2421 switch (opcode & ~HW_OWNER) {
cd28ab6a 2422 case OP_RXSTAT:
bf15fe99
SH		 2423 total_packets[port]++;
2424 total_bytes[port] += length;
497d7c86 2425 skb = sky2_receive(dev, length, status);
3225b919 2426 if (unlikely(!skb)) {
7138a0f5 2427 dev->stats.rx_dropped++;
55c9dd35 2428 break;
3225b919 2429 }
13210ce5 2430
69161611 2431 /* This chip reports checksum status differently */
05745c4a 2432 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2433 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2434 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2435 (le->css & CSS_TCPUDPCSOK))
2436 skb->ip_summed = CHECKSUM_UNNECESSARY;
2437 else
2438 skb->ip_summed = CHECKSUM_NONE;
2439 }
2440
13210ce5 2441 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2442
37e5a243 2443 sky2_skb_rx(sky2, status, skb);
13210ce5 2444
22e11703 2445 /* Stop after net poll weight */
13210ce5
SH		 2446 if (++work_done >= to_do)
2447 goto exit_loop;
cd28ab6a
SH		 2448 break;
2449
d1f13708
SH		 2450#ifdef SKY2_VLAN_TAG_USED
2451 case OP_RXVLAN:
2452 sky2->rx_tag = length;
2453 break;
2454
2455 case OP_RXCHKSVLAN:
2456 sky2->rx_tag = length;
2457 /* fall through */
2458#endif
cd28ab6a 2459 case OP_RXCHKS:
0ea065e5 2460 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
87418307
SH		 2461 break;
2462
05745c4a
SH		 2463 /* If this happens then driver assuming wrong format */
2464 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2465 if (net_ratelimit())
2466 printk(KERN_NOTICE "%s: unexpected"
2467 " checksum status\n",
2468 dev->name);
69161611 2469 break;
05745c4a 2470 }
69161611 2471
87418307
SH		 2472 /* Both checksum counters are programmed to start at
2473 * the same offset, so unless there is a problem they
2474 * should match. This failure is an early indication that
2475 * hardware receive checksumming won't work.
2476 */
2477 if (likely(status >> 16 == (status & 0xffff))) {
2478 skb = sky2->rx_ring[sky2->rx_next].skb;
2479 skb->ip_summed = CHECKSUM_COMPLETE;
b9389796 2480 skb->csum = le16_to_cpu(status);
87418307
SH		 2481 } else {
2482 printk(KERN_NOTICE PFX "%s: hardware receive "
2483 "checksum problem (status = %#x)\n",
2484 dev->name, status);
0ea065e5
SH		 2485 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2486
87418307 2487 sky2_write32(sky2->hw,
69161611 2488 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2489 BMU_DIS_RX_CHKSUM);
2490 }
cd28ab6a
SH		 2491 break;
2492
2493 case OP_TXINDEXLE:
13b97b74 2494 /* TX index reports status for both ports */
f55925d7 2495 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2496 if (hw->dev[1])
2497 sky2_tx_done(hw->dev[1],
2498 ((status >> 24) & 0xff)
2499 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2500 break;
2501
cd28ab6a
SH		 2502 default:
2503 if (net_ratelimit())
793b883e 2504 printk(KERN_WARNING PFX
ab5adecb 2505 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2506 }
26691830 2507 } while (hw->st_idx != idx);
cd28ab6a 2508
fe2a24df
SH		 2509 /* Fully processed status ring so clear irq */
2510 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2511
13210ce5 2512exit_loop:
bf15fe99
SH		 2513 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2514 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2515
e07b1aa8 2516 return work_done;
cd28ab6a
SH		 2517}
2518
2519static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2520{
2521 struct net_device *dev = hw->dev[port];
2522
3be92a70
SH		 2523 if (net_ratelimit())
2524 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2525 dev->name, status);
cd28ab6a
SH		 2526
2527 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2528 if (net_ratelimit())
2529 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2530 dev->name);
cd28ab6a
SH		 2531 /* Clear IRQ */
2532 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2533 }
2534
2535 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2536 if (net_ratelimit())
2537 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2538 dev->name);
cd28ab6a
SH		 2539
2540 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2541 }
2542
2543 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2544 if (net_ratelimit())
2545 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2546 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2547 }
2548
2549 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2550 if (net_ratelimit())
2551 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2552 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2553 }
2554
2555 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2556 if (net_ratelimit())
2557 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2558 dev->name);
cd28ab6a
SH		 2559 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2560 }
2561}
2562
2563static void sky2_hw_intr(struct sky2_hw *hw)
2564{
555382cb 2565 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2566 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2567 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2568
2569 status &= hwmsk;
cd28ab6a 2570
793b883e 2571 if (status & Y2_IS_TIST_OV)
cd28ab6a 2572 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2573
2574 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2575 u16 pci_err;
2576
82637e80 2577 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2578 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2579 if (net_ratelimit())
555382cb 2580 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2581 pci_err);
cd28ab6a 2582
b32f40c4 2583 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2584 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2585 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2586 }
2587
2588 if (status & Y2_IS_PCI_EXP) {
d571b694 2589 /* PCI-Express uncorrectable Error occurred */
555382cb 2590 u32 err;
cd28ab6a 2591
82637e80 2592 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2593 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2594 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2595 0xfffffffful);
3be92a70 2596 if (net_ratelimit())
555382cb 2597 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2598
7782c8c4 2599 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2600 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2601 }
2602
2603 if (status & Y2_HWE_L1_MASK)
2604 sky2_hw_error(hw, 0, status);
2605 status >>= 8;
2606 if (status & Y2_HWE_L1_MASK)
2607 sky2_hw_error(hw, 1, status);
2608}
2609
2610static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2611{
2612 struct net_device *dev = hw->dev[port];
2613 struct sky2_port *sky2 = netdev_priv(dev);
2614 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2615
2616 if (netif_msg_intr(sky2))
2617 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2618 dev->name, status);
2619
a3caeada
SH		 2620 if (status & GM_IS_RX_CO_OV)
2621 gma_read16(hw, port, GM_RX_IRQ_SRC);
2622
2623 if (status & GM_IS_TX_CO_OV)
2624 gma_read16(hw, port, GM_TX_IRQ_SRC);
2625
cd28ab6a 2626 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2627 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2628 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2629 }
2630
2631 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2632 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2633 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2634 }
cd28ab6a
SH		 2635}
2636
40b01727 2637/* This should never happen it is a bug. */
c119731d 2638static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2639{
2640 struct net_device *dev = hw->dev[port];
c119731d 2641 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2642
c119731d
SH		 2643 dev_err(&hw->pdev->dev, PFX
2644 "%s: descriptor error q=%#x get=%u put=%u\n",
2645 dev->name, (unsigned) q, (unsigned) idx,
2646 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2647
40b01727 2648 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2649}
cd28ab6a 2650
75e80683
SH		 2651static int sky2_rx_hung(struct net_device *dev)
2652{
2653 struct sky2_port *sky2 = netdev_priv(dev);
2654 struct sky2_hw *hw = sky2->hw;
2655 unsigned port = sky2->port;
2656 unsigned rxq = rxqaddr[port];
2657 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2658 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2659 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2660 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2661
2662 /* If idle and MAC or PCI is stuck */
2663 if (sky2->check.last == dev->last_rx &&
2664 ((mac_rp == sky2->check.mac_rp &&
2665 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2666 /* Check if the PCI RX hang */
2667 (fifo_rp == sky2->check.fifo_rp &&
2668 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2669 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2670 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2671 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2672 return 1;
2673 } else {
2674 sky2->check.last = dev->last_rx;
2675 sky2->check.mac_rp = mac_rp;
2676 sky2->check.mac_lev = mac_lev;
2677 sky2->check.fifo_rp = fifo_rp;
2678 sky2->check.fifo_lev = fifo_lev;
2679 return 0;
2680 }
2681}
2682
32c2c300 2683static void sky2_watchdog(unsigned long arg)
d27ed387 2684{
01bd7564 2685 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2686
75e80683 2687 /* Check for lost IRQ once a second */
32c2c300 2688 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2689 napi_schedule(&hw->napi);
75e80683
SH		 2690 } else {
2691 int i, active = 0;
2692
2693 for (i = 0; i < hw->ports; i++) {
bea3348e 2694 struct net_device *dev = hw->dev[i];
75e80683
SH		 2695 if (!netif_running(dev))
2696 continue;
2697 ++active;
2698
2699 /* For chips with Rx FIFO, check if stuck */
39dbd958 2700 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2701 sky2_rx_hung(dev)) {
2702 pr_info(PFX "%s: receiver hang detected\n",
2703 dev->name);
2704 schedule_work(&hw->restart_work);
2705 return;
2706 }
2707 }
2708
2709 if (active == 0)
2710 return;
32c2c300 2711 }
01bd7564 2712
75e80683 2713 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2714}
2715
40b01727
SH		 2716/* Hardware/software error handling */
2717static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2718{
40b01727
SH		 2719 if (net_ratelimit())
2720 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2721
1e5f1283
SH		 2722 if (status & Y2_IS_HW_ERR)
2723 sky2_hw_intr(hw);
d257924e 2724
1e5f1283
SH		 2725 if (status & Y2_IS_IRQ_MAC1)
2726 sky2_mac_intr(hw, 0);
cd28ab6a 2727
1e5f1283
SH		 2728 if (status & Y2_IS_IRQ_MAC2)
2729 sky2_mac_intr(hw, 1);
cd28ab6a 2730
1e5f1283 2731 if (status & Y2_IS_CHK_RX1)
c119731d 2732 sky2_le_error(hw, 0, Q_R1);
d257924e 2733
1e5f1283 2734 if (status & Y2_IS_CHK_RX2)
c119731d 2735 sky2_le_error(hw, 1, Q_R2);
d257924e 2736
1e5f1283 2737 if (status & Y2_IS_CHK_TXA1)
c119731d 2738 sky2_le_error(hw, 0, Q_XA1);
d257924e 2739
1e5f1283 2740 if (status & Y2_IS_CHK_TXA2)
c119731d 2741 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2742}
2743
bea3348e 2744static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2745{
bea3348e 2746 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2747 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2748 int work_done = 0;
26691830 2749 u16 idx;
40b01727
SH		 2750
2751 if (unlikely(status & Y2_IS_ERROR))
2752 sky2_err_intr(hw, status);
2753
2754 if (status & Y2_IS_IRQ_PHY1)
2755 sky2_phy_intr(hw, 0);
2756
2757 if (status & Y2_IS_IRQ_PHY2)
2758 sky2_phy_intr(hw, 1);
cd28ab6a 2759
26691830
SH		 2760 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2761 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2762
2763 if (work_done >= work_limit)
26691830
SH		 2764 goto done;
2765 }
6f535763 2766
26691830
SH		 2767 napi_complete(napi);
2768 sky2_read32(hw, B0_Y2_SP_LISR);
2769done:
6f535763 2770
bea3348e 2771 return work_done;
e07b1aa8
SH		 2772}
2773
7d12e780 2774static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2775{
2776 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2777 u32 status;
2778
2779 /* Reading this mask interrupts as side effect */
2780 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2781 if (status == 0 || status == ~0)
2782 return IRQ_NONE;
793b883e 2783
e07b1aa8 2784 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2785
2786 napi_schedule(&hw->napi);
793b883e 2787
cd28ab6a
SH		 2788 return IRQ_HANDLED;
2789}
2790
2791#ifdef CONFIG_NET_POLL_CONTROLLER
2792static void sky2_netpoll(struct net_device *dev)
2793{
2794 struct sky2_port *sky2 = netdev_priv(dev);
2795
bea3348e 2796 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2797}
2798#endif
2799
2800/* Chip internal frequency for clock calculations */
05745c4a 2801static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2802{
793b883e 2803 switch (hw->chip_id) {
cd28ab6a 2804 case CHIP_ID_YUKON_EC:
5a5b1ea0 2805 case CHIP_ID_YUKON_EC_U:
93745494 2806 case CHIP_ID_YUKON_EX:
ed4d4161 2807 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2808 case CHIP_ID_YUKON_UL_2:
05745c4a
SH		 2809 return 125;
2810
cd28ab6a 2811 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2812 return 100;
2813
2814 case CHIP_ID_YUKON_FE_P:
2815 return 50;
2816
2817 case CHIP_ID_YUKON_XL:
2818 return 156;
2819
2820 default:
2821 BUG();
cd28ab6a
SH		 2822 }
2823}
2824
fb17358f 2825static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2826{
fb17358f 2827 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2828}
2829
fb17358f 2830static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2831{
fb17358f 2832 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2833}
2834
fb17358f 2835
e3173832 2836static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2837{
b89165f2 2838 u8 t8;
cd28ab6a 2839
167f53d0 2840 /* Enable all clocks and check for bad PCI access */
b32f40c4 2841 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2842
cd28ab6a 2843 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2844
cd28ab6a 2845 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2846 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2847
2848 switch(hw->chip_id) {
2849 case CHIP_ID_YUKON_XL:
39dbd958 2850 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2851 break;
2852
2853 case CHIP_ID_YUKON_EC_U:
2854 hw->flags = SKY2_HW_GIGABIT
2855 | SKY2_HW_NEWER_PHY
2856 | SKY2_HW_ADV_POWER_CTL;
2857 break;
2858
2859 case CHIP_ID_YUKON_EX:
2860 hw->flags = SKY2_HW_GIGABIT
2861 | SKY2_HW_NEWER_PHY
2862 | SKY2_HW_NEW_LE
2863 | SKY2_HW_ADV_POWER_CTL;
2864
2865 /* New transmit checksum */
2866 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2867 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2868 break;
2869
2870 case CHIP_ID_YUKON_EC:
2871 /* This rev is really old, and requires untested workarounds */
2872 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2873 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2874 return -EOPNOTSUPP;
2875 }
39dbd958 2876 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2877 break;
2878
2879 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2880 break;
2881
05745c4a
SH		 2882 case CHIP_ID_YUKON_FE_P:
2883 hw->flags = SKY2_HW_NEWER_PHY
2884 | SKY2_HW_NEW_LE
2885 | SKY2_HW_AUTO_TX_SUM
2886 | SKY2_HW_ADV_POWER_CTL;
2887 break;
ed4d4161
SH		 2888
2889 case CHIP_ID_YUKON_SUPR:
2890 hw->flags = SKY2_HW_GIGABIT
2891 | SKY2_HW_NEWER_PHY
2892 | SKY2_HW_NEW_LE
2893 | SKY2_HW_AUTO_TX_SUM
2894 | SKY2_HW_ADV_POWER_CTL;
2895 break;
2896
0ce8b98d
SH		 2897 case CHIP_ID_YUKON_UL_2:
2898 hw->flags = SKY2_HW_GIGABIT
2899 | SKY2_HW_ADV_POWER_CTL;
2900 break;
2901
ea76e635 2902 default:
b02a9258
SH		 2903 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2904 hw->chip_id);
cd28ab6a
SH		 2905 return -EOPNOTSUPP;
2906 }
2907
ea76e635
SH		 2908 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2909 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2910 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2911
e3173832
SH		 2912 hw->ports = 1;
2913 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2914 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2915 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2916 ++hw->ports;
2917 }
2918
2919 return 0;
2920}
2921
2922static void sky2_reset(struct sky2_hw *hw)
2923{
555382cb 2924 struct pci_dev *pdev = hw->pdev;
e3173832 2925 u16 status;
555382cb
SH		 2926 int i, cap;
2927 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2928
cd28ab6a 2929 /* disable ASF */
4f44d8ba
SH		 2930 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2931 status = sky2_read16(hw, HCU_CCSR);
2932 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2933 HCU_CCSR_UC_STATE_MSK);
2934 sky2_write16(hw, HCU_CCSR, status);
2935 } else
2936 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2937 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2938
2939 /* do a SW reset */
2940 sky2_write8(hw, B0_CTST, CS_RST_SET);
2941 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2942
ac93a394
SH		 2943 /* allow writes to PCI config */
2944 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2945
cd28ab6a 2946 /* clear PCI errors, if any */
b32f40c4 2947 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2948 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2949 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2950
2951 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2952
555382cb
SH		 2953 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2954 if (cap) {
7782c8c4
SH		 2955 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2956 0xfffffffful);
555382cb
SH		 2957
2958 /* If error bit is stuck on ignore it */
2959 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2960 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2961 else
555382cb
SH		 2962 hwe_mask |= Y2_IS_PCI_EXP;
2963 }
cd28ab6a 2964
ae306cca 2965 sky2_power_on(hw);
82637e80 2966 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2967
2968 for (i = 0; i < hw->ports; i++) {
2969 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2970 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2971
ed4d4161
SH		 2972 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2973 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2974 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2975 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2976 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2977 }
2978
793b883e
SH		 2979 /* Clear I2C IRQ noise */
2980 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2981
2982 /* turn off hardware timer (unused) */
2983 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2984 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2985
cd28ab6a
SH		 2986 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2987
69634ee7
SH		 2988 /* Turn off descriptor polling */
2989 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2990
2991 /* Turn off receive timestamp */
2992 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2993 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2994
2995 /* enable the Tx Arbiters */
2996 for (i = 0; i < hw->ports; i++)
2997 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2998
2999 /* Initialize ram interface */
3000 for (i = 0; i < hw->ports; i++) {
793b883e 3001 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3002
3003 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3004 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3005 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3006 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3007 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3008 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3009 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3010 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3011 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3012 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3013 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3014 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3015 }
3016
555382cb 3017 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3018
cd28ab6a 3019 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3020 sky2_gmac_reset(hw, i);
cd28ab6a 3021
cd28ab6a
SH		 3022 memset(hw->st_le, 0, STATUS_LE_BYTES);
3023 hw->st_idx = 0;
3024
3025 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3026 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3027
3028 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3029 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3030
3031 /* Set the list last index */
793b883e 3032 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3033
290d4de5
SH		 3034 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3035 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3036
290d4de5
SH		 3037 /* set Status-FIFO ISR watermark */
3038 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3039 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3040 else
3041 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3042
290d4de5 3043 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3044 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3045 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3046
793b883e 3047 /* enable status unit */
cd28ab6a
SH		 3048 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3049
3050 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3051 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3052 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3053}
3054
af18d8b8
SH		 3055/* Take device down (offline).
3056 * Equivalent to doing dev_stop() but this does not
3057 * inform upper layers of the transistion.
3058 */
3059static void sky2_detach(struct net_device *dev)
3060{
3061 if (netif_running(dev)) {
3062 netif_device_detach(dev); /* stop txq */
3063 sky2_down(dev);
3064 }
3065}
3066
3067/* Bring device back after doing sky2_detach */
3068static int sky2_reattach(struct net_device *dev)
3069{
3070 int err = 0;
3071
3072 if (netif_running(dev)) {
3073 err = sky2_up(dev);
3074 if (err) {
3075 printk(KERN_INFO PFX "%s: could not restart %d\n",
3076 dev->name, err);
3077 dev_close(dev);
3078 } else {
3079 netif_device_attach(dev);
3080 sky2_set_multicast(dev);
3081 }
3082 }
3083
3084 return err;
3085}
3086
81906791
SH		 3087static void sky2_restart(struct work_struct *work)
3088{
3089 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
af18d8b8 3090 int i;
81906791 3091
81906791 3092 rtnl_lock();
af18d8b8
SH		 3093 for (i = 0; i < hw->ports; i++)
3094 sky2_detach(hw->dev[i]);
81906791 3095
8cfcbe99
SH		 3096 napi_disable(&hw->napi);
3097 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3098 sky2_reset(hw);
3099 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3100 napi_enable(&hw->napi);
81906791 3101
af18d8b8
SH		 3102 for (i = 0; i < hw->ports; i++)
3103 sky2_reattach(hw->dev[i]);
81906791 3104
81906791
SH		 3105 rtnl_unlock();
3106}
3107
e3173832
SH		 3108static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3109{
3110 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3111}
3112
3113static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3114{
3115 const struct sky2_port *sky2 = netdev_priv(dev);
3116
3117 wol->supported = sky2_wol_supported(sky2->hw);
3118 wol->wolopts = sky2->wol;
3119}
3120
3121static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3122{
3123 struct sky2_port *sky2 = netdev_priv(dev);
3124 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3125
9d731d77
RW		 3126 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3127 || !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3128 return -EOPNOTSUPP;
3129
3130 sky2->wol = wol->wolopts;
3131
05745c4a
SH		 3132 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3133 hw->chip_id == CHIP_ID_YUKON_EX ||
3134 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3135 sky2_write32(hw, B0_CTST, sky2->wol
3136 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3137
9d731d77
RW		 3138 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3139
e3173832
SH		 3140 if (!netif_running(dev))
3141 sky2_wol_init(sky2);
cd28ab6a
SH		 3142 return 0;
3143}
3144
28bd181a 3145static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3146{
b89165f2
SH		 3147 if (sky2_is_copper(hw)) {
3148 u32 modes = SUPPORTED_10baseT_Half
3149 | SUPPORTED_10baseT_Full
3150 | SUPPORTED_100baseT_Half
3151 | SUPPORTED_100baseT_Full
3152 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3153
ea76e635 3154 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3155 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3156 | SUPPORTED_1000baseT_Full;
3157 return modes;
cd28ab6a 3158 } else
b89165f2
SH		 3159 return SUPPORTED_1000baseT_Half
3160 | SUPPORTED_1000baseT_Full
3161 | SUPPORTED_Autoneg
3162 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3163}
3164
793b883e 3165static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3166{
3167 struct sky2_port *sky2 = netdev_priv(dev);
3168 struct sky2_hw *hw = sky2->hw;
3169
3170 ecmd->transceiver = XCVR_INTERNAL;
3171 ecmd->supported = sky2_supported_modes(hw);
3172 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3173 if (sky2_is_copper(hw)) {
cd28ab6a 3174 ecmd->port = PORT_TP;
b89165f2
SH		 3175 ecmd->speed = sky2->speed;
3176 } else {
3177 ecmd->speed = SPEED_1000;
cd28ab6a 3178 ecmd->port = PORT_FIBRE;
b89165f2 3179 }
cd28ab6a
SH		 3180
3181 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3182 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3183 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3184 ecmd->duplex = sky2->duplex;
3185 return 0;
3186}
3187
3188static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3189{
3190 struct sky2_port *sky2 = netdev_priv(dev);
3191 const struct sky2_hw *hw = sky2->hw;
3192 u32 supported = sky2_supported_modes(hw);
3193
3194 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3195 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3196 ecmd->advertising = supported;
3197 sky2->duplex = -1;
3198 sky2->speed = -1;
3199 } else {
3200 u32 setting;
3201
793b883e 3202 switch (ecmd->speed) {
cd28ab6a
SH		 3203 case SPEED_1000:
3204 if (ecmd->duplex == DUPLEX_FULL)
3205 setting = SUPPORTED_1000baseT_Full;
3206 else if (ecmd->duplex == DUPLEX_HALF)
3207 setting = SUPPORTED_1000baseT_Half;
3208 else
3209 return -EINVAL;
3210 break;
3211 case SPEED_100:
3212 if (ecmd->duplex == DUPLEX_FULL)
3213 setting = SUPPORTED_100baseT_Full;
3214 else if (ecmd->duplex == DUPLEX_HALF)
3215 setting = SUPPORTED_100baseT_Half;
3216 else
3217 return -EINVAL;
3218 break;
3219
3220 case SPEED_10:
3221 if (ecmd->duplex == DUPLEX_FULL)
3222 setting = SUPPORTED_10baseT_Full;
3223 else if (ecmd->duplex == DUPLEX_HALF)
3224 setting = SUPPORTED_10baseT_Half;
3225 else
3226 return -EINVAL;
3227 break;
3228 default:
3229 return -EINVAL;
3230 }
3231
3232 if ((setting & supported) == 0)
3233 return -EINVAL;
3234
3235 sky2->speed = ecmd->speed;
3236 sky2->duplex = ecmd->duplex;
0ea065e5 3237 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3238 }
3239
cd28ab6a
SH		 3240 sky2->advertising = ecmd->advertising;
3241
d1b139c0 3242 if (netif_running(dev)) {
1b537565 3243 sky2_phy_reinit(sky2);
d1b139c0
SH		 3244 sky2_set_multicast(dev);
3245 }
cd28ab6a
SH		 3246
3247 return 0;
3248}
3249
3250static void sky2_get_drvinfo(struct net_device *dev,
3251 struct ethtool_drvinfo *info)
3252{
3253 struct sky2_port *sky2 = netdev_priv(dev);
3254
3255 strcpy(info->driver, DRV_NAME);
3256 strcpy(info->version, DRV_VERSION);
3257 strcpy(info->fw_version, "N/A");
3258 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3259}
3260
3261static const struct sky2_stat {
793b883e
SH		 3262 char name[ETH_GSTRING_LEN];
3263 u16 offset;
cd28ab6a
SH		 3264} sky2_stats[] = {
3265 { "tx_bytes", GM_TXO_OK_HI },
3266 { "rx_bytes", GM_RXO_OK_HI },
3267 { "tx_broadcast", GM_TXF_BC_OK },
3268 { "rx_broadcast", GM_RXF_BC_OK },
3269 { "tx_multicast", GM_TXF_MC_OK },
3270 { "rx_multicast", GM_RXF_MC_OK },
3271 { "tx_unicast", GM_TXF_UC_OK },
3272 { "rx_unicast", GM_RXF_UC_OK },
3273 { "tx_mac_pause", GM_TXF_MPAUSE },
3274 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3275 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3276 { "late_collision",GM_TXF_LAT_COL },
3277 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3278 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3279 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3280
d2604540 3281 { "rx_short", GM_RXF_SHT },
cd28ab6a 3282 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3283 { "rx_64_byte_packets", GM_RXF_64B },
3284 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3285 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3286 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3287 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3288 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3289 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3290 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3291 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3292 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3293 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3294
3295 { "tx_64_byte_packets", GM_TXF_64B },
3296 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3297 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3298 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3299 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3300 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3301 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3302 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3303};
3304
cd28ab6a
SH		 3305static u32 sky2_get_rx_csum(struct net_device *dev)
3306{
3307 struct sky2_port *sky2 = netdev_priv(dev);
3308
0ea065e5 3309 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3310}
3311
3312static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3313{
3314 struct sky2_port *sky2 = netdev_priv(dev);
3315
0ea065e5
SH		 3316 if (data)
3317 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3318 else
3319 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3320
cd28ab6a
SH		 3321 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3322 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3323
3324 return 0;
3325}
3326
3327static u32 sky2_get_msglevel(struct net_device *netdev)
3328{
3329 struct sky2_port *sky2 = netdev_priv(netdev);
3330 return sky2->msg_enable;
3331}
3332
9a7ae0a9
SH		 3333static int sky2_nway_reset(struct net_device *dev)
3334{
3335 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3336
0ea065e5 3337 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3338 return -EINVAL;
3339
1b537565 3340 sky2_phy_reinit(sky2);
d1b139c0 3341 sky2_set_multicast(dev);
9a7ae0a9
SH		 3342
3343 return 0;
3344}
3345
793b883e 3346static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3347{
3348 struct sky2_hw *hw = sky2->hw;
3349 unsigned port = sky2->port;
3350 int i;
3351
3352 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3353 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3354 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3355 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3356
793b883e 3357 for (i = 2; i < count; i++)
cd28ab6a
SH		 3358 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3359}
3360
cd28ab6a
SH		 3361static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3362{
3363 struct sky2_port *sky2 = netdev_priv(netdev);
3364 sky2->msg_enable = value;
3365}
3366
b9f2c044 3367static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3368{
b9f2c044
JG		 3369 switch (sset) {
3370 case ETH_SS_STATS:
3371 return ARRAY_SIZE(sky2_stats);
3372 default:
3373 return -EOPNOTSUPP;
3374 }
cd28ab6a
SH		 3375}
3376
3377static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3378 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3379{
3380 struct sky2_port *sky2 = netdev_priv(dev);
3381
793b883e 3382 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3383}
3384
793b883e 3385static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3386{
3387 int i;
3388
3389 switch (stringset) {
3390 case ETH_SS_STATS:
3391 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3392 memcpy(data + i * ETH_GSTRING_LEN,
3393 sky2_stats[i].name, ETH_GSTRING_LEN);
3394 break;
3395 }
3396}
3397
cd28ab6a
SH		 3398static int sky2_set_mac_address(struct net_device *dev, void *p)
3399{
3400 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3401 struct sky2_hw *hw = sky2->hw;
3402 unsigned port = sky2->port;
3403 const struct sockaddr *addr = p;
cd28ab6a
SH		 3404
3405 if (!is_valid_ether_addr(addr->sa_data))
3406 return -EADDRNOTAVAIL;
3407
cd28ab6a 3408 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3409 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3410 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3411 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3412 dev->dev_addr, ETH_ALEN);
1b537565 3413
a8ab1ec0
SH		 3414 /* virtual address for data */
3415 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3416
3417 /* physical address: used for pause frames */
3418 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3419
3420 return 0;
cd28ab6a
SH		 3421}
3422
a052b52f
SH		 3423static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3424{
3425 u32 bit;
3426
3427 bit = ether_crc(ETH_ALEN, addr) & 63;
3428 filter[bit >> 3] |= 1 << (bit & 7);
3429}
3430
cd28ab6a
SH		 3431static void sky2_set_multicast(struct net_device *dev)
3432{
3433 struct sky2_port *sky2 = netdev_priv(dev);
3434 struct sky2_hw *hw = sky2->hw;
3435 unsigned port = sky2->port;
3436 struct dev_mc_list *list = dev->mc_list;
3437 u16 reg;
3438 u8 filter[8];
a052b52f
SH		 3439 int rx_pause;
3440 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3441
a052b52f 3442 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3443 memset(filter, 0, sizeof(filter));
3444
3445 reg = gma_read16(hw, port, GM_RX_CTRL);
3446 reg |= GM_RXCR_UCF_ENA;
3447
d571b694 3448 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3449 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3450 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3451 memset(filter, 0xff, sizeof(filter));
a052b52f 3452 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3453 reg &= ~GM_RXCR_MCF_ENA;
3454 else {
3455 int i;
3456 reg |= GM_RXCR_MCF_ENA;
3457
a052b52f
SH		 3458 if (rx_pause)
3459 sky2_add_filter(filter, pause_mc_addr);
3460
3461 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3462 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3463 }
3464
cd28ab6a 3465 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3466 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3467 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3468 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3469 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3470 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3471 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3472 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3473
3474 gma_write16(hw, port, GM_RX_CTRL, reg);
3475}
3476
3477/* Can have one global because blinking is controlled by
3478 * ethtool and that is always under RTNL mutex
3479 */
a84d0a3d 3480static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3481{
a84d0a3d
SH		 3482 struct sky2_hw *hw = sky2->hw;
3483 unsigned port = sky2->port;
793b883e 3484
a84d0a3d
SH		 3485 spin_lock_bh(&sky2->phy_lock);
3486 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3487 hw->chip_id == CHIP_ID_YUKON_EX ||
3488 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3489 u16 pg;
793b883e
SH		 3490 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3491 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3492
a84d0a3d
SH		 3493 switch (mode) {
3494 case MO_LED_OFF:
3495 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3496 PHY_M_LEDC_LOS_CTRL(8) |
3497 PHY_M_LEDC_INIT_CTRL(8) |
3498 PHY_M_LEDC_STA1_CTRL(8) |
3499 PHY_M_LEDC_STA0_CTRL(8));
3500 break;
3501 case MO_LED_ON:
3502 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3503 PHY_M_LEDC_LOS_CTRL(9) |
3504 PHY_M_LEDC_INIT_CTRL(9) |
3505 PHY_M_LEDC_STA1_CTRL(9) |
3506 PHY_M_LEDC_STA0_CTRL(9));
3507 break;
3508 case MO_LED_BLINK:
3509 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3510 PHY_M_LEDC_LOS_CTRL(0xa) |
3511 PHY_M_LEDC_INIT_CTRL(0xa) |
3512 PHY_M_LEDC_STA1_CTRL(0xa) |
3513 PHY_M_LEDC_STA0_CTRL(0xa));
3514 break;
3515 case MO_LED_NORM:
3516 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3517 PHY_M_LEDC_LOS_CTRL(1) |
3518 PHY_M_LEDC_INIT_CTRL(8) |
3519 PHY_M_LEDC_STA1_CTRL(7) |
3520 PHY_M_LEDC_STA0_CTRL(7));
3521 }
793b883e 3522
a84d0a3d
SH		 3523 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3524 } else
7d2e3cb7 3525 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3526 PHY_M_LED_MO_DUP(mode) |
3527 PHY_M_LED_MO_10(mode) |
3528 PHY_M_LED_MO_100(mode) |
3529 PHY_M_LED_MO_1000(mode) |
3530 PHY_M_LED_MO_RX(mode) |
3531 PHY_M_LED_MO_TX(mode));
3532
3533 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3534}
3535
3536/* blink LED's for finding board */
3537static int sky2_phys_id(struct net_device *dev, u32 data)
3538{
3539 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3540 unsigned int i;
cd28ab6a 3541
a84d0a3d
SH		 3542 if (data == 0)
3543 data = UINT_MAX;
cd28ab6a 3544
a84d0a3d
SH		 3545 for (i = 0; i < data; i++) {
3546 sky2_led(sky2, MO_LED_ON);
3547 if (msleep_interruptible(500))
3548 break;
3549 sky2_led(sky2, MO_LED_OFF);
3550 if (msleep_interruptible(500))
3551 break;
793b883e 3552 }
a84d0a3d 3553 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3554
3555 return 0;
3556}
3557
3558static void sky2_get_pauseparam(struct net_device *dev,
3559 struct ethtool_pauseparam *ecmd)
3560{
3561 struct sky2_port *sky2 = netdev_priv(dev);
3562
16ad91e1
SH		 3563 switch (sky2->flow_mode) {
3564 case FC_NONE:
3565 ecmd->tx_pause = ecmd->rx_pause = 0;
3566 break;
3567 case FC_TX:
3568 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3569 break;
3570 case FC_RX:
3571 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3572 break;
3573 case FC_BOTH:
3574 ecmd->tx_pause = ecmd->rx_pause = 1;
3575 }
3576
0ea065e5
SH		 3577 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3578 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3579}
3580
3581static int sky2_set_pauseparam(struct net_device *dev,
3582 struct ethtool_pauseparam *ecmd)
3583{
3584 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3585
0ea065e5
SH		 3586 if (ecmd->autoneg == AUTONEG_ENABLE)
3587 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3588 else
3589 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3590
16ad91e1 3591 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3592
16ad91e1
SH		 3593 if (netif_running(dev))
3594 sky2_phy_reinit(sky2);
cd28ab6a 3595
2eaba1a2 3596 return 0;
cd28ab6a
SH		 3597}
3598
fb17358f
SH		 3599static int sky2_get_coalesce(struct net_device *dev,
3600 struct ethtool_coalesce *ecmd)
3601{
3602 struct sky2_port *sky2 = netdev_priv(dev);
3603 struct sky2_hw *hw = sky2->hw;
3604
3605 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3606 ecmd->tx_coalesce_usecs = 0;
3607 else {
3608 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3609 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3610 }
3611 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3612
3613 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3614 ecmd->rx_coalesce_usecs = 0;
3615 else {
3616 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3617 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3618 }
3619 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3620
3621 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3622 ecmd->rx_coalesce_usecs_irq = 0;
3623 else {
3624 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3625 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3626 }
3627
3628 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3629
3630 return 0;
3631}
3632
3633/* Note: this affect both ports */
3634static int sky2_set_coalesce(struct net_device *dev,
3635 struct ethtool_coalesce *ecmd)
3636{
3637 struct sky2_port *sky2 = netdev_priv(dev);
3638 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3639 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3640
77b3d6a2
SH		 3641 if (ecmd->tx_coalesce_usecs > tmax ||
3642 ecmd->rx_coalesce_usecs > tmax ||
3643 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3644 return -EINVAL;
3645
ee5f68fe 3646 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3647 return -EINVAL;
ff81fbbe 3648 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3649 return -EINVAL;
ff81fbbe 3650 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3651 return -EINVAL;
3652
3653 if (ecmd->tx_coalesce_usecs == 0)
3654 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3655 else {
3656 sky2_write32(hw, STAT_TX_TIMER_INI,
3657 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3658 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3659 }
3660 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3661
3662 if (ecmd->rx_coalesce_usecs == 0)
3663 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3664 else {
3665 sky2_write32(hw, STAT_LEV_TIMER_INI,
3666 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3667 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3668 }
3669 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3670
3671 if (ecmd->rx_coalesce_usecs_irq == 0)
3672 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3673 else {
d28d4870 3674 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3675 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3676 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3677 }
3678 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3679 return 0;
3680}
3681
793b883e
SH		 3682static void sky2_get_ringparam(struct net_device *dev,
3683 struct ethtool_ringparam *ering)
3684{
3685 struct sky2_port *sky2 = netdev_priv(dev);
3686
3687 ering->rx_max_pending = RX_MAX_PENDING;
3688 ering->rx_mini_max_pending = 0;
3689 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3690 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3691
3692 ering->rx_pending = sky2->rx_pending;
3693 ering->rx_mini_pending = 0;
3694 ering->rx_jumbo_pending = 0;
3695 ering->tx_pending = sky2->tx_pending;
3696}
3697
3698static int sky2_set_ringparam(struct net_device *dev,
3699 struct ethtool_ringparam *ering)
3700{
3701 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3702
3703 if (ering->rx_pending > RX_MAX_PENDING ||
3704 ering->rx_pending < 8 ||
ee5f68fe
SH		 3705 ering->tx_pending < TX_MIN_PENDING ||
3706 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3707 return -EINVAL;
3708
af18d8b8 3709 sky2_detach(dev);
793b883e
SH		 3710
3711 sky2->rx_pending = ering->rx_pending;
3712 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3713 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3714
af18d8b8 3715 return sky2_reattach(dev);
793b883e
SH		 3716}
3717
793b883e
SH		 3718static int sky2_get_regs_len(struct net_device *dev)
3719{
6e4cbb34 3720 return 0x4000;
793b883e
SH		 3721}
3722
3723/*
3724 * Returns copy of control register region
3ead5db7 3725 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3726 */
3727static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3728 void *p)
3729{
3730 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3731 const void __iomem *io = sky2->hw->regs;
295b54c4 3732 unsigned int b;
793b883e
SH		 3733
3734 regs->version = 1;
793b883e 3735
295b54c4
SH		 3736 for (b = 0; b < 128; b++) {
3737 /* This complicated switch statement is to make sure and
3738 * only access regions that are unreserved.
3739 * Some blocks are only valid on dual port cards.
3740 * and block 3 has some special diagnostic registers that
3741 * are poison.
3742 */
3743 switch (b) {
3744 case 3:
3745 /* skip diagnostic ram region */
3746 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3747 break;
3ead5db7 3748
295b54c4
SH		 3749 /* dual port cards only */
3750 case 5: /* Tx Arbiter 2 */
3751 case 9: /* RX2 */
3752 case 14 ... 15: /* TX2 */
3753 case 17: case 19: /* Ram Buffer 2 */
3754 case 22 ... 23: /* Tx Ram Buffer 2 */
3755 case 25: /* Rx MAC Fifo 1 */
3756 case 27: /* Tx MAC Fifo 2 */
3757 case 31: /* GPHY 2 */
3758 case 40 ... 47: /* Pattern Ram 2 */
3759 case 52: case 54: /* TCP Segmentation 2 */
3760 case 112 ... 116: /* GMAC 2 */
3761 if (sky2->hw->ports == 1)
3762 goto reserved;
3763 /* fall through */
3764 case 0: /* Control */
3765 case 2: /* Mac address */
3766 case 4: /* Tx Arbiter 1 */
3767 case 7: /* PCI express reg */
3768 case 8: /* RX1 */
3769 case 12 ... 13: /* TX1 */
3770 case 16: case 18:/* Rx Ram Buffer 1 */
3771 case 20 ... 21: /* Tx Ram Buffer 1 */
3772 case 24: /* Rx MAC Fifo 1 */
3773 case 26: /* Tx MAC Fifo 1 */
3774 case 28 ... 29: /* Descriptor and status unit */
3775 case 30: /* GPHY 1*/
3776 case 32 ... 39: /* Pattern Ram 1 */
3777 case 48: case 50: /* TCP Segmentation 1 */
3778 case 56 ... 60: /* PCI space */
3779 case 80 ... 84: /* GMAC 1 */
3780 memcpy_fromio(p, io, 128);
3781 break;
3782 default:
3783reserved:
3784 memset(p, 0, 128);
3785 }
3ead5db7 3786
295b54c4
SH		 3787 p += 128;
3788 io += 128;
3789 }
793b883e 3790}
cd28ab6a 3791
b628ed98
SH		 3792/* In order to do Jumbo packets on these chips, need to turn off the
3793 * transmit store/forward. Therefore checksum offload won't work.
3794 */
3795static int no_tx_offload(struct net_device *dev)
3796{
3797 const struct sky2_port *sky2 = netdev_priv(dev);
3798 const struct sky2_hw *hw = sky2->hw;
3799
69161611 3800 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3801}
3802
3803static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3804{
3805 if (data && no_tx_offload(dev))
3806 return -EINVAL;
3807
3808 return ethtool_op_set_tx_csum(dev, data);
3809}
3810
3811
3812static int sky2_set_tso(struct net_device *dev, u32 data)
3813{
3814 if (data && no_tx_offload(dev))
3815 return -EINVAL;
3816
3817 return ethtool_op_set_tso(dev, data);
3818}
3819
f4331a6d
SH		 3820static int sky2_get_eeprom_len(struct net_device *dev)
3821{
3822 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3823 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3824 u16 reg2;
3825
b32f40c4 3826 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3827 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3828}
3829
1413235c 3830static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3831{
1413235c 3832 unsigned long start = jiffies;
f4331a6d 3833
1413235c
SH		 3834 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3835 /* Can take up to 10.6 ms for write */
3836 if (time_after(jiffies, start + HZ/4)) {
3837 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3838 return -ETIMEDOUT;
3839 }
3840 mdelay(1);
3841 }
167f53d0 3842
1413235c
SH		 3843 return 0;
3844}
167f53d0 3845
1413235c
SH		 3846static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3847 u16 offset, size_t length)
3848{
3849 int rc = 0;
3850
3851 while (length > 0) {
3852 u32 val;
3853
3854 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3855 rc = sky2_vpd_wait(hw, cap, 0);
3856 if (rc)
3857 break;
3858
3859 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3860
3861 memcpy(data, &val, min(sizeof(val), length));
3862 offset += sizeof(u32);
3863 data += sizeof(u32);
3864 length -= sizeof(u32);
3865 }
3866
3867 return rc;
f4331a6d
SH		 3868}
3869
1413235c
SH		 3870static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3871 u16 offset, unsigned int length)
f4331a6d 3872{
1413235c
SH		 3873 unsigned int i;
3874 int rc = 0;
3875
3876 for (i = 0; i < length; i += sizeof(u32)) {
3877 u32 val = *(u32 *)(data + i);
3878
3879 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3880 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3881
3882 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3883 if (rc)
3884 break;
3885 }
3886 return rc;
f4331a6d
SH		 3887}
3888
3889static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3890 u8 *data)
3891{
3892 struct sky2_port *sky2 = netdev_priv(dev);
3893 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3894
3895 if (!cap)
3896 return -EINVAL;
3897
3898 eeprom->magic = SKY2_EEPROM_MAGIC;
3899
1413235c 3900 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3901}
3902
3903static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3904 u8 *data)
3905{
3906 struct sky2_port *sky2 = netdev_priv(dev);
3907 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3908
3909 if (!cap)
3910 return -EINVAL;
3911
3912 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3913 return -EINVAL;
3914
1413235c
SH		 3915 /* Partial writes not supported */
3916 if ((eeprom->offset & 3) || (eeprom->len & 3))
3917 return -EINVAL;
f4331a6d 3918
1413235c 3919 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3920}
3921
3922
7282d491 3923static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3924 .get_settings = sky2_get_settings,
3925 .set_settings = sky2_set_settings,
3926 .get_drvinfo = sky2_get_drvinfo,
3927 .get_wol = sky2_get_wol,
3928 .set_wol = sky2_set_wol,
3929 .get_msglevel = sky2_get_msglevel,
3930 .set_msglevel = sky2_set_msglevel,
3931 .nway_reset = sky2_nway_reset,
3932 .get_regs_len = sky2_get_regs_len,
3933 .get_regs = sky2_get_regs,
3934 .get_link = ethtool_op_get_link,
3935 .get_eeprom_len = sky2_get_eeprom_len,
3936 .get_eeprom = sky2_get_eeprom,
3937 .set_eeprom = sky2_set_eeprom,
f4331a6d 3938 .set_sg = ethtool_op_set_sg,
f4331a6d 3939 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3940 .set_tso = sky2_set_tso,
3941 .get_rx_csum = sky2_get_rx_csum,
3942 .set_rx_csum = sky2_set_rx_csum,
3943 .get_strings = sky2_get_strings,
3944 .get_coalesce = sky2_get_coalesce,
3945 .set_coalesce = sky2_set_coalesce,
3946 .get_ringparam = sky2_get_ringparam,
3947 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3948 .get_pauseparam = sky2_get_pauseparam,
3949 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3950 .phys_id = sky2_phys_id,
b9f2c044 3951 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3952 .get_ethtool_stats = sky2_get_ethtool_stats,
3953};
3954
3cf26753
SH		 3955#ifdef CONFIG_SKY2_DEBUG
3956
3957static struct dentry *sky2_debug;
3958
e4c2abe2
SH		 3959
3960/*
3961 * Read and parse the first part of Vital Product Data
3962 */
3963#define VPD_SIZE 128
3964#define VPD_MAGIC 0x82
3965
3966static const struct vpd_tag {
3967 char tag[2];
3968 char *label;
3969} vpd_tags[] = {
3970 { "PN", "Part Number" },
3971 { "EC", "Engineering Level" },
3972 { "MN", "Manufacturer" },
3973 { "SN", "Serial Number" },
3974 { "YA", "Asset Tag" },
3975 { "VL", "First Error Log Message" },
3976 { "VF", "Second Error Log Message" },
3977 { "VB", "Boot Agent ROM Configuration" },
3978 { "VE", "EFI UNDI Configuration" },
3979};
3980
3981static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3982{
3983 size_t vpd_size;
3984 loff_t offs;
3985 u8 len;
3986 unsigned char *buf;
3987 u16 reg2;
3988
3989 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3990 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3991
3992 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
3993 buf = kmalloc(vpd_size, GFP_KERNEL);
3994 if (!buf) {
3995 seq_puts(seq, "no memory!\n");
3996 return;
3997 }
3998
3999 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4000 seq_puts(seq, "VPD read failed\n");
4001 goto out;
4002 }
4003
4004 if (buf[0] != VPD_MAGIC) {
4005 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4006 goto out;
4007 }
4008 len = buf[1];
4009 if (len == 0 || len > vpd_size - 4) {
4010 seq_printf(seq, "Invalid id length: %d\n", len);
4011 goto out;
4012 }
4013
4014 seq_printf(seq, "%.*s\n", len, buf + 3);
4015 offs = len + 3;
4016
4017 while (offs < vpd_size - 4) {
4018 int i;
4019
4020 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4021 break;
4022 len = buf[offs + 2];
4023 if (offs + len + 3 >= vpd_size)
4024 break;
4025
4026 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4027 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4028 seq_printf(seq, " %s: %.*s\n",
4029 vpd_tags[i].label, len, buf + offs + 3);
4030 break;
4031 }
4032 }
4033 offs += len + 3;
4034 }
4035out:
4036 kfree(buf);
4037}
4038
3cf26753
SH		 4039static int sky2_debug_show(struct seq_file *seq, void *v)
4040{
4041 struct net_device *dev = seq->private;
4042 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4043 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4044 unsigned port = sky2->port;
4045 unsigned idx, last;
4046 int sop;
4047
e4c2abe2 4048 sky2_show_vpd(seq, hw);
3cf26753 4049
e4c2abe2 4050 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4051 sky2_read32(hw, B0_ISRC),
4052 sky2_read32(hw, B0_IMSK),
4053 sky2_read32(hw, B0_Y2_SP_ICR));
4054
e4c2abe2
SH		 4055 if (!netif_running(dev)) {
4056 seq_printf(seq, "network not running\n");
4057 return 0;
4058 }
4059
bea3348e 4060 napi_disable(&hw->napi);
3cf26753
SH		 4061 last = sky2_read16(hw, STAT_PUT_IDX);
4062
4063 if (hw->st_idx == last)
4064 seq_puts(seq, "Status ring (empty)\n");
4065 else {
4066 seq_puts(seq, "Status ring\n");
4067 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4068 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4069 const struct sky2_status_le *le = hw->st_le + idx;
4070 seq_printf(seq, "[%d] %#x %d %#x\n",
4071 idx, le->opcode, le->length, le->status);
4072 }
4073 seq_puts(seq, "\n");
4074 }
4075
4076 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4077 sky2->tx_cons, sky2->tx_prod,
4078 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4079 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4080
4081 /* Dump contents of tx ring */
4082 sop = 1;
ee5f68fe
SH		 4083 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4084 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4085 const struct sky2_tx_le *le = sky2->tx_le + idx;
4086 u32 a = le32_to_cpu(le->addr);
4087
4088 if (sop)
4089 seq_printf(seq, "%u:", idx);
4090 sop = 0;
4091
4092 switch(le->opcode & ~HW_OWNER) {
4093 case OP_ADDR64:
4094 seq_printf(seq, " %#x:", a);
4095 break;
4096 case OP_LRGLEN:
4097 seq_printf(seq, " mtu=%d", a);
4098 break;
4099 case OP_VLAN:
4100 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4101 break;
4102 case OP_TCPLISW:
4103 seq_printf(seq, " csum=%#x", a);
4104 break;
4105 case OP_LARGESEND:
4106 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4107 break;
4108 case OP_PACKET:
4109 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4110 break;
4111 case OP_BUFFER:
4112 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4113 break;
4114 default:
4115 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4116 a, le16_to_cpu(le->length));
4117 }
4118
4119 if (le->ctrl & EOP) {
4120 seq_putc(seq, '\n');
4121 sop = 1;
4122 }
4123 }
4124
4125 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4126 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4127 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4128 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4129
d1d08d12 4130 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4131 napi_enable(&hw->napi);
3cf26753
SH		 4132 return 0;
4133}
4134
4135static int sky2_debug_open(struct inode *inode, struct file *file)
4136{
4137 return single_open(file, sky2_debug_show, inode->i_private);
4138}
4139
4140static const struct file_operations sky2_debug_fops = {
4141 .owner = THIS_MODULE,
4142 .open = sky2_debug_open,
4143 .read = seq_read,
4144 .llseek = seq_lseek,
4145 .release = single_release,
4146};
4147
4148/*
4149 * Use network device events to create/remove/rename
4150 * debugfs file entries
4151 */
4152static int sky2_device_event(struct notifier_block *unused,
4153 unsigned long event, void *ptr)
4154{
4155 struct net_device *dev = ptr;
5b296bc9 4156 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4157
1436b301 4158 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4159 return NOTIFY_DONE;
3cf26753 4160
5b296bc9
SH		 4161 switch(event) {
4162 case NETDEV_CHANGENAME:
4163 if (sky2->debugfs) {
4164 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4165 sky2_debug, dev->name);
4166 }
4167 break;
3cf26753 4168
5b296bc9
SH		 4169 case NETDEV_GOING_DOWN:
4170 if (sky2->debugfs) {
4171 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4172 dev->name);
4173 debugfs_remove(sky2->debugfs);
4174 sky2->debugfs = NULL;
3cf26753 4175 }
5b296bc9
SH		 4176 break;
4177
4178 case NETDEV_UP:
4179 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4180 sky2_debug, dev,
4181 &sky2_debug_fops);
4182 if (IS_ERR(sky2->debugfs))
4183 sky2->debugfs = NULL;
3cf26753
SH		 4184 }
4185
4186 return NOTIFY_DONE;
4187}
4188
4189static struct notifier_block sky2_notifier = {
4190 .notifier_call = sky2_device_event,
4191};
4192
4193
4194static __init void sky2_debug_init(void)
4195{
4196 struct dentry *ent;
4197
4198 ent = debugfs_create_dir("sky2", NULL);
4199 if (!ent || IS_ERR(ent))
4200 return;
4201
4202 sky2_debug = ent;
4203 register_netdevice_notifier(&sky2_notifier);
4204}
4205
4206static __exit void sky2_debug_cleanup(void)
4207{
4208 if (sky2_debug) {
4209 unregister_netdevice_notifier(&sky2_notifier);
4210 debugfs_remove(sky2_debug);
4211 sky2_debug = NULL;
4212 }
4213}
4214
4215#else
4216#define sky2_debug_init()
4217#define sky2_debug_cleanup()
4218#endif
4219
1436b301
SH		 4220/* Two copies of network device operations to handle special case of
4221 not allowing netpoll on second port */
4222static const struct net_device_ops sky2_netdev_ops[2] = {
4223 {
4224 .ndo_open = sky2_up,
4225 .ndo_stop = sky2_down,
00829823 4226 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4227 .ndo_do_ioctl = sky2_ioctl,
4228 .ndo_validate_addr = eth_validate_addr,
4229 .ndo_set_mac_address = sky2_set_mac_address,
4230 .ndo_set_multicast_list = sky2_set_multicast,
4231 .ndo_change_mtu = sky2_change_mtu,
4232 .ndo_tx_timeout = sky2_tx_timeout,
4233#ifdef SKY2_VLAN_TAG_USED
4234 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4235#endif
4236#ifdef CONFIG_NET_POLL_CONTROLLER
4237 .ndo_poll_controller = sky2_netpoll,
4238#endif
4239 },
4240 {
4241 .ndo_open = sky2_up,
4242 .ndo_stop = sky2_down,
00829823 4243 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4244 .ndo_do_ioctl = sky2_ioctl,
4245 .ndo_validate_addr = eth_validate_addr,
4246 .ndo_set_mac_address = sky2_set_mac_address,
4247 .ndo_set_multicast_list = sky2_set_multicast,
4248 .ndo_change_mtu = sky2_change_mtu,
4249 .ndo_tx_timeout = sky2_tx_timeout,
4250#ifdef SKY2_VLAN_TAG_USED
4251 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4252#endif
4253 },
4254};
3cf26753 4255
cd28ab6a
SH		 4256/* Initialize network device */
4257static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4258 unsigned port,
be63a21c 4259 int highmem, int wol)
cd28ab6a
SH		 4260{
4261 struct sky2_port *sky2;
4262 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4263
4264 if (!dev) {
898eb71c 4265 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4266 return NULL;
4267 }
4268
cd28ab6a 4269 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4270 dev->irq = hw->pdev->irq;
cd28ab6a 4271 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4272 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4273 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4274
4275 sky2 = netdev_priv(dev);
4276 sky2->netdev = dev;
4277 sky2->hw = hw;
4278 sky2->msg_enable = netif_msg_init(debug, default_msg);
4279
cd28ab6a 4280 /* Auto speed and flow control */
0ea065e5
SH		 4281 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4282 if (hw->chip_id != CHIP_ID_YUKON_XL)
4283 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4284
16ad91e1
SH		 4285 sky2->flow_mode = FC_BOTH;
4286
cd28ab6a
SH		 4287 sky2->duplex = -1;
4288 sky2->speed = -1;
4289 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4290 sky2->wol = wol;
75d070c5 4291
e07b1aa8 4292 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4293
793b883e 4294 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4295 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4296 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4297
4298 hw->dev[port] = dev;
4299
4300 sky2->port = port;
4301
4a50a876 4302 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4303 if (highmem)
4304 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4305
d1f13708 4306#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4307 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4308 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4309 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4310 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4311 }
d1f13708
SH		 4312#endif
4313
cd28ab6a 4314 /* read the mac address */
793b883e 4315 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4316 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4317
cd28ab6a
SH		 4318 return dev;
4319}
4320
28bd181a 4321static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4322{
4323 const struct sky2_port *sky2 = netdev_priv(dev);
4324
4325 if (netif_msg_probe(sky2))
e174961c
JB		 4326 printk(KERN_INFO PFX "%s: addr %pM\n",
4327 dev->name, dev->dev_addr);
cd28ab6a
SH		 4328}
4329
fb2690a9 4330/* Handle software interrupt used during MSI test */
7d12e780 4331static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4332{
4333 struct sky2_hw *hw = dev_id;
4334 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4335
4336 if (status == 0)
4337 return IRQ_NONE;
4338
4339 if (status & Y2_IS_IRQ_SW) {
ea76e635 4340 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4341 wake_up(&hw->msi_wait);
4342 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4343 }
4344 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4345
4346 return IRQ_HANDLED;
4347}
4348
4349/* Test interrupt path by forcing a a software IRQ */
4350static int __devinit sky2_test_msi(struct sky2_hw *hw)
4351{
4352 struct pci_dev *pdev = hw->pdev;
4353 int err;
4354
bb507fe1
SH		 4355 init_waitqueue_head (&hw->msi_wait);
4356
fb2690a9
SH		 4357 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4358
b0a20ded 4359 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4360 if (err) {
b02a9258 4361 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4362 return err;
4363 }
4364
fb2690a9 4365 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4366 sky2_read8(hw, B0_CTST);
fb2690a9 4367
ea76e635 4368 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4369
ea76e635 4370 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4371 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4372 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4373 "switching to INTx mode.\n");
fb2690a9
SH		 4374
4375 err = -EOPNOTSUPP;
4376 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4377 }
4378
4379 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4380 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4381
4382 free_irq(pdev->irq, hw);
4383
4384 return err;
4385}
4386
c7127a34
SH		 4387/* This driver supports yukon2 chipset only */
4388static const char *sky2_name(u8 chipid, char *buf, int sz)
4389{
4390 const char *name[] = {
4391 "XL", /* 0xb3 */
4392 "EC Ultra", /* 0xb4 */
4393 "Extreme", /* 0xb5 */
4394 "EC", /* 0xb6 */
4395 "FE", /* 0xb7 */
4396 "FE+", /* 0xb8 */
4397 "Supreme", /* 0xb9 */
0ce8b98d 4398 "UL 2", /* 0xba */
c7127a34
SH		 4399 };
4400
0ce8b98d 4401 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH		 4402 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4403 else
4404 snprintf(buf, sz, "(chip %#x)", chipid);
4405 return buf;
4406}
4407
cd28ab6a
SH		 4408static int __devinit sky2_probe(struct pci_dev *pdev,
4409 const struct pci_device_id *ent)
4410{
7f60c64b 4411 struct net_device *dev;
cd28ab6a 4412 struct sky2_hw *hw;
be63a21c 4413 int err, using_dac = 0, wol_default;
3834507d 4414 u32 reg;
c7127a34 4415 char buf1[16];
cd28ab6a 4416
793b883e
SH		 4417 err = pci_enable_device(pdev);
4418 if (err) {
b02a9258 4419 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4420 goto err_out;
4421 }
4422
6cc90a5a
SH		 4423 /* Get configuration information
4424 * Note: only regular PCI config access once to test for HW issues
4425 * other PCI access through shared memory for speed and to
4426 * avoid MMCONFIG problems.
4427 */
4428 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4429 if (err) {
4430 dev_err(&pdev->dev, "PCI read config failed\n");
4431 goto err_out;
4432 }
4433
4434 if (~reg == 0) {
4435 dev_err(&pdev->dev, "PCI configuration read error\n");
4436 goto err_out;
4437 }
4438
793b883e
SH		 4439 err = pci_request_regions(pdev, DRV_NAME);
4440 if (err) {
b02a9258 4441 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4442 goto err_out_disable;
cd28ab6a
SH		 4443 }
4444
4445 pci_set_master(pdev);
4446
d1f3d4dd 4447 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4448 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4449 using_dac = 1;
6a35528a 4450 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4451 if (err < 0) {
b02a9258
SH		 4452 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4453 "for consistent allocations\n");
d1f3d4dd
SH		 4454 goto err_out_free_regions;
4455 }
d1f3d4dd 4456 } else {
284901a9 4457 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4458 if (err) {
b02a9258 4459 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4460 goto err_out_free_regions;
4461 }
4462 }
d1f3d4dd 4463
3834507d
SH		 4464
4465#ifdef __BIG_ENDIAN
4466 /* The sk98lin vendor driver uses hardware byte swapping but
4467 * this driver uses software swapping.
4468 */
4469 reg &= ~PCI_REV_DESC;
4470 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4471 if (err) {
4472 dev_err(&pdev->dev, "PCI write config failed\n");
4473 goto err_out_free_regions;
4474 }
4475#endif
4476
9d731d77 4477 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4478
cd28ab6a 4479 err = -ENOMEM;
6aad85d6 4480 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4481 if (!hw) {
b02a9258 4482 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4483 goto err_out_free_regions;
4484 }
4485
cd28ab6a 4486 hw->pdev = pdev;
cd28ab6a
SH		 4487
4488 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4489 if (!hw->regs) {
b02a9258 4490 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4491 goto err_out_free_hw;
4492 }
4493
08c06d8a 4494 /* ring for status responses */
167f53d0 4495 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4496 if (!hw->st_le)
4497 goto err_out_iounmap;
4498
e3173832 4499 err = sky2_init(hw);
cd28ab6a 4500 if (err)
793b883e 4501 goto err_out_iounmap;
cd28ab6a 4502
c844d483
SH		 4503 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4504 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4505
e3173832
SH		 4506 sky2_reset(hw);
4507
be63a21c 4508 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4509 if (!dev) {
4510 err = -ENOMEM;
cd28ab6a 4511 goto err_out_free_pci;
7f60c64b 4512 }
cd28ab6a 4513
9fa1b1f3
SH		 4514 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4515 err = sky2_test_msi(hw);
4516 if (err == -EOPNOTSUPP)
4517 pci_disable_msi(pdev);
4518 else if (err)
4519 goto err_out_free_netdev;
4520 }
4521
793b883e
SH		 4522 err = register_netdev(dev);
4523 if (err) {
b02a9258 4524 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4525 goto err_out_free_netdev;
4526 }
4527
6de16237
SH		 4528 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4529
ea76e635
SH		 4530 err = request_irq(pdev->irq, sky2_intr,
4531 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4532 dev->name, hw);
9fa1b1f3 4533 if (err) {
b02a9258 4534 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4535 goto err_out_unregister;
4536 }
4537 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4538 napi_enable(&hw->napi);
9fa1b1f3 4539
cd28ab6a
SH		 4540 sky2_show_addr(dev);
4541
7f60c64b 4542 if (hw->ports > 1) {
4543 struct net_device *dev1;
4544
be63a21c 4545 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4546 if (!dev1)
4547 dev_warn(&pdev->dev, "allocation for second device failed\n");
4548 else if ((err = register_netdev(dev1))) {
4549 dev_warn(&pdev->dev,
4550 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4551 hw->dev[1] = NULL;
4552 free_netdev(dev1);
b02a9258
SH		 4553 } else
4554 sky2_show_addr(dev1);
cd28ab6a
SH		 4555 }
4556
32c2c300 4557 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4558 INIT_WORK(&hw->restart_work, sky2_restart);
4559
793b883e
SH		 4560 pci_set_drvdata(pdev, hw);
4561
cd28ab6a
SH		 4562 return 0;
4563
793b883e 4564err_out_unregister:
ea76e635 4565 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4566 pci_disable_msi(pdev);
793b883e 4567 unregister_netdev(dev);
cd28ab6a
SH		 4568err_out_free_netdev:
4569 free_netdev(dev);
cd28ab6a 4570err_out_free_pci:
793b883e 4571 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4572 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4573err_out_iounmap:
4574 iounmap(hw->regs);
4575err_out_free_hw:
4576 kfree(hw);
4577err_out_free_regions:
4578 pci_release_regions(pdev);
44a1d2e5 4579err_out_disable:
cd28ab6a 4580 pci_disable_device(pdev);
cd28ab6a 4581err_out:
549a68c3 4582 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4583 return err;
4584}
4585
4586static void __devexit sky2_remove(struct pci_dev *pdev)
4587{
793b883e 4588 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4589 int i;
cd28ab6a 4590
793b883e 4591 if (!hw)
cd28ab6a
SH		 4592 return;
4593
32c2c300 4594 del_timer_sync(&hw->watchdog_timer);
6de16237 4595 cancel_work_sync(&hw->restart_work);
d27ed387 4596
b877fe28 4597 for (i = hw->ports-1; i >= 0; --i)
6de16237 4598 unregister_netdev(hw->dev[i]);
81906791 4599
d27ed387 4600 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4601
ae306cca
SH		 4602 sky2_power_aux(hw);
4603
cd28ab6a 4604 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4605 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4606 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4607
4608 free_irq(pdev->irq, hw);
ea76e635 4609 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4610 pci_disable_msi(pdev);
793b883e 4611 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4612 pci_release_regions(pdev);
4613 pci_disable_device(pdev);
793b883e 4614
b877fe28 4615 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4616 free_netdev(hw->dev[i]);
4617
cd28ab6a
SH		 4618 iounmap(hw->regs);
4619 kfree(hw);
5afa0a9c 4620
cd28ab6a
SH		 4621 pci_set_drvdata(pdev, NULL);
4622}
4623
4624#ifdef CONFIG_PM
4625static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4626{
793b883e 4627 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4628 int i, wol = 0;
cd28ab6a 4629
549a68c3
SH		 4630 if (!hw)
4631 return 0;
4632
063a0b38
SH		 4633 del_timer_sync(&hw->watchdog_timer);
4634 cancel_work_sync(&hw->restart_work);
4635
19720737 4636 rtnl_lock();
f05267e7 4637 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4638 struct net_device *dev = hw->dev[i];
e3173832 4639 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4640
af18d8b8 4641 sky2_detach(dev);
e3173832
SH		 4642
4643 if (sky2->wol)
4644 sky2_wol_init(sky2);
4645
4646 wol |= sky2->wol;
cd28ab6a
SH		 4647 }
4648
8ab8fca2 4649 sky2_write32(hw, B0_IMSK, 0);
6de16237 4650 napi_disable(&hw->napi);
ae306cca 4651 sky2_power_aux(hw);
19720737 4652 rtnl_unlock();
e3173832 4653
d374c1c1 4654 pci_save_state(pdev);
e3173832 4655 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4656 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4657
2ccc99b7 4658 return 0;
cd28ab6a
SH		 4659}
4660
4661static int sky2_resume(struct pci_dev *pdev)
4662{
793b883e 4663 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4664 int i, err;
cd28ab6a 4665
549a68c3
SH		 4666 if (!hw)
4667 return 0;
4668
f71eb1a2
SH		 4669 err = pci_set_power_state(pdev, PCI_D0);
4670 if (err)
4671 goto out;
ae306cca
SH		 4672
4673 err = pci_restore_state(pdev);
4674 if (err)
4675 goto out;
4676
cd28ab6a 4677 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4678
4679 /* Re-enable all clocks */
05745c4a
SH		 4680 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4681 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4682 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4683 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4684
e3173832 4685 sky2_reset(hw);
8ab8fca2 4686 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4687 napi_enable(&hw->napi);
8ab8fca2 4688
af18d8b8 4689 rtnl_lock();
f05267e7 4690 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4691 err = sky2_reattach(hw->dev[i]);
4692 if (err)
4693 goto out;
cd28ab6a 4694 }
af18d8b8 4695 rtnl_unlock();
eb35cf60 4696
ae306cca 4697 return 0;
08c06d8a 4698out:
af18d8b8
SH		 4699 rtnl_unlock();
4700
b02a9258 4701 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4702 pci_disable_device(pdev);
08c06d8a 4703 return err;
cd28ab6a
SH		 4704}
4705#endif
4706
e3173832
SH		 4707static void sky2_shutdown(struct pci_dev *pdev)
4708{
4709 struct sky2_hw *hw = pci_get_drvdata(pdev);
4710 int i, wol = 0;
4711
549a68c3
SH		 4712 if (!hw)
4713 return;
4714
19720737 4715 rtnl_lock();
5c0d6b34 4716 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4717
4718 for (i = 0; i < hw->ports; i++) {
4719 struct net_device *dev = hw->dev[i];
4720 struct sky2_port *sky2 = netdev_priv(dev);
4721
4722 if (sky2->wol) {
4723 wol = 1;
4724 sky2_wol_init(sky2);
4725 }
4726 }
4727
4728 if (wol)
4729 sky2_power_aux(hw);
19720737 4730 rtnl_unlock();
e3173832
SH		 4731
4732 pci_enable_wake(pdev, PCI_D3hot, wol);
4733 pci_enable_wake(pdev, PCI_D3cold, wol);
4734
4735 pci_disable_device(pdev);
f71eb1a2 4736 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4737}
4738
cd28ab6a 4739static struct pci_driver sky2_driver = {
793b883e
SH		 4740 .name = DRV_NAME,
4741 .id_table = sky2_id_table,
4742 .probe = sky2_probe,
4743 .remove = __devexit_p(sky2_remove),
cd28ab6a 4744#ifdef CONFIG_PM
793b883e
SH		 4745 .suspend = sky2_suspend,
4746 .resume = sky2_resume,
cd28ab6a 4747#endif
e3173832 4748 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4749};
4750
4751static int __init sky2_init_module(void)
4752{
c844d483
SH		 4753 pr_info(PFX "driver version " DRV_VERSION "\n");
4754
3cf26753 4755 sky2_debug_init();
50241c4c 4756 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4757}
4758
4759static void __exit sky2_cleanup_module(void)
4760{
4761 pci_unregister_driver(&sky2_driver);
3cf26753 4762 sky2_debug_cleanup();
cd28ab6a
SH		 4763}
4764
4765module_init(sky2_init_module);
4766module_exit(sky2_cleanup_module);
4767
4768MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4769MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4770MODULE_LICENSE("GPL");
5f4f9dc1 4771MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree