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ibm_emac: Remove the ibm_emac driver
[net-next-2.6.git] / drivers / net / sky2.c
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cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
bcc52894 54#define DRV_VERSION "1.21"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
f4331a6d
SH		 79#define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
14d0263f 93static int copybreak __read_mostly = 128;
bdb5c58e
SH		 94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
cd28ab6a 101static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
cd28ab6a
SH		 139 { 0 }
140};
793b883e 141
cd28ab6a
SH		 142MODULE_DEVICE_TABLE(pci, sky2_id_table);
143
144/* Avoid conditionals by using array */
145static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 147static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 148
92f965e8
SH		 149/* This driver supports yukon2 chipset only */
150static const char *yukon2_name[] = {
151 "XL", /* 0xb3 */
152 "EC Ultra", /* 0xb4 */
93745494 153 "Extreme", /* 0xb5 */
92f965e8
SH		 154 "EC", /* 0xb6 */
155 "FE", /* 0xb7 */
05745c4a 156 "FE+", /* 0xb8 */
c63eddb2 157 "Supreme", /* 0xb9 */
793b883e
SH		 158};
159
d1b139c0
SH		 160static void sky2_set_multicast(struct net_device *dev);
161
af043aa5 162/* Access to PHY via serial interconnect */
ef743d33 163static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 164{
165 int i;
166
167 gma_write16(hw, port, GM_SMI_DATA, val);
168 gma_write16(hw, port, GM_SMI_CTRL,
169 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
170
171 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 172 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
173 if (ctrl == 0xffff)
174 goto io_error;
175
176 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 177 return 0;
af043aa5
SH		 178
179 udelay(10);
cd28ab6a 180 }
ef743d33 181
af043aa5 182 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 183 return -ETIMEDOUT;
af043aa5
SH		 184
185io_error:
186 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
187 return -EIO;
cd28ab6a
SH		 188}
189
ef743d33 190static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 191{
192 int i;
193
793b883e 194 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 195 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
196
197 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 198 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
199 if (ctrl == 0xffff)
200 goto io_error;
201
202 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 203 *val = gma_read16(hw, port, GM_SMI_DATA);
204 return 0;
205 }
206
af043aa5 207 udelay(10);
cd28ab6a
SH		 208 }
209
af043aa5 210 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 211 return -ETIMEDOUT;
af043aa5
SH		 212io_error:
213 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
214 return -EIO;
ef743d33
SH		 215}
216
af043aa5 217static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 218{
219 u16 v;
af043aa5 220 __gm_phy_read(hw, port, reg, &v);
ef743d33 221 return v;
cd28ab6a
SH		 222}
223
5afa0a9c 224
ae306cca
SH		 225static void sky2_power_on(struct sky2_hw *hw)
226{
227 /* switch power to VCC (WA for VAUX problem) */
228 sky2_write8(hw, B0_POWER_CTRL,
229 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 230
ae306cca
SH		 231 /* disable Core Clock Division, */
232 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 233
ae306cca
SH		 234 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
235 /* enable bits are inverted */
236 sky2_write8(hw, B2_Y2_CLK_GATE,
237 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
238 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
239 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
240 else
241 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 242
ea76e635 243 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 244 u32 reg;
5afa0a9c 245
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 247
b32f40c4 248 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 249 /* set all bits to 0 except bits 15..12 and 8 */
250 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 251 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 252
b32f40c4 253 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 254 /* set all bits to 0 except bits 28 & 27 */
255 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 256 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 257
b32f40c4 258 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 259
260 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
261 reg = sky2_read32(hw, B2_GP_IO);
262 reg |= GLB_GPIO_STAT_RACE_DIS;
263 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 264
265 sky2_read32(hw, B2_GP_IO);
5afa0a9c 266 }
ae306cca 267}
5afa0a9c 268
ae306cca
SH		 269static void sky2_power_aux(struct sky2_hw *hw)
270{
271 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
272 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
273 else
274 /* enable bits are inverted */
275 sky2_write8(hw, B2_Y2_CLK_GATE,
276 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
277 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
278 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
279
280 /* switch power to VAUX */
281 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
282 sky2_write8(hw, B0_POWER_CTRL,
283 (PC_VAUX_ENA | PC_VCC_ENA |
284 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 285}
286
a068c0ad
SH		 287static void sky2_power_state(struct sky2_hw *hw, pci_power_t state)
288{
289 u16 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
290 int pex = pci_find_capability(hw->pdev, PCI_CAP_ID_EXP);
291 u32 reg;
292
293 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
294
295 switch (state) {
296 case PCI_D0:
297 break;
298
299 case PCI_D1:
300 power_control |= 1;
301 break;
302
303 case PCI_D2:
304 power_control |= 2;
305 break;
306
307 case PCI_D3hot:
308 case PCI_D3cold:
309 power_control |= 3;
310 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
311 /* additional power saving measurements */
312 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
313
314 /* set gating core clock for LTSSM in L1 state */
315 reg |= P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
316 /* auto clock gated scheme controlled by CLKREQ */
317 P_ASPM_A1_MODE_SELECT |
318 /* enable Gate Root Core Clock */
319 P_CLK_GATE_ROOT_COR_ENA;
320
321 if (pex && (hw->flags & SKY2_HW_CLK_POWER)) {
322 /* enable Clock Power Management (CLKREQ) */
323 u16 ctrl = sky2_pci_read16(hw, pex + PCI_EXP_DEVCTL);
324
325 ctrl |= PCI_EXP_DEVCTL_AUX_PME;
326 sky2_pci_write16(hw, pex + PCI_EXP_DEVCTL, ctrl);
327 } else
328 /* force CLKREQ Enable in Our4 (A1b only) */
329 reg |= P_ASPM_FORCE_CLKREQ_ENA;
330
331 /* set Mask Register for Release/Gate Clock */
332 sky2_pci_write32(hw, PCI_DEV_REG5,
333 P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
334 P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
335 P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
336 } else
337 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_CLK_HALT);
338
339 /* put CPU into reset state */
340 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_RESET);
341 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev == CHIP_REV_YU_SU_A0)
342 /* put CPU into halt state */
343 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_HALTED);
344
345 if (pex && !(hw->flags & SKY2_HW_RAM_BUFFER)) {
346 reg = sky2_pci_read32(hw, PCI_DEV_REG1);
347 /* force to PCIe L1 */
348 reg |= PCI_FORCE_PEX_L1;
349 sky2_pci_write32(hw, PCI_DEV_REG1, reg);
350 }
351 break;
352
353 default:
354 dev_warn(&hw->pdev->dev, PFX "Invalid power state (%d) ",
355 state);
356 return;
357 }
358
359 power_control |= PCI_PM_CTRL_PME_ENABLE;
360 /* Finally, set the new power state. */
361 sky2_pci_write32(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
362
363 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
364 sky2_pci_read32(hw, B0_CTST);
365}
366
d3bcfbeb 367static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 368{
369 u16 reg;
370
371 /* disable all GMAC IRQ's */
372 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 373
cd28ab6a
SH		 374 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
375 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
376 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
377 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
378
379 reg = gma_read16(hw, port, GM_RX_CTRL);
380 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
381 gma_write16(hw, port, GM_RX_CTRL, reg);
382}
383
16ad91e1
SH		 384/* flow control to advertise bits */
385static const u16 copper_fc_adv[] = {
386 [FC_NONE] = 0,
387 [FC_TX] = PHY_M_AN_ASP,
388 [FC_RX] = PHY_M_AN_PC,
389 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
390};
391
392/* flow control to advertise bits when using 1000BaseX */
393static const u16 fiber_fc_adv[] = {
df3fe1f3 394 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 395 [FC_TX] = PHY_M_P_ASYM_MD_X,
396 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 397 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 398};
399
400/* flow control to GMA disable bits */
401static const u16 gm_fc_disable[] = {
402 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
403 [FC_TX] = GM_GPCR_FC_RX_DIS,
404 [FC_RX] = GM_GPCR_FC_TX_DIS,
405 [FC_BOTH] = 0,
406};
407
408
cd28ab6a
SH		 409static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
410{
411 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 412 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 413
ea76e635
SH		 414 if (sky2->autoneg == AUTONEG_ENABLE &&
415 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 416 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
417
418 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 419 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 420 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
421
53419c68 422 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 423 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 424 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 425 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
426 else
53419c68
SH		 427 /* set master & slave downshift counter to 1x */
428 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 429
430 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
431 }
432
433 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 434 if (sky2_is_copper(hw)) {
05745c4a 435 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 436 /* enable automatic crossover */
437 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 438
439 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
440 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
441 u16 spec;
442
443 /* Enable Class A driver for FE+ A0 */
444 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
445 spec |= PHY_M_FESC_SEL_CL_A;
446 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
447 }
cd28ab6a
SH		 448 } else {
449 /* disable energy detect */
450 ctrl &= ~PHY_M_PC_EN_DET_MSK;
451
452 /* enable automatic crossover */
453 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
454
53419c68 455 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 456 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 457 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 458 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 459 ctrl &= ~PHY_M_PC_DSC_MSK;
460 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
461 }
462 }
cd28ab6a
SH		 463 } else {
464 /* workaround for deviation #4.88 (CRC errors) */
465 /* disable Automatic Crossover */
466
467 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 468 }
cd28ab6a 469
b89165f2
SH		 470 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
471
472 /* special setup for PHY 88E1112 Fiber */
ea76e635 473 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 474 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 475
b89165f2
SH		 476 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
477 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
478 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
479 ctrl &= ~PHY_M_MAC_MD_MSK;
480 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
481 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
482
483 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 484 /* select page 1 to access Fiber registers */
485 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 486
487 /* for SFP-module set SIGDET polarity to low */
488 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
489 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 490 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 491 }
b89165f2
SH		 492
493 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 494 }
495
7800fddc 496 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 497 ct1000 = 0;
498 adv = PHY_AN_CSMA;
2eaba1a2 499 reg = 0;
cd28ab6a
SH		 500
501 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 502 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 503 if (sky2->advertising & ADVERTISED_1000baseT_Full)
504 ct1000 |= PHY_M_1000C_AFD;
505 if (sky2->advertising & ADVERTISED_1000baseT_Half)
506 ct1000 |= PHY_M_1000C_AHD;
507 if (sky2->advertising & ADVERTISED_100baseT_Full)
508 adv |= PHY_M_AN_100_FD;
509 if (sky2->advertising & ADVERTISED_100baseT_Half)
510 adv |= PHY_M_AN_100_HD;
511 if (sky2->advertising & ADVERTISED_10baseT_Full)
512 adv |= PHY_M_AN_10_FD;
513 if (sky2->advertising & ADVERTISED_10baseT_Half)
514 adv |= PHY_M_AN_10_HD;
709c6e7b 515
16ad91e1 516 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 517 } else { /* special defines for FIBER (88E1040S only) */
518 if (sky2->advertising & ADVERTISED_1000baseT_Full)
519 adv |= PHY_M_AN_1000X_AFD;
520 if (sky2->advertising & ADVERTISED_1000baseT_Half)
521 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 522
16ad91e1 523 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 524 }
cd28ab6a
SH		 525
526 /* Restart Auto-negotiation */
527 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
528 } else {
529 /* forced speed/duplex settings */
530 ct1000 = PHY_M_1000C_MSE;
531
2eaba1a2
SH		 532 /* Disable auto update for duplex flow control and speed */
533 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 534
535 switch (sky2->speed) {
536 case SPEED_1000:
537 ctrl |= PHY_CT_SP1000;
2eaba1a2 538 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 539 break;
540 case SPEED_100:
541 ctrl |= PHY_CT_SP100;
2eaba1a2 542 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 543 break;
544 }
545
2eaba1a2
SH		 546 if (sky2->duplex == DUPLEX_FULL) {
547 reg |= GM_GPCR_DUP_FULL;
548 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 549 } else if (sky2->speed < SPEED_1000)
550 sky2->flow_mode = FC_NONE;
2eaba1a2 551
2eaba1a2 552
16ad91e1 553 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 554
555 /* Forward pause packets to GMAC? */
16ad91e1 556 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 557 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
558 else
559 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 560 }
561
2eaba1a2
SH		 562 gma_write16(hw, port, GM_GP_CTRL, reg);
563
05745c4a 564 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 565 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
566
567 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
568 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
569
570 /* Setup Phy LED's */
571 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
572 ledover = 0;
573
574 switch (hw->chip_id) {
575 case CHIP_ID_YUKON_FE:
576 /* on 88E3082 these bits are at 11..9 (shifted left) */
577 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
578
579 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
580
581 /* delete ACT LED control bits */
582 ctrl &= ~PHY_M_FELP_LED1_MSK;
583 /* change ACT LED control to blink mode */
584 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
585 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
586 break;
587
05745c4a
SH		 588 case CHIP_ID_YUKON_FE_P:
589 /* Enable Link Partner Next Page */
590 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
591 ctrl |= PHY_M_PC_ENA_LIP_NP;
592
593 /* disable Energy Detect and enable scrambler */
594 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
595 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
596
597 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
598 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
599 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
600 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
601
602 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
603 break;
604
cd28ab6a 605 case CHIP_ID_YUKON_XL:
793b883e 606 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 607
608 /* select page 3 to access LED control register */
609 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
610
611 /* set LED Function Control register */
ed6d32c7
SH		 612 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
613 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
614 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
615 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
616 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 617
618 /* set Polarity Control register */
619 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 620 (PHY_M_POLC_LS1_P_MIX(4) |
621 PHY_M_POLC_IS0_P_MIX(4) |
622 PHY_M_POLC_LOS_CTRL(2) |
623 PHY_M_POLC_INIT_CTRL(2) |
624 PHY_M_POLC_STA1_CTRL(2) |
625 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 626
627 /* restore page register */
793b883e 628 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 629 break;
93745494 630
ed6d32c7 631 case CHIP_ID_YUKON_EC_U:
93745494 632 case CHIP_ID_YUKON_EX:
ed4d4161 633 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 634 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
635
636 /* select page 3 to access LED control register */
637 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
638
639 /* set LED Function Control register */
640 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
641 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
642 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
643 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
644 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
645
646 /* set Blink Rate in LED Timer Control Register */
647 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
648 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
649 /* restore page register */
650 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
651 break;
cd28ab6a
SH		 652
653 default:
654 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
655 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 656
cd28ab6a 657 /* turn off the Rx LED (LED_RX) */
a84d0a3d 658 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 659 }
660
9467a8fc
SH		 661 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
662 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 663 /* apply fixes in PHY AFE */
ed6d32c7
SH		 664 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
665
977bdf06 666 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 667 gm_phy_write(hw, port, 0x18, 0xaa99);
668 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 669
977bdf06 670 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 671 gm_phy_write(hw, port, 0x18, 0xa204);
672 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 673
674 /* set page register to 0 */
9467a8fc 675 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 676 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
677 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
678 /* apply workaround for integrated resistors calibration */
679 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
680 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 681 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 682 /* no effect on Yukon-XL */
977bdf06 683 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 684
977bdf06
SH		 685 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
686 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 687 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 688 }
cd28ab6a 689
977bdf06
SH		 690 if (ledover)
691 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
692
693 }
2eaba1a2 694
d571b694 695 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 696 if (sky2->autoneg == AUTONEG_ENABLE)
697 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
698 else
699 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
700}
701
b96936da
SH		 702static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
703static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
704
705static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 706{
707 u32 reg1;
d3bcfbeb 708
82637e80 709 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 710 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 711 reg1 &= ~phy_power[port];
d3bcfbeb 712
b96936da 713 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 714 reg1 |= coma_mode[port];
715
b32f40c4 716 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 717 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
718 sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 719}
167f53d0 720
b96936da
SH		 721static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
722{
723 u32 reg1;
db99b988
SH		 724 u16 ctrl;
725
726 /* release GPHY Control reset */
727 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
728
729 /* release GMAC reset */
730 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
731
732 if (hw->flags & SKY2_HW_NEWER_PHY) {
733 /* select page 2 to access MAC control register */
734 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
735
736 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
737 /* allow GMII Power Down */
738 ctrl &= ~PHY_M_MAC_GMIF_PUP;
739 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
740
741 /* set page register back to 0 */
742 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
743 }
744
745 /* setup General Purpose Control Register */
746 gma_write16(hw, port, GM_GP_CTRL,
747 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
748
749 if (hw->chip_id != CHIP_ID_YUKON_EC) {
750 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
751 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
752
753 /* enable Power Down */
754 ctrl |= PHY_M_PC_POW_D_ENA;
755 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
756 }
757
758 /* set IEEE compatible Power Down Mode (dev. #4.99) */
759 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
760 }
b96936da
SH		 761
762 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
763 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 764 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 765 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
766 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 767}
768
1b537565
SH		 769/* Force a renegotiation */
770static void sky2_phy_reinit(struct sky2_port *sky2)
771{
e07b1aa8 772 spin_lock_bh(&sky2->phy_lock);
1b537565 773 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 774 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 775}
776
e3173832
SH		 777/* Put device in state to listen for Wake On Lan */
778static void sky2_wol_init(struct sky2_port *sky2)
779{
780 struct sky2_hw *hw = sky2->hw;
781 unsigned port = sky2->port;
782 enum flow_control save_mode;
783 u16 ctrl;
784 u32 reg1;
785
786 /* Bring hardware out of reset */
787 sky2_write16(hw, B0_CTST, CS_RST_CLR);
788 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
789
790 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
791 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
792
793 /* Force to 10/100
794 * sky2_reset will re-enable on resume
795 */
796 save_mode = sky2->flow_mode;
797 ctrl = sky2->advertising;
798
799 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
800 sky2->flow_mode = FC_NONE;
b96936da
SH		 801
802 spin_lock_bh(&sky2->phy_lock);
803 sky2_phy_power_up(hw, port);
804 sky2_phy_init(hw, port);
805 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 806
807 sky2->flow_mode = save_mode;
808 sky2->advertising = ctrl;
809
810 /* Set GMAC to no flow control and auto update for speed/duplex */
811 gma_write16(hw, port, GM_GP_CTRL,
812 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
813 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
814
815 /* Set WOL address */
816 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
817 sky2->netdev->dev_addr, ETH_ALEN);
818
819 /* Turn on appropriate WOL control bits */
820 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
821 ctrl = 0;
822 if (sky2->wol & WAKE_PHY)
823 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
824 else
825 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
826
827 if (sky2->wol & WAKE_MAGIC)
828 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
829 else
830 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
831
832 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
833 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
834
835 /* Turn on legacy PCI-Express PME mode */
b32f40c4 836 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 837 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 838 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 839
840 /* block receiver */
841 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
842
843}
844
69161611
SH		 845static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
846{
05745c4a
SH		 847 struct net_device *dev = hw->dev[port];
848
ed4d4161
SH		 849 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
850 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
851 hw->chip_id == CHIP_ID_YUKON_FE_P ||
852 hw->chip_id == CHIP_ID_YUKON_SUPR) {
853 /* Yukon-Extreme B0 and further Extreme devices */
854 /* enable Store & Forward mode for TX */
05745c4a 855
ed4d4161
SH		 856 if (dev->mtu <= ETH_DATA_LEN)
857 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
858 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 859
ed4d4161
SH		 860 else
861 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
862 TX_JUMBO_ENA| TX_STFW_ENA);
863 } else {
864 if (dev->mtu <= ETH_DATA_LEN)
865 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
866 else {
867 /* set Tx GMAC FIFO Almost Empty Threshold */
868 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
869 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 870
ed4d4161
SH		 871 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
872
873 /* Can't do offload because of lack of store/forward */
874 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
875 }
69161611
SH		 876 }
877}
878
cd28ab6a
SH		 879static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
880{
881 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
882 u16 reg;
25cccecc 883 u32 rx_reg;
cd28ab6a
SH		 884 int i;
885 const u8 *addr = hw->dev[port]->dev_addr;
886
f350339c
SH		 887 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
888 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 889
890 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
891
793b883e 892 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 893 /* WA DEV_472 -- looks like crossed wires on port 2 */
894 /* clear GMAC 1 Control reset */
895 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
896 do {
897 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
898 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
899 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
900 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
901 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
902 }
903
793b883e 904 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 905
2eaba1a2
SH		 906 /* Enable Transmit FIFO Underrun */
907 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
908
e07b1aa8 909 spin_lock_bh(&sky2->phy_lock);
b96936da 910 sky2_phy_power_up(hw, port);
cd28ab6a 911 sky2_phy_init(hw, port);
e07b1aa8 912 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 913
914 /* MIB clear */
915 reg = gma_read16(hw, port, GM_PHY_ADDR);
916 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
917
43f2f104
SH		 918 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
919 gma_read16(hw, port, i);
cd28ab6a
SH		 920 gma_write16(hw, port, GM_PHY_ADDR, reg);
921
922 /* transmit control */
923 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
924
925 /* receive control reg: unicast + multicast + no FCS */
926 gma_write16(hw, port, GM_RX_CTRL,
793b883e 927 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 928
929 /* transmit flow control */
930 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
931
932 /* transmit parameter */
933 gma_write16(hw, port, GM_TX_PARAM,
934 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
935 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
936 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
937 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
938
939 /* serial mode register */
940 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 941 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 942
6b1a3aef 943 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 944 reg |= GM_SMOD_JUMBO_ENA;
945
946 gma_write16(hw, port, GM_SERIAL_MODE, reg);
947
cd28ab6a
SH		 948 /* virtual address for data */
949 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
950
793b883e
SH		 951 /* physical address: used for pause frames */
952 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
953
954 /* ignore counter overflows */
cd28ab6a
SH		 955 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
956 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
957 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
958
959 /* Configure Rx MAC FIFO */
960 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 961 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 962 if (hw->chip_id == CHIP_ID_YUKON_EX ||
963 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 964 rx_reg |= GMF_RX_OVER_ON;
69161611 965
25cccecc 966 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 967
798fdd07
SH		 968 if (hw->chip_id == CHIP_ID_YUKON_XL) {
969 /* Hardware errata - clear flush mask */
970 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
971 } else {
972 /* Flush Rx MAC FIFO on any flow control or error */
973 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
974 }
cd28ab6a 975
8df9a876 976 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 977 reg = RX_GMF_FL_THR_DEF + 1;
978 /* Another magic mystery workaround from sk98lin */
979 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
980 hw->chip_rev == CHIP_REV_YU_FE2_A0)
981 reg = 0x178;
982 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 983
984 /* Configure Tx MAC FIFO */
985 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
986 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 987
e0c28116 988 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 989 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 990 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 991 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 992
69161611 993 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 994 }
995
e970d1f8
SH		 996 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
997 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
998 /* disable dynamic watermark */
999 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1000 reg &= ~TX_DYN_WM_ENA;
1001 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1002 }
cd28ab6a
SH		 1003}
1004
67712901
SH		 1005/* Assign Ram Buffer allocation to queue */
1006static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 1007{
67712901
SH		 1008 u32 end;
1009
1010 /* convert from K bytes to qwords used for hw register */
1011 start *= 1024/8;
1012 space *= 1024/8;
1013 end = start + space - 1;
793b883e 1014
cd28ab6a
SH		 1015 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1016 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1017 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1018 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1019 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1020
1021 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 1022 u32 tp = space - space/4;
793b883e 1023
1c28f6ba
SH		 1024 /* On receive queue's set the thresholds
1025 * give receiver priority when > 3/4 full
1026 * send pause when down to 2K
1027 */
1028 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1029 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 1030
1c28f6ba
SH		 1031 tp = space - 2048/8;
1032 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1033 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 1034 } else {
1035 /* Enable store & forward on Tx queue's because
1036 * Tx FIFO is only 1K on Yukon
1037 */
1038 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1039 }
1040
1041 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 1042 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 1043}
1044
cd28ab6a 1045/* Setup Bus Memory Interface */
af4ed7e6 1046static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 1047{
1048 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1049 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1050 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 1051 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 1052}
1053
cd28ab6a
SH		 1054/* Setup prefetch unit registers. This is the interface between
1055 * hardware and driver list elements
1056 */
8cc048e3 1057static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 1058 u64 addr, u32 last)
1059{
cd28ab6a
SH		 1060 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1061 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1062 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
1063 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
1064 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1065 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1066
1067 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1068}
1069
793b883e
SH		 1070static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
1071{
1072 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
1073
cb5d9547 1074 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 1075 le->ctrl = 0;
793b883e
SH		 1076 return le;
1077}
cd28ab6a 1078
88f5f0ca
SH		 1079static void tx_init(struct sky2_port *sky2)
1080{
1081 struct sky2_tx_le *le;
1082
1083 sky2->tx_prod = sky2->tx_cons = 0;
1084 sky2->tx_tcpsum = 0;
1085 sky2->tx_last_mss = 0;
1086
1087 le = get_tx_le(sky2);
1088 le->addr = 0;
1089 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 1090}
1091
291ea614
SH		 1092static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1093 struct sky2_tx_le *le)
1094{
1095 return sky2->tx_ring + (le - sky2->tx_le);
1096}
1097
290d4de5
SH		 1098/* Update chip's next pointer */
1099static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1100{
50432cb5 1101 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1102 wmb();
50432cb5
SH		 1103 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1104
1105 /* Synchronize I/O on since next processor may write to tail */
1106 mmiowb();
cd28ab6a
SH		 1107}
1108
793b883e 1109
cd28ab6a
SH		 1110static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1111{
1112 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1113 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1114 le->ctrl = 0;
cd28ab6a
SH		 1115 return le;
1116}
1117
14d0263f
SH		 1118/* Build description to hardware for one receive segment */
1119static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1120 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1121{
1122 struct sky2_rx_le *le;
1123
86c6887e 1124 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1125 le = sky2_next_rx(sky2);
86c6887e 1126 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1127 le->opcode = OP_ADDR64 | HW_OWNER;
1128 }
793b883e 1129
cd28ab6a 1130 le = sky2_next_rx(sky2);
734d1868
SH		 1131 le->addr = cpu_to_le32((u32) map);
1132 le->length = cpu_to_le16(len);
14d0263f 1133 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1134}
1135
14d0263f
SH		 1136/* Build description to hardware for one possibly fragmented skb */
1137static void sky2_rx_submit(struct sky2_port *sky2,
1138 const struct rx_ring_info *re)
1139{
1140 int i;
1141
1142 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1143
1144 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1145 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1146}
1147
1148
1149static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1150 unsigned size)
1151{
1152 struct sk_buff *skb = re->skb;
1153 int i;
1154
1155 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1156 pci_unmap_len_set(re, data_size, size);
1157
1158 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1159 re->frag_addr[i] = pci_map_page(pdev,
1160 skb_shinfo(skb)->frags[i].page,
1161 skb_shinfo(skb)->frags[i].page_offset,
1162 skb_shinfo(skb)->frags[i].size,
1163 PCI_DMA_FROMDEVICE);
1164}
1165
1166static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1167{
1168 struct sk_buff *skb = re->skb;
1169 int i;
1170
1171 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1172 PCI_DMA_FROMDEVICE);
1173
1174 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1175 pci_unmap_page(pdev, re->frag_addr[i],
1176 skb_shinfo(skb)->frags[i].size,
1177 PCI_DMA_FROMDEVICE);
1178}
793b883e 1179
cd28ab6a
SH		 1180/* Tell chip where to start receive checksum.
1181 * Actually has two checksums, but set both same to avoid possible byte
1182 * order problems.
1183 */
793b883e 1184static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1185{
ea76e635 1186 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1187
ea76e635
SH		 1188 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1189 le->ctrl = 0;
1190 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1191
ea76e635
SH		 1192 sky2_write32(sky2->hw,
1193 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1194 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1195}
1196
6b1a3aef
SH		 1197/*
1198 * The RX Stop command will not work for Yukon-2 if the BMU does not
1199 * reach the end of packet and since we can't make sure that we have
1200 * incoming data, we must reset the BMU while it is not doing a DMA
1201 * transfer. Since it is possible that the RX path is still active,
1202 * the RX RAM buffer will be stopped first, so any possible incoming
1203 * data will not trigger a DMA. After the RAM buffer is stopped, the
1204 * BMU is polled until any DMA in progress is ended and only then it
1205 * will be reset.
1206 */
1207static void sky2_rx_stop(struct sky2_port *sky2)
1208{
1209 struct sky2_hw *hw = sky2->hw;
1210 unsigned rxq = rxqaddr[sky2->port];
1211 int i;
1212
1213 /* disable the RAM Buffer receive queue */
1214 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1215
1216 for (i = 0; i < 0xffff; i++)
1217 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1218 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1219 goto stopped;
1220
1221 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1222 sky2->netdev->name);
1223stopped:
1224 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1225
1226 /* reset the Rx prefetch unit */
1227 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1228 mmiowb();
6b1a3aef 1229}
793b883e 1230
d571b694 1231/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1232static void sky2_rx_clean(struct sky2_port *sky2)
1233{
1234 unsigned i;
1235
1236 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1237 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1238 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1239
1240 if (re->skb) {
14d0263f 1241 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1242 kfree_skb(re->skb);
1243 re->skb = NULL;
1244 }
1245 }
1246}
1247
ef743d33
SH		 1248/* Basic MII support */
1249static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1250{
1251 struct mii_ioctl_data *data = if_mii(ifr);
1252 struct sky2_port *sky2 = netdev_priv(dev);
1253 struct sky2_hw *hw = sky2->hw;
1254 int err = -EOPNOTSUPP;
1255
1256 if (!netif_running(dev))
1257 return -ENODEV; /* Phy still in reset */
1258
d89e1343 1259 switch (cmd) {
ef743d33
SH		 1260 case SIOCGMIIPHY:
1261 data->phy_id = PHY_ADDR_MARV;
1262
1263 /* fallthru */
1264 case SIOCGMIIREG: {
1265 u16 val = 0;
91c86df5 1266
e07b1aa8 1267 spin_lock_bh(&sky2->phy_lock);
ef743d33 1268 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1269 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1270
ef743d33
SH		 1271 data->val_out = val;
1272 break;
1273 }
1274
1275 case SIOCSMIIREG:
1276 if (!capable(CAP_NET_ADMIN))
1277 return -EPERM;
1278
e07b1aa8 1279 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1280 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1281 data->val_in);
e07b1aa8 1282 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1283 break;
1284 }
1285 return err;
1286}
1287
d1f13708 1288#ifdef SKY2_VLAN_TAG_USED
d494eacd 1289static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1290{
d494eacd 1291 if (onoff) {
3d4e66f5
SH		 1292 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1293 RX_VLAN_STRIP_ON);
1294 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1295 TX_VLAN_TAG_ON);
1296 } else {
1297 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1298 RX_VLAN_STRIP_OFF);
1299 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1300 TX_VLAN_TAG_OFF);
1301 }
d494eacd
SH		 1302}
1303
1304static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1305{
1306 struct sky2_port *sky2 = netdev_priv(dev);
1307 struct sky2_hw *hw = sky2->hw;
1308 u16 port = sky2->port;
1309
1310 netif_tx_lock_bh(dev);
1311 napi_disable(&hw->napi);
1312
1313 sky2->vlgrp = grp;
1314 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1315
d1d08d12 1316 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1317 napi_enable(&hw->napi);
2bb8c262 1318 netif_tx_unlock_bh(dev);
d1f13708
SH		 1319}
1320#endif
1321
82788c7a 1322/*
14d0263f
SH		 1323 * Allocate an skb for receiving. If the MTU is large enough
1324 * make the skb non-linear with a fragment list of pages.
82788c7a 1325 */
14d0263f 1326static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1327{
1328 struct sk_buff *skb;
14d0263f 1329 int i;
82788c7a 1330
39dbd958 1331 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1332 unsigned char *start;
1333 /*
1334 * Workaround for a bug in FIFO that cause hang
1335 * if the FIFO if the receive buffer is not 64 byte aligned.
1336 * The buffer returned from netdev_alloc_skb is
1337 * aligned except if slab debugging is enabled.
1338 */
1339 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1340 if (!skb)
1341 goto nomem;
1342 start = PTR_ALIGN(skb->data, 8);
1343 skb_reserve(skb, start - skb->data);
1344 } else {
1345 skb = netdev_alloc_skb(sky2->netdev,
1346 sky2->rx_data_size + NET_IP_ALIGN);
1347 if (!skb)
1348 goto nomem;
1349 skb_reserve(skb, NET_IP_ALIGN);
1350 }
14d0263f
SH		 1351
1352 for (i = 0; i < sky2->rx_nfrags; i++) {
1353 struct page *page = alloc_page(GFP_ATOMIC);
1354
1355 if (!page)
1356 goto free_partial;
1357 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1358 }
1359
1360 return skb;
14d0263f
SH		 1361free_partial:
1362 kfree_skb(skb);
1363nomem:
1364 return NULL;
82788c7a
SH		 1365}
1366
55c9dd35
SH		 1367static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1368{
1369 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1370}
1371
cd28ab6a
SH		 1372/*
1373 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1374 * Normal case this ends up creating one list element for skb
1375 * in the receive ring. Worst case if using large MTU and each
1376 * allocation falls on a different 64 bit region, that results
1377 * in 6 list elements per ring entry.
1378 * One element is used for checksum enable/disable, and one
1379 * extra to avoid wrap.
cd28ab6a 1380 */
6b1a3aef 1381static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1382{
6b1a3aef 1383 struct sky2_hw *hw = sky2->hw;
14d0263f 1384 struct rx_ring_info *re;
6b1a3aef 1385 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1386 unsigned i, size, thresh;
cd28ab6a 1387
6b1a3aef 1388 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1389 sky2_qset(hw, rxq);
977bdf06 1390
c3905bc4
SH		 1391 /* On PCI express lowering the watermark gives better performance */
1392 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1393 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1394
1395 /* These chips have no ram buffer?
1396 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1397 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1398 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1399 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1400 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1401
6b1a3aef
SH		 1402 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1403
ea76e635
SH		 1404 if (!(hw->flags & SKY2_HW_NEW_LE))
1405 rx_set_checksum(sky2);
14d0263f
SH		 1406
1407 /* Space needed for frame data + headers rounded up */
f957da2a 1408 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1409
1410 /* Stopping point for hardware truncation */
1411 thresh = (size - 8) / sizeof(u32);
1412
5f06eba4 1413 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1414 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1415
5f06eba4
SH		 1416 /* Compute residue after pages */
1417 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1418
5f06eba4
SH		 1419 /* Optimize to handle small packets and headers */
1420 if (size < copybreak)
1421 size = copybreak;
1422 if (size < ETH_HLEN)
1423 size = ETH_HLEN;
14d0263f 1424
14d0263f
SH		 1425 sky2->rx_data_size = size;
1426
1427 /* Fill Rx ring */
793b883e 1428 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1429 re = sky2->rx_ring + i;
cd28ab6a 1430
14d0263f 1431 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1432 if (!re->skb)
1433 goto nomem;
1434
14d0263f
SH		 1435 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1436 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1437 }
1438
a1433ac4
SH		 1439 /*
1440 * The receiver hangs if it receives frames larger than the
1441 * packet buffer. As a workaround, truncate oversize frames, but
1442 * the register is limited to 9 bits, so if you do frames > 2052
1443 * you better get the MTU right!
1444 */
a1433ac4
SH		 1445 if (thresh > 0x1ff)
1446 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1447 else {
1448 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1449 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1450 }
1451
6b1a3aef 1452 /* Tell chip about available buffers */
55c9dd35 1453 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1454 return 0;
1455nomem:
1456 sky2_rx_clean(sky2);
1457 return -ENOMEM;
1458}
1459
1460/* Bring up network interface. */
1461static int sky2_up(struct net_device *dev)
1462{
1463 struct sky2_port *sky2 = netdev_priv(dev);
1464 struct sky2_hw *hw = sky2->hw;
1465 unsigned port = sky2->port;
e0c28116 1466 u32 imask, ramsize;
ee7abb04 1467 int cap, err = -ENOMEM;
843a46f4 1468 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1469
ee7abb04
SH		 1470 /*
1471 * On dual port PCI-X card, there is an problem where status
1472 * can be received out of order due to split transactions
843a46f4 1473 */
ee7abb04
SH		 1474 if (otherdev && netif_running(otherdev) &&
1475 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1476 u16 cmd;
1477
b32f40c4 1478 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1479 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1480 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1481
ee7abb04 1482 }
843a46f4 1483
cd28ab6a
SH		 1484 if (netif_msg_ifup(sky2))
1485 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1486
55d7b4e6
SH		 1487 netif_carrier_off(dev);
1488
cd28ab6a
SH		 1489 /* must be power of 2 */
1490 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1491 TX_RING_SIZE *
1492 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1493 &sky2->tx_le_map);
1494 if (!sky2->tx_le)
1495 goto err_out;
1496
6cdbbdf3 1497 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1498 GFP_KERNEL);
1499 if (!sky2->tx_ring)
1500 goto err_out;
88f5f0ca
SH		 1501
1502 tx_init(sky2);
cd28ab6a
SH		 1503
1504 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1505 &sky2->rx_le_map);
1506 if (!sky2->rx_le)
1507 goto err_out;
1508 memset(sky2->rx_le, 0, RX_LE_BYTES);
1509
291ea614 1510 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1511 GFP_KERNEL);
1512 if (!sky2->rx_ring)
1513 goto err_out;
1514
1515 sky2_mac_init(hw, port);
1516
e0c28116
SH		 1517 /* Register is number of 4K blocks on internal RAM buffer. */
1518 ramsize = sky2_read8(hw, B2_E_0) * 4;
1519 if (ramsize > 0) {
67712901 1520 u32 rxspace;
cd28ab6a 1521
39dbd958 1522 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1523 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1524 if (ramsize < 16)
1525 rxspace = ramsize / 2;
1526 else
1527 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1528
67712901
SH		 1529 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1530 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1531
1532 /* Make sure SyncQ is disabled */
1533 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1534 RB_RST_SET);
1535 }
793b883e 1536
af4ed7e6 1537 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1538
69161611
SH		 1539 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1540 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1541 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1542
977bdf06 1543 /* Set almost empty threshold */
c2716fb4
SH		 1544 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1545 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1546 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1547
6b1a3aef
SH		 1548 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1549 TX_RING_SIZE - 1);
cd28ab6a 1550
d494eacd
SH		 1551#ifdef SKY2_VLAN_TAG_USED
1552 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1553#endif
1554
6b1a3aef 1555 err = sky2_rx_start(sky2);
6de16237 1556 if (err)
cd28ab6a
SH		 1557 goto err_out;
1558
cd28ab6a 1559 /* Enable interrupts from phy/mac for port */
e07b1aa8 1560 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1561 imask |= portirq_msk[port];
e07b1aa8
SH		 1562 sky2_write32(hw, B0_IMSK, imask);
1563
a7bffe72 1564 sky2_set_multicast(dev);
cd28ab6a
SH		 1565 return 0;
1566
1567err_out:
1b537565 1568 if (sky2->rx_le) {
cd28ab6a
SH		 1569 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1570 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1571 sky2->rx_le = NULL;
1572 }
1573 if (sky2->tx_le) {
cd28ab6a
SH		 1574 pci_free_consistent(hw->pdev,
1575 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1576 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1577 sky2->tx_le = NULL;
1578 }
1579 kfree(sky2->tx_ring);
1580 kfree(sky2->rx_ring);
cd28ab6a 1581
1b537565
SH		 1582 sky2->tx_ring = NULL;
1583 sky2->rx_ring = NULL;
cd28ab6a
SH		 1584 return err;
1585}
1586
793b883e
SH		 1587/* Modular subtraction in ring */
1588static inline int tx_dist(unsigned tail, unsigned head)
1589{
cb5d9547 1590 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1591}
cd28ab6a 1592
793b883e
SH		 1593/* Number of list elements available for next tx */
1594static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1595{
793b883e 1596 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1597}
1598
793b883e 1599/* Estimate of number of transmit list elements required */
28bd181a 1600static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1601{
793b883e
SH		 1602 unsigned count;
1603
1604 count = sizeof(dma_addr_t) / sizeof(u32);
1605 count += skb_shinfo(skb)->nr_frags * count;
1606
89114afd 1607 if (skb_is_gso(skb))
793b883e
SH		 1608 ++count;
1609
84fa7933 1610 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1611 ++count;
1612
1613 return count;
cd28ab6a
SH		 1614}
1615
793b883e
SH		 1616/*
1617 * Put one packet in ring for transmit.
1618 * A single packet can generate multiple list elements, and
1619 * the number of ring elements will probably be less than the number
1620 * of list elements used.
1621 */
cd28ab6a
SH		 1622static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1623{
1624 struct sky2_port *sky2 = netdev_priv(dev);
1625 struct sky2_hw *hw = sky2->hw;
d1f13708 1626 struct sky2_tx_le *le = NULL;
6cdbbdf3 1627 struct tx_ring_info *re;
cd28ab6a
SH		 1628 unsigned i, len;
1629 dma_addr_t mapping;
cd28ab6a
SH		 1630 u16 mss;
1631 u8 ctrl;
1632
2bb8c262
SH		 1633 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1634 return NETDEV_TX_BUSY;
cd28ab6a 1635
793b883e 1636 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1637 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1638 dev->name, sky2->tx_prod, skb->len);
1639
cd28ab6a
SH		 1640 len = skb_headlen(skb);
1641 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1642
86c6887e
SH		 1643 /* Send high bits if needed */
1644 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1645 le = get_tx_le(sky2);
86c6887e 1646 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1647 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1648 }
cd28ab6a
SH		 1649
1650 /* Check for TCP Segmentation Offload */
7967168c 1651 mss = skb_shinfo(skb)->gso_size;
793b883e 1652 if (mss != 0) {
ea76e635
SH		 1653
1654 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1655 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1656
1657 if (mss != sky2->tx_last_mss) {
1658 le = get_tx_le(sky2);
1659 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1660
1661 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1662 le->opcode = OP_MSS | HW_OWNER;
1663 else
1664 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1665 sky2->tx_last_mss = mss;
1666 }
cd28ab6a
SH		 1667 }
1668
cd28ab6a 1669 ctrl = 0;
d1f13708
SH		 1670#ifdef SKY2_VLAN_TAG_USED
1671 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1672 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1673 if (!le) {
1674 le = get_tx_le(sky2);
f65b138c 1675 le->addr = 0;
d1f13708 1676 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1677 } else
1678 le->opcode |= OP_VLAN;
1679 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1680 ctrl |= INS_VLAN;
1681 }
1682#endif
1683
1684 /* Handle TCP checksum offload */
84fa7933 1685 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1686 /* On Yukon EX (some versions) encoding change. */
ea76e635 1687 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1688 ctrl |= CALSUM; /* auto checksum */
1689 else {
1690 const unsigned offset = skb_transport_offset(skb);
1691 u32 tcpsum;
1692
1693 tcpsum = offset << 16; /* sum start */
1694 tcpsum |= offset + skb->csum_offset; /* sum write */
1695
1696 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1697 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1698 ctrl |= UDPTCP;
1699
1700 if (tcpsum != sky2->tx_tcpsum) {
1701 sky2->tx_tcpsum = tcpsum;
1702
1703 le = get_tx_le(sky2);
1704 le->addr = cpu_to_le32(tcpsum);
1705 le->length = 0; /* initial checksum value */
1706 le->ctrl = 1; /* one packet */
1707 le->opcode = OP_TCPLISW | HW_OWNER;
1708 }
1d179332 1709 }
cd28ab6a
SH		 1710 }
1711
1712 le = get_tx_le(sky2);
f65b138c 1713 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1714 le->length = cpu_to_le16(len);
1715 le->ctrl = ctrl;
793b883e 1716 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1717
291ea614 1718 re = tx_le_re(sky2, le);
cd28ab6a 1719 re->skb = skb;
6cdbbdf3 1720 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1721 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1722
1723 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1724 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1725
1726 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1727 frag->size, PCI_DMA_TODEVICE);
86c6887e
SH		 1728
1729 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1730 le = get_tx_le(sky2);
86c6887e 1731 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1732 le->ctrl = 0;
1733 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1734 }
1735
1736 le = get_tx_le(sky2);
f65b138c 1737 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1738 le->length = cpu_to_le16(frag->size);
1739 le->ctrl = ctrl;
793b883e 1740 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1741
291ea614
SH		 1742 re = tx_le_re(sky2, le);
1743 re->skb = skb;
1744 pci_unmap_addr_set(re, mapaddr, mapping);
1745 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1746 }
6cdbbdf3 1747
cd28ab6a
SH		 1748 le->ctrl |= EOP;
1749
97bda706
SH		 1750 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1751 netif_stop_queue(dev);
b19666d9 1752
290d4de5 1753 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1754
cd28ab6a
SH		 1755 dev->trans_start = jiffies;
1756 return NETDEV_TX_OK;
1757}
1758
cd28ab6a 1759/*
793b883e
SH		 1760 * Free ring elements from starting at tx_cons until "done"
1761 *
1762 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1763 * buffers so make sure not to free skb to early.
cd28ab6a 1764 */
d11c13e7 1765static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1766{
d11c13e7 1767 struct net_device *dev = sky2->netdev;
af2a58ac 1768 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1769 unsigned idx;
cd28ab6a 1770
0e3ff6aa 1771 BUG_ON(done >= TX_RING_SIZE);
2224795d 1772
291ea614
SH		 1773 for (idx = sky2->tx_cons; idx != done;
1774 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1775 struct sky2_tx_le *le = sky2->tx_le + idx;
1776 struct tx_ring_info *re = sky2->tx_ring + idx;
1777
1778 switch(le->opcode & ~HW_OWNER) {
1779 case OP_LARGESEND:
1780 case OP_PACKET:
1781 pci_unmap_single(pdev,
1782 pci_unmap_addr(re, mapaddr),
1783 pci_unmap_len(re, maplen),
1784 PCI_DMA_TODEVICE);
af2a58ac 1785 break;
291ea614
SH		 1786 case OP_BUFFER:
1787 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1788 pci_unmap_len(re, maplen),
734d1868 1789 PCI_DMA_TODEVICE);
291ea614
SH		 1790 break;
1791 }
1792
1793 if (le->ctrl & EOP) {
1794 if (unlikely(netif_msg_tx_done(sky2)))
1795 printk(KERN_DEBUG "%s: tx done %u\n",
1796 dev->name, idx);
3cf26753 1797
7138a0f5
SH		 1798 dev->stats.tx_packets++;
1799 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1800
794b2bd2 1801 dev_kfree_skb_any(re->skb);
3cf26753 1802 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1803 }
793b883e 1804 }
793b883e 1805
291ea614 1806 sky2->tx_cons = idx;
50432cb5
SH		 1807 smp_mb();
1808
22e11703 1809 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1810 netif_wake_queue(dev);
cd28ab6a
SH		 1811}
1812
1813/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1814static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1815{
2bb8c262
SH		 1816 struct sky2_port *sky2 = netdev_priv(dev);
1817
1818 netif_tx_lock_bh(dev);
d11c13e7 1819 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1820 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1821}
1822
1823/* Network shutdown */
1824static int sky2_down(struct net_device *dev)
1825{
1826 struct sky2_port *sky2 = netdev_priv(dev);
1827 struct sky2_hw *hw = sky2->hw;
1828 unsigned port = sky2->port;
1829 u16 ctrl;
e07b1aa8 1830 u32 imask;
cd28ab6a 1831
1b537565
SH		 1832 /* Never really got started! */
1833 if (!sky2->tx_le)
1834 return 0;
1835
cd28ab6a
SH		 1836 if (netif_msg_ifdown(sky2))
1837 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1838
018d1c66 1839 /* Stop more packets from being queued */
cd28ab6a
SH		 1840 netif_stop_queue(dev);
1841
ebc646f6
SH		 1842 /* Disable port IRQ */
1843 imask = sky2_read32(hw, B0_IMSK);
1844 imask &= ~portirq_msk[port];
1845 sky2_write32(hw, B0_IMSK, imask);
1846
6de16237
SH		 1847 synchronize_irq(hw->pdev->irq);
1848
d3bcfbeb 1849 sky2_gmac_reset(hw, port);
793b883e 1850
cd28ab6a
SH		 1851 /* Stop transmitter */
1852 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1853 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1854
1855 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1856 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1857
1858 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1859 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1860 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1861
6de16237
SH		 1862 /* Make sure no packets are pending */
1863 napi_synchronize(&hw->napi);
1864
cd28ab6a
SH		 1865 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1866
1867 /* Workaround shared GMAC reset */
793b883e
SH		 1868 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1869 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1870 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1871
1872 /* Disable Force Sync bit and Enable Alloc bit */
1873 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1874 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1875
1876 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1877 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1878 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1879
1880 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1881 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1882 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1883
1884 /* Reset the Tx prefetch units */
1885 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1886 PREF_UNIT_RST_SET);
1887
1888 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1889
6b1a3aef 1890 sky2_rx_stop(sky2);
cd28ab6a
SH		 1891
1892 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1893 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1894
b96936da 1895 sky2_phy_power_down(hw, port);
d3bcfbeb 1896
55d7b4e6
SH		 1897 netif_carrier_off(dev);
1898
d571b694 1899 /* turn off LED's */
cd28ab6a
SH		 1900 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1901
2bb8c262 1902 sky2_tx_clean(dev);
cd28ab6a
SH		 1903 sky2_rx_clean(sky2);
1904
1905 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1906 sky2->rx_le, sky2->rx_le_map);
1907 kfree(sky2->rx_ring);
1908
1909 pci_free_consistent(hw->pdev,
1910 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1911 sky2->tx_le, sky2->tx_le_map);
1912 kfree(sky2->tx_ring);
1913
1b537565
SH		 1914 sky2->tx_le = NULL;
1915 sky2->rx_le = NULL;
1916
1917 sky2->rx_ring = NULL;
1918 sky2->tx_ring = NULL;
1919
cd28ab6a
SH		 1920 return 0;
1921}
1922
1923static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1924{
ea76e635 1925 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1926 return SPEED_1000;
1927
05745c4a
SH		 1928 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1929 if (aux & PHY_M_PS_SPEED_100)
1930 return SPEED_100;
1931 else
1932 return SPEED_10;
1933 }
cd28ab6a
SH		 1934
1935 switch (aux & PHY_M_PS_SPEED_MSK) {
1936 case PHY_M_PS_SPEED_1000:
1937 return SPEED_1000;
1938 case PHY_M_PS_SPEED_100:
1939 return SPEED_100;
1940 default:
1941 return SPEED_10;
1942 }
1943}
1944
1945static void sky2_link_up(struct sky2_port *sky2)
1946{
1947 struct sky2_hw *hw = sky2->hw;
1948 unsigned port = sky2->port;
1949 u16 reg;
16ad91e1
SH		 1950 static const char *fc_name[] = {
1951 [FC_NONE] = "none",
1952 [FC_TX] = "tx",
1953 [FC_RX] = "rx",
1954 [FC_BOTH] = "both",
1955 };
cd28ab6a 1956
cd28ab6a 1957 /* enable Rx/Tx */
2eaba1a2 1958 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1959 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1960 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1961
1962 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1963
1964 netif_carrier_on(sky2->netdev);
cd28ab6a 1965
75e80683 1966 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1967
cd28ab6a 1968 /* Turn on link LED */
793b883e 1969 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1970 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1971
1972 if (netif_msg_link(sky2))
1973 printk(KERN_INFO PFX
d571b694 1974 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1975 sky2->netdev->name, sky2->speed,
1976 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1977 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1978}
1979
1980static void sky2_link_down(struct sky2_port *sky2)
1981{
1982 struct sky2_hw *hw = sky2->hw;
1983 unsigned port = sky2->port;
1984 u16 reg;
1985
1986 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1987
1988 reg = gma_read16(hw, port, GM_GP_CTRL);
1989 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1990 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1991
cd28ab6a 1992 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1993
1994 /* Turn on link LED */
1995 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1996
1997 if (netif_msg_link(sky2))
1998 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1999
cd28ab6a
SH		 2000 sky2_phy_init(hw, port);
2001}
2002
16ad91e1
SH		 2003static enum flow_control sky2_flow(int rx, int tx)
2004{
2005 if (rx)
2006 return tx ? FC_BOTH : FC_RX;
2007 else
2008 return tx ? FC_TX : FC_NONE;
2009}
2010
793b883e
SH		 2011static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2012{
2013 struct sky2_hw *hw = sky2->hw;
2014 unsigned port = sky2->port;
da4c1ff4 2015 u16 advert, lpa;
793b883e 2016
da4c1ff4 2017 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2018 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 2019 if (lpa & PHY_M_AN_RF) {
2020 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2021 return -1;
2022 }
2023
793b883e
SH		 2024 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2025 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2026 sky2->netdev->name);
2027 return -1;
2028 }
2029
793b883e 2030 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2031 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2032
da4c1ff4
SH		 2033 /* Since the pause result bits seem to in different positions on
2034 * different chips. look at registers.
2035 */
ea76e635 2036 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2037 /* Shift for bits in fiber PHY */
2038 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2039 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2040
2041 if (advert & ADVERTISE_1000XPAUSE)
2042 advert |= ADVERTISE_PAUSE_CAP;
2043 if (advert & ADVERTISE_1000XPSE_ASYM)
2044 advert |= ADVERTISE_PAUSE_ASYM;
2045 if (lpa & LPA_1000XPAUSE)
2046 lpa |= LPA_PAUSE_CAP;
2047 if (lpa & LPA_1000XPAUSE_ASYM)
2048 lpa |= LPA_PAUSE_ASYM;
2049 }
793b883e 2050
da4c1ff4
SH		 2051 sky2->flow_status = FC_NONE;
2052 if (advert & ADVERTISE_PAUSE_CAP) {
2053 if (lpa & LPA_PAUSE_CAP)
2054 sky2->flow_status = FC_BOTH;
2055 else if (advert & ADVERTISE_PAUSE_ASYM)
2056 sky2->flow_status = FC_RX;
2057 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2058 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2059 sky2->flow_status = FC_TX;
2060 }
793b883e 2061
16ad91e1 2062 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 2063 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2064 sky2->flow_status = FC_NONE;
2eaba1a2 2065
da4c1ff4 2066 if (sky2->flow_status & FC_TX)
793b883e
SH		 2067 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2068 else
2069 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2070
2071 return 0;
2072}
cd28ab6a 2073
e07b1aa8
SH		 2074/* Interrupt from PHY */
2075static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2076{
e07b1aa8
SH		 2077 struct net_device *dev = hw->dev[port];
2078 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2079 u16 istatus, phystat;
2080
ebc646f6
SH		 2081 if (!netif_running(dev))
2082 return;
2083
e07b1aa8
SH		 2084 spin_lock(&sky2->phy_lock);
2085 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2086 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2087
cd28ab6a
SH		 2088 if (netif_msg_intr(sky2))
2089 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2090 sky2->netdev->name, istatus, phystat);
2091
2eaba1a2 2092 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 2093 if (sky2_autoneg_done(sky2, phystat) == 0)
2094 sky2_link_up(sky2);
2095 goto out;
2096 }
cd28ab6a 2097
793b883e
SH		 2098 if (istatus & PHY_M_IS_LSP_CHANGE)
2099 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2100
793b883e
SH		 2101 if (istatus & PHY_M_IS_DUP_CHANGE)
2102 sky2->duplex =
2103 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2104
793b883e
SH		 2105 if (istatus & PHY_M_IS_LST_CHANGE) {
2106 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2107 sky2_link_up(sky2);
793b883e
SH		 2108 else
2109 sky2_link_down(sky2);
cd28ab6a 2110 }
793b883e 2111out:
e07b1aa8 2112 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2113}
2114
62335ab0 2115/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2116 * and tx queue is full (stopped).
2117 */
cd28ab6a
SH		 2118static void sky2_tx_timeout(struct net_device *dev)
2119{
2120 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2121 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2122
2123 if (netif_msg_timer(sky2))
2124 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2125
8f24664d 2126 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2127 dev->name, sky2->tx_cons, sky2->tx_prod,
2128 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2129 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2130
81906791
SH		 2131 /* can't restart safely under softirq */
2132 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2133}
2134
2135static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2136{
6b1a3aef
SH		 2137 struct sky2_port *sky2 = netdev_priv(dev);
2138 struct sky2_hw *hw = sky2->hw;
b628ed98 2139 unsigned port = sky2->port;
6b1a3aef
SH		 2140 int err;
2141 u16 ctl, mode;
e07b1aa8 2142 u32 imask;
cd28ab6a
SH		 2143
2144 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2145 return -EINVAL;
2146
05745c4a
SH		 2147 if (new_mtu > ETH_DATA_LEN &&
2148 (hw->chip_id == CHIP_ID_YUKON_FE ||
2149 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2150 return -EINVAL;
2151
6b1a3aef
SH		 2152 if (!netif_running(dev)) {
2153 dev->mtu = new_mtu;
2154 return 0;
2155 }
2156
e07b1aa8 2157 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2158 sky2_write32(hw, B0_IMSK, 0);
2159
018d1c66
SH		 2160 dev->trans_start = jiffies; /* prevent tx timeout */
2161 netif_stop_queue(dev);
bea3348e 2162 napi_disable(&hw->napi);
018d1c66 2163
e07b1aa8
SH		 2164 synchronize_irq(hw->pdev->irq);
2165
39dbd958 2166 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2167 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2168
2169 ctl = gma_read16(hw, port, GM_GP_CTRL);
2170 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2171 sky2_rx_stop(sky2);
2172 sky2_rx_clean(sky2);
cd28ab6a
SH		 2173
2174 dev->mtu = new_mtu;
14d0263f 2175
6b1a3aef
SH		 2176 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2177 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2178
2179 if (dev->mtu > ETH_DATA_LEN)
2180 mode |= GM_SMOD_JUMBO_ENA;
2181
b628ed98 2182 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2183
b628ed98 2184 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2185
6b1a3aef 2186 err = sky2_rx_start(sky2);
e07b1aa8 2187 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2188
d1d08d12 2189 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2190 napi_enable(&hw->napi);
2191
1b537565
SH		 2192 if (err)
2193 dev_close(dev);
2194 else {
b628ed98 2195 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2196
1b537565
SH		 2197 netif_wake_queue(dev);
2198 }
2199
cd28ab6a
SH		 2200 return err;
2201}
2202
14d0263f
SH		 2203/* For small just reuse existing skb for next receive */
2204static struct sk_buff *receive_copy(struct sky2_port *sky2,
2205 const struct rx_ring_info *re,
2206 unsigned length)
2207{
2208 struct sk_buff *skb;
2209
2210 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2211 if (likely(skb)) {
2212 skb_reserve(skb, 2);
2213 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2214 length, PCI_DMA_FROMDEVICE);
d626f62b 2215 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2216 skb->ip_summed = re->skb->ip_summed;
2217 skb->csum = re->skb->csum;
2218 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2219 length, PCI_DMA_FROMDEVICE);
2220 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2221 skb_put(skb, length);
14d0263f
SH		 2222 }
2223 return skb;
2224}
2225
2226/* Adjust length of skb with fragments to match received data */
2227static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2228 unsigned int length)
2229{
2230 int i, num_frags;
2231 unsigned int size;
2232
2233 /* put header into skb */
2234 size = min(length, hdr_space);
2235 skb->tail += size;
2236 skb->len += size;
2237 length -= size;
2238
2239 num_frags = skb_shinfo(skb)->nr_frags;
2240 for (i = 0; i < num_frags; i++) {
2241 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2242
2243 if (length == 0) {
2244 /* don't need this page */
2245 __free_page(frag->page);
2246 --skb_shinfo(skb)->nr_frags;
2247 } else {
2248 size = min(length, (unsigned) PAGE_SIZE);
2249
2250 frag->size = size;
2251 skb->data_len += size;
2252 skb->truesize += size;
2253 skb->len += size;
2254 length -= size;
2255 }
2256 }
2257}
2258
2259/* Normal packet - take skb from ring element and put in a new one */
2260static struct sk_buff *receive_new(struct sky2_port *sky2,
2261 struct rx_ring_info *re,
2262 unsigned int length)
2263{
2264 struct sk_buff *skb, *nskb;
2265 unsigned hdr_space = sky2->rx_data_size;
2266
14d0263f
SH		 2267 /* Don't be tricky about reusing pages (yet) */
2268 nskb = sky2_rx_alloc(sky2);
2269 if (unlikely(!nskb))
2270 return NULL;
2271
2272 skb = re->skb;
2273 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2274
2275 prefetch(skb->data);
2276 re->skb = nskb;
2277 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2278
2279 if (skb_shinfo(skb)->nr_frags)
2280 skb_put_frags(skb, hdr_space, length);
2281 else
489b10c1 2282 skb_put(skb, length);
14d0263f
SH		 2283 return skb;
2284}
2285
cd28ab6a
SH		 2286/*
2287 * Receive one packet.
d571b694 2288 * For larger packets, get new buffer.
cd28ab6a 2289 */
497d7c86 2290static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2291 u16 length, u32 status)
2292{
497d7c86 2293 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2294 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2295 struct sk_buff *skb = NULL;
d6532232
SH		 2296 u16 count = (status & GMR_FS_LEN) >> 16;
2297
2298#ifdef SKY2_VLAN_TAG_USED
2299 /* Account for vlan tag */
2300 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2301 count -= VLAN_HLEN;
2302#endif
cd28ab6a
SH		 2303
2304 if (unlikely(netif_msg_rx_status(sky2)))
2305 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2306 dev->name, sky2->rx_next, status, length);
cd28ab6a 2307
793b883e 2308 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2309 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2310
3b12e014
SH		 2311 /* This chip has hardware problems that generates bogus status.
2312 * So do only marginal checking and expect higher level protocols
2313 * to handle crap frames.
2314 */
2315 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2316 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2317 length != count)
2318 goto okay;
2319
42eeea01 2320 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2321 goto error;
2322
42eeea01
SH		 2323 if (!(status & GMR_FS_RX_OK))
2324 goto resubmit;
2325
d6532232
SH		 2326 /* if length reported by DMA does not match PHY, packet was truncated */
2327 if (length != count)
3b12e014 2328 goto len_error;
71749531 2329
3b12e014 2330okay:
14d0263f
SH		 2331 if (length < copybreak)
2332 skb = receive_copy(sky2, re, length);
2333 else
2334 skb = receive_new(sky2, re, length);
793b883e 2335resubmit:
14d0263f 2336 sky2_rx_submit(sky2, re);
79e57d32 2337
cd28ab6a
SH		 2338 return skb;
2339
3b12e014 2340len_error:
71749531
SH		 2341 /* Truncation of overlength packets
2342 causes PHY length to not match MAC length */
7138a0f5 2343 ++dev->stats.rx_length_errors;
d6532232 2344 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2345 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2346 dev->name, status, length);
d6532232 2347 goto resubmit;
71749531 2348
cd28ab6a 2349error:
7138a0f5 2350 ++dev->stats.rx_errors;
b6d77734 2351 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2352 dev->stats.rx_over_errors++;
b6d77734
SH		 2353 goto resubmit;
2354 }
6e15b712 2355
3be92a70 2356 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2357 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2358 dev->name, status, length);
793b883e
SH		 2359
2360 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2361 dev->stats.rx_length_errors++;
cd28ab6a 2362 if (status & GMR_FS_FRAGMENT)
7138a0f5 2363 dev->stats.rx_frame_errors++;
cd28ab6a 2364 if (status & GMR_FS_CRC_ERR)
7138a0f5 2365 dev->stats.rx_crc_errors++;
79e57d32 2366
793b883e 2367 goto resubmit;
cd28ab6a
SH		 2368}
2369
e07b1aa8
SH		 2370/* Transmit complete */
2371static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2372{
e07b1aa8 2373 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2374
e07b1aa8 2375 if (netif_running(dev)) {
2bb8c262 2376 netif_tx_lock(dev);
e07b1aa8 2377 sky2_tx_complete(sky2, last);
2bb8c262 2378 netif_tx_unlock(dev);
2224795d 2379 }
cd28ab6a
SH		 2380}
2381
e07b1aa8 2382/* Process status response ring */
26691830 2383static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2384{
e07b1aa8 2385 int work_done = 0;
55c9dd35 2386 unsigned rx[2] = { 0, 0 };
a8fd6266 2387
af2a58ac 2388 rmb();
26691830 2389 do {
55c9dd35 2390 struct sky2_port *sky2;
13210ce5 2391 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2392 unsigned port;
13210ce5 2393 struct net_device *dev;
cd28ab6a 2394 struct sk_buff *skb;
cd28ab6a
SH		 2395 u32 status;
2396 u16 length;
ab5adecb
SH		 2397 u8 opcode = le->opcode;
2398
2399 if (!(opcode & HW_OWNER))
2400 break;
cd28ab6a 2401
cb5d9547 2402 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2403
ab5adecb 2404 port = le->css & CSS_LINK_BIT;
69161611 2405 dev = hw->dev[port];
13210ce5 2406 sky2 = netdev_priv(dev);
f65b138c
SH		 2407 length = le16_to_cpu(le->length);
2408 status = le32_to_cpu(le->status);
cd28ab6a 2409
ab5adecb
SH		 2410 le->opcode = 0;
2411 switch (opcode & ~HW_OWNER) {
cd28ab6a 2412 case OP_RXSTAT:
55c9dd35 2413 ++rx[port];
497d7c86 2414 skb = sky2_receive(dev, length, status);
3225b919 2415 if (unlikely(!skb)) {
7138a0f5 2416 dev->stats.rx_dropped++;
55c9dd35 2417 break;
3225b919 2418 }
13210ce5 2419
69161611 2420 /* This chip reports checksum status differently */
05745c4a 2421 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2422 if (sky2->rx_csum &&
2423 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2424 (le->css & CSS_TCPUDPCSOK))
2425 skb->ip_summed = CHECKSUM_UNNECESSARY;
2426 else
2427 skb->ip_summed = CHECKSUM_NONE;
2428 }
2429
13210ce5 2430 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2431 dev->stats.rx_packets++;
2432 dev->stats.rx_bytes += skb->len;
13210ce5
SH		 2433 dev->last_rx = jiffies;
2434
d1f13708
SH		 2435#ifdef SKY2_VLAN_TAG_USED
2436 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2437 vlan_hwaccel_receive_skb(skb,
2438 sky2->vlgrp,
2439 be16_to_cpu(sky2->rx_tag));
2440 } else
2441#endif
cd28ab6a 2442 netif_receive_skb(skb);
13210ce5 2443
22e11703 2444 /* Stop after net poll weight */
13210ce5
SH		 2445 if (++work_done >= to_do)
2446 goto exit_loop;
cd28ab6a
SH		 2447 break;
2448
d1f13708
SH		 2449#ifdef SKY2_VLAN_TAG_USED
2450 case OP_RXVLAN:
2451 sky2->rx_tag = length;
2452 break;
2453
2454 case OP_RXCHKSVLAN:
2455 sky2->rx_tag = length;
2456 /* fall through */
2457#endif
cd28ab6a 2458 case OP_RXCHKS:
87418307
SH		 2459 if (!sky2->rx_csum)
2460 break;
2461
05745c4a
SH		 2462 /* If this happens then driver assuming wrong format */
2463 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2464 if (net_ratelimit())
2465 printk(KERN_NOTICE "%s: unexpected"
2466 " checksum status\n",
2467 dev->name);
69161611 2468 break;
05745c4a 2469 }
69161611 2470
87418307
SH		 2471 /* Both checksum counters are programmed to start at
2472 * the same offset, so unless there is a problem they
2473 * should match. This failure is an early indication that
2474 * hardware receive checksumming won't work.
2475 */
2476 if (likely(status >> 16 == (status & 0xffff))) {
2477 skb = sky2->rx_ring[sky2->rx_next].skb;
2478 skb->ip_summed = CHECKSUM_COMPLETE;
2479 skb->csum = status & 0xffff;
2480 } else {
2481 printk(KERN_NOTICE PFX "%s: hardware receive "
2482 "checksum problem (status = %#x)\n",
2483 dev->name, status);
2484 sky2->rx_csum = 0;
2485 sky2_write32(sky2->hw,
69161611 2486 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2487 BMU_DIS_RX_CHKSUM);
2488 }
cd28ab6a
SH		 2489 break;
2490
2491 case OP_TXINDEXLE:
13b97b74 2492 /* TX index reports status for both ports */
f55925d7
SH		 2493 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2494 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2495 if (hw->dev[1])
2496 sky2_tx_done(hw->dev[1],
2497 ((status >> 24) & 0xff)
2498 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2499 break;
2500
cd28ab6a
SH		 2501 default:
2502 if (net_ratelimit())
793b883e 2503 printk(KERN_WARNING PFX
ab5adecb 2504 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2505 }
26691830 2506 } while (hw->st_idx != idx);
cd28ab6a 2507
fe2a24df
SH		 2508 /* Fully processed status ring so clear irq */
2509 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2510
13210ce5 2511exit_loop:
55c9dd35
SH		 2512 if (rx[0])
2513 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2514
55c9dd35
SH		 2515 if (rx[1])
2516 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2517
e07b1aa8 2518 return work_done;
cd28ab6a
SH		 2519}
2520
2521static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2522{
2523 struct net_device *dev = hw->dev[port];
2524
3be92a70
SH		 2525 if (net_ratelimit())
2526 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2527 dev->name, status);
cd28ab6a
SH		 2528
2529 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2530 if (net_ratelimit())
2531 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2532 dev->name);
cd28ab6a
SH		 2533 /* Clear IRQ */
2534 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2535 }
2536
2537 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2538 if (net_ratelimit())
2539 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2540 dev->name);
cd28ab6a
SH		 2541
2542 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2543 }
2544
2545 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2546 if (net_ratelimit())
2547 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2548 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2549 }
2550
2551 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2552 if (net_ratelimit())
2553 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2554 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2555 }
2556
2557 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2558 if (net_ratelimit())
2559 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2560 dev->name);
cd28ab6a
SH		 2561 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2562 }
2563}
2564
2565static void sky2_hw_intr(struct sky2_hw *hw)
2566{
555382cb 2567 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2568 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2569 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2570
2571 status &= hwmsk;
cd28ab6a 2572
793b883e 2573 if (status & Y2_IS_TIST_OV)
cd28ab6a 2574 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2575
2576 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2577 u16 pci_err;
2578
82637e80 2579 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2580 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2581 if (net_ratelimit())
555382cb 2582 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2583 pci_err);
cd28ab6a 2584
b32f40c4 2585 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2586 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2587 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2588 }
2589
2590 if (status & Y2_IS_PCI_EXP) {
d571b694 2591 /* PCI-Express uncorrectable Error occurred */
555382cb 2592 u32 err;
cd28ab6a 2593
82637e80 2594 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2595 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2596 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2597 0xfffffffful);
3be92a70 2598 if (net_ratelimit())
555382cb 2599 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2600
7782c8c4 2601 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2602 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2603 }
2604
2605 if (status & Y2_HWE_L1_MASK)
2606 sky2_hw_error(hw, 0, status);
2607 status >>= 8;
2608 if (status & Y2_HWE_L1_MASK)
2609 sky2_hw_error(hw, 1, status);
2610}
2611
2612static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2613{
2614 struct net_device *dev = hw->dev[port];
2615 struct sky2_port *sky2 = netdev_priv(dev);
2616 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2617
2618 if (netif_msg_intr(sky2))
2619 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2620 dev->name, status);
2621
a3caeada
SH		 2622 if (status & GM_IS_RX_CO_OV)
2623 gma_read16(hw, port, GM_RX_IRQ_SRC);
2624
2625 if (status & GM_IS_TX_CO_OV)
2626 gma_read16(hw, port, GM_TX_IRQ_SRC);
2627
cd28ab6a 2628 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2629 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2630 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2631 }
2632
2633 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2634 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2635 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2636 }
cd28ab6a
SH		 2637}
2638
40b01727
SH		 2639/* This should never happen it is a bug. */
2640static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2641 u16 q, unsigned ring_size)
d257924e
SH		 2642{
2643 struct net_device *dev = hw->dev[port];
2644 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2645 unsigned idx;
2646 const u64 *le = (q == Q_R1 || q == Q_R2)
2647 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2648
40b01727
SH		 2649 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2650 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2651 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2652 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2653
40b01727 2654 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2655}
cd28ab6a 2656
75e80683
SH		 2657static int sky2_rx_hung(struct net_device *dev)
2658{
2659 struct sky2_port *sky2 = netdev_priv(dev);
2660 struct sky2_hw *hw = sky2->hw;
2661 unsigned port = sky2->port;
2662 unsigned rxq = rxqaddr[port];
2663 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2664 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2665 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2666 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2667
2668 /* If idle and MAC or PCI is stuck */
2669 if (sky2->check.last == dev->last_rx &&
2670 ((mac_rp == sky2->check.mac_rp &&
2671 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2672 /* Check if the PCI RX hang */
2673 (fifo_rp == sky2->check.fifo_rp &&
2674 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2675 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2676 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2677 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2678 return 1;
2679 } else {
2680 sky2->check.last = dev->last_rx;
2681 sky2->check.mac_rp = mac_rp;
2682 sky2->check.mac_lev = mac_lev;
2683 sky2->check.fifo_rp = fifo_rp;
2684 sky2->check.fifo_lev = fifo_lev;
2685 return 0;
2686 }
2687}
2688
32c2c300 2689static void sky2_watchdog(unsigned long arg)
d27ed387 2690{
01bd7564 2691 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2692
75e80683 2693 /* Check for lost IRQ once a second */
32c2c300 2694 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2695 napi_schedule(&hw->napi);
75e80683
SH		 2696 } else {
2697 int i, active = 0;
2698
2699 for (i = 0; i < hw->ports; i++) {
bea3348e 2700 struct net_device *dev = hw->dev[i];
75e80683
SH		 2701 if (!netif_running(dev))
2702 continue;
2703 ++active;
2704
2705 /* For chips with Rx FIFO, check if stuck */
39dbd958 2706 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2707 sky2_rx_hung(dev)) {
2708 pr_info(PFX "%s: receiver hang detected\n",
2709 dev->name);
2710 schedule_work(&hw->restart_work);
2711 return;
2712 }
2713 }
2714
2715 if (active == 0)
2716 return;
32c2c300 2717 }
01bd7564 2718
75e80683 2719 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2720}
2721
40b01727
SH		 2722/* Hardware/software error handling */
2723static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2724{
40b01727
SH		 2725 if (net_ratelimit())
2726 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2727
1e5f1283
SH		 2728 if (status & Y2_IS_HW_ERR)
2729 sky2_hw_intr(hw);
d257924e 2730
1e5f1283
SH		 2731 if (status & Y2_IS_IRQ_MAC1)
2732 sky2_mac_intr(hw, 0);
cd28ab6a 2733
1e5f1283
SH		 2734 if (status & Y2_IS_IRQ_MAC2)
2735 sky2_mac_intr(hw, 1);
cd28ab6a 2736
1e5f1283 2737 if (status & Y2_IS_CHK_RX1)
40b01727 2738 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2739
1e5f1283 2740 if (status & Y2_IS_CHK_RX2)
40b01727 2741 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2742
1e5f1283 2743 if (status & Y2_IS_CHK_TXA1)
40b01727 2744 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2745
1e5f1283 2746 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2747 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2748}
2749
bea3348e 2750static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2751{
bea3348e 2752 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2753 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2754 int work_done = 0;
26691830 2755 u16 idx;
40b01727
SH		 2756
2757 if (unlikely(status & Y2_IS_ERROR))
2758 sky2_err_intr(hw, status);
2759
2760 if (status & Y2_IS_IRQ_PHY1)
2761 sky2_phy_intr(hw, 0);
2762
2763 if (status & Y2_IS_IRQ_PHY2)
2764 sky2_phy_intr(hw, 1);
cd28ab6a 2765
26691830
SH		 2766 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2767 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2768
2769 if (work_done >= work_limit)
26691830
SH		 2770 goto done;
2771 }
6f535763 2772
26691830
SH		 2773 /* Bug/Errata workaround?
2774 * Need to kick the TX irq moderation timer.
2775 */
2776 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2777 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2778 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2779 }
26691830
SH		 2780 napi_complete(napi);
2781 sky2_read32(hw, B0_Y2_SP_LISR);
2782done:
6f535763 2783
bea3348e 2784 return work_done;
e07b1aa8
SH		 2785}
2786
7d12e780 2787static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2788{
2789 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2790 u32 status;
2791
2792 /* Reading this mask interrupts as side effect */
2793 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2794 if (status == 0 || status == ~0)
2795 return IRQ_NONE;
793b883e 2796
e07b1aa8 2797 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2798
2799 napi_schedule(&hw->napi);
793b883e 2800
cd28ab6a
SH		 2801 return IRQ_HANDLED;
2802}
2803
2804#ifdef CONFIG_NET_POLL_CONTROLLER
2805static void sky2_netpoll(struct net_device *dev)
2806{
2807 struct sky2_port *sky2 = netdev_priv(dev);
2808
bea3348e 2809 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2810}
2811#endif
2812
2813/* Chip internal frequency for clock calculations */
05745c4a 2814static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2815{
793b883e 2816 switch (hw->chip_id) {
cd28ab6a 2817 case CHIP_ID_YUKON_EC:
5a5b1ea0 2818 case CHIP_ID_YUKON_EC_U:
93745494 2819 case CHIP_ID_YUKON_EX:
ed4d4161 2820 case CHIP_ID_YUKON_SUPR:
05745c4a
SH		 2821 return 125;
2822
cd28ab6a 2823 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2824 return 100;
2825
2826 case CHIP_ID_YUKON_FE_P:
2827 return 50;
2828
2829 case CHIP_ID_YUKON_XL:
2830 return 156;
2831
2832 default:
2833 BUG();
cd28ab6a
SH		 2834 }
2835}
2836
fb17358f 2837static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2838{
fb17358f 2839 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2840}
2841
fb17358f 2842static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2843{
fb17358f 2844 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2845}
2846
fb17358f 2847
e3173832 2848static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2849{
b89165f2 2850 u8 t8;
cd28ab6a 2851
167f53d0 2852 /* Enable all clocks and check for bad PCI access */
b32f40c4 2853 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2854
cd28ab6a 2855 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2856
cd28ab6a 2857 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2858 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2859
2860 switch(hw->chip_id) {
2861 case CHIP_ID_YUKON_XL:
39dbd958 2862 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2863 break;
2864
2865 case CHIP_ID_YUKON_EC_U:
2866 hw->flags = SKY2_HW_GIGABIT
2867 | SKY2_HW_NEWER_PHY
2868 | SKY2_HW_ADV_POWER_CTL;
a068c0ad
SH		 2869
2870 /* check for Rev. A1 dev 4200 */
2871 if (sky2_read16(hw, Q_ADDR(Q_XA1, Q_WM)) == 0)
2872 hw->flags |= SKY2_HW_CLK_POWER;
ea76e635
SH		 2873 break;
2874
2875 case CHIP_ID_YUKON_EX:
2876 hw->flags = SKY2_HW_GIGABIT
2877 | SKY2_HW_NEWER_PHY
2878 | SKY2_HW_NEW_LE
2879 | SKY2_HW_ADV_POWER_CTL;
2880
2881 /* New transmit checksum */
2882 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2883 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2884 break;
2885
2886 case CHIP_ID_YUKON_EC:
2887 /* This rev is really old, and requires untested workarounds */
2888 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2889 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2890 return -EOPNOTSUPP;
2891 }
39dbd958 2892 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2893 break;
2894
2895 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2896 break;
2897
05745c4a
SH		 2898 case CHIP_ID_YUKON_FE_P:
2899 hw->flags = SKY2_HW_NEWER_PHY
2900 | SKY2_HW_NEW_LE
2901 | SKY2_HW_AUTO_TX_SUM
2902 | SKY2_HW_ADV_POWER_CTL;
2903 break;
ed4d4161
SH		 2904
2905 case CHIP_ID_YUKON_SUPR:
2906 hw->flags = SKY2_HW_GIGABIT
2907 | SKY2_HW_NEWER_PHY
2908 | SKY2_HW_NEW_LE
2909 | SKY2_HW_AUTO_TX_SUM
2910 | SKY2_HW_ADV_POWER_CTL;
2911 break;
2912
ea76e635 2913 default:
b02a9258
SH		 2914 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2915 hw->chip_id);
cd28ab6a
SH		 2916 return -EOPNOTSUPP;
2917 }
2918
ea76e635
SH		 2919 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2920 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2921 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2922
a068c0ad
SH		 2923 hw->pm_cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PM);
2924 if (hw->pm_cap == 0) {
2925 dev_err(&hw->pdev->dev, "cannot find PowerManagement capability\n");
2926 return -EIO;
2927 }
290d4de5 2928
e3173832
SH		 2929 hw->ports = 1;
2930 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2931 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2932 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2933 ++hw->ports;
2934 }
2935
2936 return 0;
2937}
2938
2939static void sky2_reset(struct sky2_hw *hw)
2940{
555382cb 2941 struct pci_dev *pdev = hw->pdev;
e3173832 2942 u16 status;
555382cb
SH		 2943 int i, cap;
2944 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2945
cd28ab6a 2946 /* disable ASF */
4f44d8ba
SH		 2947 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2948 status = sky2_read16(hw, HCU_CCSR);
2949 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2950 HCU_CCSR_UC_STATE_MSK);
2951 sky2_write16(hw, HCU_CCSR, status);
2952 } else
2953 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2954 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2955
2956 /* do a SW reset */
2957 sky2_write8(hw, B0_CTST, CS_RST_SET);
2958 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2959
ac93a394
SH		 2960 /* allow writes to PCI config */
2961 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2962
cd28ab6a 2963 /* clear PCI errors, if any */
b32f40c4 2964 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2965 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2966 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2967
2968 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2969
555382cb
SH		 2970 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2971 if (cap) {
7782c8c4
SH		 2972 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2973 0xfffffffful);
555382cb
SH		 2974
2975 /* If error bit is stuck on ignore it */
2976 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2977 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2978 else
555382cb
SH		 2979 hwe_mask |= Y2_IS_PCI_EXP;
2980 }
cd28ab6a 2981
ae306cca 2982 sky2_power_on(hw);
82637e80 2983 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2984
2985 for (i = 0; i < hw->ports; i++) {
2986 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2987 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2988
ed4d4161
SH		 2989 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2990 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2991 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2992 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2993 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2994 }
2995
793b883e
SH		 2996 /* Clear I2C IRQ noise */
2997 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2998
2999 /* turn off hardware timer (unused) */
3000 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3001 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3002
cd28ab6a
SH		 3003 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
3004
69634ee7
SH		 3005 /* Turn off descriptor polling */
3006 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3007
3008 /* Turn off receive timestamp */
3009 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3010 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3011
3012 /* enable the Tx Arbiters */
3013 for (i = 0; i < hw->ports; i++)
3014 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3015
3016 /* Initialize ram interface */
3017 for (i = 0; i < hw->ports; i++) {
793b883e 3018 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3019
3020 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3021 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3022 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3023 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3024 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3025 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3026 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3027 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3028 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3029 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3030 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3031 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3032 }
3033
555382cb 3034 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3035
cd28ab6a 3036 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3037 sky2_gmac_reset(hw, i);
cd28ab6a 3038
cd28ab6a
SH		 3039 memset(hw->st_le, 0, STATUS_LE_BYTES);
3040 hw->st_idx = 0;
3041
3042 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3043 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3044
3045 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3046 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3047
3048 /* Set the list last index */
793b883e 3049 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3050
290d4de5
SH		 3051 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3052 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3053
290d4de5
SH		 3054 /* set Status-FIFO ISR watermark */
3055 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3056 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3057 else
3058 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3059
290d4de5 3060 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3061 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3062 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3063
793b883e 3064 /* enable status unit */
cd28ab6a
SH		 3065 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3066
3067 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3068 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3069 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3070}
3071
81906791
SH		 3072static void sky2_restart(struct work_struct *work)
3073{
3074 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3075 struct net_device *dev;
3076 int i, err;
3077
81906791 3078 rtnl_lock();
81906791
SH		 3079 for (i = 0; i < hw->ports; i++) {
3080 dev = hw->dev[i];
3081 if (netif_running(dev))
3082 sky2_down(dev);
3083 }
3084
8cfcbe99
SH		 3085 napi_disable(&hw->napi);
3086 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3087 sky2_reset(hw);
3088 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3089 napi_enable(&hw->napi);
81906791
SH		 3090
3091 for (i = 0; i < hw->ports; i++) {
3092 dev = hw->dev[i];
3093 if (netif_running(dev)) {
3094 err = sky2_up(dev);
3095 if (err) {
3096 printk(KERN_INFO PFX "%s: could not restart %d\n",
3097 dev->name, err);
3098 dev_close(dev);
3099 }
3100 }
3101 }
3102
81906791
SH		 3103 rtnl_unlock();
3104}
3105
e3173832
SH		 3106static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3107{
3108 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3109}
3110
3111static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3112{
3113 const struct sky2_port *sky2 = netdev_priv(dev);
3114
3115 wol->supported = sky2_wol_supported(sky2->hw);
3116 wol->wolopts = sky2->wol;
3117}
3118
3119static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3120{
3121 struct sky2_port *sky2 = netdev_priv(dev);
3122 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3123
e3173832
SH		 3124 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
3125 return -EOPNOTSUPP;
3126
3127 sky2->wol = wol->wolopts;
3128
05745c4a
SH		 3129 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3130 hw->chip_id == CHIP_ID_YUKON_EX ||
3131 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3132 sky2_write32(hw, B0_CTST, sky2->wol
3133 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3134
3135 if (!netif_running(dev))
3136 sky2_wol_init(sky2);
cd28ab6a
SH		 3137 return 0;
3138}
3139
28bd181a 3140static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3141{
b89165f2
SH		 3142 if (sky2_is_copper(hw)) {
3143 u32 modes = SUPPORTED_10baseT_Half
3144 | SUPPORTED_10baseT_Full
3145 | SUPPORTED_100baseT_Half
3146 | SUPPORTED_100baseT_Full
3147 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3148
ea76e635 3149 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3150 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3151 | SUPPORTED_1000baseT_Full;
3152 return modes;
cd28ab6a 3153 } else
b89165f2
SH		 3154 return SUPPORTED_1000baseT_Half
3155 | SUPPORTED_1000baseT_Full
3156 | SUPPORTED_Autoneg
3157 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3158}
3159
793b883e 3160static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3161{
3162 struct sky2_port *sky2 = netdev_priv(dev);
3163 struct sky2_hw *hw = sky2->hw;
3164
3165 ecmd->transceiver = XCVR_INTERNAL;
3166 ecmd->supported = sky2_supported_modes(hw);
3167 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3168 if (sky2_is_copper(hw)) {
cd28ab6a 3169 ecmd->port = PORT_TP;
b89165f2
SH		 3170 ecmd->speed = sky2->speed;
3171 } else {
3172 ecmd->speed = SPEED_1000;
cd28ab6a 3173 ecmd->port = PORT_FIBRE;
b89165f2 3174 }
cd28ab6a
SH		 3175
3176 ecmd->advertising = sky2->advertising;
3177 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3178 ecmd->duplex = sky2->duplex;
3179 return 0;
3180}
3181
3182static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3183{
3184 struct sky2_port *sky2 = netdev_priv(dev);
3185 const struct sky2_hw *hw = sky2->hw;
3186 u32 supported = sky2_supported_modes(hw);
3187
3188 if (ecmd->autoneg == AUTONEG_ENABLE) {
3189 ecmd->advertising = supported;
3190 sky2->duplex = -1;
3191 sky2->speed = -1;
3192 } else {
3193 u32 setting;
3194
793b883e 3195 switch (ecmd->speed) {
cd28ab6a
SH		 3196 case SPEED_1000:
3197 if (ecmd->duplex == DUPLEX_FULL)
3198 setting = SUPPORTED_1000baseT_Full;
3199 else if (ecmd->duplex == DUPLEX_HALF)
3200 setting = SUPPORTED_1000baseT_Half;
3201 else
3202 return -EINVAL;
3203 break;
3204 case SPEED_100:
3205 if (ecmd->duplex == DUPLEX_FULL)
3206 setting = SUPPORTED_100baseT_Full;
3207 else if (ecmd->duplex == DUPLEX_HALF)
3208 setting = SUPPORTED_100baseT_Half;
3209 else
3210 return -EINVAL;
3211 break;
3212
3213 case SPEED_10:
3214 if (ecmd->duplex == DUPLEX_FULL)
3215 setting = SUPPORTED_10baseT_Full;
3216 else if (ecmd->duplex == DUPLEX_HALF)
3217 setting = SUPPORTED_10baseT_Half;
3218 else
3219 return -EINVAL;
3220 break;
3221 default:
3222 return -EINVAL;
3223 }
3224
3225 if ((setting & supported) == 0)
3226 return -EINVAL;
3227
3228 sky2->speed = ecmd->speed;
3229 sky2->duplex = ecmd->duplex;
3230 }
3231
3232 sky2->autoneg = ecmd->autoneg;
3233 sky2->advertising = ecmd->advertising;
3234
d1b139c0 3235 if (netif_running(dev)) {
1b537565 3236 sky2_phy_reinit(sky2);
d1b139c0
SH		 3237 sky2_set_multicast(dev);
3238 }
cd28ab6a
SH		 3239
3240 return 0;
3241}
3242
3243static void sky2_get_drvinfo(struct net_device *dev,
3244 struct ethtool_drvinfo *info)
3245{
3246 struct sky2_port *sky2 = netdev_priv(dev);
3247
3248 strcpy(info->driver, DRV_NAME);
3249 strcpy(info->version, DRV_VERSION);
3250 strcpy(info->fw_version, "N/A");
3251 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3252}
3253
3254static const struct sky2_stat {
793b883e
SH		 3255 char name[ETH_GSTRING_LEN];
3256 u16 offset;
cd28ab6a
SH		 3257} sky2_stats[] = {
3258 { "tx_bytes", GM_TXO_OK_HI },
3259 { "rx_bytes", GM_RXO_OK_HI },
3260 { "tx_broadcast", GM_TXF_BC_OK },
3261 { "rx_broadcast", GM_RXF_BC_OK },
3262 { "tx_multicast", GM_TXF_MC_OK },
3263 { "rx_multicast", GM_RXF_MC_OK },
3264 { "tx_unicast", GM_TXF_UC_OK },
3265 { "rx_unicast", GM_RXF_UC_OK },
3266 { "tx_mac_pause", GM_TXF_MPAUSE },
3267 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3268 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3269 { "late_collision",GM_TXF_LAT_COL },
3270 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3271 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3272 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3273
d2604540 3274 { "rx_short", GM_RXF_SHT },
cd28ab6a 3275 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3276 { "rx_64_byte_packets", GM_RXF_64B },
3277 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3278 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3279 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3280 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3281 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3282 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3283 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3284 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3285 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3286 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3287
3288 { "tx_64_byte_packets", GM_TXF_64B },
3289 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3290 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3291 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3292 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3293 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3294 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3295 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3296};
3297
cd28ab6a
SH		 3298static u32 sky2_get_rx_csum(struct net_device *dev)
3299{
3300 struct sky2_port *sky2 = netdev_priv(dev);
3301
3302 return sky2->rx_csum;
3303}
3304
3305static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3306{
3307 struct sky2_port *sky2 = netdev_priv(dev);
3308
3309 sky2->rx_csum = data;
793b883e 3310
cd28ab6a
SH		 3311 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3312 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3313
3314 return 0;
3315}
3316
3317static u32 sky2_get_msglevel(struct net_device *netdev)
3318{
3319 struct sky2_port *sky2 = netdev_priv(netdev);
3320 return sky2->msg_enable;
3321}
3322
9a7ae0a9
SH		 3323static int sky2_nway_reset(struct net_device *dev)
3324{
3325 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3326
16ad91e1 3327 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3328 return -EINVAL;
3329
1b537565 3330 sky2_phy_reinit(sky2);
d1b139c0 3331 sky2_set_multicast(dev);
9a7ae0a9
SH		 3332
3333 return 0;
3334}
3335
793b883e 3336static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3337{
3338 struct sky2_hw *hw = sky2->hw;
3339 unsigned port = sky2->port;
3340 int i;
3341
3342 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3343 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3344 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3345 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3346
793b883e 3347 for (i = 2; i < count; i++)
cd28ab6a
SH		 3348 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3349}
3350
cd28ab6a
SH		 3351static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3352{
3353 struct sky2_port *sky2 = netdev_priv(netdev);
3354 sky2->msg_enable = value;
3355}
3356
b9f2c044 3357static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3358{
b9f2c044
JG		 3359 switch (sset) {
3360 case ETH_SS_STATS:
3361 return ARRAY_SIZE(sky2_stats);
3362 default:
3363 return -EOPNOTSUPP;
3364 }
cd28ab6a
SH		 3365}
3366
3367static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3368 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3369{
3370 struct sky2_port *sky2 = netdev_priv(dev);
3371
793b883e 3372 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3373}
3374
793b883e 3375static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3376{
3377 int i;
3378
3379 switch (stringset) {
3380 case ETH_SS_STATS:
3381 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3382 memcpy(data + i * ETH_GSTRING_LEN,
3383 sky2_stats[i].name, ETH_GSTRING_LEN);
3384 break;
3385 }
3386}
3387
cd28ab6a
SH		 3388static int sky2_set_mac_address(struct net_device *dev, void *p)
3389{
3390 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3391 struct sky2_hw *hw = sky2->hw;
3392 unsigned port = sky2->port;
3393 const struct sockaddr *addr = p;
cd28ab6a
SH		 3394
3395 if (!is_valid_ether_addr(addr->sa_data))
3396 return -EADDRNOTAVAIL;
3397
cd28ab6a 3398 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3399 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3400 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3401 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3402 dev->dev_addr, ETH_ALEN);
1b537565 3403
a8ab1ec0
SH		 3404 /* virtual address for data */
3405 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3406
3407 /* physical address: used for pause frames */
3408 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3409
3410 return 0;
cd28ab6a
SH		 3411}
3412
a052b52f
SH		 3413static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3414{
3415 u32 bit;
3416
3417 bit = ether_crc(ETH_ALEN, addr) & 63;
3418 filter[bit >> 3] |= 1 << (bit & 7);
3419}
3420
cd28ab6a
SH		 3421static void sky2_set_multicast(struct net_device *dev)
3422{
3423 struct sky2_port *sky2 = netdev_priv(dev);
3424 struct sky2_hw *hw = sky2->hw;
3425 unsigned port = sky2->port;
3426 struct dev_mc_list *list = dev->mc_list;
3427 u16 reg;
3428 u8 filter[8];
a052b52f
SH		 3429 int rx_pause;
3430 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3431
a052b52f 3432 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3433 memset(filter, 0, sizeof(filter));
3434
3435 reg = gma_read16(hw, port, GM_RX_CTRL);
3436 reg |= GM_RXCR_UCF_ENA;
3437
d571b694 3438 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3439 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3440 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3441 memset(filter, 0xff, sizeof(filter));
a052b52f 3442 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3443 reg &= ~GM_RXCR_MCF_ENA;
3444 else {
3445 int i;
3446 reg |= GM_RXCR_MCF_ENA;
3447
a052b52f
SH		 3448 if (rx_pause)
3449 sky2_add_filter(filter, pause_mc_addr);
3450
3451 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3452 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3453 }
3454
cd28ab6a 3455 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3456 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3457 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3458 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3459 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3460 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3461 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3462 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3463
3464 gma_write16(hw, port, GM_RX_CTRL, reg);
3465}
3466
3467/* Can have one global because blinking is controlled by
3468 * ethtool and that is always under RTNL mutex
3469 */
a84d0a3d 3470static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3471{
a84d0a3d
SH		 3472 struct sky2_hw *hw = sky2->hw;
3473 unsigned port = sky2->port;
793b883e 3474
a84d0a3d
SH		 3475 spin_lock_bh(&sky2->phy_lock);
3476 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3477 hw->chip_id == CHIP_ID_YUKON_EX ||
3478 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3479 u16 pg;
793b883e
SH		 3480 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3481 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3482
a84d0a3d
SH		 3483 switch (mode) {
3484 case MO_LED_OFF:
3485 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3486 PHY_M_LEDC_LOS_CTRL(8) |
3487 PHY_M_LEDC_INIT_CTRL(8) |
3488 PHY_M_LEDC_STA1_CTRL(8) |
3489 PHY_M_LEDC_STA0_CTRL(8));
3490 break;
3491 case MO_LED_ON:
3492 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3493 PHY_M_LEDC_LOS_CTRL(9) |
3494 PHY_M_LEDC_INIT_CTRL(9) |
3495 PHY_M_LEDC_STA1_CTRL(9) |
3496 PHY_M_LEDC_STA0_CTRL(9));
3497 break;
3498 case MO_LED_BLINK:
3499 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3500 PHY_M_LEDC_LOS_CTRL(0xa) |
3501 PHY_M_LEDC_INIT_CTRL(0xa) |
3502 PHY_M_LEDC_STA1_CTRL(0xa) |
3503 PHY_M_LEDC_STA0_CTRL(0xa));
3504 break;
3505 case MO_LED_NORM:
3506 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3507 PHY_M_LEDC_LOS_CTRL(1) |
3508 PHY_M_LEDC_INIT_CTRL(8) |
3509 PHY_M_LEDC_STA1_CTRL(7) |
3510 PHY_M_LEDC_STA0_CTRL(7));
3511 }
793b883e 3512
a84d0a3d
SH		 3513 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3514 } else
7d2e3cb7 3515 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3516 PHY_M_LED_MO_DUP(mode) |
3517 PHY_M_LED_MO_10(mode) |
3518 PHY_M_LED_MO_100(mode) |
3519 PHY_M_LED_MO_1000(mode) |
3520 PHY_M_LED_MO_RX(mode) |
3521 PHY_M_LED_MO_TX(mode));
3522
3523 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3524}
3525
3526/* blink LED's for finding board */
3527static int sky2_phys_id(struct net_device *dev, u32 data)
3528{
3529 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3530 unsigned int i;
cd28ab6a 3531
a84d0a3d
SH		 3532 if (data == 0)
3533 data = UINT_MAX;
cd28ab6a 3534
a84d0a3d
SH		 3535 for (i = 0; i < data; i++) {
3536 sky2_led(sky2, MO_LED_ON);
3537 if (msleep_interruptible(500))
3538 break;
3539 sky2_led(sky2, MO_LED_OFF);
3540 if (msleep_interruptible(500))
3541 break;
793b883e 3542 }
a84d0a3d 3543 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3544
3545 return 0;
3546}
3547
3548static void sky2_get_pauseparam(struct net_device *dev,
3549 struct ethtool_pauseparam *ecmd)
3550{
3551 struct sky2_port *sky2 = netdev_priv(dev);
3552
16ad91e1
SH		 3553 switch (sky2->flow_mode) {
3554 case FC_NONE:
3555 ecmd->tx_pause = ecmd->rx_pause = 0;
3556 break;
3557 case FC_TX:
3558 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3559 break;
3560 case FC_RX:
3561 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3562 break;
3563 case FC_BOTH:
3564 ecmd->tx_pause = ecmd->rx_pause = 1;
3565 }
3566
cd28ab6a
SH		 3567 ecmd->autoneg = sky2->autoneg;
3568}
3569
3570static int sky2_set_pauseparam(struct net_device *dev,
3571 struct ethtool_pauseparam *ecmd)
3572{
3573 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3574
3575 sky2->autoneg = ecmd->autoneg;
16ad91e1 3576 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3577
16ad91e1
SH		 3578 if (netif_running(dev))
3579 sky2_phy_reinit(sky2);
cd28ab6a 3580
2eaba1a2 3581 return 0;
cd28ab6a
SH		 3582}
3583
fb17358f
SH		 3584static int sky2_get_coalesce(struct net_device *dev,
3585 struct ethtool_coalesce *ecmd)
3586{
3587 struct sky2_port *sky2 = netdev_priv(dev);
3588 struct sky2_hw *hw = sky2->hw;
3589
3590 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3591 ecmd->tx_coalesce_usecs = 0;
3592 else {
3593 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3594 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3595 }
3596 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3597
3598 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3599 ecmd->rx_coalesce_usecs = 0;
3600 else {
3601 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3602 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3603 }
3604 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3605
3606 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3607 ecmd->rx_coalesce_usecs_irq = 0;
3608 else {
3609 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3610 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3611 }
3612
3613 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3614
3615 return 0;
3616}
3617
3618/* Note: this affect both ports */
3619static int sky2_set_coalesce(struct net_device *dev,
3620 struct ethtool_coalesce *ecmd)
3621{
3622 struct sky2_port *sky2 = netdev_priv(dev);
3623 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3624 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3625
77b3d6a2
SH		 3626 if (ecmd->tx_coalesce_usecs > tmax ||
3627 ecmd->rx_coalesce_usecs > tmax ||
3628 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3629 return -EINVAL;
3630
ff81fbbe 3631 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3632 return -EINVAL;
ff81fbbe 3633 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3634 return -EINVAL;
ff81fbbe 3635 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3636 return -EINVAL;
3637
3638 if (ecmd->tx_coalesce_usecs == 0)
3639 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3640 else {
3641 sky2_write32(hw, STAT_TX_TIMER_INI,
3642 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3643 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3644 }
3645 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3646
3647 if (ecmd->rx_coalesce_usecs == 0)
3648 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3649 else {
3650 sky2_write32(hw, STAT_LEV_TIMER_INI,
3651 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3652 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3653 }
3654 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3655
3656 if (ecmd->rx_coalesce_usecs_irq == 0)
3657 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3658 else {
d28d4870 3659 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3660 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3661 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3662 }
3663 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3664 return 0;
3665}
3666
793b883e
SH		 3667static void sky2_get_ringparam(struct net_device *dev,
3668 struct ethtool_ringparam *ering)
3669{
3670 struct sky2_port *sky2 = netdev_priv(dev);
3671
3672 ering->rx_max_pending = RX_MAX_PENDING;
3673 ering->rx_mini_max_pending = 0;
3674 ering->rx_jumbo_max_pending = 0;
3675 ering->tx_max_pending = TX_RING_SIZE - 1;
3676
3677 ering->rx_pending = sky2->rx_pending;
3678 ering->rx_mini_pending = 0;
3679 ering->rx_jumbo_pending = 0;
3680 ering->tx_pending = sky2->tx_pending;
3681}
3682
3683static int sky2_set_ringparam(struct net_device *dev,
3684 struct ethtool_ringparam *ering)
3685{
3686 struct sky2_port *sky2 = netdev_priv(dev);
3687 int err = 0;
3688
3689 if (ering->rx_pending > RX_MAX_PENDING ||
3690 ering->rx_pending < 8 ||
3691 ering->tx_pending < MAX_SKB_TX_LE ||
3692 ering->tx_pending > TX_RING_SIZE - 1)
3693 return -EINVAL;
3694
3695 if (netif_running(dev))
3696 sky2_down(dev);
3697
3698 sky2->rx_pending = ering->rx_pending;
3699 sky2->tx_pending = ering->tx_pending;
3700
1b537565 3701 if (netif_running(dev)) {
793b883e 3702 err = sky2_up(dev);
1b537565
SH		 3703 if (err)
3704 dev_close(dev);
3705 }
793b883e
SH		 3706
3707 return err;
3708}
3709
793b883e
SH		 3710static int sky2_get_regs_len(struct net_device *dev)
3711{
6e4cbb34 3712 return 0x4000;
793b883e
SH		 3713}
3714
3715/*
3716 * Returns copy of control register region
3ead5db7 3717 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3718 */
3719static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3720 void *p)
3721{
3722 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3723 const void __iomem *io = sky2->hw->regs;
295b54c4 3724 unsigned int b;
793b883e
SH		 3725
3726 regs->version = 1;
793b883e 3727
295b54c4
SH		 3728 for (b = 0; b < 128; b++) {
3729 /* This complicated switch statement is to make sure and
3730 * only access regions that are unreserved.
3731 * Some blocks are only valid on dual port cards.
3732 * and block 3 has some special diagnostic registers that
3733 * are poison.
3734 */
3735 switch (b) {
3736 case 3:
3737 /* skip diagnostic ram region */
3738 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3739 break;
3ead5db7 3740
295b54c4
SH		 3741 /* dual port cards only */
3742 case 5: /* Tx Arbiter 2 */
3743 case 9: /* RX2 */
3744 case 14 ... 15: /* TX2 */
3745 case 17: case 19: /* Ram Buffer 2 */
3746 case 22 ... 23: /* Tx Ram Buffer 2 */
3747 case 25: /* Rx MAC Fifo 1 */
3748 case 27: /* Tx MAC Fifo 2 */
3749 case 31: /* GPHY 2 */
3750 case 40 ... 47: /* Pattern Ram 2 */
3751 case 52: case 54: /* TCP Segmentation 2 */
3752 case 112 ... 116: /* GMAC 2 */
3753 if (sky2->hw->ports == 1)
3754 goto reserved;
3755 /* fall through */
3756 case 0: /* Control */
3757 case 2: /* Mac address */
3758 case 4: /* Tx Arbiter 1 */
3759 case 7: /* PCI express reg */
3760 case 8: /* RX1 */
3761 case 12 ... 13: /* TX1 */
3762 case 16: case 18:/* Rx Ram Buffer 1 */
3763 case 20 ... 21: /* Tx Ram Buffer 1 */
3764 case 24: /* Rx MAC Fifo 1 */
3765 case 26: /* Tx MAC Fifo 1 */
3766 case 28 ... 29: /* Descriptor and status unit */
3767 case 30: /* GPHY 1*/
3768 case 32 ... 39: /* Pattern Ram 1 */
3769 case 48: case 50: /* TCP Segmentation 1 */
3770 case 56 ... 60: /* PCI space */
3771 case 80 ... 84: /* GMAC 1 */
3772 memcpy_fromio(p, io, 128);
3773 break;
3774 default:
3775reserved:
3776 memset(p, 0, 128);
3777 }
3ead5db7 3778
295b54c4
SH		 3779 p += 128;
3780 io += 128;
3781 }
793b883e 3782}
cd28ab6a 3783
b628ed98
SH		 3784/* In order to do Jumbo packets on these chips, need to turn off the
3785 * transmit store/forward. Therefore checksum offload won't work.
3786 */
3787static int no_tx_offload(struct net_device *dev)
3788{
3789 const struct sky2_port *sky2 = netdev_priv(dev);
3790 const struct sky2_hw *hw = sky2->hw;
3791
69161611 3792 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3793}
3794
3795static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3796{
3797 if (data && no_tx_offload(dev))
3798 return -EINVAL;
3799
3800 return ethtool_op_set_tx_csum(dev, data);
3801}
3802
3803
3804static int sky2_set_tso(struct net_device *dev, u32 data)
3805{
3806 if (data && no_tx_offload(dev))
3807 return -EINVAL;
3808
3809 return ethtool_op_set_tso(dev, data);
3810}
3811
f4331a6d
SH		 3812static int sky2_get_eeprom_len(struct net_device *dev)
3813{
3814 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3815 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3816 u16 reg2;
3817
b32f40c4 3818 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3819 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3820}
3821
b32f40c4 3822static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
f4331a6d 3823{
167f53d0 3824 u32 val;
f4331a6d 3825
b32f40c4 3826 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
167f53d0
SH		 3827
3828 do {
b32f40c4 3829 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0
SH		 3830 } while (!(offset & PCI_VPD_ADDR_F));
3831
b32f40c4 3832 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
167f53d0 3833 return val;
f4331a6d
SH		 3834}
3835
b32f40c4 3836static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
f4331a6d 3837{
b32f40c4
SH		 3838 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3839 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
f4331a6d 3840 do {
b32f40c4 3841 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0 3842 } while (offset & PCI_VPD_ADDR_F);
f4331a6d
SH		 3843}
3844
3845static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3846 u8 *data)
3847{
3848 struct sky2_port *sky2 = netdev_priv(dev);
3849 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3850 int length = eeprom->len;
3851 u16 offset = eeprom->offset;
3852
3853 if (!cap)
3854 return -EINVAL;
3855
3856 eeprom->magic = SKY2_EEPROM_MAGIC;
3857
3858 while (length > 0) {
b32f40c4 3859 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3860 int n = min_t(int, length, sizeof(val));
3861
3862 memcpy(data, &val, n);
3863 length -= n;
3864 data += n;
3865 offset += n;
3866 }
3867 return 0;
3868}
3869
3870static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3871 u8 *data)
3872{
3873 struct sky2_port *sky2 = netdev_priv(dev);
3874 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3875 int length = eeprom->len;
3876 u16 offset = eeprom->offset;
3877
3878 if (!cap)
3879 return -EINVAL;
3880
3881 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3882 return -EINVAL;
3883
3884 while (length > 0) {
3885 u32 val;
3886 int n = min_t(int, length, sizeof(val));
3887
3888 if (n < sizeof(val))
b32f40c4 3889 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3890 memcpy(&val, data, n);
3891
b32f40c4 3892 sky2_vpd_write(sky2->hw, cap, offset, val);
f4331a6d
SH		 3893
3894 length -= n;
3895 data += n;
3896 offset += n;
3897 }
3898 return 0;
3899}
3900
3901
7282d491 3902static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3903 .get_settings = sky2_get_settings,
3904 .set_settings = sky2_set_settings,
3905 .get_drvinfo = sky2_get_drvinfo,
3906 .get_wol = sky2_get_wol,
3907 .set_wol = sky2_set_wol,
3908 .get_msglevel = sky2_get_msglevel,
3909 .set_msglevel = sky2_set_msglevel,
3910 .nway_reset = sky2_nway_reset,
3911 .get_regs_len = sky2_get_regs_len,
3912 .get_regs = sky2_get_regs,
3913 .get_link = ethtool_op_get_link,
3914 .get_eeprom_len = sky2_get_eeprom_len,
3915 .get_eeprom = sky2_get_eeprom,
3916 .set_eeprom = sky2_set_eeprom,
f4331a6d 3917 .set_sg = ethtool_op_set_sg,
f4331a6d 3918 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3919 .set_tso = sky2_set_tso,
3920 .get_rx_csum = sky2_get_rx_csum,
3921 .set_rx_csum = sky2_set_rx_csum,
3922 .get_strings = sky2_get_strings,
3923 .get_coalesce = sky2_get_coalesce,
3924 .set_coalesce = sky2_set_coalesce,
3925 .get_ringparam = sky2_get_ringparam,
3926 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3927 .get_pauseparam = sky2_get_pauseparam,
3928 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3929 .phys_id = sky2_phys_id,
b9f2c044 3930 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3931 .get_ethtool_stats = sky2_get_ethtool_stats,
3932};
3933
3cf26753
SH		 3934#ifdef CONFIG_SKY2_DEBUG
3935
3936static struct dentry *sky2_debug;
3937
3938static int sky2_debug_show(struct seq_file *seq, void *v)
3939{
3940 struct net_device *dev = seq->private;
3941 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3942 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3943 unsigned port = sky2->port;
3944 unsigned idx, last;
3945 int sop;
3946
3947 if (!netif_running(dev))
3948 return -ENETDOWN;
3949
3950 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3951 sky2_read32(hw, B0_ISRC),
3952 sky2_read32(hw, B0_IMSK),
3953 sky2_read32(hw, B0_Y2_SP_ICR));
3954
bea3348e 3955 napi_disable(&hw->napi);
3cf26753
SH		 3956 last = sky2_read16(hw, STAT_PUT_IDX);
3957
3958 if (hw->st_idx == last)
3959 seq_puts(seq, "Status ring (empty)\n");
3960 else {
3961 seq_puts(seq, "Status ring\n");
3962 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3963 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3964 const struct sky2_status_le *le = hw->st_le + idx;
3965 seq_printf(seq, "[%d] %#x %d %#x\n",
3966 idx, le->opcode, le->length, le->status);
3967 }
3968 seq_puts(seq, "\n");
3969 }
3970
3971 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3972 sky2->tx_cons, sky2->tx_prod,
3973 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3974 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3975
3976 /* Dump contents of tx ring */
3977 sop = 1;
3978 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3979 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3980 const struct sky2_tx_le *le = sky2->tx_le + idx;
3981 u32 a = le32_to_cpu(le->addr);
3982
3983 if (sop)
3984 seq_printf(seq, "%u:", idx);
3985 sop = 0;
3986
3987 switch(le->opcode & ~HW_OWNER) {
3988 case OP_ADDR64:
3989 seq_printf(seq, " %#x:", a);
3990 break;
3991 case OP_LRGLEN:
3992 seq_printf(seq, " mtu=%d", a);
3993 break;
3994 case OP_VLAN:
3995 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3996 break;
3997 case OP_TCPLISW:
3998 seq_printf(seq, " csum=%#x", a);
3999 break;
4000 case OP_LARGESEND:
4001 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4002 break;
4003 case OP_PACKET:
4004 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4005 break;
4006 case OP_BUFFER:
4007 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4008 break;
4009 default:
4010 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4011 a, le16_to_cpu(le->length));
4012 }
4013
4014 if (le->ctrl & EOP) {
4015 seq_putc(seq, '\n');
4016 sop = 1;
4017 }
4018 }
4019
4020 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4021 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4022 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4023 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4024
d1d08d12 4025 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4026 napi_enable(&hw->napi);
3cf26753
SH		 4027 return 0;
4028}
4029
4030static int sky2_debug_open(struct inode *inode, struct file *file)
4031{
4032 return single_open(file, sky2_debug_show, inode->i_private);
4033}
4034
4035static const struct file_operations sky2_debug_fops = {
4036 .owner = THIS_MODULE,
4037 .open = sky2_debug_open,
4038 .read = seq_read,
4039 .llseek = seq_lseek,
4040 .release = single_release,
4041};
4042
4043/*
4044 * Use network device events to create/remove/rename
4045 * debugfs file entries
4046 */
4047static int sky2_device_event(struct notifier_block *unused,
4048 unsigned long event, void *ptr)
4049{
4050 struct net_device *dev = ptr;
5b296bc9 4051 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4052
5b296bc9
SH		 4053 if (dev->open != sky2_up || !sky2_debug)
4054 return NOTIFY_DONE;
3cf26753 4055
5b296bc9
SH		 4056 switch(event) {
4057 case NETDEV_CHANGENAME:
4058 if (sky2->debugfs) {
4059 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4060 sky2_debug, dev->name);
4061 }
4062 break;
3cf26753 4063
5b296bc9
SH		 4064 case NETDEV_GOING_DOWN:
4065 if (sky2->debugfs) {
4066 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4067 dev->name);
4068 debugfs_remove(sky2->debugfs);
4069 sky2->debugfs = NULL;
3cf26753 4070 }
5b296bc9
SH		 4071 break;
4072
4073 case NETDEV_UP:
4074 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4075 sky2_debug, dev,
4076 &sky2_debug_fops);
4077 if (IS_ERR(sky2->debugfs))
4078 sky2->debugfs = NULL;
3cf26753
SH		 4079 }
4080
4081 return NOTIFY_DONE;
4082}
4083
4084static struct notifier_block sky2_notifier = {
4085 .notifier_call = sky2_device_event,
4086};
4087
4088
4089static __init void sky2_debug_init(void)
4090{
4091 struct dentry *ent;
4092
4093 ent = debugfs_create_dir("sky2", NULL);
4094 if (!ent || IS_ERR(ent))
4095 return;
4096
4097 sky2_debug = ent;
4098 register_netdevice_notifier(&sky2_notifier);
4099}
4100
4101static __exit void sky2_debug_cleanup(void)
4102{
4103 if (sky2_debug) {
4104 unregister_netdevice_notifier(&sky2_notifier);
4105 debugfs_remove(sky2_debug);
4106 sky2_debug = NULL;
4107 }
4108}
4109
4110#else
4111#define sky2_debug_init()
4112#define sky2_debug_cleanup()
4113#endif
4114
4115
cd28ab6a
SH		 4116/* Initialize network device */
4117static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4118 unsigned port,
be63a21c 4119 int highmem, int wol)
cd28ab6a
SH		 4120{
4121 struct sky2_port *sky2;
4122 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4123
4124 if (!dev) {
898eb71c 4125 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4126 return NULL;
4127 }
4128
cd28ab6a 4129 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4130 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 4131 dev->open = sky2_up;
4132 dev->stop = sky2_down;
ef743d33 4133 dev->do_ioctl = sky2_ioctl;
cd28ab6a 4134 dev->hard_start_xmit = sky2_xmit_frame;
cd28ab6a
SH		 4135 dev->set_multicast_list = sky2_set_multicast;
4136 dev->set_mac_address = sky2_set_mac_address;
4137 dev->change_mtu = sky2_change_mtu;
4138 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4139 dev->tx_timeout = sky2_tx_timeout;
4140 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 4141#ifdef CONFIG_NET_POLL_CONTROLLER
a5e68c02
SH		 4142 if (port == 0)
4143 dev->poll_controller = sky2_netpoll;
cd28ab6a 4144#endif
cd28ab6a
SH		 4145
4146 sky2 = netdev_priv(dev);
4147 sky2->netdev = dev;
4148 sky2->hw = hw;
4149 sky2->msg_enable = netif_msg_init(debug, default_msg);
4150
cd28ab6a
SH		 4151 /* Auto speed and flow control */
4152 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4153 sky2->flow_mode = FC_BOTH;
4154
cd28ab6a
SH		 4155 sky2->duplex = -1;
4156 sky2->speed = -1;
4157 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4158 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4159 sky2->wol = wol;
75d070c5 4160
e07b1aa8 4161 spin_lock_init(&sky2->phy_lock);
793b883e 4162 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4163 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4164
4165 hw->dev[port] = dev;
4166
4167 sky2->port = port;
4168
4a50a876 4169 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4170 if (highmem)
4171 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4172
d1f13708 4173#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4174 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4175 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4176 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4177 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4178 dev->vlan_rx_register = sky2_vlan_rx_register;
4179 }
d1f13708
SH		 4180#endif
4181
cd28ab6a 4182 /* read the mac address */
793b883e 4183 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4184 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4185
cd28ab6a
SH		 4186 return dev;
4187}
4188
28bd181a 4189static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4190{
4191 const struct sky2_port *sky2 = netdev_priv(dev);
0795af57 4192 DECLARE_MAC_BUF(mac);
cd28ab6a
SH		 4193
4194 if (netif_msg_probe(sky2))
0795af57
JP		 4195 printk(KERN_INFO PFX "%s: addr %s\n",
4196 dev->name, print_mac(mac, dev->dev_addr));
cd28ab6a
SH		 4197}
4198
fb2690a9 4199/* Handle software interrupt used during MSI test */
7d12e780 4200static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4201{
4202 struct sky2_hw *hw = dev_id;
4203 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4204
4205 if (status == 0)
4206 return IRQ_NONE;
4207
4208 if (status & Y2_IS_IRQ_SW) {
ea76e635 4209 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4210 wake_up(&hw->msi_wait);
4211 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4212 }
4213 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4214
4215 return IRQ_HANDLED;
4216}
4217
4218/* Test interrupt path by forcing a a software IRQ */
4219static int __devinit sky2_test_msi(struct sky2_hw *hw)
4220{
4221 struct pci_dev *pdev = hw->pdev;
4222 int err;
4223
bb507fe1
SH		 4224 init_waitqueue_head (&hw->msi_wait);
4225
fb2690a9
SH		 4226 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4227
b0a20ded 4228 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4229 if (err) {
b02a9258 4230 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4231 return err;
4232 }
4233
fb2690a9 4234 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4235 sky2_read8(hw, B0_CTST);
fb2690a9 4236
ea76e635 4237 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4238
ea76e635 4239 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4240 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4241 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4242 "switching to INTx mode.\n");
fb2690a9
SH		 4243
4244 err = -EOPNOTSUPP;
4245 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4246 }
4247
4248 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4249 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4250
4251 free_irq(pdev->irq, hw);
4252
4253 return err;
4254}
4255
be63a21c
SH		 4256static int __devinit pci_wake_enabled(struct pci_dev *dev)
4257{
4258 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4259 u16 value;
4260
4261 if (!pm)
4262 return 0;
4263 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4264 return 0;
4265 return value & PCI_PM_CTRL_PME_ENABLE;
4266}
4267
cd28ab6a
SH		 4268static int __devinit sky2_probe(struct pci_dev *pdev,
4269 const struct pci_device_id *ent)
4270{
7f60c64b 4271 struct net_device *dev;
cd28ab6a 4272 struct sky2_hw *hw;
be63a21c 4273 int err, using_dac = 0, wol_default;
cd28ab6a 4274
793b883e
SH		 4275 err = pci_enable_device(pdev);
4276 if (err) {
b02a9258 4277 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4278 goto err_out;
4279 }
4280
793b883e
SH		 4281 err = pci_request_regions(pdev, DRV_NAME);
4282 if (err) {
b02a9258 4283 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4284 goto err_out_disable;
cd28ab6a
SH		 4285 }
4286
4287 pci_set_master(pdev);
4288
d1f3d4dd
SH		 4289 if (sizeof(dma_addr_t) > sizeof(u32) &&
4290 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4291 using_dac = 1;
4292 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4293 if (err < 0) {
b02a9258
SH		 4294 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4295 "for consistent allocations\n");
d1f3d4dd
SH		 4296 goto err_out_free_regions;
4297 }
d1f3d4dd 4298 } else {
cd28ab6a
SH		 4299 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4300 if (err) {
b02a9258 4301 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4302 goto err_out_free_regions;
4303 }
4304 }
d1f3d4dd 4305
be63a21c
SH		 4306 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4307
cd28ab6a 4308 err = -ENOMEM;
6aad85d6 4309 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4310 if (!hw) {
b02a9258 4311 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4312 goto err_out_free_regions;
4313 }
4314
cd28ab6a 4315 hw->pdev = pdev;
cd28ab6a
SH		 4316
4317 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4318 if (!hw->regs) {
b02a9258 4319 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4320 goto err_out_free_hw;
4321 }
4322
56a645cc 4323#ifdef __BIG_ENDIAN
f65b138c
SH		 4324 /* The sk98lin vendor driver uses hardware byte swapping but
4325 * this driver uses software swapping.
4326 */
56a645cc
SH		 4327 {
4328 u32 reg;
b32f40c4 4329 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4330 reg &= ~PCI_REV_DESC;
b32f40c4 4331 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
56a645cc
SH		 4332 }
4333#endif
4334
08c06d8a 4335 /* ring for status responses */
167f53d0 4336 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4337 if (!hw->st_le)
4338 goto err_out_iounmap;
4339
e3173832 4340 err = sky2_init(hw);
cd28ab6a 4341 if (err)
793b883e 4342 goto err_out_iounmap;
cd28ab6a 4343
b02a9258 4344 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4345 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4346 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4347 hw->chip_id, hw->chip_rev);
cd28ab6a 4348
e3173832
SH		 4349 sky2_reset(hw);
4350
be63a21c 4351 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4352 if (!dev) {
4353 err = -ENOMEM;
cd28ab6a 4354 goto err_out_free_pci;
7f60c64b 4355 }
cd28ab6a 4356
9fa1b1f3
SH		 4357 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4358 err = sky2_test_msi(hw);
4359 if (err == -EOPNOTSUPP)
4360 pci_disable_msi(pdev);
4361 else if (err)
4362 goto err_out_free_netdev;
4363 }
4364
793b883e
SH		 4365 err = register_netdev(dev);
4366 if (err) {
b02a9258 4367 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4368 goto err_out_free_netdev;
4369 }
4370
6de16237
SH		 4371 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4372
ea76e635
SH		 4373 err = request_irq(pdev->irq, sky2_intr,
4374 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4375 dev->name, hw);
9fa1b1f3 4376 if (err) {
b02a9258 4377 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4378 goto err_out_unregister;
4379 }
4380 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4381 napi_enable(&hw->napi);
9fa1b1f3 4382
cd28ab6a
SH		 4383 sky2_show_addr(dev);
4384
7f60c64b 4385 if (hw->ports > 1) {
4386 struct net_device *dev1;
4387
be63a21c 4388 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4389 if (!dev1)
4390 dev_warn(&pdev->dev, "allocation for second device failed\n");
4391 else if ((err = register_netdev(dev1))) {
4392 dev_warn(&pdev->dev,
4393 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4394 hw->dev[1] = NULL;
4395 free_netdev(dev1);
b02a9258
SH		 4396 } else
4397 sky2_show_addr(dev1);
cd28ab6a
SH		 4398 }
4399
32c2c300 4400 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4401 INIT_WORK(&hw->restart_work, sky2_restart);
4402
793b883e
SH		 4403 pci_set_drvdata(pdev, hw);
4404
cd28ab6a
SH		 4405 return 0;
4406
793b883e 4407err_out_unregister:
ea76e635 4408 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4409 pci_disable_msi(pdev);
793b883e 4410 unregister_netdev(dev);
cd28ab6a
SH		 4411err_out_free_netdev:
4412 free_netdev(dev);
cd28ab6a 4413err_out_free_pci:
793b883e 4414 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4415 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4416err_out_iounmap:
4417 iounmap(hw->regs);
4418err_out_free_hw:
4419 kfree(hw);
4420err_out_free_regions:
4421 pci_release_regions(pdev);
44a1d2e5 4422err_out_disable:
cd28ab6a 4423 pci_disable_device(pdev);
cd28ab6a 4424err_out:
549a68c3 4425 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4426 return err;
4427}
4428
4429static void __devexit sky2_remove(struct pci_dev *pdev)
4430{
793b883e 4431 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4432 int i;
cd28ab6a 4433
793b883e 4434 if (!hw)
cd28ab6a
SH		 4435 return;
4436
32c2c300 4437 del_timer_sync(&hw->watchdog_timer);
6de16237 4438 cancel_work_sync(&hw->restart_work);
d27ed387 4439
b877fe28 4440 for (i = hw->ports-1; i >= 0; --i)
6de16237 4441 unregister_netdev(hw->dev[i]);
81906791 4442
d27ed387 4443 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4444
ae306cca
SH		 4445 sky2_power_aux(hw);
4446
cd28ab6a 4447 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4448 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4449 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4450
4451 free_irq(pdev->irq, hw);
ea76e635 4452 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4453 pci_disable_msi(pdev);
793b883e 4454 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4455 pci_release_regions(pdev);
4456 pci_disable_device(pdev);
793b883e 4457
b877fe28 4458 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4459 free_netdev(hw->dev[i]);
4460
cd28ab6a
SH		 4461 iounmap(hw->regs);
4462 kfree(hw);
5afa0a9c 4463
cd28ab6a
SH		 4464 pci_set_drvdata(pdev, NULL);
4465}
4466
4467#ifdef CONFIG_PM
4468static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4469{
793b883e 4470 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4471 int i, wol = 0;
cd28ab6a 4472
549a68c3
SH		 4473 if (!hw)
4474 return 0;
4475
063a0b38
SH		 4476 del_timer_sync(&hw->watchdog_timer);
4477 cancel_work_sync(&hw->restart_work);
4478
f05267e7 4479 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4480 struct net_device *dev = hw->dev[i];
e3173832 4481 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4482
063a0b38 4483 netif_device_detach(dev);
e3173832 4484 if (netif_running(dev))
5afa0a9c 4485 sky2_down(dev);
e3173832
SH		 4486
4487 if (sky2->wol)
4488 sky2_wol_init(sky2);
4489
4490 wol |= sky2->wol;
cd28ab6a
SH		 4491 }
4492
8ab8fca2 4493 sky2_write32(hw, B0_IMSK, 0);
6de16237 4494 napi_disable(&hw->napi);
ae306cca 4495 sky2_power_aux(hw);
e3173832 4496
d374c1c1 4497 pci_save_state(pdev);
e3173832 4498 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
a068c0ad 4499 sky2_power_state(hw, pci_choose_state(pdev, state));
ae306cca 4500
2ccc99b7 4501 return 0;
cd28ab6a
SH		 4502}
4503
4504static int sky2_resume(struct pci_dev *pdev)
4505{
793b883e 4506 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4507 int i, err;
cd28ab6a 4508
549a68c3
SH		 4509 if (!hw)
4510 return 0;
4511
a068c0ad 4512 sky2_power_state(hw, PCI_D0);
ae306cca
SH		 4513
4514 err = pci_restore_state(pdev);
4515 if (err)
4516 goto out;
4517
cd28ab6a 4518 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4519
4520 /* Re-enable all clocks */
05745c4a
SH		 4521 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4522 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4523 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4524 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4525
e3173832 4526 sky2_reset(hw);
8ab8fca2 4527 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4528 napi_enable(&hw->napi);
8ab8fca2 4529
f05267e7 4530 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4531 struct net_device *dev = hw->dev[i];
063a0b38
SH		 4532
4533 netif_device_attach(dev);
6a5706b9 4534 if (netif_running(dev)) {
08c06d8a
SH		 4535 err = sky2_up(dev);
4536 if (err) {
4537 printk(KERN_ERR PFX "%s: could not up: %d\n",
4538 dev->name, err);
68c28898 4539 rtnl_lock();
08c06d8a 4540 dev_close(dev);
68c28898 4541 rtnl_unlock();
eb35cf60 4542 goto out;
5afa0a9c 4543 }
cd28ab6a
SH		 4544 }
4545 }
eb35cf60 4546
ae306cca 4547 return 0;
08c06d8a 4548out:
b02a9258 4549 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4550 pci_disable_device(pdev);
08c06d8a 4551 return err;
cd28ab6a
SH		 4552}
4553#endif
4554
e3173832
SH		 4555static void sky2_shutdown(struct pci_dev *pdev)
4556{
4557 struct sky2_hw *hw = pci_get_drvdata(pdev);
4558 int i, wol = 0;
4559
549a68c3
SH		 4560 if (!hw)
4561 return;
4562
5c0d6b34 4563 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4564
4565 for (i = 0; i < hw->ports; i++) {
4566 struct net_device *dev = hw->dev[i];
4567 struct sky2_port *sky2 = netdev_priv(dev);
4568
4569 if (sky2->wol) {
4570 wol = 1;
4571 sky2_wol_init(sky2);
4572 }
4573 }
4574
4575 if (wol)
4576 sky2_power_aux(hw);
4577
4578 pci_enable_wake(pdev, PCI_D3hot, wol);
4579 pci_enable_wake(pdev, PCI_D3cold, wol);
4580
4581 pci_disable_device(pdev);
a068c0ad 4582 sky2_power_state(hw, PCI_D3hot);
e3173832
SH		 4583}
4584
cd28ab6a 4585static struct pci_driver sky2_driver = {
793b883e
SH		 4586 .name = DRV_NAME,
4587 .id_table = sky2_id_table,
4588 .probe = sky2_probe,
4589 .remove = __devexit_p(sky2_remove),
cd28ab6a 4590#ifdef CONFIG_PM
793b883e
SH		 4591 .suspend = sky2_suspend,
4592 .resume = sky2_resume,
cd28ab6a 4593#endif
e3173832 4594 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4595};
4596
4597static int __init sky2_init_module(void)
4598{
3cf26753 4599 sky2_debug_init();
50241c4c 4600 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4601}
4602
4603static void __exit sky2_cleanup_module(void)
4604{
4605 pci_unregister_driver(&sky2_driver);
3cf26753 4606 sky2_debug_cleanup();
cd28ab6a
SH		 4607}
4608
4609module_init(sky2_init_module);
4610module_exit(sky2_cleanup_module);
4611
4612MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4613MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4614MODULE_LICENSE("GPL");
5f4f9dc1 4615MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree