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[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
cd28ab6a
SH		 27 * TOTEST
28 * - speed setting
724bca3c 29 * - suspend/resume
cd28ab6a
SH		 30 */
31
32#include <linux/config.h>
793b883e 33#include <linux/crc32.h>
cd28ab6a
SH		 34#include <linux/kernel.h>
35#include <linux/version.h>
36#include <linux/module.h>
37#include <linux/netdevice.h>
d0bbccfa 38#include <linux/dma-mapping.h>
cd28ab6a
SH		 39#include <linux/etherdevice.h>
40#include <linux/ethtool.h>
41#include <linux/pci.h>
42#include <linux/ip.h>
43#include <linux/tcp.h>
44#include <linux/in.h>
45#include <linux/delay.h>
91c86df5 46#include <linux/workqueue.h>
d1f13708 47#include <linux/if_vlan.h>
ef743d33 48#include <linux/mii.h>
cd28ab6a
SH		 49
50#include <asm/irq.h>
51
d1f13708
SH		 52#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
53#define SKY2_VLAN_TAG_USED 1
54#endif
55
cd28ab6a
SH		 56#include "sky2.h"
57
58#define DRV_NAME "sky2"
5f4f9dc1 59#define DRV_VERSION "0.9"
cd28ab6a
SH		 60#define PFX DRV_NAME " "
61
62/*
63 * The Yukon II chipset takes 64 bit command blocks (called list elements)
64 * that are organized into three (receive, transmit, status) different rings
65 * similar to Tigon3. A transmit can require several elements;
66 * a receive requires one (or two if using 64 bit dma).
67 */
68
cd28ab6a 69#define is_ec_a1(hw) \
21437643
SH		 70 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
71 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
cd28ab6a 72
13210ce5 73#define RX_LE_SIZE 512
cd28ab6a 74#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 75#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 76#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 77
78#define TX_RING_SIZE 512
79#define TX_DEF_PENDING (TX_RING_SIZE - 1)
80#define TX_MIN_PENDING 64
81#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
cd28ab6a 82
793b883e 83#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 84#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
85#define ETH_JUMBO_MTU 9000
86#define TX_WATCHDOG (5 * HZ)
87#define NAPI_WEIGHT 64
88#define PHY_RETRIES 1000
89
90static const u32 default_msg =
793b883e
SH		 91 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
92 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
93 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
cd28ab6a 94
793b883e 95static int debug = -1; /* defaults above */
cd28ab6a
SH		 96module_param(debug, int, 0);
97MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
98
bdb5c58e
SH		 99static int copybreak __read_mostly = 256;
100module_param(copybreak, int, 0);
101MODULE_PARM_DESC(copybreak, "Receive copy threshold");
102
cd28ab6a 103static const struct pci_device_id sky2_id_table[] = {
793b883e 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a
SH		 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 123 { 0 }
124};
793b883e 125
cd28ab6a
SH		 126MODULE_DEVICE_TABLE(pci, sky2_id_table);
127
128/* Avoid conditionals by using array */
129static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
130static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
131
92f965e8
SH		 132/* This driver supports yukon2 chipset only */
133static const char *yukon2_name[] = {
134 "XL", /* 0xb3 */
135 "EC Ultra", /* 0xb4 */
136 "UNKNOWN", /* 0xb5 */
137 "EC", /* 0xb6 */
138 "FE", /* 0xb7 */
793b883e
SH		 139};
140
793b883e 141/* Access to external PHY */
ef743d33 142static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 143{
144 int i;
145
146 gma_write16(hw, port, GM_SMI_DATA, val);
147 gma_write16(hw, port, GM_SMI_CTRL,
148 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
149
150 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 151 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 152 return 0;
793b883e 153 udelay(1);
cd28ab6a 154 }
ef743d33 155
793b883e 156 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 157 return -ETIMEDOUT;
cd28ab6a
SH		 158}
159
ef743d33 160static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 161{
162 int i;
163
793b883e 164 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 165 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
166
167 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 168 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
169 *val = gma_read16(hw, port, GM_SMI_DATA);
170 return 0;
171 }
172
793b883e 173 udelay(1);
cd28ab6a
SH		 174 }
175
ef743d33
SH		 176 return -ETIMEDOUT;
177}
178
179static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
180{
181 u16 v;
182
183 if (__gm_phy_read(hw, port, reg, &v) != 0)
184 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
185 return v;
cd28ab6a
SH		 186}
187
5afa0a9c
SH		 188static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
189{
190 u16 power_control;
191 u32 reg1;
192 int vaux;
193 int ret = 0;
194
195 pr_debug("sky2_set_power_state %d\n", state);
196 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
197
198 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
199 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
200 (power_control & PCI_PM_CAP_PME_D3cold);
201
202 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
203
204 power_control |= PCI_PM_CTRL_PME_STATUS;
205 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
206
207 switch (state) {
208 case PCI_D0:
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw, B0_POWER_CTRL,
211 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
212
213 /* disable Core Clock Division, */
214 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
215
216 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
217 /* enable bits are inverted */
218 sky2_write8(hw, B2_Y2_CLK_GATE,
219 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
220 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
221 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
222 else
223 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
224
225 /* Turn off phy power saving */
226 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
227 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
228
d571b694 229 /* looks like this XL is back asswards .. */
5afa0a9c
SH		 230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
231 reg1 |= PCI_Y2_PHY1_COMA;
232 if (hw->ports > 1)
233 reg1 |= PCI_Y2_PHY2_COMA;
234 }
235 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
236 break;
237
238 case PCI_D3hot:
239 case PCI_D3cold:
240 /* Turn on phy power saving */
241 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
242 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
243 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
244 else
245 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
246 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
247
248 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
249 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
250 else
251 /* enable bits are inverted */
252 sky2_write8(hw, B2_Y2_CLK_GATE,
253 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
254 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
255 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
256
257 /* switch power to VAUX */
258 if (vaux && state != PCI_D3cold)
259 sky2_write8(hw, B0_POWER_CTRL,
260 (PC_VAUX_ENA | PC_VCC_ENA |
261 PC_VAUX_ON | PC_VCC_OFF));
262 break;
263 default:
264 printk(KERN_ERR PFX "Unknown power state %d\n", state);
265 ret = -1;
266 }
267
268 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
269 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
270 return ret;
271}
272
cd28ab6a
SH		 273static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
274{
275 u16 reg;
276
277 /* disable all GMAC IRQ's */
278 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
279 /* disable PHY IRQs */
280 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 281
cd28ab6a
SH		 282 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
283 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
284 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
285 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
286
287 reg = gma_read16(hw, port, GM_RX_CTRL);
288 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
289 gma_write16(hw, port, GM_RX_CTRL, reg);
290}
291
292static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
293{
294 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 295 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 296
793b883e 297 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
cd28ab6a
SH		 298 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
299
300 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 301 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 302 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
303
304 if (hw->chip_id == CHIP_ID_YUKON_EC)
305 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
306 else
307 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
308
309 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
310 }
311
312 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
313 if (hw->copper) {
314 if (hw->chip_id == CHIP_ID_YUKON_FE) {
315 /* enable automatic crossover */
316 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
317 } else {
318 /* disable energy detect */
319 ctrl &= ~PHY_M_PC_EN_DET_MSK;
320
321 /* enable automatic crossover */
322 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
323
324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 hw->chip_id == CHIP_ID_YUKON_XL) {
326 ctrl &= ~PHY_M_PC_DSC_MSK;
327 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
328 }
329 }
330 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
331 } else {
332 /* workaround for deviation #4.88 (CRC errors) */
333 /* disable Automatic Crossover */
334
335 ctrl &= ~PHY_M_PC_MDIX_MSK;
336 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
337
338 if (hw->chip_id == CHIP_ID_YUKON_XL) {
339 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
340 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
341 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
342 ctrl &= ~PHY_M_MAC_MD_MSK;
343 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
345
346 /* select page 1 to access Fiber registers */
347 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
348 }
cd28ab6a
SH		 349 }
350
351 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
352 if (sky2->autoneg == AUTONEG_DISABLE)
353 ctrl &= ~PHY_CT_ANE;
354 else
355 ctrl |= PHY_CT_ANE;
356
357 ctrl |= PHY_CT_RESET;
358 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
359
360 ctrl = 0;
361 ct1000 = 0;
362 adv = PHY_AN_CSMA;
363
364 if (sky2->autoneg == AUTONEG_ENABLE) {
365 if (hw->copper) {
366 if (sky2->advertising & ADVERTISED_1000baseT_Full)
367 ct1000 |= PHY_M_1000C_AFD;
368 if (sky2->advertising & ADVERTISED_1000baseT_Half)
369 ct1000 |= PHY_M_1000C_AHD;
370 if (sky2->advertising & ADVERTISED_100baseT_Full)
371 adv |= PHY_M_AN_100_FD;
372 if (sky2->advertising & ADVERTISED_100baseT_Half)
373 adv |= PHY_M_AN_100_HD;
374 if (sky2->advertising & ADVERTISED_10baseT_Full)
375 adv |= PHY_M_AN_10_FD;
376 if (sky2->advertising & ADVERTISED_10baseT_Half)
377 adv |= PHY_M_AN_10_HD;
793b883e 378 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 379 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
380
381 /* Set Flow-control capabilities */
382 if (sky2->tx_pause && sky2->rx_pause)
793b883e 383 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 384 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 385 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 386 else if (!sky2->rx_pause && sky2->tx_pause)
387 adv |= PHY_AN_PAUSE_ASYM; /* local */
388
389 /* Restart Auto-negotiation */
390 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
391 } else {
392 /* forced speed/duplex settings */
393 ct1000 = PHY_M_1000C_MSE;
394
395 if (sky2->duplex == DUPLEX_FULL)
396 ctrl |= PHY_CT_DUP_MD;
397
398 switch (sky2->speed) {
399 case SPEED_1000:
400 ctrl |= PHY_CT_SP1000;
401 break;
402 case SPEED_100:
403 ctrl |= PHY_CT_SP100;
404 break;
405 }
406
407 ctrl |= PHY_CT_RESET;
408 }
409
410 if (hw->chip_id != CHIP_ID_YUKON_FE)
411 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
412
413 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
414 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
415
416 /* Setup Phy LED's */
417 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
418 ledover = 0;
419
420 switch (hw->chip_id) {
421 case CHIP_ID_YUKON_FE:
422 /* on 88E3082 these bits are at 11..9 (shifted left) */
423 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
424
425 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
426
427 /* delete ACT LED control bits */
428 ctrl &= ~PHY_M_FELP_LED1_MSK;
429 /* change ACT LED control to blink mode */
430 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
431 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
432 break;
433
434 case CHIP_ID_YUKON_XL:
793b883e 435 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 436
437 /* select page 3 to access LED control register */
438 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
439
440 /* set LED Function Control register */
793b883e
SH		 441 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
442 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
443 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
444 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 445
446 /* set Polarity Control register */
447 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 448 (PHY_M_POLC_LS1_P_MIX(4) |
449 PHY_M_POLC_IS0_P_MIX(4) |
450 PHY_M_POLC_LOS_CTRL(2) |
451 PHY_M_POLC_INIT_CTRL(2) |
452 PHY_M_POLC_STA1_CTRL(2) |
453 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 454
455 /* restore page register */
793b883e 456 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 457 break;
458
459 default:
460 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
461 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
462 /* turn off the Rx LED (LED_RX) */
463 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
464 }
465
466 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
467
468 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
469 /* turn on 100 Mbps LED (LED_LINK100) */
470 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
471 }
472
473 if (ledover)
474 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
475
d571b694 476 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 477 if (sky2->autoneg == AUTONEG_ENABLE)
478 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
479 else
480 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
481}
482
483static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
484{
485 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
486 u16 reg;
487 int i;
488 const u8 *addr = hw->dev[port]->dev_addr;
489
42eeea01
SH		 490 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
491 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 492
493 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
494
793b883e 495 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 496 /* WA DEV_472 -- looks like crossed wires on port 2 */
497 /* clear GMAC 1 Control reset */
498 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
499 do {
500 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
501 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
502 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
503 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
504 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
505 }
506
cd28ab6a
SH		 507 if (sky2->autoneg == AUTONEG_DISABLE) {
508 reg = gma_read16(hw, port, GM_GP_CTRL);
509 reg |= GM_GPCR_AU_ALL_DIS;
510 gma_write16(hw, port, GM_GP_CTRL, reg);
511 gma_read16(hw, port, GM_GP_CTRL);
512
cd28ab6a
SH		 513 switch (sky2->speed) {
514 case SPEED_1000:
515 reg |= GM_GPCR_SPEED_1000;
516 /* fallthru */
517 case SPEED_100:
518 reg |= GM_GPCR_SPEED_100;
519 }
520
521 if (sky2->duplex == DUPLEX_FULL)
522 reg |= GM_GPCR_DUP_FULL;
523 } else
524 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
525
526 if (!sky2->tx_pause && !sky2->rx_pause) {
527 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 528 reg |=
529 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
530 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 531 /* disable Rx flow-control */
532 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
533 }
534
535 gma_write16(hw, port, GM_GP_CTRL, reg);
536
793b883e 537 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 538
91c86df5 539 down(&sky2->phy_sema);
cd28ab6a 540 sky2_phy_init(hw, port);
91c86df5 541 up(&sky2->phy_sema);
cd28ab6a
SH		 542
543 /* MIB clear */
544 reg = gma_read16(hw, port, GM_PHY_ADDR);
545 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
546
547 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
793b883e 548 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
cd28ab6a
SH		 549 gma_write16(hw, port, GM_PHY_ADDR, reg);
550
551 /* transmit control */
552 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
553
554 /* receive control reg: unicast + multicast + no FCS */
555 gma_write16(hw, port, GM_RX_CTRL,
793b883e 556 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 557
558 /* transmit flow control */
559 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
560
561 /* transmit parameter */
562 gma_write16(hw, port, GM_TX_PARAM,
563 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
564 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
565 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
566 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
567
568 /* serial mode register */
569 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 570 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 571
6b1a3aef 572 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 573 reg |= GM_SMOD_JUMBO_ENA;
574
575 gma_write16(hw, port, GM_SERIAL_MODE, reg);
576
cd28ab6a
SH		 577 /* virtual address for data */
578 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
579
793b883e
SH		 580 /* physical address: used for pause frames */
581 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
582
583 /* ignore counter overflows */
cd28ab6a
SH		 584 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
585 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
586 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
587
588 /* Configure Rx MAC FIFO */
589 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
793b883e 590 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
d1f13708 591 GMF_RX_CTRL_DEF);
cd28ab6a 592
d571b694 593 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 594 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 595
793b883e
SH		 596 /* Set threshold to 0xa (64 bytes)
597 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 598 */
599 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
600
601 /* Configure Tx MAC FIFO */
602 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
603 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 604
605 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
606 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
607 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
608 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
609 /* set Tx GMAC FIFO Almost Empty Threshold */
610 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
611 /* Disable Store & Forward mode for TX */
612 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
613 }
614 }
615
cd28ab6a
SH		 616}
617
618static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
619{
620 u32 end;
621
622 start /= 8;
623 len /= 8;
624 end = start + len - 1;
793b883e 625
cd28ab6a
SH		 626 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
627 sky2_write32(hw, RB_ADDR(q, RB_START), start);
628 sky2_write32(hw, RB_ADDR(q, RB_END), end);
629 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
630 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
631
632 if (q == Q_R1 || q == Q_R2) {
793b883e
SH		 633 u32 rxup, rxlo;
634
635 rxlo = len/2;
636 rxup = rxlo + len/4;
793b883e 637
cd28ab6a 638 /* Set thresholds on receive queue's */
793b883e
SH		 639 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
640 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
cd28ab6a
SH		 641 } else {
642 /* Enable store & forward on Tx queue's because
643 * Tx FIFO is only 1K on Yukon
644 */
645 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
646 }
647
648 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 649 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 650}
651
cd28ab6a 652/* Setup Bus Memory Interface */
af4ed7e6 653static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 654{
655 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
656 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
657 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 658 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 659}
660
cd28ab6a
SH		 661/* Setup prefetch unit registers. This is the interface between
662 * hardware and driver list elements
663 */
664static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
665 u64 addr, u32 last)
666{
cd28ab6a
SH		 667 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
668 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
669 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
670 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
671 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
672 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 673
674 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 675}
676
793b883e
SH		 677static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
678{
679 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
680
681 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
682 return le;
683}
cd28ab6a
SH		 684
685/*
d571b694 686 * This is a workaround code taken from SysKonnect sk98lin driver
793b883e 687 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
cd28ab6a
SH		 688 */
689static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
690 u16 idx, u16 *last, u16 size)
cd28ab6a 691{
cd28ab6a
SH		 692 if (is_ec_a1(hw) && idx < *last) {
693 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
694
695 if (hwget == 0) {
696 /* Start prefetching again */
793b883e 697 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
cd28ab6a
SH		 698 goto setnew;
699 }
700
793b883e 701 if (hwget == size - 1) {
cd28ab6a
SH		 702 /* set watermark to one list element */
703 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
704
705 /* set put index to first list element */
706 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
793b883e
SH		 707 } else /* have hardware go to end of list */
708 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
709 size - 1);
cd28ab6a 710 } else {
793b883e 711setnew:
cd28ab6a 712 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
cd28ab6a 713 }
bea86103 714 *last = idx;
cd28ab6a
SH		 715}
716
793b883e 717
cd28ab6a
SH		 718static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
719{
720 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
721 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
722 return le;
723}
724
a018e330
SH		 725/* Return high part of DMA address (could be 32 or 64 bit) */
726static inline u32 high32(dma_addr_t a)
727{
728 return (a >> 16) >> 16;
729}
730
793b883e 731/* Build description to hardware about buffer */
734d1868 732static inline void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 733{
734 struct sky2_rx_le *le;
734d1868
SH		 735 u32 hi = high32(map);
736 u16 len = sky2->rx_bufsize;
cd28ab6a 737
793b883e 738 if (sky2->rx_addr64 != hi) {
cd28ab6a 739 le = sky2_next_rx(sky2);
793b883e 740 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 741 le->ctrl = 0;
742 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 743 sky2->rx_addr64 = high32(map + len);
cd28ab6a 744 }
793b883e 745
cd28ab6a 746 le = sky2_next_rx(sky2);
734d1868
SH		 747 le->addr = cpu_to_le32((u32) map);
748 le->length = cpu_to_le16(len);
cd28ab6a
SH		 749 le->ctrl = 0;
750 le->opcode = OP_PACKET | HW_OWNER;
751}
752
793b883e 753
cd28ab6a
SH		 754/* Tell chip where to start receive checksum.
755 * Actually has two checksums, but set both same to avoid possible byte
756 * order problems.
757 */
793b883e 758static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 759{
760 struct sky2_rx_le *le;
761
cd28ab6a 762 le = sky2_next_rx(sky2);
793b883e 763 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 764 le->ctrl = 0;
765 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 766
793b883e
SH		 767 sky2_write32(sky2->hw,
768 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
769 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 770
771}
772
6b1a3aef
SH		 773/*
774 * The RX Stop command will not work for Yukon-2 if the BMU does not
775 * reach the end of packet and since we can't make sure that we have
776 * incoming data, we must reset the BMU while it is not doing a DMA
777 * transfer. Since it is possible that the RX path is still active,
778 * the RX RAM buffer will be stopped first, so any possible incoming
779 * data will not trigger a DMA. After the RAM buffer is stopped, the
780 * BMU is polled until any DMA in progress is ended and only then it
781 * will be reset.
782 */
783static void sky2_rx_stop(struct sky2_port *sky2)
784{
785 struct sky2_hw *hw = sky2->hw;
786 unsigned rxq = rxqaddr[sky2->port];
787 int i;
788
789 /* disable the RAM Buffer receive queue */
790 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
791
792 for (i = 0; i < 0xffff; i++)
793 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
794 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
795 goto stopped;
796
797 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
798 sky2->netdev->name);
799stopped:
800 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
801
802 /* reset the Rx prefetch unit */
803 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
804}
793b883e 805
d571b694 806/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 807static void sky2_rx_clean(struct sky2_port *sky2)
808{
809 unsigned i;
810
811 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 812 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 813 struct ring_info *re = sky2->rx_ring + i;
814
815 if (re->skb) {
793b883e 816 pci_unmap_single(sky2->hw->pdev,
734d1868 817 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 818 PCI_DMA_FROMDEVICE);
819 kfree_skb(re->skb);
820 re->skb = NULL;
821 }
822 }
823}
824
ef743d33
SH		 825/* Basic MII support */
826static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
827{
828 struct mii_ioctl_data *data = if_mii(ifr);
829 struct sky2_port *sky2 = netdev_priv(dev);
830 struct sky2_hw *hw = sky2->hw;
831 int err = -EOPNOTSUPP;
832
833 if (!netif_running(dev))
834 return -ENODEV; /* Phy still in reset */
835
836 switch(cmd) {
837 case SIOCGMIIPHY:
838 data->phy_id = PHY_ADDR_MARV;
839
840 /* fallthru */
841 case SIOCGMIIREG: {
842 u16 val = 0;
91c86df5
SH		 843
844 down(&sky2->phy_sema);
ef743d33 845 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
91c86df5
SH		 846 up(&sky2->phy_sema);
847
ef743d33
SH		 848 data->val_out = val;
849 break;
850 }
851
852 case SIOCSMIIREG:
853 if (!capable(CAP_NET_ADMIN))
854 return -EPERM;
855
91c86df5 856 down(&sky2->phy_sema);
ef743d33
SH		 857 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
858 data->val_in);
91c86df5 859 up(&sky2->phy_sema);
ef743d33
SH		 860 break;
861 }
862 return err;
863}
864
d1f13708
SH		 865#ifdef SKY2_VLAN_TAG_USED
866static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
867{
868 struct sky2_port *sky2 = netdev_priv(dev);
869 struct sky2_hw *hw = sky2->hw;
870 u16 port = sky2->port;
d1f13708 871
f2e46561 872 spin_lock(&sky2->tx_lock);
d1f13708
SH		 873
874 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
875 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
876 sky2->vlgrp = grp;
877
f2e46561 878 spin_unlock(&sky2->tx_lock);
d1f13708
SH		 879}
880
881static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
882{
883 struct sky2_port *sky2 = netdev_priv(dev);
884 struct sky2_hw *hw = sky2->hw;
885 u16 port = sky2->port;
d1f13708 886
f2e46561 887 spin_lock(&sky2->tx_lock);
d1f13708
SH		 888
889 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
890 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
891 if (sky2->vlgrp)
892 sky2->vlgrp->vlan_devices[vid] = NULL;
893
f2e46561 894 spin_unlock(&sky2->tx_lock);
d1f13708
SH		 895}
896#endif
897
cd28ab6a
SH		 898/*
899 * Allocate and setup receiver buffer pool.
900 * In case of 64 bit dma, there are 2X as many list elements
901 * available as ring entries
902 * and need to reserve one list element so we don't wrap around.
79e57d32
SH		 903 *
904 * It appears the hardware has a bug in the FIFO logic that
905 * cause it to hang if the FIFO gets overrun and the receive buffer
906 * is not aligned. This means we can't use skb_reserve to align
907 * the IP header.
cd28ab6a 908 */
6b1a3aef 909static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 910{
6b1a3aef 911 struct sky2_hw *hw = sky2->hw;
6b1a3aef
SH		 912 unsigned rxq = rxqaddr[sky2->port];
913 int i;
cd28ab6a 914
6b1a3aef 915 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 916 sky2_qset(hw, rxq);
6b1a3aef
SH		 917 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
918
919 rx_set_checksum(sky2);
793b883e 920 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 921 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 922
734d1868 923 re->skb = dev_alloc_skb(sky2->rx_bufsize);
cd28ab6a
SH		 924 if (!re->skb)
925 goto nomem;
926
6b1a3aef 927 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 928 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
929 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 930 }
931
6b1a3aef
SH		 932 /* Tell chip about available buffers */
933 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
934 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
cd28ab6a
SH		 935 return 0;
936nomem:
937 sky2_rx_clean(sky2);
938 return -ENOMEM;
939}
940
941/* Bring up network interface. */
942static int sky2_up(struct net_device *dev)
943{
944 struct sky2_port *sky2 = netdev_priv(dev);
945 struct sky2_hw *hw = sky2->hw;
946 unsigned port = sky2->port;
947 u32 ramsize, rxspace;
948 int err = -ENOMEM;
949
950 if (netif_msg_ifup(sky2))
951 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
952
953 /* must be power of 2 */
954 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 955 TX_RING_SIZE *
956 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 957 &sky2->tx_le_map);
958 if (!sky2->tx_le)
959 goto err_out;
960
b2f5ad4f 961 sky2->tx_ring = kzalloc(TX_RING_SIZE * sizeof(struct ring_info),
cd28ab6a
SH		 962 GFP_KERNEL);
963 if (!sky2->tx_ring)
964 goto err_out;
965 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 966
967 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
968 &sky2->rx_le_map);
969 if (!sky2->rx_le)
970 goto err_out;
971 memset(sky2->rx_le, 0, RX_LE_BYTES);
972
b2f5ad4f 973 sky2->rx_ring = kzalloc(sky2->rx_pending * sizeof(struct ring_info),
cd28ab6a
SH		 974 GFP_KERNEL);
975 if (!sky2->rx_ring)
976 goto err_out;
977
978 sky2_mac_init(hw, port);
979
980 /* Configure RAM buffers */
981 if (hw->chip_id == CHIP_ID_YUKON_FE ||
982 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
983 ramsize = 4096;
984 else {
793b883e
SH		 985 u8 e0 = sky2_read8(hw, B2_E_0);
986 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
cd28ab6a
SH		 987 }
988
989 /* 2/3 for Rx */
990 rxspace = (2 * ramsize) / 3;
991 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
992 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
993
793b883e
SH		 994 /* Make sure SyncQ is disabled */
995 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
996 RB_RST_SET);
997
af4ed7e6 998 sky2_qset(hw, txqaddr[port]);
5a5b1ea0
SH		 999 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1000 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1001
1002
6b1a3aef
SH		 1003 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1004 TX_RING_SIZE - 1);
cd28ab6a 1005
6b1a3aef 1006 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1007 if (err)
1008 goto err_out;
1009
cd28ab6a
SH		 1010 /* Enable interrupts from phy/mac for port */
1011 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1012 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1013 return 0;
1014
1015err_out:
1016 if (sky2->rx_le)
1017 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1018 sky2->rx_le, sky2->rx_le_map);
1019 if (sky2->tx_le)
1020 pci_free_consistent(hw->pdev,
1021 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1022 sky2->tx_le, sky2->tx_le_map);
1023 if (sky2->tx_ring)
1024 kfree(sky2->tx_ring);
1025 if (sky2->rx_ring)
1026 kfree(sky2->rx_ring);
1027
1028 return err;
1029}
1030
793b883e
SH		 1031/* Modular subtraction in ring */
1032static inline int tx_dist(unsigned tail, unsigned head)
1033{
129372d0 1034 return (head - tail) % TX_RING_SIZE;
793b883e 1035}
cd28ab6a 1036
793b883e
SH		 1037/* Number of list elements available for next tx */
1038static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1039{
793b883e 1040 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1041}
1042
793b883e
SH		 1043/* Estimate of number of transmit list elements required */
1044static inline unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1045{
793b883e
SH		 1046 unsigned count;
1047
1048 count = sizeof(dma_addr_t) / sizeof(u32);
1049 count += skb_shinfo(skb)->nr_frags * count;
1050
1051 if (skb_shinfo(skb)->tso_size)
1052 ++count;
1053
1054 if (skb->ip_summed)
1055 ++count;
1056
1057 return count;
cd28ab6a
SH		 1058}
1059
793b883e
SH		 1060/*
1061 * Put one packet in ring for transmit.
1062 * A single packet can generate multiple list elements, and
1063 * the number of ring elements will probably be less than the number
1064 * of list elements used.
f2e46561
SH		 1065 *
1066 * No BH disabling for tx_lock here (like tg3)
793b883e 1067 */
cd28ab6a
SH		 1068static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1069{
1070 struct sky2_port *sky2 = netdev_priv(dev);
1071 struct sky2_hw *hw = sky2->hw;
d1f13708 1072 struct sky2_tx_le *le = NULL;
cd28ab6a
SH		 1073 struct ring_info *re;
1074 unsigned i, len;
1075 dma_addr_t mapping;
1076 u32 addr64;
1077 u16 mss;
1078 u8 ctrl;
1079
f2e46561 1080 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1081 return NETDEV_TX_LOCKED;
1082
793b883e 1083 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
cd28ab6a 1084 netif_stop_queue(dev);
f2e46561 1085 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1086
1087 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1088 dev->name);
1089 return NETDEV_TX_BUSY;
1090 }
1091
793b883e 1092 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1093 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1094 dev->name, sky2->tx_prod, skb->len);
1095
cd28ab6a
SH		 1096 len = skb_headlen(skb);
1097 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1098 addr64 = high32(mapping);
793b883e
SH		 1099
1100 re = sky2->tx_ring + sky2->tx_prod;
1101
a018e330
SH		 1102 /* Send high bits if changed or crosses boundary */
1103 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1104 le = get_tx_le(sky2);
1105 le->tx.addr = cpu_to_le32(addr64);
1106 le->ctrl = 0;
1107 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1108 sky2->tx_addr64 = high32(mapping + len);
793b883e 1109 }
cd28ab6a
SH		 1110
1111 /* Check for TCP Segmentation Offload */
1112 mss = skb_shinfo(skb)->tso_size;
793b883e 1113 if (mss != 0) {
cd28ab6a
SH		 1114 /* just drop the packet if non-linear expansion fails */
1115 if (skb_header_cloned(skb) &&
1116 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
793b883e
SH		 1117 dev_kfree_skb_any(skb);
1118 goto out_unlock;
cd28ab6a
SH		 1119 }
1120
1121 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1122 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1123 mss += ETH_HLEN;
793b883e 1124 }
cd28ab6a 1125
793b883e 1126 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1127 le = get_tx_le(sky2);
1128 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1129 le->tx.tso.rsvd = 0;
cd28ab6a 1130 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1131 le->ctrl = 0;
793b883e 1132 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1133 }
1134
cd28ab6a 1135 ctrl = 0;
d1f13708
SH		 1136#ifdef SKY2_VLAN_TAG_USED
1137 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1138 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1139 if (!le) {
1140 le = get_tx_le(sky2);
1141 le->tx.addr = 0;
1142 le->opcode = OP_VLAN|HW_OWNER;
1143 le->ctrl = 0;
1144 } else
1145 le->opcode |= OP_VLAN;
1146 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1147 ctrl |= INS_VLAN;
1148 }
1149#endif
1150
1151 /* Handle TCP checksum offload */
cd28ab6a 1152 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1153 u16 hdr = skb->h.raw - skb->data;
1154 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1155
1156 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1157 if (skb->nh.iph->protocol == IPPROTO_UDP)
1158 ctrl |= UDPTCP;
1159
1160 le = get_tx_le(sky2);
1161 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1162 le->tx.csum.offset = cpu_to_le16(offset);
1163 le->length = 0; /* initial checksum value */
cd28ab6a 1164 le->ctrl = 1; /* one packet */
793b883e 1165 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1166 }
1167
1168 le = get_tx_le(sky2);
1169 le->tx.addr = cpu_to_le32((u32) mapping);
1170 le->length = cpu_to_le16(len);
1171 le->ctrl = ctrl;
793b883e 1172 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1173
793b883e 1174 /* Record the transmit mapping info */
cd28ab6a 1175 re->skb = skb;
793b883e 1176 re->mapaddr = mapping;
cd28ab6a
SH		 1177
1178 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1179 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
793b883e 1180 struct ring_info *fre;
cd28ab6a
SH		 1181
1182 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1183 frag->size, PCI_DMA_TODEVICE);
793b883e
SH		 1184 addr64 = (mapping >> 16) >> 16;
1185 if (addr64 != sky2->tx_addr64) {
1186 le = get_tx_le(sky2);
1187 le->tx.addr = cpu_to_le32(addr64);
1188 le->ctrl = 0;
1189 le->opcode = OP_ADDR64 | HW_OWNER;
1190 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1191 }
1192
1193 le = get_tx_le(sky2);
1194 le->tx.addr = cpu_to_le32((u32) mapping);
1195 le->length = cpu_to_le16(frag->size);
1196 le->ctrl = ctrl;
793b883e 1197 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1198
793b883e
SH		 1199 fre = sky2->tx_ring
1200 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1201 fre->skb = NULL;
1202 fre->mapaddr = mapping;
cd28ab6a 1203 }
793b883e 1204 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1205 le->ctrl |= EOP;
1206
724bca3c 1207 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
cd28ab6a
SH		 1208 &sky2->tx_last_put, TX_RING_SIZE);
1209
793b883e 1210 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
cd28ab6a 1211 netif_stop_queue(dev);
793b883e
SH		 1212
1213out_unlock:
1214 mmiowb();
f2e46561 1215 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1216
1217 dev->trans_start = jiffies;
1218 return NETDEV_TX_OK;
1219}
1220
cd28ab6a 1221/*
793b883e
SH		 1222 * Free ring elements from starting at tx_cons until "done"
1223 *
1224 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1225 * buffers; these are deferred until completion.
cd28ab6a 1226 */
d11c13e7 1227static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1228{
d11c13e7 1229 struct net_device *dev = sky2->netdev;
793b883e 1230 unsigned i;
cd28ab6a 1231
2224795d
SH		 1232 if (done == sky2->tx_cons)
1233 return;
1234
d11c13e7 1235 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1236 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1237 dev->name, done);
cd28ab6a
SH		 1238
1239 spin_lock(&sky2->tx_lock);
cd28ab6a 1240
793b883e
SH		 1241 while (sky2->tx_cons != done) {
1242 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1243 struct sk_buff *skb;
cd28ab6a 1244
793b883e
SH		 1245 /* Check for partial status */
1246 if (tx_dist(sky2->tx_cons, done)
1247 < tx_dist(sky2->tx_cons, re->idx))
1248 goto out;
1249
1250 skb = re->skb;
734d1868
SH		 1251 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1252 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1253
1254 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1255 struct ring_info *fre;
1256 fre =
1257 sky2->tx_ring + (sky2->tx_cons + i +
1258 1) % TX_RING_SIZE;
1259 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
734d1868
SH		 1260 skb_shinfo(skb)->frags[i].size,
1261 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1262 }
1263
cd28ab6a 1264 dev_kfree_skb_any(skb);
cd28ab6a 1265
793b883e
SH		 1266 sky2->tx_cons = re->idx;
1267 }
1268out:
1269
1270 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a
SH		 1271 netif_wake_queue(dev);
1272 spin_unlock(&sky2->tx_lock);
1273}
1274
1275/* Cleanup all untransmitted buffers, assume transmitter not running */
1276static inline void sky2_tx_clean(struct sky2_port *sky2)
1277{
d11c13e7 1278 sky2_tx_complete(sky2, sky2->tx_prod);
cd28ab6a
SH		 1279}
1280
1281/* Network shutdown */
1282static int sky2_down(struct net_device *dev)
1283{
1284 struct sky2_port *sky2 = netdev_priv(dev);
1285 struct sky2_hw *hw = sky2->hw;
1286 unsigned port = sky2->port;
1287 u16 ctrl;
cd28ab6a
SH		 1288
1289 if (netif_msg_ifdown(sky2))
1290 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1291
018d1c66 1292 /* Stop more packets from being queued */
cd28ab6a
SH		 1293 netif_stop_queue(dev);
1294
018d1c66
SH		 1295 /* Disable port IRQ */
1296 local_irq_disable();
1297 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1298 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1299 local_irq_enable();
1300
91c86df5 1301 flush_scheduled_work();
018d1c66 1302
793b883e
SH		 1303 sky2_phy_reset(hw, port);
1304
cd28ab6a
SH		 1305 /* Stop transmitter */
1306 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1307 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1308
1309 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1310 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1311
1312 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1313 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1314 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1315
1316 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1317
1318 /* Workaround shared GMAC reset */
793b883e
SH		 1319 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1320 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1321 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1322
1323 /* Disable Force Sync bit and Enable Alloc bit */
1324 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1325 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1326
1327 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1328 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1329 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1330
1331 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1332 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1333 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1334
1335 /* Reset the Tx prefetch units */
1336 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1337 PREF_UNIT_RST_SET);
1338
1339 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1340
6b1a3aef 1341 sky2_rx_stop(sky2);
cd28ab6a
SH		 1342
1343 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1344 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1345
d571b694 1346 /* turn off LED's */
cd28ab6a
SH		 1347 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1348
018d1c66
SH		 1349 synchronize_irq(hw->pdev->irq);
1350
cd28ab6a
SH		 1351 sky2_tx_clean(sky2);
1352 sky2_rx_clean(sky2);
1353
1354 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1355 sky2->rx_le, sky2->rx_le_map);
1356 kfree(sky2->rx_ring);
1357
1358 pci_free_consistent(hw->pdev,
1359 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1360 sky2->tx_le, sky2->tx_le_map);
1361 kfree(sky2->tx_ring);
1362
1363 return 0;
1364}
1365
1366static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1367{
793b883e
SH		 1368 if (!hw->copper)
1369 return SPEED_1000;
1370
cd28ab6a
SH		 1371 if (hw->chip_id == CHIP_ID_YUKON_FE)
1372 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1373
1374 switch (aux & PHY_M_PS_SPEED_MSK) {
1375 case PHY_M_PS_SPEED_1000:
1376 return SPEED_1000;
1377 case PHY_M_PS_SPEED_100:
1378 return SPEED_100;
1379 default:
1380 return SPEED_10;
1381 }
1382}
1383
1384static void sky2_link_up(struct sky2_port *sky2)
1385{
1386 struct sky2_hw *hw = sky2->hw;
1387 unsigned port = sky2->port;
1388 u16 reg;
1389
1390 /* Enable Transmit FIFO Underrun */
793b883e 1391 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1392
1393 reg = gma_read16(hw, port, GM_GP_CTRL);
1394 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1395 reg |= GM_GPCR_DUP_FULL;
1396
cd28ab6a
SH		 1397 /* enable Rx/Tx */
1398 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1399 gma_write16(hw, port, GM_GP_CTRL, reg);
1400 gma_read16(hw, port, GM_GP_CTRL);
1401
1402 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1403
1404 netif_carrier_on(sky2->netdev);
1405 netif_wake_queue(sky2->netdev);
1406
1407 /* Turn on link LED */
793b883e 1408 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1409 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1410
793b883e
SH		 1411 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1412 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1413
1414 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1415 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1416 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1417 SPEED_10 ? 7 : 0) |
1418 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1419 SPEED_100 ? 7 : 0) |
1420 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1421 SPEED_1000 ? 7 : 0));
1422 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1423 }
1424
cd28ab6a
SH		 1425 if (netif_msg_link(sky2))
1426 printk(KERN_INFO PFX
d571b694 1427 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1428 sky2->netdev->name, sky2->speed,
1429 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1430 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1431 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1432}
1433
1434static void sky2_link_down(struct sky2_port *sky2)
1435{
1436 struct sky2_hw *hw = sky2->hw;
1437 unsigned port = sky2->port;
1438 u16 reg;
1439
1440 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1441
1442 reg = gma_read16(hw, port, GM_GP_CTRL);
1443 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1444 gma_write16(hw, port, GM_GP_CTRL, reg);
1445 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1446
1447 if (sky2->rx_pause && !sky2->tx_pause) {
1448 /* restore Asymmetric Pause bit */
1449 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1450 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1451 | PHY_M_AN_ASP);
cd28ab6a
SH		 1452 }
1453
1454 sky2_phy_reset(hw, port);
1455
1456 netif_carrier_off(sky2->netdev);
1457 netif_stop_queue(sky2->netdev);
1458
1459 /* Turn on link LED */
1460 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1461
1462 if (netif_msg_link(sky2))
1463 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1464 sky2_phy_init(hw, port);
1465}
1466
793b883e
SH		 1467static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1468{
1469 struct sky2_hw *hw = sky2->hw;
1470 unsigned port = sky2->port;
1471 u16 lpa;
1472
1473 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1474
1475 if (lpa & PHY_M_AN_RF) {
1476 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1477 return -1;
1478 }
1479
1480 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1481 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1482 printk(KERN_ERR PFX "%s: master/slave fault",
1483 sky2->netdev->name);
1484 return -1;
1485 }
1486
1487 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1488 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1489 sky2->netdev->name);
1490 return -1;
1491 }
1492
1493 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1494
1495 sky2->speed = sky2_phy_speed(hw, aux);
1496
1497 /* Pause bits are offset (9..8) */
1498 if (hw->chip_id == CHIP_ID_YUKON_XL)
1499 aux >>= 6;
1500
1501 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1502 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1503
1504 if ((sky2->tx_pause || sky2->rx_pause)
1505 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1506 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1507 else
1508 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1509
1510 return 0;
1511}
cd28ab6a
SH		 1512
1513/*
91c86df5 1514 * Interrupt from PHY are handled outside of interrupt context
cd28ab6a
SH		 1515 * because accessing phy registers requires spin wait which might
1516 * cause excess interrupt latency.
1517 */
91c86df5 1518static void sky2_phy_task(void *arg)
cd28ab6a 1519{
91c86df5 1520 struct sky2_port *sky2 = arg;
cd28ab6a 1521 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1522 u16 istatus, phystat;
1523
91c86df5 1524 down(&sky2->phy_sema);
793b883e
SH		 1525 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1526 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
cd28ab6a
SH		 1527
1528 if (netif_msg_intr(sky2))
1529 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1530 sky2->netdev->name, istatus, phystat);
1531
1532 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1533 if (sky2_autoneg_done(sky2, phystat) == 0)
1534 sky2_link_up(sky2);
1535 goto out;
1536 }
cd28ab6a 1537
793b883e
SH		 1538 if (istatus & PHY_M_IS_LSP_CHANGE)
1539 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1540
793b883e
SH		 1541 if (istatus & PHY_M_IS_DUP_CHANGE)
1542 sky2->duplex =
1543 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1544
793b883e
SH		 1545 if (istatus & PHY_M_IS_LST_CHANGE) {
1546 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1547 sky2_link_up(sky2);
793b883e
SH		 1548 else
1549 sky2_link_down(sky2);
cd28ab6a 1550 }
793b883e 1551out:
91c86df5 1552 up(&sky2->phy_sema);
cd28ab6a
SH		 1553
1554 local_irq_disable();
793b883e 1555 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
cd28ab6a
SH		 1556 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1557 local_irq_enable();
1558}
1559
1560static void sky2_tx_timeout(struct net_device *dev)
1561{
1562 struct sky2_port *sky2 = netdev_priv(dev);
1563
1564 if (netif_msg_timer(sky2))
1565 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1566
1567 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1568 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1569
1570 sky2_tx_clean(sky2);
1571}
1572
734d1868
SH		 1573
1574#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1575/* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1576static inline unsigned sky2_buf_size(int mtu)
1577{
1578 return roundup(mtu + ETH_HLEN + 4, 8);
1579}
1580
cd28ab6a
SH		 1581static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1582{
6b1a3aef
SH		 1583 struct sky2_port *sky2 = netdev_priv(dev);
1584 struct sky2_hw *hw = sky2->hw;
1585 int err;
1586 u16 ctl, mode;
cd28ab6a
SH		 1587
1588 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1589 return -EINVAL;
1590
5a5b1ea0
SH		 1591 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1592 return -EINVAL;
1593
6b1a3aef
SH		 1594 if (!netif_running(dev)) {
1595 dev->mtu = new_mtu;
1596 return 0;
1597 }
1598
6b1a3aef
SH		 1599 sky2_write32(hw, B0_IMSK, 0);
1600
018d1c66
SH		 1601 dev->trans_start = jiffies; /* prevent tx timeout */
1602 netif_stop_queue(dev);
1603 netif_poll_disable(hw->dev[0]);
1604
6b1a3aef
SH		 1605 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1606 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1607 sky2_rx_stop(sky2);
1608 sky2_rx_clean(sky2);
cd28ab6a
SH		 1609
1610 dev->mtu = new_mtu;
734d1868 1611 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef
SH		 1612 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1613 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1614
1615 if (dev->mtu > ETH_DATA_LEN)
1616 mode |= GM_SMOD_JUMBO_ENA;
1617
1618 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1619
6b1a3aef 1620 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1621
6b1a3aef
SH		 1622 err = sky2_rx_start(sky2);
1623 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1624
018d1c66
SH		 1625 netif_poll_disable(hw->dev[0]);
1626 netif_wake_queue(dev);
6b1a3aef 1627 sky2_write32(hw, B0_IMSK, hw->intr_mask);
018d1c66 1628
cd28ab6a
SH		 1629 return err;
1630}
1631
1632/*
1633 * Receive one packet.
1634 * For small packets or errors, just reuse existing skb.
d571b694 1635 * For larger packets, get new buffer.
cd28ab6a 1636 */
d11c13e7 1637static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1638 u16 length, u32 status)
1639{
cd28ab6a 1640 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1641 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1642
1643 if (unlikely(netif_msg_rx_status(sky2)))
1644 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1645 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1646
793b883e 1647 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
cd28ab6a 1648
42eeea01 1649 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1650 goto error;
1651
42eeea01
SH		 1652 if (!(status & GMR_FS_RX_OK))
1653 goto resubmit;
1654
bdb5c58e 1655 if (length < copybreak) {
79e57d32
SH		 1656 skb = alloc_skb(length + 2, GFP_ATOMIC);
1657 if (!skb)
793b883e
SH		 1658 goto resubmit;
1659
79e57d32 1660 skb_reserve(skb, 2);
793b883e
SH		 1661 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1662 length, PCI_DMA_FROMDEVICE);
79e57d32 1663 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1664 skb->ip_summed = re->skb->ip_summed;
1665 skb->csum = re->skb->csum;
793b883e
SH		 1666 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1667 length, PCI_DMA_FROMDEVICE);
793b883e 1668 } else {
79e57d32
SH		 1669 struct sk_buff *nskb;
1670
734d1868 1671 nskb = dev_alloc_skb(sky2->rx_bufsize);
793b883e
SH		 1672 if (!nskb)
1673 goto resubmit;
cd28ab6a 1674
793b883e 1675 skb = re->skb;
79e57d32 1676 re->skb = nskb;
793b883e 1677 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1678 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1679 prefetch(skb->data);
cd28ab6a 1680
793b883e 1681 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1682 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1683 }
cd28ab6a 1684
79e57d32 1685 skb_put(skb, length);
793b883e 1686resubmit:
d11c13e7 1687 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1688 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1689
bea86103
SH		 1690 /* Tell receiver about new buffers. */
1691 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1692 &sky2->rx_last_put, RX_LE_SIZE);
1693
cd28ab6a
SH		 1694 return skb;
1695
1696error:
1697 if (netif_msg_rx_err(sky2))
1698 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1699 sky2->netdev->name, status, length);
793b883e
SH		 1700
1701 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1702 sky2->net_stats.rx_length_errors++;
1703 if (status & GMR_FS_FRAGMENT)
1704 sky2->net_stats.rx_frame_errors++;
1705 if (status & GMR_FS_CRC_ERR)
1706 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1707 if (status & GMR_FS_RX_FF_OV)
1708 sky2->net_stats.rx_fifo_errors++;
79e57d32 1709
793b883e 1710 goto resubmit;
cd28ab6a
SH		 1711}
1712
2224795d
SH		 1713/*
1714 * Check for transmit complete
793b883e 1715 */
2224795d 1716static inline void sky2_tx_check(struct sky2_hw *hw, int port)
cd28ab6a 1717{
2224795d
SH		 1718 struct net_device *dev = hw->dev[port];
1719
1720 if (dev && netif_running(dev)) {
1721 sky2_tx_complete(netdev_priv(dev),
1722 sky2_read16(hw, port == 0
1723 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX));
1724 }
cd28ab6a
SH		 1725}
1726
1727/*
cd28ab6a
SH		 1728 * Both ports share the same status interrupt, therefore there is only
1729 * one poll routine.
cd28ab6a 1730 */
d11c13e7 1731static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 1732{
d11c13e7
SH		 1733 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1734 unsigned int to_do = min(dev0->quota, *budget);
cd28ab6a 1735 unsigned int work_done = 0;
793b883e 1736 u16 hwidx;
cd28ab6a 1737
f89c2b46 1738 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
793b883e 1739 hwidx = sky2_read16(hw, STAT_PUT_IDX);
79e57d32 1740 BUG_ON(hwidx >= STATUS_RING_SIZE);
793b883e 1741 rmb();
bea86103 1742
13210ce5
SH		 1743 while (hwidx != hw->st_idx) {
1744 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1745 struct net_device *dev;
d11c13e7 1746 struct sky2_port *sky2;
cd28ab6a 1747 struct sk_buff *skb;
cd28ab6a
SH		 1748 u32 status;
1749 u16 length;
13210ce5 1750 u8 op;
cd28ab6a 1751
13210ce5 1752 le = hw->st_le + hw->st_idx;
bea86103 1753 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
13210ce5 1754 prefetch(hw->st_le + hw->st_idx);
bea86103
SH		 1755
1756 BUG_ON(le->link >= hw->ports || !hw->dev[le->link]);
d1f13708 1757
13210ce5
SH		 1758 BUG_ON(le->link >= 2);
1759 dev = hw->dev[le->link];
1760 if (dev == NULL || !netif_running(dev))
1761 continue;
1762
1763 sky2 = netdev_priv(dev);
cd28ab6a
SH		 1764 status = le32_to_cpu(le->status);
1765 length = le16_to_cpu(le->length);
13210ce5
SH		 1766 op = le->opcode & ~HW_OWNER;
1767 le->opcode = 0;
cd28ab6a 1768
13210ce5 1769 switch (op) {
cd28ab6a 1770 case OP_RXSTAT:
d11c13e7 1771 skb = sky2_receive(sky2, length, status);
d1f13708
SH		 1772 if (!skb)
1773 break;
13210ce5
SH		 1774
1775 skb->dev = dev;
1776 skb->protocol = eth_type_trans(skb, dev);
1777 dev->last_rx = jiffies;
1778
d1f13708
SH		 1779#ifdef SKY2_VLAN_TAG_USED
1780 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1781 vlan_hwaccel_receive_skb(skb,
1782 sky2->vlgrp,
1783 be16_to_cpu(sky2->rx_tag));
1784 } else
1785#endif
cd28ab6a 1786 netif_receive_skb(skb);
13210ce5
SH		 1787
1788 if (++work_done >= to_do)
1789 goto exit_loop;
cd28ab6a
SH		 1790 break;
1791
d1f13708
SH		 1792#ifdef SKY2_VLAN_TAG_USED
1793 case OP_RXVLAN:
1794 sky2->rx_tag = length;
1795 break;
1796
1797 case OP_RXCHKSVLAN:
1798 sky2->rx_tag = length;
1799 /* fall through */
1800#endif
cd28ab6a 1801 case OP_RXCHKS:
d11c13e7
SH		 1802 skb = sky2->rx_ring[sky2->rx_next].skb;
1803 skb->ip_summed = CHECKSUM_HW;
1804 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1805 break;
1806
1807 case OP_TXINDEXLE:
2224795d 1808 /* pick up transmit status later */
cd28ab6a
SH		 1809 break;
1810
cd28ab6a
SH		 1811 default:
1812 if (net_ratelimit())
793b883e 1813 printk(KERN_WARNING PFX
13210ce5 1814 "unknown status opcode 0x%x\n", op);
cd28ab6a
SH		 1815 break;
1816 }
13210ce5 1817 }
cd28ab6a 1818
13210ce5 1819exit_loop:
2224795d
SH		 1820 sky2_tx_check(hw, 0);
1821 sky2_tx_check(hw, 1);
cd28ab6a 1822
793b883e
SH		 1823 mmiowb();
1824
cd28ab6a
SH		 1825 if (work_done < to_do) {
1826 /*
1827 * Another chip workaround, need to restart TX timer if status
1828 * LE was handled. WA_DEV_43_418
1829 */
1830 if (is_ec_a1(hw)) {
1831 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1832 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1833 }
1834
bea86103 1835 netif_rx_complete(dev0);
cd28ab6a
SH		 1836 hw->intr_mask |= Y2_IS_STAT_BMU;
1837 sky2_write32(hw, B0_IMSK, hw->intr_mask);
13210ce5
SH		 1838 mmiowb();
1839 return 0;
1840 } else {
1841 *budget -= work_done;
1842 dev0->quota -= work_done;
1843 return 1;
cd28ab6a 1844 }
cd28ab6a
SH		 1845}
1846
1847static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1848{
1849 struct net_device *dev = hw->dev[port];
1850
1851 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1852 dev->name, status);
1853
1854 if (status & Y2_IS_PAR_RD1) {
1855 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1856 dev->name);
1857 /* Clear IRQ */
1858 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1859 }
1860
1861 if (status & Y2_IS_PAR_WR1) {
1862 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1863 dev->name);
1864
1865 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1866 }
1867
1868 if (status & Y2_IS_PAR_MAC1) {
1869 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1870 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1871 }
1872
1873 if (status & Y2_IS_PAR_RX1) {
1874 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1875 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1876 }
1877
1878 if (status & Y2_IS_TCP_TXA1) {
1879 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1880 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1881 }
1882}
1883
1884static void sky2_hw_intr(struct sky2_hw *hw)
1885{
1886 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1887
793b883e 1888 if (status & Y2_IS_TIST_OV)
cd28ab6a 1889 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 1890
1891 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 1892 u16 pci_err;
1893
1894 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
cd28ab6a
SH		 1895 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1896 pci_name(hw->pdev), pci_err);
1897
1898 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1899 pci_write_config_word(hw->pdev, PCI_STATUS,
1900 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 1901 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1902 }
1903
1904 if (status & Y2_IS_PCI_EXP) {
d571b694 1905 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 1906 u32 pex_err;
1907
1908 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
cd28ab6a 1909
cd28ab6a
SH		 1910 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1911 pci_name(hw->pdev), pex_err);
1912
1913 /* clear the interrupt */
1914 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1915 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1916 0xffffffffUL);
cd28ab6a
SH		 1917 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1918
1919 if (pex_err & PEX_FATAL_ERRORS) {
1920 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1921 hwmsk &= ~Y2_IS_PCI_EXP;
1922 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1923 }
1924 }
1925
1926 if (status & Y2_HWE_L1_MASK)
1927 sky2_hw_error(hw, 0, status);
1928 status >>= 8;
1929 if (status & Y2_HWE_L1_MASK)
1930 sky2_hw_error(hw, 1, status);
1931}
1932
1933static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1934{
1935 struct net_device *dev = hw->dev[port];
1936 struct sky2_port *sky2 = netdev_priv(dev);
1937 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1938
1939 if (netif_msg_intr(sky2))
1940 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1941 dev->name, status);
1942
1943 if (status & GM_IS_RX_FF_OR) {
1944 ++sky2->net_stats.rx_fifo_errors;
1945 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1946 }
1947
1948 if (status & GM_IS_TX_FF_UR) {
1949 ++sky2->net_stats.tx_fifo_errors;
1950 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1951 }
cd28ab6a
SH		 1952}
1953
1954static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1955{
1956 struct net_device *dev = hw->dev[port];
1957 struct sky2_port *sky2 = netdev_priv(dev);
1958
1959 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1960 sky2_write32(hw, B0_IMSK, hw->intr_mask);
91c86df5 1961 schedule_work(&sky2->phy_task);
cd28ab6a
SH		 1962}
1963
1964static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1965{
1966 struct sky2_hw *hw = dev_id;
bea86103 1967 struct net_device *dev0 = hw->dev[0];
cd28ab6a
SH		 1968 u32 status;
1969
1970 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
793b883e 1971 if (status == 0 || status == ~0)
cd28ab6a
SH		 1972 return IRQ_NONE;
1973
1974 if (status & Y2_IS_HW_ERR)
1975 sky2_hw_intr(hw);
1976
793b883e 1977 /* Do NAPI for Rx and Tx status */
bea86103 1978 if (status & Y2_IS_STAT_BMU) {
cd28ab6a
SH		 1979 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1980 sky2_write32(hw, B0_IMSK, hw->intr_mask);
bea86103 1981
0a122576
SH		 1982 if (likely(__netif_rx_schedule_prep(dev0))) {
1983 prefetch(&hw->st_le[hw->st_idx]);
bea86103 1984 __netif_rx_schedule(dev0);
0a122576 1985 }
cd28ab6a
SH		 1986 }
1987
793b883e 1988 if (status & Y2_IS_IRQ_PHY1)
cd28ab6a
SH		 1989 sky2_phy_intr(hw, 0);
1990
1991 if (status & Y2_IS_IRQ_PHY2)
1992 sky2_phy_intr(hw, 1);
1993
1994 if (status & Y2_IS_IRQ_MAC1)
1995 sky2_mac_intr(hw, 0);
1996
1997 if (status & Y2_IS_IRQ_MAC2)
1998 sky2_mac_intr(hw, 1);
1999
cd28ab6a 2000 sky2_write32(hw, B0_Y2_SP_ICR, 2);
793b883e
SH		 2001
2002 sky2_read32(hw, B0_IMSK);
2003
cd28ab6a
SH		 2004 return IRQ_HANDLED;
2005}
2006
2007#ifdef CONFIG_NET_POLL_CONTROLLER
2008static void sky2_netpoll(struct net_device *dev)
2009{
2010 struct sky2_port *sky2 = netdev_priv(dev);
2011
793b883e 2012 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 2013}
2014#endif
2015
2016/* Chip internal frequency for clock calculations */
fb17358f 2017static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2018{
793b883e 2019 switch (hw->chip_id) {
cd28ab6a 2020 case CHIP_ID_YUKON_EC:
5a5b1ea0 2021 case CHIP_ID_YUKON_EC_U:
fb17358f 2022 return 125; /* 125 Mhz */
cd28ab6a 2023 case CHIP_ID_YUKON_FE:
fb17358f 2024 return 100; /* 100 Mhz */
793b883e 2025 default: /* YUKON_XL */
fb17358f 2026 return 156; /* 156 Mhz */
cd28ab6a
SH		 2027 }
2028}
2029
fb17358f 2030static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2031{
fb17358f 2032 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2033}
2034
fb17358f 2035static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2036{
fb17358f 2037 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2038}
2039
fb17358f 2040
cd28ab6a
SH		 2041static int sky2_reset(struct sky2_hw *hw)
2042{
5afa0a9c 2043 u32 ctst;
cd28ab6a
SH		 2044 u16 status;
2045 u8 t8, pmd_type;
2046 int i;
2047
2048 ctst = sky2_read32(hw, B0_CTST);
2049
2050 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2051 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2052 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2053 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2054 pci_name(hw->pdev), hw->chip_id);
2055 return -EOPNOTSUPP;
2056 }
2057
793b883e
SH		 2058 /* ring for status responses */
2059 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
2060 &hw->st_dma);
2061 if (!hw->st_le)
2062 return -ENOMEM;
2063
cd28ab6a
SH		 2064 /* disable ASF */
2065 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2066 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2067 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2068 }
2069
2070 /* do a SW reset */
2071 sky2_write8(hw, B0_CTST, CS_RST_SET);
2072 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2073
2074 /* clear PCI errors, if any */
793b883e 2075 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
cd28ab6a 2076 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 2077 pci_write_config_word(hw->pdev, PCI_STATUS,
2078 status | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2079
2080 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2081
2082 /* clear any PEX errors */
2083 if (is_pciex(hw)) {
793b883e
SH		 2084 u16 lstat;
2085 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2086 0xffffffffUL);
2087 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
cd28ab6a
SH		 2088 }
2089
2090 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2091 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2092
2093 hw->ports = 1;
2094 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2095 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2096 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2097 ++hw->ports;
2098 }
2099 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2100
5afa0a9c 2101 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2102
2103 for (i = 0; i < hw->ports; i++) {
2104 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2105 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2106 }
2107
2108 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2109
793b883e
SH		 2110 /* Clear I2C IRQ noise */
2111 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2112
2113 /* turn off hardware timer (unused) */
2114 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2115 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2116
cd28ab6a
SH		 2117 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2118
793b883e 2119 /* Turn on descriptor polling (every 75us) */
cd28ab6a
SH		 2120 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
2121 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
2122
2123 /* Turn off receive timestamp */
2124 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2125 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2126
2127 /* enable the Tx Arbiters */
2128 for (i = 0; i < hw->ports; i++)
2129 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2130
2131 /* Initialize ram interface */
2132 for (i = 0; i < hw->ports; i++) {
793b883e 2133 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2134
2135 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2136 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2137 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2138 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2139 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2140 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2141 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2142 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2143 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2144 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2145 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2146 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2147 }
2148
cd28ab6a
SH		 2149 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2150
cd28ab6a
SH		 2151 for (i = 0; i < hw->ports; i++)
2152 sky2_phy_reset(hw, i);
cd28ab6a 2153
cd28ab6a
SH		 2154 memset(hw->st_le, 0, STATUS_LE_BYTES);
2155 hw->st_idx = 0;
2156
2157 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2158 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2159
2160 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2161 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2162
2163 /* Set the list last index */
793b883e 2164 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2165
fb17358f 2166 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
793b883e
SH		 2167
2168 /* These status setup values are copied from SysKonnect's driver */
cd28ab6a
SH		 2169 if (is_ec_a1(hw)) {
2170 /* WA for dev. #4.3 */
793b883e 2171 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
cd28ab6a
SH		 2172
2173 /* set Status-FIFO watermark */
2174 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2175
2176 /* set Status-FIFO ISR watermark */
793b883e 2177 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
cd28ab6a 2178
cd28ab6a 2179 } else {
cd28ab6a
SH		 2180 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
2181
2182 /* set Status-FIFO watermark */
2183 sky2_write8(hw, STAT_FIFO_WM, 0x10);
2184
2185 /* set Status-FIFO ISR watermark */
2186 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2187 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
2188
d571b694 2189 else /* WA dev 4.109 */
cd28ab6a
SH		 2190 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
2191
2192 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
2193 }
2194
793b883e 2195 /* enable status unit */
cd28ab6a
SH		 2196 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2197
2198 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2199 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2200 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2201
2202 return 0;
2203}
2204
2205static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2206{
2207 u32 modes;
2208 if (hw->copper) {
793b883e
SH		 2209 modes = SUPPORTED_10baseT_Half
2210 | SUPPORTED_10baseT_Full
2211 | SUPPORTED_100baseT_Half
2212 | SUPPORTED_100baseT_Full
2213 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2214
2215 if (hw->chip_id != CHIP_ID_YUKON_FE)
2216 modes |= SUPPORTED_1000baseT_Half
793b883e 2217 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2218 } else
2219 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2220 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2221 return modes;
2222}
2223
793b883e 2224static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2225{
2226 struct sky2_port *sky2 = netdev_priv(dev);
2227 struct sky2_hw *hw = sky2->hw;
2228
2229 ecmd->transceiver = XCVR_INTERNAL;
2230 ecmd->supported = sky2_supported_modes(hw);
2231 ecmd->phy_address = PHY_ADDR_MARV;
2232 if (hw->copper) {
2233 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2234 | SUPPORTED_10baseT_Full
2235 | SUPPORTED_100baseT_Half
2236 | SUPPORTED_100baseT_Full
2237 | SUPPORTED_1000baseT_Half
2238 | SUPPORTED_1000baseT_Full
2239 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2240 ecmd->port = PORT_TP;
2241 } else
2242 ecmd->port = PORT_FIBRE;
2243
2244 ecmd->advertising = sky2->advertising;
2245 ecmd->autoneg = sky2->autoneg;
2246 ecmd->speed = sky2->speed;
2247 ecmd->duplex = sky2->duplex;
2248 return 0;
2249}
2250
2251static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2252{
2253 struct sky2_port *sky2 = netdev_priv(dev);
2254 const struct sky2_hw *hw = sky2->hw;
2255 u32 supported = sky2_supported_modes(hw);
2256
2257 if (ecmd->autoneg == AUTONEG_ENABLE) {
2258 ecmd->advertising = supported;
2259 sky2->duplex = -1;
2260 sky2->speed = -1;
2261 } else {
2262 u32 setting;
2263
793b883e 2264 switch (ecmd->speed) {
cd28ab6a
SH		 2265 case SPEED_1000:
2266 if (ecmd->duplex == DUPLEX_FULL)
2267 setting = SUPPORTED_1000baseT_Full;
2268 else if (ecmd->duplex == DUPLEX_HALF)
2269 setting = SUPPORTED_1000baseT_Half;
2270 else
2271 return -EINVAL;
2272 break;
2273 case SPEED_100:
2274 if (ecmd->duplex == DUPLEX_FULL)
2275 setting = SUPPORTED_100baseT_Full;
2276 else if (ecmd->duplex == DUPLEX_HALF)
2277 setting = SUPPORTED_100baseT_Half;
2278 else
2279 return -EINVAL;
2280 break;
2281
2282 case SPEED_10:
2283 if (ecmd->duplex == DUPLEX_FULL)
2284 setting = SUPPORTED_10baseT_Full;
2285 else if (ecmd->duplex == DUPLEX_HALF)
2286 setting = SUPPORTED_10baseT_Half;
2287 else
2288 return -EINVAL;
2289 break;
2290 default:
2291 return -EINVAL;
2292 }
2293
2294 if ((setting & supported) == 0)
2295 return -EINVAL;
2296
2297 sky2->speed = ecmd->speed;
2298 sky2->duplex = ecmd->duplex;
2299 }
2300
2301 sky2->autoneg = ecmd->autoneg;
2302 sky2->advertising = ecmd->advertising;
2303
2304 if (netif_running(dev)) {
2305 sky2_down(dev);
2306 sky2_up(dev);
2307 }
2308
2309 return 0;
2310}
2311
2312static void sky2_get_drvinfo(struct net_device *dev,
2313 struct ethtool_drvinfo *info)
2314{
2315 struct sky2_port *sky2 = netdev_priv(dev);
2316
2317 strcpy(info->driver, DRV_NAME);
2318 strcpy(info->version, DRV_VERSION);
2319 strcpy(info->fw_version, "N/A");
2320 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2321}
2322
2323static const struct sky2_stat {
793b883e
SH		 2324 char name[ETH_GSTRING_LEN];
2325 u16 offset;
cd28ab6a
SH		 2326} sky2_stats[] = {
2327 { "tx_bytes", GM_TXO_OK_HI },
2328 { "rx_bytes", GM_RXO_OK_HI },
2329 { "tx_broadcast", GM_TXF_BC_OK },
2330 { "rx_broadcast", GM_RXF_BC_OK },
2331 { "tx_multicast", GM_TXF_MC_OK },
2332 { "rx_multicast", GM_RXF_MC_OK },
2333 { "tx_unicast", GM_TXF_UC_OK },
2334 { "rx_unicast", GM_RXF_UC_OK },
2335 { "tx_mac_pause", GM_TXF_MPAUSE },
2336 { "rx_mac_pause", GM_RXF_MPAUSE },
2337 { "collisions", GM_TXF_SNG_COL },
2338 { "late_collision",GM_TXF_LAT_COL },
2339 { "aborted", GM_TXF_ABO_COL },
2340 { "multi_collisions", GM_TXF_MUL_COL },
2341 { "fifo_underrun", GM_TXE_FIFO_UR },
2342 { "fifo_overflow", GM_RXE_FIFO_OV },
2343 { "rx_toolong", GM_RXF_LNG_ERR },
2344 { "rx_jabber", GM_RXF_JAB_PKT },
2345 { "rx_runt", GM_RXE_FRAG },
2346 { "rx_too_long", GM_RXF_LNG_ERR },
2347 { "rx_fcs_error", GM_RXF_FCS_ERR },
2348};
2349
cd28ab6a
SH		 2350static u32 sky2_get_rx_csum(struct net_device *dev)
2351{
2352 struct sky2_port *sky2 = netdev_priv(dev);
2353
2354 return sky2->rx_csum;
2355}
2356
2357static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2358{
2359 struct sky2_port *sky2 = netdev_priv(dev);
2360
2361 sky2->rx_csum = data;
793b883e 2362
cd28ab6a
SH		 2363 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2364 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2365
2366 return 0;
2367}
2368
2369static u32 sky2_get_msglevel(struct net_device *netdev)
2370{
2371 struct sky2_port *sky2 = netdev_priv(netdev);
2372 return sky2->msg_enable;
2373}
2374
9a7ae0a9
SH		 2375static int sky2_nway_reset(struct net_device *dev)
2376{
2377 struct sky2_port *sky2 = netdev_priv(dev);
2378 struct sky2_hw *hw = sky2->hw;
2379
2380 if (sky2->autoneg != AUTONEG_ENABLE)
2381 return -EINVAL;
2382
2383 netif_stop_queue(dev);
2384
91c86df5 2385 down(&sky2->phy_sema);
9a7ae0a9
SH		 2386 sky2_phy_reset(hw, sky2->port);
2387 sky2_phy_init(hw, sky2->port);
91c86df5 2388 up(&sky2->phy_sema);
9a7ae0a9
SH		 2389
2390 return 0;
2391}
2392
793b883e 2393static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2394{
2395 struct sky2_hw *hw = sky2->hw;
2396 unsigned port = sky2->port;
2397 int i;
2398
2399 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2400 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2401 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2402 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2403
793b883e 2404 for (i = 2; i < count; i++)
cd28ab6a
SH		 2405 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2406}
2407
cd28ab6a
SH		 2408static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2409{
2410 struct sky2_port *sky2 = netdev_priv(netdev);
2411 sky2->msg_enable = value;
2412}
2413
2414static int sky2_get_stats_count(struct net_device *dev)
2415{
2416 return ARRAY_SIZE(sky2_stats);
2417}
2418
2419static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2420 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2421{
2422 struct sky2_port *sky2 = netdev_priv(dev);
2423
793b883e 2424 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2425}
2426
793b883e 2427static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2428{
2429 int i;
2430
2431 switch (stringset) {
2432 case ETH_SS_STATS:
2433 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2434 memcpy(data + i * ETH_GSTRING_LEN,
2435 sky2_stats[i].name, ETH_GSTRING_LEN);
2436 break;
2437 }
2438}
2439
2440/* Use hardware MIB variables for critical path statistics and
2441 * transmit feedback not reported at interrupt.
2442 * Other errors are accounted for in interrupt handler.
2443 */
2444static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2445{
2446 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2447 u64 data[13];
cd28ab6a 2448
793b883e 2449 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2450
2451 sky2->net_stats.tx_bytes = data[0];
2452 sky2->net_stats.rx_bytes = data[1];
2453 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2454 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2455 sky2->net_stats.multicast = data[5] + data[7];
2456 sky2->net_stats.collisions = data[10];
2457 sky2->net_stats.tx_aborted_errors = data[12];
2458
2459 return &sky2->net_stats;
2460}
2461
2462static int sky2_set_mac_address(struct net_device *dev, void *p)
2463{
2464 struct sky2_port *sky2 = netdev_priv(dev);
2465 struct sockaddr *addr = p;
2466 int err = 0;
2467
2468 if (!is_valid_ether_addr(addr->sa_data))
2469 return -EADDRNOTAVAIL;
2470
2471 sky2_down(dev);
2472 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
793b883e 2473 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
cd28ab6a 2474 dev->dev_addr, ETH_ALEN);
793b883e 2475 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
cd28ab6a
SH		 2476 dev->dev_addr, ETH_ALEN);
2477 if (dev->flags & IFF_UP)
2478 err = sky2_up(dev);
2479 return err;
2480}
2481
2482static void sky2_set_multicast(struct net_device *dev)
2483{
2484 struct sky2_port *sky2 = netdev_priv(dev);
2485 struct sky2_hw *hw = sky2->hw;
2486 unsigned port = sky2->port;
2487 struct dev_mc_list *list = dev->mc_list;
2488 u16 reg;
2489 u8 filter[8];
2490
2491 memset(filter, 0, sizeof(filter));
2492
2493 reg = gma_read16(hw, port, GM_RX_CTRL);
2494 reg |= GM_RXCR_UCF_ENA;
2495
d571b694 2496 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2497 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2498 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2499 memset(filter, 0xff, sizeof(filter));
793b883e 2500 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2501 reg &= ~GM_RXCR_MCF_ENA;
2502 else {
2503 int i;
2504 reg |= GM_RXCR_MCF_ENA;
2505
2506 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2507 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2508 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2509 }
2510 }
2511
cd28ab6a 2512 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2513 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2514 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2515 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2516 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2517 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2518 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2519 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2520
2521 gma_write16(hw, port, GM_RX_CTRL, reg);
2522}
2523
2524/* Can have one global because blinking is controlled by
2525 * ethtool and that is always under RTNL mutex
2526 */
91c86df5 2527static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2528{
793b883e
SH		 2529 u16 pg;
2530
793b883e
SH		 2531 switch (hw->chip_id) {
2532 case CHIP_ID_YUKON_XL:
2533 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2534 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2535 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2536 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2537 PHY_M_LEDC_INIT_CTRL(7) |
2538 PHY_M_LEDC_STA1_CTRL(7) |
2539 PHY_M_LEDC_STA0_CTRL(7))
2540 : 0);
2541
2542 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2543 break;
2544
2545 default:
2546 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2547 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2548 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2549 PHY_M_LED_MO_10(MO_LED_ON) |
2550 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2551 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2552 PHY_M_LED_MO_RX(MO_LED_ON)
2553 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2554 PHY_M_LED_MO_10(MO_LED_OFF) |
2555 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2556 PHY_M_LED_MO_1000(MO_LED_OFF) |
2557 PHY_M_LED_MO_RX(MO_LED_OFF));
2558
793b883e 2559 }
cd28ab6a
SH		 2560}
2561
2562/* blink LED's for finding board */
2563static int sky2_phys_id(struct net_device *dev, u32 data)
2564{
2565 struct sky2_port *sky2 = netdev_priv(dev);
2566 struct sky2_hw *hw = sky2->hw;
2567 unsigned port = sky2->port;
793b883e 2568 u16 ledctrl, ledover = 0;
cd28ab6a 2569 long ms;
91c86df5 2570 int interrupted;
cd28ab6a
SH		 2571 int onoff = 1;
2572
793b883e 2573 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2574 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2575 else
2576 ms = data * 1000;
2577
2578 /* save initial values */
91c86df5 2579 down(&sky2->phy_sema);
793b883e
SH		 2580 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2581 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2582 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2583 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2585 } else {
2586 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2587 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2588 }
cd28ab6a 2589
91c86df5
SH		 2590 interrupted = 0;
2591 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2592 sky2_led(hw, port, onoff);
2593 onoff = !onoff;
2594
91c86df5
SH		 2595 up(&sky2->phy_sema);
2596 interrupted = msleep_interruptible(250);
2597 down(&sky2->phy_sema);
2598
cd28ab6a
SH		 2599 ms -= 250;
2600 }
2601
2602 /* resume regularly scheduled programming */
793b883e
SH		 2603 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2604 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2605 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2606 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2607 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2608 } else {
2609 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2610 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2611 }
91c86df5 2612 up(&sky2->phy_sema);
cd28ab6a
SH		 2613
2614 return 0;
2615}
2616
2617static void sky2_get_pauseparam(struct net_device *dev,
2618 struct ethtool_pauseparam *ecmd)
2619{
2620 struct sky2_port *sky2 = netdev_priv(dev);
2621
2622 ecmd->tx_pause = sky2->tx_pause;
2623 ecmd->rx_pause = sky2->rx_pause;
2624 ecmd->autoneg = sky2->autoneg;
2625}
2626
2627static int sky2_set_pauseparam(struct net_device *dev,
2628 struct ethtool_pauseparam *ecmd)
2629{
2630 struct sky2_port *sky2 = netdev_priv(dev);
2631 int err = 0;
2632
2633 sky2->autoneg = ecmd->autoneg;
2634 sky2->tx_pause = ecmd->tx_pause != 0;
2635 sky2->rx_pause = ecmd->rx_pause != 0;
2636
2637 if (netif_running(dev)) {
2638 sky2_down(dev);
2639 err = sky2_up(dev);
2640 }
2641
2642 return err;
2643}
2644
2645#ifdef CONFIG_PM
2646static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2647{
2648 struct sky2_port *sky2 = netdev_priv(dev);
2649
2650 wol->supported = WAKE_MAGIC;
2651 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2652}
2653
2654static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2655{
2656 struct sky2_port *sky2 = netdev_priv(dev);
2657 struct sky2_hw *hw = sky2->hw;
2658
2659 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2660 return -EOPNOTSUPP;
2661
2662 sky2->wol = wol->wolopts == WAKE_MAGIC;
2663
2664 if (sky2->wol) {
2665 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2666
2667 sky2_write16(hw, WOL_CTRL_STAT,
2668 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2669 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2670 } else
2671 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2672
2673 return 0;
2674}
2675#endif
2676
fb17358f
SH		 2677static int sky2_get_coalesce(struct net_device *dev,
2678 struct ethtool_coalesce *ecmd)
2679{
2680 struct sky2_port *sky2 = netdev_priv(dev);
2681 struct sky2_hw *hw = sky2->hw;
2682
2683 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2684 ecmd->tx_coalesce_usecs = 0;
2685 else {
2686 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2687 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2688 }
2689 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2690
2691 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2692 ecmd->rx_coalesce_usecs = 0;
2693 else {
2694 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2695 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2696 }
2697 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2698
2699 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2700 ecmd->rx_coalesce_usecs_irq = 0;
2701 else {
2702 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2703 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2704 }
2705
2706 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2707
2708 return 0;
2709}
2710
2711/* Note: this affect both ports */
2712static int sky2_set_coalesce(struct net_device *dev,
2713 struct ethtool_coalesce *ecmd)
2714{
2715 struct sky2_port *sky2 = netdev_priv(dev);
2716 struct sky2_hw *hw = sky2->hw;
2717 const u32 tmin = sky2_clk2us(hw, 1);
2718 const u32 tmax = 5000;
2719
2720 if (ecmd->tx_coalesce_usecs != 0 &&
2721 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2722 return -EINVAL;
2723
2724 if (ecmd->rx_coalesce_usecs != 0 &&
2725 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2726 return -EINVAL;
2727
2728 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2729 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2730 return -EINVAL;
2731
2732 if (ecmd->tx_max_coalesced_frames > 0xffff)
2733 return -EINVAL;
2734 if (ecmd->rx_max_coalesced_frames > 0xff)
2735 return -EINVAL;
2736 if (ecmd->rx_max_coalesced_frames_irq > 0xff)
2737 return -EINVAL;
2738
2739 if (ecmd->tx_coalesce_usecs == 0)
2740 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2741 else {
2742 sky2_write32(hw, STAT_TX_TIMER_INI,
2743 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2744 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2745 }
2746 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2747
2748 if (ecmd->rx_coalesce_usecs == 0)
2749 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2750 else {
2751 sky2_write32(hw, STAT_LEV_TIMER_INI,
2752 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2753 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2754 }
2755 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2756
2757 if (ecmd->rx_coalesce_usecs_irq == 0)
2758 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2759 else {
2760 sky2_write32(hw, STAT_TX_TIMER_INI,
2761 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2762 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2763 }
2764 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2765 return 0;
2766}
2767
793b883e
SH		 2768static void sky2_get_ringparam(struct net_device *dev,
2769 struct ethtool_ringparam *ering)
2770{
2771 struct sky2_port *sky2 = netdev_priv(dev);
2772
2773 ering->rx_max_pending = RX_MAX_PENDING;
2774 ering->rx_mini_max_pending = 0;
2775 ering->rx_jumbo_max_pending = 0;
2776 ering->tx_max_pending = TX_RING_SIZE - 1;
2777
2778 ering->rx_pending = sky2->rx_pending;
2779 ering->rx_mini_pending = 0;
2780 ering->rx_jumbo_pending = 0;
2781 ering->tx_pending = sky2->tx_pending;
2782}
2783
2784static int sky2_set_ringparam(struct net_device *dev,
2785 struct ethtool_ringparam *ering)
2786{
2787 struct sky2_port *sky2 = netdev_priv(dev);
2788 int err = 0;
2789
2790 if (ering->rx_pending > RX_MAX_PENDING ||
2791 ering->rx_pending < 8 ||
2792 ering->tx_pending < MAX_SKB_TX_LE ||
2793 ering->tx_pending > TX_RING_SIZE - 1)
2794 return -EINVAL;
2795
2796 if (netif_running(dev))
2797 sky2_down(dev);
2798
2799 sky2->rx_pending = ering->rx_pending;
2800 sky2->tx_pending = ering->tx_pending;
2801
2802 if (netif_running(dev))
2803 err = sky2_up(dev);
2804
2805 return err;
2806}
2807
793b883e
SH		 2808static int sky2_get_regs_len(struct net_device *dev)
2809{
6e4cbb34 2810 return 0x4000;
793b883e
SH		 2811}
2812
2813/*
2814 * Returns copy of control register region
6e4cbb34 2815 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2816 */
2817static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2818 void *p)
2819{
2820 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2821 const void __iomem *io = sky2->hw->regs;
793b883e 2822
6e4cbb34 2823 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 2824 regs->version = 1;
6e4cbb34 2825 memset(p, 0, regs->len);
793b883e 2826
6e4cbb34
SH		 2827 memcpy_fromio(p, io, B3_RAM_ADDR);
2828
2829 memcpy_fromio(p + B3_RI_WTO_R1,
2830 io + B3_RI_WTO_R1,
2831 regs->len - B3_RI_WTO_R1);
793b883e 2832}
cd28ab6a
SH		 2833
2834static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 2835 .get_settings = sky2_get_settings,
2836 .set_settings = sky2_set_settings,
2837 .get_drvinfo = sky2_get_drvinfo,
2838 .get_msglevel = sky2_get_msglevel,
2839 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 2840 .nway_reset = sky2_nway_reset,
793b883e
SH		 2841 .get_regs_len = sky2_get_regs_len,
2842 .get_regs = sky2_get_regs,
2843 .get_link = ethtool_op_get_link,
2844 .get_sg = ethtool_op_get_sg,
2845 .set_sg = ethtool_op_set_sg,
2846 .get_tx_csum = ethtool_op_get_tx_csum,
2847 .set_tx_csum = ethtool_op_set_tx_csum,
2848 .get_tso = ethtool_op_get_tso,
2849 .set_tso = ethtool_op_set_tso,
2850 .get_rx_csum = sky2_get_rx_csum,
2851 .set_rx_csum = sky2_set_rx_csum,
2852 .get_strings = sky2_get_strings,
fb17358f
SH		 2853 .get_coalesce = sky2_get_coalesce,
2854 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 2855 .get_ringparam = sky2_get_ringparam,
2856 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 2857 .get_pauseparam = sky2_get_pauseparam,
2858 .set_pauseparam = sky2_set_pauseparam,
2859#ifdef CONFIG_PM
793b883e
SH		 2860 .get_wol = sky2_get_wol,
2861 .set_wol = sky2_set_wol,
cd28ab6a 2862#endif
793b883e 2863 .phys_id = sky2_phys_id,
cd28ab6a
SH		 2864 .get_stats_count = sky2_get_stats_count,
2865 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 2866 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 2867};
2868
2869/* Initialize network device */
2870static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2871 unsigned port, int highmem)
2872{
2873 struct sky2_port *sky2;
2874 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2875
2876 if (!dev) {
2877 printk(KERN_ERR "sky2 etherdev alloc failed");
2878 return NULL;
2879 }
2880
2881 SET_MODULE_OWNER(dev);
2882 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 2883 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 2884 dev->open = sky2_up;
2885 dev->stop = sky2_down;
ef743d33 2886 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 2887 dev->hard_start_xmit = sky2_xmit_frame;
2888 dev->get_stats = sky2_get_stats;
2889 dev->set_multicast_list = sky2_set_multicast;
2890 dev->set_mac_address = sky2_set_mac_address;
2891 dev->change_mtu = sky2_change_mtu;
2892 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2893 dev->tx_timeout = sky2_tx_timeout;
2894 dev->watchdog_timeo = TX_WATCHDOG;
2895 if (port == 0)
2896 dev->poll = sky2_poll;
2897 dev->weight = NAPI_WEIGHT;
2898#ifdef CONFIG_NET_POLL_CONTROLLER
2899 dev->poll_controller = sky2_netpoll;
2900#endif
cd28ab6a
SH		 2901
2902 sky2 = netdev_priv(dev);
2903 sky2->netdev = dev;
2904 sky2->hw = hw;
2905 sky2->msg_enable = netif_msg_init(debug, default_msg);
2906
2907 spin_lock_init(&sky2->tx_lock);
2908 /* Auto speed and flow control */
2909 sky2->autoneg = AUTONEG_ENABLE;
2910 sky2->tx_pause = 0;
2911 sky2->rx_pause = 1;
2912 sky2->duplex = -1;
2913 sky2->speed = -1;
2914 sky2->advertising = sky2_supported_modes(hw);
2915 sky2->rx_csum = 1;
91c86df5
SH		 2916 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
2917 init_MUTEX(&sky2->phy_sema);
793b883e
SH		 2918 sky2->tx_pending = TX_DEF_PENDING;
2919 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
734d1868 2920 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 2921
2922 hw->dev[port] = dev;
2923
2924 sky2->port = port;
2925
5a5b1ea0
SH		 2926 dev->features |= NETIF_F_LLTX;
2927 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
2928 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 2929 if (highmem)
2930 dev->features |= NETIF_F_HIGHDMA;
793b883e 2931 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 2932
d1f13708
SH		 2933#ifdef SKY2_VLAN_TAG_USED
2934 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2935 dev->vlan_rx_register = sky2_vlan_rx_register;
2936 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
2937#endif
2938
cd28ab6a 2939 /* read the mac address */
793b883e 2940 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 2941 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 2942
2943 /* device is off until link detection */
2944 netif_carrier_off(dev);
2945 netif_stop_queue(dev);
2946
2947 return dev;
2948}
2949
2950static inline void sky2_show_addr(struct net_device *dev)
2951{
2952 const struct sky2_port *sky2 = netdev_priv(dev);
2953
2954 if (netif_msg_probe(sky2))
2955 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2956 dev->name,
2957 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2958 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2959}
2960
2961static int __devinit sky2_probe(struct pci_dev *pdev,
2962 const struct pci_device_id *ent)
2963{
793b883e 2964 struct net_device *dev, *dev1 = NULL;
cd28ab6a 2965 struct sky2_hw *hw;
5afa0a9c 2966 int err, pm_cap, using_dac = 0;
cd28ab6a 2967
793b883e
SH		 2968 err = pci_enable_device(pdev);
2969 if (err) {
cd28ab6a
SH		 2970 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2971 pci_name(pdev));
2972 goto err_out;
2973 }
2974
793b883e
SH		 2975 err = pci_request_regions(pdev, DRV_NAME);
2976 if (err) {
cd28ab6a
SH		 2977 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2978 pci_name(pdev));
793b883e 2979 goto err_out;
cd28ab6a
SH		 2980 }
2981
2982 pci_set_master(pdev);
2983
5afa0a9c
SH		 2984 /* Find power-management capability. */
2985 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2986 if (pm_cap == 0) {
2987 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
2988 "aborting.\n");
2989 err = -EIO;
2990 goto err_out_free_regions;
2991 }
2992
cd28ab6a
SH		 2993 if (sizeof(dma_addr_t) > sizeof(u32)) {
2994 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2995 if (!err)
2996 using_dac = 1;
2997 }
2998
2999 if (!using_dac) {
3000 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3001 if (err) {
3002 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3003 pci_name(pdev));
3004 goto err_out_free_regions;
3005 }
3006 }
cd28ab6a 3007#ifdef __BIG_ENDIAN
d571b694 3008 /* byte swap descriptors in hardware */
cd28ab6a
SH		 3009 {
3010 u32 reg;
3011
3012 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3013 reg |= PCI_REV_DESC;
3014 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3015 }
3016#endif
3017
3018 err = -ENOMEM;
3019 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3020 if (!hw) {
3021 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3022 pci_name(pdev));
3023 goto err_out_free_regions;
3024 }
3025
3026 memset(hw, 0, sizeof(*hw));
3027 hw->pdev = pdev;
cd28ab6a
SH		 3028
3029 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3030 if (!hw->regs) {
3031 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3032 pci_name(pdev));
3033 goto err_out_free_hw;
3034 }
5afa0a9c 3035 hw->pm_cap = pm_cap;
cd28ab6a 3036
cd28ab6a
SH		 3037 err = sky2_reset(hw);
3038 if (err)
793b883e 3039 goto err_out_iounmap;
cd28ab6a 3040
5f4f9dc1
SH		 3041 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3042 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
92f965e8 3043 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3044 hw->chip_id, hw->chip_rev);
cd28ab6a 3045
793b883e
SH		 3046 dev = sky2_init_netdev(hw, 0, using_dac);
3047 if (!dev)
cd28ab6a
SH		 3048 goto err_out_free_pci;
3049
793b883e
SH		 3050 err = register_netdev(dev);
3051 if (err) {
cd28ab6a
SH		 3052 printk(KERN_ERR PFX "%s: cannot register net device\n",
3053 pci_name(pdev));
3054 goto err_out_free_netdev;
3055 }
3056
3057 sky2_show_addr(dev);
3058
3059 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3060 if (register_netdev(dev1) == 0)
3061 sky2_show_addr(dev1);
3062 else {
3063 /* Failure to register second port need not be fatal */
793b883e
SH		 3064 printk(KERN_WARNING PFX
3065 "register of second port failed\n");
cd28ab6a
SH		 3066 hw->dev[1] = NULL;
3067 free_netdev(dev1);
3068 }
3069 }
3070
793b883e
SH		 3071 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3072 if (err) {
3073 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3074 pci_name(pdev), pdev->irq);
3075 goto err_out_unregister;
3076 }
3077
3078 hw->intr_mask = Y2_IS_BASE;
3079 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3080
3081 pci_set_drvdata(pdev, hw);
3082
cd28ab6a
SH		 3083 return 0;
3084
793b883e
SH		 3085err_out_unregister:
3086 if (dev1) {
3087 unregister_netdev(dev1);
3088 free_netdev(dev1);
3089 }
3090 unregister_netdev(dev);
cd28ab6a
SH		 3091err_out_free_netdev:
3092 free_netdev(dev);
cd28ab6a 3093err_out_free_pci:
793b883e 3094 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3095 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3096err_out_iounmap:
3097 iounmap(hw->regs);
3098err_out_free_hw:
3099 kfree(hw);
3100err_out_free_regions:
3101 pci_release_regions(pdev);
cd28ab6a 3102 pci_disable_device(pdev);
cd28ab6a
SH		 3103err_out:
3104 return err;
3105}
3106
3107static void __devexit sky2_remove(struct pci_dev *pdev)
3108{
793b883e 3109 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3110 struct net_device *dev0, *dev1;
3111
793b883e 3112 if (!hw)
cd28ab6a
SH		 3113 return;
3114
cd28ab6a 3115 dev0 = hw->dev[0];
793b883e
SH		 3116 dev1 = hw->dev[1];
3117 if (dev1)
3118 unregister_netdev(dev1);
cd28ab6a
SH		 3119 unregister_netdev(dev0);
3120
793b883e 3121 sky2_write32(hw, B0_IMSK, 0);
5afa0a9c 3122 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3123 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3124 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3125 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3126
3127 free_irq(pdev->irq, hw);
793b883e 3128 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3129 pci_release_regions(pdev);
3130 pci_disable_device(pdev);
793b883e 3131
cd28ab6a
SH		 3132 if (dev1)
3133 free_netdev(dev1);
3134 free_netdev(dev0);
3135 iounmap(hw->regs);
3136 kfree(hw);
5afa0a9c 3137
cd28ab6a
SH		 3138 pci_set_drvdata(pdev, NULL);
3139}
3140
3141#ifdef CONFIG_PM
3142static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3143{
793b883e 3144 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3145 int i;
cd28ab6a
SH		 3146
3147 for (i = 0; i < 2; i++) {
3148 struct net_device *dev = hw->dev[i];
3149
3150 if (dev) {
5afa0a9c
SH		 3151 if (!netif_running(dev))
3152 continue;
3153
3154 sky2_down(dev);
cd28ab6a 3155 netif_device_detach(dev);
cd28ab6a
SH		 3156 }
3157 }
3158
5afa0a9c 3159 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 3160}
3161
3162static int sky2_resume(struct pci_dev *pdev)
3163{
793b883e 3164 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3165 int i;
3166
cd28ab6a
SH		 3167 pci_restore_state(pdev);
3168 pci_enable_wake(pdev, PCI_D0, 0);
5afa0a9c 3169 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 3170
3171 sky2_reset(hw);
3172
3173 for (i = 0; i < 2; i++) {
3174 struct net_device *dev = hw->dev[i];
3175 if (dev) {
5afa0a9c
SH		 3176 if (netif_running(dev)) {
3177 netif_device_attach(dev);
cd28ab6a 3178 sky2_up(dev);
5afa0a9c 3179 }
cd28ab6a
SH		 3180 }
3181 }
3182 return 0;
3183}
3184#endif
3185
3186static struct pci_driver sky2_driver = {
793b883e
SH		 3187 .name = DRV_NAME,
3188 .id_table = sky2_id_table,
3189 .probe = sky2_probe,
3190 .remove = __devexit_p(sky2_remove),
cd28ab6a 3191#ifdef CONFIG_PM
793b883e
SH		 3192 .suspend = sky2_suspend,
3193 .resume = sky2_resume,
cd28ab6a
SH		 3194#endif
3195};
3196
3197static int __init sky2_init_module(void)
3198{
50241c4c 3199 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3200}
3201
3202static void __exit sky2_cleanup_module(void)
3203{
3204 pci_unregister_driver(&sky2_driver);
3205}
3206
3207module_init(sky2_init_module);
3208module_exit(sky2_cleanup_module);
3209
3210MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3211MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3212MODULE_LICENSE("GPL");
5f4f9dc1 3213MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree