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Commit | Line | Data |
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cd28ab6a SH |
1 | /* |
2 | * New driver for Marvell Yukon 2 chipset. | |
3 | * Based on earlier sk98lin, and skge driver. | |
4 | * | |
5 | * This driver intentionally does not support all the features | |
6 | * of the original driver such as link fail-over and link management because | |
7 | * those should be done at higher levels. | |
8 | * | |
9 | * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
793b883e | 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
cd28ab6a SH |
19 | * GNU General Public License for more details. |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
26 | /* | |
27 | * TODO | |
28 | * - coalescing setting? | |
793b883e | 29 | * - vlan support |
cd28ab6a SH |
30 | * |
31 | * TOTEST | |
793b883e | 32 | * - variable ring size |
cd28ab6a SH |
33 | * - speed setting |
34 | * - power management | |
793b883e | 35 | * - netpoll |
cd28ab6a SH |
36 | */ |
37 | ||
38 | #include <linux/config.h> | |
793b883e | 39 | #include <linux/crc32.h> |
cd28ab6a SH |
40 | #include <linux/kernel.h> |
41 | #include <linux/version.h> | |
42 | #include <linux/module.h> | |
43 | #include <linux/netdevice.h> | |
44 | #include <linux/etherdevice.h> | |
45 | #include <linux/ethtool.h> | |
46 | #include <linux/pci.h> | |
47 | #include <linux/ip.h> | |
48 | #include <linux/tcp.h> | |
49 | #include <linux/in.h> | |
50 | #include <linux/delay.h> | |
cd28ab6a SH |
51 | |
52 | #include <asm/irq.h> | |
53 | ||
54 | #include "sky2.h" | |
55 | ||
56 | #define DRV_NAME "sky2" | |
ecfd7f32 | 57 | #define DRV_VERSION "0.5" |
cd28ab6a SH |
58 | #define PFX DRV_NAME " " |
59 | ||
60 | /* | |
61 | * The Yukon II chipset takes 64 bit command blocks (called list elements) | |
62 | * that are organized into three (receive, transmit, status) different rings | |
63 | * similar to Tigon3. A transmit can require several elements; | |
64 | * a receive requires one (or two if using 64 bit dma). | |
65 | */ | |
66 | ||
67 | #ifdef CONFIG_SKY2_EC_A1 | |
68 | #define is_ec_a1(hw) \ | |
69 | ((hw)->chip_id == CHIP_ID_YUKON_EC && \ | |
70 | (hw)->chip_rev == CHIP_REV_YU_EC_A1) | |
71 | #else | |
72 | #define is_ec_a1(hw) 0 | |
73 | #endif | |
74 | ||
793b883e | 75 | #define RX_LE_SIZE 256 |
cd28ab6a | 76 | #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
793b883e SH |
77 | #define RX_MAX_PENDING (RX_LE_SIZE/2 - 1) |
78 | #define RX_DEF_PENDING 128 | |
79e57d32 | 79 | #define RX_COPY_THRESHOLD 256 |
793b883e SH |
80 | |
81 | #define TX_RING_SIZE 512 | |
82 | #define TX_DEF_PENDING (TX_RING_SIZE - 1) | |
83 | #define TX_MIN_PENDING 64 | |
84 | #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS) | |
cd28ab6a | 85 | |
793b883e | 86 | #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */ |
cd28ab6a SH |
87 | #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) |
88 | #define ETH_JUMBO_MTU 9000 | |
89 | #define TX_WATCHDOG (5 * HZ) | |
90 | #define NAPI_WEIGHT 64 | |
91 | #define PHY_RETRIES 1000 | |
92 | ||
93 | static const u32 default_msg = | |
793b883e SH |
94 | NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
95 | | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | |
96 | | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR; | |
cd28ab6a | 97 | |
793b883e | 98 | static int debug = -1; /* defaults above */ |
cd28ab6a SH |
99 | module_param(debug, int, 0); |
100 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
101 | ||
102 | static const struct pci_device_id sky2_id_table[] = { | |
793b883e | 103 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, |
cd28ab6a SH |
104 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, |
105 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, | |
106 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, | |
107 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, | |
108 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, | |
109 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, | |
110 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, | |
111 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, | |
112 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, | |
113 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, | |
114 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, | |
115 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, | |
116 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, | |
117 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, | |
118 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, | |
119 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, | |
120 | { 0 } | |
121 | }; | |
793b883e | 122 | |
cd28ab6a SH |
123 | MODULE_DEVICE_TABLE(pci, sky2_id_table); |
124 | ||
125 | /* Avoid conditionals by using array */ | |
126 | static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; | |
127 | static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; | |
128 | ||
793b883e SH |
129 | static const char *yukon_name[] = { |
130 | [CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */ | |
131 | [CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */ | |
132 | [CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */ | |
cd28ab6a | 133 | |
793b883e SH |
134 | [CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */ |
135 | [CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */ | |
136 | }; | |
137 | ||
138 | ||
139 | /* Access to external PHY */ | |
cd28ab6a SH |
140 | static void gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) |
141 | { | |
142 | int i; | |
143 | ||
144 | gma_write16(hw, port, GM_SMI_DATA, val); | |
145 | gma_write16(hw, port, GM_SMI_CTRL, | |
146 | GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); | |
147 | ||
148 | for (i = 0; i < PHY_RETRIES; i++) { | |
cd28ab6a | 149 | if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) |
793b883e SH |
150 | return; |
151 | udelay(1); | |
cd28ab6a | 152 | } |
793b883e | 153 | printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name); |
cd28ab6a SH |
154 | } |
155 | ||
156 | static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) | |
157 | { | |
158 | int i; | |
159 | ||
793b883e | 160 | gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) |
cd28ab6a SH |
161 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); |
162 | ||
163 | for (i = 0; i < PHY_RETRIES; i++) { | |
cd28ab6a SH |
164 | if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) |
165 | goto ready; | |
793b883e | 166 | udelay(1); |
cd28ab6a SH |
167 | } |
168 | ||
793b883e SH |
169 | printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name); |
170 | ready: | |
cd28ab6a SH |
171 | return gma_read16(hw, port, GM_SMI_DATA); |
172 | } | |
173 | ||
174 | static void sky2_phy_reset(struct sky2_hw *hw, unsigned port) | |
175 | { | |
176 | u16 reg; | |
177 | ||
178 | /* disable all GMAC IRQ's */ | |
179 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); | |
180 | /* disable PHY IRQs */ | |
181 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
793b883e | 182 | |
cd28ab6a SH |
183 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ |
184 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
185 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
186 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
187 | ||
188 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
189 | reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; | |
190 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
191 | } | |
192 | ||
193 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |
194 | { | |
195 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
793b883e | 196 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover; |
cd28ab6a | 197 | |
793b883e | 198 | if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) { |
cd28ab6a SH |
199 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
200 | ||
201 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
793b883e | 202 | PHY_M_EC_MAC_S_MSK); |
cd28ab6a SH |
203 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); |
204 | ||
205 | if (hw->chip_id == CHIP_ID_YUKON_EC) | |
206 | ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; | |
207 | else | |
208 | ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3); | |
209 | ||
210 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); | |
211 | } | |
212 | ||
213 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
214 | if (hw->copper) { | |
215 | if (hw->chip_id == CHIP_ID_YUKON_FE) { | |
216 | /* enable automatic crossover */ | |
217 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; | |
218 | } else { | |
219 | /* disable energy detect */ | |
220 | ctrl &= ~PHY_M_PC_EN_DET_MSK; | |
221 | ||
222 | /* enable automatic crossover */ | |
223 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); | |
224 | ||
225 | if (sky2->autoneg == AUTONEG_ENABLE && | |
226 | hw->chip_id == CHIP_ID_YUKON_XL) { | |
227 | ctrl &= ~PHY_M_PC_DSC_MSK; | |
228 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; | |
229 | } | |
230 | } | |
231 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
232 | } else { | |
233 | /* workaround for deviation #4.88 (CRC errors) */ | |
234 | /* disable Automatic Crossover */ | |
235 | ||
236 | ctrl &= ~PHY_M_PC_MDIX_MSK; | |
237 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
238 | ||
239 | if (hw->chip_id == CHIP_ID_YUKON_XL) { | |
240 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ | |
241 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
242 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
243 | ctrl &= ~PHY_M_MAC_MD_MSK; | |
244 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); | |
245 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
246 | ||
247 | /* select page 1 to access Fiber registers */ | |
248 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); | |
249 | } | |
cd28ab6a SH |
250 | } |
251 | ||
252 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
253 | if (sky2->autoneg == AUTONEG_DISABLE) | |
254 | ctrl &= ~PHY_CT_ANE; | |
255 | else | |
256 | ctrl |= PHY_CT_ANE; | |
257 | ||
258 | ctrl |= PHY_CT_RESET; | |
259 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
260 | ||
261 | ctrl = 0; | |
262 | ct1000 = 0; | |
263 | adv = PHY_AN_CSMA; | |
264 | ||
265 | if (sky2->autoneg == AUTONEG_ENABLE) { | |
266 | if (hw->copper) { | |
267 | if (sky2->advertising & ADVERTISED_1000baseT_Full) | |
268 | ct1000 |= PHY_M_1000C_AFD; | |
269 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
270 | ct1000 |= PHY_M_1000C_AHD; | |
271 | if (sky2->advertising & ADVERTISED_100baseT_Full) | |
272 | adv |= PHY_M_AN_100_FD; | |
273 | if (sky2->advertising & ADVERTISED_100baseT_Half) | |
274 | adv |= PHY_M_AN_100_HD; | |
275 | if (sky2->advertising & ADVERTISED_10baseT_Full) | |
276 | adv |= PHY_M_AN_10_FD; | |
277 | if (sky2->advertising & ADVERTISED_10baseT_Half) | |
278 | adv |= PHY_M_AN_10_HD; | |
793b883e | 279 | } else /* special defines for FIBER (88E1011S only) */ |
cd28ab6a SH |
280 | adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; |
281 | ||
282 | /* Set Flow-control capabilities */ | |
283 | if (sky2->tx_pause && sky2->rx_pause) | |
793b883e | 284 | adv |= PHY_AN_PAUSE_CAP; /* symmetric */ |
cd28ab6a | 285 | else if (sky2->rx_pause && !sky2->tx_pause) |
793b883e | 286 | adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP; |
cd28ab6a SH |
287 | else if (!sky2->rx_pause && sky2->tx_pause) |
288 | adv |= PHY_AN_PAUSE_ASYM; /* local */ | |
289 | ||
290 | /* Restart Auto-negotiation */ | |
291 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
292 | } else { | |
293 | /* forced speed/duplex settings */ | |
294 | ct1000 = PHY_M_1000C_MSE; | |
295 | ||
296 | if (sky2->duplex == DUPLEX_FULL) | |
297 | ctrl |= PHY_CT_DUP_MD; | |
298 | ||
299 | switch (sky2->speed) { | |
300 | case SPEED_1000: | |
301 | ctrl |= PHY_CT_SP1000; | |
302 | break; | |
303 | case SPEED_100: | |
304 | ctrl |= PHY_CT_SP100; | |
305 | break; | |
306 | } | |
307 | ||
308 | ctrl |= PHY_CT_RESET; | |
309 | } | |
310 | ||
311 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
312 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); | |
313 | ||
314 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); | |
315 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
316 | ||
317 | /* Setup Phy LED's */ | |
318 | ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); | |
319 | ledover = 0; | |
320 | ||
321 | switch (hw->chip_id) { | |
322 | case CHIP_ID_YUKON_FE: | |
323 | /* on 88E3082 these bits are at 11..9 (shifted left) */ | |
324 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; | |
325 | ||
326 | ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); | |
327 | ||
328 | /* delete ACT LED control bits */ | |
329 | ctrl &= ~PHY_M_FELP_LED1_MSK; | |
330 | /* change ACT LED control to blink mode */ | |
331 | ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); | |
332 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
333 | break; | |
334 | ||
335 | case CHIP_ID_YUKON_XL: | |
793b883e | 336 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a SH |
337 | |
338 | /* select page 3 to access LED control register */ | |
339 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
340 | ||
341 | /* set LED Function Control register */ | |
793b883e SH |
342 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ |
343 | PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ | |
344 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
345 | PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ | |
cd28ab6a SH |
346 | |
347 | /* set Polarity Control register */ | |
348 | gm_phy_write(hw, port, PHY_MARV_PHY_STAT, | |
793b883e SH |
349 | (PHY_M_POLC_LS1_P_MIX(4) | |
350 | PHY_M_POLC_IS0_P_MIX(4) | | |
351 | PHY_M_POLC_LOS_CTRL(2) | | |
352 | PHY_M_POLC_INIT_CTRL(2) | | |
353 | PHY_M_POLC_STA1_CTRL(2) | | |
354 | PHY_M_POLC_STA0_CTRL(2))); | |
cd28ab6a SH |
355 | |
356 | /* restore page register */ | |
793b883e | 357 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
cd28ab6a SH |
358 | break; |
359 | ||
360 | default: | |
361 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ | |
362 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; | |
363 | /* turn off the Rx LED (LED_RX) */ | |
364 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); | |
365 | } | |
366 | ||
367 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
368 | ||
369 | if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { | |
370 | /* turn on 100 Mbps LED (LED_LINK100) */ | |
371 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); | |
372 | } | |
373 | ||
374 | if (ledover) | |
375 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
376 | ||
377 | /* Enable phy interrupt on autonegotiation complete (or link up) */ | |
378 | if (sky2->autoneg == AUTONEG_ENABLE) | |
379 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); | |
380 | else | |
381 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
382 | } | |
383 | ||
384 | static void sky2_mac_init(struct sky2_hw *hw, unsigned port) | |
385 | { | |
386 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
387 | u16 reg; | |
388 | int i; | |
389 | const u8 *addr = hw->dev[port]->dev_addr; | |
390 | ||
391 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | |
392 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
393 | ||
394 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
395 | ||
793b883e | 396 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) { |
cd28ab6a SH |
397 | /* WA DEV_472 -- looks like crossed wires on port 2 */ |
398 | /* clear GMAC 1 Control reset */ | |
399 | sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); | |
400 | do { | |
401 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); | |
402 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); | |
403 | } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || | |
404 | gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || | |
405 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); | |
406 | } | |
407 | ||
cd28ab6a SH |
408 | if (sky2->autoneg == AUTONEG_DISABLE) { |
409 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
410 | reg |= GM_GPCR_AU_ALL_DIS; | |
411 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
412 | gma_read16(hw, port, GM_GP_CTRL); | |
413 | ||
cd28ab6a SH |
414 | switch (sky2->speed) { |
415 | case SPEED_1000: | |
416 | reg |= GM_GPCR_SPEED_1000; | |
417 | /* fallthru */ | |
418 | case SPEED_100: | |
419 | reg |= GM_GPCR_SPEED_100; | |
420 | } | |
421 | ||
422 | if (sky2->duplex == DUPLEX_FULL) | |
423 | reg |= GM_GPCR_DUP_FULL; | |
424 | } else | |
425 | reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; | |
426 | ||
427 | if (!sky2->tx_pause && !sky2->rx_pause) { | |
428 | sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
793b883e SH |
429 | reg |= |
430 | GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
431 | } else if (sky2->tx_pause && !sky2->rx_pause) { | |
cd28ab6a SH |
432 | /* disable Rx flow-control */ |
433 | reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
434 | } | |
435 | ||
436 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
437 | ||
793b883e | 438 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
cd28ab6a SH |
439 | |
440 | spin_lock_bh(&hw->phy_lock); | |
441 | sky2_phy_init(hw, port); | |
442 | spin_unlock_bh(&hw->phy_lock); | |
443 | ||
444 | /* MIB clear */ | |
445 | reg = gma_read16(hw, port, GM_PHY_ADDR); | |
446 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
447 | ||
448 | for (i = 0; i < GM_MIB_CNT_SIZE; i++) | |
793b883e | 449 | gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i); |
cd28ab6a SH |
450 | gma_write16(hw, port, GM_PHY_ADDR, reg); |
451 | ||
452 | /* transmit control */ | |
453 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); | |
454 | ||
455 | /* receive control reg: unicast + multicast + no FCS */ | |
456 | gma_write16(hw, port, GM_RX_CTRL, | |
793b883e | 457 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
cd28ab6a SH |
458 | |
459 | /* transmit flow control */ | |
460 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); | |
461 | ||
462 | /* transmit parameter */ | |
463 | gma_write16(hw, port, GM_TX_PARAM, | |
464 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | | |
465 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
466 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | | |
467 | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); | |
468 | ||
469 | /* serial mode register */ | |
470 | reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | | |
6b1a3aef | 471 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); |
cd28ab6a | 472 | |
6b1a3aef | 473 | if (hw->dev[port]->mtu > ETH_DATA_LEN) |
cd28ab6a SH |
474 | reg |= GM_SMOD_JUMBO_ENA; |
475 | ||
476 | gma_write16(hw, port, GM_SERIAL_MODE, reg); | |
477 | ||
cd28ab6a SH |
478 | /* virtual address for data */ |
479 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); | |
480 | ||
793b883e SH |
481 | /* physical address: used for pause frames */ |
482 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); | |
483 | ||
484 | /* ignore counter overflows */ | |
cd28ab6a SH |
485 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
486 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
487 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
488 | ||
489 | /* Configure Rx MAC FIFO */ | |
490 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); | |
793b883e | 491 | sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T), |
cd28ab6a SH |
492 | GMF_OPER_ON | GMF_RX_F_FL_ON); |
493 | ||
793b883e SH |
494 | /* Flush Rx MAC FIFO on any flowcontrol or error */ |
495 | reg = GMR_FS_ANY_ERR; | |
cd28ab6a SH |
496 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1) |
497 | reg = 0; /* WA Dev #4115 */ | |
498 | ||
499 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg); | |
793b883e SH |
500 | /* Set threshold to 0xa (64 bytes) |
501 | * ASF disabled so no need to do WA dev #4.30 | |
cd28ab6a SH |
502 | */ |
503 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); | |
504 | ||
505 | /* Configure Tx MAC FIFO */ | |
506 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); | |
507 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
cd28ab6a SH |
508 | } |
509 | ||
510 | static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len) | |
511 | { | |
512 | u32 end; | |
513 | ||
514 | start /= 8; | |
515 | len /= 8; | |
516 | end = start + len - 1; | |
793b883e | 517 | |
cd28ab6a SH |
518 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); |
519 | sky2_write32(hw, RB_ADDR(q, RB_START), start); | |
520 | sky2_write32(hw, RB_ADDR(q, RB_END), end); | |
521 | sky2_write32(hw, RB_ADDR(q, RB_WP), start); | |
522 | sky2_write32(hw, RB_ADDR(q, RB_RP), start); | |
523 | ||
524 | if (q == Q_R1 || q == Q_R2) { | |
793b883e SH |
525 | u32 rxup, rxlo; |
526 | ||
527 | rxlo = len/2; | |
528 | rxup = rxlo + len/4; | |
793b883e | 529 | |
cd28ab6a | 530 | /* Set thresholds on receive queue's */ |
793b883e SH |
531 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup); |
532 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo); | |
cd28ab6a SH |
533 | } else { |
534 | /* Enable store & forward on Tx queue's because | |
535 | * Tx FIFO is only 1K on Yukon | |
536 | */ | |
537 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
538 | } | |
539 | ||
540 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
793b883e | 541 | sky2_read8(hw, RB_ADDR(q, RB_CTRL)); |
cd28ab6a SH |
542 | } |
543 | ||
cd28ab6a SH |
544 | /* Setup Bus Memory Interface */ |
545 | static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm) | |
546 | { | |
547 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); | |
548 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); | |
549 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); | |
550 | sky2_write32(hw, Q_ADDR(q, Q_WM), wm); | |
551 | } | |
552 | ||
cd28ab6a SH |
553 | /* Setup prefetch unit registers. This is the interface between |
554 | * hardware and driver list elements | |
555 | */ | |
556 | static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, | |
557 | u64 addr, u32 last) | |
558 | { | |
cd28ab6a SH |
559 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
560 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); | |
561 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32); | |
562 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr); | |
563 | sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); | |
564 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); | |
793b883e SH |
565 | |
566 | sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); | |
cd28ab6a SH |
567 | } |
568 | ||
793b883e SH |
569 | static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2) |
570 | { | |
571 | struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod; | |
572 | ||
573 | sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE; | |
574 | return le; | |
575 | } | |
cd28ab6a SH |
576 | |
577 | /* | |
578 | * This is a workaround code taken from syskonnect sk98lin driver | |
793b883e | 579 | * to deal with chip bug on Yukon EC rev 0 in the wraparound case. |
cd28ab6a SH |
580 | */ |
581 | static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, | |
582 | u16 idx, u16 *last, u16 size) | |
cd28ab6a | 583 | { |
cd28ab6a SH |
584 | if (is_ec_a1(hw) && idx < *last) { |
585 | u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); | |
586 | ||
587 | if (hwget == 0) { | |
588 | /* Start prefetching again */ | |
793b883e | 589 | sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0); |
cd28ab6a SH |
590 | goto setnew; |
591 | } | |
592 | ||
793b883e | 593 | if (hwget == size - 1) { |
cd28ab6a SH |
594 | /* set watermark to one list element */ |
595 | sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8); | |
596 | ||
597 | /* set put index to first list element */ | |
598 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0); | |
793b883e SH |
599 | } else /* have hardware go to end of list */ |
600 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), | |
601 | size - 1); | |
cd28ab6a | 602 | } else { |
793b883e | 603 | setnew: |
cd28ab6a | 604 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); |
cd28ab6a | 605 | } |
793b883e | 606 | *last = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)); |
cd28ab6a SH |
607 | } |
608 | ||
793b883e | 609 | |
cd28ab6a SH |
610 | static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) |
611 | { | |
612 | struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; | |
613 | sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE; | |
614 | return le; | |
615 | } | |
616 | ||
793b883e SH |
617 | /* Build description to hardware about buffer */ |
618 | static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re) | |
cd28ab6a SH |
619 | { |
620 | struct sky2_rx_le *le; | |
793b883e | 621 | u32 hi = (re->mapaddr >> 16) >> 16; |
cd28ab6a | 622 | |
793b883e SH |
623 | re->idx = sky2->rx_put; |
624 | if (sky2->rx_addr64 != hi) { | |
cd28ab6a | 625 | le = sky2_next_rx(sky2); |
793b883e | 626 | le->addr = cpu_to_le32(hi); |
cd28ab6a SH |
627 | le->ctrl = 0; |
628 | le->opcode = OP_ADDR64 | HW_OWNER; | |
793b883e | 629 | sky2->rx_addr64 = hi; |
cd28ab6a | 630 | } |
793b883e | 631 | |
cd28ab6a | 632 | le = sky2_next_rx(sky2); |
793b883e SH |
633 | le->addr = cpu_to_le32((u32) re->mapaddr); |
634 | le->length = cpu_to_le16(re->maplen); | |
cd28ab6a SH |
635 | le->ctrl = 0; |
636 | le->opcode = OP_PACKET | HW_OWNER; | |
637 | } | |
638 | ||
793b883e SH |
639 | /* Tell receiver about new buffers. */ |
640 | static inline void rx_set_put(struct net_device *dev) | |
641 | { | |
642 | struct sky2_port *sky2 = netdev_priv(dev); | |
643 | ||
644 | if (sky2->rx_last_put != sky2->rx_put) | |
645 | sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put, | |
646 | &sky2->rx_last_put, RX_LE_SIZE); | |
647 | } | |
648 | ||
cd28ab6a SH |
649 | /* Tell chip where to start receive checksum. |
650 | * Actually has two checksums, but set both same to avoid possible byte | |
651 | * order problems. | |
652 | */ | |
793b883e | 653 | static void rx_set_checksum(struct sky2_port *sky2) |
cd28ab6a SH |
654 | { |
655 | struct sky2_rx_le *le; | |
656 | ||
cd28ab6a | 657 | le = sky2_next_rx(sky2); |
793b883e | 658 | le->addr = (ETH_HLEN << 16) | ETH_HLEN; |
cd28ab6a SH |
659 | le->ctrl = 0; |
660 | le->opcode = OP_TCPSTART | HW_OWNER; | |
793b883e | 661 | |
793b883e SH |
662 | sky2_write32(sky2->hw, |
663 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
664 | sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
cd28ab6a SH |
665 | |
666 | } | |
667 | ||
6b1a3aef SH |
668 | /* |
669 | * The RX Stop command will not work for Yukon-2 if the BMU does not | |
670 | * reach the end of packet and since we can't make sure that we have | |
671 | * incoming data, we must reset the BMU while it is not doing a DMA | |
672 | * transfer. Since it is possible that the RX path is still active, | |
673 | * the RX RAM buffer will be stopped first, so any possible incoming | |
674 | * data will not trigger a DMA. After the RAM buffer is stopped, the | |
675 | * BMU is polled until any DMA in progress is ended and only then it | |
676 | * will be reset. | |
677 | */ | |
678 | static void sky2_rx_stop(struct sky2_port *sky2) | |
679 | { | |
680 | struct sky2_hw *hw = sky2->hw; | |
681 | unsigned rxq = rxqaddr[sky2->port]; | |
682 | int i; | |
683 | ||
684 | /* disable the RAM Buffer receive queue */ | |
685 | sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); | |
686 | ||
687 | for (i = 0; i < 0xffff; i++) | |
688 | if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) | |
689 | == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) | |
690 | goto stopped; | |
691 | ||
692 | printk(KERN_WARNING PFX "%s: receiver stop failed\n", | |
693 | sky2->netdev->name); | |
694 | stopped: | |
695 | sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); | |
696 | ||
697 | /* reset the Rx prefetch unit */ | |
698 | sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
699 | } | |
793b883e | 700 | |
cd28ab6a SH |
701 | /* Cleanout receive buffer area, assumes receiver hardware stopped */ |
702 | static void sky2_rx_clean(struct sky2_port *sky2) | |
703 | { | |
704 | unsigned i; | |
705 | ||
706 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
793b883e | 707 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a SH |
708 | struct ring_info *re = sky2->rx_ring + i; |
709 | ||
710 | if (re->skb) { | |
793b883e SH |
711 | pci_unmap_single(sky2->hw->pdev, |
712 | re->mapaddr, re->maplen, | |
cd28ab6a SH |
713 | PCI_DMA_FROMDEVICE); |
714 | kfree_skb(re->skb); | |
715 | re->skb = NULL; | |
716 | } | |
717 | } | |
718 | } | |
719 | ||
79e57d32 | 720 | #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) |
6b1a3aef | 721 | static inline unsigned rx_size(const struct sky2_port *sky2) |
cd28ab6a | 722 | { |
79e57d32 | 723 | return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8); |
cd28ab6a SH |
724 | } |
725 | ||
726 | /* | |
727 | * Allocate and setup receiver buffer pool. | |
728 | * In case of 64 bit dma, there are 2X as many list elements | |
729 | * available as ring entries | |
730 | * and need to reserve one list element so we don't wrap around. | |
79e57d32 SH |
731 | * |
732 | * It appears the hardware has a bug in the FIFO logic that | |
733 | * cause it to hang if the FIFO gets overrun and the receive buffer | |
734 | * is not aligned. This means we can't use skb_reserve to align | |
735 | * the IP header. | |
cd28ab6a | 736 | */ |
6b1a3aef | 737 | static int sky2_rx_start(struct sky2_port *sky2) |
cd28ab6a | 738 | { |
6b1a3aef SH |
739 | struct sky2_hw *hw = sky2->hw; |
740 | unsigned size = rx_size(sky2); | |
741 | unsigned rxq = rxqaddr[sky2->port]; | |
742 | int i; | |
cd28ab6a | 743 | |
6b1a3aef SH |
744 | sky2->rx_put = sky2->rx_next = 0; |
745 | sky2_qset(hw, rxq, is_pciex(hw) ? 0x80 : 0x600); | |
746 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); | |
747 | ||
748 | rx_set_checksum(sky2); | |
793b883e | 749 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a | 750 | struct ring_info *re = sky2->rx_ring + i; |
cd28ab6a | 751 | |
79e57d32 | 752 | re->skb = dev_alloc_skb(size); |
cd28ab6a SH |
753 | if (!re->skb) |
754 | goto nomem; | |
755 | ||
6b1a3aef | 756 | re->mapaddr = pci_map_single(hw->pdev, re->skb->data, |
79e57d32 SH |
757 | size, PCI_DMA_FROMDEVICE); |
758 | re->maplen = size; | |
793b883e | 759 | sky2_rx_add(sky2, re); |
cd28ab6a SH |
760 | } |
761 | ||
6b1a3aef SH |
762 | /* Tell chip about available buffers */ |
763 | sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put); | |
764 | sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX)); | |
cd28ab6a SH |
765 | return 0; |
766 | nomem: | |
767 | sky2_rx_clean(sky2); | |
768 | return -ENOMEM; | |
769 | } | |
770 | ||
771 | /* Bring up network interface. */ | |
772 | static int sky2_up(struct net_device *dev) | |
773 | { | |
774 | struct sky2_port *sky2 = netdev_priv(dev); | |
775 | struct sky2_hw *hw = sky2->hw; | |
776 | unsigned port = sky2->port; | |
777 | u32 ramsize, rxspace; | |
778 | int err = -ENOMEM; | |
779 | ||
780 | if (netif_msg_ifup(sky2)) | |
781 | printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); | |
782 | ||
783 | /* must be power of 2 */ | |
784 | sky2->tx_le = pci_alloc_consistent(hw->pdev, | |
793b883e SH |
785 | TX_RING_SIZE * |
786 | sizeof(struct sky2_tx_le), | |
cd28ab6a SH |
787 | &sky2->tx_le_map); |
788 | if (!sky2->tx_le) | |
789 | goto err_out; | |
790 | ||
791 | sky2->tx_ring = kmalloc(TX_RING_SIZE * sizeof(struct ring_info), | |
792 | GFP_KERNEL); | |
793 | if (!sky2->tx_ring) | |
794 | goto err_out; | |
795 | sky2->tx_prod = sky2->tx_cons = 0; | |
796 | memset(sky2->tx_ring, 0, TX_RING_SIZE * sizeof(struct ring_info)); | |
797 | ||
798 | sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, | |
799 | &sky2->rx_le_map); | |
800 | if (!sky2->rx_le) | |
801 | goto err_out; | |
802 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
803 | ||
793b883e | 804 | sky2->rx_ring = kmalloc(sky2->rx_pending * sizeof(struct ring_info), |
cd28ab6a SH |
805 | GFP_KERNEL); |
806 | if (!sky2->rx_ring) | |
807 | goto err_out; | |
808 | ||
809 | sky2_mac_init(hw, port); | |
810 | ||
811 | /* Configure RAM buffers */ | |
812 | if (hw->chip_id == CHIP_ID_YUKON_FE || | |
813 | (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2)) | |
814 | ramsize = 4096; | |
815 | else { | |
793b883e SH |
816 | u8 e0 = sky2_read8(hw, B2_E_0); |
817 | ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096); | |
cd28ab6a SH |
818 | } |
819 | ||
820 | /* 2/3 for Rx */ | |
821 | rxspace = (2 * ramsize) / 3; | |
822 | sky2_ramset(hw, rxqaddr[port], 0, rxspace); | |
823 | sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); | |
824 | ||
793b883e SH |
825 | /* Make sure SyncQ is disabled */ |
826 | sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), | |
827 | RB_RST_SET); | |
828 | ||
cd28ab6a | 829 | sky2_qset(hw, txqaddr[port], 0x600); |
6b1a3aef SH |
830 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, |
831 | TX_RING_SIZE - 1); | |
cd28ab6a | 832 | |
6b1a3aef | 833 | err = sky2_rx_start(sky2); |
cd28ab6a SH |
834 | if (err) |
835 | goto err_out; | |
836 | ||
cd28ab6a SH |
837 | /* Enable interrupts from phy/mac for port */ |
838 | hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2; | |
839 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
840 | return 0; | |
841 | ||
842 | err_out: | |
843 | if (sky2->rx_le) | |
844 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
845 | sky2->rx_le, sky2->rx_le_map); | |
846 | if (sky2->tx_le) | |
847 | pci_free_consistent(hw->pdev, | |
848 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
849 | sky2->tx_le, sky2->tx_le_map); | |
850 | if (sky2->tx_ring) | |
851 | kfree(sky2->tx_ring); | |
852 | if (sky2->rx_ring) | |
853 | kfree(sky2->rx_ring); | |
854 | ||
855 | return err; | |
856 | } | |
857 | ||
793b883e SH |
858 | /* Modular subtraction in ring */ |
859 | static inline int tx_dist(unsigned tail, unsigned head) | |
860 | { | |
861 | return (head >= tail ? head : head + TX_RING_SIZE) - tail; | |
862 | } | |
cd28ab6a | 863 | |
793b883e SH |
864 | /* Number of list elements available for next tx */ |
865 | static inline int tx_avail(const struct sky2_port *sky2) | |
cd28ab6a | 866 | { |
793b883e | 867 | return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod); |
cd28ab6a SH |
868 | } |
869 | ||
793b883e SH |
870 | /* Estimate of number of transmit list elements required */ |
871 | static inline unsigned tx_le_req(const struct sk_buff *skb) | |
cd28ab6a | 872 | { |
793b883e SH |
873 | unsigned count; |
874 | ||
875 | count = sizeof(dma_addr_t) / sizeof(u32); | |
876 | count += skb_shinfo(skb)->nr_frags * count; | |
877 | ||
878 | if (skb_shinfo(skb)->tso_size) | |
879 | ++count; | |
880 | ||
881 | if (skb->ip_summed) | |
882 | ++count; | |
883 | ||
884 | return count; | |
cd28ab6a SH |
885 | } |
886 | ||
793b883e SH |
887 | /* |
888 | * Put one packet in ring for transmit. | |
889 | * A single packet can generate multiple list elements, and | |
890 | * the number of ring elements will probably be less than the number | |
891 | * of list elements used. | |
892 | */ | |
cd28ab6a SH |
893 | static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) |
894 | { | |
895 | struct sky2_port *sky2 = netdev_priv(dev); | |
896 | struct sky2_hw *hw = sky2->hw; | |
897 | struct sky2_tx_le *le; | |
898 | struct ring_info *re; | |
793b883e | 899 | unsigned long flags; |
cd28ab6a SH |
900 | unsigned i, len; |
901 | dma_addr_t mapping; | |
902 | u32 addr64; | |
903 | u16 mss; | |
904 | u8 ctrl; | |
905 | ||
793b883e SH |
906 | local_irq_save(flags); |
907 | if (!spin_trylock(&sky2->tx_lock)) { | |
908 | local_irq_restore(flags); | |
cd28ab6a | 909 | return NETDEV_TX_LOCKED; |
793b883e | 910 | } |
cd28ab6a | 911 | |
793b883e | 912 | if (unlikely(tx_avail(sky2) < tx_le_req(skb))) { |
cd28ab6a | 913 | netif_stop_queue(dev); |
793b883e | 914 | spin_unlock_irqrestore(&sky2->tx_lock, flags); |
cd28ab6a SH |
915 | |
916 | printk(KERN_WARNING PFX "%s: ring full when queue awake!\n", | |
917 | dev->name); | |
918 | return NETDEV_TX_BUSY; | |
919 | } | |
920 | ||
793b883e | 921 | if (unlikely(netif_msg_tx_queued(sky2))) |
cd28ab6a SH |
922 | printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n", |
923 | dev->name, sky2->tx_prod, skb->len); | |
924 | ||
cd28ab6a SH |
925 | len = skb_headlen(skb); |
926 | mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
793b883e SH |
927 | addr64 = (mapping >> 16) >> 16; |
928 | ||
929 | re = sky2->tx_ring + sky2->tx_prod; | |
930 | ||
931 | /* Send high bits if changed */ | |
932 | if (addr64 != sky2->tx_addr64) { | |
933 | le = get_tx_le(sky2); | |
934 | le->tx.addr = cpu_to_le32(addr64); | |
935 | le->ctrl = 0; | |
936 | le->opcode = OP_ADDR64 | HW_OWNER; | |
937 | sky2->tx_addr64 = addr64; | |
938 | } | |
cd28ab6a SH |
939 | |
940 | /* Check for TCP Segmentation Offload */ | |
941 | mss = skb_shinfo(skb)->tso_size; | |
793b883e | 942 | if (mss != 0) { |
cd28ab6a SH |
943 | /* just drop the packet if non-linear expansion fails */ |
944 | if (skb_header_cloned(skb) && | |
945 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
793b883e SH |
946 | dev_kfree_skb_any(skb); |
947 | goto out_unlock; | |
cd28ab6a SH |
948 | } |
949 | ||
950 | mss += ((skb->h.th->doff - 5) * 4); /* TCP options */ | |
951 | mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr); | |
952 | mss += ETH_HLEN; | |
793b883e | 953 | } |
cd28ab6a | 954 | |
793b883e | 955 | if (mss != sky2->tx_last_mss) { |
cd28ab6a SH |
956 | le = get_tx_le(sky2); |
957 | le->tx.tso.size = cpu_to_le16(mss); | |
793b883e | 958 | le->tx.tso.rsvd = 0; |
cd28ab6a | 959 | le->opcode = OP_LRGLEN | HW_OWNER; |
cd28ab6a | 960 | le->ctrl = 0; |
793b883e | 961 | sky2->tx_last_mss = mss; |
cd28ab6a SH |
962 | } |
963 | ||
964 | /* Handle TCP checksum offload */ | |
965 | ctrl = 0; | |
966 | if (skb->ip_summed == CHECKSUM_HW) { | |
793b883e SH |
967 | u16 hdr = skb->h.raw - skb->data; |
968 | u16 offset = hdr + skb->csum; | |
cd28ab6a SH |
969 | |
970 | ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; | |
971 | if (skb->nh.iph->protocol == IPPROTO_UDP) | |
972 | ctrl |= UDPTCP; | |
973 | ||
974 | le = get_tx_le(sky2); | |
975 | le->tx.csum.start = cpu_to_le16(hdr); | |
793b883e SH |
976 | le->tx.csum.offset = cpu_to_le16(offset); |
977 | le->length = 0; /* initial checksum value */ | |
cd28ab6a | 978 | le->ctrl = 1; /* one packet */ |
793b883e | 979 | le->opcode = OP_TCPLISW | HW_OWNER; |
cd28ab6a SH |
980 | } |
981 | ||
982 | le = get_tx_le(sky2); | |
983 | le->tx.addr = cpu_to_le32((u32) mapping); | |
984 | le->length = cpu_to_le16(len); | |
985 | le->ctrl = ctrl; | |
793b883e | 986 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); |
cd28ab6a | 987 | |
793b883e | 988 | /* Record the transmit mapping info */ |
cd28ab6a | 989 | re->skb = skb; |
793b883e SH |
990 | re->mapaddr = mapping; |
991 | re->maplen = len; | |
cd28ab6a SH |
992 | |
993 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
994 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
793b883e | 995 | struct ring_info *fre; |
cd28ab6a SH |
996 | |
997 | mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
998 | frag->size, PCI_DMA_TODEVICE); | |
793b883e SH |
999 | addr64 = (mapping >> 16) >> 16; |
1000 | if (addr64 != sky2->tx_addr64) { | |
1001 | le = get_tx_le(sky2); | |
1002 | le->tx.addr = cpu_to_le32(addr64); | |
1003 | le->ctrl = 0; | |
1004 | le->opcode = OP_ADDR64 | HW_OWNER; | |
1005 | sky2->tx_addr64 = addr64; | |
cd28ab6a SH |
1006 | } |
1007 | ||
1008 | le = get_tx_le(sky2); | |
1009 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1010 | le->length = cpu_to_le16(frag->size); | |
1011 | le->ctrl = ctrl; | |
793b883e | 1012 | le->opcode = OP_BUFFER | HW_OWNER; |
cd28ab6a | 1013 | |
793b883e SH |
1014 | fre = sky2->tx_ring |
1015 | + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE; | |
1016 | fre->skb = NULL; | |
1017 | fre->mapaddr = mapping; | |
1018 | fre->maplen = frag->size; | |
cd28ab6a | 1019 | } |
793b883e | 1020 | re->idx = sky2->tx_prod; |
cd28ab6a SH |
1021 | le->ctrl |= EOP; |
1022 | ||
1023 | sky2_put_idx(sky2->hw, txqaddr[sky2->port], sky2->tx_prod, | |
1024 | &sky2->tx_last_put, TX_RING_SIZE); | |
1025 | ||
793b883e | 1026 | if (tx_avail(sky2) < MAX_SKB_TX_LE + 1) |
cd28ab6a | 1027 | netif_stop_queue(dev); |
793b883e SH |
1028 | |
1029 | out_unlock: | |
1030 | mmiowb(); | |
1031 | spin_unlock_irqrestore(&sky2->tx_lock, flags); | |
cd28ab6a SH |
1032 | |
1033 | dev->trans_start = jiffies; | |
1034 | return NETDEV_TX_OK; | |
1035 | } | |
1036 | ||
cd28ab6a | 1037 | /* |
793b883e SH |
1038 | * Free ring elements from starting at tx_cons until "done" |
1039 | * | |
1040 | * NB: the hardware will tell us about partial completion of multi-part | |
1041 | * buffers; these are defered until completion. | |
cd28ab6a SH |
1042 | */ |
1043 | static void sky2_tx_complete(struct net_device *dev, u16 done) | |
1044 | { | |
1045 | struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 1046 | unsigned i; |
cd28ab6a | 1047 | |
793b883e SH |
1048 | if (netif_msg_tx_done(sky2)) |
1049 | printk(KERN_DEBUG "%s: tx done, upto %u\n", dev->name, done); | |
cd28ab6a SH |
1050 | |
1051 | spin_lock(&sky2->tx_lock); | |
cd28ab6a | 1052 | |
793b883e SH |
1053 | while (sky2->tx_cons != done) { |
1054 | struct ring_info *re = sky2->tx_ring + sky2->tx_cons; | |
1055 | struct sk_buff *skb; | |
cd28ab6a | 1056 | |
793b883e SH |
1057 | /* Check for partial status */ |
1058 | if (tx_dist(sky2->tx_cons, done) | |
1059 | < tx_dist(sky2->tx_cons, re->idx)) | |
1060 | goto out; | |
1061 | ||
1062 | skb = re->skb; | |
1063 | pci_unmap_single(sky2->hw->pdev, | |
1064 | re->mapaddr, re->maplen, PCI_DMA_TODEVICE); | |
1065 | ||
1066 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1067 | struct ring_info *fre; | |
1068 | fre = | |
1069 | sky2->tx_ring + (sky2->tx_cons + i + | |
1070 | 1) % TX_RING_SIZE; | |
1071 | pci_unmap_page(sky2->hw->pdev, fre->mapaddr, | |
1072 | fre->maplen, PCI_DMA_TODEVICE); | |
cd28ab6a SH |
1073 | } |
1074 | ||
cd28ab6a | 1075 | dev_kfree_skb_any(skb); |
cd28ab6a | 1076 | |
793b883e SH |
1077 | sky2->tx_cons = re->idx; |
1078 | } | |
1079 | out: | |
1080 | ||
1081 | if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE) | |
cd28ab6a SH |
1082 | netif_wake_queue(dev); |
1083 | spin_unlock(&sky2->tx_lock); | |
1084 | } | |
1085 | ||
1086 | /* Cleanup all untransmitted buffers, assume transmitter not running */ | |
1087 | static inline void sky2_tx_clean(struct sky2_port *sky2) | |
1088 | { | |
1089 | sky2_tx_complete(sky2->netdev, sky2->tx_prod); | |
1090 | } | |
1091 | ||
1092 | /* Network shutdown */ | |
1093 | static int sky2_down(struct net_device *dev) | |
1094 | { | |
1095 | struct sky2_port *sky2 = netdev_priv(dev); | |
1096 | struct sky2_hw *hw = sky2->hw; | |
1097 | unsigned port = sky2->port; | |
1098 | u16 ctrl; | |
cd28ab6a SH |
1099 | |
1100 | if (netif_msg_ifdown(sky2)) | |
1101 | printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); | |
1102 | ||
1103 | netif_stop_queue(dev); | |
1104 | ||
793b883e SH |
1105 | sky2_phy_reset(hw, port); |
1106 | ||
cd28ab6a SH |
1107 | /* Stop transmitter */ |
1108 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); | |
1109 | sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); | |
1110 | ||
1111 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
793b883e | 1112 | RB_RST_SET | RB_DIS_OP_MD); |
cd28ab6a SH |
1113 | |
1114 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
793b883e | 1115 | ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); |
cd28ab6a SH |
1116 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
1117 | ||
1118 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | |
1119 | ||
1120 | /* Workaround shared GMAC reset */ | |
793b883e SH |
1121 | if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 |
1122 | && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) | |
cd28ab6a SH |
1123 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
1124 | ||
1125 | /* Disable Force Sync bit and Enable Alloc bit */ | |
1126 | sky2_write8(hw, SK_REG(port, TXA_CTRL), | |
1127 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); | |
1128 | ||
1129 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
1130 | sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); | |
1131 | sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
1132 | ||
1133 | /* Reset the PCI FIFO of the async Tx queue */ | |
793b883e SH |
1134 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), |
1135 | BMU_RST_SET | BMU_FIFO_RST); | |
cd28ab6a SH |
1136 | |
1137 | /* Reset the Tx prefetch units */ | |
1138 | sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), | |
1139 | PREF_UNIT_RST_SET); | |
1140 | ||
1141 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
1142 | ||
6b1a3aef | 1143 | sky2_rx_stop(sky2); |
cd28ab6a SH |
1144 | |
1145 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
1146 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
1147 | ||
1148 | /* turn off led's */ | |
1149 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); | |
1150 | ||
1151 | sky2_tx_clean(sky2); | |
1152 | sky2_rx_clean(sky2); | |
1153 | ||
1154 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
1155 | sky2->rx_le, sky2->rx_le_map); | |
1156 | kfree(sky2->rx_ring); | |
1157 | ||
1158 | pci_free_consistent(hw->pdev, | |
1159 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1160 | sky2->tx_le, sky2->tx_le_map); | |
1161 | kfree(sky2->tx_ring); | |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) | |
1167 | { | |
793b883e SH |
1168 | if (!hw->copper) |
1169 | return SPEED_1000; | |
1170 | ||
cd28ab6a SH |
1171 | if (hw->chip_id == CHIP_ID_YUKON_FE) |
1172 | return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10; | |
1173 | ||
1174 | switch (aux & PHY_M_PS_SPEED_MSK) { | |
1175 | case PHY_M_PS_SPEED_1000: | |
1176 | return SPEED_1000; | |
1177 | case PHY_M_PS_SPEED_100: | |
1178 | return SPEED_100; | |
1179 | default: | |
1180 | return SPEED_10; | |
1181 | } | |
1182 | } | |
1183 | ||
1184 | static void sky2_link_up(struct sky2_port *sky2) | |
1185 | { | |
1186 | struct sky2_hw *hw = sky2->hw; | |
1187 | unsigned port = sky2->port; | |
1188 | u16 reg; | |
1189 | ||
793b883e SH |
1190 | /* disable Rx GMAC FIFO flush mode */ |
1191 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RX_F_FL_OFF); | |
1192 | ||
cd28ab6a | 1193 | /* Enable Transmit FIFO Underrun */ |
793b883e | 1194 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
cd28ab6a SH |
1195 | |
1196 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
1197 | if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE) | |
1198 | reg |= GM_GPCR_DUP_FULL; | |
1199 | ||
cd28ab6a SH |
1200 | /* enable Rx/Tx */ |
1201 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
1202 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1203 | gma_read16(hw, port, GM_GP_CTRL); | |
1204 | ||
1205 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
1206 | ||
1207 | netif_carrier_on(sky2->netdev); | |
1208 | netif_wake_queue(sky2->netdev); | |
1209 | ||
1210 | /* Turn on link LED */ | |
793b883e | 1211 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), |
cd28ab6a SH |
1212 | LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); |
1213 | ||
793b883e SH |
1214 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
1215 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
1216 | ||
1217 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
1218 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
1219 | PHY_M_LEDC_INIT_CTRL(sky2->speed == | |
1220 | SPEED_10 ? 7 : 0) | | |
1221 | PHY_M_LEDC_STA1_CTRL(sky2->speed == | |
1222 | SPEED_100 ? 7 : 0) | | |
1223 | PHY_M_LEDC_STA0_CTRL(sky2->speed == | |
1224 | SPEED_1000 ? 7 : 0)); | |
1225 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
1226 | } | |
1227 | ||
cd28ab6a SH |
1228 | if (netif_msg_link(sky2)) |
1229 | printk(KERN_INFO PFX | |
1230 | "%s: Link is up at %d Mbps, %s duplex, flowcontrol %s\n", | |
1231 | sky2->netdev->name, sky2->speed, | |
1232 | sky2->duplex == DUPLEX_FULL ? "full" : "half", | |
1233 | (sky2->tx_pause && sky2->rx_pause) ? "both" : | |
793b883e | 1234 | sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none"); |
cd28ab6a SH |
1235 | } |
1236 | ||
1237 | static void sky2_link_down(struct sky2_port *sky2) | |
1238 | { | |
1239 | struct sky2_hw *hw = sky2->hw; | |
1240 | unsigned port = sky2->port; | |
1241 | u16 reg; | |
1242 | ||
1243 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
1244 | ||
1245 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
1246 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
1247 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1248 | gma_read16(hw, port, GM_GP_CTRL); /* PCI post */ | |
1249 | ||
1250 | if (sky2->rx_pause && !sky2->tx_pause) { | |
1251 | /* restore Asymmetric Pause bit */ | |
1252 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, | |
793b883e SH |
1253 | gm_phy_read(hw, port, PHY_MARV_AUNE_ADV) |
1254 | | PHY_M_AN_ASP); | |
cd28ab6a SH |
1255 | } |
1256 | ||
1257 | sky2_phy_reset(hw, port); | |
1258 | ||
1259 | netif_carrier_off(sky2->netdev); | |
1260 | netif_stop_queue(sky2->netdev); | |
1261 | ||
1262 | /* Turn on link LED */ | |
1263 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); | |
1264 | ||
1265 | if (netif_msg_link(sky2)) | |
1266 | printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); | |
1267 | sky2_phy_init(hw, port); | |
1268 | } | |
1269 | ||
793b883e SH |
1270 | static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) |
1271 | { | |
1272 | struct sky2_hw *hw = sky2->hw; | |
1273 | unsigned port = sky2->port; | |
1274 | u16 lpa; | |
1275 | ||
1276 | lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); | |
1277 | ||
1278 | if (lpa & PHY_M_AN_RF) { | |
1279 | printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name); | |
1280 | return -1; | |
1281 | } | |
1282 | ||
1283 | if (hw->chip_id != CHIP_ID_YUKON_FE && | |
1284 | gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { | |
1285 | printk(KERN_ERR PFX "%s: master/slave fault", | |
1286 | sky2->netdev->name); | |
1287 | return -1; | |
1288 | } | |
1289 | ||
1290 | if (!(aux & PHY_M_PS_SPDUP_RES)) { | |
1291 | printk(KERN_ERR PFX "%s: speed/duplex mismatch", | |
1292 | sky2->netdev->name); | |
1293 | return -1; | |
1294 | } | |
1295 | ||
1296 | sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
1297 | ||
1298 | sky2->speed = sky2_phy_speed(hw, aux); | |
1299 | ||
1300 | /* Pause bits are offset (9..8) */ | |
1301 | if (hw->chip_id == CHIP_ID_YUKON_XL) | |
1302 | aux >>= 6; | |
1303 | ||
1304 | sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; | |
1305 | sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0; | |
1306 | ||
1307 | if ((sky2->tx_pause || sky2->rx_pause) | |
1308 | && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF)) | |
1309 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); | |
1310 | else | |
1311 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
1312 | ||
1313 | return 0; | |
1314 | } | |
cd28ab6a SH |
1315 | |
1316 | /* | |
1317 | * Interrrupt from PHY are handled in tasklet (soft irq) | |
1318 | * because accessing phy registers requires spin wait which might | |
1319 | * cause excess interrupt latency. | |
1320 | */ | |
1321 | static void sky2_phy_task(unsigned long data) | |
1322 | { | |
793b883e | 1323 | struct sky2_port *sky2 = (struct sky2_port *)data; |
cd28ab6a | 1324 | struct sky2_hw *hw = sky2->hw; |
cd28ab6a SH |
1325 | u16 istatus, phystat; |
1326 | ||
793b883e SH |
1327 | spin_lock(&hw->phy_lock); |
1328 | istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT); | |
1329 | phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT); | |
cd28ab6a SH |
1330 | |
1331 | if (netif_msg_intr(sky2)) | |
1332 | printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", | |
1333 | sky2->netdev->name, istatus, phystat); | |
1334 | ||
1335 | if (istatus & PHY_M_IS_AN_COMPL) { | |
793b883e SH |
1336 | if (sky2_autoneg_done(sky2, phystat) == 0) |
1337 | sky2_link_up(sky2); | |
1338 | goto out; | |
1339 | } | |
cd28ab6a | 1340 | |
793b883e SH |
1341 | if (istatus & PHY_M_IS_LSP_CHANGE) |
1342 | sky2->speed = sky2_phy_speed(hw, phystat); | |
cd28ab6a | 1343 | |
793b883e SH |
1344 | if (istatus & PHY_M_IS_DUP_CHANGE) |
1345 | sky2->duplex = | |
1346 | (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
cd28ab6a | 1347 | |
793b883e SH |
1348 | if (istatus & PHY_M_IS_LST_CHANGE) { |
1349 | if (phystat & PHY_M_PS_LINK_UP) | |
cd28ab6a | 1350 | sky2_link_up(sky2); |
793b883e SH |
1351 | else |
1352 | sky2_link_down(sky2); | |
cd28ab6a | 1353 | } |
793b883e SH |
1354 | out: |
1355 | spin_unlock(&hw->phy_lock); | |
cd28ab6a SH |
1356 | |
1357 | local_irq_disable(); | |
793b883e | 1358 | hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2; |
cd28ab6a SH |
1359 | sky2_write32(hw, B0_IMSK, hw->intr_mask); |
1360 | local_irq_enable(); | |
1361 | } | |
1362 | ||
1363 | static void sky2_tx_timeout(struct net_device *dev) | |
1364 | { | |
1365 | struct sky2_port *sky2 = netdev_priv(dev); | |
1366 | ||
1367 | if (netif_msg_timer(sky2)) | |
1368 | printk(KERN_ERR PFX "%s: tx timeout\n", dev->name); | |
1369 | ||
1370 | sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP); | |
1371 | sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR)); | |
1372 | ||
1373 | sky2_tx_clean(sky2); | |
1374 | } | |
1375 | ||
1376 | static int sky2_change_mtu(struct net_device *dev, int new_mtu) | |
1377 | { | |
6b1a3aef SH |
1378 | struct sky2_port *sky2 = netdev_priv(dev); |
1379 | struct sky2_hw *hw = sky2->hw; | |
1380 | int err; | |
1381 | u16 ctl, mode; | |
cd28ab6a SH |
1382 | |
1383 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) | |
1384 | return -EINVAL; | |
1385 | ||
6b1a3aef SH |
1386 | if (!netif_running(dev)) { |
1387 | dev->mtu = new_mtu; | |
1388 | return 0; | |
1389 | } | |
1390 | ||
1391 | local_irq_disable(); | |
1392 | sky2_write32(hw, B0_IMSK, 0); | |
1393 | ||
1394 | ctl = gma_read16(hw, sky2->port, GM_GP_CTRL); | |
1395 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); | |
1396 | sky2_rx_stop(sky2); | |
1397 | sky2_rx_clean(sky2); | |
cd28ab6a SH |
1398 | |
1399 | dev->mtu = new_mtu; | |
6b1a3aef SH |
1400 | mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | |
1401 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); | |
1402 | ||
1403 | if (dev->mtu > ETH_DATA_LEN) | |
1404 | mode |= GM_SMOD_JUMBO_ENA; | |
1405 | ||
1406 | gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode); | |
cd28ab6a | 1407 | |
6b1a3aef | 1408 | sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD); |
cd28ab6a | 1409 | |
6b1a3aef SH |
1410 | err = sky2_rx_start(sky2); |
1411 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl); | |
1412 | ||
1413 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
1414 | sky2_read32(hw, B0_IMSK); | |
1415 | local_irq_enable(); | |
cd28ab6a SH |
1416 | return err; |
1417 | } | |
1418 | ||
1419 | /* | |
1420 | * Receive one packet. | |
1421 | * For small packets or errors, just reuse existing skb. | |
1422 | * For larger pakects, get new buffer. | |
1423 | */ | |
1424 | static struct sk_buff *sky2_receive(struct sky2_hw *hw, unsigned port, | |
1425 | u16 length, u32 status) | |
1426 | { | |
1427 | struct net_device *dev = hw->dev[port]; | |
1428 | struct sky2_port *sky2 = netdev_priv(dev); | |
1429 | struct ring_info *re = sky2->rx_ring + sky2->rx_next; | |
79e57d32 | 1430 | struct sk_buff *skb = NULL; |
6b1a3aef | 1431 | const unsigned int bufsize = rx_size(sky2); |
cd28ab6a SH |
1432 | |
1433 | if (unlikely(netif_msg_rx_status(sky2))) | |
1434 | printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", | |
1435 | dev->name, sky2->rx_next, status, length); | |
1436 | ||
793b883e | 1437 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; |
cd28ab6a | 1438 | |
793b883e SH |
1439 | if (!(status & GMR_FS_RX_OK) |
1440 | || (status & GMR_FS_ANY_ERR) | |
1441 | || (length << 16) != (status & GMR_FS_LEN) | |
79e57d32 | 1442 | || length > bufsize) |
cd28ab6a SH |
1443 | goto error; |
1444 | ||
793b883e | 1445 | if (length < RX_COPY_THRESHOLD) { |
79e57d32 SH |
1446 | skb = alloc_skb(length + 2, GFP_ATOMIC); |
1447 | if (!skb) | |
793b883e SH |
1448 | goto resubmit; |
1449 | ||
79e57d32 | 1450 | skb_reserve(skb, 2); |
793b883e SH |
1451 | pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr, |
1452 | length, PCI_DMA_FROMDEVICE); | |
79e57d32 | 1453 | memcpy(skb->data, re->skb->data, length); |
793b883e SH |
1454 | pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr, |
1455 | length, PCI_DMA_FROMDEVICE); | |
793b883e | 1456 | } else { |
79e57d32 SH |
1457 | struct sk_buff *nskb; |
1458 | ||
1459 | nskb = dev_alloc_skb(bufsize); | |
793b883e SH |
1460 | if (!nskb) |
1461 | goto resubmit; | |
cd28ab6a | 1462 | |
793b883e | 1463 | skb = re->skb; |
79e57d32 | 1464 | re->skb = nskb; |
793b883e SH |
1465 | pci_unmap_single(sky2->hw->pdev, re->mapaddr, |
1466 | re->maplen, PCI_DMA_FROMDEVICE); | |
1467 | prefetch(skb->data); | |
cd28ab6a | 1468 | |
793b883e | 1469 | re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data, |
79e57d32 SH |
1470 | bufsize, PCI_DMA_FROMDEVICE); |
1471 | re->maplen = bufsize; | |
793b883e | 1472 | } |
cd28ab6a | 1473 | |
79e57d32 SH |
1474 | skb->dev = dev; |
1475 | skb_put(skb, length); | |
1476 | skb->protocol = eth_type_trans(skb, dev); | |
1477 | dev->last_rx = jiffies; | |
1478 | ||
793b883e | 1479 | resubmit: |
793b883e | 1480 | sky2_rx_add(sky2, re); |
79e57d32 | 1481 | |
cd28ab6a SH |
1482 | return skb; |
1483 | ||
1484 | error: | |
793b883e SH |
1485 | if (status & GMR_FS_GOOD_FC) |
1486 | goto resubmit; | |
1487 | ||
cd28ab6a SH |
1488 | if (netif_msg_rx_err(sky2)) |
1489 | printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", | |
1490 | sky2->netdev->name, status, length); | |
793b883e SH |
1491 | |
1492 | if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) | |
cd28ab6a SH |
1493 | sky2->net_stats.rx_length_errors++; |
1494 | if (status & GMR_FS_FRAGMENT) | |
1495 | sky2->net_stats.rx_frame_errors++; | |
1496 | if (status & GMR_FS_CRC_ERR) | |
1497 | sky2->net_stats.rx_crc_errors++; | |
793b883e SH |
1498 | if (status & GMR_FS_RX_FF_OV) |
1499 | sky2->net_stats.rx_fifo_errors++; | |
79e57d32 | 1500 | |
793b883e | 1501 | goto resubmit; |
cd28ab6a SH |
1502 | } |
1503 | ||
793b883e SH |
1504 | /* Transmit ring index in reported status block is encoded as: |
1505 | * | |
1506 | * | TXS2 | TXA2 | TXS1 | TXA1 | |
1507 | */ | |
1508 | static inline u16 tx_index(u8 port, u32 status, u16 len) | |
cd28ab6a SH |
1509 | { |
1510 | if (port == 0) | |
1511 | return status & 0xfff; | |
1512 | else | |
1513 | return ((status >> 24) & 0xff) | (len & 0xf) << 8; | |
1514 | } | |
1515 | ||
1516 | /* | |
cd28ab6a SH |
1517 | * Both ports share the same status interrupt, therefore there is only |
1518 | * one poll routine. | |
cd28ab6a SH |
1519 | */ |
1520 | static int sky2_poll(struct net_device *dev, int *budget) | |
1521 | { | |
1522 | struct sky2_port *sky2 = netdev_priv(dev); | |
1523 | struct sky2_hw *hw = sky2->hw; | |
1524 | unsigned int to_do = min(dev->quota, *budget); | |
1525 | unsigned int work_done = 0; | |
793b883e | 1526 | u16 hwidx; |
cd28ab6a | 1527 | unsigned char summed[2] = { CHECKSUM_NONE, CHECKSUM_NONE }; |
793b883e | 1528 | unsigned int csum[2]; |
cd28ab6a | 1529 | |
793b883e | 1530 | hwidx = sky2_read16(hw, STAT_PUT_IDX); |
79e57d32 | 1531 | BUG_ON(hwidx >= STATUS_RING_SIZE); |
793b883e SH |
1532 | rmb(); |
1533 | while (hw->st_idx != hwidx && work_done < to_do) { | |
cd28ab6a SH |
1534 | struct sky2_status_le *le = hw->st_le + hw->st_idx; |
1535 | struct sk_buff *skb; | |
1536 | u8 port; | |
1537 | u32 status; | |
1538 | u16 length; | |
1539 | ||
cd28ab6a SH |
1540 | status = le32_to_cpu(le->status); |
1541 | length = le16_to_cpu(le->length); | |
1542 | port = le->link; | |
1543 | ||
793b883e | 1544 | BUG_ON(port >= hw->ports || hw->dev[port] == NULL); |
cd28ab6a | 1545 | |
793b883e | 1546 | switch (le->opcode & ~HW_OWNER) { |
cd28ab6a | 1547 | case OP_RXSTAT: |
cd28ab6a SH |
1548 | skb = sky2_receive(hw, port, length, status); |
1549 | if (likely(skb)) { | |
cd28ab6a SH |
1550 | /* Add hw checksum if available */ |
1551 | skb->ip_summed = summed[port]; | |
1552 | skb->csum = csum[port]; | |
1553 | ||
cd28ab6a | 1554 | netif_receive_skb(skb); |
cd28ab6a SH |
1555 | ++work_done; |
1556 | } | |
79e57d32 SH |
1557 | |
1558 | /* Clear for next packet */ | |
1559 | csum[port] = 0; | |
1560 | summed[port] = CHECKSUM_NONE; | |
1561 | ||
cd28ab6a SH |
1562 | break; |
1563 | ||
1564 | case OP_RXCHKS: | |
1565 | /* Save computed checksum for next rx */ | |
1566 | csum[port] = le16_to_cpu(status & 0xffff); | |
1567 | summed[port] = CHECKSUM_HW; | |
1568 | break; | |
1569 | ||
1570 | case OP_TXINDEXLE: | |
1571 | sky2_tx_complete(hw->dev[port], | |
793b883e | 1572 | tx_index(port, status, length)); |
cd28ab6a SH |
1573 | break; |
1574 | ||
1575 | case OP_RXTIMESTAMP: | |
1576 | break; | |
1577 | ||
1578 | default: | |
1579 | if (net_ratelimit()) | |
793b883e SH |
1580 | printk(KERN_WARNING PFX |
1581 | "unknown status opcode 0x%x\n", | |
cd28ab6a SH |
1582 | le->opcode); |
1583 | break; | |
1584 | } | |
1585 | ||
793b883e SH |
1586 | hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE; |
1587 | if (hw->st_idx == hwidx) { | |
1588 | hwidx = sky2_read16(hw, STAT_PUT_IDX); | |
1589 | rmb(); | |
1590 | } | |
cd28ab6a SH |
1591 | } |
1592 | ||
793b883e SH |
1593 | mmiowb(); |
1594 | ||
1595 | if (hw->dev[0]) | |
1596 | rx_set_put(hw->dev[0]); | |
1597 | ||
1598 | if (hw->dev[1]) | |
1599 | rx_set_put(hw->dev[1]); | |
1600 | ||
cd28ab6a SH |
1601 | *budget -= work_done; |
1602 | dev->quota -= work_done; | |
1603 | if (work_done < to_do) { | |
1604 | /* | |
1605 | * Another chip workaround, need to restart TX timer if status | |
1606 | * LE was handled. WA_DEV_43_418 | |
1607 | */ | |
1608 | if (is_ec_a1(hw)) { | |
1609 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
1610 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
1611 | } | |
1612 | ||
1613 | hw->intr_mask |= Y2_IS_STAT_BMU; | |
1614 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
793b883e | 1615 | sky2_read32(hw, B0_IMSK); |
cd28ab6a SH |
1616 | netif_rx_complete(dev); |
1617 | } | |
1618 | ||
1619 | return work_done >= to_do; | |
1620 | ||
1621 | } | |
1622 | ||
1623 | static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) | |
1624 | { | |
1625 | struct net_device *dev = hw->dev[port]; | |
1626 | ||
1627 | printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n", | |
1628 | dev->name, status); | |
1629 | ||
1630 | if (status & Y2_IS_PAR_RD1) { | |
1631 | printk(KERN_ERR PFX "%s: ram data read parity error\n", | |
1632 | dev->name); | |
1633 | /* Clear IRQ */ | |
1634 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); | |
1635 | } | |
1636 | ||
1637 | if (status & Y2_IS_PAR_WR1) { | |
1638 | printk(KERN_ERR PFX "%s: ram data write parity error\n", | |
1639 | dev->name); | |
1640 | ||
1641 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); | |
1642 | } | |
1643 | ||
1644 | if (status & Y2_IS_PAR_MAC1) { | |
1645 | printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name); | |
1646 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); | |
1647 | } | |
1648 | ||
1649 | if (status & Y2_IS_PAR_RX1) { | |
1650 | printk(KERN_ERR PFX "%s: RX parity error\n", dev->name); | |
1651 | sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); | |
1652 | } | |
1653 | ||
1654 | if (status & Y2_IS_TCP_TXA1) { | |
1655 | printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name); | |
1656 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); | |
1657 | } | |
1658 | } | |
1659 | ||
1660 | static void sky2_hw_intr(struct sky2_hw *hw) | |
1661 | { | |
1662 | u32 status = sky2_read32(hw, B0_HWE_ISRC); | |
1663 | ||
793b883e | 1664 | if (status & Y2_IS_TIST_OV) |
cd28ab6a | 1665 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
1666 | |
1667 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | |
793b883e SH |
1668 | u16 pci_err; |
1669 | ||
1670 | pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err); | |
cd28ab6a SH |
1671 | printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n", |
1672 | pci_name(hw->pdev), pci_err); | |
1673 | ||
1674 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
793b883e SH |
1675 | pci_write_config_word(hw->pdev, PCI_STATUS, |
1676 | pci_err | PCI_STATUS_ERROR_BITS); | |
cd28ab6a SH |
1677 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
1678 | } | |
1679 | ||
1680 | if (status & Y2_IS_PCI_EXP) { | |
1681 | /* PCI-Express uncorrectable Error occured */ | |
793b883e SH |
1682 | u32 pex_err; |
1683 | ||
1684 | pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err); | |
cd28ab6a | 1685 | |
cd28ab6a SH |
1686 | printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", |
1687 | pci_name(hw->pdev), pex_err); | |
1688 | ||
1689 | /* clear the interrupt */ | |
1690 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
793b883e SH |
1691 | pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, |
1692 | 0xffffffffUL); | |
cd28ab6a SH |
1693 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
1694 | ||
1695 | if (pex_err & PEX_FATAL_ERRORS) { | |
1696 | u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); | |
1697 | hwmsk &= ~Y2_IS_PCI_EXP; | |
1698 | sky2_write32(hw, B0_HWE_IMSK, hwmsk); | |
1699 | } | |
1700 | } | |
1701 | ||
1702 | if (status & Y2_HWE_L1_MASK) | |
1703 | sky2_hw_error(hw, 0, status); | |
1704 | status >>= 8; | |
1705 | if (status & Y2_HWE_L1_MASK) | |
1706 | sky2_hw_error(hw, 1, status); | |
1707 | } | |
1708 | ||
1709 | static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) | |
1710 | { | |
1711 | struct net_device *dev = hw->dev[port]; | |
1712 | struct sky2_port *sky2 = netdev_priv(dev); | |
1713 | u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); | |
1714 | ||
1715 | if (netif_msg_intr(sky2)) | |
1716 | printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n", | |
1717 | dev->name, status); | |
1718 | ||
1719 | if (status & GM_IS_RX_FF_OR) { | |
1720 | ++sky2->net_stats.rx_fifo_errors; | |
1721 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); | |
1722 | } | |
1723 | ||
1724 | if (status & GM_IS_TX_FF_UR) { | |
1725 | ++sky2->net_stats.tx_fifo_errors; | |
1726 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); | |
1727 | } | |
cd28ab6a SH |
1728 | } |
1729 | ||
1730 | static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) | |
1731 | { | |
1732 | struct net_device *dev = hw->dev[port]; | |
1733 | struct sky2_port *sky2 = netdev_priv(dev); | |
1734 | ||
1735 | hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); | |
1736 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
1737 | tasklet_schedule(&sky2->phy_task); | |
1738 | } | |
1739 | ||
1740 | static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs) | |
1741 | { | |
1742 | struct sky2_hw *hw = dev_id; | |
1743 | u32 status; | |
1744 | ||
1745 | status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
793b883e | 1746 | if (status == 0 || status == ~0) |
cd28ab6a SH |
1747 | return IRQ_NONE; |
1748 | ||
1749 | if (status & Y2_IS_HW_ERR) | |
1750 | sky2_hw_intr(hw); | |
1751 | ||
793b883e SH |
1752 | /* Do NAPI for Rx and Tx status */ |
1753 | if ((status & Y2_IS_STAT_BMU) && netif_rx_schedule_test(hw->dev[0])) { | |
1754 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); | |
1755 | ||
cd28ab6a SH |
1756 | hw->intr_mask &= ~Y2_IS_STAT_BMU; |
1757 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
1758 | __netif_rx_schedule(hw->dev[0]); | |
1759 | } | |
1760 | ||
793b883e | 1761 | if (status & Y2_IS_IRQ_PHY1) |
cd28ab6a SH |
1762 | sky2_phy_intr(hw, 0); |
1763 | ||
1764 | if (status & Y2_IS_IRQ_PHY2) | |
1765 | sky2_phy_intr(hw, 1); | |
1766 | ||
1767 | if (status & Y2_IS_IRQ_MAC1) | |
1768 | sky2_mac_intr(hw, 0); | |
1769 | ||
1770 | if (status & Y2_IS_IRQ_MAC2) | |
1771 | sky2_mac_intr(hw, 1); | |
1772 | ||
cd28ab6a | 1773 | sky2_write32(hw, B0_Y2_SP_ICR, 2); |
793b883e SH |
1774 | |
1775 | sky2_read32(hw, B0_IMSK); | |
1776 | ||
cd28ab6a SH |
1777 | return IRQ_HANDLED; |
1778 | } | |
1779 | ||
1780 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1781 | static void sky2_netpoll(struct net_device *dev) | |
1782 | { | |
1783 | struct sky2_port *sky2 = netdev_priv(dev); | |
1784 | ||
793b883e | 1785 | sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL); |
cd28ab6a SH |
1786 | } |
1787 | #endif | |
1788 | ||
1789 | /* Chip internal frequency for clock calculations */ | |
1790 | static inline u32 sky2_khz(const struct sky2_hw *hw) | |
1791 | { | |
793b883e | 1792 | switch (hw->chip_id) { |
cd28ab6a SH |
1793 | case CHIP_ID_YUKON_EC: |
1794 | return 125000; /* 125 Mhz */ | |
1795 | case CHIP_ID_YUKON_FE: | |
1796 | return 100000; /* 100 Mhz */ | |
793b883e | 1797 | default: /* YUKON_XL */ |
cd28ab6a SH |
1798 | return 156000; /* 156 Mhz */ |
1799 | } | |
1800 | } | |
1801 | ||
1802 | static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms) | |
1803 | { | |
1804 | return sky2_khz(hw) * ms; | |
1805 | } | |
1806 | ||
1807 | static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) | |
1808 | { | |
793b883e | 1809 | return (sky2_khz(hw) * us) / 1000; |
cd28ab6a SH |
1810 | } |
1811 | ||
1812 | static int sky2_reset(struct sky2_hw *hw) | |
1813 | { | |
1814 | u32 ctst, power; | |
1815 | u16 status; | |
1816 | u8 t8, pmd_type; | |
1817 | int i; | |
1818 | ||
1819 | ctst = sky2_read32(hw, B0_CTST); | |
1820 | ||
1821 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
1822 | hw->chip_id = sky2_read8(hw, B2_CHIP_ID); | |
1823 | if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) { | |
1824 | printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n", | |
1825 | pci_name(hw->pdev), hw->chip_id); | |
1826 | return -EOPNOTSUPP; | |
1827 | } | |
1828 | ||
793b883e SH |
1829 | /* ring for status responses */ |
1830 | hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES, | |
1831 | &hw->st_dma); | |
1832 | if (!hw->st_le) | |
1833 | return -ENOMEM; | |
1834 | ||
cd28ab6a SH |
1835 | /* disable ASF */ |
1836 | if (hw->chip_id <= CHIP_ID_YUKON_EC) { | |
1837 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); | |
1838 | sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); | |
1839 | } | |
1840 | ||
1841 | /* do a SW reset */ | |
1842 | sky2_write8(hw, B0_CTST, CS_RST_SET); | |
1843 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
1844 | ||
1845 | /* clear PCI errors, if any */ | |
793b883e | 1846 | pci_read_config_word(hw->pdev, PCI_STATUS, &status); |
cd28ab6a | 1847 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
793b883e SH |
1848 | pci_write_config_word(hw->pdev, PCI_STATUS, |
1849 | status | PCI_STATUS_ERROR_BITS); | |
cd28ab6a SH |
1850 | |
1851 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | |
1852 | ||
1853 | /* clear any PEX errors */ | |
1854 | if (is_pciex(hw)) { | |
793b883e SH |
1855 | u16 lstat; |
1856 | pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, | |
1857 | 0xffffffffUL); | |
1858 | pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat); | |
cd28ab6a SH |
1859 | } |
1860 | ||
1861 | pmd_type = sky2_read8(hw, B2_PMD_TYP); | |
1862 | hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); | |
1863 | ||
1864 | hw->ports = 1; | |
1865 | t8 = sky2_read8(hw, B2_Y2_HW_RES); | |
1866 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { | |
1867 | if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) | |
1868 | ++hw->ports; | |
1869 | } | |
1870 | hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; | |
1871 | ||
1872 | /* switch power to VCC (WA for VAUX problem) */ | |
1873 | sky2_write8(hw, B0_POWER_CTRL, | |
1874 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
1875 | ||
1876 | /* disable Core Clock Division, */ | |
1877 | sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); | |
1878 | ||
1879 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
1880 | /* enable bits are inverted */ | |
1881 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
1882 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
1883 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
1884 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
793b883e SH |
1885 | else |
1886 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
cd28ab6a SH |
1887 | |
1888 | /* Turn off phy power saving */ | |
793b883e SH |
1889 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &power); |
1890 | power &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
cd28ab6a | 1891 | |
793b883e | 1892 | /* looks like this xl is back asswards .. */ |
cd28ab6a SH |
1893 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) { |
1894 | power |= PCI_Y2_PHY1_COMA; | |
1895 | if (hw->ports > 1) | |
1896 | power |= PCI_Y2_PHY2_COMA; | |
1897 | } | |
793b883e | 1898 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, power); |
cd28ab6a SH |
1899 | |
1900 | for (i = 0; i < hw->ports; i++) { | |
1901 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); | |
1902 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
1903 | } | |
1904 | ||
1905 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
1906 | ||
793b883e SH |
1907 | /* Clear I2C IRQ noise */ |
1908 | sky2_write32(hw, B2_I2C_IRQ, 1); | |
cd28ab6a SH |
1909 | |
1910 | /* turn off hardware timer (unused) */ | |
1911 | sky2_write8(hw, B2_TI_CTRL, TIM_STOP); | |
1912 | sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
793b883e | 1913 | |
cd28ab6a SH |
1914 | sky2_write8(hw, B0_Y2LED, LED_STAT_ON); |
1915 | ||
793b883e | 1916 | /* Turn on descriptor polling (every 75us) */ |
cd28ab6a SH |
1917 | sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75)); |
1918 | sky2_write8(hw, B28_DPT_CTRL, DPT_START); | |
1919 | ||
1920 | /* Turn off receive timestamp */ | |
1921 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); | |
793b883e | 1922 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
1923 | |
1924 | /* enable the Tx Arbiters */ | |
1925 | for (i = 0; i < hw->ports; i++) | |
1926 | sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); | |
1927 | ||
1928 | /* Initialize ram interface */ | |
1929 | for (i = 0; i < hw->ports; i++) { | |
793b883e | 1930 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); |
cd28ab6a SH |
1931 | |
1932 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); | |
1933 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); | |
1934 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); | |
1935 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); | |
1936 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); | |
1937 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); | |
1938 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); | |
1939 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); | |
1940 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); | |
1941 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); | |
1942 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); | |
1943 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); | |
1944 | } | |
1945 | ||
cd28ab6a | 1946 | if (is_pciex(hw)) { |
793b883e SH |
1947 | u16 pctrl; |
1948 | ||
1949 | /* change Max. Read Request Size to 2048 bytes */ | |
1950 | pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl); | |
1951 | pctrl &= ~PEX_DC_MAX_RRS_MSK; | |
1952 | pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4); | |
1953 | ||
1954 | ||
cd28ab6a | 1955 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
793b883e | 1956 | pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl); |
cd28ab6a SH |
1957 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
1958 | } | |
1959 | ||
1960 | sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); | |
1961 | ||
cd28ab6a SH |
1962 | spin_lock_bh(&hw->phy_lock); |
1963 | for (i = 0; i < hw->ports; i++) | |
1964 | sky2_phy_reset(hw, i); | |
1965 | spin_unlock_bh(&hw->phy_lock); | |
1966 | ||
cd28ab6a SH |
1967 | memset(hw->st_le, 0, STATUS_LE_BYTES); |
1968 | hw->st_idx = 0; | |
1969 | ||
1970 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); | |
1971 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); | |
1972 | ||
1973 | sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); | |
793b883e | 1974 | sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); |
cd28ab6a SH |
1975 | |
1976 | /* Set the list last index */ | |
793b883e | 1977 | sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1); |
cd28ab6a | 1978 | |
793b883e SH |
1979 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10)); |
1980 | ||
1981 | /* These status setup values are copied from SysKonnect's driver */ | |
cd28ab6a SH |
1982 | if (is_ec_a1(hw)) { |
1983 | /* WA for dev. #4.3 */ | |
793b883e | 1984 | sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */ |
cd28ab6a SH |
1985 | |
1986 | /* set Status-FIFO watermark */ | |
1987 | sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */ | |
1988 | ||
1989 | /* set Status-FIFO ISR watermark */ | |
793b883e | 1990 | sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */ |
cd28ab6a | 1991 | |
cd28ab6a | 1992 | } else { |
cd28ab6a SH |
1993 | sky2_write16(hw, STAT_TX_IDX_TH, 0x000a); |
1994 | ||
1995 | /* set Status-FIFO watermark */ | |
1996 | sky2_write8(hw, STAT_FIFO_WM, 0x10); | |
1997 | ||
1998 | /* set Status-FIFO ISR watermark */ | |
1999 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) | |
2000 | sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10); | |
2001 | ||
793b883e | 2002 | else /* WA 4109 */ |
cd28ab6a SH |
2003 | sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04); |
2004 | ||
2005 | sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190); | |
2006 | } | |
2007 | ||
793b883e | 2008 | /* enable status unit */ |
cd28ab6a SH |
2009 | sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); |
2010 | ||
2011 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2012 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2013 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2014 | ||
2015 | return 0; | |
2016 | } | |
2017 | ||
2018 | static inline u32 sky2_supported_modes(const struct sky2_hw *hw) | |
2019 | { | |
2020 | u32 modes; | |
2021 | if (hw->copper) { | |
793b883e SH |
2022 | modes = SUPPORTED_10baseT_Half |
2023 | | SUPPORTED_10baseT_Full | |
2024 | | SUPPORTED_100baseT_Half | |
2025 | | SUPPORTED_100baseT_Full | |
2026 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2027 | |
2028 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
2029 | modes |= SUPPORTED_1000baseT_Half | |
793b883e | 2030 | | SUPPORTED_1000baseT_Full; |
cd28ab6a SH |
2031 | } else |
2032 | modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE | |
793b883e | 2033 | | SUPPORTED_Autoneg; |
cd28ab6a SH |
2034 | return modes; |
2035 | } | |
2036 | ||
793b883e | 2037 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
cd28ab6a SH |
2038 | { |
2039 | struct sky2_port *sky2 = netdev_priv(dev); | |
2040 | struct sky2_hw *hw = sky2->hw; | |
2041 | ||
2042 | ecmd->transceiver = XCVR_INTERNAL; | |
2043 | ecmd->supported = sky2_supported_modes(hw); | |
2044 | ecmd->phy_address = PHY_ADDR_MARV; | |
2045 | if (hw->copper) { | |
2046 | ecmd->supported = SUPPORTED_10baseT_Half | |
793b883e SH |
2047 | | SUPPORTED_10baseT_Full |
2048 | | SUPPORTED_100baseT_Half | |
2049 | | SUPPORTED_100baseT_Full | |
2050 | | SUPPORTED_1000baseT_Half | |
2051 | | SUPPORTED_1000baseT_Full | |
2052 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2053 | ecmd->port = PORT_TP; |
2054 | } else | |
2055 | ecmd->port = PORT_FIBRE; | |
2056 | ||
2057 | ecmd->advertising = sky2->advertising; | |
2058 | ecmd->autoneg = sky2->autoneg; | |
2059 | ecmd->speed = sky2->speed; | |
2060 | ecmd->duplex = sky2->duplex; | |
2061 | return 0; | |
2062 | } | |
2063 | ||
2064 | static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
2065 | { | |
2066 | struct sky2_port *sky2 = netdev_priv(dev); | |
2067 | const struct sky2_hw *hw = sky2->hw; | |
2068 | u32 supported = sky2_supported_modes(hw); | |
2069 | ||
2070 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2071 | ecmd->advertising = supported; | |
2072 | sky2->duplex = -1; | |
2073 | sky2->speed = -1; | |
2074 | } else { | |
2075 | u32 setting; | |
2076 | ||
793b883e | 2077 | switch (ecmd->speed) { |
cd28ab6a SH |
2078 | case SPEED_1000: |
2079 | if (ecmd->duplex == DUPLEX_FULL) | |
2080 | setting = SUPPORTED_1000baseT_Full; | |
2081 | else if (ecmd->duplex == DUPLEX_HALF) | |
2082 | setting = SUPPORTED_1000baseT_Half; | |
2083 | else | |
2084 | return -EINVAL; | |
2085 | break; | |
2086 | case SPEED_100: | |
2087 | if (ecmd->duplex == DUPLEX_FULL) | |
2088 | setting = SUPPORTED_100baseT_Full; | |
2089 | else if (ecmd->duplex == DUPLEX_HALF) | |
2090 | setting = SUPPORTED_100baseT_Half; | |
2091 | else | |
2092 | return -EINVAL; | |
2093 | break; | |
2094 | ||
2095 | case SPEED_10: | |
2096 | if (ecmd->duplex == DUPLEX_FULL) | |
2097 | setting = SUPPORTED_10baseT_Full; | |
2098 | else if (ecmd->duplex == DUPLEX_HALF) | |
2099 | setting = SUPPORTED_10baseT_Half; | |
2100 | else | |
2101 | return -EINVAL; | |
2102 | break; | |
2103 | default: | |
2104 | return -EINVAL; | |
2105 | } | |
2106 | ||
2107 | if ((setting & supported) == 0) | |
2108 | return -EINVAL; | |
2109 | ||
2110 | sky2->speed = ecmd->speed; | |
2111 | sky2->duplex = ecmd->duplex; | |
2112 | } | |
2113 | ||
2114 | sky2->autoneg = ecmd->autoneg; | |
2115 | sky2->advertising = ecmd->advertising; | |
2116 | ||
2117 | if (netif_running(dev)) { | |
2118 | sky2_down(dev); | |
2119 | sky2_up(dev); | |
2120 | } | |
2121 | ||
2122 | return 0; | |
2123 | } | |
2124 | ||
2125 | static void sky2_get_drvinfo(struct net_device *dev, | |
2126 | struct ethtool_drvinfo *info) | |
2127 | { | |
2128 | struct sky2_port *sky2 = netdev_priv(dev); | |
2129 | ||
2130 | strcpy(info->driver, DRV_NAME); | |
2131 | strcpy(info->version, DRV_VERSION); | |
2132 | strcpy(info->fw_version, "N/A"); | |
2133 | strcpy(info->bus_info, pci_name(sky2->hw->pdev)); | |
2134 | } | |
2135 | ||
2136 | static const struct sky2_stat { | |
793b883e SH |
2137 | char name[ETH_GSTRING_LEN]; |
2138 | u16 offset; | |
cd28ab6a SH |
2139 | } sky2_stats[] = { |
2140 | { "tx_bytes", GM_TXO_OK_HI }, | |
2141 | { "rx_bytes", GM_RXO_OK_HI }, | |
2142 | { "tx_broadcast", GM_TXF_BC_OK }, | |
2143 | { "rx_broadcast", GM_RXF_BC_OK }, | |
2144 | { "tx_multicast", GM_TXF_MC_OK }, | |
2145 | { "rx_multicast", GM_RXF_MC_OK }, | |
2146 | { "tx_unicast", GM_TXF_UC_OK }, | |
2147 | { "rx_unicast", GM_RXF_UC_OK }, | |
2148 | { "tx_mac_pause", GM_TXF_MPAUSE }, | |
2149 | { "rx_mac_pause", GM_RXF_MPAUSE }, | |
2150 | { "collisions", GM_TXF_SNG_COL }, | |
2151 | { "late_collision",GM_TXF_LAT_COL }, | |
2152 | { "aborted", GM_TXF_ABO_COL }, | |
2153 | { "multi_collisions", GM_TXF_MUL_COL }, | |
2154 | { "fifo_underrun", GM_TXE_FIFO_UR }, | |
2155 | { "fifo_overflow", GM_RXE_FIFO_OV }, | |
2156 | { "rx_toolong", GM_RXF_LNG_ERR }, | |
2157 | { "rx_jabber", GM_RXF_JAB_PKT }, | |
2158 | { "rx_runt", GM_RXE_FRAG }, | |
2159 | { "rx_too_long", GM_RXF_LNG_ERR }, | |
2160 | { "rx_fcs_error", GM_RXF_FCS_ERR }, | |
2161 | }; | |
2162 | ||
cd28ab6a SH |
2163 | static u32 sky2_get_rx_csum(struct net_device *dev) |
2164 | { | |
2165 | struct sky2_port *sky2 = netdev_priv(dev); | |
2166 | ||
2167 | return sky2->rx_csum; | |
2168 | } | |
2169 | ||
2170 | static int sky2_set_rx_csum(struct net_device *dev, u32 data) | |
2171 | { | |
2172 | struct sky2_port *sky2 = netdev_priv(dev); | |
2173 | ||
2174 | sky2->rx_csum = data; | |
793b883e | 2175 | |
cd28ab6a SH |
2176 | sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), |
2177 | data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
2178 | ||
2179 | return 0; | |
2180 | } | |
2181 | ||
2182 | static u32 sky2_get_msglevel(struct net_device *netdev) | |
2183 | { | |
2184 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2185 | return sky2->msg_enable; | |
2186 | } | |
2187 | ||
793b883e | 2188 | static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) |
cd28ab6a SH |
2189 | { |
2190 | struct sky2_hw *hw = sky2->hw; | |
2191 | unsigned port = sky2->port; | |
2192 | int i; | |
2193 | ||
2194 | data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 | |
793b883e | 2195 | | (u64) gma_read32(hw, port, GM_TXO_OK_LO); |
cd28ab6a | 2196 | data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 |
793b883e | 2197 | | (u64) gma_read32(hw, port, GM_RXO_OK_LO); |
cd28ab6a | 2198 | |
793b883e | 2199 | for (i = 2; i < count; i++) |
cd28ab6a SH |
2200 | data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset); |
2201 | } | |
2202 | ||
cd28ab6a SH |
2203 | static void sky2_set_msglevel(struct net_device *netdev, u32 value) |
2204 | { | |
2205 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2206 | sky2->msg_enable = value; | |
2207 | } | |
2208 | ||
2209 | static int sky2_get_stats_count(struct net_device *dev) | |
2210 | { | |
2211 | return ARRAY_SIZE(sky2_stats); | |
2212 | } | |
2213 | ||
2214 | static void sky2_get_ethtool_stats(struct net_device *dev, | |
793b883e | 2215 | struct ethtool_stats *stats, u64 * data) |
cd28ab6a SH |
2216 | { |
2217 | struct sky2_port *sky2 = netdev_priv(dev); | |
2218 | ||
793b883e | 2219 | sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); |
cd28ab6a SH |
2220 | } |
2221 | ||
793b883e | 2222 | static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) |
cd28ab6a SH |
2223 | { |
2224 | int i; | |
2225 | ||
2226 | switch (stringset) { | |
2227 | case ETH_SS_STATS: | |
2228 | for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) | |
2229 | memcpy(data + i * ETH_GSTRING_LEN, | |
2230 | sky2_stats[i].name, ETH_GSTRING_LEN); | |
2231 | break; | |
2232 | } | |
2233 | } | |
2234 | ||
2235 | /* Use hardware MIB variables for critical path statistics and | |
2236 | * transmit feedback not reported at interrupt. | |
2237 | * Other errors are accounted for in interrupt handler. | |
2238 | */ | |
2239 | static struct net_device_stats *sky2_get_stats(struct net_device *dev) | |
2240 | { | |
2241 | struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2242 | u64 data[13]; |
cd28ab6a | 2243 | |
793b883e | 2244 | sky2_phy_stats(sky2, data, ARRAY_SIZE(data)); |
cd28ab6a SH |
2245 | |
2246 | sky2->net_stats.tx_bytes = data[0]; | |
2247 | sky2->net_stats.rx_bytes = data[1]; | |
2248 | sky2->net_stats.tx_packets = data[2] + data[4] + data[6]; | |
2249 | sky2->net_stats.rx_packets = data[3] + data[5] + data[7]; | |
2250 | sky2->net_stats.multicast = data[5] + data[7]; | |
2251 | sky2->net_stats.collisions = data[10]; | |
2252 | sky2->net_stats.tx_aborted_errors = data[12]; | |
2253 | ||
2254 | return &sky2->net_stats; | |
2255 | } | |
2256 | ||
2257 | static int sky2_set_mac_address(struct net_device *dev, void *p) | |
2258 | { | |
2259 | struct sky2_port *sky2 = netdev_priv(dev); | |
2260 | struct sockaddr *addr = p; | |
2261 | int err = 0; | |
2262 | ||
2263 | if (!is_valid_ether_addr(addr->sa_data)) | |
2264 | return -EADDRNOTAVAIL; | |
2265 | ||
2266 | sky2_down(dev); | |
2267 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
793b883e | 2268 | memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8, |
cd28ab6a | 2269 | dev->dev_addr, ETH_ALEN); |
793b883e | 2270 | memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8, |
cd28ab6a SH |
2271 | dev->dev_addr, ETH_ALEN); |
2272 | if (dev->flags & IFF_UP) | |
2273 | err = sky2_up(dev); | |
2274 | return err; | |
2275 | } | |
2276 | ||
2277 | static void sky2_set_multicast(struct net_device *dev) | |
2278 | { | |
2279 | struct sky2_port *sky2 = netdev_priv(dev); | |
2280 | struct sky2_hw *hw = sky2->hw; | |
2281 | unsigned port = sky2->port; | |
2282 | struct dev_mc_list *list = dev->mc_list; | |
2283 | u16 reg; | |
2284 | u8 filter[8]; | |
2285 | ||
2286 | memset(filter, 0, sizeof(filter)); | |
2287 | ||
2288 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
2289 | reg |= GM_RXCR_UCF_ENA; | |
2290 | ||
793b883e | 2291 | if (dev->flags & IFF_PROMISC) /* promiscious */ |
cd28ab6a | 2292 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
793b883e | 2293 | else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */ |
cd28ab6a | 2294 | memset(filter, 0xff, sizeof(filter)); |
793b883e | 2295 | else if (dev->mc_count == 0) /* no multicast */ |
cd28ab6a SH |
2296 | reg &= ~GM_RXCR_MCF_ENA; |
2297 | else { | |
2298 | int i; | |
2299 | reg |= GM_RXCR_MCF_ENA; | |
2300 | ||
2301 | for (i = 0; list && i < dev->mc_count; i++, list = list->next) { | |
2302 | u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; | |
793b883e | 2303 | filter[bit / 8] |= 1 << (bit % 8); |
cd28ab6a SH |
2304 | } |
2305 | } | |
2306 | ||
cd28ab6a | 2307 | gma_write16(hw, port, GM_MC_ADDR_H1, |
793b883e | 2308 | (u16) filter[0] | ((u16) filter[1] << 8)); |
cd28ab6a | 2309 | gma_write16(hw, port, GM_MC_ADDR_H2, |
793b883e | 2310 | (u16) filter[2] | ((u16) filter[3] << 8)); |
cd28ab6a | 2311 | gma_write16(hw, port, GM_MC_ADDR_H3, |
793b883e | 2312 | (u16) filter[4] | ((u16) filter[5] << 8)); |
cd28ab6a | 2313 | gma_write16(hw, port, GM_MC_ADDR_H4, |
793b883e | 2314 | (u16) filter[6] | ((u16) filter[7] << 8)); |
cd28ab6a SH |
2315 | |
2316 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
2317 | } | |
2318 | ||
2319 | /* Can have one global because blinking is controlled by | |
2320 | * ethtool and that is always under RTNL mutex | |
2321 | */ | |
2322 | static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on) | |
2323 | { | |
793b883e SH |
2324 | u16 pg; |
2325 | ||
cd28ab6a | 2326 | spin_lock_bh(&hw->phy_lock); |
793b883e SH |
2327 | switch (hw->chip_id) { |
2328 | case CHIP_ID_YUKON_XL: | |
2329 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2330 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2331 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
2332 | on ? (PHY_M_LEDC_LOS_CTRL(1) | | |
2333 | PHY_M_LEDC_INIT_CTRL(7) | | |
2334 | PHY_M_LEDC_STA1_CTRL(7) | | |
2335 | PHY_M_LEDC_STA0_CTRL(7)) | |
2336 | : 0); | |
2337 | ||
2338 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2339 | break; | |
2340 | ||
2341 | default: | |
2342 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
cd28ab6a | 2343 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
793b883e SH |
2344 | on ? PHY_M_LED_MO_DUP(MO_LED_ON) | |
2345 | PHY_M_LED_MO_10(MO_LED_ON) | | |
2346 | PHY_M_LED_MO_100(MO_LED_ON) | | |
cd28ab6a | 2347 | PHY_M_LED_MO_1000(MO_LED_ON) | |
793b883e SH |
2348 | PHY_M_LED_MO_RX(MO_LED_ON) |
2349 | : PHY_M_LED_MO_DUP(MO_LED_OFF) | | |
2350 | PHY_M_LED_MO_10(MO_LED_OFF) | | |
2351 | PHY_M_LED_MO_100(MO_LED_OFF) | | |
cd28ab6a SH |
2352 | PHY_M_LED_MO_1000(MO_LED_OFF) | |
2353 | PHY_M_LED_MO_RX(MO_LED_OFF)); | |
2354 | ||
793b883e | 2355 | } |
cd28ab6a SH |
2356 | spin_unlock_bh(&hw->phy_lock); |
2357 | } | |
2358 | ||
2359 | /* blink LED's for finding board */ | |
2360 | static int sky2_phys_id(struct net_device *dev, u32 data) | |
2361 | { | |
2362 | struct sky2_port *sky2 = netdev_priv(dev); | |
2363 | struct sky2_hw *hw = sky2->hw; | |
2364 | unsigned port = sky2->port; | |
793b883e | 2365 | u16 ledctrl, ledover = 0; |
cd28ab6a SH |
2366 | long ms; |
2367 | int onoff = 1; | |
2368 | ||
793b883e | 2369 | if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)) |
cd28ab6a SH |
2370 | ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT); |
2371 | else | |
2372 | ms = data * 1000; | |
2373 | ||
2374 | /* save initial values */ | |
2375 | spin_lock_bh(&hw->phy_lock); | |
793b883e SH |
2376 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2377 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2378 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2379 | ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
2380 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2381 | } else { | |
2382 | ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL); | |
2383 | ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER); | |
2384 | } | |
cd28ab6a SH |
2385 | spin_unlock_bh(&hw->phy_lock); |
2386 | ||
2387 | while (ms > 0) { | |
2388 | sky2_led(hw, port, onoff); | |
2389 | onoff = !onoff; | |
2390 | ||
2391 | if (msleep_interruptible(250)) | |
2392 | break; /* interrupted */ | |
2393 | ms -= 250; | |
2394 | } | |
2395 | ||
2396 | /* resume regularly scheduled programming */ | |
2397 | spin_lock_bh(&hw->phy_lock); | |
793b883e SH |
2398 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2399 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2400 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2401 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl); | |
2402 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2403 | } else { | |
2404 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
2405 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
2406 | } | |
cd28ab6a SH |
2407 | spin_unlock_bh(&hw->phy_lock); |
2408 | ||
2409 | return 0; | |
2410 | } | |
2411 | ||
2412 | static void sky2_get_pauseparam(struct net_device *dev, | |
2413 | struct ethtool_pauseparam *ecmd) | |
2414 | { | |
2415 | struct sky2_port *sky2 = netdev_priv(dev); | |
2416 | ||
2417 | ecmd->tx_pause = sky2->tx_pause; | |
2418 | ecmd->rx_pause = sky2->rx_pause; | |
2419 | ecmd->autoneg = sky2->autoneg; | |
2420 | } | |
2421 | ||
2422 | static int sky2_set_pauseparam(struct net_device *dev, | |
2423 | struct ethtool_pauseparam *ecmd) | |
2424 | { | |
2425 | struct sky2_port *sky2 = netdev_priv(dev); | |
2426 | int err = 0; | |
2427 | ||
2428 | sky2->autoneg = ecmd->autoneg; | |
2429 | sky2->tx_pause = ecmd->tx_pause != 0; | |
2430 | sky2->rx_pause = ecmd->rx_pause != 0; | |
2431 | ||
2432 | if (netif_running(dev)) { | |
2433 | sky2_down(dev); | |
2434 | err = sky2_up(dev); | |
2435 | } | |
2436 | ||
2437 | return err; | |
2438 | } | |
2439 | ||
2440 | #ifdef CONFIG_PM | |
2441 | static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2442 | { | |
2443 | struct sky2_port *sky2 = netdev_priv(dev); | |
2444 | ||
2445 | wol->supported = WAKE_MAGIC; | |
2446 | wol->wolopts = sky2->wol ? WAKE_MAGIC : 0; | |
2447 | } | |
2448 | ||
2449 | static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2450 | { | |
2451 | struct sky2_port *sky2 = netdev_priv(dev); | |
2452 | struct sky2_hw *hw = sky2->hw; | |
2453 | ||
2454 | if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0) | |
2455 | return -EOPNOTSUPP; | |
2456 | ||
2457 | sky2->wol = wol->wolopts == WAKE_MAGIC; | |
2458 | ||
2459 | if (sky2->wol) { | |
2460 | memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN); | |
2461 | ||
2462 | sky2_write16(hw, WOL_CTRL_STAT, | |
2463 | WOL_CTL_ENA_PME_ON_MAGIC_PKT | | |
2464 | WOL_CTL_ENA_MAGIC_PKT_UNIT); | |
2465 | } else | |
2466 | sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT); | |
2467 | ||
2468 | return 0; | |
2469 | } | |
2470 | #endif | |
2471 | ||
793b883e SH |
2472 | static void sky2_get_ringparam(struct net_device *dev, |
2473 | struct ethtool_ringparam *ering) | |
2474 | { | |
2475 | struct sky2_port *sky2 = netdev_priv(dev); | |
2476 | ||
2477 | ering->rx_max_pending = RX_MAX_PENDING; | |
2478 | ering->rx_mini_max_pending = 0; | |
2479 | ering->rx_jumbo_max_pending = 0; | |
2480 | ering->tx_max_pending = TX_RING_SIZE - 1; | |
2481 | ||
2482 | ering->rx_pending = sky2->rx_pending; | |
2483 | ering->rx_mini_pending = 0; | |
2484 | ering->rx_jumbo_pending = 0; | |
2485 | ering->tx_pending = sky2->tx_pending; | |
2486 | } | |
2487 | ||
2488 | static int sky2_set_ringparam(struct net_device *dev, | |
2489 | struct ethtool_ringparam *ering) | |
2490 | { | |
2491 | struct sky2_port *sky2 = netdev_priv(dev); | |
2492 | int err = 0; | |
2493 | ||
2494 | if (ering->rx_pending > RX_MAX_PENDING || | |
2495 | ering->rx_pending < 8 || | |
2496 | ering->tx_pending < MAX_SKB_TX_LE || | |
2497 | ering->tx_pending > TX_RING_SIZE - 1) | |
2498 | return -EINVAL; | |
2499 | ||
2500 | if (netif_running(dev)) | |
2501 | sky2_down(dev); | |
2502 | ||
2503 | sky2->rx_pending = ering->rx_pending; | |
2504 | sky2->tx_pending = ering->tx_pending; | |
2505 | ||
2506 | if (netif_running(dev)) | |
2507 | err = sky2_up(dev); | |
2508 | ||
2509 | return err; | |
2510 | } | |
2511 | ||
793b883e SH |
2512 | static int sky2_get_regs_len(struct net_device *dev) |
2513 | { | |
6e4cbb34 | 2514 | return 0x4000; |
793b883e SH |
2515 | } |
2516 | ||
2517 | /* | |
2518 | * Returns copy of control register region | |
6e4cbb34 | 2519 | * Note: access to the RAM address register set will cause timeouts. |
793b883e SH |
2520 | */ |
2521 | static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
2522 | void *p) | |
2523 | { | |
2524 | const struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2525 | const void __iomem *io = sky2->hw->regs; |
793b883e | 2526 | |
6e4cbb34 | 2527 | BUG_ON(regs->len < B3_RI_WTO_R1); |
793b883e | 2528 | regs->version = 1; |
6e4cbb34 | 2529 | memset(p, 0, regs->len); |
793b883e | 2530 | |
6e4cbb34 SH |
2531 | memcpy_fromio(p, io, B3_RAM_ADDR); |
2532 | ||
2533 | memcpy_fromio(p + B3_RI_WTO_R1, | |
2534 | io + B3_RI_WTO_R1, | |
2535 | regs->len - B3_RI_WTO_R1); | |
793b883e | 2536 | } |
cd28ab6a SH |
2537 | |
2538 | static struct ethtool_ops sky2_ethtool_ops = { | |
793b883e SH |
2539 | .get_settings = sky2_get_settings, |
2540 | .set_settings = sky2_set_settings, | |
2541 | .get_drvinfo = sky2_get_drvinfo, | |
2542 | .get_msglevel = sky2_get_msglevel, | |
2543 | .set_msglevel = sky2_set_msglevel, | |
2544 | .get_regs_len = sky2_get_regs_len, | |
2545 | .get_regs = sky2_get_regs, | |
2546 | .get_link = ethtool_op_get_link, | |
2547 | .get_sg = ethtool_op_get_sg, | |
2548 | .set_sg = ethtool_op_set_sg, | |
2549 | .get_tx_csum = ethtool_op_get_tx_csum, | |
2550 | .set_tx_csum = ethtool_op_set_tx_csum, | |
2551 | .get_tso = ethtool_op_get_tso, | |
2552 | .set_tso = ethtool_op_set_tso, | |
2553 | .get_rx_csum = sky2_get_rx_csum, | |
2554 | .set_rx_csum = sky2_set_rx_csum, | |
2555 | .get_strings = sky2_get_strings, | |
2556 | .get_ringparam = sky2_get_ringparam, | |
2557 | .set_ringparam = sky2_set_ringparam, | |
cd28ab6a SH |
2558 | .get_pauseparam = sky2_get_pauseparam, |
2559 | .set_pauseparam = sky2_set_pauseparam, | |
2560 | #ifdef CONFIG_PM | |
793b883e SH |
2561 | .get_wol = sky2_get_wol, |
2562 | .set_wol = sky2_set_wol, | |
cd28ab6a | 2563 | #endif |
793b883e | 2564 | .phys_id = sky2_phys_id, |
cd28ab6a SH |
2565 | .get_stats_count = sky2_get_stats_count, |
2566 | .get_ethtool_stats = sky2_get_ethtool_stats, | |
2567 | }; | |
2568 | ||
2569 | /* Initialize network device */ | |
2570 | static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, | |
2571 | unsigned port, int highmem) | |
2572 | { | |
2573 | struct sky2_port *sky2; | |
2574 | struct net_device *dev = alloc_etherdev(sizeof(*sky2)); | |
2575 | ||
2576 | if (!dev) { | |
2577 | printk(KERN_ERR "sky2 etherdev alloc failed"); | |
2578 | return NULL; | |
2579 | } | |
2580 | ||
2581 | SET_MODULE_OWNER(dev); | |
2582 | SET_NETDEV_DEV(dev, &hw->pdev->dev); | |
2583 | dev->open = sky2_up; | |
2584 | dev->stop = sky2_down; | |
2585 | dev->hard_start_xmit = sky2_xmit_frame; | |
2586 | dev->get_stats = sky2_get_stats; | |
2587 | dev->set_multicast_list = sky2_set_multicast; | |
2588 | dev->set_mac_address = sky2_set_mac_address; | |
2589 | dev->change_mtu = sky2_change_mtu; | |
2590 | SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); | |
2591 | dev->tx_timeout = sky2_tx_timeout; | |
2592 | dev->watchdog_timeo = TX_WATCHDOG; | |
2593 | if (port == 0) | |
2594 | dev->poll = sky2_poll; | |
2595 | dev->weight = NAPI_WEIGHT; | |
2596 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2597 | dev->poll_controller = sky2_netpoll; | |
2598 | #endif | |
cd28ab6a SH |
2599 | |
2600 | sky2 = netdev_priv(dev); | |
2601 | sky2->netdev = dev; | |
2602 | sky2->hw = hw; | |
2603 | sky2->msg_enable = netif_msg_init(debug, default_msg); | |
2604 | ||
2605 | spin_lock_init(&sky2->tx_lock); | |
2606 | /* Auto speed and flow control */ | |
2607 | sky2->autoneg = AUTONEG_ENABLE; | |
2608 | sky2->tx_pause = 0; | |
2609 | sky2->rx_pause = 1; | |
2610 | sky2->duplex = -1; | |
2611 | sky2->speed = -1; | |
2612 | sky2->advertising = sky2_supported_modes(hw); | |
2613 | sky2->rx_csum = 1; | |
793b883e SH |
2614 | tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2); |
2615 | sky2->tx_pending = TX_DEF_PENDING; | |
2616 | sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING; | |
cd28ab6a SH |
2617 | |
2618 | hw->dev[port] = dev; | |
2619 | ||
2620 | sky2->port = port; | |
2621 | ||
793b883e | 2622 | dev->features |= NETIF_F_LLTX | NETIF_F_TSO; |
cd28ab6a SH |
2623 | if (highmem) |
2624 | dev->features |= NETIF_F_HIGHDMA; | |
793b883e | 2625 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
cd28ab6a SH |
2626 | |
2627 | /* read the mac address */ | |
793b883e | 2628 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); |
cd28ab6a SH |
2629 | |
2630 | /* device is off until link detection */ | |
2631 | netif_carrier_off(dev); | |
2632 | netif_stop_queue(dev); | |
2633 | ||
2634 | return dev; | |
2635 | } | |
2636 | ||
2637 | static inline void sky2_show_addr(struct net_device *dev) | |
2638 | { | |
2639 | const struct sky2_port *sky2 = netdev_priv(dev); | |
2640 | ||
2641 | if (netif_msg_probe(sky2)) | |
2642 | printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n", | |
2643 | dev->name, | |
2644 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
2645 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
2646 | } | |
2647 | ||
2648 | static int __devinit sky2_probe(struct pci_dev *pdev, | |
2649 | const struct pci_device_id *ent) | |
2650 | { | |
793b883e | 2651 | struct net_device *dev, *dev1 = NULL; |
cd28ab6a SH |
2652 | struct sky2_hw *hw; |
2653 | int err, using_dac = 0; | |
2654 | ||
793b883e SH |
2655 | err = pci_enable_device(pdev); |
2656 | if (err) { | |
cd28ab6a SH |
2657 | printk(KERN_ERR PFX "%s cannot enable PCI device\n", |
2658 | pci_name(pdev)); | |
2659 | goto err_out; | |
2660 | } | |
2661 | ||
793b883e SH |
2662 | err = pci_request_regions(pdev, DRV_NAME); |
2663 | if (err) { | |
cd28ab6a SH |
2664 | printk(KERN_ERR PFX "%s cannot obtain PCI resources\n", |
2665 | pci_name(pdev)); | |
793b883e | 2666 | goto err_out; |
cd28ab6a SH |
2667 | } |
2668 | ||
2669 | pci_set_master(pdev); | |
2670 | ||
2671 | if (sizeof(dma_addr_t) > sizeof(u32)) { | |
2672 | err = pci_set_dma_mask(pdev, DMA_64BIT_MASK); | |
2673 | if (!err) | |
2674 | using_dac = 1; | |
2675 | } | |
2676 | ||
2677 | if (!using_dac) { | |
2678 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
2679 | if (err) { | |
2680 | printk(KERN_ERR PFX "%s no usable DMA configuration\n", | |
2681 | pci_name(pdev)); | |
2682 | goto err_out_free_regions; | |
2683 | } | |
2684 | } | |
cd28ab6a SH |
2685 | #ifdef __BIG_ENDIAN |
2686 | /* byte swap decriptors in hardware */ | |
2687 | { | |
2688 | u32 reg; | |
2689 | ||
2690 | pci_read_config_dword(pdev, PCI_DEV_REG2, ®); | |
2691 | reg |= PCI_REV_DESC; | |
2692 | pci_write_config_dword(pdev, PCI_DEV_REG2, reg); | |
2693 | } | |
2694 | #endif | |
2695 | ||
2696 | err = -ENOMEM; | |
2697 | hw = kmalloc(sizeof(*hw), GFP_KERNEL); | |
2698 | if (!hw) { | |
2699 | printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n", | |
2700 | pci_name(pdev)); | |
2701 | goto err_out_free_regions; | |
2702 | } | |
2703 | ||
2704 | memset(hw, 0, sizeof(*hw)); | |
2705 | hw->pdev = pdev; | |
2706 | spin_lock_init(&hw->phy_lock); | |
2707 | ||
2708 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
2709 | if (!hw->regs) { | |
2710 | printk(KERN_ERR PFX "%s: cannot map device registers\n", | |
2711 | pci_name(pdev)); | |
2712 | goto err_out_free_hw; | |
2713 | } | |
2714 | ||
cd28ab6a SH |
2715 | err = sky2_reset(hw); |
2716 | if (err) | |
793b883e | 2717 | goto err_out_iounmap; |
cd28ab6a | 2718 | |
793b883e | 2719 | printk(KERN_INFO PFX "addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n", |
cd28ab6a | 2720 | pci_resource_start(pdev, 0), pdev->irq, |
793b883e SH |
2721 | yukon_name[hw->chip_id - CHIP_ID_YUKON], |
2722 | hw->chip_id, hw->chip_rev); | |
cd28ab6a | 2723 | |
793b883e SH |
2724 | dev = sky2_init_netdev(hw, 0, using_dac); |
2725 | if (!dev) | |
cd28ab6a SH |
2726 | goto err_out_free_pci; |
2727 | ||
793b883e SH |
2728 | err = register_netdev(dev); |
2729 | if (err) { | |
cd28ab6a SH |
2730 | printk(KERN_ERR PFX "%s: cannot register net device\n", |
2731 | pci_name(pdev)); | |
2732 | goto err_out_free_netdev; | |
2733 | } | |
2734 | ||
2735 | sky2_show_addr(dev); | |
2736 | ||
2737 | if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) { | |
2738 | if (register_netdev(dev1) == 0) | |
2739 | sky2_show_addr(dev1); | |
2740 | else { | |
2741 | /* Failure to register second port need not be fatal */ | |
793b883e SH |
2742 | printk(KERN_WARNING PFX |
2743 | "register of second port failed\n"); | |
cd28ab6a SH |
2744 | hw->dev[1] = NULL; |
2745 | free_netdev(dev1); | |
2746 | } | |
2747 | } | |
2748 | ||
793b883e SH |
2749 | err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw); |
2750 | if (err) { | |
2751 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
2752 | pci_name(pdev), pdev->irq); | |
2753 | goto err_out_unregister; | |
2754 | } | |
2755 | ||
2756 | hw->intr_mask = Y2_IS_BASE; | |
2757 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
2758 | ||
2759 | pci_set_drvdata(pdev, hw); | |
2760 | ||
cd28ab6a SH |
2761 | return 0; |
2762 | ||
793b883e SH |
2763 | err_out_unregister: |
2764 | if (dev1) { | |
2765 | unregister_netdev(dev1); | |
2766 | free_netdev(dev1); | |
2767 | } | |
2768 | unregister_netdev(dev); | |
cd28ab6a SH |
2769 | err_out_free_netdev: |
2770 | free_netdev(dev); | |
cd28ab6a | 2771 | err_out_free_pci: |
793b883e | 2772 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
cd28ab6a SH |
2773 | pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
2774 | err_out_iounmap: | |
2775 | iounmap(hw->regs); | |
2776 | err_out_free_hw: | |
2777 | kfree(hw); | |
2778 | err_out_free_regions: | |
2779 | pci_release_regions(pdev); | |
cd28ab6a | 2780 | pci_disable_device(pdev); |
cd28ab6a SH |
2781 | err_out: |
2782 | return err; | |
2783 | } | |
2784 | ||
2785 | static void __devexit sky2_remove(struct pci_dev *pdev) | |
2786 | { | |
793b883e | 2787 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
cd28ab6a SH |
2788 | struct net_device *dev0, *dev1; |
2789 | ||
793b883e | 2790 | if (!hw) |
cd28ab6a SH |
2791 | return; |
2792 | ||
cd28ab6a | 2793 | dev0 = hw->dev[0]; |
793b883e SH |
2794 | dev1 = hw->dev[1]; |
2795 | if (dev1) | |
2796 | unregister_netdev(dev1); | |
cd28ab6a SH |
2797 | unregister_netdev(dev0); |
2798 | ||
793b883e | 2799 | sky2_write32(hw, B0_IMSK, 0); |
cd28ab6a | 2800 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
793b883e | 2801 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
cd28ab6a SH |
2802 | |
2803 | free_irq(pdev->irq, hw); | |
793b883e | 2804 | pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
cd28ab6a SH |
2805 | pci_release_regions(pdev); |
2806 | pci_disable_device(pdev); | |
793b883e | 2807 | |
cd28ab6a SH |
2808 | if (dev1) |
2809 | free_netdev(dev1); | |
2810 | free_netdev(dev0); | |
2811 | iounmap(hw->regs); | |
2812 | kfree(hw); | |
2813 | pci_set_drvdata(pdev, NULL); | |
2814 | } | |
2815 | ||
2816 | #ifdef CONFIG_PM | |
2817 | static int sky2_suspend(struct pci_dev *pdev, pm_message_t state) | |
2818 | { | |
793b883e | 2819 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
cd28ab6a SH |
2820 | int i, wol = 0; |
2821 | ||
2822 | for (i = 0; i < 2; i++) { | |
2823 | struct net_device *dev = hw->dev[i]; | |
2824 | ||
2825 | if (dev) { | |
2826 | struct sky2_port *sky2 = netdev_priv(dev); | |
2827 | if (netif_running(dev)) { | |
2828 | netif_carrier_off(dev); | |
2829 | sky2_down(dev); | |
2830 | } | |
2831 | netif_device_detach(dev); | |
2832 | wol |= sky2->wol; | |
2833 | } | |
2834 | } | |
2835 | ||
2836 | pci_save_state(pdev); | |
2837 | pci_enable_wake(pdev, pci_choose_state(pdev, state), wol); | |
2838 | pci_disable_device(pdev); | |
2839 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
2840 | ||
2841 | return 0; | |
2842 | } | |
2843 | ||
2844 | static int sky2_resume(struct pci_dev *pdev) | |
2845 | { | |
793b883e | 2846 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
cd28ab6a SH |
2847 | int i; |
2848 | ||
2849 | pci_set_power_state(pdev, PCI_D0); | |
2850 | pci_restore_state(pdev); | |
2851 | pci_enable_wake(pdev, PCI_D0, 0); | |
2852 | ||
2853 | sky2_reset(hw); | |
2854 | ||
2855 | for (i = 0; i < 2; i++) { | |
2856 | struct net_device *dev = hw->dev[i]; | |
2857 | if (dev) { | |
2858 | netif_device_attach(dev); | |
2859 | if (netif_running(dev)) | |
2860 | sky2_up(dev); | |
2861 | } | |
2862 | } | |
2863 | return 0; | |
2864 | } | |
2865 | #endif | |
2866 | ||
2867 | static struct pci_driver sky2_driver = { | |
793b883e SH |
2868 | .name = DRV_NAME, |
2869 | .id_table = sky2_id_table, | |
2870 | .probe = sky2_probe, | |
2871 | .remove = __devexit_p(sky2_remove), | |
cd28ab6a | 2872 | #ifdef CONFIG_PM |
793b883e SH |
2873 | .suspend = sky2_suspend, |
2874 | .resume = sky2_resume, | |
cd28ab6a SH |
2875 | #endif |
2876 | }; | |
2877 | ||
2878 | static int __init sky2_init_module(void) | |
2879 | { | |
cd28ab6a SH |
2880 | return pci_module_init(&sky2_driver); |
2881 | } | |
2882 | ||
2883 | static void __exit sky2_cleanup_module(void) | |
2884 | { | |
2885 | pci_unregister_driver(&sky2_driver); | |
2886 | } | |
2887 | ||
2888 | module_init(sky2_init_module); | |
2889 | module_exit(sky2_cleanup_module); | |
2890 | ||
2891 | MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); | |
2892 | MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>"); | |
2893 | MODULE_LICENSE("GPL"); |