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phy: export phy_mii_ioctl
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
c2cb71fa 54#define DRV_VERSION "1.17"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 133 { 0 }
134};
793b883e 135
cd28ab6a
SH		 136MODULE_DEVICE_TABLE(pci, sky2_id_table);
137
138/* Avoid conditionals by using array */
139static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
140static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 141static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 142
92f965e8
SH		 143/* This driver supports yukon2 chipset only */
144static const char *yukon2_name[] = {
145 "XL", /* 0xb3 */
146 "EC Ultra", /* 0xb4 */
93745494 147 "Extreme", /* 0xb5 */
92f965e8
SH		 148 "EC", /* 0xb6 */
149 "FE", /* 0xb7 */
793b883e
SH		 150};
151
d1b139c0
SH		 152static void sky2_set_multicast(struct net_device *dev);
153
793b883e 154/* Access to external PHY */
ef743d33 155static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 156{
157 int i;
158
159 gma_write16(hw, port, GM_SMI_DATA, val);
160 gma_write16(hw, port, GM_SMI_CTRL,
161 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
162
163 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 164 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 165 return 0;
793b883e 166 udelay(1);
cd28ab6a 167 }
ef743d33 168
793b883e 169 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 170 return -ETIMEDOUT;
cd28ab6a
SH		 171}
172
ef743d33 173static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 174{
175 int i;
176
793b883e 177 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 178 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
179
180 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 181 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
182 *val = gma_read16(hw, port, GM_SMI_DATA);
183 return 0;
184 }
185
793b883e 186 udelay(1);
cd28ab6a
SH		 187 }
188
ef743d33
SH		 189 return -ETIMEDOUT;
190}
191
192static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
193{
194 u16 v;
195
196 if (__gm_phy_read(hw, port, reg, &v) != 0)
197 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
198 return v;
cd28ab6a
SH		 199}
200
5afa0a9c 201
ae306cca
SH		 202static void sky2_power_on(struct sky2_hw *hw)
203{
204 /* switch power to VCC (WA for VAUX problem) */
205 sky2_write8(hw, B0_POWER_CTRL,
206 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 207
ae306cca
SH		 208 /* disable Core Clock Division, */
209 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 210
ae306cca
SH		 211 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
212 /* enable bits are inverted */
213 sky2_write8(hw, B2_Y2_CLK_GATE,
214 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
215 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
216 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
217 else
218 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 219
b2345773
SH		 220 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
221 hw->chip_id == CHIP_ID_YUKON_EX) {
fc99fe06 222 u32 reg;
5afa0a9c 223
b2345773
SH		 224 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
225
fc99fe06
SH		 226 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
227 /* set all bits to 0 except bits 15..12 and 8 */
228 reg &= P_ASPM_CONTROL_MSK;
229 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
230
231 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
232 /* set all bits to 0 except bits 28 & 27 */
233 reg &= P_CTL_TIM_VMAIN_AV_MSK;
234 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
235
236 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 237
238 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
239 reg = sky2_read32(hw, B2_GP_IO);
240 reg |= GLB_GPIO_STAT_RACE_DIS;
241 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 242
243 sky2_read32(hw, B2_GP_IO);
5afa0a9c 244 }
ae306cca 245}
5afa0a9c 246
ae306cca
SH		 247static void sky2_power_aux(struct sky2_hw *hw)
248{
249 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
250 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
251 else
252 /* enable bits are inverted */
253 sky2_write8(hw, B2_Y2_CLK_GATE,
254 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
255 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
256 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
257
258 /* switch power to VAUX */
259 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
260 sky2_write8(hw, B0_POWER_CTRL,
261 (PC_VAUX_ENA | PC_VCC_ENA |
262 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 263}
264
d3bcfbeb 265static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 266{
267 u16 reg;
268
269 /* disable all GMAC IRQ's */
270 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
271 /* disable PHY IRQs */
272 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 273
cd28ab6a
SH		 274 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
275 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
276 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
277 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
278
279 reg = gma_read16(hw, port, GM_RX_CTRL);
280 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
281 gma_write16(hw, port, GM_RX_CTRL, reg);
282}
283
16ad91e1
SH		 284/* flow control to advertise bits */
285static const u16 copper_fc_adv[] = {
286 [FC_NONE] = 0,
287 [FC_TX] = PHY_M_AN_ASP,
288 [FC_RX] = PHY_M_AN_PC,
289 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
290};
291
292/* flow control to advertise bits when using 1000BaseX */
293static const u16 fiber_fc_adv[] = {
294 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
295 [FC_TX] = PHY_M_P_ASYM_MD_X,
296 [FC_RX] = PHY_M_P_SYM_MD_X,
297 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
298};
299
300/* flow control to GMA disable bits */
301static const u16 gm_fc_disable[] = {
302 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
303 [FC_TX] = GM_GPCR_FC_RX_DIS,
304 [FC_RX] = GM_GPCR_FC_TX_DIS,
305 [FC_BOTH] = 0,
306};
307
308
cd28ab6a
SH		 309static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
310{
311 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 312 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 313
93745494
SH		 314 if (sky2->autoneg == AUTONEG_ENABLE
315 && !(hw->chip_id == CHIP_ID_YUKON_XL
316 || hw->chip_id == CHIP_ID_YUKON_EC_U
317 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 318 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
319
320 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 321 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 322 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
323
53419c68 324 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 325 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 326 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 327 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
328 else
53419c68
SH		 329 /* set master & slave downshift counter to 1x */
330 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 331
332 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
333 }
334
335 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 336 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 337 if (hw->chip_id == CHIP_ID_YUKON_FE) {
338 /* enable automatic crossover */
339 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
340 } else {
341 /* disable energy detect */
342 ctrl &= ~PHY_M_PC_EN_DET_MSK;
343
344 /* enable automatic crossover */
345 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
346
53419c68 347 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494
SH		 348 if (sky2->autoneg == AUTONEG_ENABLE
349 && (hw->chip_id == CHIP_ID_YUKON_XL
350 || hw->chip_id == CHIP_ID_YUKON_EC_U
351 || hw->chip_id == CHIP_ID_YUKON_EX)) {
53419c68 352 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 353 ctrl &= ~PHY_M_PC_DSC_MSK;
354 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
355 }
356 }
cd28ab6a
SH		 357 } else {
358 /* workaround for deviation #4.88 (CRC errors) */
359 /* disable Automatic Crossover */
360
361 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 362 }
cd28ab6a 363
b89165f2
SH		 364 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
365
366 /* special setup for PHY 88E1112 Fiber */
367 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
368 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 369
b89165f2
SH		 370 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
371 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
372 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
373 ctrl &= ~PHY_M_MAC_MD_MSK;
374 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
375 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
376
377 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 378 /* select page 1 to access Fiber registers */
379 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 380
381 /* for SFP-module set SIGDET polarity to low */
382 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
383 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 384 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 385 }
b89165f2
SH		 386
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 388 }
389
7800fddc 390 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 391 ct1000 = 0;
392 adv = PHY_AN_CSMA;
2eaba1a2 393 reg = 0;
cd28ab6a
SH		 394
395 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 396 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 397 if (sky2->advertising & ADVERTISED_1000baseT_Full)
398 ct1000 |= PHY_M_1000C_AFD;
399 if (sky2->advertising & ADVERTISED_1000baseT_Half)
400 ct1000 |= PHY_M_1000C_AHD;
401 if (sky2->advertising & ADVERTISED_100baseT_Full)
402 adv |= PHY_M_AN_100_FD;
403 if (sky2->advertising & ADVERTISED_100baseT_Half)
404 adv |= PHY_M_AN_100_HD;
405 if (sky2->advertising & ADVERTISED_10baseT_Full)
406 adv |= PHY_M_AN_10_FD;
407 if (sky2->advertising & ADVERTISED_10baseT_Half)
408 adv |= PHY_M_AN_10_HD;
709c6e7b 409
16ad91e1 410 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 411 } else { /* special defines for FIBER (88E1040S only) */
412 if (sky2->advertising & ADVERTISED_1000baseT_Full)
413 adv |= PHY_M_AN_1000X_AFD;
414 if (sky2->advertising & ADVERTISED_1000baseT_Half)
415 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 416
16ad91e1 417 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 418 }
cd28ab6a
SH		 419
420 /* Restart Auto-negotiation */
421 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
422 } else {
423 /* forced speed/duplex settings */
424 ct1000 = PHY_M_1000C_MSE;
425
2eaba1a2
SH		 426 /* Disable auto update for duplex flow control and speed */
427 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 428
429 switch (sky2->speed) {
430 case SPEED_1000:
431 ctrl |= PHY_CT_SP1000;
2eaba1a2 432 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 433 break;
434 case SPEED_100:
435 ctrl |= PHY_CT_SP100;
2eaba1a2 436 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 437 break;
438 }
439
2eaba1a2
SH		 440 if (sky2->duplex == DUPLEX_FULL) {
441 reg |= GM_GPCR_DUP_FULL;
442 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 443 } else if (sky2->speed < SPEED_1000)
444 sky2->flow_mode = FC_NONE;
2eaba1a2 445
2eaba1a2 446
16ad91e1 447 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 448
449 /* Forward pause packets to GMAC? */
16ad91e1 450 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 451 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
452 else
453 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 454 }
455
2eaba1a2
SH		 456 gma_write16(hw, port, GM_GP_CTRL, reg);
457
cd28ab6a
SH		 458 if (hw->chip_id != CHIP_ID_YUKON_FE)
459 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
460
461 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
462 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
463
464 /* Setup Phy LED's */
465 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
466 ledover = 0;
467
468 switch (hw->chip_id) {
469 case CHIP_ID_YUKON_FE:
470 /* on 88E3082 these bits are at 11..9 (shifted left) */
471 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
472
473 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
474
475 /* delete ACT LED control bits */
476 ctrl &= ~PHY_M_FELP_LED1_MSK;
477 /* change ACT LED control to blink mode */
478 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
479 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
480 break;
481
482 case CHIP_ID_YUKON_XL:
793b883e 483 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 484
485 /* select page 3 to access LED control register */
486 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
487
488 /* set LED Function Control register */
ed6d32c7
SH		 489 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
490 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
491 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
492 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
493 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 494
495 /* set Polarity Control register */
496 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 497 (PHY_M_POLC_LS1_P_MIX(4) |
498 PHY_M_POLC_IS0_P_MIX(4) |
499 PHY_M_POLC_LOS_CTRL(2) |
500 PHY_M_POLC_INIT_CTRL(2) |
501 PHY_M_POLC_STA1_CTRL(2) |
502 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 503
504 /* restore page register */
793b883e 505 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 506 break;
93745494 507
ed6d32c7 508 case CHIP_ID_YUKON_EC_U:
93745494 509 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 510 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
511
512 /* select page 3 to access LED control register */
513 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
514
515 /* set LED Function Control register */
516 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
517 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
518 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
519 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
520 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
521
522 /* set Blink Rate in LED Timer Control Register */
523 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
524 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
525 /* restore page register */
526 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
527 break;
cd28ab6a
SH		 528
529 default:
530 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
531 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
532 /* turn off the Rx LED (LED_RX) */
0efdf262 533 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 534 }
535
9467a8fc
SH		 536 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
537 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 538 /* apply fixes in PHY AFE */
ed6d32c7
SH		 539 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
540
977bdf06 541 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 542 gm_phy_write(hw, port, 0x18, 0xaa99);
543 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 544
977bdf06 545 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 546 gm_phy_write(hw, port, 0x18, 0xa204);
547 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 548
549 /* set page register to 0 */
9467a8fc 550 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
93745494 551 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 552 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 553
977bdf06
SH		 554 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
555 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 556 ledover |= PHY_M_LED_MO_100;
977bdf06 557 }
cd28ab6a 558
977bdf06
SH		 559 if (ledover)
560 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
561
562 }
2eaba1a2 563
d571b694 564 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 565 if (sky2->autoneg == AUTONEG_ENABLE)
566 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
567 else
568 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
569}
570
d3bcfbeb
SH		 571static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
572{
573 u32 reg1;
574 static const u32 phy_power[]
575 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
576
577 /* looks like this XL is back asswards .. */
578 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
579 onoff = !onoff;
580
aed2cec4 581 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 582 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 583 if (onoff)
584 /* Turn off phy power saving */
585 reg1 &= ~phy_power[port];
586 else
587 reg1 |= phy_power[port];
588
589 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 590 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 591 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 592 udelay(100);
593}
594
1b537565
SH		 595/* Force a renegotiation */
596static void sky2_phy_reinit(struct sky2_port *sky2)
597{
e07b1aa8 598 spin_lock_bh(&sky2->phy_lock);
1b537565 599 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 600 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 601}
602
e3173832
SH		 603/* Put device in state to listen for Wake On Lan */
604static void sky2_wol_init(struct sky2_port *sky2)
605{
606 struct sky2_hw *hw = sky2->hw;
607 unsigned port = sky2->port;
608 enum flow_control save_mode;
609 u16 ctrl;
610 u32 reg1;
611
612 /* Bring hardware out of reset */
613 sky2_write16(hw, B0_CTST, CS_RST_CLR);
614 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
615
616 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
617 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
618
619 /* Force to 10/100
620 * sky2_reset will re-enable on resume
621 */
622 save_mode = sky2->flow_mode;
623 ctrl = sky2->advertising;
624
625 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
626 sky2->flow_mode = FC_NONE;
627 sky2_phy_power(hw, port, 1);
628 sky2_phy_reinit(sky2);
629
630 sky2->flow_mode = save_mode;
631 sky2->advertising = ctrl;
632
633 /* Set GMAC to no flow control and auto update for speed/duplex */
634 gma_write16(hw, port, GM_GP_CTRL,
635 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
636 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
637
638 /* Set WOL address */
639 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
640 sky2->netdev->dev_addr, ETH_ALEN);
641
642 /* Turn on appropriate WOL control bits */
643 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
644 ctrl = 0;
645 if (sky2->wol & WAKE_PHY)
646 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
647 else
648 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
649
650 if (sky2->wol & WAKE_MAGIC)
651 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
652 else
653 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
654
655 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
656 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
657
658 /* Turn on legacy PCI-Express PME mode */
659 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
660 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
661 reg1 |= PCI_Y2_PME_LEGACY;
662 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
663 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
664
665 /* block receiver */
666 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
667
668}
669
69161611
SH		 670static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
671{
672 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev != CHIP_REV_YU_EX_A0) {
673 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
674 TX_STFW_ENA |
675 (hw->dev[port]->mtu > ETH_DATA_LEN) ? TX_JUMBO_ENA : TX_JUMBO_DIS);
676 } else {
677 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
678 /* set Tx GMAC FIFO Almost Empty Threshold */
679 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
680 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
681
682 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
683 TX_JUMBO_ENA | TX_STFW_DIS);
684
685 /* Can't do offload because of lack of store/forward */
686 hw->dev[port]->features &= ~(NETIF_F_TSO | NETIF_F_SG
687 | NETIF_F_ALL_CSUM);
688 } else
689 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
690 TX_JUMBO_DIS | TX_STFW_ENA);
691 }
692}
693
cd28ab6a
SH		 694static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
695{
696 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
697 u16 reg;
25cccecc 698 u32 rx_reg;
cd28ab6a
SH		 699 int i;
700 const u8 *addr = hw->dev[port]->dev_addr;
701
f350339c
SH		 702 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
703 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 704
705 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
706
793b883e 707 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 708 /* WA DEV_472 -- looks like crossed wires on port 2 */
709 /* clear GMAC 1 Control reset */
710 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
711 do {
712 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
713 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
714 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
715 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
716 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
717 }
718
793b883e 719 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 720
2eaba1a2
SH		 721 /* Enable Transmit FIFO Underrun */
722 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
723
e07b1aa8 724 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 725 sky2_phy_init(hw, port);
e07b1aa8 726 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 727
728 /* MIB clear */
729 reg = gma_read16(hw, port, GM_PHY_ADDR);
730 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
731
43f2f104
SH		 732 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
733 gma_read16(hw, port, i);
cd28ab6a
SH		 734 gma_write16(hw, port, GM_PHY_ADDR, reg);
735
736 /* transmit control */
737 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
738
739 /* receive control reg: unicast + multicast + no FCS */
740 gma_write16(hw, port, GM_RX_CTRL,
793b883e 741 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 742
743 /* transmit flow control */
744 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
745
746 /* transmit parameter */
747 gma_write16(hw, port, GM_TX_PARAM,
748 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
749 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
750 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
751 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
752
753 /* serial mode register */
754 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 755 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 756
6b1a3aef 757 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 758 reg |= GM_SMOD_JUMBO_ENA;
759
760 gma_write16(hw, port, GM_SERIAL_MODE, reg);
761
cd28ab6a
SH		 762 /* virtual address for data */
763 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
764
793b883e
SH		 765 /* physical address: used for pause frames */
766 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
767
768 /* ignore counter overflows */
cd28ab6a
SH		 769 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
770 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
771 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
772
773 /* Configure Rx MAC FIFO */
774 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 775 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
69161611 776 if (hw->chip_id == CHIP_ID_YUKON_EX)
25cccecc 777 rx_reg |= GMF_RX_OVER_ON;
69161611 778
25cccecc 779 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 780
d571b694 781 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 782 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 783
8df9a876
SH		 784 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
785 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 786
787 /* Configure Tx MAC FIFO */
788 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
789 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 790
93745494 791 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 792 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 793 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 794
69161611 795 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 796 }
797
cd28ab6a
SH		 798}
799
67712901
SH		 800/* Assign Ram Buffer allocation to queue */
801static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 802{
67712901
SH		 803 u32 end;
804
805 /* convert from K bytes to qwords used for hw register */
806 start *= 1024/8;
807 space *= 1024/8;
808 end = start + space - 1;
793b883e 809
cd28ab6a
SH		 810 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
811 sky2_write32(hw, RB_ADDR(q, RB_START), start);
812 sky2_write32(hw, RB_ADDR(q, RB_END), end);
813 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
814 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
815
816 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 817 u32 tp = space - space/4;
793b883e 818
1c28f6ba
SH		 819 /* On receive queue's set the thresholds
820 * give receiver priority when > 3/4 full
821 * send pause when down to 2K
822 */
823 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
824 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 825
1c28f6ba
SH		 826 tp = space - 2048/8;
827 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
828 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 829 } else {
830 /* Enable store & forward on Tx queue's because
831 * Tx FIFO is only 1K on Yukon
832 */
833 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
834 }
835
836 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 837 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 838}
839
cd28ab6a 840/* Setup Bus Memory Interface */
af4ed7e6 841static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 842{
843 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
844 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
845 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 846 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 847}
848
cd28ab6a
SH		 849/* Setup prefetch unit registers. This is the interface between
850 * hardware and driver list elements
851 */
8cc048e3 852static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 853 u64 addr, u32 last)
854{
cd28ab6a
SH		 855 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
856 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
857 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
858 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
859 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
860 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 861
862 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 863}
864
793b883e
SH		 865static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
866{
867 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
868
cb5d9547 869 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 870 le->ctrl = 0;
793b883e
SH		 871 return le;
872}
cd28ab6a 873
291ea614
SH		 874static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
875 struct sky2_tx_le *le)
876{
877 return sky2->tx_ring + (le - sky2->tx_le);
878}
879
290d4de5
SH		 880/* Update chip's next pointer */
881static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 882{
50432cb5 883 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 884 wmb();
50432cb5
SH		 885 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
886
887 /* Synchronize I/O on since next processor may write to tail */
888 mmiowb();
cd28ab6a
SH		 889}
890
793b883e 891
cd28ab6a
SH		 892static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
893{
894 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 895 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 896 le->ctrl = 0;
cd28ab6a
SH		 897 return le;
898}
899
14d0263f
SH		 900/* Build description to hardware for one receive segment */
901static void sky2_rx_add(struct sky2_port *sky2, u8 op,
902 dma_addr_t map, unsigned len)
cd28ab6a
SH		 903{
904 struct sky2_rx_le *le;
36eb0c71 905 u32 hi = upper_32_bits(map);
cd28ab6a 906
793b883e 907 if (sky2->rx_addr64 != hi) {
cd28ab6a 908 le = sky2_next_rx(sky2);
793b883e 909 le->addr = cpu_to_le32(hi);
cd28ab6a 910 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 911 sky2->rx_addr64 = upper_32_bits(map + len);
cd28ab6a 912 }
793b883e 913
cd28ab6a 914 le = sky2_next_rx(sky2);
734d1868
SH		 915 le->addr = cpu_to_le32((u32) map);
916 le->length = cpu_to_le16(len);
14d0263f 917 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 918}
919
14d0263f
SH		 920/* Build description to hardware for one possibly fragmented skb */
921static void sky2_rx_submit(struct sky2_port *sky2,
922 const struct rx_ring_info *re)
923{
924 int i;
925
926 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
927
928 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
929 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
930}
931
932
933static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
934 unsigned size)
935{
936 struct sk_buff *skb = re->skb;
937 int i;
938
939 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
940 pci_unmap_len_set(re, data_size, size);
941
942 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
943 re->frag_addr[i] = pci_map_page(pdev,
944 skb_shinfo(skb)->frags[i].page,
945 skb_shinfo(skb)->frags[i].page_offset,
946 skb_shinfo(skb)->frags[i].size,
947 PCI_DMA_FROMDEVICE);
948}
949
950static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
951{
952 struct sk_buff *skb = re->skb;
953 int i;
954
955 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
956 PCI_DMA_FROMDEVICE);
957
958 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
959 pci_unmap_page(pdev, re->frag_addr[i],
960 skb_shinfo(skb)->frags[i].size,
961 PCI_DMA_FROMDEVICE);
962}
793b883e 963
cd28ab6a
SH		 964/* Tell chip where to start receive checksum.
965 * Actually has two checksums, but set both same to avoid possible byte
966 * order problems.
967 */
793b883e 968static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 969{
970 struct sky2_rx_le *le;
971
69161611
SH		 972 if (sky2->hw->chip_id != CHIP_ID_YUKON_EX) {
973 le = sky2_next_rx(sky2);
974 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
975 le->ctrl = 0;
976 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 977
69161611
SH		 978 sky2_write32(sky2->hw,
979 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
980 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
981 }
cd28ab6a
SH		 982
983}
984
6b1a3aef
SH		 985/*
986 * The RX Stop command will not work for Yukon-2 if the BMU does not
987 * reach the end of packet and since we can't make sure that we have
988 * incoming data, we must reset the BMU while it is not doing a DMA
989 * transfer. Since it is possible that the RX path is still active,
990 * the RX RAM buffer will be stopped first, so any possible incoming
991 * data will not trigger a DMA. After the RAM buffer is stopped, the
992 * BMU is polled until any DMA in progress is ended and only then it
993 * will be reset.
994 */
995static void sky2_rx_stop(struct sky2_port *sky2)
996{
997 struct sky2_hw *hw = sky2->hw;
998 unsigned rxq = rxqaddr[sky2->port];
999 int i;
1000
1001 /* disable the RAM Buffer receive queue */
1002 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1003
1004 for (i = 0; i < 0xffff; i++)
1005 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1006 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1007 goto stopped;
1008
1009 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1010 sky2->netdev->name);
1011stopped:
1012 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1013
1014 /* reset the Rx prefetch unit */
1015 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1016 mmiowb();
6b1a3aef 1017}
793b883e 1018
d571b694 1019/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1020static void sky2_rx_clean(struct sky2_port *sky2)
1021{
1022 unsigned i;
1023
1024 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1025 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1026 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1027
1028 if (re->skb) {
14d0263f 1029 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1030 kfree_skb(re->skb);
1031 re->skb = NULL;
1032 }
1033 }
1034}
1035
ef743d33
SH		 1036/* Basic MII support */
1037static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1038{
1039 struct mii_ioctl_data *data = if_mii(ifr);
1040 struct sky2_port *sky2 = netdev_priv(dev);
1041 struct sky2_hw *hw = sky2->hw;
1042 int err = -EOPNOTSUPP;
1043
1044 if (!netif_running(dev))
1045 return -ENODEV; /* Phy still in reset */
1046
d89e1343 1047 switch (cmd) {
ef743d33
SH		 1048 case SIOCGMIIPHY:
1049 data->phy_id = PHY_ADDR_MARV;
1050
1051 /* fallthru */
1052 case SIOCGMIIREG: {
1053 u16 val = 0;
91c86df5 1054
e07b1aa8 1055 spin_lock_bh(&sky2->phy_lock);
ef743d33 1056 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1057 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1058
ef743d33
SH		 1059 data->val_out = val;
1060 break;
1061 }
1062
1063 case SIOCSMIIREG:
1064 if (!capable(CAP_NET_ADMIN))
1065 return -EPERM;
1066
e07b1aa8 1067 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1068 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1069 data->val_in);
e07b1aa8 1070 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1071 break;
1072 }
1073 return err;
1074}
1075
d1f13708
SH		 1076#ifdef SKY2_VLAN_TAG_USED
1077static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1078{
1079 struct sky2_port *sky2 = netdev_priv(dev);
1080 struct sky2_hw *hw = sky2->hw;
1081 u16 port = sky2->port;
d1f13708 1082
2bb8c262 1083 netif_tx_lock_bh(dev);
3d4e66f5 1084 netif_poll_disable(sky2->hw->dev[0]);
d1f13708 1085
d1f13708 1086 sky2->vlgrp = grp;
3d4e66f5
SH		 1087 if (grp) {
1088 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1089 RX_VLAN_STRIP_ON);
1090 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1091 TX_VLAN_TAG_ON);
1092 } else {
1093 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1094 RX_VLAN_STRIP_OFF);
1095 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1096 TX_VLAN_TAG_OFF);
1097 }
d1f13708 1098
3d4e66f5 1099 netif_poll_enable(sky2->hw->dev[0]);
2bb8c262 1100 netif_tx_unlock_bh(dev);
d1f13708
SH		 1101}
1102#endif
1103
82788c7a 1104/*
14d0263f
SH		 1105 * Allocate an skb for receiving. If the MTU is large enough
1106 * make the skb non-linear with a fragment list of pages.
1107 *
82788c7a
SH		 1108 * It appears the hardware has a bug in the FIFO logic that
1109 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1110 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1111 * aligned except if slab debugging is enabled.
82788c7a 1112 */
14d0263f 1113static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1114{
1115 struct sk_buff *skb;
14d0263f
SH		 1116 unsigned long p;
1117 int i;
82788c7a 1118
14d0263f
SH		 1119 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1120 if (!skb)
1121 goto nomem;
1122
1123 p = (unsigned long) skb->data;
1124 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1125
1126 for (i = 0; i < sky2->rx_nfrags; i++) {
1127 struct page *page = alloc_page(GFP_ATOMIC);
1128
1129 if (!page)
1130 goto free_partial;
1131 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1132 }
1133
1134 return skb;
14d0263f
SH		 1135free_partial:
1136 kfree_skb(skb);
1137nomem:
1138 return NULL;
82788c7a
SH		 1139}
1140
55c9dd35
SH		 1141static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1142{
1143 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1144}
1145
cd28ab6a
SH		 1146/*
1147 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1148 * Normal case this ends up creating one list element for skb
1149 * in the receive ring. Worst case if using large MTU and each
1150 * allocation falls on a different 64 bit region, that results
1151 * in 6 list elements per ring entry.
1152 * One element is used for checksum enable/disable, and one
1153 * extra to avoid wrap.
cd28ab6a 1154 */
6b1a3aef 1155static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1156{
6b1a3aef 1157 struct sky2_hw *hw = sky2->hw;
14d0263f 1158 struct rx_ring_info *re;
6b1a3aef 1159 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1160 unsigned i, size, space, thresh;
cd28ab6a 1161
6b1a3aef 1162 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1163 sky2_qset(hw, rxq);
977bdf06 1164
c3905bc4
SH		 1165 /* On PCI express lowering the watermark gives better performance */
1166 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1167 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1168
1169 /* These chips have no ram buffer?
1170 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1171 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1172 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1173 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1174 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1175
6b1a3aef
SH		 1176 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1177
1178 rx_set_checksum(sky2);
14d0263f
SH		 1179
1180 /* Space needed for frame data + headers rounded up */
f957da2a 1181 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1182
1183 /* Stopping point for hardware truncation */
1184 thresh = (size - 8) / sizeof(u32);
1185
1186 /* Account for overhead of skb - to avoid order > 0 allocation */
1187 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1188 + sizeof(struct skb_shared_info);
1189
1190 sky2->rx_nfrags = space >> PAGE_SHIFT;
1191 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1192
1193 if (sky2->rx_nfrags != 0) {
1194 /* Compute residue after pages */
1195 space = sky2->rx_nfrags << PAGE_SHIFT;
1196
1197 if (space < size)
1198 size -= space;
1199 else
1200 size = 0;
1201
1202 /* Optimize to handle small packets and headers */
1203 if (size < copybreak)
1204 size = copybreak;
1205 if (size < ETH_HLEN)
1206 size = ETH_HLEN;
1207 }
1208 sky2->rx_data_size = size;
1209
1210 /* Fill Rx ring */
793b883e 1211 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1212 re = sky2->rx_ring + i;
cd28ab6a 1213
14d0263f 1214 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1215 if (!re->skb)
1216 goto nomem;
1217
14d0263f
SH		 1218 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1219 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1220 }
1221
a1433ac4
SH		 1222 /*
1223 * The receiver hangs if it receives frames larger than the
1224 * packet buffer. As a workaround, truncate oversize frames, but
1225 * the register is limited to 9 bits, so if you do frames > 2052
1226 * you better get the MTU right!
1227 */
a1433ac4
SH		 1228 if (thresh > 0x1ff)
1229 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1230 else {
1231 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1232 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1233 }
1234
6b1a3aef 1235 /* Tell chip about available buffers */
55c9dd35 1236 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1237 return 0;
1238nomem:
1239 sky2_rx_clean(sky2);
1240 return -ENOMEM;
1241}
1242
1243/* Bring up network interface. */
1244static int sky2_up(struct net_device *dev)
1245{
1246 struct sky2_port *sky2 = netdev_priv(dev);
1247 struct sky2_hw *hw = sky2->hw;
1248 unsigned port = sky2->port;
67712901 1249 u32 ramsize, imask;
ee7abb04 1250 int cap, err = -ENOMEM;
843a46f4 1251 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1252
ee7abb04
SH		 1253 /*
1254 * On dual port PCI-X card, there is an problem where status
1255 * can be received out of order due to split transactions
843a46f4 1256 */
ee7abb04
SH		 1257 if (otherdev && netif_running(otherdev) &&
1258 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1259 struct sky2_port *osky2 = netdev_priv(otherdev);
1260 u16 cmd;
1261
1262 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1263 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1264 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1265
1266 sky2->rx_csum = 0;
1267 osky2->rx_csum = 0;
1268 }
843a46f4 1269
cd28ab6a
SH		 1270 if (netif_msg_ifup(sky2))
1271 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1272
55d7b4e6
SH		 1273 netif_carrier_off(dev);
1274
cd28ab6a
SH		 1275 /* must be power of 2 */
1276 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1277 TX_RING_SIZE *
1278 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1279 &sky2->tx_le_map);
1280 if (!sky2->tx_le)
1281 goto err_out;
1282
6cdbbdf3 1283 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1284 GFP_KERNEL);
1285 if (!sky2->tx_ring)
1286 goto err_out;
1287 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1288
1289 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1290 &sky2->rx_le_map);
1291 if (!sky2->rx_le)
1292 goto err_out;
1293 memset(sky2->rx_le, 0, RX_LE_BYTES);
1294
291ea614 1295 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1296 GFP_KERNEL);
1297 if (!sky2->rx_ring)
1298 goto err_out;
1299
d3bcfbeb
SH		 1300 sky2_phy_power(hw, port, 1);
1301
cd28ab6a
SH		 1302 sky2_mac_init(hw, port);
1303
67712901
SH		 1304 /* Register is number of 4K blocks on internal RAM buffer. */
1305 ramsize = sky2_read8(hw, B2_E_0) * 4;
1306 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1307
67712901
SH		 1308 if (ramsize > 0) {
1309 u32 rxspace;
cd28ab6a 1310
67712901
SH		 1311 if (ramsize < 16)
1312 rxspace = ramsize / 2;
1313 else
1314 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1315
67712901
SH		 1316 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1317 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1318
1319 /* Make sure SyncQ is disabled */
1320 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1321 RB_RST_SET);
1322 }
793b883e 1323
af4ed7e6 1324 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1325
69161611
SH		 1326 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1327 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1328 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1329
977bdf06 1330 /* Set almost empty threshold */
c2716fb4
SH		 1331 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1332 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1333 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1334
6b1a3aef
SH		 1335 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1336 TX_RING_SIZE - 1);
cd28ab6a 1337
6b1a3aef 1338 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1339 if (err)
1340 goto err_out;
1341
cd28ab6a 1342 /* Enable interrupts from phy/mac for port */
e07b1aa8 1343 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1344 imask |= portirq_msk[port];
e07b1aa8
SH		 1345 sky2_write32(hw, B0_IMSK, imask);
1346
cd28ab6a
SH		 1347 return 0;
1348
1349err_out:
1b537565 1350 if (sky2->rx_le) {
cd28ab6a
SH		 1351 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1352 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1353 sky2->rx_le = NULL;
1354 }
1355 if (sky2->tx_le) {
cd28ab6a
SH		 1356 pci_free_consistent(hw->pdev,
1357 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1358 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1359 sky2->tx_le = NULL;
1360 }
1361 kfree(sky2->tx_ring);
1362 kfree(sky2->rx_ring);
cd28ab6a 1363
1b537565
SH		 1364 sky2->tx_ring = NULL;
1365 sky2->rx_ring = NULL;
cd28ab6a
SH		 1366 return err;
1367}
1368
793b883e
SH		 1369/* Modular subtraction in ring */
1370static inline int tx_dist(unsigned tail, unsigned head)
1371{
cb5d9547 1372 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1373}
cd28ab6a 1374
793b883e
SH		 1375/* Number of list elements available for next tx */
1376static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1377{
793b883e 1378 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1379}
1380
793b883e 1381/* Estimate of number of transmit list elements required */
28bd181a 1382static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1383{
793b883e
SH		 1384 unsigned count;
1385
1386 count = sizeof(dma_addr_t) / sizeof(u32);
1387 count += skb_shinfo(skb)->nr_frags * count;
1388
89114afd 1389 if (skb_is_gso(skb))
793b883e
SH		 1390 ++count;
1391
84fa7933 1392 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1393 ++count;
1394
1395 return count;
cd28ab6a
SH		 1396}
1397
793b883e
SH		 1398/*
1399 * Put one packet in ring for transmit.
1400 * A single packet can generate multiple list elements, and
1401 * the number of ring elements will probably be less than the number
1402 * of list elements used.
1403 */
cd28ab6a
SH		 1404static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1405{
1406 struct sky2_port *sky2 = netdev_priv(dev);
1407 struct sky2_hw *hw = sky2->hw;
d1f13708 1408 struct sky2_tx_le *le = NULL;
6cdbbdf3 1409 struct tx_ring_info *re;
cd28ab6a
SH		 1410 unsigned i, len;
1411 dma_addr_t mapping;
1412 u32 addr64;
1413 u16 mss;
1414 u8 ctrl;
1415
2bb8c262
SH		 1416 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1417 return NETDEV_TX_BUSY;
cd28ab6a 1418
793b883e 1419 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1420 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1421 dev->name, sky2->tx_prod, skb->len);
1422
cd28ab6a
SH		 1423 len = skb_headlen(skb);
1424 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
36eb0c71 1425 addr64 = upper_32_bits(mapping);
793b883e 1426
a018e330 1427 /* Send high bits if changed or crosses boundary */
36eb0c71
SH		 1428 if (addr64 != sky2->tx_addr64 ||
1429 upper_32_bits(mapping + len) != sky2->tx_addr64) {
793b883e 1430 le = get_tx_le(sky2);
f65b138c 1431 le->addr = cpu_to_le32(addr64);
793b883e 1432 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 1433 sky2->tx_addr64 = upper_32_bits(mapping + len);
793b883e 1434 }
cd28ab6a
SH		 1435
1436 /* Check for TCP Segmentation Offload */
7967168c 1437 mss = skb_shinfo(skb)->gso_size;
793b883e 1438 if (mss != 0) {
69161611
SH		 1439 if (hw->chip_id != CHIP_ID_YUKON_EX)
1440 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1441
1442 if (mss != sky2->tx_last_mss) {
1443 le = get_tx_le(sky2);
1444 le->addr = cpu_to_le32(mss);
1445 if (hw->chip_id == CHIP_ID_YUKON_EX)
1446 le->opcode = OP_MSS | HW_OWNER;
1447 else
1448 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1449 sky2->tx_last_mss = mss;
1450 }
cd28ab6a
SH		 1451 }
1452
cd28ab6a 1453 ctrl = 0;
d1f13708
SH		 1454#ifdef SKY2_VLAN_TAG_USED
1455 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1456 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1457 if (!le) {
1458 le = get_tx_le(sky2);
f65b138c 1459 le->addr = 0;
d1f13708 1460 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1461 } else
1462 le->opcode |= OP_VLAN;
1463 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1464 ctrl |= INS_VLAN;
1465 }
1466#endif
1467
1468 /* Handle TCP checksum offload */
84fa7933 1469 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611
SH		 1470 /* On Yukon EX (some versions) encoding change. */
1471 if (hw->chip_id == CHIP_ID_YUKON_EX
1472 && hw->chip_rev != CHIP_REV_YU_EX_B0)
1473 ctrl |= CALSUM; /* auto checksum */
1474 else {
1475 const unsigned offset = skb_transport_offset(skb);
1476 u32 tcpsum;
1477
1478 tcpsum = offset << 16; /* sum start */
1479 tcpsum |= offset + skb->csum_offset; /* sum write */
1480
1481 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1482 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1483 ctrl |= UDPTCP;
1484
1485 if (tcpsum != sky2->tx_tcpsum) {
1486 sky2->tx_tcpsum = tcpsum;
1487
1488 le = get_tx_le(sky2);
1489 le->addr = cpu_to_le32(tcpsum);
1490 le->length = 0; /* initial checksum value */
1491 le->ctrl = 1; /* one packet */
1492 le->opcode = OP_TCPLISW | HW_OWNER;
1493 }
1d179332 1494 }
cd28ab6a
SH		 1495 }
1496
1497 le = get_tx_le(sky2);
f65b138c 1498 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1499 le->length = cpu_to_le16(len);
1500 le->ctrl = ctrl;
793b883e 1501 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1502
291ea614 1503 re = tx_le_re(sky2, le);
cd28ab6a 1504 re->skb = skb;
6cdbbdf3 1505 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1506 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1507
1508 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1509 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1510
1511 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1512 frag->size, PCI_DMA_TODEVICE);
36eb0c71 1513 addr64 = upper_32_bits(mapping);
793b883e
SH		 1514 if (addr64 != sky2->tx_addr64) {
1515 le = get_tx_le(sky2);
f65b138c 1516 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1517 le->ctrl = 0;
1518 le->opcode = OP_ADDR64 | HW_OWNER;
1519 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1520 }
1521
1522 le = get_tx_le(sky2);
f65b138c 1523 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1524 le->length = cpu_to_le16(frag->size);
1525 le->ctrl = ctrl;
793b883e 1526 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1527
291ea614
SH		 1528 re = tx_le_re(sky2, le);
1529 re->skb = skb;
1530 pci_unmap_addr_set(re, mapaddr, mapping);
1531 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1532 }
6cdbbdf3 1533
cd28ab6a
SH		 1534 le->ctrl |= EOP;
1535
97bda706
SH		 1536 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1537 netif_stop_queue(dev);
b19666d9 1538
290d4de5 1539 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1540
cd28ab6a
SH		 1541 dev->trans_start = jiffies;
1542 return NETDEV_TX_OK;
1543}
1544
cd28ab6a 1545/*
793b883e
SH		 1546 * Free ring elements from starting at tx_cons until "done"
1547 *
1548 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1549 * buffers so make sure not to free skb to early.
cd28ab6a 1550 */
d11c13e7 1551static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1552{
d11c13e7 1553 struct net_device *dev = sky2->netdev;
af2a58ac 1554 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1555 unsigned idx;
cd28ab6a 1556
0e3ff6aa 1557 BUG_ON(done >= TX_RING_SIZE);
2224795d 1558
291ea614
SH		 1559 for (idx = sky2->tx_cons; idx != done;
1560 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1561 struct sky2_tx_le *le = sky2->tx_le + idx;
1562 struct tx_ring_info *re = sky2->tx_ring + idx;
1563
1564 switch(le->opcode & ~HW_OWNER) {
1565 case OP_LARGESEND:
1566 case OP_PACKET:
1567 pci_unmap_single(pdev,
1568 pci_unmap_addr(re, mapaddr),
1569 pci_unmap_len(re, maplen),
1570 PCI_DMA_TODEVICE);
af2a58ac 1571 break;
291ea614
SH		 1572 case OP_BUFFER:
1573 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1574 pci_unmap_len(re, maplen),
734d1868 1575 PCI_DMA_TODEVICE);
291ea614
SH		 1576 break;
1577 }
1578
1579 if (le->ctrl & EOP) {
1580 if (unlikely(netif_msg_tx_done(sky2)))
1581 printk(KERN_DEBUG "%s: tx done %u\n",
1582 dev->name, idx);
3cf26753 1583
2bf56fe2 1584 sky2->net_stats.tx_packets++;
1585 sky2->net_stats.tx_bytes += re->skb->len;
1586
794b2bd2 1587 dev_kfree_skb_any(re->skb);
3cf26753 1588 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1589 }
793b883e 1590 }
793b883e 1591
291ea614 1592 sky2->tx_cons = idx;
50432cb5
SH		 1593 smp_mb();
1594
22e11703 1595 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1596 netif_wake_queue(dev);
cd28ab6a
SH		 1597}
1598
1599/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1600static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1601{
2bb8c262
SH		 1602 struct sky2_port *sky2 = netdev_priv(dev);
1603
1604 netif_tx_lock_bh(dev);
d11c13e7 1605 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1606 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1607}
1608
1609/* Network shutdown */
1610static int sky2_down(struct net_device *dev)
1611{
1612 struct sky2_port *sky2 = netdev_priv(dev);
1613 struct sky2_hw *hw = sky2->hw;
1614 unsigned port = sky2->port;
1615 u16 ctrl;
e07b1aa8 1616 u32 imask;
cd28ab6a 1617
1b537565
SH		 1618 /* Never really got started! */
1619 if (!sky2->tx_le)
1620 return 0;
1621
cd28ab6a
SH		 1622 if (netif_msg_ifdown(sky2))
1623 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1624
32c2c300
SH		 1625 if (netif_carrier_ok(dev) && --hw->active == 0)
1626 del_timer(&hw->watchdog_timer);
1627
018d1c66 1628 /* Stop more packets from being queued */
cd28ab6a
SH		 1629 netif_stop_queue(dev);
1630
ebc646f6
SH		 1631 /* Disable port IRQ */
1632 imask = sky2_read32(hw, B0_IMSK);
1633 imask &= ~portirq_msk[port];
1634 sky2_write32(hw, B0_IMSK, imask);
1635
d3bcfbeb 1636 sky2_gmac_reset(hw, port);
793b883e 1637
cd28ab6a
SH		 1638 /* Stop transmitter */
1639 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1640 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1641
1642 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1643 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1644
1645 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1646 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1647 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1648
1649 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1650
1651 /* Workaround shared GMAC reset */
793b883e
SH		 1652 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1653 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1654 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1655
1656 /* Disable Force Sync bit and Enable Alloc bit */
1657 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1658 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1659
1660 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1661 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1662 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1663
1664 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1665 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1666 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1667
1668 /* Reset the Tx prefetch units */
1669 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1670 PREF_UNIT_RST_SET);
1671
1672 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1673
6b1a3aef 1674 sky2_rx_stop(sky2);
cd28ab6a
SH		 1675
1676 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1677 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1678
d3bcfbeb
SH		 1679 sky2_phy_power(hw, port, 0);
1680
55d7b4e6
SH		 1681 netif_carrier_off(dev);
1682
d571b694 1683 /* turn off LED's */
cd28ab6a
SH		 1684 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1685
018d1c66
SH		 1686 synchronize_irq(hw->pdev->irq);
1687
2bb8c262 1688 sky2_tx_clean(dev);
cd28ab6a
SH		 1689 sky2_rx_clean(sky2);
1690
1691 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1692 sky2->rx_le, sky2->rx_le_map);
1693 kfree(sky2->rx_ring);
1694
1695 pci_free_consistent(hw->pdev,
1696 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1697 sky2->tx_le, sky2->tx_le_map);
1698 kfree(sky2->tx_ring);
1699
1b537565
SH		 1700 sky2->tx_le = NULL;
1701 sky2->rx_le = NULL;
1702
1703 sky2->rx_ring = NULL;
1704 sky2->tx_ring = NULL;
1705
cd28ab6a
SH		 1706 return 0;
1707}
1708
1709static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1710{
b89165f2 1711 if (!sky2_is_copper(hw))
793b883e
SH		 1712 return SPEED_1000;
1713
cd28ab6a
SH		 1714 if (hw->chip_id == CHIP_ID_YUKON_FE)
1715 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1716
1717 switch (aux & PHY_M_PS_SPEED_MSK) {
1718 case PHY_M_PS_SPEED_1000:
1719 return SPEED_1000;
1720 case PHY_M_PS_SPEED_100:
1721 return SPEED_100;
1722 default:
1723 return SPEED_10;
1724 }
1725}
1726
1727static void sky2_link_up(struct sky2_port *sky2)
1728{
1729 struct sky2_hw *hw = sky2->hw;
1730 unsigned port = sky2->port;
1731 u16 reg;
16ad91e1
SH		 1732 static const char *fc_name[] = {
1733 [FC_NONE] = "none",
1734 [FC_TX] = "tx",
1735 [FC_RX] = "rx",
1736 [FC_BOTH] = "both",
1737 };
cd28ab6a 1738
cd28ab6a 1739 /* enable Rx/Tx */
2eaba1a2 1740 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1741 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1742 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1743
1744 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1745
1746 netif_carrier_on(sky2->netdev);
cd28ab6a 1747
32c2c300
SH		 1748 if (hw->active++ == 0)
1749 mod_timer(&hw->watchdog_timer, jiffies + 1);
1750
1751
cd28ab6a 1752 /* Turn on link LED */
793b883e 1753 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1754 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1755
93745494
SH		 1756 if (hw->chip_id == CHIP_ID_YUKON_XL
1757 || hw->chip_id == CHIP_ID_YUKON_EC_U
1758 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1759 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1760 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1761
1762 switch(sky2->speed) {
1763 case SPEED_10:
1764 led |= PHY_M_LEDC_INIT_CTRL(7);
1765 break;
1766
1767 case SPEED_100:
1768 led |= PHY_M_LEDC_STA1_CTRL(7);
1769 break;
1770
1771 case SPEED_1000:
1772 led |= PHY_M_LEDC_STA0_CTRL(7);
1773 break;
1774 }
793b883e
SH		 1775
1776 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1777 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1778 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1779 }
1780
cd28ab6a
SH		 1781 if (netif_msg_link(sky2))
1782 printk(KERN_INFO PFX
d571b694 1783 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1784 sky2->netdev->name, sky2->speed,
1785 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1786 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1787}
1788
1789static void sky2_link_down(struct sky2_port *sky2)
1790{
1791 struct sky2_hw *hw = sky2->hw;
1792 unsigned port = sky2->port;
1793 u16 reg;
1794
1795 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1796
1797 reg = gma_read16(hw, port, GM_GP_CTRL);
1798 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1799 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1800
cd28ab6a 1801 netif_carrier_off(sky2->netdev);
cd28ab6a 1802
32c2c300
SH		 1803 /* Stop watchdog if both ports are not active */
1804 if (--hw->active == 0)
1805 del_timer(&hw->watchdog_timer);
1806
1807
cd28ab6a
SH		 1808 /* Turn on link LED */
1809 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1810
1811 if (netif_msg_link(sky2))
1812 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1813
cd28ab6a
SH		 1814 sky2_phy_init(hw, port);
1815}
1816
16ad91e1
SH		 1817static enum flow_control sky2_flow(int rx, int tx)
1818{
1819 if (rx)
1820 return tx ? FC_BOTH : FC_RX;
1821 else
1822 return tx ? FC_TX : FC_NONE;
1823}
1824
793b883e
SH		 1825static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1826{
1827 struct sky2_hw *hw = sky2->hw;
1828 unsigned port = sky2->port;
da4c1ff4 1829 u16 advert, lpa;
793b883e 1830
da4c1ff4 1831 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1832 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1833 if (lpa & PHY_M_AN_RF) {
1834 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1835 return -1;
1836 }
1837
793b883e
SH		 1838 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1839 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1840 sky2->netdev->name);
1841 return -1;
1842 }
1843
793b883e 1844 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1845 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1846
da4c1ff4
SH		 1847 /* Since the pause result bits seem to in different positions on
1848 * different chips. look at registers.
1849 */
1850 if (!sky2_is_copper(hw)) {
1851 /* Shift for bits in fiber PHY */
1852 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1853 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1854
1855 if (advert & ADVERTISE_1000XPAUSE)
1856 advert |= ADVERTISE_PAUSE_CAP;
1857 if (advert & ADVERTISE_1000XPSE_ASYM)
1858 advert |= ADVERTISE_PAUSE_ASYM;
1859 if (lpa & LPA_1000XPAUSE)
1860 lpa |= LPA_PAUSE_CAP;
1861 if (lpa & LPA_1000XPAUSE_ASYM)
1862 lpa |= LPA_PAUSE_ASYM;
1863 }
793b883e 1864
da4c1ff4
SH		 1865 sky2->flow_status = FC_NONE;
1866 if (advert & ADVERTISE_PAUSE_CAP) {
1867 if (lpa & LPA_PAUSE_CAP)
1868 sky2->flow_status = FC_BOTH;
1869 else if (advert & ADVERTISE_PAUSE_ASYM)
1870 sky2->flow_status = FC_RX;
1871 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1872 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1873 sky2->flow_status = FC_TX;
1874 }
793b883e 1875
16ad91e1 1876 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1877 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1878 sky2->flow_status = FC_NONE;
2eaba1a2 1879
da4c1ff4 1880 if (sky2->flow_status & FC_TX)
793b883e
SH		 1881 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1882 else
1883 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1884
1885 return 0;
1886}
cd28ab6a 1887
e07b1aa8
SH		 1888/* Interrupt from PHY */
1889static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1890{
e07b1aa8
SH		 1891 struct net_device *dev = hw->dev[port];
1892 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1893 u16 istatus, phystat;
1894
ebc646f6
SH		 1895 if (!netif_running(dev))
1896 return;
1897
e07b1aa8
SH		 1898 spin_lock(&sky2->phy_lock);
1899 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1900 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1901
cd28ab6a
SH		 1902 if (netif_msg_intr(sky2))
1903 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1904 sky2->netdev->name, istatus, phystat);
1905
2eaba1a2 1906 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1907 if (sky2_autoneg_done(sky2, phystat) == 0)
1908 sky2_link_up(sky2);
1909 goto out;
1910 }
cd28ab6a 1911
793b883e
SH		 1912 if (istatus & PHY_M_IS_LSP_CHANGE)
1913 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1914
793b883e
SH		 1915 if (istatus & PHY_M_IS_DUP_CHANGE)
1916 sky2->duplex =
1917 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1918
793b883e
SH		 1919 if (istatus & PHY_M_IS_LST_CHANGE) {
1920 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1921 sky2_link_up(sky2);
793b883e
SH		 1922 else
1923 sky2_link_down(sky2);
cd28ab6a 1924 }
793b883e 1925out:
e07b1aa8 1926 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1927}
1928
62335ab0 1929/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1930 * and tx queue is full (stopped).
1931 */
cd28ab6a
SH		 1932static void sky2_tx_timeout(struct net_device *dev)
1933{
1934 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1935 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1936
1937 if (netif_msg_timer(sky2))
1938 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1939
8f24664d 1940 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1941 dev->name, sky2->tx_cons, sky2->tx_prod,
1942 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1943 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1944
81906791
SH		 1945 /* can't restart safely under softirq */
1946 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1947}
1948
1949static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1950{
6b1a3aef
SH		 1951 struct sky2_port *sky2 = netdev_priv(dev);
1952 struct sky2_hw *hw = sky2->hw;
b628ed98 1953 unsigned port = sky2->port;
6b1a3aef
SH		 1954 int err;
1955 u16 ctl, mode;
e07b1aa8 1956 u32 imask;
cd28ab6a
SH		 1957
1958 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1959 return -EINVAL;
1960
d2adf4f6
SH		 1961 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1962 return -EINVAL;
1963
6b1a3aef
SH		 1964 if (!netif_running(dev)) {
1965 dev->mtu = new_mtu;
1966 return 0;
1967 }
1968
e07b1aa8 1969 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1970 sky2_write32(hw, B0_IMSK, 0);
1971
018d1c66
SH		 1972 dev->trans_start = jiffies; /* prevent tx timeout */
1973 netif_stop_queue(dev);
1974 netif_poll_disable(hw->dev[0]);
1975
e07b1aa8
SH		 1976 synchronize_irq(hw->pdev->irq);
1977
69161611
SH		 1978 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
1979 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 1980
1981 ctl = gma_read16(hw, port, GM_GP_CTRL);
1982 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 1983 sky2_rx_stop(sky2);
1984 sky2_rx_clean(sky2);
cd28ab6a
SH		 1985
1986 dev->mtu = new_mtu;
14d0263f 1987
6b1a3aef
SH		 1988 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1989 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1990
1991 if (dev->mtu > ETH_DATA_LEN)
1992 mode |= GM_SMOD_JUMBO_ENA;
1993
b628ed98 1994 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 1995
b628ed98 1996 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1997
6b1a3aef 1998 err = sky2_rx_start(sky2);
e07b1aa8 1999 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2000
1b537565
SH		 2001 if (err)
2002 dev_close(dev);
2003 else {
b628ed98 2004 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 2005
2006 netif_poll_enable(hw->dev[0]);
2007 netif_wake_queue(dev);
2008 }
2009
cd28ab6a
SH		 2010 return err;
2011}
2012
14d0263f
SH		 2013/* For small just reuse existing skb for next receive */
2014static struct sk_buff *receive_copy(struct sky2_port *sky2,
2015 const struct rx_ring_info *re,
2016 unsigned length)
2017{
2018 struct sk_buff *skb;
2019
2020 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2021 if (likely(skb)) {
2022 skb_reserve(skb, 2);
2023 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2024 length, PCI_DMA_FROMDEVICE);
d626f62b 2025 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2026 skb->ip_summed = re->skb->ip_summed;
2027 skb->csum = re->skb->csum;
2028 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2029 length, PCI_DMA_FROMDEVICE);
2030 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2031 skb_put(skb, length);
14d0263f
SH		 2032 }
2033 return skb;
2034}
2035
2036/* Adjust length of skb with fragments to match received data */
2037static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2038 unsigned int length)
2039{
2040 int i, num_frags;
2041 unsigned int size;
2042
2043 /* put header into skb */
2044 size = min(length, hdr_space);
2045 skb->tail += size;
2046 skb->len += size;
2047 length -= size;
2048
2049 num_frags = skb_shinfo(skb)->nr_frags;
2050 for (i = 0; i < num_frags; i++) {
2051 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2052
2053 if (length == 0) {
2054 /* don't need this page */
2055 __free_page(frag->page);
2056 --skb_shinfo(skb)->nr_frags;
2057 } else {
2058 size = min(length, (unsigned) PAGE_SIZE);
2059
2060 frag->size = size;
2061 skb->data_len += size;
2062 skb->truesize += size;
2063 skb->len += size;
2064 length -= size;
2065 }
2066 }
2067}
2068
2069/* Normal packet - take skb from ring element and put in a new one */
2070static struct sk_buff *receive_new(struct sky2_port *sky2,
2071 struct rx_ring_info *re,
2072 unsigned int length)
2073{
2074 struct sk_buff *skb, *nskb;
2075 unsigned hdr_space = sky2->rx_data_size;
2076
14d0263f
SH		 2077 /* Don't be tricky about reusing pages (yet) */
2078 nskb = sky2_rx_alloc(sky2);
2079 if (unlikely(!nskb))
2080 return NULL;
2081
2082 skb = re->skb;
2083 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2084
2085 prefetch(skb->data);
2086 re->skb = nskb;
2087 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2088
2089 if (skb_shinfo(skb)->nr_frags)
2090 skb_put_frags(skb, hdr_space, length);
2091 else
489b10c1 2092 skb_put(skb, length);
14d0263f
SH		 2093 return skb;
2094}
2095
cd28ab6a
SH		 2096/*
2097 * Receive one packet.
d571b694 2098 * For larger packets, get new buffer.
cd28ab6a 2099 */
497d7c86 2100static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2101 u16 length, u32 status)
2102{
497d7c86 2103 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2104 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2105 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2106
2107 if (unlikely(netif_msg_rx_status(sky2)))
2108 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2109 dev->name, sky2->rx_next, status, length);
cd28ab6a 2110
793b883e 2111 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2112 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2113
42eeea01 2114 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2115 goto error;
2116
42eeea01
SH		 2117 if (!(status & GMR_FS_RX_OK))
2118 goto resubmit;
2119
71749531
SH		 2120 if (status >> 16 != length)
2121 goto len_mismatch;
2122
14d0263f
SH		 2123 if (length < copybreak)
2124 skb = receive_copy(sky2, re, length);
2125 else
2126 skb = receive_new(sky2, re, length);
793b883e 2127resubmit:
14d0263f 2128 sky2_rx_submit(sky2, re);
79e57d32 2129
cd28ab6a
SH		 2130 return skb;
2131
71749531
SH		 2132len_mismatch:
2133 /* Truncation of overlength packets
2134 causes PHY length to not match MAC length */
2135 ++sky2->net_stats.rx_length_errors;
2136
cd28ab6a 2137error:
6e15b712 2138 ++sky2->net_stats.rx_errors;
b6d77734 2139 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2140 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2141 goto resubmit;
2142 }
6e15b712 2143
3be92a70 2144 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2145 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2146 dev->name, status, length);
793b883e
SH		 2147
2148 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2149 sky2->net_stats.rx_length_errors++;
2150 if (status & GMR_FS_FRAGMENT)
2151 sky2->net_stats.rx_frame_errors++;
2152 if (status & GMR_FS_CRC_ERR)
2153 sky2->net_stats.rx_crc_errors++;
79e57d32 2154
793b883e 2155 goto resubmit;
cd28ab6a
SH		 2156}
2157
e07b1aa8
SH		 2158/* Transmit complete */
2159static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2160{
e07b1aa8 2161 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2162
e07b1aa8 2163 if (netif_running(dev)) {
2bb8c262 2164 netif_tx_lock(dev);
e07b1aa8 2165 sky2_tx_complete(sky2, last);
2bb8c262 2166 netif_tx_unlock(dev);
2224795d 2167 }
cd28ab6a
SH		 2168}
2169
e07b1aa8
SH		 2170/* Process status response ring */
2171static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2172{
e07b1aa8 2173 int work_done = 0;
55c9dd35 2174 unsigned rx[2] = { 0, 0 };
e71ebd73 2175 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2176
af2a58ac 2177 rmb();
bea86103 2178
e71ebd73 2179 while (hw->st_idx != hwidx) {
55c9dd35 2180 struct sky2_port *sky2;
13210ce5 2181 struct sky2_status_le *le = hw->st_le + hw->st_idx;
69161611 2182 unsigned port = le->css & CSS_LINK_BIT;
13210ce5 2183 struct net_device *dev;
cd28ab6a 2184 struct sk_buff *skb;
cd28ab6a
SH		 2185 u32 status;
2186 u16 length;
2187
cb5d9547 2188 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2189
69161611 2190 dev = hw->dev[port];
13210ce5 2191 sky2 = netdev_priv(dev);
f65b138c
SH		 2192 length = le16_to_cpu(le->length);
2193 status = le32_to_cpu(le->status);
cd28ab6a 2194
e71ebd73 2195 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2196 case OP_RXSTAT:
55c9dd35 2197 ++rx[port];
497d7c86 2198 skb = sky2_receive(dev, length, status);
3225b919
SH		 2199 if (unlikely(!skb)) {
2200 sky2->net_stats.rx_dropped++;
55c9dd35 2201 break;
3225b919 2202 }
13210ce5 2203
69161611
SH		 2204 /* This chip reports checksum status differently */
2205 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2206 if (sky2->rx_csum &&
2207 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2208 (le->css & CSS_TCPUDPCSOK))
2209 skb->ip_summed = CHECKSUM_UNNECESSARY;
2210 else
2211 skb->ip_summed = CHECKSUM_NONE;
2212 }
2213
13210ce5 2214 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2215 sky2->net_stats.rx_packets++;
2216 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2217 dev->last_rx = jiffies;
2218
d1f13708
SH		 2219#ifdef SKY2_VLAN_TAG_USED
2220 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2221 vlan_hwaccel_receive_skb(skb,
2222 sky2->vlgrp,
2223 be16_to_cpu(sky2->rx_tag));
2224 } else
2225#endif
cd28ab6a 2226 netif_receive_skb(skb);
13210ce5 2227
22e11703 2228 /* Stop after net poll weight */
13210ce5
SH		 2229 if (++work_done >= to_do)
2230 goto exit_loop;
cd28ab6a
SH		 2231 break;
2232
d1f13708
SH		 2233#ifdef SKY2_VLAN_TAG_USED
2234 case OP_RXVLAN:
2235 sky2->rx_tag = length;
2236 break;
2237
2238 case OP_RXCHKSVLAN:
2239 sky2->rx_tag = length;
2240 /* fall through */
2241#endif
cd28ab6a 2242 case OP_RXCHKS:
87418307
SH		 2243 if (!sky2->rx_csum)
2244 break;
2245
69161611
SH		 2246 if (hw->chip_id == CHIP_ID_YUKON_EX)
2247 break;
2248
87418307
SH		 2249 /* Both checksum counters are programmed to start at
2250 * the same offset, so unless there is a problem they
2251 * should match. This failure is an early indication that
2252 * hardware receive checksumming won't work.
2253 */
2254 if (likely(status >> 16 == (status & 0xffff))) {
2255 skb = sky2->rx_ring[sky2->rx_next].skb;
2256 skb->ip_summed = CHECKSUM_COMPLETE;
2257 skb->csum = status & 0xffff;
2258 } else {
2259 printk(KERN_NOTICE PFX "%s: hardware receive "
2260 "checksum problem (status = %#x)\n",
2261 dev->name, status);
2262 sky2->rx_csum = 0;
2263 sky2_write32(sky2->hw,
69161611 2264 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2265 BMU_DIS_RX_CHKSUM);
2266 }
cd28ab6a
SH		 2267 break;
2268
2269 case OP_TXINDEXLE:
13b97b74 2270 /* TX index reports status for both ports */
f55925d7
SH		 2271 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2272 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2273 if (hw->dev[1])
2274 sky2_tx_done(hw->dev[1],
2275 ((status >> 24) & 0xff)
2276 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2277 break;
2278
cd28ab6a
SH		 2279 default:
2280 if (net_ratelimit())
793b883e 2281 printk(KERN_WARNING PFX
e71ebd73 2282 "unknown status opcode 0x%x\n", le->opcode);
cd28ab6a 2283 }
13210ce5 2284 }
cd28ab6a 2285
fe2a24df
SH		 2286 /* Fully processed status ring so clear irq */
2287 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2288
13210ce5 2289exit_loop:
55c9dd35
SH		 2290 if (rx[0])
2291 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2292
55c9dd35
SH		 2293 if (rx[1])
2294 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2295
e07b1aa8 2296 return work_done;
cd28ab6a
SH		 2297}
2298
2299static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2300{
2301 struct net_device *dev = hw->dev[port];
2302
3be92a70
SH		 2303 if (net_ratelimit())
2304 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2305 dev->name, status);
cd28ab6a
SH		 2306
2307 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2308 if (net_ratelimit())
2309 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2310 dev->name);
cd28ab6a
SH		 2311 /* Clear IRQ */
2312 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2313 }
2314
2315 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2316 if (net_ratelimit())
2317 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2318 dev->name);
cd28ab6a
SH		 2319
2320 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2321 }
2322
2323 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2324 if (net_ratelimit())
2325 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2326 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2327 }
2328
2329 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2330 if (net_ratelimit())
2331 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2332 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2333 }
2334
2335 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2336 if (net_ratelimit())
2337 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2338 dev->name);
cd28ab6a
SH		 2339 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2340 }
2341}
2342
2343static void sky2_hw_intr(struct sky2_hw *hw)
2344{
2345 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2346
793b883e 2347 if (status & Y2_IS_TIST_OV)
cd28ab6a 2348 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2349
2350 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2351 u16 pci_err;
2352
56a645cc 2353 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2354 if (net_ratelimit())
b02a9258
SH		 2355 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2356 pci_err);
cd28ab6a
SH		 2357
2358 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2359 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2360 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2361 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2362 }
2363
2364 if (status & Y2_IS_PCI_EXP) {
d571b694 2365 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2366 u32 pex_err;
2367
7bd656d1 2368 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2369
3be92a70 2370 if (net_ratelimit())
b02a9258
SH		 2371 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2372 pex_err);
cd28ab6a
SH		 2373
2374 /* clear the interrupt */
2375 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2376 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2377 0xffffffffUL);
cd28ab6a
SH		 2378 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2379
7bd656d1 2380 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2381 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2382 hwmsk &= ~Y2_IS_PCI_EXP;
2383 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2384 }
2385 }
2386
2387 if (status & Y2_HWE_L1_MASK)
2388 sky2_hw_error(hw, 0, status);
2389 status >>= 8;
2390 if (status & Y2_HWE_L1_MASK)
2391 sky2_hw_error(hw, 1, status);
2392}
2393
2394static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2395{
2396 struct net_device *dev = hw->dev[port];
2397 struct sky2_port *sky2 = netdev_priv(dev);
2398 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2399
2400 if (netif_msg_intr(sky2))
2401 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2402 dev->name, status);
2403
a3caeada
SH		 2404 if (status & GM_IS_RX_CO_OV)
2405 gma_read16(hw, port, GM_RX_IRQ_SRC);
2406
2407 if (status & GM_IS_TX_CO_OV)
2408 gma_read16(hw, port, GM_TX_IRQ_SRC);
2409
cd28ab6a
SH		 2410 if (status & GM_IS_RX_FF_OR) {
2411 ++sky2->net_stats.rx_fifo_errors;
2412 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2413 }
2414
2415 if (status & GM_IS_TX_FF_UR) {
2416 ++sky2->net_stats.tx_fifo_errors;
2417 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2418 }
cd28ab6a
SH		 2419}
2420
40b01727
SH		 2421/* This should never happen it is a bug. */
2422static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2423 u16 q, unsigned ring_size)
d257924e
SH		 2424{
2425 struct net_device *dev = hw->dev[port];
2426 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2427 unsigned idx;
2428 const u64 *le = (q == Q_R1 || q == Q_R2)
2429 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2430
40b01727
SH		 2431 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2432 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2433 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2434 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2435
40b01727 2436 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2437}
cd28ab6a 2438
32c2c300
SH		 2439/* Check for lost IRQ once a second */
2440static void sky2_watchdog(unsigned long arg)
d27ed387 2441{
01bd7564 2442 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2443
32c2c300
SH		 2444 if (sky2_read32(hw, B0_ISRC)) {
2445 struct net_device *dev = hw->dev[0];
2446
2447 if (__netif_rx_schedule_prep(dev))
2448 __netif_rx_schedule(dev);
2449 }
01bd7564 2450
32c2c300
SH		 2451 if (hw->active > 0)
2452 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2453}
2454
40b01727
SH		 2455/* Hardware/software error handling */
2456static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2457{
40b01727
SH		 2458 if (net_ratelimit())
2459 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2460
1e5f1283
SH		 2461 if (status & Y2_IS_HW_ERR)
2462 sky2_hw_intr(hw);
d257924e 2463
1e5f1283
SH		 2464 if (status & Y2_IS_IRQ_MAC1)
2465 sky2_mac_intr(hw, 0);
cd28ab6a 2466
1e5f1283
SH		 2467 if (status & Y2_IS_IRQ_MAC2)
2468 sky2_mac_intr(hw, 1);
cd28ab6a 2469
1e5f1283 2470 if (status & Y2_IS_CHK_RX1)
40b01727 2471 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2472
1e5f1283 2473 if (status & Y2_IS_CHK_RX2)
40b01727 2474 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2475
1e5f1283 2476 if (status & Y2_IS_CHK_TXA1)
40b01727 2477 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2478
1e5f1283 2479 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2480 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2481}
2482
2483static int sky2_poll(struct net_device *dev0, int *budget)
2484{
2485 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
5c11ce70 2486 int work_done;
40b01727
SH		 2487 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2488
2489 if (unlikely(status & Y2_IS_ERROR))
2490 sky2_err_intr(hw, status);
2491
2492 if (status & Y2_IS_IRQ_PHY1)
2493 sky2_phy_intr(hw, 0);
2494
2495 if (status & Y2_IS_IRQ_PHY2)
2496 sky2_phy_intr(hw, 1);
cd28ab6a 2497
5c11ce70
SH		 2498 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2499 *budget -= work_done;
2500 dev0->quota -= work_done;
86fba634 2501
5c11ce70
SH		 2502 /* More work? */
2503 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
1e5f1283 2504 return 1;
5c11ce70
SH		 2505
2506 /* Bug/Errata workaround?
2507 * Need to kick the TX irq moderation timer.
2508 */
2509 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2510 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2511 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2512 }
5c11ce70
SH		 2513 netif_rx_complete(dev0);
2514
2515 sky2_read32(hw, B0_Y2_SP_LISR);
2516 return 0;
e07b1aa8
SH		 2517}
2518
7d12e780 2519static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2520{
2521 struct sky2_hw *hw = dev_id;
2522 struct net_device *dev0 = hw->dev[0];
2523 u32 status;
2524
2525 /* Reading this mask interrupts as side effect */
2526 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2527 if (status == 0 || status == ~0)
2528 return IRQ_NONE;
793b883e 2529
e07b1aa8
SH		 2530 prefetch(&hw->st_le[hw->st_idx]);
2531 if (likely(__netif_rx_schedule_prep(dev0)))
2532 __netif_rx_schedule(dev0);
793b883e 2533
cd28ab6a
SH		 2534 return IRQ_HANDLED;
2535}
2536
2537#ifdef CONFIG_NET_POLL_CONTROLLER
2538static void sky2_netpoll(struct net_device *dev)
2539{
2540 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2541 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2542
88d11360
SH		 2543 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2544 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2545}
2546#endif
2547
2548/* Chip internal frequency for clock calculations */
fb17358f 2549static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2550{
793b883e 2551 switch (hw->chip_id) {
cd28ab6a 2552 case CHIP_ID_YUKON_EC:
5a5b1ea0 2553 case CHIP_ID_YUKON_EC_U:
93745494 2554 case CHIP_ID_YUKON_EX:
fb17358f 2555 return 125; /* 125 Mhz */
cd28ab6a 2556 case CHIP_ID_YUKON_FE:
fb17358f 2557 return 100; /* 100 Mhz */
793b883e 2558 default: /* YUKON_XL */
fb17358f 2559 return 156; /* 156 Mhz */
cd28ab6a
SH		 2560 }
2561}
2562
fb17358f 2563static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2564{
fb17358f 2565 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2566}
2567
fb17358f 2568static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2569{
fb17358f 2570 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2571}
2572
fb17358f 2573
e3173832 2574static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2575{
b89165f2 2576 u8 t8;
cd28ab6a 2577
451af335
SH		 2578 /* Enable all clocks */
2579 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2580
cd28ab6a 2581 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2582
cd28ab6a
SH		 2583 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2584 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2585 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2586 hw->chip_id);
cd28ab6a
SH		 2587 return -EOPNOTSUPP;
2588 }
2589
290d4de5
SH		 2590 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2591
2592 /* This rev is really old, and requires untested workarounds */
2593 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2594 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2595 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2596 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2597 return -EOPNOTSUPP;
2598 }
2599
e3173832
SH		 2600 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2601 hw->ports = 1;
2602 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2603 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2604 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2605 ++hw->ports;
2606 }
2607
2608 return 0;
2609}
2610
2611static void sky2_reset(struct sky2_hw *hw)
2612{
2613 u16 status;
2614 int i;
2615
cd28ab6a 2616 /* disable ASF */
4f44d8ba
SH		 2617 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2618 status = sky2_read16(hw, HCU_CCSR);
2619 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2620 HCU_CCSR_UC_STATE_MSK);
2621 sky2_write16(hw, HCU_CCSR, status);
2622 } else
2623 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2624 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2625
2626 /* do a SW reset */
2627 sky2_write8(hw, B0_CTST, CS_RST_SET);
2628 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2629
2630 /* clear PCI errors, if any */
56a645cc 2631 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2632
cd28ab6a 2633 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2634 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2635
cd28ab6a
SH		 2636
2637 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2638
2639 /* clear any PEX errors */
7bd656d1
SH		 2640 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2641 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2642
cd28ab6a 2643
ae306cca 2644 sky2_power_on(hw);
cd28ab6a
SH		 2645
2646 for (i = 0; i < hw->ports; i++) {
2647 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2648 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2649
2650 if (hw->chip_id == CHIP_ID_YUKON_EX)
2651 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2652 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2653 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2654 }
2655
2656 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2657
793b883e
SH		 2658 /* Clear I2C IRQ noise */
2659 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2660
2661 /* turn off hardware timer (unused) */
2662 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2663 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2664
cd28ab6a
SH		 2665 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2666
69634ee7
SH		 2667 /* Turn off descriptor polling */
2668 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2669
2670 /* Turn off receive timestamp */
2671 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2672 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2673
2674 /* enable the Tx Arbiters */
2675 for (i = 0; i < hw->ports; i++)
2676 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2677
2678 /* Initialize ram interface */
2679 for (i = 0; i < hw->ports; i++) {
793b883e 2680 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2681
2682 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2683 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2684 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2685 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2686 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2687 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2688 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2689 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2690 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2691 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2692 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2693 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2694 }
2695
7bd656d1 2696 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2697
cd28ab6a 2698 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2699 sky2_gmac_reset(hw, i);
cd28ab6a 2700
cd28ab6a
SH		 2701 memset(hw->st_le, 0, STATUS_LE_BYTES);
2702 hw->st_idx = 0;
2703
2704 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2705 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2706
2707 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2708 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2709
2710 /* Set the list last index */
793b883e 2711 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2712
290d4de5
SH		 2713 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2714 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2715
290d4de5
SH		 2716 /* set Status-FIFO ISR watermark */
2717 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2718 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2719 else
2720 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2721
290d4de5 2722 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2723 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2724 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2725
793b883e 2726 /* enable status unit */
cd28ab6a
SH		 2727 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2728
2729 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2730 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2731 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2732}
2733
81906791
SH		 2734static void sky2_restart(struct work_struct *work)
2735{
2736 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2737 struct net_device *dev;
2738 int i, err;
2739
81906791
SH		 2740 rtnl_lock();
2741 sky2_write32(hw, B0_IMSK, 0);
2742 sky2_read32(hw, B0_IMSK);
2743
2744 netif_poll_disable(hw->dev[0]);
2745
2746 for (i = 0; i < hw->ports; i++) {
2747 dev = hw->dev[i];
2748 if (netif_running(dev))
2749 sky2_down(dev);
2750 }
2751
2752 sky2_reset(hw);
2753 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2754 netif_poll_enable(hw->dev[0]);
2755
2756 for (i = 0; i < hw->ports; i++) {
2757 dev = hw->dev[i];
2758 if (netif_running(dev)) {
2759 err = sky2_up(dev);
2760 if (err) {
2761 printk(KERN_INFO PFX "%s: could not restart %d\n",
2762 dev->name, err);
2763 dev_close(dev);
2764 }
2765 }
2766 }
2767
81906791
SH		 2768 rtnl_unlock();
2769}
2770
e3173832
SH		 2771static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2772{
2773 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2774}
2775
2776static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2777{
2778 const struct sky2_port *sky2 = netdev_priv(dev);
2779
2780 wol->supported = sky2_wol_supported(sky2->hw);
2781 wol->wolopts = sky2->wol;
2782}
2783
2784static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2785{
2786 struct sky2_port *sky2 = netdev_priv(dev);
2787 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2788
e3173832
SH		 2789 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2790 return -EOPNOTSUPP;
2791
2792 sky2->wol = wol->wolopts;
2793
69161611 2794 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
e3173832
SH		 2795 sky2_write32(hw, B0_CTST, sky2->wol
2796 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2797
2798 if (!netif_running(dev))
2799 sky2_wol_init(sky2);
cd28ab6a
SH		 2800 return 0;
2801}
2802
28bd181a 2803static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2804{
b89165f2
SH		 2805 if (sky2_is_copper(hw)) {
2806 u32 modes = SUPPORTED_10baseT_Half
2807 | SUPPORTED_10baseT_Full
2808 | SUPPORTED_100baseT_Half
2809 | SUPPORTED_100baseT_Full
2810 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2811
2812 if (hw->chip_id != CHIP_ID_YUKON_FE)
2813 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2814 | SUPPORTED_1000baseT_Full;
2815 return modes;
cd28ab6a 2816 } else
b89165f2
SH		 2817 return SUPPORTED_1000baseT_Half
2818 | SUPPORTED_1000baseT_Full
2819 | SUPPORTED_Autoneg
2820 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2821}
2822
793b883e 2823static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2824{
2825 struct sky2_port *sky2 = netdev_priv(dev);
2826 struct sky2_hw *hw = sky2->hw;
2827
2828 ecmd->transceiver = XCVR_INTERNAL;
2829 ecmd->supported = sky2_supported_modes(hw);
2830 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2831 if (sky2_is_copper(hw)) {
cd28ab6a 2832 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2833 | SUPPORTED_10baseT_Full
2834 | SUPPORTED_100baseT_Half
2835 | SUPPORTED_100baseT_Full
2836 | SUPPORTED_1000baseT_Half
2837 | SUPPORTED_1000baseT_Full
2838 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2839 ecmd->port = PORT_TP;
b89165f2
SH		 2840 ecmd->speed = sky2->speed;
2841 } else {
2842 ecmd->speed = SPEED_1000;
cd28ab6a 2843 ecmd->port = PORT_FIBRE;
b89165f2 2844 }
cd28ab6a
SH		 2845
2846 ecmd->advertising = sky2->advertising;
2847 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2848 ecmd->duplex = sky2->duplex;
2849 return 0;
2850}
2851
2852static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2853{
2854 struct sky2_port *sky2 = netdev_priv(dev);
2855 const struct sky2_hw *hw = sky2->hw;
2856 u32 supported = sky2_supported_modes(hw);
2857
2858 if (ecmd->autoneg == AUTONEG_ENABLE) {
2859 ecmd->advertising = supported;
2860 sky2->duplex = -1;
2861 sky2->speed = -1;
2862 } else {
2863 u32 setting;
2864
793b883e 2865 switch (ecmd->speed) {
cd28ab6a
SH		 2866 case SPEED_1000:
2867 if (ecmd->duplex == DUPLEX_FULL)
2868 setting = SUPPORTED_1000baseT_Full;
2869 else if (ecmd->duplex == DUPLEX_HALF)
2870 setting = SUPPORTED_1000baseT_Half;
2871 else
2872 return -EINVAL;
2873 break;
2874 case SPEED_100:
2875 if (ecmd->duplex == DUPLEX_FULL)
2876 setting = SUPPORTED_100baseT_Full;
2877 else if (ecmd->duplex == DUPLEX_HALF)
2878 setting = SUPPORTED_100baseT_Half;
2879 else
2880 return -EINVAL;
2881 break;
2882
2883 case SPEED_10:
2884 if (ecmd->duplex == DUPLEX_FULL)
2885 setting = SUPPORTED_10baseT_Full;
2886 else if (ecmd->duplex == DUPLEX_HALF)
2887 setting = SUPPORTED_10baseT_Half;
2888 else
2889 return -EINVAL;
2890 break;
2891 default:
2892 return -EINVAL;
2893 }
2894
2895 if ((setting & supported) == 0)
2896 return -EINVAL;
2897
2898 sky2->speed = ecmd->speed;
2899 sky2->duplex = ecmd->duplex;
2900 }
2901
2902 sky2->autoneg = ecmd->autoneg;
2903 sky2->advertising = ecmd->advertising;
2904
d1b139c0 2905 if (netif_running(dev)) {
1b537565 2906 sky2_phy_reinit(sky2);
d1b139c0
SH		 2907 sky2_set_multicast(dev);
2908 }
cd28ab6a
SH		 2909
2910 return 0;
2911}
2912
2913static void sky2_get_drvinfo(struct net_device *dev,
2914 struct ethtool_drvinfo *info)
2915{
2916 struct sky2_port *sky2 = netdev_priv(dev);
2917
2918 strcpy(info->driver, DRV_NAME);
2919 strcpy(info->version, DRV_VERSION);
2920 strcpy(info->fw_version, "N/A");
2921 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2922}
2923
2924static const struct sky2_stat {
793b883e
SH		 2925 char name[ETH_GSTRING_LEN];
2926 u16 offset;
cd28ab6a
SH		 2927} sky2_stats[] = {
2928 { "tx_bytes", GM_TXO_OK_HI },
2929 { "rx_bytes", GM_RXO_OK_HI },
2930 { "tx_broadcast", GM_TXF_BC_OK },
2931 { "rx_broadcast", GM_RXF_BC_OK },
2932 { "tx_multicast", GM_TXF_MC_OK },
2933 { "rx_multicast", GM_RXF_MC_OK },
2934 { "tx_unicast", GM_TXF_UC_OK },
2935 { "rx_unicast", GM_RXF_UC_OK },
2936 { "tx_mac_pause", GM_TXF_MPAUSE },
2937 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2938 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2939 { "late_collision",GM_TXF_LAT_COL },
2940 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2941 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2942 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2943
d2604540 2944 { "rx_short", GM_RXF_SHT },
cd28ab6a 2945 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2946 { "rx_64_byte_packets", GM_RXF_64B },
2947 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2948 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2949 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2950 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2951 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2952 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2953 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2954 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2955 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2956 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2957
2958 { "tx_64_byte_packets", GM_TXF_64B },
2959 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2960 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2961 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2962 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2963 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2964 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2965 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2966};
2967
cd28ab6a
SH		 2968static u32 sky2_get_rx_csum(struct net_device *dev)
2969{
2970 struct sky2_port *sky2 = netdev_priv(dev);
2971
2972 return sky2->rx_csum;
2973}
2974
2975static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2976{
2977 struct sky2_port *sky2 = netdev_priv(dev);
2978
2979 sky2->rx_csum = data;
793b883e 2980
cd28ab6a
SH		 2981 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2982 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2983
2984 return 0;
2985}
2986
2987static u32 sky2_get_msglevel(struct net_device *netdev)
2988{
2989 struct sky2_port *sky2 = netdev_priv(netdev);
2990 return sky2->msg_enable;
2991}
2992
9a7ae0a9
SH		 2993static int sky2_nway_reset(struct net_device *dev)
2994{
2995 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2996
16ad91e1 2997 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2998 return -EINVAL;
2999
1b537565 3000 sky2_phy_reinit(sky2);
d1b139c0 3001 sky2_set_multicast(dev);
9a7ae0a9
SH		 3002
3003 return 0;
3004}
3005
793b883e 3006static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3007{
3008 struct sky2_hw *hw = sky2->hw;
3009 unsigned port = sky2->port;
3010 int i;
3011
3012 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3013 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3014 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3015 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3016
793b883e 3017 for (i = 2; i < count; i++)
cd28ab6a
SH		 3018 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3019}
3020
cd28ab6a
SH		 3021static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3022{
3023 struct sky2_port *sky2 = netdev_priv(netdev);
3024 sky2->msg_enable = value;
3025}
3026
3027static int sky2_get_stats_count(struct net_device *dev)
3028{
3029 return ARRAY_SIZE(sky2_stats);
3030}
3031
3032static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3033 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3034{
3035 struct sky2_port *sky2 = netdev_priv(dev);
3036
793b883e 3037 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3038}
3039
793b883e 3040static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3041{
3042 int i;
3043
3044 switch (stringset) {
3045 case ETH_SS_STATS:
3046 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3047 memcpy(data + i * ETH_GSTRING_LEN,
3048 sky2_stats[i].name, ETH_GSTRING_LEN);
3049 break;
3050 }
3051}
3052
cd28ab6a
SH		 3053static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3054{
3055 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3056 return &sky2->net_stats;
3057}
3058
3059static int sky2_set_mac_address(struct net_device *dev, void *p)
3060{
3061 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3062 struct sky2_hw *hw = sky2->hw;
3063 unsigned port = sky2->port;
3064 const struct sockaddr *addr = p;
cd28ab6a
SH		 3065
3066 if (!is_valid_ether_addr(addr->sa_data))
3067 return -EADDRNOTAVAIL;
3068
cd28ab6a 3069 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3070 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3071 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3072 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3073 dev->dev_addr, ETH_ALEN);
1b537565 3074
a8ab1ec0
SH		 3075 /* virtual address for data */
3076 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3077
3078 /* physical address: used for pause frames */
3079 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3080
3081 return 0;
cd28ab6a
SH		 3082}
3083
a052b52f
SH		 3084static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3085{
3086 u32 bit;
3087
3088 bit = ether_crc(ETH_ALEN, addr) & 63;
3089 filter[bit >> 3] |= 1 << (bit & 7);
3090}
3091
cd28ab6a
SH		 3092static void sky2_set_multicast(struct net_device *dev)
3093{
3094 struct sky2_port *sky2 = netdev_priv(dev);
3095 struct sky2_hw *hw = sky2->hw;
3096 unsigned port = sky2->port;
3097 struct dev_mc_list *list = dev->mc_list;
3098 u16 reg;
3099 u8 filter[8];
a052b52f
SH		 3100 int rx_pause;
3101 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3102
a052b52f 3103 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3104 memset(filter, 0, sizeof(filter));
3105
3106 reg = gma_read16(hw, port, GM_RX_CTRL);
3107 reg |= GM_RXCR_UCF_ENA;
3108
d571b694 3109 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3110 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3111 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3112 memset(filter, 0xff, sizeof(filter));
a052b52f 3113 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3114 reg &= ~GM_RXCR_MCF_ENA;
3115 else {
3116 int i;
3117 reg |= GM_RXCR_MCF_ENA;
3118
a052b52f
SH		 3119 if (rx_pause)
3120 sky2_add_filter(filter, pause_mc_addr);
3121
3122 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3123 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3124 }
3125
cd28ab6a 3126 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3127 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3128 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3129 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3130 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3131 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3132 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3133 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3134
3135 gma_write16(hw, port, GM_RX_CTRL, reg);
3136}
3137
3138/* Can have one global because blinking is controlled by
3139 * ethtool and that is always under RTNL mutex
3140 */
91c86df5 3141static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3142{
793b883e
SH		 3143 u16 pg;
3144
793b883e
SH		 3145 switch (hw->chip_id) {
3146 case CHIP_ID_YUKON_XL:
3147 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3148 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3149 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3150 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3151 PHY_M_LEDC_INIT_CTRL(7) |
3152 PHY_M_LEDC_STA1_CTRL(7) |
3153 PHY_M_LEDC_STA0_CTRL(7))
3154 : 0);
3155
3156 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3157 break;
3158
3159 default:
3160 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3161 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3162 on ? PHY_M_LED_ALL : 0);
793b883e 3163 }
cd28ab6a
SH		 3164}
3165
3166/* blink LED's for finding board */
3167static int sky2_phys_id(struct net_device *dev, u32 data)
3168{
3169 struct sky2_port *sky2 = netdev_priv(dev);
3170 struct sky2_hw *hw = sky2->hw;
3171 unsigned port = sky2->port;
793b883e 3172 u16 ledctrl, ledover = 0;
cd28ab6a 3173 long ms;
91c86df5 3174 int interrupted;
cd28ab6a
SH		 3175 int onoff = 1;
3176
793b883e 3177 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3178 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3179 else
3180 ms = data * 1000;
3181
3182 /* save initial values */
e07b1aa8 3183 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3184 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3185 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3186 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3187 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3188 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3189 } else {
3190 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3191 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3192 }
cd28ab6a 3193
91c86df5
SH		 3194 interrupted = 0;
3195 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3196 sky2_led(hw, port, onoff);
3197 onoff = !onoff;
3198
e07b1aa8 3199 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3200 interrupted = msleep_interruptible(250);
e07b1aa8 3201 spin_lock_bh(&sky2->phy_lock);
91c86df5 3202
cd28ab6a
SH		 3203 ms -= 250;
3204 }
3205
3206 /* resume regularly scheduled programming */
793b883e
SH		 3207 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3208 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3209 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3210 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3211 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3212 } else {
3213 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3214 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3215 }
e07b1aa8 3216 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3217
3218 return 0;
3219}
3220
3221static void sky2_get_pauseparam(struct net_device *dev,
3222 struct ethtool_pauseparam *ecmd)
3223{
3224 struct sky2_port *sky2 = netdev_priv(dev);
3225
16ad91e1
SH		 3226 switch (sky2->flow_mode) {
3227 case FC_NONE:
3228 ecmd->tx_pause = ecmd->rx_pause = 0;
3229 break;
3230 case FC_TX:
3231 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3232 break;
3233 case FC_RX:
3234 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3235 break;
3236 case FC_BOTH:
3237 ecmd->tx_pause = ecmd->rx_pause = 1;
3238 }
3239
cd28ab6a
SH		 3240 ecmd->autoneg = sky2->autoneg;
3241}
3242
3243static int sky2_set_pauseparam(struct net_device *dev,
3244 struct ethtool_pauseparam *ecmd)
3245{
3246 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3247
3248 sky2->autoneg = ecmd->autoneg;
16ad91e1 3249 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3250
16ad91e1
SH		 3251 if (netif_running(dev))
3252 sky2_phy_reinit(sky2);
cd28ab6a 3253
2eaba1a2 3254 return 0;
cd28ab6a
SH		 3255}
3256
fb17358f
SH		 3257static int sky2_get_coalesce(struct net_device *dev,
3258 struct ethtool_coalesce *ecmd)
3259{
3260 struct sky2_port *sky2 = netdev_priv(dev);
3261 struct sky2_hw *hw = sky2->hw;
3262
3263 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3264 ecmd->tx_coalesce_usecs = 0;
3265 else {
3266 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3267 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3268 }
3269 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3270
3271 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3272 ecmd->rx_coalesce_usecs = 0;
3273 else {
3274 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3275 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3276 }
3277 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3278
3279 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3280 ecmd->rx_coalesce_usecs_irq = 0;
3281 else {
3282 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3283 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3284 }
3285
3286 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3287
3288 return 0;
3289}
3290
3291/* Note: this affect both ports */
3292static int sky2_set_coalesce(struct net_device *dev,
3293 struct ethtool_coalesce *ecmd)
3294{
3295 struct sky2_port *sky2 = netdev_priv(dev);
3296 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3297 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3298
77b3d6a2
SH		 3299 if (ecmd->tx_coalesce_usecs > tmax ||
3300 ecmd->rx_coalesce_usecs > tmax ||
3301 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3302 return -EINVAL;
3303
ff81fbbe 3304 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3305 return -EINVAL;
ff81fbbe 3306 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3307 return -EINVAL;
ff81fbbe 3308 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3309 return -EINVAL;
3310
3311 if (ecmd->tx_coalesce_usecs == 0)
3312 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3313 else {
3314 sky2_write32(hw, STAT_TX_TIMER_INI,
3315 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3316 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3317 }
3318 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3319
3320 if (ecmd->rx_coalesce_usecs == 0)
3321 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3322 else {
3323 sky2_write32(hw, STAT_LEV_TIMER_INI,
3324 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3325 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3326 }
3327 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3328
3329 if (ecmd->rx_coalesce_usecs_irq == 0)
3330 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3331 else {
d28d4870 3332 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3333 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3334 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3335 }
3336 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3337 return 0;
3338}
3339
793b883e
SH		 3340static void sky2_get_ringparam(struct net_device *dev,
3341 struct ethtool_ringparam *ering)
3342{
3343 struct sky2_port *sky2 = netdev_priv(dev);
3344
3345 ering->rx_max_pending = RX_MAX_PENDING;
3346 ering->rx_mini_max_pending = 0;
3347 ering->rx_jumbo_max_pending = 0;
3348 ering->tx_max_pending = TX_RING_SIZE - 1;
3349
3350 ering->rx_pending = sky2->rx_pending;
3351 ering->rx_mini_pending = 0;
3352 ering->rx_jumbo_pending = 0;
3353 ering->tx_pending = sky2->tx_pending;
3354}
3355
3356static int sky2_set_ringparam(struct net_device *dev,
3357 struct ethtool_ringparam *ering)
3358{
3359 struct sky2_port *sky2 = netdev_priv(dev);
3360 int err = 0;
3361
3362 if (ering->rx_pending > RX_MAX_PENDING ||
3363 ering->rx_pending < 8 ||
3364 ering->tx_pending < MAX_SKB_TX_LE ||
3365 ering->tx_pending > TX_RING_SIZE - 1)
3366 return -EINVAL;
3367
3368 if (netif_running(dev))
3369 sky2_down(dev);
3370
3371 sky2->rx_pending = ering->rx_pending;
3372 sky2->tx_pending = ering->tx_pending;
3373
1b537565 3374 if (netif_running(dev)) {
793b883e 3375 err = sky2_up(dev);
1b537565
SH		 3376 if (err)
3377 dev_close(dev);
6ed995bb
SH		 3378 else
3379 sky2_set_multicast(dev);
1b537565 3380 }
793b883e
SH		 3381
3382 return err;
3383}
3384
793b883e
SH		 3385static int sky2_get_regs_len(struct net_device *dev)
3386{
6e4cbb34 3387 return 0x4000;
793b883e
SH		 3388}
3389
3390/*
3391 * Returns copy of control register region
3ead5db7 3392 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3393 */
3394static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3395 void *p)
3396{
3397 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3398 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3399
3400 regs->version = 1;
6e4cbb34 3401 memset(p, 0, regs->len);
793b883e 3402
6e4cbb34
SH		 3403 memcpy_fromio(p, io, B3_RAM_ADDR);
3404
3ead5db7
SH		 3405 /* skip diagnostic ram region */
3406 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3407
3408 /* copy GMAC registers */
3409 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3410 if (sky2->hw->ports > 1)
3411 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3412
793b883e 3413}
cd28ab6a 3414
b628ed98
SH		 3415/* In order to do Jumbo packets on these chips, need to turn off the
3416 * transmit store/forward. Therefore checksum offload won't work.
3417 */
3418static int no_tx_offload(struct net_device *dev)
3419{
3420 const struct sky2_port *sky2 = netdev_priv(dev);
3421 const struct sky2_hw *hw = sky2->hw;
3422
69161611 3423 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3424}
3425
3426static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3427{
3428 if (data && no_tx_offload(dev))
3429 return -EINVAL;
3430
3431 return ethtool_op_set_tx_csum(dev, data);
3432}
3433
3434
3435static int sky2_set_tso(struct net_device *dev, u32 data)
3436{
3437 if (data && no_tx_offload(dev))
3438 return -EINVAL;
3439
3440 return ethtool_op_set_tso(dev, data);
3441}
3442
f4331a6d
SH		 3443static int sky2_get_eeprom_len(struct net_device *dev)
3444{
3445 struct sky2_port *sky2 = netdev_priv(dev);
3446 u16 reg2;
3447
3448 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3449 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3450}
3451
3452static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3453{
3454 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3455
3456 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3457 cpu_relax();
3458 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3459}
3460
3461static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3462{
3463 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3464 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3465 do {
3466 cpu_relax();
3467 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3468}
3469
3470static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3471 u8 *data)
3472{
3473 struct sky2_port *sky2 = netdev_priv(dev);
3474 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3475 int length = eeprom->len;
3476 u16 offset = eeprom->offset;
3477
3478 if (!cap)
3479 return -EINVAL;
3480
3481 eeprom->magic = SKY2_EEPROM_MAGIC;
3482
3483 while (length > 0) {
3484 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3485 int n = min_t(int, length, sizeof(val));
3486
3487 memcpy(data, &val, n);
3488 length -= n;
3489 data += n;
3490 offset += n;
3491 }
3492 return 0;
3493}
3494
3495static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3496 u8 *data)
3497{
3498 struct sky2_port *sky2 = netdev_priv(dev);
3499 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3500 int length = eeprom->len;
3501 u16 offset = eeprom->offset;
3502
3503 if (!cap)
3504 return -EINVAL;
3505
3506 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3507 return -EINVAL;
3508
3509 while (length > 0) {
3510 u32 val;
3511 int n = min_t(int, length, sizeof(val));
3512
3513 if (n < sizeof(val))
3514 val = sky2_vpd_read(sky2->hw, cap, offset);
3515 memcpy(&val, data, n);
3516
3517 sky2_vpd_write(sky2->hw, cap, offset, val);
3518
3519 length -= n;
3520 data += n;
3521 offset += n;
3522 }
3523 return 0;
3524}
3525
3526
7282d491 3527static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3528 .get_settings = sky2_get_settings,
3529 .set_settings = sky2_set_settings,
3530 .get_drvinfo = sky2_get_drvinfo,
3531 .get_wol = sky2_get_wol,
3532 .set_wol = sky2_set_wol,
3533 .get_msglevel = sky2_get_msglevel,
3534 .set_msglevel = sky2_set_msglevel,
3535 .nway_reset = sky2_nway_reset,
3536 .get_regs_len = sky2_get_regs_len,
3537 .get_regs = sky2_get_regs,
3538 .get_link = ethtool_op_get_link,
3539 .get_eeprom_len = sky2_get_eeprom_len,
3540 .get_eeprom = sky2_get_eeprom,
3541 .set_eeprom = sky2_set_eeprom,
3542 .get_sg = ethtool_op_get_sg,
3543 .set_sg = ethtool_op_set_sg,
3544 .get_tx_csum = ethtool_op_get_tx_csum,
3545 .set_tx_csum = sky2_set_tx_csum,
3546 .get_tso = ethtool_op_get_tso,
3547 .set_tso = sky2_set_tso,
3548 .get_rx_csum = sky2_get_rx_csum,
3549 .set_rx_csum = sky2_set_rx_csum,
3550 .get_strings = sky2_get_strings,
3551 .get_coalesce = sky2_get_coalesce,
3552 .set_coalesce = sky2_set_coalesce,
3553 .get_ringparam = sky2_get_ringparam,
3554 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3555 .get_pauseparam = sky2_get_pauseparam,
3556 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3557 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3558 .get_stats_count = sky2_get_stats_count,
3559 .get_ethtool_stats = sky2_get_ethtool_stats,
3560};
3561
3cf26753
SH		 3562#ifdef CONFIG_SKY2_DEBUG
3563
3564static struct dentry *sky2_debug;
3565
3566static int sky2_debug_show(struct seq_file *seq, void *v)
3567{
3568 struct net_device *dev = seq->private;
3569 const struct sky2_port *sky2 = netdev_priv(dev);
3570 const struct sky2_hw *hw = sky2->hw;
3571 unsigned port = sky2->port;
3572 unsigned idx, last;
3573 int sop;
3574
3575 if (!netif_running(dev))
3576 return -ENETDOWN;
3577
3578 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3579 sky2_read32(hw, B0_ISRC),
3580 sky2_read32(hw, B0_IMSK),
3581 sky2_read32(hw, B0_Y2_SP_ICR));
3582
3583 netif_poll_disable(hw->dev[0]);
3584 last = sky2_read16(hw, STAT_PUT_IDX);
3585
3586 if (hw->st_idx == last)
3587 seq_puts(seq, "Status ring (empty)\n");
3588 else {
3589 seq_puts(seq, "Status ring\n");
3590 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3591 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3592 const struct sky2_status_le *le = hw->st_le + idx;
3593 seq_printf(seq, "[%d] %#x %d %#x\n",
3594 idx, le->opcode, le->length, le->status);
3595 }
3596 seq_puts(seq, "\n");
3597 }
3598
3599 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3600 sky2->tx_cons, sky2->tx_prod,
3601 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3602 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3603
3604 /* Dump contents of tx ring */
3605 sop = 1;
3606 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3607 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3608 const struct sky2_tx_le *le = sky2->tx_le + idx;
3609 u32 a = le32_to_cpu(le->addr);
3610
3611 if (sop)
3612 seq_printf(seq, "%u:", idx);
3613 sop = 0;
3614
3615 switch(le->opcode & ~HW_OWNER) {
3616 case OP_ADDR64:
3617 seq_printf(seq, " %#x:", a);
3618 break;
3619 case OP_LRGLEN:
3620 seq_printf(seq, " mtu=%d", a);
3621 break;
3622 case OP_VLAN:
3623 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3624 break;
3625 case OP_TCPLISW:
3626 seq_printf(seq, " csum=%#x", a);
3627 break;
3628 case OP_LARGESEND:
3629 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3630 break;
3631 case OP_PACKET:
3632 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3633 break;
3634 case OP_BUFFER:
3635 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3636 break;
3637 default:
3638 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3639 a, le16_to_cpu(le->length));
3640 }
3641
3642 if (le->ctrl & EOP) {
3643 seq_putc(seq, '\n');
3644 sop = 1;
3645 }
3646 }
3647
3648 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3649 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3650 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3651 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3652
3653 netif_poll_enable(hw->dev[0]);
3654 return 0;
3655}
3656
3657static int sky2_debug_open(struct inode *inode, struct file *file)
3658{
3659 return single_open(file, sky2_debug_show, inode->i_private);
3660}
3661
3662static const struct file_operations sky2_debug_fops = {
3663 .owner = THIS_MODULE,
3664 .open = sky2_debug_open,
3665 .read = seq_read,
3666 .llseek = seq_lseek,
3667 .release = single_release,
3668};
3669
3670/*
3671 * Use network device events to create/remove/rename
3672 * debugfs file entries
3673 */
3674static int sky2_device_event(struct notifier_block *unused,
3675 unsigned long event, void *ptr)
3676{
3677 struct net_device *dev = ptr;
3678
3679 if (dev->open == sky2_up) {
3680 struct sky2_port *sky2 = netdev_priv(dev);
3681
3682 switch(event) {
3683 case NETDEV_CHANGENAME:
3684 if (!netif_running(dev))
3685 break;
3686 /* fallthrough */
3687 case NETDEV_DOWN:
3688 case NETDEV_GOING_DOWN:
3689 if (sky2->debugfs) {
3690 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3691 dev->name);
3692 debugfs_remove(sky2->debugfs);
3693 sky2->debugfs = NULL;
3694 }
3695
3696 if (event != NETDEV_CHANGENAME)
3697 break;
3698 /* fallthrough for changename */
3699 case NETDEV_UP:
3700 if (sky2_debug) {
3701 struct dentry *d;
3702 d = debugfs_create_file(dev->name, S_IRUGO,
3703 sky2_debug, dev,
3704 &sky2_debug_fops);
3705 if (d == NULL || IS_ERR(d))
3706 printk(KERN_INFO PFX
3707 "%s: debugfs create failed\n",
3708 dev->name);
3709 else
3710 sky2->debugfs = d;
3711 }
3712 break;
3713 }
3714 }
3715
3716 return NOTIFY_DONE;
3717}
3718
3719static struct notifier_block sky2_notifier = {
3720 .notifier_call = sky2_device_event,
3721};
3722
3723
3724static __init void sky2_debug_init(void)
3725{
3726 struct dentry *ent;
3727
3728 ent = debugfs_create_dir("sky2", NULL);
3729 if (!ent || IS_ERR(ent))
3730 return;
3731
3732 sky2_debug = ent;
3733 register_netdevice_notifier(&sky2_notifier);
3734}
3735
3736static __exit void sky2_debug_cleanup(void)
3737{
3738 if (sky2_debug) {
3739 unregister_netdevice_notifier(&sky2_notifier);
3740 debugfs_remove(sky2_debug);
3741 sky2_debug = NULL;
3742 }
3743}
3744
3745#else
3746#define sky2_debug_init()
3747#define sky2_debug_cleanup()
3748#endif
3749
3750
cd28ab6a
SH		 3751/* Initialize network device */
3752static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3753 unsigned port,
3754 int highmem, int wol)
cd28ab6a
SH		 3755{
3756 struct sky2_port *sky2;
3757 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3758
3759 if (!dev) {
b02a9258 3760 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3761 return NULL;
3762 }
3763
3764 SET_MODULE_OWNER(dev);
3765 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3766 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3767 dev->open = sky2_up;
3768 dev->stop = sky2_down;
ef743d33 3769 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3770 dev->hard_start_xmit = sky2_xmit_frame;
3771 dev->get_stats = sky2_get_stats;
3772 dev->set_multicast_list = sky2_set_multicast;
3773 dev->set_mac_address = sky2_set_mac_address;
3774 dev->change_mtu = sky2_change_mtu;
3775 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3776 dev->tx_timeout = sky2_tx_timeout;
3777 dev->watchdog_timeo = TX_WATCHDOG;
3778 if (port == 0)
3779 dev->poll = sky2_poll;
3780 dev->weight = NAPI_WEIGHT;
3781#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3782 /* Network console (only works on port 0)
3783 * because netpoll makes assumptions about NAPI
3784 */
3785 if (port == 0)
3786 dev->poll_controller = sky2_netpoll;
cd28ab6a 3787#endif
cd28ab6a
SH		 3788
3789 sky2 = netdev_priv(dev);
3790 sky2->netdev = dev;
3791 sky2->hw = hw;
3792 sky2->msg_enable = netif_msg_init(debug, default_msg);
3793
cd28ab6a
SH		 3794 /* Auto speed and flow control */
3795 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3796 sky2->flow_mode = FC_BOTH;
3797
cd28ab6a
SH		 3798 sky2->duplex = -1;
3799 sky2->speed = -1;
3800 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3801 sky2->rx_csum = 1;
e3173832 3802 sky2->wol = wol;
75d070c5 3803
e07b1aa8 3804 spin_lock_init(&sky2->phy_lock);
793b883e 3805 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3806 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3807
3808 hw->dev[port] = dev;
3809
3810 sky2->port = port;
3811
4a50a876 3812 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3813 if (highmem)
3814 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3815
d1f13708
SH		 3816#ifdef SKY2_VLAN_TAG_USED
3817 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3818 dev->vlan_rx_register = sky2_vlan_rx_register;
d1f13708
SH		 3819#endif
3820
cd28ab6a 3821 /* read the mac address */
793b883e 3822 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3823 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 3824
cd28ab6a
SH		 3825 return dev;
3826}
3827
28bd181a 3828static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3829{
3830 const struct sky2_port *sky2 = netdev_priv(dev);
3831
3832 if (netif_msg_probe(sky2))
3833 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3834 dev->name,
3835 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3836 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3837}
3838
fb2690a9 3839/* Handle software interrupt used during MSI test */
7d12e780 3840static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3841{
3842 struct sky2_hw *hw = dev_id;
3843 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3844
3845 if (status == 0)
3846 return IRQ_NONE;
3847
3848 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3849 hw->msi = 1;
fb2690a9
SH		 3850 wake_up(&hw->msi_wait);
3851 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3852 }
3853 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3854
3855 return IRQ_HANDLED;
3856}
3857
3858/* Test interrupt path by forcing a a software IRQ */
3859static int __devinit sky2_test_msi(struct sky2_hw *hw)
3860{
3861 struct pci_dev *pdev = hw->pdev;
3862 int err;
3863
bb507fe1
SH		 3864 init_waitqueue_head (&hw->msi_wait);
3865
fb2690a9
SH		 3866 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3867
b0a20ded 3868 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3869 if (err) {
b02a9258 3870 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3871 return err;
3872 }
3873
fb2690a9 3874 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3875 sky2_read8(hw, B0_CTST);
fb2690a9 3876
b0a20ded 3877 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3878
b0a20ded 3879 if (!hw->msi) {
fb2690a9 3880 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3881 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3882 "switching to INTx mode.\n");
fb2690a9
SH		 3883
3884 err = -EOPNOTSUPP;
3885 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3886 }
3887
3888 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3889 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3890
3891 free_irq(pdev->irq, hw);
3892
3893 return err;
3894}
3895
e3173832
SH		 3896static int __devinit pci_wake_enabled(struct pci_dev *dev)
3897{
3898 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3899 u16 value;
3900
3901 if (!pm)
3902 return 0;
3903 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3904 return 0;
3905 return value & PCI_PM_CTRL_PME_ENABLE;
3906}
3907
cd28ab6a
SH		 3908static int __devinit sky2_probe(struct pci_dev *pdev,
3909 const struct pci_device_id *ent)
3910{
7f60c64b 3911 struct net_device *dev;
cd28ab6a 3912 struct sky2_hw *hw;
e3173832 3913 int err, using_dac = 0, wol_default;
cd28ab6a 3914
793b883e
SH		 3915 err = pci_enable_device(pdev);
3916 if (err) {
b02a9258 3917 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3918 goto err_out;
3919 }
3920
793b883e
SH		 3921 err = pci_request_regions(pdev, DRV_NAME);
3922 if (err) {
b02a9258 3923 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 3924 goto err_out_disable;
cd28ab6a
SH		 3925 }
3926
3927 pci_set_master(pdev);
3928
d1f3d4dd
SH		 3929 if (sizeof(dma_addr_t) > sizeof(u32) &&
3930 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3931 using_dac = 1;
3932 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3933 if (err < 0) {
b02a9258
SH		 3934 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3935 "for consistent allocations\n");
d1f3d4dd
SH		 3936 goto err_out_free_regions;
3937 }
d1f3d4dd 3938 } else {
cd28ab6a
SH		 3939 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3940 if (err) {
b02a9258 3941 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3942 goto err_out_free_regions;
3943 }
3944 }
d1f3d4dd 3945
e3173832
SH		 3946 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3947
cd28ab6a 3948 err = -ENOMEM;
6aad85d6 3949 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3950 if (!hw) {
b02a9258 3951 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3952 goto err_out_free_regions;
3953 }
3954
cd28ab6a 3955 hw->pdev = pdev;
cd28ab6a
SH		 3956
3957 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3958 if (!hw->regs) {
b02a9258 3959 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3960 goto err_out_free_hw;
3961 }
3962
56a645cc 3963#ifdef __BIG_ENDIAN
f65b138c
SH		 3964 /* The sk98lin vendor driver uses hardware byte swapping but
3965 * this driver uses software swapping.
3966 */
56a645cc
SH		 3967 {
3968 u32 reg;
56a645cc 3969 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3970 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3971 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3972 }
3973#endif
3974
08c06d8a
SH		 3975 /* ring for status responses */
3976 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3977 &hw->st_dma);
3978 if (!hw->st_le)
3979 goto err_out_iounmap;
3980
e3173832 3981 err = sky2_init(hw);
cd28ab6a 3982 if (err)
793b883e 3983 goto err_out_iounmap;
cd28ab6a 3984
b02a9258 3985 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3986 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3987 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3988 hw->chip_id, hw->chip_rev);
cd28ab6a 3989
e3173832
SH		 3990 sky2_reset(hw);
3991
3992 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3993 if (!dev) {
3994 err = -ENOMEM;
cd28ab6a 3995 goto err_out_free_pci;
7f60c64b 3996 }
cd28ab6a 3997
9fa1b1f3
SH		 3998 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3999 err = sky2_test_msi(hw);
4000 if (err == -EOPNOTSUPP)
4001 pci_disable_msi(pdev);
4002 else if (err)
4003 goto err_out_free_netdev;
4004 }
4005
793b883e
SH		 4006 err = register_netdev(dev);
4007 if (err) {
b02a9258 4008 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4009 goto err_out_free_netdev;
4010 }
4011
b0a20ded
SH		 4012 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
4013 dev->name, hw);
9fa1b1f3 4014 if (err) {
b02a9258 4015 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4016 goto err_out_unregister;
4017 }
4018 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4019
cd28ab6a
SH		 4020 sky2_show_addr(dev);
4021
7f60c64b 4022 if (hw->ports > 1) {
4023 struct net_device *dev1;
4024
e3173832 4025 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4026 if (!dev1)
4027 dev_warn(&pdev->dev, "allocation for second device failed\n");
4028 else if ((err = register_netdev(dev1))) {
4029 dev_warn(&pdev->dev,
4030 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4031 hw->dev[1] = NULL;
4032 free_netdev(dev1);
b02a9258
SH		 4033 } else
4034 sky2_show_addr(dev1);
cd28ab6a
SH		 4035 }
4036
32c2c300 4037 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4038 INIT_WORK(&hw->restart_work, sky2_restart);
4039
793b883e
SH		 4040 pci_set_drvdata(pdev, hw);
4041
cd28ab6a
SH		 4042 return 0;
4043
793b883e 4044err_out_unregister:
b0a20ded
SH		 4045 if (hw->msi)
4046 pci_disable_msi(pdev);
793b883e 4047 unregister_netdev(dev);
cd28ab6a
SH		 4048err_out_free_netdev:
4049 free_netdev(dev);
cd28ab6a 4050err_out_free_pci:
793b883e 4051 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4052 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4053err_out_iounmap:
4054 iounmap(hw->regs);
4055err_out_free_hw:
4056 kfree(hw);
4057err_out_free_regions:
4058 pci_release_regions(pdev);
44a1d2e5 4059err_out_disable:
cd28ab6a 4060 pci_disable_device(pdev);
cd28ab6a 4061err_out:
549a68c3 4062 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4063 return err;
4064}
4065
4066static void __devexit sky2_remove(struct pci_dev *pdev)
4067{
793b883e 4068 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 4069 struct net_device *dev0, *dev1;
4070
793b883e 4071 if (!hw)
cd28ab6a
SH		 4072 return;
4073
32c2c300 4074 del_timer_sync(&hw->watchdog_timer);
d27ed387 4075
81906791
SH		 4076 flush_scheduled_work();
4077
d27ed387 4078 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 4079 synchronize_irq(hw->pdev->irq);
4080
cd28ab6a 4081 dev0 = hw->dev[0];
793b883e
SH		 4082 dev1 = hw->dev[1];
4083 if (dev1)
4084 unregister_netdev(dev1);
cd28ab6a
SH		 4085 unregister_netdev(dev0);
4086
ae306cca
SH		 4087 sky2_power_aux(hw);
4088
cd28ab6a 4089 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4090 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4091 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4092
4093 free_irq(pdev->irq, hw);
b0a20ded
SH		 4094 if (hw->msi)
4095 pci_disable_msi(pdev);
793b883e 4096 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4097 pci_release_regions(pdev);
4098 pci_disable_device(pdev);
793b883e 4099
cd28ab6a
SH		 4100 if (dev1)
4101 free_netdev(dev1);
4102 free_netdev(dev0);
4103 iounmap(hw->regs);
4104 kfree(hw);
5afa0a9c 4105
cd28ab6a
SH		 4106 pci_set_drvdata(pdev, NULL);
4107}
4108
4109#ifdef CONFIG_PM
4110static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4111{
793b883e 4112 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4113 int i, wol = 0;
cd28ab6a 4114
549a68c3
SH		 4115 if (!hw)
4116 return 0;
4117
6a5706b9 4118 netif_poll_disable(hw->dev[0]);
eb35cf60 4119
f05267e7 4120 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4121 struct net_device *dev = hw->dev[i];
e3173832 4122 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4123
e3173832 4124 if (netif_running(dev))
5afa0a9c 4125 sky2_down(dev);
e3173832
SH		 4126
4127 if (sky2->wol)
4128 sky2_wol_init(sky2);
4129
4130 wol |= sky2->wol;
cd28ab6a
SH		 4131 }
4132
8ab8fca2 4133 sky2_write32(hw, B0_IMSK, 0);
ae306cca 4134 sky2_power_aux(hw);
e3173832 4135
d374c1c1 4136 pci_save_state(pdev);
e3173832 4137 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4138 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4139
2ccc99b7 4140 return 0;
cd28ab6a
SH		 4141}
4142
4143static int sky2_resume(struct pci_dev *pdev)
4144{
793b883e 4145 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4146 int i, err;
cd28ab6a 4147
549a68c3
SH		 4148 if (!hw)
4149 return 0;
4150
ae306cca
SH		 4151 err = pci_set_power_state(pdev, PCI_D0);
4152 if (err)
4153 goto out;
4154
4155 err = pci_restore_state(pdev);
4156 if (err)
4157 goto out;
4158
cd28ab6a 4159 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4160
4161 /* Re-enable all clocks */
4162 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
4163 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4164
e3173832 4165 sky2_reset(hw);
cd28ab6a 4166
8ab8fca2
SH		 4167 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4168
f05267e7 4169 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4170 struct net_device *dev = hw->dev[i];
6a5706b9 4171 if (netif_running(dev)) {
08c06d8a
SH		 4172 err = sky2_up(dev);
4173 if (err) {
4174 printk(KERN_ERR PFX "%s: could not up: %d\n",
4175 dev->name, err);
4176 dev_close(dev);
eb35cf60 4177 goto out;
5afa0a9c 4178 }
d1b139c0
SH		 4179
4180 sky2_set_multicast(dev);
cd28ab6a
SH		 4181 }
4182 }
eb35cf60 4183
6a5706b9 4184 netif_poll_enable(hw->dev[0]);
32c2c300 4185
ae306cca 4186 return 0;
08c06d8a 4187out:
b02a9258 4188 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4189 pci_disable_device(pdev);
08c06d8a 4190 return err;
cd28ab6a
SH		 4191}
4192#endif
4193
e3173832
SH		 4194static void sky2_shutdown(struct pci_dev *pdev)
4195{
4196 struct sky2_hw *hw = pci_get_drvdata(pdev);
4197 int i, wol = 0;
4198
549a68c3
SH		 4199 if (!hw)
4200 return;
4201
e3173832
SH		 4202 netif_poll_disable(hw->dev[0]);
4203
4204 for (i = 0; i < hw->ports; i++) {
4205 struct net_device *dev = hw->dev[i];
4206 struct sky2_port *sky2 = netdev_priv(dev);
4207
4208 if (sky2->wol) {
4209 wol = 1;
4210 sky2_wol_init(sky2);
4211 }
4212 }
4213
4214 if (wol)
4215 sky2_power_aux(hw);
4216
4217 pci_enable_wake(pdev, PCI_D3hot, wol);
4218 pci_enable_wake(pdev, PCI_D3cold, wol);
4219
4220 pci_disable_device(pdev);
4221 pci_set_power_state(pdev, PCI_D3hot);
4222
4223}
4224
cd28ab6a 4225static struct pci_driver sky2_driver = {
793b883e
SH		 4226 .name = DRV_NAME,
4227 .id_table = sky2_id_table,
4228 .probe = sky2_probe,
4229 .remove = __devexit_p(sky2_remove),
cd28ab6a 4230#ifdef CONFIG_PM
793b883e
SH		 4231 .suspend = sky2_suspend,
4232 .resume = sky2_resume,
cd28ab6a 4233#endif
e3173832 4234 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4235};
4236
4237static int __init sky2_init_module(void)
4238{
3cf26753 4239 sky2_debug_init();
50241c4c 4240 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4241}
4242
4243static void __exit sky2_cleanup_module(void)
4244{
4245 pci_unregister_driver(&sky2_driver);
3cf26753 4246 sky2_debug_cleanup();
cd28ab6a
SH		 4247}
4248
4249module_init(sky2_init_module);
4250module_exit(sky2_cleanup_module);
4251
4252MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4253MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4254MODULE_LICENSE("GPL");
5f4f9dc1 4255MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree