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sky2: safer transmit timeout
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
ef743d33 41#include <linux/mii.h>
cd28ab6a
SH		 42
43#include <asm/irq.h>
44
d1f13708
SH		 45#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46#define SKY2_VLAN_TAG_USED 1
47#endif
48
cd28ab6a
SH		 49#include "sky2.h"
50
51#define DRV_NAME "sky2"
285e6ddd 52#define DRV_VERSION "1.11.1"
cd28ab6a
SH		 53#define PFX DRV_NAME " "
54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
14d0263f 58 * similar to Tigon3.
cd28ab6a
SH		 59 */
60
14d0263f 61#define RX_LE_SIZE 1024
cd28ab6a 62#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 63#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 64#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 65#define RX_SKB_ALIGN 8
22e11703 66#define RX_BUF_WRITE 16
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
cb5d9547
SH		 79#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80
cd28ab6a 81static const u32 default_msg =
793b883e
SH		 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 85
793b883e 86static int debug = -1; /* defaults above */
cd28ab6a
SH		 87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
14d0263f 90static int copybreak __read_mostly = 128;
bdb5c58e
SH		 91module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
fb2690a9
SH		 94static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
e561a83b 98static int idle_timeout = 0;
01bd7564 99module_param(idle_timeout, int, 0);
e561a83b 100MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
cd28ab6a
SH		 129 { 0 }
130};
793b883e 131
cd28ab6a
SH		 132MODULE_DEVICE_TABLE(pci, sky2_id_table);
133
134/* Avoid conditionals by using array */
135static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
136static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 137static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 138
92f965e8
SH		 139/* This driver supports yukon2 chipset only */
140static const char *yukon2_name[] = {
141 "XL", /* 0xb3 */
142 "EC Ultra", /* 0xb4 */
143 "UNKNOWN", /* 0xb5 */
144 "EC", /* 0xb6 */
145 "FE", /* 0xb7 */
793b883e
SH		 146};
147
793b883e 148/* Access to external PHY */
ef743d33 149static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 150{
151 int i;
152
153 gma_write16(hw, port, GM_SMI_DATA, val);
154 gma_write16(hw, port, GM_SMI_CTRL,
155 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
156
157 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 158 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 159 return 0;
793b883e 160 udelay(1);
cd28ab6a 161 }
ef743d33 162
793b883e 163 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 164 return -ETIMEDOUT;
cd28ab6a
SH		 165}
166
ef743d33 167static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 168{
169 int i;
170
793b883e 171 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 172 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
173
174 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 175 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
176 *val = gma_read16(hw, port, GM_SMI_DATA);
177 return 0;
178 }
179
793b883e 180 udelay(1);
cd28ab6a
SH		 181 }
182
ef743d33
SH		 183 return -ETIMEDOUT;
184}
185
186static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
187{
188 u16 v;
189
190 if (__gm_phy_read(hw, port, reg, &v) != 0)
191 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
192 return v;
cd28ab6a
SH		 193}
194
5afa0a9c 195
ae306cca
SH		 196static void sky2_power_on(struct sky2_hw *hw)
197{
198 /* switch power to VCC (WA for VAUX problem) */
199 sky2_write8(hw, B0_POWER_CTRL,
200 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 201
ae306cca
SH		 202 /* disable Core Clock Division, */
203 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 204
ae306cca
SH		 205 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
206 /* enable bits are inverted */
207 sky2_write8(hw, B2_Y2_CLK_GATE,
208 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
209 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
210 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
211 else
212 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 213
ae306cca
SH		 214 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
215 u32 reg1;
5afa0a9c 216
ae306cca
SH		 217 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
218 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
219 reg1 &= P_ASPM_CONTROL_MSK;
220 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
221 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
5afa0a9c 222 }
ae306cca 223}
5afa0a9c 224
ae306cca
SH		 225static void sky2_power_aux(struct sky2_hw *hw)
226{
227 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
228 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
229 else
230 /* enable bits are inverted */
231 sky2_write8(hw, B2_Y2_CLK_GATE,
232 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
233 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
234 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
235
236 /* switch power to VAUX */
237 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
238 sky2_write8(hw, B0_POWER_CTRL,
239 (PC_VAUX_ENA | PC_VCC_ENA |
240 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 241}
242
d3bcfbeb 243static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 244{
245 u16 reg;
246
247 /* disable all GMAC IRQ's */
248 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
249 /* disable PHY IRQs */
250 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 251
cd28ab6a
SH		 252 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
253 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
254 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
255 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
256
257 reg = gma_read16(hw, port, GM_RX_CTRL);
258 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
259 gma_write16(hw, port, GM_RX_CTRL, reg);
260}
261
16ad91e1
SH		 262/* flow control to advertise bits */
263static const u16 copper_fc_adv[] = {
264 [FC_NONE] = 0,
265 [FC_TX] = PHY_M_AN_ASP,
266 [FC_RX] = PHY_M_AN_PC,
267 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
268};
269
270/* flow control to advertise bits when using 1000BaseX */
271static const u16 fiber_fc_adv[] = {
272 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
273 [FC_TX] = PHY_M_P_ASYM_MD_X,
274 [FC_RX] = PHY_M_P_SYM_MD_X,
275 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
276};
277
278/* flow control to GMA disable bits */
279static const u16 gm_fc_disable[] = {
280 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
281 [FC_TX] = GM_GPCR_FC_RX_DIS,
282 [FC_RX] = GM_GPCR_FC_TX_DIS,
283 [FC_BOTH] = 0,
284};
285
286
cd28ab6a
SH		 287static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
288{
289 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 290 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 291
ed6d32c7 292 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 293 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 294 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
295
296 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 297 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 298 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
299
300 if (hw->chip_id == CHIP_ID_YUKON_EC)
301 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
302 else
303 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
304
305 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
306 }
307
308 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 309 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 310 if (hw->chip_id == CHIP_ID_YUKON_FE) {
311 /* enable automatic crossover */
312 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
313 } else {
314 /* disable energy detect */
315 ctrl &= ~PHY_M_PC_EN_DET_MSK;
316
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
319
320 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 321 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 322 ctrl &= ~PHY_M_PC_DSC_MSK;
323 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
324 }
325 }
cd28ab6a
SH		 326 } else {
327 /* workaround for deviation #4.88 (CRC errors) */
328 /* disable Automatic Crossover */
329
330 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 331 }
cd28ab6a 332
b89165f2
SH		 333 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
334
335 /* special setup for PHY 88E1112 Fiber */
336 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
337 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 338
b89165f2
SH		 339 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
340 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
341 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
342 ctrl &= ~PHY_M_MAC_MD_MSK;
343 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
345
346 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 347 /* select page 1 to access Fiber registers */
348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 349
350 /* for SFP-module set SIGDET polarity to low */
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 ctrl |= PHY_M_FIB_SIGD_POL;
353 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 354 }
b89165f2
SH		 355
356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 357 }
358
7800fddc 359 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 360 ct1000 = 0;
361 adv = PHY_AN_CSMA;
2eaba1a2 362 reg = 0;
cd28ab6a
SH		 363
364 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 365 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 366 if (sky2->advertising & ADVERTISED_1000baseT_Full)
367 ct1000 |= PHY_M_1000C_AFD;
368 if (sky2->advertising & ADVERTISED_1000baseT_Half)
369 ct1000 |= PHY_M_1000C_AHD;
370 if (sky2->advertising & ADVERTISED_100baseT_Full)
371 adv |= PHY_M_AN_100_FD;
372 if (sky2->advertising & ADVERTISED_100baseT_Half)
373 adv |= PHY_M_AN_100_HD;
374 if (sky2->advertising & ADVERTISED_10baseT_Full)
375 adv |= PHY_M_AN_10_FD;
376 if (sky2->advertising & ADVERTISED_10baseT_Half)
377 adv |= PHY_M_AN_10_HD;
709c6e7b 378
16ad91e1 379 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 380 } else { /* special defines for FIBER (88E1040S only) */
381 if (sky2->advertising & ADVERTISED_1000baseT_Full)
382 adv |= PHY_M_AN_1000X_AFD;
383 if (sky2->advertising & ADVERTISED_1000baseT_Half)
384 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 385
16ad91e1 386 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 387 }
cd28ab6a
SH		 388
389 /* Restart Auto-negotiation */
390 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
391 } else {
392 /* forced speed/duplex settings */
393 ct1000 = PHY_M_1000C_MSE;
394
2eaba1a2
SH		 395 /* Disable auto update for duplex flow control and speed */
396 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 397
398 switch (sky2->speed) {
399 case SPEED_1000:
400 ctrl |= PHY_CT_SP1000;
2eaba1a2 401 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 402 break;
403 case SPEED_100:
404 ctrl |= PHY_CT_SP100;
2eaba1a2 405 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 406 break;
407 }
408
2eaba1a2
SH		 409 if (sky2->duplex == DUPLEX_FULL) {
410 reg |= GM_GPCR_DUP_FULL;
411 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 412 } else if (sky2->speed < SPEED_1000)
413 sky2->flow_mode = FC_NONE;
2eaba1a2 414
2eaba1a2 415
16ad91e1 416 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 417
418 /* Forward pause packets to GMAC? */
16ad91e1 419 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 420 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
421 else
422 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 423 }
424
2eaba1a2
SH		 425 gma_write16(hw, port, GM_GP_CTRL, reg);
426
cd28ab6a
SH		 427 if (hw->chip_id != CHIP_ID_YUKON_FE)
428 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
429
430 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
431 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
432
433 /* Setup Phy LED's */
434 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
435 ledover = 0;
436
437 switch (hw->chip_id) {
438 case CHIP_ID_YUKON_FE:
439 /* on 88E3082 these bits are at 11..9 (shifted left) */
440 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
441
442 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
443
444 /* delete ACT LED control bits */
445 ctrl &= ~PHY_M_FELP_LED1_MSK;
446 /* change ACT LED control to blink mode */
447 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
448 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
449 break;
450
451 case CHIP_ID_YUKON_XL:
793b883e 452 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 453
454 /* select page 3 to access LED control register */
455 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
456
457 /* set LED Function Control register */
ed6d32c7
SH		 458 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
459 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
460 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
461 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
462 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 463
464 /* set Polarity Control register */
465 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 466 (PHY_M_POLC_LS1_P_MIX(4) |
467 PHY_M_POLC_IS0_P_MIX(4) |
468 PHY_M_POLC_LOS_CTRL(2) |
469 PHY_M_POLC_INIT_CTRL(2) |
470 PHY_M_POLC_STA1_CTRL(2) |
471 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 472
473 /* restore page register */
793b883e 474 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 475 break;
ed6d32c7
SH		 476 case CHIP_ID_YUKON_EC_U:
477 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
478
479 /* select page 3 to access LED control register */
480 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
481
482 /* set LED Function Control register */
483 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
484 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
485 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
486 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
487 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
488
489 /* set Blink Rate in LED Timer Control Register */
490 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
491 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
492 /* restore page register */
493 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
494 break;
cd28ab6a
SH		 495
496 default:
497 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
498 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
499 /* turn off the Rx LED (LED_RX) */
0efdf262 500 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 501 }
502
ed6d32c7 503 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 504 /* apply fixes in PHY AFE */
ed6d32c7
SH		 505 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
506 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
507
977bdf06 508 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 509 gm_phy_write(hw, port, 0x18, 0xaa99);
510 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 511
977bdf06 512 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 513 gm_phy_write(hw, port, 0x18, 0xa204);
514 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 515
516 /* set page register to 0 */
ed6d32c7 517 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 518 } else {
519 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 520
977bdf06
SH		 521 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
522 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 523 ledover |= PHY_M_LED_MO_100;
977bdf06 524 }
cd28ab6a 525
977bdf06
SH		 526 if (ledover)
527 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
528
529 }
2eaba1a2 530
d571b694 531 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 532 if (sky2->autoneg == AUTONEG_ENABLE)
533 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
534 else
535 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
536}
537
d3bcfbeb
SH		 538static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
539{
540 u32 reg1;
541 static const u32 phy_power[]
542 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
543
544 /* looks like this XL is back asswards .. */
545 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
546 onoff = !onoff;
547
aed2cec4 548 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 549 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 550 if (onoff)
551 /* Turn off phy power saving */
552 reg1 &= ~phy_power[port];
553 else
554 reg1 |= phy_power[port];
555
556 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 557 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 558 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 559 udelay(100);
560}
561
1b537565
SH		 562/* Force a renegotiation */
563static void sky2_phy_reinit(struct sky2_port *sky2)
564{
e07b1aa8 565 spin_lock_bh(&sky2->phy_lock);
1b537565 566 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 567 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 568}
569
e3173832
SH		 570/* Put device in state to listen for Wake On Lan */
571static void sky2_wol_init(struct sky2_port *sky2)
572{
573 struct sky2_hw *hw = sky2->hw;
574 unsigned port = sky2->port;
575 enum flow_control save_mode;
576 u16 ctrl;
577 u32 reg1;
578
579 /* Bring hardware out of reset */
580 sky2_write16(hw, B0_CTST, CS_RST_CLR);
581 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
582
583 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
584 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
585
586 /* Force to 10/100
587 * sky2_reset will re-enable on resume
588 */
589 save_mode = sky2->flow_mode;
590 ctrl = sky2->advertising;
591
592 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
593 sky2->flow_mode = FC_NONE;
594 sky2_phy_power(hw, port, 1);
595 sky2_phy_reinit(sky2);
596
597 sky2->flow_mode = save_mode;
598 sky2->advertising = ctrl;
599
600 /* Set GMAC to no flow control and auto update for speed/duplex */
601 gma_write16(hw, port, GM_GP_CTRL,
602 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
603 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
604
605 /* Set WOL address */
606 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
607 sky2->netdev->dev_addr, ETH_ALEN);
608
609 /* Turn on appropriate WOL control bits */
610 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
611 ctrl = 0;
612 if (sky2->wol & WAKE_PHY)
613 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
614 else
615 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
616
617 if (sky2->wol & WAKE_MAGIC)
618 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
619 else
620 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
621
622 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
623 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
624
625 /* Turn on legacy PCI-Express PME mode */
626 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
627 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
628 reg1 |= PCI_Y2_PME_LEGACY;
629 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
630 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
631
632 /* block receiver */
633 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
634
635}
636
cd28ab6a
SH		 637static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
638{
639 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
640 u16 reg;
641 int i;
642 const u8 *addr = hw->dev[port]->dev_addr;
643
42eeea01
SH		 644 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
645 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 646
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
648
793b883e 649 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 650 /* WA DEV_472 -- looks like crossed wires on port 2 */
651 /* clear GMAC 1 Control reset */
652 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
653 do {
654 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
655 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
656 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
657 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
658 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
659 }
660
793b883e 661 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 662
2eaba1a2
SH		 663 /* Enable Transmit FIFO Underrun */
664 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
665
e07b1aa8 666 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 667 sky2_phy_init(hw, port);
e07b1aa8 668 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 669
670 /* MIB clear */
671 reg = gma_read16(hw, port, GM_PHY_ADDR);
672 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
673
43f2f104
SH		 674 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
675 gma_read16(hw, port, i);
cd28ab6a
SH		 676 gma_write16(hw, port, GM_PHY_ADDR, reg);
677
678 /* transmit control */
679 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
680
681 /* receive control reg: unicast + multicast + no FCS */
682 gma_write16(hw, port, GM_RX_CTRL,
793b883e 683 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 684
685 /* transmit flow control */
686 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
687
688 /* transmit parameter */
689 gma_write16(hw, port, GM_TX_PARAM,
690 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
691 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
692 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
693 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
694
695 /* serial mode register */
696 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 697 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 698
6b1a3aef 699 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 700 reg |= GM_SMOD_JUMBO_ENA;
701
702 gma_write16(hw, port, GM_SERIAL_MODE, reg);
703
cd28ab6a
SH		 704 /* virtual address for data */
705 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
706
793b883e
SH		 707 /* physical address: used for pause frames */
708 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
709
710 /* ignore counter overflows */
cd28ab6a
SH		 711 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
712 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
713 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
714
715 /* Configure Rx MAC FIFO */
716 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 717 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
718 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 719
d571b694 720 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 721 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 722
8df9a876
SH		 723 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
724 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 725
726 /* Configure Tx MAC FIFO */
727 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
728 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 729
730 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
8df9a876 731 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0
SH		 732 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
733 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
734 /* set Tx GMAC FIFO Almost Empty Threshold */
735 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
736 /* Disable Store & Forward mode for TX */
737 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
738 }
739 }
740
cd28ab6a
SH		 741}
742
67712901
SH		 743/* Assign Ram Buffer allocation to queue */
744static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 745{
67712901
SH		 746 u32 end;
747
748 /* convert from K bytes to qwords used for hw register */
749 start *= 1024/8;
750 space *= 1024/8;
751 end = start + space - 1;
793b883e 752
cd28ab6a
SH		 753 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
754 sky2_write32(hw, RB_ADDR(q, RB_START), start);
755 sky2_write32(hw, RB_ADDR(q, RB_END), end);
756 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
757 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
758
759 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 760 u32 tp = space - space/4;
793b883e 761
1c28f6ba
SH		 762 /* On receive queue's set the thresholds
763 * give receiver priority when > 3/4 full
764 * send pause when down to 2K
765 */
766 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
767 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 768
1c28f6ba
SH		 769 tp = space - 2048/8;
770 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
771 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 772 } else {
773 /* Enable store & forward on Tx queue's because
774 * Tx FIFO is only 1K on Yukon
775 */
776 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
777 }
778
779 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 780 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 781}
782
cd28ab6a 783/* Setup Bus Memory Interface */
af4ed7e6 784static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 785{
786 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
787 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
788 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 789 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 790}
791
cd28ab6a
SH		 792/* Setup prefetch unit registers. This is the interface between
793 * hardware and driver list elements
794 */
8cc048e3 795static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 796 u64 addr, u32 last)
797{
cd28ab6a
SH		 798 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
799 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
800 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
801 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
802 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
803 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 804
805 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 806}
807
793b883e
SH		 808static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
809{
810 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
811
cb5d9547 812 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 813 le->ctrl = 0;
793b883e
SH		 814 return le;
815}
cd28ab6a 816
291ea614
SH		 817static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
818 struct sky2_tx_le *le)
819{
820 return sky2->tx_ring + (le - sky2->tx_le);
821}
822
290d4de5
SH		 823/* Update chip's next pointer */
824static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 825{
98232f85 826 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 827 wmb();
98232f85
SH		 828 sky2_write16(hw, q, idx);
829 sky2_read16(hw, q);
cd28ab6a
SH		 830}
831
793b883e 832
cd28ab6a
SH		 833static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
834{
835 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 836 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 837 le->ctrl = 0;
cd28ab6a
SH		 838 return le;
839}
840
a018e330
SH		 841/* Return high part of DMA address (could be 32 or 64 bit) */
842static inline u32 high32(dma_addr_t a)
843{
a036119f 844 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 845}
846
14d0263f
SH		 847/* Build description to hardware for one receive segment */
848static void sky2_rx_add(struct sky2_port *sky2, u8 op,
849 dma_addr_t map, unsigned len)
cd28ab6a
SH		 850{
851 struct sky2_rx_le *le;
734d1868 852 u32 hi = high32(map);
cd28ab6a 853
793b883e 854 if (sky2->rx_addr64 != hi) {
cd28ab6a 855 le = sky2_next_rx(sky2);
793b883e 856 le->addr = cpu_to_le32(hi);
cd28ab6a 857 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 858 sky2->rx_addr64 = high32(map + len);
cd28ab6a 859 }
793b883e 860
cd28ab6a 861 le = sky2_next_rx(sky2);
734d1868
SH		 862 le->addr = cpu_to_le32((u32) map);
863 le->length = cpu_to_le16(len);
14d0263f 864 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 865}
866
14d0263f
SH		 867/* Build description to hardware for one possibly fragmented skb */
868static void sky2_rx_submit(struct sky2_port *sky2,
869 const struct rx_ring_info *re)
870{
871 int i;
872
873 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
874
875 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
876 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
877}
878
879
880static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
881 unsigned size)
882{
883 struct sk_buff *skb = re->skb;
884 int i;
885
886 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
887 pci_unmap_len_set(re, data_size, size);
888
889 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
890 re->frag_addr[i] = pci_map_page(pdev,
891 skb_shinfo(skb)->frags[i].page,
892 skb_shinfo(skb)->frags[i].page_offset,
893 skb_shinfo(skb)->frags[i].size,
894 PCI_DMA_FROMDEVICE);
895}
896
897static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
898{
899 struct sk_buff *skb = re->skb;
900 int i;
901
902 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
903 PCI_DMA_FROMDEVICE);
904
905 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
906 pci_unmap_page(pdev, re->frag_addr[i],
907 skb_shinfo(skb)->frags[i].size,
908 PCI_DMA_FROMDEVICE);
909}
793b883e 910
cd28ab6a
SH		 911/* Tell chip where to start receive checksum.
912 * Actually has two checksums, but set both same to avoid possible byte
913 * order problems.
914 */
793b883e 915static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 916{
917 struct sky2_rx_le *le;
918
cd28ab6a 919 le = sky2_next_rx(sky2);
f65b138c 920 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 921 le->ctrl = 0;
922 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 923
793b883e
SH		 924 sky2_write32(sky2->hw,
925 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
926 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 927
928}
929
6b1a3aef
SH		 930/*
931 * The RX Stop command will not work for Yukon-2 if the BMU does not
932 * reach the end of packet and since we can't make sure that we have
933 * incoming data, we must reset the BMU while it is not doing a DMA
934 * transfer. Since it is possible that the RX path is still active,
935 * the RX RAM buffer will be stopped first, so any possible incoming
936 * data will not trigger a DMA. After the RAM buffer is stopped, the
937 * BMU is polled until any DMA in progress is ended and only then it
938 * will be reset.
939 */
940static void sky2_rx_stop(struct sky2_port *sky2)
941{
942 struct sky2_hw *hw = sky2->hw;
943 unsigned rxq = rxqaddr[sky2->port];
944 int i;
945
946 /* disable the RAM Buffer receive queue */
947 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
948
949 for (i = 0; i < 0xffff; i++)
950 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
951 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
952 goto stopped;
953
954 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
955 sky2->netdev->name);
956stopped:
957 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
958
959 /* reset the Rx prefetch unit */
960 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
961}
793b883e 962
d571b694 963/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 964static void sky2_rx_clean(struct sky2_port *sky2)
965{
966 unsigned i;
967
968 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 969 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 970 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 971
972 if (re->skb) {
14d0263f 973 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 974 kfree_skb(re->skb);
975 re->skb = NULL;
976 }
977 }
978}
979
ef743d33
SH		 980/* Basic MII support */
981static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
982{
983 struct mii_ioctl_data *data = if_mii(ifr);
984 struct sky2_port *sky2 = netdev_priv(dev);
985 struct sky2_hw *hw = sky2->hw;
986 int err = -EOPNOTSUPP;
987
988 if (!netif_running(dev))
989 return -ENODEV; /* Phy still in reset */
990
d89e1343 991 switch (cmd) {
ef743d33
SH		 992 case SIOCGMIIPHY:
993 data->phy_id = PHY_ADDR_MARV;
994
995 /* fallthru */
996 case SIOCGMIIREG: {
997 u16 val = 0;
91c86df5 998
e07b1aa8 999 spin_lock_bh(&sky2->phy_lock);
ef743d33 1000 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1001 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1002
ef743d33
SH		 1003 data->val_out = val;
1004 break;
1005 }
1006
1007 case SIOCSMIIREG:
1008 if (!capable(CAP_NET_ADMIN))
1009 return -EPERM;
1010
e07b1aa8 1011 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1012 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1013 data->val_in);
e07b1aa8 1014 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1015 break;
1016 }
1017 return err;
1018}
1019
d1f13708
SH		 1020#ifdef SKY2_VLAN_TAG_USED
1021static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1022{
1023 struct sky2_port *sky2 = netdev_priv(dev);
1024 struct sky2_hw *hw = sky2->hw;
1025 u16 port = sky2->port;
d1f13708 1026
2bb8c262 1027 netif_tx_lock_bh(dev);
d1f13708
SH		 1028
1029 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1030 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1031 sky2->vlgrp = grp;
1032
2bb8c262 1033 netif_tx_unlock_bh(dev);
d1f13708
SH		 1034}
1035
1036static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1037{
1038 struct sky2_port *sky2 = netdev_priv(dev);
1039 struct sky2_hw *hw = sky2->hw;
1040 u16 port = sky2->port;
d1f13708 1041
2bb8c262 1042 netif_tx_lock_bh(dev);
d1f13708
SH		 1043
1044 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1045 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1046 if (sky2->vlgrp)
1047 sky2->vlgrp->vlan_devices[vid] = NULL;
1048
2bb8c262 1049 netif_tx_unlock_bh(dev);
d1f13708
SH		 1050}
1051#endif
1052
82788c7a 1053/*
14d0263f
SH		 1054 * Allocate an skb for receiving. If the MTU is large enough
1055 * make the skb non-linear with a fragment list of pages.
1056 *
82788c7a
SH		 1057 * It appears the hardware has a bug in the FIFO logic that
1058 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1059 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1060 * aligned except if slab debugging is enabled.
82788c7a 1061 */
14d0263f 1062static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1063{
1064 struct sk_buff *skb;
14d0263f
SH		 1065 unsigned long p;
1066 int i;
82788c7a 1067
14d0263f
SH		 1068 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1069 if (!skb)
1070 goto nomem;
1071
1072 p = (unsigned long) skb->data;
1073 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1074
1075 for (i = 0; i < sky2->rx_nfrags; i++) {
1076 struct page *page = alloc_page(GFP_ATOMIC);
1077
1078 if (!page)
1079 goto free_partial;
1080 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1081 }
1082
1083 return skb;
14d0263f
SH		 1084free_partial:
1085 kfree_skb(skb);
1086nomem:
1087 return NULL;
82788c7a
SH		 1088}
1089
cd28ab6a
SH		 1090/*
1091 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1092 * Normal case this ends up creating one list element for skb
1093 * in the receive ring. Worst case if using large MTU and each
1094 * allocation falls on a different 64 bit region, that results
1095 * in 6 list elements per ring entry.
1096 * One element is used for checksum enable/disable, and one
1097 * extra to avoid wrap.
cd28ab6a 1098 */
6b1a3aef 1099static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1100{
6b1a3aef 1101 struct sky2_hw *hw = sky2->hw;
14d0263f 1102 struct rx_ring_info *re;
6b1a3aef 1103 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1104 unsigned i, size, space, thresh;
cd28ab6a 1105
6b1a3aef 1106 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1107 sky2_qset(hw, rxq);
977bdf06 1108
c3905bc4
SH		 1109 /* On PCI express lowering the watermark gives better performance */
1110 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1111 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1112
1113 /* These chips have no ram buffer?
1114 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1115 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1116 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1117 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
977bdf06 1118 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
977bdf06 1119
6b1a3aef
SH		 1120 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1121
1122 rx_set_checksum(sky2);
14d0263f
SH		 1123
1124 /* Space needed for frame data + headers rounded up */
1125 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1126 + 8;
1127
1128 /* Stopping point for hardware truncation */
1129 thresh = (size - 8) / sizeof(u32);
1130
1131 /* Account for overhead of skb - to avoid order > 0 allocation */
1132 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1133 + sizeof(struct skb_shared_info);
1134
1135 sky2->rx_nfrags = space >> PAGE_SHIFT;
1136 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1137
1138 if (sky2->rx_nfrags != 0) {
1139 /* Compute residue after pages */
1140 space = sky2->rx_nfrags << PAGE_SHIFT;
1141
1142 if (space < size)
1143 size -= space;
1144 else
1145 size = 0;
1146
1147 /* Optimize to handle small packets and headers */
1148 if (size < copybreak)
1149 size = copybreak;
1150 if (size < ETH_HLEN)
1151 size = ETH_HLEN;
1152 }
1153 sky2->rx_data_size = size;
1154
1155 /* Fill Rx ring */
793b883e 1156 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1157 re = sky2->rx_ring + i;
cd28ab6a 1158
14d0263f 1159 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1160 if (!re->skb)
1161 goto nomem;
1162
14d0263f
SH		 1163 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1164 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1165 }
1166
a1433ac4
SH		 1167 /*
1168 * The receiver hangs if it receives frames larger than the
1169 * packet buffer. As a workaround, truncate oversize frames, but
1170 * the register is limited to 9 bits, so if you do frames > 2052
1171 * you better get the MTU right!
1172 */
a1433ac4
SH		 1173 if (thresh > 0x1ff)
1174 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1175 else {
1176 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1177 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1178 }
1179
6b1a3aef
SH		 1180 /* Tell chip about available buffers */
1181 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1182 return 0;
1183nomem:
1184 sky2_rx_clean(sky2);
1185 return -ENOMEM;
1186}
1187
1188/* Bring up network interface. */
1189static int sky2_up(struct net_device *dev)
1190{
1191 struct sky2_port *sky2 = netdev_priv(dev);
1192 struct sky2_hw *hw = sky2->hw;
1193 unsigned port = sky2->port;
67712901 1194 u32 ramsize, imask;
ee7abb04 1195 int cap, err = -ENOMEM;
843a46f4 1196 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1197
ee7abb04
SH		 1198 /*
1199 * On dual port PCI-X card, there is an problem where status
1200 * can be received out of order due to split transactions
843a46f4 1201 */
ee7abb04
SH		 1202 if (otherdev && netif_running(otherdev) &&
1203 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1204 struct sky2_port *osky2 = netdev_priv(otherdev);
1205 u16 cmd;
1206
1207 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1208 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1209 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1210
1211 sky2->rx_csum = 0;
1212 osky2->rx_csum = 0;
1213 }
843a46f4 1214
cd28ab6a
SH		 1215 if (netif_msg_ifup(sky2))
1216 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1217
1218 /* must be power of 2 */
1219 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1220 TX_RING_SIZE *
1221 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1222 &sky2->tx_le_map);
1223 if (!sky2->tx_le)
1224 goto err_out;
1225
6cdbbdf3 1226 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1227 GFP_KERNEL);
1228 if (!sky2->tx_ring)
1229 goto err_out;
1230 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1231
1232 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1233 &sky2->rx_le_map);
1234 if (!sky2->rx_le)
1235 goto err_out;
1236 memset(sky2->rx_le, 0, RX_LE_BYTES);
1237
291ea614 1238 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1239 GFP_KERNEL);
1240 if (!sky2->rx_ring)
1241 goto err_out;
1242
d3bcfbeb
SH		 1243 sky2_phy_power(hw, port, 1);
1244
cd28ab6a
SH		 1245 sky2_mac_init(hw, port);
1246
67712901
SH		 1247 /* Register is number of 4K blocks on internal RAM buffer. */
1248 ramsize = sky2_read8(hw, B2_E_0) * 4;
1249 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1250
67712901
SH		 1251 if (ramsize > 0) {
1252 u32 rxspace;
cd28ab6a 1253
67712901
SH		 1254 if (ramsize < 16)
1255 rxspace = ramsize / 2;
1256 else
1257 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1258
67712901
SH		 1259 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1260 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1261
1262 /* Make sure SyncQ is disabled */
1263 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1264 RB_RST_SET);
1265 }
793b883e 1266
af4ed7e6 1267 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1268
977bdf06 1269 /* Set almost empty threshold */
c2716fb4
SH		 1270 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1271 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1272 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1273
6b1a3aef
SH		 1274 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1275 TX_RING_SIZE - 1);
cd28ab6a 1276
6b1a3aef 1277 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1278 if (err)
1279 goto err_out;
1280
cd28ab6a 1281 /* Enable interrupts from phy/mac for port */
e07b1aa8 1282 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1283 imask |= portirq_msk[port];
e07b1aa8
SH		 1284 sky2_write32(hw, B0_IMSK, imask);
1285
cd28ab6a
SH		 1286 return 0;
1287
1288err_out:
1b537565 1289 if (sky2->rx_le) {
cd28ab6a
SH		 1290 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1291 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1292 sky2->rx_le = NULL;
1293 }
1294 if (sky2->tx_le) {
cd28ab6a
SH		 1295 pci_free_consistent(hw->pdev,
1296 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1297 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1298 sky2->tx_le = NULL;
1299 }
1300 kfree(sky2->tx_ring);
1301 kfree(sky2->rx_ring);
cd28ab6a 1302
1b537565
SH		 1303 sky2->tx_ring = NULL;
1304 sky2->rx_ring = NULL;
cd28ab6a
SH		 1305 return err;
1306}
1307
793b883e
SH		 1308/* Modular subtraction in ring */
1309static inline int tx_dist(unsigned tail, unsigned head)
1310{
cb5d9547 1311 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1312}
cd28ab6a 1313
793b883e
SH		 1314/* Number of list elements available for next tx */
1315static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1316{
793b883e 1317 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1318}
1319
793b883e 1320/* Estimate of number of transmit list elements required */
28bd181a 1321static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1322{
793b883e
SH		 1323 unsigned count;
1324
1325 count = sizeof(dma_addr_t) / sizeof(u32);
1326 count += skb_shinfo(skb)->nr_frags * count;
1327
89114afd 1328 if (skb_is_gso(skb))
793b883e
SH		 1329 ++count;
1330
84fa7933 1331 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1332 ++count;
1333
1334 return count;
cd28ab6a
SH		 1335}
1336
793b883e
SH		 1337/*
1338 * Put one packet in ring for transmit.
1339 * A single packet can generate multiple list elements, and
1340 * the number of ring elements will probably be less than the number
1341 * of list elements used.
1342 */
cd28ab6a
SH		 1343static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1344{
1345 struct sky2_port *sky2 = netdev_priv(dev);
1346 struct sky2_hw *hw = sky2->hw;
d1f13708 1347 struct sky2_tx_le *le = NULL;
6cdbbdf3 1348 struct tx_ring_info *re;
cd28ab6a
SH		 1349 unsigned i, len;
1350 dma_addr_t mapping;
1351 u32 addr64;
1352 u16 mss;
1353 u8 ctrl;
1354
2bb8c262
SH		 1355 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1356 return NETDEV_TX_BUSY;
cd28ab6a 1357
793b883e 1358 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1359 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1360 dev->name, sky2->tx_prod, skb->len);
1361
cd28ab6a
SH		 1362 len = skb_headlen(skb);
1363 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1364 addr64 = high32(mapping);
793b883e 1365
a018e330
SH		 1366 /* Send high bits if changed or crosses boundary */
1367 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1368 le = get_tx_le(sky2);
f65b138c 1369 le->addr = cpu_to_le32(addr64);
793b883e 1370 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1371 sky2->tx_addr64 = high32(mapping + len);
793b883e 1372 }
cd28ab6a
SH		 1373
1374 /* Check for TCP Segmentation Offload */
7967168c 1375 mss = skb_shinfo(skb)->gso_size;
793b883e 1376 if (mss != 0) {
cd28ab6a
SH		 1377 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1378 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1379 mss += ETH_HLEN;
1380
e07560cd
SH		 1381 if (mss != sky2->tx_last_mss) {
1382 le = get_tx_le(sky2);
f65b138c 1383 le->addr = cpu_to_le32(mss);
e07560cd 1384 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1385 sky2->tx_last_mss = mss;
1386 }
cd28ab6a
SH		 1387 }
1388
cd28ab6a 1389 ctrl = 0;
d1f13708
SH		 1390#ifdef SKY2_VLAN_TAG_USED
1391 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1392 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1393 if (!le) {
1394 le = get_tx_le(sky2);
f65b138c 1395 le->addr = 0;
d1f13708 1396 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1397 } else
1398 le->opcode |= OP_VLAN;
1399 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1400 ctrl |= INS_VLAN;
1401 }
1402#endif
1403
1404 /* Handle TCP checksum offload */
84fa7933 1405 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1406 unsigned offset = skb->h.raw - skb->data;
1407 u32 tcpsum;
1408
1409 tcpsum = offset << 16; /* sum start */
ff1dcadb 1410 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a
SH		 1411
1412 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1413 if (skb->nh.iph->protocol == IPPROTO_UDP)
1414 ctrl |= UDPTCP;
1415
f65b138c
SH		 1416 if (tcpsum != sky2->tx_tcpsum) {
1417 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1418
1419 le = get_tx_le(sky2);
f65b138c 1420 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1421 le->length = 0; /* initial checksum value */
1422 le->ctrl = 1; /* one packet */
1423 le->opcode = OP_TCPLISW | HW_OWNER;
1424 }
cd28ab6a
SH		 1425 }
1426
1427 le = get_tx_le(sky2);
f65b138c 1428 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1429 le->length = cpu_to_le16(len);
1430 le->ctrl = ctrl;
793b883e 1431 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1432
291ea614 1433 re = tx_le_re(sky2, le);
cd28ab6a 1434 re->skb = skb;
6cdbbdf3 1435 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1436 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1437
1438 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1439 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1440
1441 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1442 frag->size, PCI_DMA_TODEVICE);
a036119f 1443 addr64 = high32(mapping);
793b883e
SH		 1444 if (addr64 != sky2->tx_addr64) {
1445 le = get_tx_le(sky2);
f65b138c 1446 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1447 le->ctrl = 0;
1448 le->opcode = OP_ADDR64 | HW_OWNER;
1449 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1450 }
1451
1452 le = get_tx_le(sky2);
f65b138c 1453 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1454 le->length = cpu_to_le16(frag->size);
1455 le->ctrl = ctrl;
793b883e 1456 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1457
291ea614
SH		 1458 re = tx_le_re(sky2, le);
1459 re->skb = skb;
1460 pci_unmap_addr_set(re, mapaddr, mapping);
1461 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1462 }
6cdbbdf3 1463
cd28ab6a
SH		 1464 le->ctrl |= EOP;
1465
97bda706
SH		 1466 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1467 netif_stop_queue(dev);
b19666d9 1468
290d4de5 1469 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1470
cd28ab6a
SH		 1471 dev->trans_start = jiffies;
1472 return NETDEV_TX_OK;
1473}
1474
cd28ab6a 1475/*
793b883e
SH		 1476 * Free ring elements from starting at tx_cons until "done"
1477 *
1478 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1479 * buffers so make sure not to free skb to early.
cd28ab6a 1480 */
d11c13e7 1481static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1482{
d11c13e7 1483 struct net_device *dev = sky2->netdev;
af2a58ac 1484 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1485 unsigned idx;
cd28ab6a 1486
0e3ff6aa 1487 BUG_ON(done >= TX_RING_SIZE);
2224795d 1488
291ea614
SH		 1489 for (idx = sky2->tx_cons; idx != done;
1490 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1491 struct sky2_tx_le *le = sky2->tx_le + idx;
1492 struct tx_ring_info *re = sky2->tx_ring + idx;
1493
1494 switch(le->opcode & ~HW_OWNER) {
1495 case OP_LARGESEND:
1496 case OP_PACKET:
1497 pci_unmap_single(pdev,
1498 pci_unmap_addr(re, mapaddr),
1499 pci_unmap_len(re, maplen),
1500 PCI_DMA_TODEVICE);
af2a58ac 1501 break;
291ea614
SH		 1502 case OP_BUFFER:
1503 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1504 pci_unmap_len(re, maplen),
734d1868 1505 PCI_DMA_TODEVICE);
291ea614
SH		 1506 break;
1507 }
1508
1509 if (le->ctrl & EOP) {
1510 if (unlikely(netif_msg_tx_done(sky2)))
1511 printk(KERN_DEBUG "%s: tx done %u\n",
1512 dev->name, idx);
2bf56fe2 1513 sky2->net_stats.tx_packets++;
1514 sky2->net_stats.tx_bytes += re->skb->len;
1515
794b2bd2 1516 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1517 }
1518
291ea614 1519 le->opcode = 0; /* paranoia */
793b883e 1520 }
793b883e 1521
291ea614 1522 sky2->tx_cons = idx;
22e11703 1523 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1524 netif_wake_queue(dev);
cd28ab6a
SH		 1525}
1526
1527/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1528static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1529{
2bb8c262
SH		 1530 struct sky2_port *sky2 = netdev_priv(dev);
1531
1532 netif_tx_lock_bh(dev);
d11c13e7 1533 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1534 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1535}
1536
1537/* Network shutdown */
1538static int sky2_down(struct net_device *dev)
1539{
1540 struct sky2_port *sky2 = netdev_priv(dev);
1541 struct sky2_hw *hw = sky2->hw;
1542 unsigned port = sky2->port;
1543 u16 ctrl;
e07b1aa8 1544 u32 imask;
cd28ab6a 1545
1b537565
SH		 1546 /* Never really got started! */
1547 if (!sky2->tx_le)
1548 return 0;
1549
cd28ab6a
SH		 1550 if (netif_msg_ifdown(sky2))
1551 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1552
018d1c66 1553 /* Stop more packets from being queued */
cd28ab6a
SH		 1554 netif_stop_queue(dev);
1555
ebc646f6
SH		 1556 /* Disable port IRQ */
1557 imask = sky2_read32(hw, B0_IMSK);
1558 imask &= ~portirq_msk[port];
1559 sky2_write32(hw, B0_IMSK, imask);
1560
25d82d7a
SH		 1561 /*
1562 * Both ports share the NAPI poll on port 0, so if necessary undo the
1563 * the disable that is done in dev_close.
1564 */
1565 if (sky2->port == 0 && hw->ports > 1)
1566 netif_poll_enable(dev);
1567
d3bcfbeb 1568 sky2_gmac_reset(hw, port);
793b883e 1569
cd28ab6a
SH		 1570 /* Stop transmitter */
1571 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1572 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1573
1574 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1575 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1576
c2716fb4
SH		 1577 /* WA for dev. #4.209 */
1578 if (hw->chip_id == CHIP_ID_YUKON_EC_U
8df9a876 1579 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
c2716fb4
SH		 1580 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1581 sky2->speed != SPEED_1000 ?
1582 TX_STFW_ENA : TX_STFW_DIS);
1583
cd28ab6a 1584 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1585 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1586 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1587
1588 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1589
1590 /* Workaround shared GMAC reset */
793b883e
SH		 1591 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1592 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1593 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1594
1595 /* Disable Force Sync bit and Enable Alloc bit */
1596 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1597 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1598
1599 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1600 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1601 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1602
1603 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1604 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1605 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1606
1607 /* Reset the Tx prefetch units */
1608 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1609 PREF_UNIT_RST_SET);
1610
1611 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1612
6b1a3aef 1613 sky2_rx_stop(sky2);
cd28ab6a
SH		 1614
1615 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1616 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1617
d3bcfbeb
SH		 1618 sky2_phy_power(hw, port, 0);
1619
d571b694 1620 /* turn off LED's */
cd28ab6a
SH		 1621 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1622
018d1c66
SH		 1623 synchronize_irq(hw->pdev->irq);
1624
2bb8c262 1625 sky2_tx_clean(dev);
cd28ab6a
SH		 1626 sky2_rx_clean(sky2);
1627
1628 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1629 sky2->rx_le, sky2->rx_le_map);
1630 kfree(sky2->rx_ring);
1631
1632 pci_free_consistent(hw->pdev,
1633 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1634 sky2->tx_le, sky2->tx_le_map);
1635 kfree(sky2->tx_ring);
1636
1b537565
SH		 1637 sky2->tx_le = NULL;
1638 sky2->rx_le = NULL;
1639
1640 sky2->rx_ring = NULL;
1641 sky2->tx_ring = NULL;
1642
cd28ab6a
SH		 1643 return 0;
1644}
1645
1646static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1647{
b89165f2 1648 if (!sky2_is_copper(hw))
793b883e
SH		 1649 return SPEED_1000;
1650
cd28ab6a
SH		 1651 if (hw->chip_id == CHIP_ID_YUKON_FE)
1652 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1653
1654 switch (aux & PHY_M_PS_SPEED_MSK) {
1655 case PHY_M_PS_SPEED_1000:
1656 return SPEED_1000;
1657 case PHY_M_PS_SPEED_100:
1658 return SPEED_100;
1659 default:
1660 return SPEED_10;
1661 }
1662}
1663
1664static void sky2_link_up(struct sky2_port *sky2)
1665{
1666 struct sky2_hw *hw = sky2->hw;
1667 unsigned port = sky2->port;
1668 u16 reg;
16ad91e1
SH		 1669 static const char *fc_name[] = {
1670 [FC_NONE] = "none",
1671 [FC_TX] = "tx",
1672 [FC_RX] = "rx",
1673 [FC_BOTH] = "both",
1674 };
cd28ab6a 1675
cd28ab6a 1676 /* enable Rx/Tx */
2eaba1a2 1677 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1678 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1679 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1680
1681 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1682
1683 netif_carrier_on(sky2->netdev);
1684 netif_wake_queue(sky2->netdev);
1685
1686 /* Turn on link LED */
793b883e 1687 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1688 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1689
ed6d32c7 1690 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1691 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1692 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1693
1694 switch(sky2->speed) {
1695 case SPEED_10:
1696 led |= PHY_M_LEDC_INIT_CTRL(7);
1697 break;
1698
1699 case SPEED_100:
1700 led |= PHY_M_LEDC_STA1_CTRL(7);
1701 break;
1702
1703 case SPEED_1000:
1704 led |= PHY_M_LEDC_STA0_CTRL(7);
1705 break;
1706 }
793b883e
SH		 1707
1708 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1709 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1710 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1711 }
1712
cd28ab6a
SH		 1713 if (netif_msg_link(sky2))
1714 printk(KERN_INFO PFX
d571b694 1715 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1716 sky2->netdev->name, sky2->speed,
1717 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1718 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1719}
1720
1721static void sky2_link_down(struct sky2_port *sky2)
1722{
1723 struct sky2_hw *hw = sky2->hw;
1724 unsigned port = sky2->port;
1725 u16 reg;
1726
1727 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1728
1729 reg = gma_read16(hw, port, GM_GP_CTRL);
1730 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1731 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1732
16ad91e1 1733 if (sky2->flow_status == FC_RX) {
cd28ab6a
SH		 1734 /* restore Asymmetric Pause bit */
1735 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1736 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1737 | PHY_M_AN_ASP);
cd28ab6a
SH		 1738 }
1739
cd28ab6a
SH		 1740 netif_carrier_off(sky2->netdev);
1741 netif_stop_queue(sky2->netdev);
1742
1743 /* Turn on link LED */
1744 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1745
1746 if (netif_msg_link(sky2))
1747 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1748
cd28ab6a
SH		 1749 sky2_phy_init(hw, port);
1750}
1751
16ad91e1
SH		 1752static enum flow_control sky2_flow(int rx, int tx)
1753{
1754 if (rx)
1755 return tx ? FC_BOTH : FC_RX;
1756 else
1757 return tx ? FC_TX : FC_NONE;
1758}
1759
793b883e
SH		 1760static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1761{
1762 struct sky2_hw *hw = sky2->hw;
1763 unsigned port = sky2->port;
1764 u16 lpa;
1765
1766 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1767
1768 if (lpa & PHY_M_AN_RF) {
1769 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1770 return -1;
1771 }
1772
793b883e
SH		 1773 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1774 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1775 sky2->netdev->name);
1776 return -1;
1777 }
1778
793b883e 1779 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1780 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e
SH		 1781
1782 /* Pause bits are offset (9..8) */
ed6d32c7 1783 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1784 aux >>= 6;
1785
16ad91e1
SH		 1786 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1787 aux & PHY_M_PS_TX_P_EN);
793b883e 1788
16ad91e1 1789 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2eaba1a2 1790 && hw->chip_id != CHIP_ID_YUKON_EC_U)
16ad91e1 1791 sky2->flow_status = FC_NONE;
2eaba1a2 1792
16ad91e1 1793 if (aux & PHY_M_PS_RX_P_EN)
793b883e
SH		 1794 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1795 else
1796 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1797
1798 return 0;
1799}
cd28ab6a 1800
e07b1aa8
SH		 1801/* Interrupt from PHY */
1802static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1803{
e07b1aa8
SH		 1804 struct net_device *dev = hw->dev[port];
1805 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1806 u16 istatus, phystat;
1807
ebc646f6
SH		 1808 if (!netif_running(dev))
1809 return;
1810
e07b1aa8
SH		 1811 spin_lock(&sky2->phy_lock);
1812 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1813 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1814
cd28ab6a
SH		 1815 if (netif_msg_intr(sky2))
1816 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1817 sky2->netdev->name, istatus, phystat);
1818
2eaba1a2 1819 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1820 if (sky2_autoneg_done(sky2, phystat) == 0)
1821 sky2_link_up(sky2);
1822 goto out;
1823 }
cd28ab6a 1824
793b883e
SH		 1825 if (istatus & PHY_M_IS_LSP_CHANGE)
1826 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1827
793b883e
SH		 1828 if (istatus & PHY_M_IS_DUP_CHANGE)
1829 sky2->duplex =
1830 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1831
793b883e
SH		 1832 if (istatus & PHY_M_IS_LST_CHANGE) {
1833 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1834 sky2_link_up(sky2);
793b883e
SH		 1835 else
1836 sky2_link_down(sky2);
cd28ab6a 1837 }
793b883e 1838out:
e07b1aa8 1839 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1840}
1841
302d1252 1842
62335ab0 1843/* Transmit timeout is only called if we are running, carrier is up
302d1252 1844 * and tx queue is full (stopped).
62335ab0 1845 * Called with netif_tx_lock held.
302d1252 1846 */
cd28ab6a
SH		 1847static void sky2_tx_timeout(struct net_device *dev)
1848{
1849 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1850 struct sky2_hw *hw = sky2->hw;
62335ab0 1851 u32 imask;
cd28ab6a
SH		 1852
1853 if (netif_msg_timer(sky2))
1854 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1855
8f24664d 1856 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1857 dev->name, sky2->tx_cons, sky2->tx_prod,
1858 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1859 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1860
62335ab0
SH		 1861 imask = sky2_read32(hw, B0_IMSK); /* block IRQ in hw */
1862 sky2_write32(hw, B0_IMSK, 0);
1863 sky2_read32(hw, B0_IMSK);
8f24664d 1864
62335ab0
SH		 1865 netif_poll_disable(hw->dev[0]); /* stop NAPI poll */
1866 synchronize_irq(hw->pdev->irq);
8cc048e3 1867
62335ab0
SH		 1868 netif_start_queue(dev); /* don't wakeup during flush */
1869 sky2_tx_complete(sky2, sky2->tx_prod); /* Flush transmit queue */
8f24664d 1870
62335ab0 1871 sky2_write32(hw, B0_IMSK, imask);
8f24664d 1872
62335ab0 1873 sky2_phy_reinit(sky2); /* this clears flow control etc */
cd28ab6a
SH		 1874}
1875
1876static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1877{
6b1a3aef
SH		 1878 struct sky2_port *sky2 = netdev_priv(dev);
1879 struct sky2_hw *hw = sky2->hw;
1880 int err;
1881 u16 ctl, mode;
e07b1aa8 1882 u32 imask;
cd28ab6a
SH		 1883
1884 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1885 return -EINVAL;
1886
4a50a876 1887 /* TSO on Yukon Ultra and MTU > 1500 not supported */
5a5b1ea0 1888 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
4a50a876 1889 dev->features &= ~NETIF_F_TSO;
5a5b1ea0 1890
6b1a3aef
SH		 1891 if (!netif_running(dev)) {
1892 dev->mtu = new_mtu;
1893 return 0;
1894 }
1895
e07b1aa8 1896 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1897 sky2_write32(hw, B0_IMSK, 0);
1898
018d1c66
SH		 1899 dev->trans_start = jiffies; /* prevent tx timeout */
1900 netif_stop_queue(dev);
1901 netif_poll_disable(hw->dev[0]);
1902
e07b1aa8
SH		 1903 synchronize_irq(hw->pdev->irq);
1904
6b1a3aef
SH		 1905 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1906 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1907 sky2_rx_stop(sky2);
1908 sky2_rx_clean(sky2);
cd28ab6a
SH		 1909
1910 dev->mtu = new_mtu;
14d0263f 1911
6b1a3aef
SH		 1912 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1913 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1914
1915 if (dev->mtu > ETH_DATA_LEN)
1916 mode |= GM_SMOD_JUMBO_ENA;
1917
1918 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1919
6b1a3aef 1920 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1921
6b1a3aef 1922 err = sky2_rx_start(sky2);
e07b1aa8 1923 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1924
1b537565
SH		 1925 if (err)
1926 dev_close(dev);
1927 else {
1928 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1929
1930 netif_poll_enable(hw->dev[0]);
1931 netif_wake_queue(dev);
1932 }
1933
cd28ab6a
SH		 1934 return err;
1935}
1936
14d0263f
SH		 1937/* For small just reuse existing skb for next receive */
1938static struct sk_buff *receive_copy(struct sky2_port *sky2,
1939 const struct rx_ring_info *re,
1940 unsigned length)
1941{
1942 struct sk_buff *skb;
1943
1944 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1945 if (likely(skb)) {
1946 skb_reserve(skb, 2);
1947 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1948 length, PCI_DMA_FROMDEVICE);
1949 memcpy(skb->data, re->skb->data, length);
1950 skb->ip_summed = re->skb->ip_summed;
1951 skb->csum = re->skb->csum;
1952 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1953 length, PCI_DMA_FROMDEVICE);
1954 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1955 skb_put(skb, length);
14d0263f
SH		 1956 }
1957 return skb;
1958}
1959
1960/* Adjust length of skb with fragments to match received data */
1961static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1962 unsigned int length)
1963{
1964 int i, num_frags;
1965 unsigned int size;
1966
1967 /* put header into skb */
1968 size = min(length, hdr_space);
1969 skb->tail += size;
1970 skb->len += size;
1971 length -= size;
1972
1973 num_frags = skb_shinfo(skb)->nr_frags;
1974 for (i = 0; i < num_frags; i++) {
1975 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1976
1977 if (length == 0) {
1978 /* don't need this page */
1979 __free_page(frag->page);
1980 --skb_shinfo(skb)->nr_frags;
1981 } else {
1982 size = min(length, (unsigned) PAGE_SIZE);
1983
1984 frag->size = size;
1985 skb->data_len += size;
1986 skb->truesize += size;
1987 skb->len += size;
1988 length -= size;
1989 }
1990 }
1991}
1992
1993/* Normal packet - take skb from ring element and put in a new one */
1994static struct sk_buff *receive_new(struct sky2_port *sky2,
1995 struct rx_ring_info *re,
1996 unsigned int length)
1997{
1998 struct sk_buff *skb, *nskb;
1999 unsigned hdr_space = sky2->rx_data_size;
2000
2001 pr_debug(PFX "receive new length=%d\n", length);
2002
2003 /* Don't be tricky about reusing pages (yet) */
2004 nskb = sky2_rx_alloc(sky2);
2005 if (unlikely(!nskb))
2006 return NULL;
2007
2008 skb = re->skb;
2009 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2010
2011 prefetch(skb->data);
2012 re->skb = nskb;
2013 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2014
2015 if (skb_shinfo(skb)->nr_frags)
2016 skb_put_frags(skb, hdr_space, length);
2017 else
489b10c1 2018 skb_put(skb, length);
14d0263f
SH		 2019 return skb;
2020}
2021
cd28ab6a
SH		 2022/*
2023 * Receive one packet.
d571b694 2024 * For larger packets, get new buffer.
cd28ab6a 2025 */
497d7c86 2026static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2027 u16 length, u32 status)
2028{
497d7c86 2029 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2030 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2031 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2032
2033 if (unlikely(netif_msg_rx_status(sky2)))
2034 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2035 dev->name, sky2->rx_next, status, length);
cd28ab6a 2036
793b883e 2037 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2038 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2039
42eeea01 2040 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2041 goto error;
2042
42eeea01
SH		 2043 if (!(status & GMR_FS_RX_OK))
2044 goto resubmit;
2045
497d7c86 2046 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 2047 goto oversize;
2048
14d0263f
SH		 2049 if (length < copybreak)
2050 skb = receive_copy(sky2, re, length);
2051 else
2052 skb = receive_new(sky2, re, length);
793b883e 2053resubmit:
14d0263f 2054 sky2_rx_submit(sky2, re);
79e57d32 2055
cd28ab6a
SH		 2056 return skb;
2057
6e15b712
SH		 2058oversize:
2059 ++sky2->net_stats.rx_over_errors;
2060 goto resubmit;
2061
cd28ab6a 2062error:
6e15b712 2063 ++sky2->net_stats.rx_errors;
b6d77734
SH		 2064 if (status & GMR_FS_RX_FF_OV) {
2065 sky2->net_stats.rx_fifo_errors++;
2066 goto resubmit;
2067 }
6e15b712 2068
3be92a70 2069 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2070 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2071 dev->name, status, length);
793b883e
SH		 2072
2073 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2074 sky2->net_stats.rx_length_errors++;
2075 if (status & GMR_FS_FRAGMENT)
2076 sky2->net_stats.rx_frame_errors++;
2077 if (status & GMR_FS_CRC_ERR)
2078 sky2->net_stats.rx_crc_errors++;
79e57d32 2079
793b883e 2080 goto resubmit;
cd28ab6a
SH		 2081}
2082
e07b1aa8
SH		 2083/* Transmit complete */
2084static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2085{
e07b1aa8 2086 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2087
e07b1aa8 2088 if (netif_running(dev)) {
2bb8c262 2089 netif_tx_lock(dev);
e07b1aa8 2090 sky2_tx_complete(sky2, last);
2bb8c262 2091 netif_tx_unlock(dev);
2224795d 2092 }
cd28ab6a
SH		 2093}
2094
e07b1aa8
SH		 2095/* Process status response ring */
2096static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2097{
22e11703 2098 struct sky2_port *sky2;
e07b1aa8 2099 int work_done = 0;
22e11703 2100 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2101 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2102
af2a58ac 2103 rmb();
bea86103 2104
e71ebd73 2105 while (hw->st_idx != hwidx) {
13210ce5
SH		 2106 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2107 struct net_device *dev;
cd28ab6a 2108 struct sk_buff *skb;
cd28ab6a
SH		 2109 u32 status;
2110 u16 length;
2111
cb5d9547 2112 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2113
e71ebd73
SH		 2114 BUG_ON(le->link >= 2);
2115 dev = hw->dev[le->link];
13210ce5
SH		 2116
2117 sky2 = netdev_priv(dev);
f65b138c
SH		 2118 length = le16_to_cpu(le->length);
2119 status = le32_to_cpu(le->status);
cd28ab6a 2120
e71ebd73 2121 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2122 case OP_RXSTAT:
497d7c86 2123 skb = sky2_receive(dev, length, status);
d1f13708 2124 if (!skb)
5df79111 2125 goto force_update;
13210ce5 2126
13210ce5 2127 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2128 sky2->net_stats.rx_packets++;
2129 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2130 dev->last_rx = jiffies;
2131
d1f13708
SH		 2132#ifdef SKY2_VLAN_TAG_USED
2133 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2134 vlan_hwaccel_receive_skb(skb,
2135 sky2->vlgrp,
2136 be16_to_cpu(sky2->rx_tag));
2137 } else
2138#endif
cd28ab6a 2139 netif_receive_skb(skb);
13210ce5 2140
22e11703
SH		 2141 /* Update receiver after 16 frames */
2142 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2143force_update:
2144 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2145 buf_write[le->link] = 0;
2146 }
2147
2148 /* Stop after net poll weight */
13210ce5
SH		 2149 if (++work_done >= to_do)
2150 goto exit_loop;
cd28ab6a
SH		 2151 break;
2152
d1f13708
SH		 2153#ifdef SKY2_VLAN_TAG_USED
2154 case OP_RXVLAN:
2155 sky2->rx_tag = length;
2156 break;
2157
2158 case OP_RXCHKSVLAN:
2159 sky2->rx_tag = length;
2160 /* fall through */
2161#endif
cd28ab6a 2162 case OP_RXCHKS:
d11c13e7 2163 skb = sky2->rx_ring[sky2->rx_next].skb;
84fa7933 2164 skb->ip_summed = CHECKSUM_COMPLETE;
f65b138c 2165 skb->csum = status & 0xffff;
cd28ab6a
SH		 2166 break;
2167
2168 case OP_TXINDEXLE:
13b97b74 2169 /* TX index reports status for both ports */
f55925d7
SH		 2170 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2171 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2172 if (hw->dev[1])
2173 sky2_tx_done(hw->dev[1],
2174 ((status >> 24) & 0xff)
2175 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2176 break;
2177
cd28ab6a
SH		 2178 default:
2179 if (net_ratelimit())
793b883e 2180 printk(KERN_WARNING PFX
e71ebd73
SH		 2181 "unknown status opcode 0x%x\n", le->opcode);
2182 goto exit_loop;
cd28ab6a 2183 }
13210ce5 2184 }
cd28ab6a 2185
fe2a24df
SH		 2186 /* Fully processed status ring so clear irq */
2187 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2188
13210ce5 2189exit_loop:
22e11703
SH		 2190 if (buf_write[0]) {
2191 sky2 = netdev_priv(hw->dev[0]);
2192 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2193 }
2194
2195 if (buf_write[1]) {
2196 sky2 = netdev_priv(hw->dev[1]);
2197 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2198 }
2199
e07b1aa8 2200 return work_done;
cd28ab6a
SH		 2201}
2202
2203static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2204{
2205 struct net_device *dev = hw->dev[port];
2206
3be92a70
SH		 2207 if (net_ratelimit())
2208 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2209 dev->name, status);
cd28ab6a
SH		 2210
2211 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2212 if (net_ratelimit())
2213 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2214 dev->name);
cd28ab6a
SH		 2215 /* Clear IRQ */
2216 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2217 }
2218
2219 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2220 if (net_ratelimit())
2221 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2222 dev->name);
cd28ab6a
SH		 2223
2224 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2225 }
2226
2227 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2228 if (net_ratelimit())
2229 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2230 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2231 }
2232
2233 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2234 if (net_ratelimit())
2235 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2236 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2237 }
2238
2239 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2240 if (net_ratelimit())
2241 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2242 dev->name);
cd28ab6a
SH		 2243 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2244 }
2245}
2246
2247static void sky2_hw_intr(struct sky2_hw *hw)
2248{
2249 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2250
793b883e 2251 if (status & Y2_IS_TIST_OV)
cd28ab6a 2252 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2253
2254 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2255 u16 pci_err;
2256
56a645cc 2257 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2258 if (net_ratelimit())
b02a9258
SH		 2259 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2260 pci_err);
cd28ab6a
SH		 2261
2262 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2263 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2264 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2265 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2266 }
2267
2268 if (status & Y2_IS_PCI_EXP) {
d571b694 2269 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2270 u32 pex_err;
2271
7bd656d1 2272 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2273
3be92a70 2274 if (net_ratelimit())
b02a9258
SH		 2275 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2276 pex_err);
cd28ab6a
SH		 2277
2278 /* clear the interrupt */
2279 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2280 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2281 0xffffffffUL);
cd28ab6a
SH		 2282 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2283
7bd656d1 2284 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2285 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2286 hwmsk &= ~Y2_IS_PCI_EXP;
2287 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2288 }
2289 }
2290
2291 if (status & Y2_HWE_L1_MASK)
2292 sky2_hw_error(hw, 0, status);
2293 status >>= 8;
2294 if (status & Y2_HWE_L1_MASK)
2295 sky2_hw_error(hw, 1, status);
2296}
2297
2298static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2299{
2300 struct net_device *dev = hw->dev[port];
2301 struct sky2_port *sky2 = netdev_priv(dev);
2302 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2303
2304 if (netif_msg_intr(sky2))
2305 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2306 dev->name, status);
2307
2308 if (status & GM_IS_RX_FF_OR) {
2309 ++sky2->net_stats.rx_fifo_errors;
2310 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2311 }
2312
2313 if (status & GM_IS_TX_FF_UR) {
2314 ++sky2->net_stats.tx_fifo_errors;
2315 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2316 }
cd28ab6a
SH		 2317}
2318
d257924e
SH		 2319/* This should never happen it is a fatal situation */
2320static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2321 const char *rxtx, u32 mask)
2322{
2323 struct net_device *dev = hw->dev[port];
2324 struct sky2_port *sky2 = netdev_priv(dev);
2325 u32 imask;
2326
2327 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2328 dev ? dev->name : "<not registered>", rxtx);
2329
2330 imask = sky2_read32(hw, B0_IMSK);
2331 imask &= ~mask;
2332 sky2_write32(hw, B0_IMSK, imask);
2333
2334 if (dev) {
2335 spin_lock(&sky2->phy_lock);
2336 sky2_link_down(sky2);
2337 spin_unlock(&sky2->phy_lock);
2338 }
2339}
cd28ab6a 2340
d27ed387
SH		 2341/* If idle then force a fake soft NAPI poll once a second
2342 * to work around cases where sharing an edge triggered interrupt.
2343 */
eb35cf60
SH		 2344static inline void sky2_idle_start(struct sky2_hw *hw)
2345{
2346 if (idle_timeout > 0)
2347 mod_timer(&hw->idle_timer,
2348 jiffies + msecs_to_jiffies(idle_timeout));
2349}
2350
d27ed387
SH		 2351static void sky2_idle(unsigned long arg)
2352{
01bd7564
SH		 2353 struct sky2_hw *hw = (struct sky2_hw *) arg;
2354 struct net_device *dev = hw->dev[0];
d27ed387 2355
d27ed387
SH		 2356 if (__netif_rx_schedule_prep(dev))
2357 __netif_rx_schedule(dev);
01bd7564
SH		 2358
2359 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2360}
2361
2362
e07b1aa8 2363static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2364{
e07b1aa8
SH		 2365 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2366 int work_limit = min(dev0->quota, *budget);
2367 int work_done = 0;
fb2690a9 2368 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2369
1e5f1283
SH		 2370 if (status & Y2_IS_HW_ERR)
2371 sky2_hw_intr(hw);
d257924e 2372
1e5f1283
SH		 2373 if (status & Y2_IS_IRQ_PHY1)
2374 sky2_phy_intr(hw, 0);
cd28ab6a 2375
1e5f1283
SH		 2376 if (status & Y2_IS_IRQ_PHY2)
2377 sky2_phy_intr(hw, 1);
cd28ab6a 2378
1e5f1283
SH		 2379 if (status & Y2_IS_IRQ_MAC1)
2380 sky2_mac_intr(hw, 0);
cd28ab6a 2381
1e5f1283
SH		 2382 if (status & Y2_IS_IRQ_MAC2)
2383 sky2_mac_intr(hw, 1);
cd28ab6a 2384
1e5f1283
SH		 2385 if (status & Y2_IS_CHK_RX1)
2386 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2387
1e5f1283
SH		 2388 if (status & Y2_IS_CHK_RX2)
2389 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2390
1e5f1283
SH		 2391 if (status & Y2_IS_CHK_TXA1)
2392 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2393
1e5f1283
SH		 2394 if (status & Y2_IS_CHK_TXA2)
2395 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2396
1e5f1283 2397 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2398 if (work_done < work_limit) {
2399 netif_rx_complete(dev0);
86fba634 2400
fe2a24df
SH		 2401 sky2_read32(hw, B0_Y2_SP_LISR);
2402 return 0;
2403 } else {
2404 *budget -= work_done;
2405 dev0->quota -= work_done;
1e5f1283 2406 return 1;
fe2a24df 2407 }
e07b1aa8
SH		 2408}
2409
7d12e780 2410static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2411{
2412 struct sky2_hw *hw = dev_id;
2413 struct net_device *dev0 = hw->dev[0];
2414 u32 status;
2415
2416 /* Reading this mask interrupts as side effect */
2417 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2418 if (status == 0 || status == ~0)
2419 return IRQ_NONE;
793b883e 2420
e07b1aa8
SH		 2421 prefetch(&hw->st_le[hw->st_idx]);
2422 if (likely(__netif_rx_schedule_prep(dev0)))
2423 __netif_rx_schedule(dev0);
793b883e 2424
cd28ab6a
SH		 2425 return IRQ_HANDLED;
2426}
2427
2428#ifdef CONFIG_NET_POLL_CONTROLLER
2429static void sky2_netpoll(struct net_device *dev)
2430{
2431 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2432 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2433
88d11360
SH		 2434 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2435 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2436}
2437#endif
2438
2439/* Chip internal frequency for clock calculations */
fb17358f 2440static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2441{
793b883e 2442 switch (hw->chip_id) {
cd28ab6a 2443 case CHIP_ID_YUKON_EC:
5a5b1ea0 2444 case CHIP_ID_YUKON_EC_U:
fb17358f 2445 return 125; /* 125 Mhz */
cd28ab6a 2446 case CHIP_ID_YUKON_FE:
fb17358f 2447 return 100; /* 100 Mhz */
793b883e 2448 default: /* YUKON_XL */
fb17358f 2449 return 156; /* 156 Mhz */
cd28ab6a
SH		 2450 }
2451}
2452
fb17358f 2453static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2454{
fb17358f 2455 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2456}
2457
fb17358f 2458static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2459{
fb17358f 2460 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2461}
2462
fb17358f 2463
e3173832 2464static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2465{
b89165f2 2466 u8 t8;
cd28ab6a 2467
cd28ab6a 2468 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2469
cd28ab6a
SH		 2470 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2471 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2472 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2473 hw->chip_id);
cd28ab6a
SH		 2474 return -EOPNOTSUPP;
2475 }
2476
290d4de5
SH		 2477 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2478
2479 /* This rev is really old, and requires untested workarounds */
2480 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2481 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2482 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2483 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2484 return -EOPNOTSUPP;
2485 }
2486
e3173832
SH		 2487 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2488 hw->ports = 1;
2489 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2490 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2491 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2492 ++hw->ports;
2493 }
2494
2495 return 0;
2496}
2497
2498static void sky2_reset(struct sky2_hw *hw)
2499{
2500 u16 status;
2501 int i;
2502
cd28ab6a
SH		 2503 /* disable ASF */
2504 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2505 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2506 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2507 }
2508
2509 /* do a SW reset */
2510 sky2_write8(hw, B0_CTST, CS_RST_SET);
2511 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2512
2513 /* clear PCI errors, if any */
56a645cc 2514 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2515
cd28ab6a 2516 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2517 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2518
cd28ab6a
SH		 2519
2520 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2521
2522 /* clear any PEX errors */
7bd656d1
SH		 2523 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2524 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2525
cd28ab6a 2526
ae306cca 2527 sky2_power_on(hw);
cd28ab6a
SH		 2528
2529 for (i = 0; i < hw->ports; i++) {
2530 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2531 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2532 }
2533
2534 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2535
793b883e
SH		 2536 /* Clear I2C IRQ noise */
2537 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2538
2539 /* turn off hardware timer (unused) */
2540 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2541 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2542
cd28ab6a
SH		 2543 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2544
69634ee7
SH		 2545 /* Turn off descriptor polling */
2546 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2547
2548 /* Turn off receive timestamp */
2549 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2550 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2551
2552 /* enable the Tx Arbiters */
2553 for (i = 0; i < hw->ports; i++)
2554 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2555
2556 /* Initialize ram interface */
2557 for (i = 0; i < hw->ports; i++) {
793b883e 2558 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2559
2560 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2561 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2562 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2563 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2564 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2565 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2566 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2567 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2568 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2569 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2570 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2571 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2572 }
2573
7bd656d1 2574 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2575
cd28ab6a 2576 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2577 sky2_gmac_reset(hw, i);
cd28ab6a 2578
cd28ab6a
SH		 2579 memset(hw->st_le, 0, STATUS_LE_BYTES);
2580 hw->st_idx = 0;
2581
2582 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2583 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2584
2585 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2586 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2587
2588 /* Set the list last index */
793b883e 2589 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2590
290d4de5
SH		 2591 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2592 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2593
290d4de5
SH		 2594 /* set Status-FIFO ISR watermark */
2595 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2596 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2597 else
2598 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2599
290d4de5 2600 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2601 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2602 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2603
793b883e 2604 /* enable status unit */
cd28ab6a
SH		 2605 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2606
2607 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2608 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2609 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2610}
2611
2612static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2613{
2614 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2615}
2616
2617static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2618{
2619 const struct sky2_port *sky2 = netdev_priv(dev);
2620
2621 wol->supported = sky2_wol_supported(sky2->hw);
2622 wol->wolopts = sky2->wol;
2623}
2624
2625static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2626{
2627 struct sky2_port *sky2 = netdev_priv(dev);
2628 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2629
e3173832
SH		 2630 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2631 return -EOPNOTSUPP;
2632
2633 sky2->wol = wol->wolopts;
2634
2635 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2636 sky2_write32(hw, B0_CTST, sky2->wol
2637 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2638
2639 if (!netif_running(dev))
2640 sky2_wol_init(sky2);
cd28ab6a
SH		 2641 return 0;
2642}
2643
28bd181a 2644static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2645{
b89165f2
SH		 2646 if (sky2_is_copper(hw)) {
2647 u32 modes = SUPPORTED_10baseT_Half
2648 | SUPPORTED_10baseT_Full
2649 | SUPPORTED_100baseT_Half
2650 | SUPPORTED_100baseT_Full
2651 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2652
2653 if (hw->chip_id != CHIP_ID_YUKON_FE)
2654 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2655 | SUPPORTED_1000baseT_Full;
2656 return modes;
cd28ab6a 2657 } else
b89165f2
SH		 2658 return SUPPORTED_1000baseT_Half
2659 | SUPPORTED_1000baseT_Full
2660 | SUPPORTED_Autoneg
2661 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2662}
2663
793b883e 2664static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2665{
2666 struct sky2_port *sky2 = netdev_priv(dev);
2667 struct sky2_hw *hw = sky2->hw;
2668
2669 ecmd->transceiver = XCVR_INTERNAL;
2670 ecmd->supported = sky2_supported_modes(hw);
2671 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2672 if (sky2_is_copper(hw)) {
cd28ab6a 2673 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2674 | SUPPORTED_10baseT_Full
2675 | SUPPORTED_100baseT_Half
2676 | SUPPORTED_100baseT_Full
2677 | SUPPORTED_1000baseT_Half
2678 | SUPPORTED_1000baseT_Full
2679 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2680 ecmd->port = PORT_TP;
b89165f2
SH		 2681 ecmd->speed = sky2->speed;
2682 } else {
2683 ecmd->speed = SPEED_1000;
cd28ab6a 2684 ecmd->port = PORT_FIBRE;
b89165f2 2685 }
cd28ab6a
SH		 2686
2687 ecmd->advertising = sky2->advertising;
2688 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2689 ecmd->duplex = sky2->duplex;
2690 return 0;
2691}
2692
2693static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2694{
2695 struct sky2_port *sky2 = netdev_priv(dev);
2696 const struct sky2_hw *hw = sky2->hw;
2697 u32 supported = sky2_supported_modes(hw);
2698
2699 if (ecmd->autoneg == AUTONEG_ENABLE) {
2700 ecmd->advertising = supported;
2701 sky2->duplex = -1;
2702 sky2->speed = -1;
2703 } else {
2704 u32 setting;
2705
793b883e 2706 switch (ecmd->speed) {
cd28ab6a
SH		 2707 case SPEED_1000:
2708 if (ecmd->duplex == DUPLEX_FULL)
2709 setting = SUPPORTED_1000baseT_Full;
2710 else if (ecmd->duplex == DUPLEX_HALF)
2711 setting = SUPPORTED_1000baseT_Half;
2712 else
2713 return -EINVAL;
2714 break;
2715 case SPEED_100:
2716 if (ecmd->duplex == DUPLEX_FULL)
2717 setting = SUPPORTED_100baseT_Full;
2718 else if (ecmd->duplex == DUPLEX_HALF)
2719 setting = SUPPORTED_100baseT_Half;
2720 else
2721 return -EINVAL;
2722 break;
2723
2724 case SPEED_10:
2725 if (ecmd->duplex == DUPLEX_FULL)
2726 setting = SUPPORTED_10baseT_Full;
2727 else if (ecmd->duplex == DUPLEX_HALF)
2728 setting = SUPPORTED_10baseT_Half;
2729 else
2730 return -EINVAL;
2731 break;
2732 default:
2733 return -EINVAL;
2734 }
2735
2736 if ((setting & supported) == 0)
2737 return -EINVAL;
2738
2739 sky2->speed = ecmd->speed;
2740 sky2->duplex = ecmd->duplex;
2741 }
2742
2743 sky2->autoneg = ecmd->autoneg;
2744 sky2->advertising = ecmd->advertising;
2745
1b537565
SH		 2746 if (netif_running(dev))
2747 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2748
2749 return 0;
2750}
2751
2752static void sky2_get_drvinfo(struct net_device *dev,
2753 struct ethtool_drvinfo *info)
2754{
2755 struct sky2_port *sky2 = netdev_priv(dev);
2756
2757 strcpy(info->driver, DRV_NAME);
2758 strcpy(info->version, DRV_VERSION);
2759 strcpy(info->fw_version, "N/A");
2760 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2761}
2762
2763static const struct sky2_stat {
793b883e
SH		 2764 char name[ETH_GSTRING_LEN];
2765 u16 offset;
cd28ab6a
SH		 2766} sky2_stats[] = {
2767 { "tx_bytes", GM_TXO_OK_HI },
2768 { "rx_bytes", GM_RXO_OK_HI },
2769 { "tx_broadcast", GM_TXF_BC_OK },
2770 { "rx_broadcast", GM_RXF_BC_OK },
2771 { "tx_multicast", GM_TXF_MC_OK },
2772 { "rx_multicast", GM_RXF_MC_OK },
2773 { "tx_unicast", GM_TXF_UC_OK },
2774 { "rx_unicast", GM_RXF_UC_OK },
2775 { "tx_mac_pause", GM_TXF_MPAUSE },
2776 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2777 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2778 { "late_collision",GM_TXF_LAT_COL },
2779 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2780 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2781 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2782
d2604540 2783 { "rx_short", GM_RXF_SHT },
cd28ab6a 2784 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2785 { "rx_64_byte_packets", GM_RXF_64B },
2786 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2787 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2788 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2789 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2790 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2791 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2792 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2793 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2794 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2795 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2796
2797 { "tx_64_byte_packets", GM_TXF_64B },
2798 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2799 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2800 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2801 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2802 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2803 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2804 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2805};
2806
cd28ab6a
SH		 2807static u32 sky2_get_rx_csum(struct net_device *dev)
2808{
2809 struct sky2_port *sky2 = netdev_priv(dev);
2810
2811 return sky2->rx_csum;
2812}
2813
2814static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2815{
2816 struct sky2_port *sky2 = netdev_priv(dev);
2817
2818 sky2->rx_csum = data;
793b883e 2819
cd28ab6a
SH		 2820 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2821 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2822
2823 return 0;
2824}
2825
2826static u32 sky2_get_msglevel(struct net_device *netdev)
2827{
2828 struct sky2_port *sky2 = netdev_priv(netdev);
2829 return sky2->msg_enable;
2830}
2831
9a7ae0a9
SH		 2832static int sky2_nway_reset(struct net_device *dev)
2833{
2834 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2835
16ad91e1 2836 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2837 return -EINVAL;
2838
1b537565 2839 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2840
2841 return 0;
2842}
2843
793b883e 2844static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2845{
2846 struct sky2_hw *hw = sky2->hw;
2847 unsigned port = sky2->port;
2848 int i;
2849
2850 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2851 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2852 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2853 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2854
793b883e 2855 for (i = 2; i < count; i++)
cd28ab6a
SH		 2856 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2857}
2858
cd28ab6a
SH		 2859static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2860{
2861 struct sky2_port *sky2 = netdev_priv(netdev);
2862 sky2->msg_enable = value;
2863}
2864
2865static int sky2_get_stats_count(struct net_device *dev)
2866{
2867 return ARRAY_SIZE(sky2_stats);
2868}
2869
2870static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2871 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2872{
2873 struct sky2_port *sky2 = netdev_priv(dev);
2874
793b883e 2875 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2876}
2877
793b883e 2878static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2879{
2880 int i;
2881
2882 switch (stringset) {
2883 case ETH_SS_STATS:
2884 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2885 memcpy(data + i * ETH_GSTRING_LEN,
2886 sky2_stats[i].name, ETH_GSTRING_LEN);
2887 break;
2888 }
2889}
2890
cd28ab6a
SH		 2891static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2892{
2893 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2894 return &sky2->net_stats;
2895}
2896
2897static int sky2_set_mac_address(struct net_device *dev, void *p)
2898{
2899 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2900 struct sky2_hw *hw = sky2->hw;
2901 unsigned port = sky2->port;
2902 const struct sockaddr *addr = p;
cd28ab6a
SH		 2903
2904 if (!is_valid_ether_addr(addr->sa_data))
2905 return -EADDRNOTAVAIL;
2906
cd28ab6a 2907 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2908 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2909 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2910 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2911 dev->dev_addr, ETH_ALEN);
1b537565 2912
a8ab1ec0
SH		 2913 /* virtual address for data */
2914 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2915
2916 /* physical address: used for pause frames */
2917 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2918
2919 return 0;
cd28ab6a
SH		 2920}
2921
a052b52f
SH		 2922static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2923{
2924 u32 bit;
2925
2926 bit = ether_crc(ETH_ALEN, addr) & 63;
2927 filter[bit >> 3] |= 1 << (bit & 7);
2928}
2929
cd28ab6a
SH		 2930static void sky2_set_multicast(struct net_device *dev)
2931{
2932 struct sky2_port *sky2 = netdev_priv(dev);
2933 struct sky2_hw *hw = sky2->hw;
2934 unsigned port = sky2->port;
2935 struct dev_mc_list *list = dev->mc_list;
2936 u16 reg;
2937 u8 filter[8];
a052b52f
SH		 2938 int rx_pause;
2939 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 2940
a052b52f 2941 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 2942 memset(filter, 0, sizeof(filter));
2943
2944 reg = gma_read16(hw, port, GM_RX_CTRL);
2945 reg |= GM_RXCR_UCF_ENA;
2946
d571b694 2947 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2948 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 2949 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 2950 memset(filter, 0xff, sizeof(filter));
a052b52f 2951 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 2952 reg &= ~GM_RXCR_MCF_ENA;
2953 else {
2954 int i;
2955 reg |= GM_RXCR_MCF_ENA;
2956
a052b52f
SH		 2957 if (rx_pause)
2958 sky2_add_filter(filter, pause_mc_addr);
2959
2960 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2961 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 2962 }
2963
cd28ab6a 2964 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2965 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2966 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2967 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2968 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2969 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2970 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2971 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2972
2973 gma_write16(hw, port, GM_RX_CTRL, reg);
2974}
2975
2976/* Can have one global because blinking is controlled by
2977 * ethtool and that is always under RTNL mutex
2978 */
91c86df5 2979static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2980{
793b883e
SH		 2981 u16 pg;
2982
793b883e
SH		 2983 switch (hw->chip_id) {
2984 case CHIP_ID_YUKON_XL:
2985 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2986 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2987 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2988 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2989 PHY_M_LEDC_INIT_CTRL(7) |
2990 PHY_M_LEDC_STA1_CTRL(7) |
2991 PHY_M_LEDC_STA0_CTRL(7))
2992 : 0);
2993
2994 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2995 break;
2996
2997 default:
2998 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 2999 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3000 on ? PHY_M_LED_ALL : 0);
793b883e 3001 }
cd28ab6a
SH		 3002}
3003
3004/* blink LED's for finding board */
3005static int sky2_phys_id(struct net_device *dev, u32 data)
3006{
3007 struct sky2_port *sky2 = netdev_priv(dev);
3008 struct sky2_hw *hw = sky2->hw;
3009 unsigned port = sky2->port;
793b883e 3010 u16 ledctrl, ledover = 0;
cd28ab6a 3011 long ms;
91c86df5 3012 int interrupted;
cd28ab6a
SH		 3013 int onoff = 1;
3014
793b883e 3015 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3016 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3017 else
3018 ms = data * 1000;
3019
3020 /* save initial values */
e07b1aa8 3021 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3022 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3023 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3024 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3025 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3026 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3027 } else {
3028 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3029 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3030 }
cd28ab6a 3031
91c86df5
SH		 3032 interrupted = 0;
3033 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3034 sky2_led(hw, port, onoff);
3035 onoff = !onoff;
3036
e07b1aa8 3037 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3038 interrupted = msleep_interruptible(250);
e07b1aa8 3039 spin_lock_bh(&sky2->phy_lock);
91c86df5 3040
cd28ab6a
SH		 3041 ms -= 250;
3042 }
3043
3044 /* resume regularly scheduled programming */
793b883e
SH		 3045 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3046 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3047 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3048 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3049 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3050 } else {
3051 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3052 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3053 }
e07b1aa8 3054 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3055
3056 return 0;
3057}
3058
3059static void sky2_get_pauseparam(struct net_device *dev,
3060 struct ethtool_pauseparam *ecmd)
3061{
3062 struct sky2_port *sky2 = netdev_priv(dev);
3063
16ad91e1
SH		 3064 switch (sky2->flow_mode) {
3065 case FC_NONE:
3066 ecmd->tx_pause = ecmd->rx_pause = 0;
3067 break;
3068 case FC_TX:
3069 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3070 break;
3071 case FC_RX:
3072 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3073 break;
3074 case FC_BOTH:
3075 ecmd->tx_pause = ecmd->rx_pause = 1;
3076 }
3077
cd28ab6a
SH		 3078 ecmd->autoneg = sky2->autoneg;
3079}
3080
3081static int sky2_set_pauseparam(struct net_device *dev,
3082 struct ethtool_pauseparam *ecmd)
3083{
3084 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3085
3086 sky2->autoneg = ecmd->autoneg;
16ad91e1 3087 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3088
16ad91e1
SH		 3089 if (netif_running(dev))
3090 sky2_phy_reinit(sky2);
cd28ab6a 3091
2eaba1a2 3092 return 0;
cd28ab6a
SH		 3093}
3094
fb17358f
SH		 3095static int sky2_get_coalesce(struct net_device *dev,
3096 struct ethtool_coalesce *ecmd)
3097{
3098 struct sky2_port *sky2 = netdev_priv(dev);
3099 struct sky2_hw *hw = sky2->hw;
3100
3101 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3102 ecmd->tx_coalesce_usecs = 0;
3103 else {
3104 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3105 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3106 }
3107 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3108
3109 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3110 ecmd->rx_coalesce_usecs = 0;
3111 else {
3112 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3113 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3114 }
3115 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3116
3117 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3118 ecmd->rx_coalesce_usecs_irq = 0;
3119 else {
3120 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3121 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3122 }
3123
3124 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3125
3126 return 0;
3127}
3128
3129/* Note: this affect both ports */
3130static int sky2_set_coalesce(struct net_device *dev,
3131 struct ethtool_coalesce *ecmd)
3132{
3133 struct sky2_port *sky2 = netdev_priv(dev);
3134 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3135 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3136
77b3d6a2
SH		 3137 if (ecmd->tx_coalesce_usecs > tmax ||
3138 ecmd->rx_coalesce_usecs > tmax ||
3139 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3140 return -EINVAL;
3141
ff81fbbe 3142 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3143 return -EINVAL;
ff81fbbe 3144 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3145 return -EINVAL;
ff81fbbe 3146 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3147 return -EINVAL;
3148
3149 if (ecmd->tx_coalesce_usecs == 0)
3150 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3151 else {
3152 sky2_write32(hw, STAT_TX_TIMER_INI,
3153 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3154 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3155 }
3156 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3157
3158 if (ecmd->rx_coalesce_usecs == 0)
3159 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3160 else {
3161 sky2_write32(hw, STAT_LEV_TIMER_INI,
3162 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3163 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3164 }
3165 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3166
3167 if (ecmd->rx_coalesce_usecs_irq == 0)
3168 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3169 else {
d28d4870 3170 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3171 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3172 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3173 }
3174 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3175 return 0;
3176}
3177
793b883e
SH		 3178static void sky2_get_ringparam(struct net_device *dev,
3179 struct ethtool_ringparam *ering)
3180{
3181 struct sky2_port *sky2 = netdev_priv(dev);
3182
3183 ering->rx_max_pending = RX_MAX_PENDING;
3184 ering->rx_mini_max_pending = 0;
3185 ering->rx_jumbo_max_pending = 0;
3186 ering->tx_max_pending = TX_RING_SIZE - 1;
3187
3188 ering->rx_pending = sky2->rx_pending;
3189 ering->rx_mini_pending = 0;
3190 ering->rx_jumbo_pending = 0;
3191 ering->tx_pending = sky2->tx_pending;
3192}
3193
3194static int sky2_set_ringparam(struct net_device *dev,
3195 struct ethtool_ringparam *ering)
3196{
3197 struct sky2_port *sky2 = netdev_priv(dev);
3198 int err = 0;
3199
3200 if (ering->rx_pending > RX_MAX_PENDING ||
3201 ering->rx_pending < 8 ||
3202 ering->tx_pending < MAX_SKB_TX_LE ||
3203 ering->tx_pending > TX_RING_SIZE - 1)
3204 return -EINVAL;
3205
3206 if (netif_running(dev))
3207 sky2_down(dev);
3208
3209 sky2->rx_pending = ering->rx_pending;
3210 sky2->tx_pending = ering->tx_pending;
3211
1b537565 3212 if (netif_running(dev)) {
793b883e 3213 err = sky2_up(dev);
1b537565
SH		 3214 if (err)
3215 dev_close(dev);
6ed995bb
SH		 3216 else
3217 sky2_set_multicast(dev);
1b537565 3218 }
793b883e
SH		 3219
3220 return err;
3221}
3222
793b883e
SH		 3223static int sky2_get_regs_len(struct net_device *dev)
3224{
6e4cbb34 3225 return 0x4000;
793b883e
SH		 3226}
3227
3228/*
3229 * Returns copy of control register region
6e4cbb34 3230 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3231 */
3232static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3233 void *p)
3234{
3235 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3236 const void __iomem *io = sky2->hw->regs;
793b883e 3237
6e4cbb34 3238 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3239 regs->version = 1;
6e4cbb34 3240 memset(p, 0, regs->len);
793b883e 3241
6e4cbb34
SH		 3242 memcpy_fromio(p, io, B3_RAM_ADDR);
3243
3244 memcpy_fromio(p + B3_RI_WTO_R1,
3245 io + B3_RI_WTO_R1,
3246 regs->len - B3_RI_WTO_R1);
793b883e 3247}
cd28ab6a 3248
7282d491 3249static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3250 .get_settings = sky2_get_settings,
3251 .set_settings = sky2_set_settings,
e3173832
SH		 3252 .get_drvinfo = sky2_get_drvinfo,
3253 .get_wol = sky2_get_wol,
3254 .set_wol = sky2_set_wol,
793b883e
SH		 3255 .get_msglevel = sky2_get_msglevel,
3256 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3257 .nway_reset = sky2_nway_reset,
793b883e
SH		 3258 .get_regs_len = sky2_get_regs_len,
3259 .get_regs = sky2_get_regs,
3260 .get_link = ethtool_op_get_link,
3261 .get_sg = ethtool_op_get_sg,
3262 .set_sg = ethtool_op_set_sg,
3263 .get_tx_csum = ethtool_op_get_tx_csum,
3264 .set_tx_csum = ethtool_op_set_tx_csum,
3265 .get_tso = ethtool_op_get_tso,
3266 .set_tso = ethtool_op_set_tso,
3267 .get_rx_csum = sky2_get_rx_csum,
3268 .set_rx_csum = sky2_set_rx_csum,
3269 .get_strings = sky2_get_strings,
fb17358f
SH		 3270 .get_coalesce = sky2_get_coalesce,
3271 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3272 .get_ringparam = sky2_get_ringparam,
3273 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3274 .get_pauseparam = sky2_get_pauseparam,
3275 .set_pauseparam = sky2_set_pauseparam,
793b883e 3276 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3277 .get_stats_count = sky2_get_stats_count,
3278 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3279 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3280};
3281
3282/* Initialize network device */
3283static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3284 unsigned port,
3285 int highmem, int wol)
cd28ab6a
SH		 3286{
3287 struct sky2_port *sky2;
3288 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3289
3290 if (!dev) {
b02a9258 3291 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3292 return NULL;
3293 }
3294
3295 SET_MODULE_OWNER(dev);
3296 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3297 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3298 dev->open = sky2_up;
3299 dev->stop = sky2_down;
ef743d33 3300 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3301 dev->hard_start_xmit = sky2_xmit_frame;
3302 dev->get_stats = sky2_get_stats;
3303 dev->set_multicast_list = sky2_set_multicast;
3304 dev->set_mac_address = sky2_set_mac_address;
3305 dev->change_mtu = sky2_change_mtu;
3306 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3307 dev->tx_timeout = sky2_tx_timeout;
3308 dev->watchdog_timeo = TX_WATCHDOG;
3309 if (port == 0)
3310 dev->poll = sky2_poll;
3311 dev->weight = NAPI_WEIGHT;
3312#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3313 /* Network console (only works on port 0)
3314 * because netpoll makes assumptions about NAPI
3315 */
3316 if (port == 0)
3317 dev->poll_controller = sky2_netpoll;
cd28ab6a 3318#endif
cd28ab6a
SH		 3319
3320 sky2 = netdev_priv(dev);
3321 sky2->netdev = dev;
3322 sky2->hw = hw;
3323 sky2->msg_enable = netif_msg_init(debug, default_msg);
3324
cd28ab6a
SH		 3325 /* Auto speed and flow control */
3326 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3327 sky2->flow_mode = FC_BOTH;
3328
cd28ab6a
SH		 3329 sky2->duplex = -1;
3330 sky2->speed = -1;
3331 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3332 sky2->rx_csum = 1;
e3173832 3333 sky2->wol = wol;
75d070c5 3334
e07b1aa8 3335 spin_lock_init(&sky2->phy_lock);
793b883e 3336 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3337 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3338
3339 hw->dev[port] = dev;
3340
3341 sky2->port = port;
3342
4a50a876 3343 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3344 if (highmem)
3345 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3346
d1f13708
SH		 3347#ifdef SKY2_VLAN_TAG_USED
3348 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3349 dev->vlan_rx_register = sky2_vlan_rx_register;
3350 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3351#endif
3352
cd28ab6a 3353 /* read the mac address */
793b883e 3354 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3355 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3356
3357 /* device is off until link detection */
3358 netif_carrier_off(dev);
3359 netif_stop_queue(dev);
3360
3361 return dev;
3362}
3363
28bd181a 3364static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3365{
3366 const struct sky2_port *sky2 = netdev_priv(dev);
3367
3368 if (netif_msg_probe(sky2))
3369 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3370 dev->name,
3371 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3372 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3373}
3374
fb2690a9 3375/* Handle software interrupt used during MSI test */
7d12e780 3376static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3377{
3378 struct sky2_hw *hw = dev_id;
3379 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3380
3381 if (status == 0)
3382 return IRQ_NONE;
3383
3384 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3385 hw->msi = 1;
fb2690a9
SH		 3386 wake_up(&hw->msi_wait);
3387 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3388 }
3389 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3390
3391 return IRQ_HANDLED;
3392}
3393
3394/* Test interrupt path by forcing a a software IRQ */
3395static int __devinit sky2_test_msi(struct sky2_hw *hw)
3396{
3397 struct pci_dev *pdev = hw->pdev;
3398 int err;
3399
bb507fe1
SH		 3400 init_waitqueue_head (&hw->msi_wait);
3401
fb2690a9
SH		 3402 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3403
b0a20ded 3404 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3405 if (err) {
b02a9258 3406 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3407 return err;
3408 }
3409
fb2690a9 3410 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3411 sky2_read8(hw, B0_CTST);
fb2690a9 3412
b0a20ded 3413 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3414
b0a20ded 3415 if (!hw->msi) {
fb2690a9 3416 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3417 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3418 "switching to INTx mode.\n");
fb2690a9
SH		 3419
3420 err = -EOPNOTSUPP;
3421 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3422 }
3423
3424 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3425 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3426
3427 free_irq(pdev->irq, hw);
3428
3429 return err;
3430}
3431
e3173832
SH		 3432static int __devinit pci_wake_enabled(struct pci_dev *dev)
3433{
3434 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3435 u16 value;
3436
3437 if (!pm)
3438 return 0;
3439 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3440 return 0;
3441 return value & PCI_PM_CTRL_PME_ENABLE;
3442}
3443
cd28ab6a
SH		 3444static int __devinit sky2_probe(struct pci_dev *pdev,
3445 const struct pci_device_id *ent)
3446{
7f60c64b 3447 struct net_device *dev;
cd28ab6a 3448 struct sky2_hw *hw;
e3173832 3449 int err, using_dac = 0, wol_default;
cd28ab6a 3450
793b883e
SH		 3451 err = pci_enable_device(pdev);
3452 if (err) {
b02a9258 3453 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3454 goto err_out;
3455 }
3456
793b883e
SH		 3457 err = pci_request_regions(pdev, DRV_NAME);
3458 if (err) {
b02a9258 3459 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
793b883e 3460 goto err_out;
cd28ab6a
SH		 3461 }
3462
3463 pci_set_master(pdev);
3464
d1f3d4dd
SH		 3465 if (sizeof(dma_addr_t) > sizeof(u32) &&
3466 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3467 using_dac = 1;
3468 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3469 if (err < 0) {
b02a9258
SH		 3470 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3471 "for consistent allocations\n");
d1f3d4dd
SH		 3472 goto err_out_free_regions;
3473 }
d1f3d4dd 3474 } else {
cd28ab6a
SH		 3475 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3476 if (err) {
b02a9258 3477 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3478 goto err_out_free_regions;
3479 }
3480 }
d1f3d4dd 3481
e3173832
SH		 3482 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3483
cd28ab6a 3484 err = -ENOMEM;
6aad85d6 3485 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3486 if (!hw) {
b02a9258 3487 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3488 goto err_out_free_regions;
3489 }
3490
cd28ab6a 3491 hw->pdev = pdev;
cd28ab6a
SH		 3492
3493 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3494 if (!hw->regs) {
b02a9258 3495 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3496 goto err_out_free_hw;
3497 }
3498
56a645cc 3499#ifdef __BIG_ENDIAN
f65b138c
SH		 3500 /* The sk98lin vendor driver uses hardware byte swapping but
3501 * this driver uses software swapping.
3502 */
56a645cc
SH		 3503 {
3504 u32 reg;
56a645cc 3505 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3506 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3507 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3508 }
3509#endif
3510
08c06d8a
SH		 3511 /* ring for status responses */
3512 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3513 &hw->st_dma);
3514 if (!hw->st_le)
3515 goto err_out_iounmap;
3516
e3173832 3517 err = sky2_init(hw);
cd28ab6a 3518 if (err)
793b883e 3519 goto err_out_iounmap;
cd28ab6a 3520
b02a9258 3521 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3522 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3523 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3524 hw->chip_id, hw->chip_rev);
cd28ab6a 3525
e3173832
SH		 3526 sky2_reset(hw);
3527
3528 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3529 if (!dev) {
3530 err = -ENOMEM;
cd28ab6a 3531 goto err_out_free_pci;
7f60c64b 3532 }
cd28ab6a 3533
9fa1b1f3
SH		 3534 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3535 err = sky2_test_msi(hw);
3536 if (err == -EOPNOTSUPP)
3537 pci_disable_msi(pdev);
3538 else if (err)
3539 goto err_out_free_netdev;
3540 }
3541
793b883e
SH		 3542 err = register_netdev(dev);
3543 if (err) {
b02a9258 3544 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 3545 goto err_out_free_netdev;
3546 }
3547
b0a20ded
SH		 3548 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3549 dev->name, hw);
9fa1b1f3 3550 if (err) {
b02a9258 3551 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 3552 goto err_out_unregister;
3553 }
3554 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3555
cd28ab6a
SH		 3556 sky2_show_addr(dev);
3557
7f60c64b 3558 if (hw->ports > 1) {
3559 struct net_device *dev1;
3560
e3173832 3561 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 3562 if (!dev1)
3563 dev_warn(&pdev->dev, "allocation for second device failed\n");
3564 else if ((err = register_netdev(dev1))) {
3565 dev_warn(&pdev->dev,
3566 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 3567 hw->dev[1] = NULL;
3568 free_netdev(dev1);
b02a9258
SH		 3569 } else
3570 sky2_show_addr(dev1);
cd28ab6a
SH		 3571 }
3572
01bd7564 3573 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3574 sky2_idle_start(hw);
d27ed387 3575
793b883e
SH		 3576 pci_set_drvdata(pdev, hw);
3577
cd28ab6a
SH		 3578 return 0;
3579
793b883e 3580err_out_unregister:
b0a20ded
SH		 3581 if (hw->msi)
3582 pci_disable_msi(pdev);
793b883e 3583 unregister_netdev(dev);
cd28ab6a
SH		 3584err_out_free_netdev:
3585 free_netdev(dev);
cd28ab6a 3586err_out_free_pci:
793b883e 3587 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3588 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3589err_out_iounmap:
3590 iounmap(hw->regs);
3591err_out_free_hw:
3592 kfree(hw);
3593err_out_free_regions:
3594 pci_release_regions(pdev);
cd28ab6a 3595 pci_disable_device(pdev);
cd28ab6a
SH		 3596err_out:
3597 return err;
3598}
3599
3600static void __devexit sky2_remove(struct pci_dev *pdev)
3601{
793b883e 3602 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3603 struct net_device *dev0, *dev1;
3604
793b883e 3605 if (!hw)
cd28ab6a
SH		 3606 return;
3607
d27ed387
SH		 3608 del_timer_sync(&hw->idle_timer);
3609
3610 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3611 synchronize_irq(hw->pdev->irq);
3612
cd28ab6a 3613 dev0 = hw->dev[0];
793b883e
SH		 3614 dev1 = hw->dev[1];
3615 if (dev1)
3616 unregister_netdev(dev1);
cd28ab6a
SH		 3617 unregister_netdev(dev0);
3618
ae306cca
SH		 3619 sky2_power_aux(hw);
3620
cd28ab6a 3621 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3622 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3623 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3624
3625 free_irq(pdev->irq, hw);
b0a20ded
SH		 3626 if (hw->msi)
3627 pci_disable_msi(pdev);
793b883e 3628 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3629 pci_release_regions(pdev);
3630 pci_disable_device(pdev);
793b883e 3631
cd28ab6a
SH		 3632 if (dev1)
3633 free_netdev(dev1);
3634 free_netdev(dev0);
3635 iounmap(hw->regs);
3636 kfree(hw);
5afa0a9c 3637
cd28ab6a
SH		 3638 pci_set_drvdata(pdev, NULL);
3639}
3640
3641#ifdef CONFIG_PM
3642static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3643{
793b883e 3644 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 3645 int i, wol = 0;
cd28ab6a 3646
eb35cf60 3647 del_timer_sync(&hw->idle_timer);
6a5706b9 3648 netif_poll_disable(hw->dev[0]);
eb35cf60 3649
f05267e7 3650 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3651 struct net_device *dev = hw->dev[i];
e3173832 3652 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3653
e3173832 3654 if (netif_running(dev))
5afa0a9c 3655 sky2_down(dev);
e3173832
SH		 3656
3657 if (sky2->wol)
3658 sky2_wol_init(sky2);
3659
3660 wol |= sky2->wol;
cd28ab6a
SH		 3661 }
3662
8ab8fca2 3663 sky2_write32(hw, B0_IMSK, 0);
ae306cca 3664 sky2_power_aux(hw);
e3173832 3665
d374c1c1 3666 pci_save_state(pdev);
e3173832 3667 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 3668 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3669
2ccc99b7 3670 return 0;
cd28ab6a
SH		 3671}
3672
3673static int sky2_resume(struct pci_dev *pdev)
3674{
793b883e 3675 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3676 int i, err;
cd28ab6a 3677
ae306cca
SH		 3678 err = pci_set_power_state(pdev, PCI_D0);
3679 if (err)
3680 goto out;
3681
3682 err = pci_restore_state(pdev);
3683 if (err)
3684 goto out;
3685
cd28ab6a 3686 pci_enable_wake(pdev, PCI_D0, 0);
e3173832 3687 sky2_reset(hw);
cd28ab6a 3688
8ab8fca2
SH		 3689 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3690
f05267e7 3691 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3692 struct net_device *dev = hw->dev[i];
6a5706b9 3693 if (netif_running(dev)) {
08c06d8a
SH		 3694 err = sky2_up(dev);
3695 if (err) {
3696 printk(KERN_ERR PFX "%s: could not up: %d\n",
3697 dev->name, err);
3698 dev_close(dev);
eb35cf60 3699 goto out;
5afa0a9c 3700 }
cd28ab6a
SH		 3701 }
3702 }
eb35cf60 3703
6a5706b9 3704 netif_poll_enable(hw->dev[0]);
eb35cf60 3705 sky2_idle_start(hw);
ae306cca 3706 return 0;
08c06d8a 3707out:
b02a9258 3708 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 3709 pci_disable_device(pdev);
08c06d8a 3710 return err;
cd28ab6a
SH		 3711}
3712#endif
3713
e3173832
SH		 3714static void sky2_shutdown(struct pci_dev *pdev)
3715{
3716 struct sky2_hw *hw = pci_get_drvdata(pdev);
3717 int i, wol = 0;
3718
3719 del_timer_sync(&hw->idle_timer);
3720 netif_poll_disable(hw->dev[0]);
3721
3722 for (i = 0; i < hw->ports; i++) {
3723 struct net_device *dev = hw->dev[i];
3724 struct sky2_port *sky2 = netdev_priv(dev);
3725
3726 if (sky2->wol) {
3727 wol = 1;
3728 sky2_wol_init(sky2);
3729 }
3730 }
3731
3732 if (wol)
3733 sky2_power_aux(hw);
3734
3735 pci_enable_wake(pdev, PCI_D3hot, wol);
3736 pci_enable_wake(pdev, PCI_D3cold, wol);
3737
3738 pci_disable_device(pdev);
3739 pci_set_power_state(pdev, PCI_D3hot);
3740
3741}
3742
cd28ab6a 3743static struct pci_driver sky2_driver = {
793b883e
SH		 3744 .name = DRV_NAME,
3745 .id_table = sky2_id_table,
3746 .probe = sky2_probe,
3747 .remove = __devexit_p(sky2_remove),
cd28ab6a 3748#ifdef CONFIG_PM
793b883e
SH		 3749 .suspend = sky2_suspend,
3750 .resume = sky2_resume,
cd28ab6a 3751#endif
e3173832 3752 .shutdown = sky2_shutdown,
cd28ab6a
SH		 3753};
3754
3755static int __init sky2_init_module(void)
3756{
50241c4c 3757 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3758}
3759
3760static void __exit sky2_cleanup_module(void)
3761{
3762 pci_unregister_driver(&sky2_driver);
3763}
3764
3765module_init(sky2_init_module);
3766module_exit(sky2_cleanup_module);
3767
3768MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 3769MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 3770MODULE_LICENSE("GPL");
5f4f9dc1 3771MODULE_VERSION(DRV_VERSION);
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