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atl1: disable broken 64-bit DMA
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
c2cb71fa 54#define DRV_VERSION "1.17"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 133 { 0 }
134};
793b883e 135
cd28ab6a
SH		 136MODULE_DEVICE_TABLE(pci, sky2_id_table);
137
138/* Avoid conditionals by using array */
139static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
140static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 141static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 142
92f965e8
SH		 143/* This driver supports yukon2 chipset only */
144static const char *yukon2_name[] = {
145 "XL", /* 0xb3 */
146 "EC Ultra", /* 0xb4 */
93745494 147 "Extreme", /* 0xb5 */
92f965e8
SH		 148 "EC", /* 0xb6 */
149 "FE", /* 0xb7 */
793b883e
SH		 150};
151
793b883e 152/* Access to external PHY */
ef743d33 153static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 154{
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 162 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 163 return 0;
793b883e 164 udelay(1);
cd28ab6a 165 }
ef743d33 166
793b883e 167 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 168 return -ETIMEDOUT;
cd28ab6a
SH		 169}
170
ef743d33 171static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 172{
173 int i;
174
793b883e 175 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 176 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
177
178 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 179 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
180 *val = gma_read16(hw, port, GM_SMI_DATA);
181 return 0;
182 }
183
793b883e 184 udelay(1);
cd28ab6a
SH		 185 }
186
ef743d33
SH		 187 return -ETIMEDOUT;
188}
189
190static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
191{
192 u16 v;
193
194 if (__gm_phy_read(hw, port, reg, &v) != 0)
195 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
196 return v;
cd28ab6a
SH		 197}
198
5afa0a9c 199
ae306cca
SH		 200static void sky2_power_on(struct sky2_hw *hw)
201{
202 /* switch power to VCC (WA for VAUX problem) */
203 sky2_write8(hw, B0_POWER_CTRL,
204 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 205
ae306cca
SH		 206 /* disable Core Clock Division, */
207 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 208
ae306cca
SH		 209 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
210 /* enable bits are inverted */
211 sky2_write8(hw, B2_Y2_CLK_GATE,
212 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
213 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
214 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
215 else
216 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 217
b2345773
SH		 218 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
219 hw->chip_id == CHIP_ID_YUKON_EX) {
fc99fe06 220 u32 reg;
5afa0a9c 221
b2345773
SH		 222 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
223
fc99fe06
SH		 224 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
225 /* set all bits to 0 except bits 15..12 and 8 */
226 reg &= P_ASPM_CONTROL_MSK;
227 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
228
229 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
230 /* set all bits to 0 except bits 28 & 27 */
231 reg &= P_CTL_TIM_VMAIN_AV_MSK;
232 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
233
234 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 235
236 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
237 reg = sky2_read32(hw, B2_GP_IO);
238 reg |= GLB_GPIO_STAT_RACE_DIS;
239 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 240
241 sky2_read32(hw, B2_GP_IO);
5afa0a9c 242 }
ae306cca 243}
5afa0a9c 244
ae306cca
SH		 245static void sky2_power_aux(struct sky2_hw *hw)
246{
247 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
248 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
249 else
250 /* enable bits are inverted */
251 sky2_write8(hw, B2_Y2_CLK_GATE,
252 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
253 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
254 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
255
256 /* switch power to VAUX */
257 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
258 sky2_write8(hw, B0_POWER_CTRL,
259 (PC_VAUX_ENA | PC_VCC_ENA |
260 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 261}
262
d3bcfbeb 263static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 264{
265 u16 reg;
266
267 /* disable all GMAC IRQ's */
268 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
269 /* disable PHY IRQs */
270 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 271
cd28ab6a
SH		 272 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
273 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
274 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
275 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
276
277 reg = gma_read16(hw, port, GM_RX_CTRL);
278 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
279 gma_write16(hw, port, GM_RX_CTRL, reg);
280}
281
16ad91e1
SH		 282/* flow control to advertise bits */
283static const u16 copper_fc_adv[] = {
284 [FC_NONE] = 0,
285 [FC_TX] = PHY_M_AN_ASP,
286 [FC_RX] = PHY_M_AN_PC,
287 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
288};
289
290/* flow control to advertise bits when using 1000BaseX */
291static const u16 fiber_fc_adv[] = {
292 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
293 [FC_TX] = PHY_M_P_ASYM_MD_X,
294 [FC_RX] = PHY_M_P_SYM_MD_X,
295 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
296};
297
298/* flow control to GMA disable bits */
299static const u16 gm_fc_disable[] = {
300 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
301 [FC_TX] = GM_GPCR_FC_RX_DIS,
302 [FC_RX] = GM_GPCR_FC_TX_DIS,
303 [FC_BOTH] = 0,
304};
305
306
cd28ab6a
SH		 307static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
308{
309 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 310 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 311
93745494
SH		 312 if (sky2->autoneg == AUTONEG_ENABLE
313 && !(hw->chip_id == CHIP_ID_YUKON_XL
314 || hw->chip_id == CHIP_ID_YUKON_EC_U
315 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 316 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
317
318 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 319 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 320 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
321
53419c68 322 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 323 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 324 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 325 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
326 else
53419c68
SH		 327 /* set master & slave downshift counter to 1x */
328 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 329
330 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
331 }
332
333 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 334 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 335 if (hw->chip_id == CHIP_ID_YUKON_FE) {
336 /* enable automatic crossover */
337 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
338 } else {
339 /* disable energy detect */
340 ctrl &= ~PHY_M_PC_EN_DET_MSK;
341
342 /* enable automatic crossover */
343 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
344
53419c68 345 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494
SH		 346 if (sky2->autoneg == AUTONEG_ENABLE
347 && (hw->chip_id == CHIP_ID_YUKON_XL
348 || hw->chip_id == CHIP_ID_YUKON_EC_U
349 || hw->chip_id == CHIP_ID_YUKON_EX)) {
53419c68 350 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 351 ctrl &= ~PHY_M_PC_DSC_MSK;
352 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
353 }
354 }
cd28ab6a
SH		 355 } else {
356 /* workaround for deviation #4.88 (CRC errors) */
357 /* disable Automatic Crossover */
358
359 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 360 }
cd28ab6a 361
b89165f2
SH		 362 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
363
364 /* special setup for PHY 88E1112 Fiber */
365 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
366 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 367
b89165f2
SH		 368 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
369 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
370 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
371 ctrl &= ~PHY_M_MAC_MD_MSK;
372 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
373 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
374
375 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 376 /* select page 1 to access Fiber registers */
377 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 378
379 /* for SFP-module set SIGDET polarity to low */
380 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
381 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 382 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 383 }
b89165f2
SH		 384
385 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 386 }
387
7800fddc 388 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 389 ct1000 = 0;
390 adv = PHY_AN_CSMA;
2eaba1a2 391 reg = 0;
cd28ab6a
SH		 392
393 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 394 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 395 if (sky2->advertising & ADVERTISED_1000baseT_Full)
396 ct1000 |= PHY_M_1000C_AFD;
397 if (sky2->advertising & ADVERTISED_1000baseT_Half)
398 ct1000 |= PHY_M_1000C_AHD;
399 if (sky2->advertising & ADVERTISED_100baseT_Full)
400 adv |= PHY_M_AN_100_FD;
401 if (sky2->advertising & ADVERTISED_100baseT_Half)
402 adv |= PHY_M_AN_100_HD;
403 if (sky2->advertising & ADVERTISED_10baseT_Full)
404 adv |= PHY_M_AN_10_FD;
405 if (sky2->advertising & ADVERTISED_10baseT_Half)
406 adv |= PHY_M_AN_10_HD;
709c6e7b 407
16ad91e1 408 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 409 } else { /* special defines for FIBER (88E1040S only) */
410 if (sky2->advertising & ADVERTISED_1000baseT_Full)
411 adv |= PHY_M_AN_1000X_AFD;
412 if (sky2->advertising & ADVERTISED_1000baseT_Half)
413 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 414
16ad91e1 415 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 416 }
cd28ab6a
SH		 417
418 /* Restart Auto-negotiation */
419 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
420 } else {
421 /* forced speed/duplex settings */
422 ct1000 = PHY_M_1000C_MSE;
423
2eaba1a2
SH		 424 /* Disable auto update for duplex flow control and speed */
425 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 426
427 switch (sky2->speed) {
428 case SPEED_1000:
429 ctrl |= PHY_CT_SP1000;
2eaba1a2 430 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 431 break;
432 case SPEED_100:
433 ctrl |= PHY_CT_SP100;
2eaba1a2 434 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 435 break;
436 }
437
2eaba1a2
SH		 438 if (sky2->duplex == DUPLEX_FULL) {
439 reg |= GM_GPCR_DUP_FULL;
440 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 441 } else if (sky2->speed < SPEED_1000)
442 sky2->flow_mode = FC_NONE;
2eaba1a2 443
2eaba1a2 444
16ad91e1 445 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 446
447 /* Forward pause packets to GMAC? */
16ad91e1 448 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 449 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
450 else
451 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 452 }
453
2eaba1a2
SH		 454 gma_write16(hw, port, GM_GP_CTRL, reg);
455
cd28ab6a
SH		 456 if (hw->chip_id != CHIP_ID_YUKON_FE)
457 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
458
459 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
460 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
461
462 /* Setup Phy LED's */
463 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
464 ledover = 0;
465
466 switch (hw->chip_id) {
467 case CHIP_ID_YUKON_FE:
468 /* on 88E3082 these bits are at 11..9 (shifted left) */
469 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
470
471 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
472
473 /* delete ACT LED control bits */
474 ctrl &= ~PHY_M_FELP_LED1_MSK;
475 /* change ACT LED control to blink mode */
476 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
477 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
478 break;
479
480 case CHIP_ID_YUKON_XL:
793b883e 481 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 482
483 /* select page 3 to access LED control register */
484 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
485
486 /* set LED Function Control register */
ed6d32c7
SH		 487 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
488 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
489 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
490 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
491 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 492
493 /* set Polarity Control register */
494 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 495 (PHY_M_POLC_LS1_P_MIX(4) |
496 PHY_M_POLC_IS0_P_MIX(4) |
497 PHY_M_POLC_LOS_CTRL(2) |
498 PHY_M_POLC_INIT_CTRL(2) |
499 PHY_M_POLC_STA1_CTRL(2) |
500 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 501
502 /* restore page register */
793b883e 503 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 504 break;
93745494 505
ed6d32c7 506 case CHIP_ID_YUKON_EC_U:
93745494 507 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 508 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
509
510 /* select page 3 to access LED control register */
511 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
512
513 /* set LED Function Control register */
514 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
515 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
516 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
517 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
518 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
519
520 /* set Blink Rate in LED Timer Control Register */
521 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
522 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
523 /* restore page register */
524 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
525 break;
cd28ab6a
SH		 526
527 default:
528 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
529 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
530 /* turn off the Rx LED (LED_RX) */
0efdf262 531 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 532 }
533
9467a8fc
SH		 534 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
535 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 536 /* apply fixes in PHY AFE */
ed6d32c7
SH		 537 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
538
977bdf06 539 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 540 gm_phy_write(hw, port, 0x18, 0xaa99);
541 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 542
977bdf06 543 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 544 gm_phy_write(hw, port, 0x18, 0xa204);
545 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 546
547 /* set page register to 0 */
9467a8fc 548 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
93745494 549 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 550 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 551
977bdf06
SH		 552 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
553 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 554 ledover |= PHY_M_LED_MO_100;
977bdf06 555 }
cd28ab6a 556
977bdf06
SH		 557 if (ledover)
558 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
559
560 }
2eaba1a2 561
d571b694 562 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 563 if (sky2->autoneg == AUTONEG_ENABLE)
564 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
565 else
566 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
567}
568
d3bcfbeb
SH		 569static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
570{
571 u32 reg1;
572 static const u32 phy_power[]
573 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
574
575 /* looks like this XL is back asswards .. */
576 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
577 onoff = !onoff;
578
aed2cec4 579 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 580 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 581 if (onoff)
582 /* Turn off phy power saving */
583 reg1 &= ~phy_power[port];
584 else
585 reg1 |= phy_power[port];
586
587 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 588 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 589 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 590 udelay(100);
591}
592
1b537565
SH		 593/* Force a renegotiation */
594static void sky2_phy_reinit(struct sky2_port *sky2)
595{
e07b1aa8 596 spin_lock_bh(&sky2->phy_lock);
1b537565 597 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 598 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 599}
600
e3173832
SH		 601/* Put device in state to listen for Wake On Lan */
602static void sky2_wol_init(struct sky2_port *sky2)
603{
604 struct sky2_hw *hw = sky2->hw;
605 unsigned port = sky2->port;
606 enum flow_control save_mode;
607 u16 ctrl;
608 u32 reg1;
609
610 /* Bring hardware out of reset */
611 sky2_write16(hw, B0_CTST, CS_RST_CLR);
612 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
613
614 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
615 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
616
617 /* Force to 10/100
618 * sky2_reset will re-enable on resume
619 */
620 save_mode = sky2->flow_mode;
621 ctrl = sky2->advertising;
622
623 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
624 sky2->flow_mode = FC_NONE;
625 sky2_phy_power(hw, port, 1);
626 sky2_phy_reinit(sky2);
627
628 sky2->flow_mode = save_mode;
629 sky2->advertising = ctrl;
630
631 /* Set GMAC to no flow control and auto update for speed/duplex */
632 gma_write16(hw, port, GM_GP_CTRL,
633 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
634 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
635
636 /* Set WOL address */
637 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
638 sky2->netdev->dev_addr, ETH_ALEN);
639
640 /* Turn on appropriate WOL control bits */
641 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
642 ctrl = 0;
643 if (sky2->wol & WAKE_PHY)
644 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
645 else
646 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
647
648 if (sky2->wol & WAKE_MAGIC)
649 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
650 else
651 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
652
653 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
654 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
655
656 /* Turn on legacy PCI-Express PME mode */
657 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
658 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
659 reg1 |= PCI_Y2_PME_LEGACY;
660 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
661 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
662
663 /* block receiver */
664 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
665
666}
667
69161611
SH		 668static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
669{
670 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev != CHIP_REV_YU_EX_A0) {
671 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
672 TX_STFW_ENA |
673 (hw->dev[port]->mtu > ETH_DATA_LEN) ? TX_JUMBO_ENA : TX_JUMBO_DIS);
674 } else {
675 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
676 /* set Tx GMAC FIFO Almost Empty Threshold */
677 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
678 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
679
680 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
681 TX_JUMBO_ENA | TX_STFW_DIS);
682
683 /* Can't do offload because of lack of store/forward */
684 hw->dev[port]->features &= ~(NETIF_F_TSO | NETIF_F_SG
685 | NETIF_F_ALL_CSUM);
686 } else
687 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
688 TX_JUMBO_DIS | TX_STFW_ENA);
689 }
690}
691
cd28ab6a
SH		 692static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
693{
694 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
695 u16 reg;
25cccecc 696 u32 rx_reg;
cd28ab6a
SH		 697 int i;
698 const u8 *addr = hw->dev[port]->dev_addr;
699
f350339c
SH		 700 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
701 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 702
703 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
704
793b883e 705 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 706 /* WA DEV_472 -- looks like crossed wires on port 2 */
707 /* clear GMAC 1 Control reset */
708 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
709 do {
710 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
711 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
712 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
713 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
714 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
715 }
716
793b883e 717 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 718
2eaba1a2
SH		 719 /* Enable Transmit FIFO Underrun */
720 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
721
e07b1aa8 722 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 723 sky2_phy_init(hw, port);
e07b1aa8 724 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 725
726 /* MIB clear */
727 reg = gma_read16(hw, port, GM_PHY_ADDR);
728 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
729
43f2f104
SH		 730 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
731 gma_read16(hw, port, i);
cd28ab6a
SH		 732 gma_write16(hw, port, GM_PHY_ADDR, reg);
733
734 /* transmit control */
735 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
736
737 /* receive control reg: unicast + multicast + no FCS */
738 gma_write16(hw, port, GM_RX_CTRL,
793b883e 739 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 740
741 /* transmit flow control */
742 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
743
744 /* transmit parameter */
745 gma_write16(hw, port, GM_TX_PARAM,
746 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
747 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
748 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
749 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
750
751 /* serial mode register */
752 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 753 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 754
6b1a3aef 755 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 756 reg |= GM_SMOD_JUMBO_ENA;
757
758 gma_write16(hw, port, GM_SERIAL_MODE, reg);
759
cd28ab6a
SH		 760 /* virtual address for data */
761 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
762
793b883e
SH		 763 /* physical address: used for pause frames */
764 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
765
766 /* ignore counter overflows */
cd28ab6a
SH		 767 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
768 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
769 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
770
771 /* Configure Rx MAC FIFO */
772 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 773 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
69161611 774 if (hw->chip_id == CHIP_ID_YUKON_EX)
25cccecc 775 rx_reg |= GMF_RX_OVER_ON;
69161611 776
25cccecc 777 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 778
d571b694 779 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 780 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 781
8df9a876
SH		 782 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
783 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 784
785 /* Configure Tx MAC FIFO */
786 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
787 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 788
93745494 789 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 790 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 791 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 792
69161611 793 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 794 }
795
cd28ab6a
SH		 796}
797
67712901
SH		 798/* Assign Ram Buffer allocation to queue */
799static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 800{
67712901
SH		 801 u32 end;
802
803 /* convert from K bytes to qwords used for hw register */
804 start *= 1024/8;
805 space *= 1024/8;
806 end = start + space - 1;
793b883e 807
cd28ab6a
SH		 808 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
809 sky2_write32(hw, RB_ADDR(q, RB_START), start);
810 sky2_write32(hw, RB_ADDR(q, RB_END), end);
811 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
812 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
813
814 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 815 u32 tp = space - space/4;
793b883e 816
1c28f6ba
SH		 817 /* On receive queue's set the thresholds
818 * give receiver priority when > 3/4 full
819 * send pause when down to 2K
820 */
821 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
822 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 823
1c28f6ba
SH		 824 tp = space - 2048/8;
825 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
826 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 827 } else {
828 /* Enable store & forward on Tx queue's because
829 * Tx FIFO is only 1K on Yukon
830 */
831 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
832 }
833
834 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 835 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 836}
837
cd28ab6a 838/* Setup Bus Memory Interface */
af4ed7e6 839static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 840{
841 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
842 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
843 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 844 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 845}
846
cd28ab6a
SH		 847/* Setup prefetch unit registers. This is the interface between
848 * hardware and driver list elements
849 */
8cc048e3 850static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 851 u64 addr, u32 last)
852{
cd28ab6a
SH		 853 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
854 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
855 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
856 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
857 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
858 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 859
860 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 861}
862
793b883e
SH		 863static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
864{
865 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
866
cb5d9547 867 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 868 le->ctrl = 0;
793b883e
SH		 869 return le;
870}
cd28ab6a 871
291ea614
SH		 872static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
873 struct sky2_tx_le *le)
874{
875 return sky2->tx_ring + (le - sky2->tx_le);
876}
877
290d4de5
SH		 878/* Update chip's next pointer */
879static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 880{
50432cb5 881 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 882 wmb();
50432cb5
SH		 883 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
884
885 /* Synchronize I/O on since next processor may write to tail */
886 mmiowb();
cd28ab6a
SH		 887}
888
793b883e 889
cd28ab6a
SH		 890static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
891{
892 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 893 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 894 le->ctrl = 0;
cd28ab6a
SH		 895 return le;
896}
897
14d0263f
SH		 898/* Build description to hardware for one receive segment */
899static void sky2_rx_add(struct sky2_port *sky2, u8 op,
900 dma_addr_t map, unsigned len)
cd28ab6a
SH		 901{
902 struct sky2_rx_le *le;
36eb0c71 903 u32 hi = upper_32_bits(map);
cd28ab6a 904
793b883e 905 if (sky2->rx_addr64 != hi) {
cd28ab6a 906 le = sky2_next_rx(sky2);
793b883e 907 le->addr = cpu_to_le32(hi);
cd28ab6a 908 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 909 sky2->rx_addr64 = upper_32_bits(map + len);
cd28ab6a 910 }
793b883e 911
cd28ab6a 912 le = sky2_next_rx(sky2);
734d1868
SH		 913 le->addr = cpu_to_le32((u32) map);
914 le->length = cpu_to_le16(len);
14d0263f 915 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 916}
917
14d0263f
SH		 918/* Build description to hardware for one possibly fragmented skb */
919static void sky2_rx_submit(struct sky2_port *sky2,
920 const struct rx_ring_info *re)
921{
922 int i;
923
924 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
925
926 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
927 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
928}
929
930
931static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
932 unsigned size)
933{
934 struct sk_buff *skb = re->skb;
935 int i;
936
937 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
938 pci_unmap_len_set(re, data_size, size);
939
940 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
941 re->frag_addr[i] = pci_map_page(pdev,
942 skb_shinfo(skb)->frags[i].page,
943 skb_shinfo(skb)->frags[i].page_offset,
944 skb_shinfo(skb)->frags[i].size,
945 PCI_DMA_FROMDEVICE);
946}
947
948static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
949{
950 struct sk_buff *skb = re->skb;
951 int i;
952
953 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
954 PCI_DMA_FROMDEVICE);
955
956 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
957 pci_unmap_page(pdev, re->frag_addr[i],
958 skb_shinfo(skb)->frags[i].size,
959 PCI_DMA_FROMDEVICE);
960}
793b883e 961
cd28ab6a
SH		 962/* Tell chip where to start receive checksum.
963 * Actually has two checksums, but set both same to avoid possible byte
964 * order problems.
965 */
793b883e 966static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 967{
968 struct sky2_rx_le *le;
969
69161611
SH		 970 if (sky2->hw->chip_id != CHIP_ID_YUKON_EX) {
971 le = sky2_next_rx(sky2);
972 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
973 le->ctrl = 0;
974 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 975
69161611
SH		 976 sky2_write32(sky2->hw,
977 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
978 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
979 }
cd28ab6a
SH		 980
981}
982
6b1a3aef
SH		 983/*
984 * The RX Stop command will not work for Yukon-2 if the BMU does not
985 * reach the end of packet and since we can't make sure that we have
986 * incoming data, we must reset the BMU while it is not doing a DMA
987 * transfer. Since it is possible that the RX path is still active,
988 * the RX RAM buffer will be stopped first, so any possible incoming
989 * data will not trigger a DMA. After the RAM buffer is stopped, the
990 * BMU is polled until any DMA in progress is ended and only then it
991 * will be reset.
992 */
993static void sky2_rx_stop(struct sky2_port *sky2)
994{
995 struct sky2_hw *hw = sky2->hw;
996 unsigned rxq = rxqaddr[sky2->port];
997 int i;
998
999 /* disable the RAM Buffer receive queue */
1000 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1001
1002 for (i = 0; i < 0xffff; i++)
1003 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1004 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1005 goto stopped;
1006
1007 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1008 sky2->netdev->name);
1009stopped:
1010 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1011
1012 /* reset the Rx prefetch unit */
1013 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1014 mmiowb();
6b1a3aef 1015}
793b883e 1016
d571b694 1017/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1018static void sky2_rx_clean(struct sky2_port *sky2)
1019{
1020 unsigned i;
1021
1022 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1023 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1024 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1025
1026 if (re->skb) {
14d0263f 1027 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1028 kfree_skb(re->skb);
1029 re->skb = NULL;
1030 }
1031 }
1032}
1033
ef743d33
SH		 1034/* Basic MII support */
1035static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1036{
1037 struct mii_ioctl_data *data = if_mii(ifr);
1038 struct sky2_port *sky2 = netdev_priv(dev);
1039 struct sky2_hw *hw = sky2->hw;
1040 int err = -EOPNOTSUPP;
1041
1042 if (!netif_running(dev))
1043 return -ENODEV; /* Phy still in reset */
1044
d89e1343 1045 switch (cmd) {
ef743d33
SH		 1046 case SIOCGMIIPHY:
1047 data->phy_id = PHY_ADDR_MARV;
1048
1049 /* fallthru */
1050 case SIOCGMIIREG: {
1051 u16 val = 0;
91c86df5 1052
e07b1aa8 1053 spin_lock_bh(&sky2->phy_lock);
ef743d33 1054 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1055 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1056
ef743d33
SH		 1057 data->val_out = val;
1058 break;
1059 }
1060
1061 case SIOCSMIIREG:
1062 if (!capable(CAP_NET_ADMIN))
1063 return -EPERM;
1064
e07b1aa8 1065 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1066 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1067 data->val_in);
e07b1aa8 1068 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1069 break;
1070 }
1071 return err;
1072}
1073
d1f13708
SH		 1074#ifdef SKY2_VLAN_TAG_USED
1075static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1076{
1077 struct sky2_port *sky2 = netdev_priv(dev);
1078 struct sky2_hw *hw = sky2->hw;
1079 u16 port = sky2->port;
d1f13708 1080
2bb8c262 1081 netif_tx_lock_bh(dev);
3d4e66f5 1082 netif_poll_disable(sky2->hw->dev[0]);
d1f13708 1083
d1f13708 1084 sky2->vlgrp = grp;
3d4e66f5
SH		 1085 if (grp) {
1086 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1087 RX_VLAN_STRIP_ON);
1088 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1089 TX_VLAN_TAG_ON);
1090 } else {
1091 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1092 RX_VLAN_STRIP_OFF);
1093 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1094 TX_VLAN_TAG_OFF);
1095 }
d1f13708 1096
3d4e66f5 1097 netif_poll_enable(sky2->hw->dev[0]);
2bb8c262 1098 netif_tx_unlock_bh(dev);
d1f13708
SH		 1099}
1100#endif
1101
82788c7a 1102/*
14d0263f
SH		 1103 * Allocate an skb for receiving. If the MTU is large enough
1104 * make the skb non-linear with a fragment list of pages.
1105 *
82788c7a
SH		 1106 * It appears the hardware has a bug in the FIFO logic that
1107 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1108 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1109 * aligned except if slab debugging is enabled.
82788c7a 1110 */
14d0263f 1111static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1112{
1113 struct sk_buff *skb;
14d0263f
SH		 1114 unsigned long p;
1115 int i;
82788c7a 1116
14d0263f
SH		 1117 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1118 if (!skb)
1119 goto nomem;
1120
1121 p = (unsigned long) skb->data;
1122 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1123
1124 for (i = 0; i < sky2->rx_nfrags; i++) {
1125 struct page *page = alloc_page(GFP_ATOMIC);
1126
1127 if (!page)
1128 goto free_partial;
1129 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1130 }
1131
1132 return skb;
14d0263f
SH		 1133free_partial:
1134 kfree_skb(skb);
1135nomem:
1136 return NULL;
82788c7a
SH		 1137}
1138
55c9dd35
SH		 1139static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1140{
1141 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1142}
1143
cd28ab6a
SH		 1144/*
1145 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1146 * Normal case this ends up creating one list element for skb
1147 * in the receive ring. Worst case if using large MTU and each
1148 * allocation falls on a different 64 bit region, that results
1149 * in 6 list elements per ring entry.
1150 * One element is used for checksum enable/disable, and one
1151 * extra to avoid wrap.
cd28ab6a 1152 */
6b1a3aef 1153static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1154{
6b1a3aef 1155 struct sky2_hw *hw = sky2->hw;
14d0263f 1156 struct rx_ring_info *re;
6b1a3aef 1157 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1158 unsigned i, size, space, thresh;
cd28ab6a 1159
6b1a3aef 1160 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1161 sky2_qset(hw, rxq);
977bdf06 1162
c3905bc4
SH		 1163 /* On PCI express lowering the watermark gives better performance */
1164 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1165 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1166
1167 /* These chips have no ram buffer?
1168 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1169 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1170 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1171 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1172 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1173
6b1a3aef
SH		 1174 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1175
1176 rx_set_checksum(sky2);
14d0263f
SH		 1177
1178 /* Space needed for frame data + headers rounded up */
f957da2a 1179 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1180
1181 /* Stopping point for hardware truncation */
1182 thresh = (size - 8) / sizeof(u32);
1183
1184 /* Account for overhead of skb - to avoid order > 0 allocation */
1185 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1186 + sizeof(struct skb_shared_info);
1187
1188 sky2->rx_nfrags = space >> PAGE_SHIFT;
1189 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1190
1191 if (sky2->rx_nfrags != 0) {
1192 /* Compute residue after pages */
1193 space = sky2->rx_nfrags << PAGE_SHIFT;
1194
1195 if (space < size)
1196 size -= space;
1197 else
1198 size = 0;
1199
1200 /* Optimize to handle small packets and headers */
1201 if (size < copybreak)
1202 size = copybreak;
1203 if (size < ETH_HLEN)
1204 size = ETH_HLEN;
1205 }
1206 sky2->rx_data_size = size;
1207
1208 /* Fill Rx ring */
793b883e 1209 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1210 re = sky2->rx_ring + i;
cd28ab6a 1211
14d0263f 1212 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1213 if (!re->skb)
1214 goto nomem;
1215
14d0263f
SH		 1216 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1217 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1218 }
1219
a1433ac4
SH		 1220 /*
1221 * The receiver hangs if it receives frames larger than the
1222 * packet buffer. As a workaround, truncate oversize frames, but
1223 * the register is limited to 9 bits, so if you do frames > 2052
1224 * you better get the MTU right!
1225 */
a1433ac4
SH		 1226 if (thresh > 0x1ff)
1227 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1228 else {
1229 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1230 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1231 }
1232
6b1a3aef 1233 /* Tell chip about available buffers */
55c9dd35 1234 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1235 return 0;
1236nomem:
1237 sky2_rx_clean(sky2);
1238 return -ENOMEM;
1239}
1240
1241/* Bring up network interface. */
1242static int sky2_up(struct net_device *dev)
1243{
1244 struct sky2_port *sky2 = netdev_priv(dev);
1245 struct sky2_hw *hw = sky2->hw;
1246 unsigned port = sky2->port;
67712901 1247 u32 ramsize, imask;
ee7abb04 1248 int cap, err = -ENOMEM;
843a46f4 1249 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1250
ee7abb04
SH		 1251 /*
1252 * On dual port PCI-X card, there is an problem where status
1253 * can be received out of order due to split transactions
843a46f4 1254 */
ee7abb04
SH		 1255 if (otherdev && netif_running(otherdev) &&
1256 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1257 struct sky2_port *osky2 = netdev_priv(otherdev);
1258 u16 cmd;
1259
1260 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1261 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1262 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1263
1264 sky2->rx_csum = 0;
1265 osky2->rx_csum = 0;
1266 }
843a46f4 1267
cd28ab6a
SH		 1268 if (netif_msg_ifup(sky2))
1269 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1270
55d7b4e6
SH		 1271 netif_carrier_off(dev);
1272
cd28ab6a
SH		 1273 /* must be power of 2 */
1274 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1275 TX_RING_SIZE *
1276 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1277 &sky2->tx_le_map);
1278 if (!sky2->tx_le)
1279 goto err_out;
1280
6cdbbdf3 1281 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1282 GFP_KERNEL);
1283 if (!sky2->tx_ring)
1284 goto err_out;
1285 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1286
1287 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1288 &sky2->rx_le_map);
1289 if (!sky2->rx_le)
1290 goto err_out;
1291 memset(sky2->rx_le, 0, RX_LE_BYTES);
1292
291ea614 1293 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1294 GFP_KERNEL);
1295 if (!sky2->rx_ring)
1296 goto err_out;
1297
d3bcfbeb
SH		 1298 sky2_phy_power(hw, port, 1);
1299
cd28ab6a
SH		 1300 sky2_mac_init(hw, port);
1301
67712901
SH		 1302 /* Register is number of 4K blocks on internal RAM buffer. */
1303 ramsize = sky2_read8(hw, B2_E_0) * 4;
1304 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1305
67712901
SH		 1306 if (ramsize > 0) {
1307 u32 rxspace;
cd28ab6a 1308
67712901
SH		 1309 if (ramsize < 16)
1310 rxspace = ramsize / 2;
1311 else
1312 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1313
67712901
SH		 1314 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1315 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1316
1317 /* Make sure SyncQ is disabled */
1318 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1319 RB_RST_SET);
1320 }
793b883e 1321
af4ed7e6 1322 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1323
69161611
SH		 1324 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1325 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1326 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1327
977bdf06 1328 /* Set almost empty threshold */
c2716fb4
SH		 1329 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1330 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1331 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1332
6b1a3aef
SH		 1333 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1334 TX_RING_SIZE - 1);
cd28ab6a 1335
6b1a3aef 1336 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1337 if (err)
1338 goto err_out;
1339
cd28ab6a 1340 /* Enable interrupts from phy/mac for port */
e07b1aa8 1341 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1342 imask |= portirq_msk[port];
e07b1aa8
SH		 1343 sky2_write32(hw, B0_IMSK, imask);
1344
cd28ab6a
SH		 1345 return 0;
1346
1347err_out:
1b537565 1348 if (sky2->rx_le) {
cd28ab6a
SH		 1349 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1350 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1351 sky2->rx_le = NULL;
1352 }
1353 if (sky2->tx_le) {
cd28ab6a
SH		 1354 pci_free_consistent(hw->pdev,
1355 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1356 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1357 sky2->tx_le = NULL;
1358 }
1359 kfree(sky2->tx_ring);
1360 kfree(sky2->rx_ring);
cd28ab6a 1361
1b537565
SH		 1362 sky2->tx_ring = NULL;
1363 sky2->rx_ring = NULL;
cd28ab6a
SH		 1364 return err;
1365}
1366
793b883e
SH		 1367/* Modular subtraction in ring */
1368static inline int tx_dist(unsigned tail, unsigned head)
1369{
cb5d9547 1370 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1371}
cd28ab6a 1372
793b883e
SH		 1373/* Number of list elements available for next tx */
1374static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1375{
793b883e 1376 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1377}
1378
793b883e 1379/* Estimate of number of transmit list elements required */
28bd181a 1380static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1381{
793b883e
SH		 1382 unsigned count;
1383
1384 count = sizeof(dma_addr_t) / sizeof(u32);
1385 count += skb_shinfo(skb)->nr_frags * count;
1386
89114afd 1387 if (skb_is_gso(skb))
793b883e
SH		 1388 ++count;
1389
84fa7933 1390 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1391 ++count;
1392
1393 return count;
cd28ab6a
SH		 1394}
1395
793b883e
SH		 1396/*
1397 * Put one packet in ring for transmit.
1398 * A single packet can generate multiple list elements, and
1399 * the number of ring elements will probably be less than the number
1400 * of list elements used.
1401 */
cd28ab6a
SH		 1402static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1403{
1404 struct sky2_port *sky2 = netdev_priv(dev);
1405 struct sky2_hw *hw = sky2->hw;
d1f13708 1406 struct sky2_tx_le *le = NULL;
6cdbbdf3 1407 struct tx_ring_info *re;
cd28ab6a
SH		 1408 unsigned i, len;
1409 dma_addr_t mapping;
1410 u32 addr64;
1411 u16 mss;
1412 u8 ctrl;
1413
2bb8c262
SH		 1414 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1415 return NETDEV_TX_BUSY;
cd28ab6a 1416
793b883e 1417 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1418 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1419 dev->name, sky2->tx_prod, skb->len);
1420
cd28ab6a
SH		 1421 len = skb_headlen(skb);
1422 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
36eb0c71 1423 addr64 = upper_32_bits(mapping);
793b883e 1424
a018e330 1425 /* Send high bits if changed or crosses boundary */
36eb0c71
SH		 1426 if (addr64 != sky2->tx_addr64 ||
1427 upper_32_bits(mapping + len) != sky2->tx_addr64) {
793b883e 1428 le = get_tx_le(sky2);
f65b138c 1429 le->addr = cpu_to_le32(addr64);
793b883e 1430 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 1431 sky2->tx_addr64 = upper_32_bits(mapping + len);
793b883e 1432 }
cd28ab6a
SH		 1433
1434 /* Check for TCP Segmentation Offload */
7967168c 1435 mss = skb_shinfo(skb)->gso_size;
793b883e 1436 if (mss != 0) {
69161611
SH		 1437 if (hw->chip_id != CHIP_ID_YUKON_EX)
1438 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1439
1440 if (mss != sky2->tx_last_mss) {
1441 le = get_tx_le(sky2);
1442 le->addr = cpu_to_le32(mss);
1443 if (hw->chip_id == CHIP_ID_YUKON_EX)
1444 le->opcode = OP_MSS | HW_OWNER;
1445 else
1446 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1447 sky2->tx_last_mss = mss;
1448 }
cd28ab6a
SH		 1449 }
1450
cd28ab6a 1451 ctrl = 0;
d1f13708
SH		 1452#ifdef SKY2_VLAN_TAG_USED
1453 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1454 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1455 if (!le) {
1456 le = get_tx_le(sky2);
f65b138c 1457 le->addr = 0;
d1f13708 1458 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1459 } else
1460 le->opcode |= OP_VLAN;
1461 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1462 ctrl |= INS_VLAN;
1463 }
1464#endif
1465
1466 /* Handle TCP checksum offload */
84fa7933 1467 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611
SH		 1468 /* On Yukon EX (some versions) encoding change. */
1469 if (hw->chip_id == CHIP_ID_YUKON_EX
1470 && hw->chip_rev != CHIP_REV_YU_EX_B0)
1471 ctrl |= CALSUM; /* auto checksum */
1472 else {
1473 const unsigned offset = skb_transport_offset(skb);
1474 u32 tcpsum;
1475
1476 tcpsum = offset << 16; /* sum start */
1477 tcpsum |= offset + skb->csum_offset; /* sum write */
1478
1479 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1480 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1481 ctrl |= UDPTCP;
1482
1483 if (tcpsum != sky2->tx_tcpsum) {
1484 sky2->tx_tcpsum = tcpsum;
1485
1486 le = get_tx_le(sky2);
1487 le->addr = cpu_to_le32(tcpsum);
1488 le->length = 0; /* initial checksum value */
1489 le->ctrl = 1; /* one packet */
1490 le->opcode = OP_TCPLISW | HW_OWNER;
1491 }
1d179332 1492 }
cd28ab6a
SH		 1493 }
1494
1495 le = get_tx_le(sky2);
f65b138c 1496 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1497 le->length = cpu_to_le16(len);
1498 le->ctrl = ctrl;
793b883e 1499 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1500
291ea614 1501 re = tx_le_re(sky2, le);
cd28ab6a 1502 re->skb = skb;
6cdbbdf3 1503 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1504 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1505
1506 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1507 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1508
1509 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1510 frag->size, PCI_DMA_TODEVICE);
36eb0c71 1511 addr64 = upper_32_bits(mapping);
793b883e
SH		 1512 if (addr64 != sky2->tx_addr64) {
1513 le = get_tx_le(sky2);
f65b138c 1514 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1515 le->ctrl = 0;
1516 le->opcode = OP_ADDR64 | HW_OWNER;
1517 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1518 }
1519
1520 le = get_tx_le(sky2);
f65b138c 1521 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1522 le->length = cpu_to_le16(frag->size);
1523 le->ctrl = ctrl;
793b883e 1524 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1525
291ea614
SH		 1526 re = tx_le_re(sky2, le);
1527 re->skb = skb;
1528 pci_unmap_addr_set(re, mapaddr, mapping);
1529 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1530 }
6cdbbdf3 1531
cd28ab6a
SH		 1532 le->ctrl |= EOP;
1533
97bda706
SH		 1534 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1535 netif_stop_queue(dev);
b19666d9 1536
290d4de5 1537 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1538
cd28ab6a
SH		 1539 dev->trans_start = jiffies;
1540 return NETDEV_TX_OK;
1541}
1542
cd28ab6a 1543/*
793b883e
SH		 1544 * Free ring elements from starting at tx_cons until "done"
1545 *
1546 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1547 * buffers so make sure not to free skb to early.
cd28ab6a 1548 */
d11c13e7 1549static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1550{
d11c13e7 1551 struct net_device *dev = sky2->netdev;
af2a58ac 1552 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1553 unsigned idx;
cd28ab6a 1554
0e3ff6aa 1555 BUG_ON(done >= TX_RING_SIZE);
2224795d 1556
291ea614
SH		 1557 for (idx = sky2->tx_cons; idx != done;
1558 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1559 struct sky2_tx_le *le = sky2->tx_le + idx;
1560 struct tx_ring_info *re = sky2->tx_ring + idx;
1561
1562 switch(le->opcode & ~HW_OWNER) {
1563 case OP_LARGESEND:
1564 case OP_PACKET:
1565 pci_unmap_single(pdev,
1566 pci_unmap_addr(re, mapaddr),
1567 pci_unmap_len(re, maplen),
1568 PCI_DMA_TODEVICE);
af2a58ac 1569 break;
291ea614
SH		 1570 case OP_BUFFER:
1571 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1572 pci_unmap_len(re, maplen),
734d1868 1573 PCI_DMA_TODEVICE);
291ea614
SH		 1574 break;
1575 }
1576
1577 if (le->ctrl & EOP) {
1578 if (unlikely(netif_msg_tx_done(sky2)))
1579 printk(KERN_DEBUG "%s: tx done %u\n",
1580 dev->name, idx);
3cf26753 1581
2bf56fe2 1582 sky2->net_stats.tx_packets++;
1583 sky2->net_stats.tx_bytes += re->skb->len;
1584
794b2bd2 1585 dev_kfree_skb_any(re->skb);
3cf26753 1586 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1587 }
793b883e 1588 }
793b883e 1589
291ea614 1590 sky2->tx_cons = idx;
50432cb5
SH		 1591 smp_mb();
1592
22e11703 1593 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1594 netif_wake_queue(dev);
cd28ab6a
SH		 1595}
1596
1597/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1598static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1599{
2bb8c262
SH		 1600 struct sky2_port *sky2 = netdev_priv(dev);
1601
1602 netif_tx_lock_bh(dev);
d11c13e7 1603 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1604 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1605}
1606
1607/* Network shutdown */
1608static int sky2_down(struct net_device *dev)
1609{
1610 struct sky2_port *sky2 = netdev_priv(dev);
1611 struct sky2_hw *hw = sky2->hw;
1612 unsigned port = sky2->port;
1613 u16 ctrl;
e07b1aa8 1614 u32 imask;
cd28ab6a 1615
1b537565
SH		 1616 /* Never really got started! */
1617 if (!sky2->tx_le)
1618 return 0;
1619
cd28ab6a
SH		 1620 if (netif_msg_ifdown(sky2))
1621 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1622
32c2c300
SH		 1623 if (netif_carrier_ok(dev) && --hw->active == 0)
1624 del_timer(&hw->watchdog_timer);
1625
018d1c66 1626 /* Stop more packets from being queued */
cd28ab6a
SH		 1627 netif_stop_queue(dev);
1628
ebc646f6
SH		 1629 /* Disable port IRQ */
1630 imask = sky2_read32(hw, B0_IMSK);
1631 imask &= ~portirq_msk[port];
1632 sky2_write32(hw, B0_IMSK, imask);
1633
d3bcfbeb 1634 sky2_gmac_reset(hw, port);
793b883e 1635
cd28ab6a
SH		 1636 /* Stop transmitter */
1637 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1638 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1639
1640 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1641 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1642
1643 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1644 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1645 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1646
1647 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1648
1649 /* Workaround shared GMAC reset */
793b883e
SH		 1650 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1651 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1652 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1653
1654 /* Disable Force Sync bit and Enable Alloc bit */
1655 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1656 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1657
1658 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1659 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1660 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1661
1662 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1663 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1664 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1665
1666 /* Reset the Tx prefetch units */
1667 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1668 PREF_UNIT_RST_SET);
1669
1670 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1671
6b1a3aef 1672 sky2_rx_stop(sky2);
cd28ab6a
SH		 1673
1674 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1675 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1676
d3bcfbeb
SH		 1677 sky2_phy_power(hw, port, 0);
1678
55d7b4e6
SH		 1679 netif_carrier_off(dev);
1680
d571b694 1681 /* turn off LED's */
cd28ab6a
SH		 1682 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1683
018d1c66
SH		 1684 synchronize_irq(hw->pdev->irq);
1685
2bb8c262 1686 sky2_tx_clean(dev);
cd28ab6a
SH		 1687 sky2_rx_clean(sky2);
1688
1689 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1690 sky2->rx_le, sky2->rx_le_map);
1691 kfree(sky2->rx_ring);
1692
1693 pci_free_consistent(hw->pdev,
1694 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1695 sky2->tx_le, sky2->tx_le_map);
1696 kfree(sky2->tx_ring);
1697
1b537565
SH		 1698 sky2->tx_le = NULL;
1699 sky2->rx_le = NULL;
1700
1701 sky2->rx_ring = NULL;
1702 sky2->tx_ring = NULL;
1703
cd28ab6a
SH		 1704 return 0;
1705}
1706
1707static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1708{
b89165f2 1709 if (!sky2_is_copper(hw))
793b883e
SH		 1710 return SPEED_1000;
1711
cd28ab6a
SH		 1712 if (hw->chip_id == CHIP_ID_YUKON_FE)
1713 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1714
1715 switch (aux & PHY_M_PS_SPEED_MSK) {
1716 case PHY_M_PS_SPEED_1000:
1717 return SPEED_1000;
1718 case PHY_M_PS_SPEED_100:
1719 return SPEED_100;
1720 default:
1721 return SPEED_10;
1722 }
1723}
1724
1725static void sky2_link_up(struct sky2_port *sky2)
1726{
1727 struct sky2_hw *hw = sky2->hw;
1728 unsigned port = sky2->port;
1729 u16 reg;
16ad91e1
SH		 1730 static const char *fc_name[] = {
1731 [FC_NONE] = "none",
1732 [FC_TX] = "tx",
1733 [FC_RX] = "rx",
1734 [FC_BOTH] = "both",
1735 };
cd28ab6a 1736
cd28ab6a 1737 /* enable Rx/Tx */
2eaba1a2 1738 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1739 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1740 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1741
1742 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1743
1744 netif_carrier_on(sky2->netdev);
cd28ab6a 1745
32c2c300
SH		 1746 if (hw->active++ == 0)
1747 mod_timer(&hw->watchdog_timer, jiffies + 1);
1748
1749
cd28ab6a 1750 /* Turn on link LED */
793b883e 1751 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1752 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1753
93745494
SH		 1754 if (hw->chip_id == CHIP_ID_YUKON_XL
1755 || hw->chip_id == CHIP_ID_YUKON_EC_U
1756 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1757 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1758 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1759
1760 switch(sky2->speed) {
1761 case SPEED_10:
1762 led |= PHY_M_LEDC_INIT_CTRL(7);
1763 break;
1764
1765 case SPEED_100:
1766 led |= PHY_M_LEDC_STA1_CTRL(7);
1767 break;
1768
1769 case SPEED_1000:
1770 led |= PHY_M_LEDC_STA0_CTRL(7);
1771 break;
1772 }
793b883e
SH		 1773
1774 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1775 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1776 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1777 }
1778
cd28ab6a
SH		 1779 if (netif_msg_link(sky2))
1780 printk(KERN_INFO PFX
d571b694 1781 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1782 sky2->netdev->name, sky2->speed,
1783 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1784 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1785}
1786
1787static void sky2_link_down(struct sky2_port *sky2)
1788{
1789 struct sky2_hw *hw = sky2->hw;
1790 unsigned port = sky2->port;
1791 u16 reg;
1792
1793 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1794
1795 reg = gma_read16(hw, port, GM_GP_CTRL);
1796 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1797 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1798
cd28ab6a 1799 netif_carrier_off(sky2->netdev);
cd28ab6a 1800
32c2c300
SH		 1801 /* Stop watchdog if both ports are not active */
1802 if (--hw->active == 0)
1803 del_timer(&hw->watchdog_timer);
1804
1805
cd28ab6a
SH		 1806 /* Turn on link LED */
1807 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1808
1809 if (netif_msg_link(sky2))
1810 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1811
cd28ab6a
SH		 1812 sky2_phy_init(hw, port);
1813}
1814
16ad91e1
SH		 1815static enum flow_control sky2_flow(int rx, int tx)
1816{
1817 if (rx)
1818 return tx ? FC_BOTH : FC_RX;
1819 else
1820 return tx ? FC_TX : FC_NONE;
1821}
1822
793b883e
SH		 1823static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1824{
1825 struct sky2_hw *hw = sky2->hw;
1826 unsigned port = sky2->port;
da4c1ff4 1827 u16 advert, lpa;
793b883e 1828
da4c1ff4 1829 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1830 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1831 if (lpa & PHY_M_AN_RF) {
1832 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1833 return -1;
1834 }
1835
793b883e
SH		 1836 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1837 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1838 sky2->netdev->name);
1839 return -1;
1840 }
1841
793b883e 1842 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1843 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1844
da4c1ff4
SH		 1845 /* Since the pause result bits seem to in different positions on
1846 * different chips. look at registers.
1847 */
1848 if (!sky2_is_copper(hw)) {
1849 /* Shift for bits in fiber PHY */
1850 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1851 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1852
1853 if (advert & ADVERTISE_1000XPAUSE)
1854 advert |= ADVERTISE_PAUSE_CAP;
1855 if (advert & ADVERTISE_1000XPSE_ASYM)
1856 advert |= ADVERTISE_PAUSE_ASYM;
1857 if (lpa & LPA_1000XPAUSE)
1858 lpa |= LPA_PAUSE_CAP;
1859 if (lpa & LPA_1000XPAUSE_ASYM)
1860 lpa |= LPA_PAUSE_ASYM;
1861 }
793b883e 1862
da4c1ff4
SH		 1863 sky2->flow_status = FC_NONE;
1864 if (advert & ADVERTISE_PAUSE_CAP) {
1865 if (lpa & LPA_PAUSE_CAP)
1866 sky2->flow_status = FC_BOTH;
1867 else if (advert & ADVERTISE_PAUSE_ASYM)
1868 sky2->flow_status = FC_RX;
1869 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1870 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1871 sky2->flow_status = FC_TX;
1872 }
793b883e 1873
16ad91e1 1874 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1875 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1876 sky2->flow_status = FC_NONE;
2eaba1a2 1877
da4c1ff4 1878 if (sky2->flow_status & FC_TX)
793b883e
SH		 1879 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1880 else
1881 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1882
1883 return 0;
1884}
cd28ab6a 1885
e07b1aa8
SH		 1886/* Interrupt from PHY */
1887static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1888{
e07b1aa8
SH		 1889 struct net_device *dev = hw->dev[port];
1890 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1891 u16 istatus, phystat;
1892
ebc646f6
SH		 1893 if (!netif_running(dev))
1894 return;
1895
e07b1aa8
SH		 1896 spin_lock(&sky2->phy_lock);
1897 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1898 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1899
cd28ab6a
SH		 1900 if (netif_msg_intr(sky2))
1901 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1902 sky2->netdev->name, istatus, phystat);
1903
2eaba1a2 1904 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1905 if (sky2_autoneg_done(sky2, phystat) == 0)
1906 sky2_link_up(sky2);
1907 goto out;
1908 }
cd28ab6a 1909
793b883e
SH		 1910 if (istatus & PHY_M_IS_LSP_CHANGE)
1911 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1912
793b883e
SH		 1913 if (istatus & PHY_M_IS_DUP_CHANGE)
1914 sky2->duplex =
1915 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1916
793b883e
SH		 1917 if (istatus & PHY_M_IS_LST_CHANGE) {
1918 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1919 sky2_link_up(sky2);
793b883e
SH		 1920 else
1921 sky2_link_down(sky2);
cd28ab6a 1922 }
793b883e 1923out:
e07b1aa8 1924 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1925}
1926
62335ab0 1927/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1928 * and tx queue is full (stopped).
1929 */
cd28ab6a
SH		 1930static void sky2_tx_timeout(struct net_device *dev)
1931{
1932 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1933 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1934
1935 if (netif_msg_timer(sky2))
1936 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1937
8f24664d 1938 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1939 dev->name, sky2->tx_cons, sky2->tx_prod,
1940 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1941 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1942
81906791
SH		 1943 /* can't restart safely under softirq */
1944 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1945}
1946
1947static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1948{
6b1a3aef
SH		 1949 struct sky2_port *sky2 = netdev_priv(dev);
1950 struct sky2_hw *hw = sky2->hw;
b628ed98 1951 unsigned port = sky2->port;
6b1a3aef
SH		 1952 int err;
1953 u16 ctl, mode;
e07b1aa8 1954 u32 imask;
cd28ab6a
SH		 1955
1956 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1957 return -EINVAL;
1958
d2adf4f6
SH		 1959 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1960 return -EINVAL;
1961
6b1a3aef
SH		 1962 if (!netif_running(dev)) {
1963 dev->mtu = new_mtu;
1964 return 0;
1965 }
1966
e07b1aa8 1967 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1968 sky2_write32(hw, B0_IMSK, 0);
1969
018d1c66
SH		 1970 dev->trans_start = jiffies; /* prevent tx timeout */
1971 netif_stop_queue(dev);
1972 netif_poll_disable(hw->dev[0]);
1973
e07b1aa8
SH		 1974 synchronize_irq(hw->pdev->irq);
1975
69161611
SH		 1976 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
1977 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 1978
1979 ctl = gma_read16(hw, port, GM_GP_CTRL);
1980 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 1981 sky2_rx_stop(sky2);
1982 sky2_rx_clean(sky2);
cd28ab6a
SH		 1983
1984 dev->mtu = new_mtu;
14d0263f 1985
6b1a3aef
SH		 1986 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1987 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1988
1989 if (dev->mtu > ETH_DATA_LEN)
1990 mode |= GM_SMOD_JUMBO_ENA;
1991
b628ed98 1992 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 1993
b628ed98 1994 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1995
6b1a3aef 1996 err = sky2_rx_start(sky2);
e07b1aa8 1997 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1998
1b537565
SH		 1999 if (err)
2000 dev_close(dev);
2001 else {
b628ed98 2002 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 2003
2004 netif_poll_enable(hw->dev[0]);
2005 netif_wake_queue(dev);
2006 }
2007
cd28ab6a
SH		 2008 return err;
2009}
2010
14d0263f
SH		 2011/* For small just reuse existing skb for next receive */
2012static struct sk_buff *receive_copy(struct sky2_port *sky2,
2013 const struct rx_ring_info *re,
2014 unsigned length)
2015{
2016 struct sk_buff *skb;
2017
2018 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2019 if (likely(skb)) {
2020 skb_reserve(skb, 2);
2021 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2022 length, PCI_DMA_FROMDEVICE);
d626f62b 2023 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2024 skb->ip_summed = re->skb->ip_summed;
2025 skb->csum = re->skb->csum;
2026 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2027 length, PCI_DMA_FROMDEVICE);
2028 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2029 skb_put(skb, length);
14d0263f
SH		 2030 }
2031 return skb;
2032}
2033
2034/* Adjust length of skb with fragments to match received data */
2035static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2036 unsigned int length)
2037{
2038 int i, num_frags;
2039 unsigned int size;
2040
2041 /* put header into skb */
2042 size = min(length, hdr_space);
2043 skb->tail += size;
2044 skb->len += size;
2045 length -= size;
2046
2047 num_frags = skb_shinfo(skb)->nr_frags;
2048 for (i = 0; i < num_frags; i++) {
2049 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2050
2051 if (length == 0) {
2052 /* don't need this page */
2053 __free_page(frag->page);
2054 --skb_shinfo(skb)->nr_frags;
2055 } else {
2056 size = min(length, (unsigned) PAGE_SIZE);
2057
2058 frag->size = size;
2059 skb->data_len += size;
2060 skb->truesize += size;
2061 skb->len += size;
2062 length -= size;
2063 }
2064 }
2065}
2066
2067/* Normal packet - take skb from ring element and put in a new one */
2068static struct sk_buff *receive_new(struct sky2_port *sky2,
2069 struct rx_ring_info *re,
2070 unsigned int length)
2071{
2072 struct sk_buff *skb, *nskb;
2073 unsigned hdr_space = sky2->rx_data_size;
2074
14d0263f
SH		 2075 /* Don't be tricky about reusing pages (yet) */
2076 nskb = sky2_rx_alloc(sky2);
2077 if (unlikely(!nskb))
2078 return NULL;
2079
2080 skb = re->skb;
2081 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2082
2083 prefetch(skb->data);
2084 re->skb = nskb;
2085 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2086
2087 if (skb_shinfo(skb)->nr_frags)
2088 skb_put_frags(skb, hdr_space, length);
2089 else
489b10c1 2090 skb_put(skb, length);
14d0263f
SH		 2091 return skb;
2092}
2093
cd28ab6a
SH		 2094/*
2095 * Receive one packet.
d571b694 2096 * For larger packets, get new buffer.
cd28ab6a 2097 */
497d7c86 2098static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2099 u16 length, u32 status)
2100{
497d7c86 2101 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2102 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2103 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2104
2105 if (unlikely(netif_msg_rx_status(sky2)))
2106 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2107 dev->name, sky2->rx_next, status, length);
cd28ab6a 2108
793b883e 2109 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2110 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2111
42eeea01 2112 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2113 goto error;
2114
42eeea01
SH		 2115 if (!(status & GMR_FS_RX_OK))
2116 goto resubmit;
2117
71749531
SH		 2118 if (status >> 16 != length)
2119 goto len_mismatch;
2120
14d0263f
SH		 2121 if (length < copybreak)
2122 skb = receive_copy(sky2, re, length);
2123 else
2124 skb = receive_new(sky2, re, length);
793b883e 2125resubmit:
14d0263f 2126 sky2_rx_submit(sky2, re);
79e57d32 2127
cd28ab6a
SH		 2128 return skb;
2129
71749531
SH		 2130len_mismatch:
2131 /* Truncation of overlength packets
2132 causes PHY length to not match MAC length */
2133 ++sky2->net_stats.rx_length_errors;
2134
cd28ab6a 2135error:
6e15b712 2136 ++sky2->net_stats.rx_errors;
b6d77734 2137 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2138 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2139 goto resubmit;
2140 }
6e15b712 2141
3be92a70 2142 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2143 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2144 dev->name, status, length);
793b883e
SH		 2145
2146 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2147 sky2->net_stats.rx_length_errors++;
2148 if (status & GMR_FS_FRAGMENT)
2149 sky2->net_stats.rx_frame_errors++;
2150 if (status & GMR_FS_CRC_ERR)
2151 sky2->net_stats.rx_crc_errors++;
79e57d32 2152
793b883e 2153 goto resubmit;
cd28ab6a
SH		 2154}
2155
e07b1aa8
SH		 2156/* Transmit complete */
2157static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2158{
e07b1aa8 2159 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2160
e07b1aa8 2161 if (netif_running(dev)) {
2bb8c262 2162 netif_tx_lock(dev);
e07b1aa8 2163 sky2_tx_complete(sky2, last);
2bb8c262 2164 netif_tx_unlock(dev);
2224795d 2165 }
cd28ab6a
SH		 2166}
2167
e07b1aa8
SH		 2168/* Process status response ring */
2169static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2170{
e07b1aa8 2171 int work_done = 0;
55c9dd35 2172 unsigned rx[2] = { 0, 0 };
e71ebd73 2173 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2174
af2a58ac 2175 rmb();
bea86103 2176
e71ebd73 2177 while (hw->st_idx != hwidx) {
55c9dd35 2178 struct sky2_port *sky2;
13210ce5 2179 struct sky2_status_le *le = hw->st_le + hw->st_idx;
69161611 2180 unsigned port = le->css & CSS_LINK_BIT;
13210ce5 2181 struct net_device *dev;
cd28ab6a 2182 struct sk_buff *skb;
cd28ab6a
SH		 2183 u32 status;
2184 u16 length;
2185
cb5d9547 2186 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2187
69161611 2188 dev = hw->dev[port];
13210ce5 2189 sky2 = netdev_priv(dev);
f65b138c
SH		 2190 length = le16_to_cpu(le->length);
2191 status = le32_to_cpu(le->status);
cd28ab6a 2192
e71ebd73 2193 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2194 case OP_RXSTAT:
55c9dd35 2195 ++rx[port];
497d7c86 2196 skb = sky2_receive(dev, length, status);
3225b919
SH		 2197 if (unlikely(!skb)) {
2198 sky2->net_stats.rx_dropped++;
55c9dd35 2199 break;
3225b919 2200 }
13210ce5 2201
69161611
SH		 2202 /* This chip reports checksum status differently */
2203 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2204 if (sky2->rx_csum &&
2205 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2206 (le->css & CSS_TCPUDPCSOK))
2207 skb->ip_summed = CHECKSUM_UNNECESSARY;
2208 else
2209 skb->ip_summed = CHECKSUM_NONE;
2210 }
2211
13210ce5 2212 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2213 sky2->net_stats.rx_packets++;
2214 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2215 dev->last_rx = jiffies;
2216
d1f13708
SH		 2217#ifdef SKY2_VLAN_TAG_USED
2218 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2219 vlan_hwaccel_receive_skb(skb,
2220 sky2->vlgrp,
2221 be16_to_cpu(sky2->rx_tag));
2222 } else
2223#endif
cd28ab6a 2224 netif_receive_skb(skb);
13210ce5 2225
22e11703 2226 /* Stop after net poll weight */
13210ce5
SH		 2227 if (++work_done >= to_do)
2228 goto exit_loop;
cd28ab6a
SH		 2229 break;
2230
d1f13708
SH		 2231#ifdef SKY2_VLAN_TAG_USED
2232 case OP_RXVLAN:
2233 sky2->rx_tag = length;
2234 break;
2235
2236 case OP_RXCHKSVLAN:
2237 sky2->rx_tag = length;
2238 /* fall through */
2239#endif
cd28ab6a 2240 case OP_RXCHKS:
87418307
SH		 2241 if (!sky2->rx_csum)
2242 break;
2243
69161611
SH		 2244 if (hw->chip_id == CHIP_ID_YUKON_EX)
2245 break;
2246
87418307
SH		 2247 /* Both checksum counters are programmed to start at
2248 * the same offset, so unless there is a problem they
2249 * should match. This failure is an early indication that
2250 * hardware receive checksumming won't work.
2251 */
2252 if (likely(status >> 16 == (status & 0xffff))) {
2253 skb = sky2->rx_ring[sky2->rx_next].skb;
2254 skb->ip_summed = CHECKSUM_COMPLETE;
2255 skb->csum = status & 0xffff;
2256 } else {
2257 printk(KERN_NOTICE PFX "%s: hardware receive "
2258 "checksum problem (status = %#x)\n",
2259 dev->name, status);
2260 sky2->rx_csum = 0;
2261 sky2_write32(sky2->hw,
69161611 2262 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2263 BMU_DIS_RX_CHKSUM);
2264 }
cd28ab6a
SH		 2265 break;
2266
2267 case OP_TXINDEXLE:
13b97b74 2268 /* TX index reports status for both ports */
f55925d7
SH		 2269 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2270 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2271 if (hw->dev[1])
2272 sky2_tx_done(hw->dev[1],
2273 ((status >> 24) & 0xff)
2274 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2275 break;
2276
cd28ab6a
SH		 2277 default:
2278 if (net_ratelimit())
793b883e 2279 printk(KERN_WARNING PFX
e71ebd73 2280 "unknown status opcode 0x%x\n", le->opcode);
cd28ab6a 2281 }
13210ce5 2282 }
cd28ab6a 2283
fe2a24df
SH		 2284 /* Fully processed status ring so clear irq */
2285 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2286
13210ce5 2287exit_loop:
55c9dd35
SH		 2288 if (rx[0])
2289 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2290
55c9dd35
SH		 2291 if (rx[1])
2292 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2293
e07b1aa8 2294 return work_done;
cd28ab6a
SH		 2295}
2296
2297static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2298{
2299 struct net_device *dev = hw->dev[port];
2300
3be92a70
SH		 2301 if (net_ratelimit())
2302 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2303 dev->name, status);
cd28ab6a
SH		 2304
2305 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2306 if (net_ratelimit())
2307 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2308 dev->name);
cd28ab6a
SH		 2309 /* Clear IRQ */
2310 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2311 }
2312
2313 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2314 if (net_ratelimit())
2315 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2316 dev->name);
cd28ab6a
SH		 2317
2318 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2319 }
2320
2321 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2322 if (net_ratelimit())
2323 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2324 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2325 }
2326
2327 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2328 if (net_ratelimit())
2329 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2330 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2331 }
2332
2333 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2334 if (net_ratelimit())
2335 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2336 dev->name);
cd28ab6a
SH		 2337 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2338 }
2339}
2340
2341static void sky2_hw_intr(struct sky2_hw *hw)
2342{
2343 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2344
793b883e 2345 if (status & Y2_IS_TIST_OV)
cd28ab6a 2346 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2347
2348 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2349 u16 pci_err;
2350
56a645cc 2351 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2352 if (net_ratelimit())
b02a9258
SH		 2353 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2354 pci_err);
cd28ab6a
SH		 2355
2356 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2357 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2358 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2359 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2360 }
2361
2362 if (status & Y2_IS_PCI_EXP) {
d571b694 2363 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2364 u32 pex_err;
2365
7bd656d1 2366 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2367
3be92a70 2368 if (net_ratelimit())
b02a9258
SH		 2369 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2370 pex_err);
cd28ab6a
SH		 2371
2372 /* clear the interrupt */
2373 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2374 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2375 0xffffffffUL);
cd28ab6a
SH		 2376 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2377
7bd656d1 2378 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2379 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2380 hwmsk &= ~Y2_IS_PCI_EXP;
2381 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2382 }
2383 }
2384
2385 if (status & Y2_HWE_L1_MASK)
2386 sky2_hw_error(hw, 0, status);
2387 status >>= 8;
2388 if (status & Y2_HWE_L1_MASK)
2389 sky2_hw_error(hw, 1, status);
2390}
2391
2392static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2393{
2394 struct net_device *dev = hw->dev[port];
2395 struct sky2_port *sky2 = netdev_priv(dev);
2396 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2397
2398 if (netif_msg_intr(sky2))
2399 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2400 dev->name, status);
2401
a3caeada
SH		 2402 if (status & GM_IS_RX_CO_OV)
2403 gma_read16(hw, port, GM_RX_IRQ_SRC);
2404
2405 if (status & GM_IS_TX_CO_OV)
2406 gma_read16(hw, port, GM_TX_IRQ_SRC);
2407
cd28ab6a
SH		 2408 if (status & GM_IS_RX_FF_OR) {
2409 ++sky2->net_stats.rx_fifo_errors;
2410 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2411 }
2412
2413 if (status & GM_IS_TX_FF_UR) {
2414 ++sky2->net_stats.tx_fifo_errors;
2415 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2416 }
cd28ab6a
SH		 2417}
2418
40b01727
SH		 2419/* This should never happen it is a bug. */
2420static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2421 u16 q, unsigned ring_size)
d257924e
SH		 2422{
2423 struct net_device *dev = hw->dev[port];
2424 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2425 unsigned idx;
2426 const u64 *le = (q == Q_R1 || q == Q_R2)
2427 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2428
40b01727
SH		 2429 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2430 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2431 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2432 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2433
40b01727 2434 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2435}
cd28ab6a 2436
32c2c300
SH		 2437/* Check for lost IRQ once a second */
2438static void sky2_watchdog(unsigned long arg)
d27ed387 2439{
01bd7564 2440 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2441
32c2c300
SH		 2442 if (sky2_read32(hw, B0_ISRC)) {
2443 struct net_device *dev = hw->dev[0];
2444
2445 if (__netif_rx_schedule_prep(dev))
2446 __netif_rx_schedule(dev);
2447 }
01bd7564 2448
32c2c300
SH		 2449 if (hw->active > 0)
2450 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2451}
2452
40b01727
SH		 2453/* Hardware/software error handling */
2454static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2455{
40b01727
SH		 2456 if (net_ratelimit())
2457 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2458
1e5f1283
SH		 2459 if (status & Y2_IS_HW_ERR)
2460 sky2_hw_intr(hw);
d257924e 2461
1e5f1283
SH		 2462 if (status & Y2_IS_IRQ_MAC1)
2463 sky2_mac_intr(hw, 0);
cd28ab6a 2464
1e5f1283
SH		 2465 if (status & Y2_IS_IRQ_MAC2)
2466 sky2_mac_intr(hw, 1);
cd28ab6a 2467
1e5f1283 2468 if (status & Y2_IS_CHK_RX1)
40b01727 2469 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2470
1e5f1283 2471 if (status & Y2_IS_CHK_RX2)
40b01727 2472 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2473
1e5f1283 2474 if (status & Y2_IS_CHK_TXA1)
40b01727 2475 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2476
1e5f1283 2477 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2478 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2479}
2480
2481static int sky2_poll(struct net_device *dev0, int *budget)
2482{
2483 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
5c11ce70 2484 int work_done;
40b01727
SH		 2485 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2486
2487 if (unlikely(status & Y2_IS_ERROR))
2488 sky2_err_intr(hw, status);
2489
2490 if (status & Y2_IS_IRQ_PHY1)
2491 sky2_phy_intr(hw, 0);
2492
2493 if (status & Y2_IS_IRQ_PHY2)
2494 sky2_phy_intr(hw, 1);
cd28ab6a 2495
5c11ce70
SH		 2496 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2497 *budget -= work_done;
2498 dev0->quota -= work_done;
86fba634 2499
5c11ce70
SH		 2500 /* More work? */
2501 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
1e5f1283 2502 return 1;
5c11ce70
SH		 2503
2504 /* Bug/Errata workaround?
2505 * Need to kick the TX irq moderation timer.
2506 */
2507 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2508 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2509 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2510 }
5c11ce70
SH		 2511 netif_rx_complete(dev0);
2512
2513 sky2_read32(hw, B0_Y2_SP_LISR);
2514 return 0;
e07b1aa8
SH		 2515}
2516
7d12e780 2517static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2518{
2519 struct sky2_hw *hw = dev_id;
2520 struct net_device *dev0 = hw->dev[0];
2521 u32 status;
2522
2523 /* Reading this mask interrupts as side effect */
2524 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2525 if (status == 0 || status == ~0)
2526 return IRQ_NONE;
793b883e 2527
e07b1aa8
SH		 2528 prefetch(&hw->st_le[hw->st_idx]);
2529 if (likely(__netif_rx_schedule_prep(dev0)))
2530 __netif_rx_schedule(dev0);
793b883e 2531
cd28ab6a
SH		 2532 return IRQ_HANDLED;
2533}
2534
2535#ifdef CONFIG_NET_POLL_CONTROLLER
2536static void sky2_netpoll(struct net_device *dev)
2537{
2538 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2539 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2540
88d11360
SH		 2541 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2542 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2543}
2544#endif
2545
2546/* Chip internal frequency for clock calculations */
fb17358f 2547static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2548{
793b883e 2549 switch (hw->chip_id) {
cd28ab6a 2550 case CHIP_ID_YUKON_EC:
5a5b1ea0 2551 case CHIP_ID_YUKON_EC_U:
93745494 2552 case CHIP_ID_YUKON_EX:
fb17358f 2553 return 125; /* 125 Mhz */
cd28ab6a 2554 case CHIP_ID_YUKON_FE:
fb17358f 2555 return 100; /* 100 Mhz */
793b883e 2556 default: /* YUKON_XL */
fb17358f 2557 return 156; /* 156 Mhz */
cd28ab6a
SH		 2558 }
2559}
2560
fb17358f 2561static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2562{
fb17358f 2563 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2564}
2565
fb17358f 2566static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2567{
fb17358f 2568 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2569}
2570
fb17358f 2571
e3173832 2572static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2573{
b89165f2 2574 u8 t8;
cd28ab6a 2575
451af335
SH		 2576 /* Enable all clocks */
2577 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2578
cd28ab6a 2579 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2580
cd28ab6a
SH		 2581 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2582 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2583 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2584 hw->chip_id);
cd28ab6a
SH		 2585 return -EOPNOTSUPP;
2586 }
2587
290d4de5
SH		 2588 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2589
2590 /* This rev is really old, and requires untested workarounds */
2591 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2592 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2593 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2594 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2595 return -EOPNOTSUPP;
2596 }
2597
e3173832
SH		 2598 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2599 hw->ports = 1;
2600 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2601 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2602 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2603 ++hw->ports;
2604 }
2605
2606 return 0;
2607}
2608
2609static void sky2_reset(struct sky2_hw *hw)
2610{
2611 u16 status;
2612 int i;
2613
cd28ab6a 2614 /* disable ASF */
4f44d8ba
SH		 2615 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2616 status = sky2_read16(hw, HCU_CCSR);
2617 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2618 HCU_CCSR_UC_STATE_MSK);
2619 sky2_write16(hw, HCU_CCSR, status);
2620 } else
2621 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2622 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2623
2624 /* do a SW reset */
2625 sky2_write8(hw, B0_CTST, CS_RST_SET);
2626 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2627
2628 /* clear PCI errors, if any */
56a645cc 2629 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2630
cd28ab6a 2631 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2632 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2633
cd28ab6a
SH		 2634
2635 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2636
2637 /* clear any PEX errors */
7bd656d1
SH		 2638 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2639 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2640
cd28ab6a 2641
ae306cca 2642 sky2_power_on(hw);
cd28ab6a
SH		 2643
2644 for (i = 0; i < hw->ports; i++) {
2645 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2646 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2647
2648 if (hw->chip_id == CHIP_ID_YUKON_EX)
2649 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2650 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2651 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2652 }
2653
2654 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2655
793b883e
SH		 2656 /* Clear I2C IRQ noise */
2657 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2658
2659 /* turn off hardware timer (unused) */
2660 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2661 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2662
cd28ab6a
SH		 2663 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2664
69634ee7
SH		 2665 /* Turn off descriptor polling */
2666 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2667
2668 /* Turn off receive timestamp */
2669 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2670 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2671
2672 /* enable the Tx Arbiters */
2673 for (i = 0; i < hw->ports; i++)
2674 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2675
2676 /* Initialize ram interface */
2677 for (i = 0; i < hw->ports; i++) {
793b883e 2678 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2679
2680 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2681 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2682 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2683 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2684 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2685 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2686 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2687 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2688 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2689 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2690 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2691 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2692 }
2693
7bd656d1 2694 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2695
cd28ab6a 2696 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2697 sky2_gmac_reset(hw, i);
cd28ab6a 2698
cd28ab6a
SH		 2699 memset(hw->st_le, 0, STATUS_LE_BYTES);
2700 hw->st_idx = 0;
2701
2702 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2703 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2704
2705 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2706 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2707
2708 /* Set the list last index */
793b883e 2709 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2710
290d4de5
SH		 2711 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2712 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2713
290d4de5
SH		 2714 /* set Status-FIFO ISR watermark */
2715 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2716 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2717 else
2718 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2719
290d4de5 2720 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2721 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2722 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2723
793b883e 2724 /* enable status unit */
cd28ab6a
SH		 2725 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2726
2727 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2728 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2729 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2730}
2731
81906791
SH		 2732static void sky2_restart(struct work_struct *work)
2733{
2734 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2735 struct net_device *dev;
2736 int i, err;
2737
81906791
SH		 2738 rtnl_lock();
2739 sky2_write32(hw, B0_IMSK, 0);
2740 sky2_read32(hw, B0_IMSK);
2741
2742 netif_poll_disable(hw->dev[0]);
2743
2744 for (i = 0; i < hw->ports; i++) {
2745 dev = hw->dev[i];
2746 if (netif_running(dev))
2747 sky2_down(dev);
2748 }
2749
2750 sky2_reset(hw);
2751 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2752 netif_poll_enable(hw->dev[0]);
2753
2754 for (i = 0; i < hw->ports; i++) {
2755 dev = hw->dev[i];
2756 if (netif_running(dev)) {
2757 err = sky2_up(dev);
2758 if (err) {
2759 printk(KERN_INFO PFX "%s: could not restart %d\n",
2760 dev->name, err);
2761 dev_close(dev);
2762 }
2763 }
2764 }
2765
81906791
SH		 2766 rtnl_unlock();
2767}
2768
e3173832
SH		 2769static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2770{
2771 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2772}
2773
2774static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2775{
2776 const struct sky2_port *sky2 = netdev_priv(dev);
2777
2778 wol->supported = sky2_wol_supported(sky2->hw);
2779 wol->wolopts = sky2->wol;
2780}
2781
2782static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2783{
2784 struct sky2_port *sky2 = netdev_priv(dev);
2785 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2786
e3173832
SH		 2787 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2788 return -EOPNOTSUPP;
2789
2790 sky2->wol = wol->wolopts;
2791
69161611 2792 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
e3173832
SH		 2793 sky2_write32(hw, B0_CTST, sky2->wol
2794 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2795
2796 if (!netif_running(dev))
2797 sky2_wol_init(sky2);
cd28ab6a
SH		 2798 return 0;
2799}
2800
28bd181a 2801static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2802{
b89165f2
SH		 2803 if (sky2_is_copper(hw)) {
2804 u32 modes = SUPPORTED_10baseT_Half
2805 | SUPPORTED_10baseT_Full
2806 | SUPPORTED_100baseT_Half
2807 | SUPPORTED_100baseT_Full
2808 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2809
2810 if (hw->chip_id != CHIP_ID_YUKON_FE)
2811 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2812 | SUPPORTED_1000baseT_Full;
2813 return modes;
cd28ab6a 2814 } else
b89165f2
SH		 2815 return SUPPORTED_1000baseT_Half
2816 | SUPPORTED_1000baseT_Full
2817 | SUPPORTED_Autoneg
2818 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2819}
2820
793b883e 2821static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2822{
2823 struct sky2_port *sky2 = netdev_priv(dev);
2824 struct sky2_hw *hw = sky2->hw;
2825
2826 ecmd->transceiver = XCVR_INTERNAL;
2827 ecmd->supported = sky2_supported_modes(hw);
2828 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2829 if (sky2_is_copper(hw)) {
cd28ab6a 2830 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2831 | SUPPORTED_10baseT_Full
2832 | SUPPORTED_100baseT_Half
2833 | SUPPORTED_100baseT_Full
2834 | SUPPORTED_1000baseT_Half
2835 | SUPPORTED_1000baseT_Full
2836 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2837 ecmd->port = PORT_TP;
b89165f2
SH		 2838 ecmd->speed = sky2->speed;
2839 } else {
2840 ecmd->speed = SPEED_1000;
cd28ab6a 2841 ecmd->port = PORT_FIBRE;
b89165f2 2842 }
cd28ab6a
SH		 2843
2844 ecmd->advertising = sky2->advertising;
2845 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2846 ecmd->duplex = sky2->duplex;
2847 return 0;
2848}
2849
2850static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2851{
2852 struct sky2_port *sky2 = netdev_priv(dev);
2853 const struct sky2_hw *hw = sky2->hw;
2854 u32 supported = sky2_supported_modes(hw);
2855
2856 if (ecmd->autoneg == AUTONEG_ENABLE) {
2857 ecmd->advertising = supported;
2858 sky2->duplex = -1;
2859 sky2->speed = -1;
2860 } else {
2861 u32 setting;
2862
793b883e 2863 switch (ecmd->speed) {
cd28ab6a
SH		 2864 case SPEED_1000:
2865 if (ecmd->duplex == DUPLEX_FULL)
2866 setting = SUPPORTED_1000baseT_Full;
2867 else if (ecmd->duplex == DUPLEX_HALF)
2868 setting = SUPPORTED_1000baseT_Half;
2869 else
2870 return -EINVAL;
2871 break;
2872 case SPEED_100:
2873 if (ecmd->duplex == DUPLEX_FULL)
2874 setting = SUPPORTED_100baseT_Full;
2875 else if (ecmd->duplex == DUPLEX_HALF)
2876 setting = SUPPORTED_100baseT_Half;
2877 else
2878 return -EINVAL;
2879 break;
2880
2881 case SPEED_10:
2882 if (ecmd->duplex == DUPLEX_FULL)
2883 setting = SUPPORTED_10baseT_Full;
2884 else if (ecmd->duplex == DUPLEX_HALF)
2885 setting = SUPPORTED_10baseT_Half;
2886 else
2887 return -EINVAL;
2888 break;
2889 default:
2890 return -EINVAL;
2891 }
2892
2893 if ((setting & supported) == 0)
2894 return -EINVAL;
2895
2896 sky2->speed = ecmd->speed;
2897 sky2->duplex = ecmd->duplex;
2898 }
2899
2900 sky2->autoneg = ecmd->autoneg;
2901 sky2->advertising = ecmd->advertising;
2902
1b537565
SH		 2903 if (netif_running(dev))
2904 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2905
2906 return 0;
2907}
2908
2909static void sky2_get_drvinfo(struct net_device *dev,
2910 struct ethtool_drvinfo *info)
2911{
2912 struct sky2_port *sky2 = netdev_priv(dev);
2913
2914 strcpy(info->driver, DRV_NAME);
2915 strcpy(info->version, DRV_VERSION);
2916 strcpy(info->fw_version, "N/A");
2917 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2918}
2919
2920static const struct sky2_stat {
793b883e
SH		 2921 char name[ETH_GSTRING_LEN];
2922 u16 offset;
cd28ab6a
SH		 2923} sky2_stats[] = {
2924 { "tx_bytes", GM_TXO_OK_HI },
2925 { "rx_bytes", GM_RXO_OK_HI },
2926 { "tx_broadcast", GM_TXF_BC_OK },
2927 { "rx_broadcast", GM_RXF_BC_OK },
2928 { "tx_multicast", GM_TXF_MC_OK },
2929 { "rx_multicast", GM_RXF_MC_OK },
2930 { "tx_unicast", GM_TXF_UC_OK },
2931 { "rx_unicast", GM_RXF_UC_OK },
2932 { "tx_mac_pause", GM_TXF_MPAUSE },
2933 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2934 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2935 { "late_collision",GM_TXF_LAT_COL },
2936 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2937 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2938 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2939
d2604540 2940 { "rx_short", GM_RXF_SHT },
cd28ab6a 2941 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2942 { "rx_64_byte_packets", GM_RXF_64B },
2943 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2944 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2945 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2946 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2947 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2948 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2949 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2950 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2951 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2952 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2953
2954 { "tx_64_byte_packets", GM_TXF_64B },
2955 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2956 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2957 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2958 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2959 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2960 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2961 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2962};
2963
cd28ab6a
SH		 2964static u32 sky2_get_rx_csum(struct net_device *dev)
2965{
2966 struct sky2_port *sky2 = netdev_priv(dev);
2967
2968 return sky2->rx_csum;
2969}
2970
2971static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2972{
2973 struct sky2_port *sky2 = netdev_priv(dev);
2974
2975 sky2->rx_csum = data;
793b883e 2976
cd28ab6a
SH		 2977 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2978 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2979
2980 return 0;
2981}
2982
2983static u32 sky2_get_msglevel(struct net_device *netdev)
2984{
2985 struct sky2_port *sky2 = netdev_priv(netdev);
2986 return sky2->msg_enable;
2987}
2988
9a7ae0a9
SH		 2989static int sky2_nway_reset(struct net_device *dev)
2990{
2991 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2992
16ad91e1 2993 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2994 return -EINVAL;
2995
1b537565 2996 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2997
2998 return 0;
2999}
3000
793b883e 3001static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3002{
3003 struct sky2_hw *hw = sky2->hw;
3004 unsigned port = sky2->port;
3005 int i;
3006
3007 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3008 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3009 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3010 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3011
793b883e 3012 for (i = 2; i < count; i++)
cd28ab6a
SH		 3013 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3014}
3015
cd28ab6a
SH		 3016static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3017{
3018 struct sky2_port *sky2 = netdev_priv(netdev);
3019 sky2->msg_enable = value;
3020}
3021
3022static int sky2_get_stats_count(struct net_device *dev)
3023{
3024 return ARRAY_SIZE(sky2_stats);
3025}
3026
3027static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3028 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3029{
3030 struct sky2_port *sky2 = netdev_priv(dev);
3031
793b883e 3032 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3033}
3034
793b883e 3035static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3036{
3037 int i;
3038
3039 switch (stringset) {
3040 case ETH_SS_STATS:
3041 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3042 memcpy(data + i * ETH_GSTRING_LEN,
3043 sky2_stats[i].name, ETH_GSTRING_LEN);
3044 break;
3045 }
3046}
3047
cd28ab6a
SH		 3048static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3049{
3050 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3051 return &sky2->net_stats;
3052}
3053
3054static int sky2_set_mac_address(struct net_device *dev, void *p)
3055{
3056 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3057 struct sky2_hw *hw = sky2->hw;
3058 unsigned port = sky2->port;
3059 const struct sockaddr *addr = p;
cd28ab6a
SH		 3060
3061 if (!is_valid_ether_addr(addr->sa_data))
3062 return -EADDRNOTAVAIL;
3063
cd28ab6a 3064 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3065 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3066 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3067 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3068 dev->dev_addr, ETH_ALEN);
1b537565 3069
a8ab1ec0
SH		 3070 /* virtual address for data */
3071 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3072
3073 /* physical address: used for pause frames */
3074 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3075
3076 return 0;
cd28ab6a
SH		 3077}
3078
a052b52f
SH		 3079static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3080{
3081 u32 bit;
3082
3083 bit = ether_crc(ETH_ALEN, addr) & 63;
3084 filter[bit >> 3] |= 1 << (bit & 7);
3085}
3086
cd28ab6a
SH		 3087static void sky2_set_multicast(struct net_device *dev)
3088{
3089 struct sky2_port *sky2 = netdev_priv(dev);
3090 struct sky2_hw *hw = sky2->hw;
3091 unsigned port = sky2->port;
3092 struct dev_mc_list *list = dev->mc_list;
3093 u16 reg;
3094 u8 filter[8];
a052b52f
SH		 3095 int rx_pause;
3096 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3097
a052b52f 3098 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3099 memset(filter, 0, sizeof(filter));
3100
3101 reg = gma_read16(hw, port, GM_RX_CTRL);
3102 reg |= GM_RXCR_UCF_ENA;
3103
d571b694 3104 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3105 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3106 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3107 memset(filter, 0xff, sizeof(filter));
a052b52f 3108 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3109 reg &= ~GM_RXCR_MCF_ENA;
3110 else {
3111 int i;
3112 reg |= GM_RXCR_MCF_ENA;
3113
a052b52f
SH		 3114 if (rx_pause)
3115 sky2_add_filter(filter, pause_mc_addr);
3116
3117 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3118 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3119 }
3120
cd28ab6a 3121 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3122 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3123 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3124 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3125 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3126 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3127 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3128 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3129
3130 gma_write16(hw, port, GM_RX_CTRL, reg);
3131}
3132
3133/* Can have one global because blinking is controlled by
3134 * ethtool and that is always under RTNL mutex
3135 */
91c86df5 3136static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3137{
793b883e
SH		 3138 u16 pg;
3139
793b883e
SH		 3140 switch (hw->chip_id) {
3141 case CHIP_ID_YUKON_XL:
3142 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3143 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3144 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3145 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3146 PHY_M_LEDC_INIT_CTRL(7) |
3147 PHY_M_LEDC_STA1_CTRL(7) |
3148 PHY_M_LEDC_STA0_CTRL(7))
3149 : 0);
3150
3151 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3152 break;
3153
3154 default:
3155 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3156 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3157 on ? PHY_M_LED_ALL : 0);
793b883e 3158 }
cd28ab6a
SH		 3159}
3160
3161/* blink LED's for finding board */
3162static int sky2_phys_id(struct net_device *dev, u32 data)
3163{
3164 struct sky2_port *sky2 = netdev_priv(dev);
3165 struct sky2_hw *hw = sky2->hw;
3166 unsigned port = sky2->port;
793b883e 3167 u16 ledctrl, ledover = 0;
cd28ab6a 3168 long ms;
91c86df5 3169 int interrupted;
cd28ab6a
SH		 3170 int onoff = 1;
3171
793b883e 3172 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3173 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3174 else
3175 ms = data * 1000;
3176
3177 /* save initial values */
e07b1aa8 3178 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3179 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3180 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3181 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3182 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3183 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3184 } else {
3185 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3186 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3187 }
cd28ab6a 3188
91c86df5
SH		 3189 interrupted = 0;
3190 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3191 sky2_led(hw, port, onoff);
3192 onoff = !onoff;
3193
e07b1aa8 3194 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3195 interrupted = msleep_interruptible(250);
e07b1aa8 3196 spin_lock_bh(&sky2->phy_lock);
91c86df5 3197
cd28ab6a
SH		 3198 ms -= 250;
3199 }
3200
3201 /* resume regularly scheduled programming */
793b883e
SH		 3202 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3203 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3204 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3205 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3206 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3207 } else {
3208 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3209 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3210 }
e07b1aa8 3211 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3212
3213 return 0;
3214}
3215
3216static void sky2_get_pauseparam(struct net_device *dev,
3217 struct ethtool_pauseparam *ecmd)
3218{
3219 struct sky2_port *sky2 = netdev_priv(dev);
3220
16ad91e1
SH		 3221 switch (sky2->flow_mode) {
3222 case FC_NONE:
3223 ecmd->tx_pause = ecmd->rx_pause = 0;
3224 break;
3225 case FC_TX:
3226 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3227 break;
3228 case FC_RX:
3229 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3230 break;
3231 case FC_BOTH:
3232 ecmd->tx_pause = ecmd->rx_pause = 1;
3233 }
3234
cd28ab6a
SH		 3235 ecmd->autoneg = sky2->autoneg;
3236}
3237
3238static int sky2_set_pauseparam(struct net_device *dev,
3239 struct ethtool_pauseparam *ecmd)
3240{
3241 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3242
3243 sky2->autoneg = ecmd->autoneg;
16ad91e1 3244 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3245
16ad91e1
SH		 3246 if (netif_running(dev))
3247 sky2_phy_reinit(sky2);
cd28ab6a 3248
2eaba1a2 3249 return 0;
cd28ab6a
SH		 3250}
3251
fb17358f
SH		 3252static int sky2_get_coalesce(struct net_device *dev,
3253 struct ethtool_coalesce *ecmd)
3254{
3255 struct sky2_port *sky2 = netdev_priv(dev);
3256 struct sky2_hw *hw = sky2->hw;
3257
3258 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3259 ecmd->tx_coalesce_usecs = 0;
3260 else {
3261 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3262 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3263 }
3264 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3265
3266 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3267 ecmd->rx_coalesce_usecs = 0;
3268 else {
3269 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3270 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3271 }
3272 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3273
3274 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3275 ecmd->rx_coalesce_usecs_irq = 0;
3276 else {
3277 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3278 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3279 }
3280
3281 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3282
3283 return 0;
3284}
3285
3286/* Note: this affect both ports */
3287static int sky2_set_coalesce(struct net_device *dev,
3288 struct ethtool_coalesce *ecmd)
3289{
3290 struct sky2_port *sky2 = netdev_priv(dev);
3291 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3292 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3293
77b3d6a2
SH		 3294 if (ecmd->tx_coalesce_usecs > tmax ||
3295 ecmd->rx_coalesce_usecs > tmax ||
3296 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3297 return -EINVAL;
3298
ff81fbbe 3299 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3300 return -EINVAL;
ff81fbbe 3301 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3302 return -EINVAL;
ff81fbbe 3303 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3304 return -EINVAL;
3305
3306 if (ecmd->tx_coalesce_usecs == 0)
3307 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3308 else {
3309 sky2_write32(hw, STAT_TX_TIMER_INI,
3310 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3311 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3312 }
3313 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3314
3315 if (ecmd->rx_coalesce_usecs == 0)
3316 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3317 else {
3318 sky2_write32(hw, STAT_LEV_TIMER_INI,
3319 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3320 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3321 }
3322 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3323
3324 if (ecmd->rx_coalesce_usecs_irq == 0)
3325 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3326 else {
d28d4870 3327 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3328 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3329 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3330 }
3331 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3332 return 0;
3333}
3334
793b883e
SH		 3335static void sky2_get_ringparam(struct net_device *dev,
3336 struct ethtool_ringparam *ering)
3337{
3338 struct sky2_port *sky2 = netdev_priv(dev);
3339
3340 ering->rx_max_pending = RX_MAX_PENDING;
3341 ering->rx_mini_max_pending = 0;
3342 ering->rx_jumbo_max_pending = 0;
3343 ering->tx_max_pending = TX_RING_SIZE - 1;
3344
3345 ering->rx_pending = sky2->rx_pending;
3346 ering->rx_mini_pending = 0;
3347 ering->rx_jumbo_pending = 0;
3348 ering->tx_pending = sky2->tx_pending;
3349}
3350
3351static int sky2_set_ringparam(struct net_device *dev,
3352 struct ethtool_ringparam *ering)
3353{
3354 struct sky2_port *sky2 = netdev_priv(dev);
3355 int err = 0;
3356
3357 if (ering->rx_pending > RX_MAX_PENDING ||
3358 ering->rx_pending < 8 ||
3359 ering->tx_pending < MAX_SKB_TX_LE ||
3360 ering->tx_pending > TX_RING_SIZE - 1)
3361 return -EINVAL;
3362
3363 if (netif_running(dev))
3364 sky2_down(dev);
3365
3366 sky2->rx_pending = ering->rx_pending;
3367 sky2->tx_pending = ering->tx_pending;
3368
1b537565 3369 if (netif_running(dev)) {
793b883e 3370 err = sky2_up(dev);
1b537565
SH		 3371 if (err)
3372 dev_close(dev);
6ed995bb
SH		 3373 else
3374 sky2_set_multicast(dev);
1b537565 3375 }
793b883e
SH		 3376
3377 return err;
3378}
3379
793b883e
SH		 3380static int sky2_get_regs_len(struct net_device *dev)
3381{
6e4cbb34 3382 return 0x4000;
793b883e
SH		 3383}
3384
3385/*
3386 * Returns copy of control register region
3ead5db7 3387 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3388 */
3389static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3390 void *p)
3391{
3392 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3393 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3394
3395 regs->version = 1;
6e4cbb34 3396 memset(p, 0, regs->len);
793b883e 3397
6e4cbb34
SH		 3398 memcpy_fromio(p, io, B3_RAM_ADDR);
3399
3ead5db7
SH		 3400 /* skip diagnostic ram region */
3401 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3402
3403 /* copy GMAC registers */
3404 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3405 if (sky2->hw->ports > 1)
3406 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3407
793b883e 3408}
cd28ab6a 3409
b628ed98
SH		 3410/* In order to do Jumbo packets on these chips, need to turn off the
3411 * transmit store/forward. Therefore checksum offload won't work.
3412 */
3413static int no_tx_offload(struct net_device *dev)
3414{
3415 const struct sky2_port *sky2 = netdev_priv(dev);
3416 const struct sky2_hw *hw = sky2->hw;
3417
69161611 3418 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3419}
3420
3421static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3422{
3423 if (data && no_tx_offload(dev))
3424 return -EINVAL;
3425
3426 return ethtool_op_set_tx_csum(dev, data);
3427}
3428
3429
3430static int sky2_set_tso(struct net_device *dev, u32 data)
3431{
3432 if (data && no_tx_offload(dev))
3433 return -EINVAL;
3434
3435 return ethtool_op_set_tso(dev, data);
3436}
3437
f4331a6d
SH		 3438static int sky2_get_eeprom_len(struct net_device *dev)
3439{
3440 struct sky2_port *sky2 = netdev_priv(dev);
3441 u16 reg2;
3442
3443 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3444 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3445}
3446
3447static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3448{
3449 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3450
3451 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3452 cpu_relax();
3453 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3454}
3455
3456static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3457{
3458 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3459 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3460 do {
3461 cpu_relax();
3462 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3463}
3464
3465static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3466 u8 *data)
3467{
3468 struct sky2_port *sky2 = netdev_priv(dev);
3469 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3470 int length = eeprom->len;
3471 u16 offset = eeprom->offset;
3472
3473 if (!cap)
3474 return -EINVAL;
3475
3476 eeprom->magic = SKY2_EEPROM_MAGIC;
3477
3478 while (length > 0) {
3479 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3480 int n = min_t(int, length, sizeof(val));
3481
3482 memcpy(data, &val, n);
3483 length -= n;
3484 data += n;
3485 offset += n;
3486 }
3487 return 0;
3488}
3489
3490static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3491 u8 *data)
3492{
3493 struct sky2_port *sky2 = netdev_priv(dev);
3494 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3495 int length = eeprom->len;
3496 u16 offset = eeprom->offset;
3497
3498 if (!cap)
3499 return -EINVAL;
3500
3501 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3502 return -EINVAL;
3503
3504 while (length > 0) {
3505 u32 val;
3506 int n = min_t(int, length, sizeof(val));
3507
3508 if (n < sizeof(val))
3509 val = sky2_vpd_read(sky2->hw, cap, offset);
3510 memcpy(&val, data, n);
3511
3512 sky2_vpd_write(sky2->hw, cap, offset, val);
3513
3514 length -= n;
3515 data += n;
3516 offset += n;
3517 }
3518 return 0;
3519}
3520
3521
7282d491 3522static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3523 .get_settings = sky2_get_settings,
3524 .set_settings = sky2_set_settings,
3525 .get_drvinfo = sky2_get_drvinfo,
3526 .get_wol = sky2_get_wol,
3527 .set_wol = sky2_set_wol,
3528 .get_msglevel = sky2_get_msglevel,
3529 .set_msglevel = sky2_set_msglevel,
3530 .nway_reset = sky2_nway_reset,
3531 .get_regs_len = sky2_get_regs_len,
3532 .get_regs = sky2_get_regs,
3533 .get_link = ethtool_op_get_link,
3534 .get_eeprom_len = sky2_get_eeprom_len,
3535 .get_eeprom = sky2_get_eeprom,
3536 .set_eeprom = sky2_set_eeprom,
3537 .get_sg = ethtool_op_get_sg,
3538 .set_sg = ethtool_op_set_sg,
3539 .get_tx_csum = ethtool_op_get_tx_csum,
3540 .set_tx_csum = sky2_set_tx_csum,
3541 .get_tso = ethtool_op_get_tso,
3542 .set_tso = sky2_set_tso,
3543 .get_rx_csum = sky2_get_rx_csum,
3544 .set_rx_csum = sky2_set_rx_csum,
3545 .get_strings = sky2_get_strings,
3546 .get_coalesce = sky2_get_coalesce,
3547 .set_coalesce = sky2_set_coalesce,
3548 .get_ringparam = sky2_get_ringparam,
3549 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3550 .get_pauseparam = sky2_get_pauseparam,
3551 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3552 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3553 .get_stats_count = sky2_get_stats_count,
3554 .get_ethtool_stats = sky2_get_ethtool_stats,
3555};
3556
3cf26753
SH		 3557#ifdef CONFIG_SKY2_DEBUG
3558
3559static struct dentry *sky2_debug;
3560
3561static int sky2_debug_show(struct seq_file *seq, void *v)
3562{
3563 struct net_device *dev = seq->private;
3564 const struct sky2_port *sky2 = netdev_priv(dev);
3565 const struct sky2_hw *hw = sky2->hw;
3566 unsigned port = sky2->port;
3567 unsigned idx, last;
3568 int sop;
3569
3570 if (!netif_running(dev))
3571 return -ENETDOWN;
3572
3573 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3574 sky2_read32(hw, B0_ISRC),
3575 sky2_read32(hw, B0_IMSK),
3576 sky2_read32(hw, B0_Y2_SP_ICR));
3577
3578 netif_poll_disable(hw->dev[0]);
3579 last = sky2_read16(hw, STAT_PUT_IDX);
3580
3581 if (hw->st_idx == last)
3582 seq_puts(seq, "Status ring (empty)\n");
3583 else {
3584 seq_puts(seq, "Status ring\n");
3585 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3586 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3587 const struct sky2_status_le *le = hw->st_le + idx;
3588 seq_printf(seq, "[%d] %#x %d %#x\n",
3589 idx, le->opcode, le->length, le->status);
3590 }
3591 seq_puts(seq, "\n");
3592 }
3593
3594 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3595 sky2->tx_cons, sky2->tx_prod,
3596 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3597 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3598
3599 /* Dump contents of tx ring */
3600 sop = 1;
3601 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3602 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3603 const struct sky2_tx_le *le = sky2->tx_le + idx;
3604 u32 a = le32_to_cpu(le->addr);
3605
3606 if (sop)
3607 seq_printf(seq, "%u:", idx);
3608 sop = 0;
3609
3610 switch(le->opcode & ~HW_OWNER) {
3611 case OP_ADDR64:
3612 seq_printf(seq, " %#x:", a);
3613 break;
3614 case OP_LRGLEN:
3615 seq_printf(seq, " mtu=%d", a);
3616 break;
3617 case OP_VLAN:
3618 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3619 break;
3620 case OP_TCPLISW:
3621 seq_printf(seq, " csum=%#x", a);
3622 break;
3623 case OP_LARGESEND:
3624 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3625 break;
3626 case OP_PACKET:
3627 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3628 break;
3629 case OP_BUFFER:
3630 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3631 break;
3632 default:
3633 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3634 a, le16_to_cpu(le->length));
3635 }
3636
3637 if (le->ctrl & EOP) {
3638 seq_putc(seq, '\n');
3639 sop = 1;
3640 }
3641 }
3642
3643 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3644 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3645 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3646 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3647
3648 netif_poll_enable(hw->dev[0]);
3649 return 0;
3650}
3651
3652static int sky2_debug_open(struct inode *inode, struct file *file)
3653{
3654 return single_open(file, sky2_debug_show, inode->i_private);
3655}
3656
3657static const struct file_operations sky2_debug_fops = {
3658 .owner = THIS_MODULE,
3659 .open = sky2_debug_open,
3660 .read = seq_read,
3661 .llseek = seq_lseek,
3662 .release = single_release,
3663};
3664
3665/*
3666 * Use network device events to create/remove/rename
3667 * debugfs file entries
3668 */
3669static int sky2_device_event(struct notifier_block *unused,
3670 unsigned long event, void *ptr)
3671{
3672 struct net_device *dev = ptr;
3673
3674 if (dev->open == sky2_up) {
3675 struct sky2_port *sky2 = netdev_priv(dev);
3676
3677 switch(event) {
3678 case NETDEV_CHANGENAME:
3679 if (!netif_running(dev))
3680 break;
3681 /* fallthrough */
3682 case NETDEV_DOWN:
3683 case NETDEV_GOING_DOWN:
3684 if (sky2->debugfs) {
3685 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3686 dev->name);
3687 debugfs_remove(sky2->debugfs);
3688 sky2->debugfs = NULL;
3689 }
3690
3691 if (event != NETDEV_CHANGENAME)
3692 break;
3693 /* fallthrough for changename */
3694 case NETDEV_UP:
3695 if (sky2_debug) {
3696 struct dentry *d;
3697 d = debugfs_create_file(dev->name, S_IRUGO,
3698 sky2_debug, dev,
3699 &sky2_debug_fops);
3700 if (d == NULL || IS_ERR(d))
3701 printk(KERN_INFO PFX
3702 "%s: debugfs create failed\n",
3703 dev->name);
3704 else
3705 sky2->debugfs = d;
3706 }
3707 break;
3708 }
3709 }
3710
3711 return NOTIFY_DONE;
3712}
3713
3714static struct notifier_block sky2_notifier = {
3715 .notifier_call = sky2_device_event,
3716};
3717
3718
3719static __init void sky2_debug_init(void)
3720{
3721 struct dentry *ent;
3722
3723 ent = debugfs_create_dir("sky2", NULL);
3724 if (!ent || IS_ERR(ent))
3725 return;
3726
3727 sky2_debug = ent;
3728 register_netdevice_notifier(&sky2_notifier);
3729}
3730
3731static __exit void sky2_debug_cleanup(void)
3732{
3733 if (sky2_debug) {
3734 unregister_netdevice_notifier(&sky2_notifier);
3735 debugfs_remove(sky2_debug);
3736 sky2_debug = NULL;
3737 }
3738}
3739
3740#else
3741#define sky2_debug_init()
3742#define sky2_debug_cleanup()
3743#endif
3744
3745
cd28ab6a
SH		 3746/* Initialize network device */
3747static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3748 unsigned port,
3749 int highmem, int wol)
cd28ab6a
SH		 3750{
3751 struct sky2_port *sky2;
3752 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3753
3754 if (!dev) {
b02a9258 3755 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3756 return NULL;
3757 }
3758
3759 SET_MODULE_OWNER(dev);
3760 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3761 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3762 dev->open = sky2_up;
3763 dev->stop = sky2_down;
ef743d33 3764 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3765 dev->hard_start_xmit = sky2_xmit_frame;
3766 dev->get_stats = sky2_get_stats;
3767 dev->set_multicast_list = sky2_set_multicast;
3768 dev->set_mac_address = sky2_set_mac_address;
3769 dev->change_mtu = sky2_change_mtu;
3770 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3771 dev->tx_timeout = sky2_tx_timeout;
3772 dev->watchdog_timeo = TX_WATCHDOG;
3773 if (port == 0)
3774 dev->poll = sky2_poll;
3775 dev->weight = NAPI_WEIGHT;
3776#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3777 /* Network console (only works on port 0)
3778 * because netpoll makes assumptions about NAPI
3779 */
3780 if (port == 0)
3781 dev->poll_controller = sky2_netpoll;
cd28ab6a 3782#endif
cd28ab6a
SH		 3783
3784 sky2 = netdev_priv(dev);
3785 sky2->netdev = dev;
3786 sky2->hw = hw;
3787 sky2->msg_enable = netif_msg_init(debug, default_msg);
3788
cd28ab6a
SH		 3789 /* Auto speed and flow control */
3790 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3791 sky2->flow_mode = FC_BOTH;
3792
cd28ab6a
SH		 3793 sky2->duplex = -1;
3794 sky2->speed = -1;
3795 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3796 sky2->rx_csum = 1;
e3173832 3797 sky2->wol = wol;
75d070c5 3798
e07b1aa8 3799 spin_lock_init(&sky2->phy_lock);
793b883e 3800 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3801 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3802
3803 hw->dev[port] = dev;
3804
3805 sky2->port = port;
3806
4a50a876 3807 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3808 if (highmem)
3809 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3810
d1f13708
SH		 3811#ifdef SKY2_VLAN_TAG_USED
3812 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3813 dev->vlan_rx_register = sky2_vlan_rx_register;
d1f13708
SH		 3814#endif
3815
cd28ab6a 3816 /* read the mac address */
793b883e 3817 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3818 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 3819
cd28ab6a
SH		 3820 return dev;
3821}
3822
28bd181a 3823static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3824{
3825 const struct sky2_port *sky2 = netdev_priv(dev);
3826
3827 if (netif_msg_probe(sky2))
3828 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3829 dev->name,
3830 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3831 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3832}
3833
fb2690a9 3834/* Handle software interrupt used during MSI test */
7d12e780 3835static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3836{
3837 struct sky2_hw *hw = dev_id;
3838 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3839
3840 if (status == 0)
3841 return IRQ_NONE;
3842
3843 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3844 hw->msi = 1;
fb2690a9
SH		 3845 wake_up(&hw->msi_wait);
3846 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3847 }
3848 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3849
3850 return IRQ_HANDLED;
3851}
3852
3853/* Test interrupt path by forcing a a software IRQ */
3854static int __devinit sky2_test_msi(struct sky2_hw *hw)
3855{
3856 struct pci_dev *pdev = hw->pdev;
3857 int err;
3858
bb507fe1
SH		 3859 init_waitqueue_head (&hw->msi_wait);
3860
fb2690a9
SH		 3861 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3862
b0a20ded 3863 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3864 if (err) {
b02a9258 3865 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3866 return err;
3867 }
3868
fb2690a9 3869 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3870 sky2_read8(hw, B0_CTST);
fb2690a9 3871
b0a20ded 3872 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3873
b0a20ded 3874 if (!hw->msi) {
fb2690a9 3875 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3876 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3877 "switching to INTx mode.\n");
fb2690a9
SH		 3878
3879 err = -EOPNOTSUPP;
3880 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3881 }
3882
3883 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3884 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3885
3886 free_irq(pdev->irq, hw);
3887
3888 return err;
3889}
3890
e3173832
SH		 3891static int __devinit pci_wake_enabled(struct pci_dev *dev)
3892{
3893 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3894 u16 value;
3895
3896 if (!pm)
3897 return 0;
3898 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3899 return 0;
3900 return value & PCI_PM_CTRL_PME_ENABLE;
3901}
3902
cd28ab6a
SH		 3903static int __devinit sky2_probe(struct pci_dev *pdev,
3904 const struct pci_device_id *ent)
3905{
7f60c64b 3906 struct net_device *dev;
cd28ab6a 3907 struct sky2_hw *hw;
e3173832 3908 int err, using_dac = 0, wol_default;
cd28ab6a 3909
793b883e
SH		 3910 err = pci_enable_device(pdev);
3911 if (err) {
b02a9258 3912 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3913 goto err_out;
3914 }
3915
793b883e
SH		 3916 err = pci_request_regions(pdev, DRV_NAME);
3917 if (err) {
b02a9258 3918 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 3919 goto err_out_disable;
cd28ab6a
SH		 3920 }
3921
3922 pci_set_master(pdev);
3923
d1f3d4dd
SH		 3924 if (sizeof(dma_addr_t) > sizeof(u32) &&
3925 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3926 using_dac = 1;
3927 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3928 if (err < 0) {
b02a9258
SH		 3929 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3930 "for consistent allocations\n");
d1f3d4dd
SH		 3931 goto err_out_free_regions;
3932 }
d1f3d4dd 3933 } else {
cd28ab6a
SH		 3934 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3935 if (err) {
b02a9258 3936 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3937 goto err_out_free_regions;
3938 }
3939 }
d1f3d4dd 3940
e3173832
SH		 3941 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3942
cd28ab6a 3943 err = -ENOMEM;
6aad85d6 3944 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3945 if (!hw) {
b02a9258 3946 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3947 goto err_out_free_regions;
3948 }
3949
cd28ab6a 3950 hw->pdev = pdev;
cd28ab6a
SH		 3951
3952 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3953 if (!hw->regs) {
b02a9258 3954 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3955 goto err_out_free_hw;
3956 }
3957
56a645cc 3958#ifdef __BIG_ENDIAN
f65b138c
SH		 3959 /* The sk98lin vendor driver uses hardware byte swapping but
3960 * this driver uses software swapping.
3961 */
56a645cc
SH		 3962 {
3963 u32 reg;
56a645cc 3964 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3965 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3966 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3967 }
3968#endif
3969
08c06d8a
SH		 3970 /* ring for status responses */
3971 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3972 &hw->st_dma);
3973 if (!hw->st_le)
3974 goto err_out_iounmap;
3975
e3173832 3976 err = sky2_init(hw);
cd28ab6a 3977 if (err)
793b883e 3978 goto err_out_iounmap;
cd28ab6a 3979
b02a9258 3980 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3981 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3982 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3983 hw->chip_id, hw->chip_rev);
cd28ab6a 3984
e3173832
SH		 3985 sky2_reset(hw);
3986
3987 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3988 if (!dev) {
3989 err = -ENOMEM;
cd28ab6a 3990 goto err_out_free_pci;
7f60c64b 3991 }
cd28ab6a 3992
9fa1b1f3
SH		 3993 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3994 err = sky2_test_msi(hw);
3995 if (err == -EOPNOTSUPP)
3996 pci_disable_msi(pdev);
3997 else if (err)
3998 goto err_out_free_netdev;
3999 }
4000
793b883e
SH		 4001 err = register_netdev(dev);
4002 if (err) {
b02a9258 4003 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4004 goto err_out_free_netdev;
4005 }
4006
b0a20ded
SH		 4007 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
4008 dev->name, hw);
9fa1b1f3 4009 if (err) {
b02a9258 4010 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4011 goto err_out_unregister;
4012 }
4013 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4014
cd28ab6a
SH		 4015 sky2_show_addr(dev);
4016
7f60c64b 4017 if (hw->ports > 1) {
4018 struct net_device *dev1;
4019
e3173832 4020 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4021 if (!dev1)
4022 dev_warn(&pdev->dev, "allocation for second device failed\n");
4023 else if ((err = register_netdev(dev1))) {
4024 dev_warn(&pdev->dev,
4025 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4026 hw->dev[1] = NULL;
4027 free_netdev(dev1);
b02a9258
SH		 4028 } else
4029 sky2_show_addr(dev1);
cd28ab6a
SH		 4030 }
4031
32c2c300 4032 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4033 INIT_WORK(&hw->restart_work, sky2_restart);
4034
793b883e
SH		 4035 pci_set_drvdata(pdev, hw);
4036
cd28ab6a
SH		 4037 return 0;
4038
793b883e 4039err_out_unregister:
b0a20ded
SH		 4040 if (hw->msi)
4041 pci_disable_msi(pdev);
793b883e 4042 unregister_netdev(dev);
cd28ab6a
SH		 4043err_out_free_netdev:
4044 free_netdev(dev);
cd28ab6a 4045err_out_free_pci:
793b883e 4046 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4047 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4048err_out_iounmap:
4049 iounmap(hw->regs);
4050err_out_free_hw:
4051 kfree(hw);
4052err_out_free_regions:
4053 pci_release_regions(pdev);
44a1d2e5 4054err_out_disable:
cd28ab6a 4055 pci_disable_device(pdev);
cd28ab6a 4056err_out:
549a68c3 4057 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4058 return err;
4059}
4060
4061static void __devexit sky2_remove(struct pci_dev *pdev)
4062{
793b883e 4063 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 4064 struct net_device *dev0, *dev1;
4065
793b883e 4066 if (!hw)
cd28ab6a
SH		 4067 return;
4068
32c2c300 4069 del_timer_sync(&hw->watchdog_timer);
d27ed387 4070
81906791
SH		 4071 flush_scheduled_work();
4072
d27ed387 4073 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 4074 synchronize_irq(hw->pdev->irq);
4075
cd28ab6a 4076 dev0 = hw->dev[0];
793b883e
SH		 4077 dev1 = hw->dev[1];
4078 if (dev1)
4079 unregister_netdev(dev1);
cd28ab6a
SH		 4080 unregister_netdev(dev0);
4081
ae306cca
SH		 4082 sky2_power_aux(hw);
4083
cd28ab6a 4084 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4085 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4086 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4087
4088 free_irq(pdev->irq, hw);
b0a20ded
SH		 4089 if (hw->msi)
4090 pci_disable_msi(pdev);
793b883e 4091 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4092 pci_release_regions(pdev);
4093 pci_disable_device(pdev);
793b883e 4094
cd28ab6a
SH		 4095 if (dev1)
4096 free_netdev(dev1);
4097 free_netdev(dev0);
4098 iounmap(hw->regs);
4099 kfree(hw);
5afa0a9c 4100
cd28ab6a
SH		 4101 pci_set_drvdata(pdev, NULL);
4102}
4103
4104#ifdef CONFIG_PM
4105static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4106{
793b883e 4107 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4108 int i, wol = 0;
cd28ab6a 4109
549a68c3
SH		 4110 if (!hw)
4111 return 0;
4112
6a5706b9 4113 netif_poll_disable(hw->dev[0]);
eb35cf60 4114
f05267e7 4115 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4116 struct net_device *dev = hw->dev[i];
e3173832 4117 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4118
e3173832 4119 if (netif_running(dev))
5afa0a9c 4120 sky2_down(dev);
e3173832
SH		 4121
4122 if (sky2->wol)
4123 sky2_wol_init(sky2);
4124
4125 wol |= sky2->wol;
cd28ab6a
SH		 4126 }
4127
8ab8fca2 4128 sky2_write32(hw, B0_IMSK, 0);
ae306cca 4129 sky2_power_aux(hw);
e3173832 4130
d374c1c1 4131 pci_save_state(pdev);
e3173832 4132 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4133 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4134
2ccc99b7 4135 return 0;
cd28ab6a
SH		 4136}
4137
4138static int sky2_resume(struct pci_dev *pdev)
4139{
793b883e 4140 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4141 int i, err;
cd28ab6a 4142
549a68c3
SH		 4143 if (!hw)
4144 return 0;
4145
ae306cca
SH		 4146 err = pci_set_power_state(pdev, PCI_D0);
4147 if (err)
4148 goto out;
4149
4150 err = pci_restore_state(pdev);
4151 if (err)
4152 goto out;
4153
cd28ab6a 4154 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4155
4156 /* Re-enable all clocks */
4157 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
4158 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4159
e3173832 4160 sky2_reset(hw);
cd28ab6a 4161
8ab8fca2
SH		 4162 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4163
f05267e7 4164 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4165 struct net_device *dev = hw->dev[i];
6a5706b9 4166 if (netif_running(dev)) {
08c06d8a
SH		 4167 err = sky2_up(dev);
4168 if (err) {
4169 printk(KERN_ERR PFX "%s: could not up: %d\n",
4170 dev->name, err);
4171 dev_close(dev);
eb35cf60 4172 goto out;
5afa0a9c 4173 }
cd28ab6a
SH		 4174 }
4175 }
eb35cf60 4176
6a5706b9 4177 netif_poll_enable(hw->dev[0]);
32c2c300 4178
ae306cca 4179 return 0;
08c06d8a 4180out:
b02a9258 4181 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4182 pci_disable_device(pdev);
08c06d8a 4183 return err;
cd28ab6a
SH		 4184}
4185#endif
4186
e3173832
SH		 4187static void sky2_shutdown(struct pci_dev *pdev)
4188{
4189 struct sky2_hw *hw = pci_get_drvdata(pdev);
4190 int i, wol = 0;
4191
549a68c3
SH		 4192 if (!hw)
4193 return;
4194
e3173832
SH		 4195 netif_poll_disable(hw->dev[0]);
4196
4197 for (i = 0; i < hw->ports; i++) {
4198 struct net_device *dev = hw->dev[i];
4199 struct sky2_port *sky2 = netdev_priv(dev);
4200
4201 if (sky2->wol) {
4202 wol = 1;
4203 sky2_wol_init(sky2);
4204 }
4205 }
4206
4207 if (wol)
4208 sky2_power_aux(hw);
4209
4210 pci_enable_wake(pdev, PCI_D3hot, wol);
4211 pci_enable_wake(pdev, PCI_D3cold, wol);
4212
4213 pci_disable_device(pdev);
4214 pci_set_power_state(pdev, PCI_D3hot);
4215
4216}
4217
cd28ab6a 4218static struct pci_driver sky2_driver = {
793b883e
SH		 4219 .name = DRV_NAME,
4220 .id_table = sky2_id_table,
4221 .probe = sky2_probe,
4222 .remove = __devexit_p(sky2_remove),
cd28ab6a 4223#ifdef CONFIG_PM
793b883e
SH		 4224 .suspend = sky2_suspend,
4225 .resume = sky2_resume,
cd28ab6a 4226#endif
e3173832 4227 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4228};
4229
4230static int __init sky2_init_module(void)
4231{
3cf26753 4232 sky2_debug_init();
50241c4c 4233 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4234}
4235
4236static void __exit sky2_cleanup_module(void)
4237{
4238 pci_unregister_driver(&sky2_driver);
3cf26753 4239 sky2_debug_cleanup();
cd28ab6a
SH		 4240}
4241
4242module_init(sky2_init_module);
4243module_exit(sky2_cleanup_module);
4244
4245MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4246MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4247MODULE_LICENSE("GPL");
5f4f9dc1 4248MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree