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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
ada1db5c
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
793b883e 27#include <linux/crc32.h>
cd28ab6a 28#include <linux/kernel.h>
cd28ab6a
SH		 29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
5a0e3ad6 36#include <linux/slab.h>
c9bdd4b5 37#include <net/ip.h>
cd28ab6a
SH		 38#include <linux/tcp.h>
39#include <linux/in.h>
40#include <linux/delay.h>
91c86df5 41#include <linux/workqueue.h>
d1f13708 42#include <linux/if_vlan.h>
d70cd51a 43#include <linux/prefetch.h>
3cf26753 44#include <linux/debugfs.h>
ef743d33 45#include <linux/mii.h>
cd28ab6a
SH		 46
47#include <asm/irq.h>
48
d1f13708
SH		 49#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
50#define SKY2_VLAN_TAG_USED 1
51#endif
52
cd28ab6a
SH		 53#include "sky2.h"
54
55#define DRV_NAME "sky2"
cfc0861b 56#define DRV_VERSION "1.27"
cd28ab6a
SH		 57
58/*
59 * The Yukon II chipset takes 64 bit command blocks (called list elements)
60 * that are organized into three (receive, transmit, status) different rings
14d0263f 61 * similar to Tigon3.
cd28ab6a
SH		 62 */
63
14d0263f 64#define RX_LE_SIZE 1024
cd28ab6a 65#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 66#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 67#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 68
ee5f68fe 69/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 70 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
71#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 72#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
ee5f68fe
SH		 73#define TX_MAX_PENDING 4096
74#define TX_DEF_PENDING 127
cd28ab6a 75
793b883e 76#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 77#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
f4331a6d
SH		 82#define SKY2_EEPROM_MAGIC 0x9955aabb
83
84
cb5d9547
SH		 85#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
86
cd28ab6a 87static const u32 default_msg =
793b883e
SH		 88 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
89 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 90 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 91
793b883e 92static int debug = -1; /* defaults above */
cd28ab6a
SH		 93module_param(debug, int, 0);
94MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
95
14d0263f 96static int copybreak __read_mostly = 128;
bdb5c58e
SH		 97module_param(copybreak, int, 0);
98MODULE_PARM_DESC(copybreak, "Receive copy threshold");
99
fb2690a9
SH		 100static int disable_msi = 0;
101module_param(disable_msi, int, 0);
102MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
103
e6cac9ba 104static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 111 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 144 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 145 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 146 { 0 }
147};
793b883e 148
cd28ab6a
SH		 149MODULE_DEVICE_TABLE(pci, sky2_id_table);
150
151/* Avoid conditionals by using array */
152static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
153static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 154static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 155
d1b139c0
SH		 156static void sky2_set_multicast(struct net_device *dev);
157
af043aa5 158/* Access to PHY via serial interconnect */
ef743d33 159static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 160{
161 int i;
162
163 gma_write16(hw, port, GM_SMI_DATA, val);
164 gma_write16(hw, port, GM_SMI_CTRL,
165 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
166
167 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 168 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
169 if (ctrl == 0xffff)
170 goto io_error;
171
172 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 173 return 0;
af043aa5
SH		 174
175 udelay(10);
cd28ab6a 176 }
ef743d33 177
af043aa5 178 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 179 return -ETIMEDOUT;
af043aa5
SH		 180
181io_error:
182 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
183 return -EIO;
cd28ab6a
SH		 184}
185
ef743d33 186static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 187{
188 int i;
189
793b883e 190 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 191 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
192
193 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 194 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
195 if (ctrl == 0xffff)
196 goto io_error;
197
198 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 199 *val = gma_read16(hw, port, GM_SMI_DATA);
200 return 0;
201 }
202
af043aa5 203 udelay(10);
cd28ab6a
SH		 204 }
205
af043aa5 206 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 207 return -ETIMEDOUT;
af043aa5
SH		 208io_error:
209 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
210 return -EIO;
ef743d33
SH		 211}
212
af043aa5 213static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 214{
215 u16 v;
af043aa5 216 __gm_phy_read(hw, port, reg, &v);
ef743d33 217 return v;
cd28ab6a
SH		 218}
219
5afa0a9c 220
ae306cca
SH		 221static void sky2_power_on(struct sky2_hw *hw)
222{
223 /* switch power to VCC (WA for VAUX problem) */
224 sky2_write8(hw, B0_POWER_CTRL,
225 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 226
ae306cca
SH		 227 /* disable Core Clock Division, */
228 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 229
ae306cca
SH		 230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
231 /* enable bits are inverted */
232 sky2_write8(hw, B2_Y2_CLK_GATE,
233 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
234 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
235 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
236 else
237 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 238
ea76e635 239 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 240 u32 reg;
5afa0a9c 241
b32f40c4 242 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 243
b32f40c4 244 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 245 /* set all bits to 0 except bits 15..12 and 8 */
246 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 247 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 248
b32f40c4 249 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 250 /* set all bits to 0 except bits 28 & 27 */
251 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 252 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 253
b32f40c4 254 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 255
5f8ae5c5 256 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
257
8f70920f
SH		 258 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
259 reg = sky2_read32(hw, B2_GP_IO);
260 reg |= GLB_GPIO_STAT_RACE_DIS;
261 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 262
263 sky2_read32(hw, B2_GP_IO);
5afa0a9c 264 }
10547ae2
SH		 265
266 /* Turn on "driver loaded" LED */
267 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 268}
5afa0a9c 269
ae306cca
SH		 270static void sky2_power_aux(struct sky2_hw *hw)
271{
272 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
273 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
274 else
275 /* enable bits are inverted */
276 sky2_write8(hw, B2_Y2_CLK_GATE,
277 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
278 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
279 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
280
c23ddf8f
SH		 281 /* switch power to VAUX if supported and PME from D3cold */
282 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
283 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 284 sky2_write8(hw, B0_POWER_CTRL,
285 (PC_VAUX_ENA | PC_VCC_ENA |
286 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 287
288 /* turn off "driver loaded LED" */
289 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c
SH		 290}
291
d3bcfbeb 292static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 293{
294 u16 reg;
295
296 /* disable all GMAC IRQ's */
297 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 298
cd28ab6a
SH		 299 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
300 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
301 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
302 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
303
304 reg = gma_read16(hw, port, GM_RX_CTRL);
305 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
306 gma_write16(hw, port, GM_RX_CTRL, reg);
307}
308
16ad91e1
SH		 309/* flow control to advertise bits */
310static const u16 copper_fc_adv[] = {
311 [FC_NONE] = 0,
312 [FC_TX] = PHY_M_AN_ASP,
313 [FC_RX] = PHY_M_AN_PC,
314 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
315};
316
317/* flow control to advertise bits when using 1000BaseX */
318static const u16 fiber_fc_adv[] = {
df3fe1f3 319 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 320 [FC_TX] = PHY_M_P_ASYM_MD_X,
321 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 322 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 323};
324
325/* flow control to GMA disable bits */
326static const u16 gm_fc_disable[] = {
327 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
328 [FC_TX] = GM_GPCR_FC_RX_DIS,
329 [FC_RX] = GM_GPCR_FC_TX_DIS,
330 [FC_BOTH] = 0,
331};
332
333
cd28ab6a
SH		 334static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
335{
336 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 337 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 338
0ea065e5 339 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 340 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 341 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
342
343 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 344 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 345 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
346
53419c68 347 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 348 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 349 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 350 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
351 else
53419c68
SH		 352 /* set master & slave downshift counter to 1x */
353 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 354
355 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
356 }
357
358 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 359 if (sky2_is_copper(hw)) {
05745c4a 360 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 361 /* enable automatic crossover */
362 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 363
364 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
365 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
366 u16 spec;
367
368 /* Enable Class A driver for FE+ A0 */
369 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
370 spec |= PHY_M_FESC_SEL_CL_A;
371 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
372 }
cd28ab6a
SH		 373 } else {
374 /* disable energy detect */
375 ctrl &= ~PHY_M_PC_EN_DET_MSK;
376
377 /* enable automatic crossover */
378 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
379
53419c68 380 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 381 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
382 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 383 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 384 ctrl &= ~PHY_M_PC_DSC_MSK;
385 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
386 }
387 }
cd28ab6a
SH		 388 } else {
389 /* workaround for deviation #4.88 (CRC errors) */
390 /* disable Automatic Crossover */
391
392 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 393 }
cd28ab6a 394
b89165f2
SH		 395 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
396
397 /* special setup for PHY 88E1112 Fiber */
ea76e635 398 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 399 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 400
b89165f2
SH		 401 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
402 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
403 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
404 ctrl &= ~PHY_M_MAC_MD_MSK;
405 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
406 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
407
408 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 409 /* select page 1 to access Fiber registers */
410 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 411
412 /* for SFP-module set SIGDET polarity to low */
413 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
414 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 415 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 416 }
b89165f2
SH		 417
418 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 419 }
420
7800fddc 421 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 422 ct1000 = 0;
423 adv = PHY_AN_CSMA;
2eaba1a2 424 reg = 0;
cd28ab6a 425
0ea065e5 426 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 427 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 ct1000 |= PHY_M_1000C_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 ct1000 |= PHY_M_1000C_AHD;
432 if (sky2->advertising & ADVERTISED_100baseT_Full)
433 adv |= PHY_M_AN_100_FD;
434 if (sky2->advertising & ADVERTISED_100baseT_Half)
435 adv |= PHY_M_AN_100_HD;
436 if (sky2->advertising & ADVERTISED_10baseT_Full)
437 adv |= PHY_M_AN_10_FD;
438 if (sky2->advertising & ADVERTISED_10baseT_Half)
439 adv |= PHY_M_AN_10_HD;
709c6e7b 440
b89165f2
SH		 441 } else { /* special defines for FIBER (88E1040S only) */
442 if (sky2->advertising & ADVERTISED_1000baseT_Full)
443 adv |= PHY_M_AN_1000X_AFD;
444 if (sky2->advertising & ADVERTISED_1000baseT_Half)
445 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 446 }
cd28ab6a
SH		 447
448 /* Restart Auto-negotiation */
449 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
450 } else {
451 /* forced speed/duplex settings */
452 ct1000 = PHY_M_1000C_MSE;
453
0ea065e5
SH		 454 /* Disable auto update for duplex flow control and duplex */
455 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 456
457 switch (sky2->speed) {
458 case SPEED_1000:
459 ctrl |= PHY_CT_SP1000;
2eaba1a2 460 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 461 break;
462 case SPEED_100:
463 ctrl |= PHY_CT_SP100;
2eaba1a2 464 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 465 break;
466 }
467
2eaba1a2
SH		 468 if (sky2->duplex == DUPLEX_FULL) {
469 reg |= GM_GPCR_DUP_FULL;
470 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 471 } else if (sky2->speed < SPEED_1000)
472 sky2->flow_mode = FC_NONE;
0ea065e5 473 }
2eaba1a2 474
0ea065e5
SH		 475 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
476 if (sky2_is_copper(hw))
477 adv |= copper_fc_adv[sky2->flow_mode];
478 else
479 adv |= fiber_fc_adv[sky2->flow_mode];
480 } else {
481 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 482 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 483
484 /* Forward pause packets to GMAC? */
16ad91e1 485 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 486 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
487 else
488 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 489 }
490
2eaba1a2
SH		 491 gma_write16(hw, port, GM_GP_CTRL, reg);
492
05745c4a 493 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 494 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
495
496 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
497 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
498
499 /* Setup Phy LED's */
500 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
501 ledover = 0;
502
503 switch (hw->chip_id) {
504 case CHIP_ID_YUKON_FE:
505 /* on 88E3082 these bits are at 11..9 (shifted left) */
506 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
507
508 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
509
510 /* delete ACT LED control bits */
511 ctrl &= ~PHY_M_FELP_LED1_MSK;
512 /* change ACT LED control to blink mode */
513 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
514 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
515 break;
516
05745c4a
SH		 517 case CHIP_ID_YUKON_FE_P:
518 /* Enable Link Partner Next Page */
519 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
520 ctrl |= PHY_M_PC_ENA_LIP_NP;
521
522 /* disable Energy Detect and enable scrambler */
523 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
524 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
525
526 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
527 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
528 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
529 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
530
531 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
532 break;
533
cd28ab6a 534 case CHIP_ID_YUKON_XL:
793b883e 535 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 536
537 /* select page 3 to access LED control register */
538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
539
540 /* set LED Function Control register */
ed6d32c7
SH		 541 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
542 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
543 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
544 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
545 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 546
547 /* set Polarity Control register */
548 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 549 (PHY_M_POLC_LS1_P_MIX(4) |
550 PHY_M_POLC_IS0_P_MIX(4) |
551 PHY_M_POLC_LOS_CTRL(2) |
552 PHY_M_POLC_INIT_CTRL(2) |
553 PHY_M_POLC_STA1_CTRL(2) |
554 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 555
556 /* restore page register */
793b883e 557 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 558 break;
93745494 559
ed6d32c7 560 case CHIP_ID_YUKON_EC_U:
93745494 561 case CHIP_ID_YUKON_EX:
ed4d4161 562 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 563 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
564
565 /* select page 3 to access LED control register */
566 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
567
568 /* set LED Function Control register */
569 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
570 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
571 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
572 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
573 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
574
575 /* set Blink Rate in LED Timer Control Register */
576 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
577 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
578 /* restore page register */
579 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
580 break;
cd28ab6a
SH		 581
582 default:
583 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
584 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 585
cd28ab6a 586 /* turn off the Rx LED (LED_RX) */
a84d0a3d 587 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 588 }
589
0ce8b98d 590 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 591 /* apply fixes in PHY AFE */
ed6d32c7
SH		 592 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
593
977bdf06 594 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 595 gm_phy_write(hw, port, 0x18, 0xaa99);
596 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 597
0ce8b98d
SH		 598 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
599 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
600 gm_phy_write(hw, port, 0x18, 0xa204);
601 gm_phy_write(hw, port, 0x17, 0x2002);
602 }
977bdf06
SH		 603
604 /* set page register to 0 */
9467a8fc 605 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 606 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
607 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
608 /* apply workaround for integrated resistors calibration */
609 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
610 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 611 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
612 /* apply fixes in PHY AFE */
613 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
614
615 /* apply RDAC termination workaround */
616 gm_phy_write(hw, port, 24, 0x2800);
617 gm_phy_write(hw, port, 23, 0x2001);
618
619 /* set page register back to 0 */
620 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 621 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
622 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 623 /* no effect on Yukon-XL */
977bdf06 624 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 625
8e95a202
JP		 626 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
627 sky2->speed == SPEED_100) {
977bdf06 628 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 629 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 630 }
cd28ab6a 631
977bdf06
SH		 632 if (ledover)
633 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
634
635 }
2eaba1a2 636
d571b694 637 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 638 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 639 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
640 else
641 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
642}
643
b96936da
SH		 644static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
645static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
646
647static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 648{
649 u32 reg1;
d3bcfbeb 650
a40ccc68 651 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 652 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 653 reg1 &= ~phy_power[port];
d3bcfbeb 654
b96936da 655 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 656 reg1 |= coma_mode[port];
657
b32f40c4 658 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 659 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 660 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 661
662 if (hw->chip_id == CHIP_ID_YUKON_FE)
663 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
664 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
665 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 666}
167f53d0 667
b96936da
SH		 668static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
669{
670 u32 reg1;
db99b988
SH		 671 u16 ctrl;
672
673 /* release GPHY Control reset */
674 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
675
676 /* release GMAC reset */
677 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
678
679 if (hw->flags & SKY2_HW_NEWER_PHY) {
680 /* select page 2 to access MAC control register */
681 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
682
683 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
684 /* allow GMII Power Down */
685 ctrl &= ~PHY_M_MAC_GMIF_PUP;
686 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
687
688 /* set page register back to 0 */
689 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
690 }
691
692 /* setup General Purpose Control Register */
693 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 694 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
695 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
696 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 697
698 if (hw->chip_id != CHIP_ID_YUKON_EC) {
699 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 700 /* select page 2 to access MAC control register */
701 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 702
e484d5f5 703 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 704 /* enable Power Down */
705 ctrl |= PHY_M_PC_POW_D_ENA;
706 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 707
708 /* set page register back to 0 */
709 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 710 }
711
712 /* set IEEE compatible Power Down Mode (dev. #4.99) */
713 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
714 }
b96936da 715
a40ccc68 716 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 717 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 718 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 719 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 720 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 721}
722
1b537565
SH		 723/* Force a renegotiation */
724static void sky2_phy_reinit(struct sky2_port *sky2)
725{
e07b1aa8 726 spin_lock_bh(&sky2->phy_lock);
1b537565 727 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 728 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 729}
730
e3173832
SH		 731/* Put device in state to listen for Wake On Lan */
732static void sky2_wol_init(struct sky2_port *sky2)
733{
734 struct sky2_hw *hw = sky2->hw;
735 unsigned port = sky2->port;
736 enum flow_control save_mode;
737 u16 ctrl;
e3173832
SH		 738
739 /* Bring hardware out of reset */
740 sky2_write16(hw, B0_CTST, CS_RST_CLR);
741 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
742
743 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
744 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
745
746 /* Force to 10/100
747 * sky2_reset will re-enable on resume
748 */
749 save_mode = sky2->flow_mode;
750 ctrl = sky2->advertising;
751
752 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
753 sky2->flow_mode = FC_NONE;
b96936da
SH		 754
755 spin_lock_bh(&sky2->phy_lock);
756 sky2_phy_power_up(hw, port);
757 sky2_phy_init(hw, port);
758 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 759
760 sky2->flow_mode = save_mode;
761 sky2->advertising = ctrl;
762
763 /* Set GMAC to no flow control and auto update for speed/duplex */
764 gma_write16(hw, port, GM_GP_CTRL,
765 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
766 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
767
768 /* Set WOL address */
769 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
770 sky2->netdev->dev_addr, ETH_ALEN);
771
772 /* Turn on appropriate WOL control bits */
773 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
774 ctrl = 0;
775 if (sky2->wol & WAKE_PHY)
776 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
777 else
778 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
779
780 if (sky2->wol & WAKE_MAGIC)
781 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
782 else
a419aef8 783 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 784
785 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
786 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
787
5f8ae5c5 788 /* Disable PiG firmware */
789 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
790
e3173832
SH		 791 /* block receiver */
792 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
e3173832
SH		 793}
794
69161611
SH		 795static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
796{
05745c4a
SH		 797 struct net_device *dev = hw->dev[port];
798
ed4d4161
SH		 799 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
800 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 801 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161 802 /* Yukon-Extreme B0 and further Extreme devices */
44dde56d 803 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
804 } else if (dev->mtu > ETH_DATA_LEN) {
805 /* set Tx GMAC FIFO Almost Empty Threshold */
806 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
807 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
05745c4a 808
44dde56d 809 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
810 } else
811 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
69161611
SH		 812}
813
cd28ab6a
SH		 814static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
815{
816 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
817 u16 reg;
25cccecc 818 u32 rx_reg;
cd28ab6a
SH		 819 int i;
820 const u8 *addr = hw->dev[port]->dev_addr;
821
f350339c
SH		 822 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
823 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 824
825 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
826
793b883e 827 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 828 /* WA DEV_472 -- looks like crossed wires on port 2 */
829 /* clear GMAC 1 Control reset */
830 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
831 do {
832 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
833 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
834 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
835 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
836 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
837 }
838
793b883e 839 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 840
2eaba1a2
SH		 841 /* Enable Transmit FIFO Underrun */
842 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
843
e07b1aa8 844 spin_lock_bh(&sky2->phy_lock);
b96936da 845 sky2_phy_power_up(hw, port);
cd28ab6a 846 sky2_phy_init(hw, port);
e07b1aa8 847 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 848
849 /* MIB clear */
850 reg = gma_read16(hw, port, GM_PHY_ADDR);
851 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
852
43f2f104
SH		 853 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
854 gma_read16(hw, port, i);
cd28ab6a
SH		 855 gma_write16(hw, port, GM_PHY_ADDR, reg);
856
857 /* transmit control */
858 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
859
860 /* receive control reg: unicast + multicast + no FCS */
861 gma_write16(hw, port, GM_RX_CTRL,
793b883e 862 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 863
864 /* transmit flow control */
865 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
866
867 /* transmit parameter */
868 gma_write16(hw, port, GM_TX_PARAM,
869 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
870 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
871 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
872 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
873
874 /* serial mode register */
875 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 876 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 877
6b1a3aef 878 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 879 reg |= GM_SMOD_JUMBO_ENA;
880
881 gma_write16(hw, port, GM_SERIAL_MODE, reg);
882
cd28ab6a
SH		 883 /* virtual address for data */
884 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
885
793b883e
SH		 886 /* physical address: used for pause frames */
887 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
888
889 /* ignore counter overflows */
cd28ab6a
SH		 890 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
891 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
892 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
893
894 /* Configure Rx MAC FIFO */
895 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 896 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 897 if (hw->chip_id == CHIP_ID_YUKON_EX ||
898 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 899 rx_reg |= GMF_RX_OVER_ON;
69161611 900
25cccecc 901 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 902
798fdd07
SH		 903 if (hw->chip_id == CHIP_ID_YUKON_XL) {
904 /* Hardware errata - clear flush mask */
905 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
906 } else {
907 /* Flush Rx MAC FIFO on any flow control or error */
908 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
909 }
cd28ab6a 910
8df9a876 911 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 912 reg = RX_GMF_FL_THR_DEF + 1;
913 /* Another magic mystery workaround from sk98lin */
914 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
915 hw->chip_rev == CHIP_REV_YU_FE2_A0)
916 reg = 0x178;
917 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 918
919 /* Configure Tx MAC FIFO */
920 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
921 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 922
e0c28116 923 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 924 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 925 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 926 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
927 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 928 reg = 1568 / 8;
929 else
930 reg = 1024 / 8;
931 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
932 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 933
69161611 934 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 935 }
936
e970d1f8
SH		 937 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
938 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
939 /* disable dynamic watermark */
940 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
941 reg &= ~TX_DYN_WM_ENA;
942 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
943 }
cd28ab6a
SH		 944}
945
67712901
SH		 946/* Assign Ram Buffer allocation to queue */
947static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 948{
67712901
SH		 949 u32 end;
950
951 /* convert from K bytes to qwords used for hw register */
952 start *= 1024/8;
953 space *= 1024/8;
954 end = start + space - 1;
793b883e 955
cd28ab6a
SH		 956 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
957 sky2_write32(hw, RB_ADDR(q, RB_START), start);
958 sky2_write32(hw, RB_ADDR(q, RB_END), end);
959 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
960 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
961
962 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 963 u32 tp = space - space/4;
793b883e 964
1c28f6ba
SH		 965 /* On receive queue's set the thresholds
966 * give receiver priority when > 3/4 full
967 * send pause when down to 2K
968 */
969 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
970 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 971
1c28f6ba
SH		 972 tp = space - 2048/8;
973 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
974 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 975 } else {
976 /* Enable store & forward on Tx queue's because
977 * Tx FIFO is only 1K on Yukon
978 */
979 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
980 }
981
982 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 983 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 984}
985
cd28ab6a 986/* Setup Bus Memory Interface */
af4ed7e6 987static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 988{
989 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
990 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
991 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 992 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 993}
994
cd28ab6a
SH		 995/* Setup prefetch unit registers. This is the interface between
996 * hardware and driver list elements
997 */
8cc048e3 998static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 999 dma_addr_t addr, u32 last)
cd28ab6a 1000{
cd28ab6a
SH		 1001 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1002 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1003 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1004 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1005 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1006 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1007
1008 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1009}
1010
9b289c33 1011static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1012{
9b289c33 1013 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1014
ee5f68fe 1015 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1016 le->ctrl = 0;
793b883e
SH		 1017 return le;
1018}
cd28ab6a 1019
88f5f0ca
SH		 1020static void tx_init(struct sky2_port *sky2)
1021{
1022 struct sky2_tx_le *le;
1023
1024 sky2->tx_prod = sky2->tx_cons = 0;
1025 sky2->tx_tcpsum = 0;
1026 sky2->tx_last_mss = 0;
1027
9b289c33 1028 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1029 le->addr = 0;
1030 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1031 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1032}
1033
290d4de5
SH		 1034/* Update chip's next pointer */
1035static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1036{
50432cb5 1037 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1038 wmb();
50432cb5
SH		 1039 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1040
1041 /* Synchronize I/O on since next processor may write to tail */
1042 mmiowb();
cd28ab6a
SH		 1043}
1044
793b883e 1045
cd28ab6a
SH		 1046static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1047{
1048 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1049 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1050 le->ctrl = 0;
cd28ab6a
SH		 1051 return le;
1052}
1053
39ef110b
MM		 1054static unsigned sky2_get_rx_threshold(struct sky2_port* sky2)
1055{
1056 unsigned size;
1057
1058 /* Space needed for frame data + headers rounded up */
1059 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1060
1061 /* Stopping point for hardware truncation */
1062 return (size - 8) / sizeof(u32);
1063}
1064
1065static unsigned sky2_get_rx_data_size(struct sky2_port* sky2)
1066{
1067 struct rx_ring_info *re;
1068 unsigned size;
1069
1070 /* Space needed for frame data + headers rounded up */
1071 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1072
1073 sky2->rx_nfrags = size >> PAGE_SHIFT;
1074 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1075
1076 /* Compute residue after pages */
1077 size -= sky2->rx_nfrags << PAGE_SHIFT;
1078
1079 /* Optimize to handle small packets and headers */
1080 if (size < copybreak)
1081 size = copybreak;
1082 if (size < ETH_HLEN)
1083 size = ETH_HLEN;
1084
1085 return size;
1086}
1087
14d0263f
SH		 1088/* Build description to hardware for one receive segment */
1089static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1090 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1091{
1092 struct sky2_rx_le *le;
1093
86c6887e 1094 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1095 le = sky2_next_rx(sky2);
86c6887e 1096 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1097 le->opcode = OP_ADDR64 | HW_OWNER;
1098 }
793b883e 1099
cd28ab6a 1100 le = sky2_next_rx(sky2);
d6e74b6b 1101 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1102 le->length = cpu_to_le16(len);
14d0263f 1103 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1104}
1105
14d0263f
SH		 1106/* Build description to hardware for one possibly fragmented skb */
1107static void sky2_rx_submit(struct sky2_port *sky2,
1108 const struct rx_ring_info *re)
1109{
1110 int i;
1111
1112 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1113
1114 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1115 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1116}
1117
1118
454e6cb6 1119static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1120 unsigned size)
1121{
1122 struct sk_buff *skb = re->skb;
1123 int i;
1124
1125 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1126 if (pci_dma_mapping_error(pdev, re->data_addr))
1127 goto mapping_error;
454e6cb6 1128
14d0263f
SH		 1129 pci_unmap_len_set(re, data_size, size);
1130
3fbd9187 1131 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1132 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1133
1134 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1135 frag->page_offset,
1136 frag->size,
14d0263f 1137 PCI_DMA_FROMDEVICE);
3fbd9187 1138
1139 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1140 goto map_page_error;
1141 }
454e6cb6 1142 return 0;
3fbd9187 1143
1144map_page_error:
1145 while (--i >= 0) {
1146 pci_unmap_page(pdev, re->frag_addr[i],
1147 skb_shinfo(skb)->frags[i].size,
1148 PCI_DMA_FROMDEVICE);
1149 }
1150
1151 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1152 PCI_DMA_FROMDEVICE);
1153
1154mapping_error:
1155 if (net_ratelimit())
1156 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1157 skb->dev->name);
1158 return -EIO;
14d0263f
SH		 1159}
1160
1161static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1162{
1163 struct sk_buff *skb = re->skb;
1164 int i;
1165
1166 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1167 PCI_DMA_FROMDEVICE);
1168
1169 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1170 pci_unmap_page(pdev, re->frag_addr[i],
1171 skb_shinfo(skb)->frags[i].size,
1172 PCI_DMA_FROMDEVICE);
1173}
793b883e 1174
cd28ab6a
SH		 1175/* Tell chip where to start receive checksum.
1176 * Actually has two checksums, but set both same to avoid possible byte
1177 * order problems.
1178 */
793b883e 1179static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1180{
ea76e635 1181 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1182
ea76e635
SH		 1183 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1184 le->ctrl = 0;
1185 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1186
ea76e635
SH		 1187 sky2_write32(sky2->hw,
1188 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1189 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1190 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1191}
1192
6b1a3aef
SH		 1193/*
1194 * The RX Stop command will not work for Yukon-2 if the BMU does not
1195 * reach the end of packet and since we can't make sure that we have
1196 * incoming data, we must reset the BMU while it is not doing a DMA
1197 * transfer. Since it is possible that the RX path is still active,
1198 * the RX RAM buffer will be stopped first, so any possible incoming
1199 * data will not trigger a DMA. After the RAM buffer is stopped, the
1200 * BMU is polled until any DMA in progress is ended and only then it
1201 * will be reset.
1202 */
1203static void sky2_rx_stop(struct sky2_port *sky2)
1204{
1205 struct sky2_hw *hw = sky2->hw;
1206 unsigned rxq = rxqaddr[sky2->port];
1207 int i;
1208
1209 /* disable the RAM Buffer receive queue */
1210 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1211
1212 for (i = 0; i < 0xffff; i++)
1213 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1214 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1215 goto stopped;
1216
ada1db5c 1217 netdev_warn(sky2->netdev, "receiver stop failed\n");
6b1a3aef
SH		 1218stopped:
1219 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1220
1221 /* reset the Rx prefetch unit */
1222 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1223 mmiowb();
6b1a3aef 1224}
793b883e 1225
d571b694 1226/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1227static void sky2_rx_clean(struct sky2_port *sky2)
1228{
1229 unsigned i;
1230
1231 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1232 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1233 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1234
1235 if (re->skb) {
14d0263f 1236 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1237 kfree_skb(re->skb);
1238 re->skb = NULL;
1239 }
1240 }
1241}
1242
ef743d33
SH		 1243/* Basic MII support */
1244static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1245{
1246 struct mii_ioctl_data *data = if_mii(ifr);
1247 struct sky2_port *sky2 = netdev_priv(dev);
1248 struct sky2_hw *hw = sky2->hw;
1249 int err = -EOPNOTSUPP;
1250
1251 if (!netif_running(dev))
1252 return -ENODEV; /* Phy still in reset */
1253
d89e1343 1254 switch (cmd) {
ef743d33
SH		 1255 case SIOCGMIIPHY:
1256 data->phy_id = PHY_ADDR_MARV;
1257
1258 /* fallthru */
1259 case SIOCGMIIREG: {
1260 u16 val = 0;
91c86df5 1261
e07b1aa8 1262 spin_lock_bh(&sky2->phy_lock);
ef743d33 1263 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1264 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1265
ef743d33
SH		 1266 data->val_out = val;
1267 break;
1268 }
1269
1270 case SIOCSMIIREG:
e07b1aa8 1271 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1272 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1273 data->val_in);
e07b1aa8 1274 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1275 break;
1276 }
1277 return err;
1278}
1279
d1f13708 1280#ifdef SKY2_VLAN_TAG_USED
d494eacd 1281static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1282{
d494eacd 1283 if (onoff) {
3d4e66f5
SH		 1284 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1285 RX_VLAN_STRIP_ON);
1286 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1287 TX_VLAN_TAG_ON);
1288 } else {
1289 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1290 RX_VLAN_STRIP_OFF);
1291 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1292 TX_VLAN_TAG_OFF);
1293 }
d494eacd
SH		 1294}
1295
1296static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1297{
1298 struct sky2_port *sky2 = netdev_priv(dev);
1299 struct sky2_hw *hw = sky2->hw;
1300 u16 port = sky2->port;
1301
1302 netif_tx_lock_bh(dev);
1303 napi_disable(&hw->napi);
1304
1305 sky2->vlgrp = grp;
1306 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1307
d1d08d12 1308 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1309 napi_enable(&hw->napi);
2bb8c262 1310 netif_tx_unlock_bh(dev);
d1f13708
SH		 1311}
1312#endif
1313
bd1c6869
SH		 1314/* Amount of required worst case padding in rx buffer */
1315static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1316{
1317 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1318}
1319
82788c7a 1320/*
14d0263f
SH		 1321 * Allocate an skb for receiving. If the MTU is large enough
1322 * make the skb non-linear with a fragment list of pages.
82788c7a 1323 */
14d0263f 1324static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1325{
1326 struct sk_buff *skb;
14d0263f 1327 int i;
82788c7a 1328
724b6942
SH		 1329 skb = netdev_alloc_skb(sky2->netdev,
1330 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1331 if (!skb)
1332 goto nomem;
1333
39dbd958 1334 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1335 unsigned char *start;
1336 /*
1337 * Workaround for a bug in FIFO that cause hang
1338 * if the FIFO if the receive buffer is not 64 byte aligned.
1339 * The buffer returned from netdev_alloc_skb is
1340 * aligned except if slab debugging is enabled.
1341 */
f03b8654
SH		 1342 start = PTR_ALIGN(skb->data, 8);
1343 skb_reserve(skb, start - skb->data);
bd1c6869 1344 } else
f03b8654 1345 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1346
1347 for (i = 0; i < sky2->rx_nfrags; i++) {
1348 struct page *page = alloc_page(GFP_ATOMIC);
1349
1350 if (!page)
1351 goto free_partial;
1352 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1353 }
1354
1355 return skb;
14d0263f
SH		 1356free_partial:
1357 kfree_skb(skb);
1358nomem:
1359 return NULL;
82788c7a
SH		 1360}
1361
55c9dd35
SH		 1362static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1363{
1364 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1365}
1366
200ac492
MM		 1367static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1368{
1369 struct sky2_hw *hw = sky2->hw;
1370 unsigned i;
1371
1372 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1373
1374 /* Fill Rx ring */
1375 for (i = 0; i < sky2->rx_pending; i++) {
1376 struct rx_ring_info *re = sky2->rx_ring + i;
1377
1378 re->skb = sky2_rx_alloc(sky2);
1379 if (!re->skb)
1380 return -ENOMEM;
1381
1382 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1383 dev_kfree_skb(re->skb);
1384 re->skb = NULL;
1385 return -ENOMEM;
1386 }
1387 }
1388 return 0;
1389}
1390
cd28ab6a 1391/*
200ac492 1392 * Setup receiver buffer pool.
14d0263f
SH		 1393 * Normal case this ends up creating one list element for skb
1394 * in the receive ring. Worst case if using large MTU and each
1395 * allocation falls on a different 64 bit region, that results
1396 * in 6 list elements per ring entry.
1397 * One element is used for checksum enable/disable, and one
1398 * extra to avoid wrap.
cd28ab6a 1399 */
200ac492 1400static void sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1401{
6b1a3aef 1402 struct sky2_hw *hw = sky2->hw;
14d0263f 1403 struct rx_ring_info *re;
6b1a3aef 1404 unsigned rxq = rxqaddr[sky2->port];
39ef110b 1405 unsigned i, thresh;
cd28ab6a 1406
6b1a3aef 1407 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1408 sky2_qset(hw, rxq);
977bdf06 1409
c3905bc4
SH		 1410 /* On PCI express lowering the watermark gives better performance */
1411 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1412 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1413
1414 /* These chips have no ram buffer?
1415 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1416 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
8e95a202
JP		 1417 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1418 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1419 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1420
6b1a3aef
SH		 1421 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1422
ea76e635
SH		 1423 if (!(hw->flags & SKY2_HW_NEW_LE))
1424 rx_set_checksum(sky2);
14d0263f 1425
200ac492 1426 /* submit Rx ring */
793b883e 1427 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1428 re = sky2->rx_ring + i;
14d0263f 1429 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1430 }
1431
a1433ac4
SH		 1432 /*
1433 * The receiver hangs if it receives frames larger than the
1434 * packet buffer. As a workaround, truncate oversize frames, but
1435 * the register is limited to 9 bits, so if you do frames > 2052
1436 * you better get the MTU right!
1437 */
39ef110b 1438 thresh = sky2_get_rx_threshold(sky2);
a1433ac4
SH		 1439 if (thresh > 0x1ff)
1440 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1441 else {
1442 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1443 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1444 }
1445
6b1a3aef 1446 /* Tell chip about available buffers */
55c9dd35 1447 sky2_rx_update(sky2, rxq);
877c8570
SH		 1448
1449 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1450 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1451 /*
1452 * Disable flushing of non ASF packets;
1453 * must be done after initializing the BMUs;
1454 * drivers without ASF support should do this too, otherwise
1455 * it may happen that they cannot run on ASF devices;
1456 * remember that the MAC FIFO isn't reset during initialization.
1457 */
1458 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1459 }
1460
1461 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1462 /* Enable RX Home Address & Routing Header checksum fix */
1463 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1464 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1465
1466 /* Enable TX Home Address & Routing Header checksum fix */
1467 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1468 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1469 }
cd28ab6a
SH		 1470}
1471
90bbebb4
MM		 1472static int sky2_alloc_buffers(struct sky2_port *sky2)
1473{
1474 struct sky2_hw *hw = sky2->hw;
1475
1476 /* must be power of 2 */
1477 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1478 sky2->tx_ring_size *
1479 sizeof(struct sky2_tx_le),
1480 &sky2->tx_le_map);
1481 if (!sky2->tx_le)
1482 goto nomem;
1483
1484 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1485 GFP_KERNEL);
1486 if (!sky2->tx_ring)
1487 goto nomem;
1488
1489 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1490 &sky2->rx_le_map);
1491 if (!sky2->rx_le)
1492 goto nomem;
1493 memset(sky2->rx_le, 0, RX_LE_BYTES);
1494
1495 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1496 GFP_KERNEL);
1497 if (!sky2->rx_ring)
1498 goto nomem;
1499
200ac492 1500 return sky2_alloc_rx_skbs(sky2);
90bbebb4
MM		 1501nomem:
1502 return -ENOMEM;
1503}
1504
1505static void sky2_free_buffers(struct sky2_port *sky2)
1506{
1507 struct sky2_hw *hw = sky2->hw;
1508
200ac492
MM		 1509 sky2_rx_clean(sky2);
1510
90bbebb4
MM		 1511 if (sky2->rx_le) {
1512 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1513 sky2->rx_le, sky2->rx_le_map);
1514 sky2->rx_le = NULL;
1515 }
1516 if (sky2->tx_le) {
1517 pci_free_consistent(hw->pdev,
1518 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1519 sky2->tx_le, sky2->tx_le_map);
1520 sky2->tx_le = NULL;
1521 }
1522 kfree(sky2->tx_ring);
1523 kfree(sky2->rx_ring);
1524
1525 sky2->tx_ring = NULL;
1526 sky2->rx_ring = NULL;
1527}
1528
ea0f71e5 1529static void sky2_hw_up(struct sky2_port *sky2)
cd28ab6a 1530{
cd28ab6a
SH		 1531 struct sky2_hw *hw = sky2->hw;
1532 unsigned port = sky2->port;
ea0f71e5
MM		 1533 u32 ramsize;
1534 int cap;
843a46f4 1535 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1536
ea0f71e5
MM		 1537 tx_init(sky2);
1538
ee7abb04
SH		 1539 /*
1540 * On dual port PCI-X card, there is an problem where status
1541 * can be received out of order due to split transactions
843a46f4 1542 */
ee7abb04
SH		 1543 if (otherdev && netif_running(otherdev) &&
1544 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1545 u16 cmd;
1546
b32f40c4 1547 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1548 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4 1549 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
ea0f71e5 1550 }
cd28ab6a 1551
cd28ab6a
SH		 1552 sky2_mac_init(hw, port);
1553
e0c28116
SH		 1554 /* Register is number of 4K blocks on internal RAM buffer. */
1555 ramsize = sky2_read8(hw, B2_E_0) * 4;
1556 if (ramsize > 0) {
67712901 1557 u32 rxspace;
cd28ab6a 1558
ada1db5c 1559 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
67712901
SH		 1560 if (ramsize < 16)
1561 rxspace = ramsize / 2;
1562 else
1563 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1564
67712901
SH		 1565 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1566 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1567
1568 /* Make sure SyncQ is disabled */
1569 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1570 RB_RST_SET);
1571 }
793b883e 1572
af4ed7e6 1573 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1574
69161611
SH		 1575 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1576 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1577 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1578
977bdf06 1579 /* Set almost empty threshold */
8e95a202
JP		 1580 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1581 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1582 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1583
6b1a3aef 1584 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1585 sky2->tx_ring_size - 1);
cd28ab6a 1586
d494eacd
SH		 1587#ifdef SKY2_VLAN_TAG_USED
1588 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1589#endif
1590
200ac492 1591 sky2_rx_start(sky2);
ea0f71e5
MM		 1592}
1593
1594/* Bring up network interface. */
1595static int sky2_up(struct net_device *dev)
1596{
1597 struct sky2_port *sky2 = netdev_priv(dev);
1598 struct sky2_hw *hw = sky2->hw;
1599 unsigned port = sky2->port;
1600 u32 imask;
1601 int err;
1602
1603 netif_carrier_off(dev);
1604
1605 err = sky2_alloc_buffers(sky2);
1606 if (err)
1607 goto err_out;
1608
1609 sky2_hw_up(sky2);
cd28ab6a 1610
cd28ab6a 1611 /* Enable interrupts from phy/mac for port */
e07b1aa8 1612 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1613 imask |= portirq_msk[port];
e07b1aa8 1614 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1615 sky2_read32(hw, B0_IMSK);
e07b1aa8 1616
6c35abae 1617 netif_info(sky2, ifup, dev, "enabling interface\n");
af18d8b8 1618
cd28ab6a
SH		 1619 return 0;
1620
1621err_out:
90bbebb4 1622 sky2_free_buffers(sky2);
cd28ab6a
SH		 1623 return err;
1624}
1625
793b883e 1626/* Modular subtraction in ring */
ee5f68fe 1627static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1628{
ee5f68fe 1629 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1630}
cd28ab6a 1631
793b883e
SH		 1632/* Number of list elements available for next tx */
1633static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1634{
ee5f68fe 1635 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1636}
1637
793b883e 1638/* Estimate of number of transmit list elements required */
28bd181a 1639static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1640{
793b883e
SH		 1641 unsigned count;
1642
07e31637
SH		 1643 count = (skb_shinfo(skb)->nr_frags + 1)
1644 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1645
89114afd 1646 if (skb_is_gso(skb))
793b883e 1647 ++count;
07e31637
SH		 1648 else if (sizeof(dma_addr_t) == sizeof(u32))
1649 ++count; /* possible vlan */
793b883e 1650
84fa7933 1651 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1652 ++count;
1653
1654 return count;
cd28ab6a
SH		 1655}
1656
f6815077 1657static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1658{
1659 if (re->flags & TX_MAP_SINGLE)
1660 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1661 pci_unmap_len(re, maplen),
1662 PCI_DMA_TODEVICE);
1663 else if (re->flags & TX_MAP_PAGE)
1664 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1665 pci_unmap_len(re, maplen),
1666 PCI_DMA_TODEVICE);
f6815077 1667 re->flags = 0;
6b84daca
SH		 1668}
1669
793b883e
SH		 1670/*
1671 * Put one packet in ring for transmit.
1672 * A single packet can generate multiple list elements, and
1673 * the number of ring elements will probably be less than the number
1674 * of list elements used.
1675 */
61357325
SH		 1676static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1677 struct net_device *dev)
cd28ab6a
SH		 1678{
1679 struct sky2_port *sky2 = netdev_priv(dev);
1680 struct sky2_hw *hw = sky2->hw;
d1f13708 1681 struct sky2_tx_le *le = NULL;
6cdbbdf3 1682 struct tx_ring_info *re;
9b289c33 1683 unsigned i, len;
cd28ab6a 1684 dma_addr_t mapping;
5dce95e5
SH		 1685 u32 upper;
1686 u16 slot;
cd28ab6a
SH		 1687 u16 mss;
1688 u8 ctrl;
1689
2bb8c262
SH		 1690 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1691 return NETDEV_TX_BUSY;
cd28ab6a 1692
cd28ab6a
SH		 1693 len = skb_headlen(skb);
1694 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1695
454e6cb6
SH		 1696 if (pci_dma_mapping_error(hw->pdev, mapping))
1697 goto mapping_error;
1698
9b289c33 1699 slot = sky2->tx_prod;
6c35abae
JP		 1700 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1701 "tx queued, slot %u, len %d\n", slot, skb->len);
454e6cb6 1702
86c6887e 1703 /* Send high bits if needed */
5dce95e5
SH		 1704 upper = upper_32_bits(mapping);
1705 if (upper != sky2->tx_last_upper) {
9b289c33 1706 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1707 le->addr = cpu_to_le32(upper);
1708 sky2->tx_last_upper = upper;
793b883e 1709 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1710 }
cd28ab6a
SH		 1711
1712 /* Check for TCP Segmentation Offload */
7967168c 1713 mss = skb_shinfo(skb)->gso_size;
793b883e 1714 if (mss != 0) {
ea76e635
SH		 1715
1716 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1717 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1718
1719 if (mss != sky2->tx_last_mss) {
9b289c33 1720 le = get_tx_le(sky2, &slot);
69161611 1721 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1722
1723 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1724 le->opcode = OP_MSS | HW_OWNER;
1725 else
1726 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1727 sky2->tx_last_mss = mss;
1728 }
cd28ab6a
SH		 1729 }
1730
cd28ab6a 1731 ctrl = 0;
d1f13708
SH		 1732#ifdef SKY2_VLAN_TAG_USED
1733 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1734 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1735 if (!le) {
9b289c33 1736 le = get_tx_le(sky2, &slot);
f65b138c 1737 le->addr = 0;
d1f13708 1738 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1739 } else
1740 le->opcode |= OP_VLAN;
1741 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1742 ctrl |= INS_VLAN;
1743 }
1744#endif
1745
1746 /* Handle TCP checksum offload */
84fa7933 1747 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1748 /* On Yukon EX (some versions) encoding change. */
ea76e635 1749 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1750 ctrl |= CALSUM; /* auto checksum */
1751 else {
1752 const unsigned offset = skb_transport_offset(skb);
1753 u32 tcpsum;
1754
1755 tcpsum = offset << 16; /* sum start */
1756 tcpsum |= offset + skb->csum_offset; /* sum write */
1757
1758 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1759 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1760 ctrl |= UDPTCP;
1761
1762 if (tcpsum != sky2->tx_tcpsum) {
1763 sky2->tx_tcpsum = tcpsum;
1764
9b289c33 1765 le = get_tx_le(sky2, &slot);
69161611
SH		 1766 le->addr = cpu_to_le32(tcpsum);
1767 le->length = 0; /* initial checksum value */
1768 le->ctrl = 1; /* one packet */
1769 le->opcode = OP_TCPLISW | HW_OWNER;
1770 }
1d179332 1771 }
cd28ab6a
SH		 1772 }
1773
6b84daca
SH		 1774 re = sky2->tx_ring + slot;
1775 re->flags = TX_MAP_SINGLE;
1776 pci_unmap_addr_set(re, mapaddr, mapping);
1777 pci_unmap_len_set(re, maplen, len);
1778
9b289c33 1779 le = get_tx_le(sky2, &slot);
d6e74b6b 1780 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1781 le->length = cpu_to_le16(len);
1782 le->ctrl = ctrl;
793b883e 1783 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1784
cd28ab6a
SH		 1785
1786 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1787 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1788
1789 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1790 frag->size, PCI_DMA_TODEVICE);
86c6887e 1791
454e6cb6
SH		 1792 if (pci_dma_mapping_error(hw->pdev, mapping))
1793 goto mapping_unwind;
1794
5dce95e5
SH		 1795 upper = upper_32_bits(mapping);
1796 if (upper != sky2->tx_last_upper) {
9b289c33 1797 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1798 le->addr = cpu_to_le32(upper);
1799 sky2->tx_last_upper = upper;
793b883e 1800 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1801 }
1802
6b84daca
SH		 1803 re = sky2->tx_ring + slot;
1804 re->flags = TX_MAP_PAGE;
1805 pci_unmap_addr_set(re, mapaddr, mapping);
1806 pci_unmap_len_set(re, maplen, frag->size);
1807
9b289c33 1808 le = get_tx_le(sky2, &slot);
d6e74b6b 1809 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1810 le->length = cpu_to_le16(frag->size);
1811 le->ctrl = ctrl;
793b883e 1812 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1813 }
6cdbbdf3 1814
6b84daca 1815 re->skb = skb;
cd28ab6a
SH		 1816 le->ctrl |= EOP;
1817
9b289c33
MM		 1818 sky2->tx_prod = slot;
1819
97bda706
SH		 1820 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1821 netif_stop_queue(dev);
b19666d9 1822
290d4de5 1823 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1824
cd28ab6a 1825 return NETDEV_TX_OK;
454e6cb6
SH		 1826
1827mapping_unwind:
ee5f68fe 1828 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1829 re = sky2->tx_ring + i;
1830
6b84daca 1831 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1832 }
1833
454e6cb6
SH		 1834mapping_error:
1835 if (net_ratelimit())
1836 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1837 dev_kfree_skb(skb);
1838 return NETDEV_TX_OK;
cd28ab6a
SH		 1839}
1840
cd28ab6a 1841/*
793b883e
SH		 1842 * Free ring elements from starting at tx_cons until "done"
1843 *
481cea4a
SH		 1844 * NB:
1845 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1846 * buffers so make sure not to free skb to early.
481cea4a
SH		 1847 * 2. This may run in parallel start_xmit because the it only
1848 * looks at the tail of the queue of FIFO (tx_cons), not
1849 * the head (tx_prod)
cd28ab6a 1850 */
d11c13e7 1851static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1852{
d11c13e7 1853 struct net_device *dev = sky2->netdev;
291ea614 1854 unsigned idx;
cd28ab6a 1855
ee5f68fe 1856 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1857
291ea614 1858 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1859 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1860 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1861 struct sk_buff *skb = re->skb;
291ea614 1862
6b84daca 1863 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1864
6b84daca 1865 if (skb) {
6c35abae
JP		 1866 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1867 "tx done %u\n", idx);
3cf26753 1868
7138a0f5 1869 dev->stats.tx_packets++;
bd1c6869
SH		 1870 dev->stats.tx_bytes += skb->len;
1871
f6815077 1872 re->skb = NULL;
724b6942 1873 dev_kfree_skb_any(skb);
2bf56fe2 1874
ee5f68fe 1875 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1876 }
793b883e 1877 }
793b883e 1878
291ea614 1879 sky2->tx_cons = idx;
50432cb5 1880 smp_mb();
cd28ab6a
SH		 1881}
1882
264bb4fa 1883static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1884{
a510996b
MM		 1885 /* Disable Force Sync bit and Enable Alloc bit */
1886 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1887 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1888
1889 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1890 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1891 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1892
1893 /* Reset the PCI FIFO of the async Tx queue */
1894 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1895 BMU_RST_SET | BMU_FIFO_RST);
1896
1897 /* Reset the Tx prefetch units */
1898 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1899 PREF_UNIT_RST_SET);
1900
1901 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1902 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1903}
1904
f2b31cb3 1905static void sky2_hw_down(struct sky2_port *sky2)
cd28ab6a 1906{
cd28ab6a
SH		 1907 struct sky2_hw *hw = sky2->hw;
1908 unsigned port = sky2->port;
f2b31cb3 1909 u16 ctrl;
cd28ab6a 1910
d104acaf
SH		 1911 /* Force flow control off */
1912 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1913
cd28ab6a
SH		 1914 /* Stop transmitter */
1915 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1916 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1917
1918 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1919 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1920
1921 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1922 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1923 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1924
1925 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1926
1927 /* Workaround shared GMAC reset */
8e95a202
JP		 1928 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1929 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1930 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1931
cd28ab6a 1932 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1933
6c83504f
SH		 1934 /* Force any delayed status interrrupt and NAPI */
1935 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1936 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1937 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1938 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1939
a947a39d
MM		 1940 sky2_rx_stop(sky2);
1941
0da6d7b3 1942 spin_lock_bh(&sky2->phy_lock);
b96936da 1943 sky2_phy_power_down(hw, port);
0da6d7b3 1944 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1945
264bb4fa
MM		 1946 sky2_tx_reset(hw, port);
1947
481cea4a
SH		 1948 /* Free any pending frames stuck in HW queue */
1949 sky2_tx_complete(sky2, sky2->tx_prod);
f2b31cb3
MM		 1950}
1951
1952/* Network shutdown */
1953static int sky2_down(struct net_device *dev)
1954{
1955 struct sky2_port *sky2 = netdev_priv(dev);
8a0c9228 1956 struct sky2_hw *hw = sky2->hw;
f2b31cb3
MM		 1957
1958 /* Never really got started! */
1959 if (!sky2->tx_le)
1960 return 0;
1961
6c35abae 1962 netif_info(sky2, ifdown, dev, "disabling interface\n");
f2b31cb3 1963
8a0c9228
MM		 1964 /* Disable port IRQ */
1965 sky2_write32(hw, B0_IMSK,
1966 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
1967 sky2_read32(hw, B0_IMSK);
1968
1969 synchronize_irq(hw->pdev->irq);
1970 napi_synchronize(&hw->napi);
1971
f2b31cb3 1972 sky2_hw_down(sky2);
481cea4a 1973
90bbebb4 1974 sky2_free_buffers(sky2);
1b537565 1975
cd28ab6a
SH		 1976 return 0;
1977}
1978
1979static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1980{
ea76e635 1981 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1982 return SPEED_1000;
1983
05745c4a
SH		 1984 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1985 if (aux & PHY_M_PS_SPEED_100)
1986 return SPEED_100;
1987 else
1988 return SPEED_10;
1989 }
cd28ab6a
SH		 1990
1991 switch (aux & PHY_M_PS_SPEED_MSK) {
1992 case PHY_M_PS_SPEED_1000:
1993 return SPEED_1000;
1994 case PHY_M_PS_SPEED_100:
1995 return SPEED_100;
1996 default:
1997 return SPEED_10;
1998 }
1999}
2000
2001static void sky2_link_up(struct sky2_port *sky2)
2002{
2003 struct sky2_hw *hw = sky2->hw;
2004 unsigned port = sky2->port;
2005 u16 reg;
16ad91e1
SH		 2006 static const char *fc_name[] = {
2007 [FC_NONE] = "none",
2008 [FC_TX] = "tx",
2009 [FC_RX] = "rx",
2010 [FC_BOTH] = "both",
2011 };
cd28ab6a 2012
cd28ab6a 2013 /* enable Rx/Tx */
2eaba1a2 2014 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 2015 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2016 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 2017
2018 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2019
2020 netif_carrier_on(sky2->netdev);
cd28ab6a 2021
75e80683 2022 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 2023
cd28ab6a 2024 /* Turn on link LED */
793b883e 2025 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2026 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2027
6c35abae
JP		 2028 netif_info(sky2, link, sky2->netdev,
2029 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2030 sky2->speed,
2031 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2032 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2033}
2034
2035static void sky2_link_down(struct sky2_port *sky2)
2036{
2037 struct sky2_hw *hw = sky2->hw;
2038 unsigned port = sky2->port;
2039 u16 reg;
2040
2041 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2042
2043 reg = gma_read16(hw, port, GM_GP_CTRL);
2044 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2045 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2046
cd28ab6a 2047 netif_carrier_off(sky2->netdev);
cd28ab6a 2048
809aaaae 2049 /* Turn off link LED */
cd28ab6a
SH		 2050 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2051
6c35abae 2052 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2eaba1a2 2053
cd28ab6a
SH		 2054 sky2_phy_init(hw, port);
2055}
2056
16ad91e1
SH		 2057static enum flow_control sky2_flow(int rx, int tx)
2058{
2059 if (rx)
2060 return tx ? FC_BOTH : FC_RX;
2061 else
2062 return tx ? FC_TX : FC_NONE;
2063}
2064
793b883e
SH		 2065static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2066{
2067 struct sky2_hw *hw = sky2->hw;
2068 unsigned port = sky2->port;
da4c1ff4 2069 u16 advert, lpa;
793b883e 2070
da4c1ff4 2071 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2072 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e 2073 if (lpa & PHY_M_AN_RF) {
ada1db5c 2074 netdev_err(sky2->netdev, "remote fault\n");
793b883e
SH		 2075 return -1;
2076 }
2077
793b883e 2078 if (!(aux & PHY_M_PS_SPDUP_RES)) {
ada1db5c 2079 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
793b883e
SH		 2080 return -1;
2081 }
2082
793b883e 2083 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2084 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2085
da4c1ff4
SH		 2086 /* Since the pause result bits seem to in different positions on
2087 * different chips. look at registers.
2088 */
ea76e635 2089 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2090 /* Shift for bits in fiber PHY */
2091 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2092 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2093
2094 if (advert & ADVERTISE_1000XPAUSE)
2095 advert |= ADVERTISE_PAUSE_CAP;
2096 if (advert & ADVERTISE_1000XPSE_ASYM)
2097 advert |= ADVERTISE_PAUSE_ASYM;
2098 if (lpa & LPA_1000XPAUSE)
2099 lpa |= LPA_PAUSE_CAP;
2100 if (lpa & LPA_1000XPAUSE_ASYM)
2101 lpa |= LPA_PAUSE_ASYM;
2102 }
793b883e 2103
da4c1ff4
SH		 2104 sky2->flow_status = FC_NONE;
2105 if (advert & ADVERTISE_PAUSE_CAP) {
2106 if (lpa & LPA_PAUSE_CAP)
2107 sky2->flow_status = FC_BOTH;
2108 else if (advert & ADVERTISE_PAUSE_ASYM)
2109 sky2->flow_status = FC_RX;
2110 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2111 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2112 sky2->flow_status = FC_TX;
2113 }
793b883e 2114
8e95a202
JP		 2115 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2116 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2117 sky2->flow_status = FC_NONE;
2eaba1a2 2118
da4c1ff4 2119 if (sky2->flow_status & FC_TX)
793b883e
SH		 2120 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2121 else
2122 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2123
2124 return 0;
2125}
cd28ab6a 2126
e07b1aa8
SH		 2127/* Interrupt from PHY */
2128static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2129{
e07b1aa8
SH		 2130 struct net_device *dev = hw->dev[port];
2131 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2132 u16 istatus, phystat;
2133
ebc646f6
SH		 2134 if (!netif_running(dev))
2135 return;
2136
e07b1aa8
SH		 2137 spin_lock(&sky2->phy_lock);
2138 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2139 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2140
6c35abae
JP		 2141 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2142 istatus, phystat);
cd28ab6a 2143
0ea065e5 2144 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2145 if (sky2_autoneg_done(sky2, phystat) == 0)
2146 sky2_link_up(sky2);
2147 goto out;
2148 }
cd28ab6a 2149
793b883e
SH		 2150 if (istatus & PHY_M_IS_LSP_CHANGE)
2151 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2152
793b883e
SH		 2153 if (istatus & PHY_M_IS_DUP_CHANGE)
2154 sky2->duplex =
2155 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2156
793b883e
SH		 2157 if (istatus & PHY_M_IS_LST_CHANGE) {
2158 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2159 sky2_link_up(sky2);
793b883e
SH		 2160 else
2161 sky2_link_down(sky2);
cd28ab6a 2162 }
793b883e 2163out:
e07b1aa8 2164 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2165}
2166
0f5aac70
SH		 2167/* Special quick link interrupt (Yukon-2 Optima only) */
2168static void sky2_qlink_intr(struct sky2_hw *hw)
2169{
2170 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2171 u32 imask;
2172 u16 phy;
2173
2174 /* disable irq */
2175 imask = sky2_read32(hw, B0_IMSK);
2176 imask &= ~Y2_IS_PHY_QLNK;
2177 sky2_write32(hw, B0_IMSK, imask);
2178
2179 /* reset PHY Link Detect */
2180 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2181 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2182 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2183 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2184
2185 sky2_link_up(sky2);
2186}
2187
62335ab0 2188/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2189 * and tx queue is full (stopped).
2190 */
cd28ab6a
SH		 2191static void sky2_tx_timeout(struct net_device *dev)
2192{
2193 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2194 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2195
6c35abae 2196 netif_err(sky2, timer, dev, "tx timeout\n");
cd28ab6a 2197
ada1db5c
JP		 2198 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2199 sky2->tx_cons, sky2->tx_prod,
2200 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2201 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2202
81906791
SH		 2203 /* can't restart safely under softirq */
2204 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2205}
2206
2207static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2208{
6b1a3aef
SH		 2209 struct sky2_port *sky2 = netdev_priv(dev);
2210 struct sky2_hw *hw = sky2->hw;
b628ed98 2211 unsigned port = sky2->port;
6b1a3aef
SH		 2212 int err;
2213 u16 ctl, mode;
e07b1aa8 2214 u32 imask;
cd28ab6a 2215
44dde56d 2216 /* MTU size outside the spec */
cd28ab6a
SH		 2217 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2218 return -EINVAL;
2219
44dde56d 2220 /* MTU > 1500 on yukon FE and FE+ not allowed */
05745c4a
SH		 2221 if (new_mtu > ETH_DATA_LEN &&
2222 (hw->chip_id == CHIP_ID_YUKON_FE ||
2223 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2224 return -EINVAL;
2225
44dde56d 2226 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2227 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
2228 dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
2229
6b1a3aef
SH		 2230 if (!netif_running(dev)) {
2231 dev->mtu = new_mtu;
2232 return 0;
2233 }
2234
e07b1aa8 2235 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2236 sky2_write32(hw, B0_IMSK, 0);
2237
018d1c66
SH		 2238 dev->trans_start = jiffies; /* prevent tx timeout */
2239 netif_stop_queue(dev);
bea3348e 2240 napi_disable(&hw->napi);
018d1c66 2241
e07b1aa8
SH		 2242 synchronize_irq(hw->pdev->irq);
2243
39dbd958 2244 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2245 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2246
2247 ctl = gma_read16(hw, port, GM_GP_CTRL);
2248 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2249 sky2_rx_stop(sky2);
2250 sky2_rx_clean(sky2);
cd28ab6a
SH		 2251
2252 dev->mtu = new_mtu;
14d0263f 2253
6b1a3aef
SH		 2254 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2255 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2256
2257 if (dev->mtu > ETH_DATA_LEN)
2258 mode |= GM_SMOD_JUMBO_ENA;
2259
b628ed98 2260 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2261
b628ed98 2262 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2263
200ac492
MM		 2264 err = sky2_alloc_rx_skbs(sky2);
2265 if (!err)
2266 sky2_rx_start(sky2);
2267 else
2268 sky2_rx_clean(sky2);
e07b1aa8 2269 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2270
d1d08d12 2271 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2272 napi_enable(&hw->napi);
2273
1b537565
SH		 2274 if (err)
2275 dev_close(dev);
2276 else {
b628ed98 2277 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2278
1b537565
SH		 2279 netif_wake_queue(dev);
2280 }
2281
cd28ab6a
SH		 2282 return err;
2283}
2284
14d0263f
SH		 2285/* For small just reuse existing skb for next receive */
2286static struct sk_buff *receive_copy(struct sky2_port *sky2,
2287 const struct rx_ring_info *re,
2288 unsigned length)
2289{
2290 struct sk_buff *skb;
2291
89d71a66 2292 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2293 if (likely(skb)) {
14d0263f
SH		 2294 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2295 length, PCI_DMA_FROMDEVICE);
d626f62b 2296 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2297 skb->ip_summed = re->skb->ip_summed;
2298 skb->csum = re->skb->csum;
2299 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2300 length, PCI_DMA_FROMDEVICE);
2301 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2302 skb_put(skb, length);
14d0263f
SH		 2303 }
2304 return skb;
2305}
2306
2307/* Adjust length of skb with fragments to match received data */
2308static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2309 unsigned int length)
2310{
2311 int i, num_frags;
2312 unsigned int size;
2313
2314 /* put header into skb */
2315 size = min(length, hdr_space);
2316 skb->tail += size;
2317 skb->len += size;
2318 length -= size;
2319
2320 num_frags = skb_shinfo(skb)->nr_frags;
2321 for (i = 0; i < num_frags; i++) {
2322 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2323
2324 if (length == 0) {
2325 /* don't need this page */
2326 __free_page(frag->page);
2327 --skb_shinfo(skb)->nr_frags;
2328 } else {
2329 size = min(length, (unsigned) PAGE_SIZE);
2330
2331 frag->size = size;
2332 skb->data_len += size;
2333 skb->truesize += size;
2334 skb->len += size;
2335 length -= size;
2336 }
2337 }
2338}
2339
2340/* Normal packet - take skb from ring element and put in a new one */
2341static struct sk_buff *receive_new(struct sky2_port *sky2,
2342 struct rx_ring_info *re,
2343 unsigned int length)
2344{
3fbd9187 2345 struct sk_buff *skb;
2346 struct rx_ring_info nre;
14d0263f
SH		 2347 unsigned hdr_space = sky2->rx_data_size;
2348
3fbd9187 2349 nre.skb = sky2_rx_alloc(sky2);
2350 if (unlikely(!nre.skb))
2351 goto nobuf;
2352
2353 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2354 goto nomap;
14d0263f
SH		 2355
2356 skb = re->skb;
2357 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2358 prefetch(skb->data);
3fbd9187 2359 *re = nre;
14d0263f
SH		 2360
2361 if (skb_shinfo(skb)->nr_frags)
2362 skb_put_frags(skb, hdr_space, length);
2363 else
489b10c1 2364 skb_put(skb, length);
14d0263f 2365 return skb;
3fbd9187 2366
2367nomap:
2368 dev_kfree_skb(nre.skb);
2369nobuf:
2370 return NULL;
14d0263f
SH		 2371}
2372
cd28ab6a
SH		 2373/*
2374 * Receive one packet.
d571b694 2375 * For larger packets, get new buffer.
cd28ab6a 2376 */
497d7c86 2377static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2378 u16 length, u32 status)
2379{
497d7c86 2380 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2381 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2382 struct sk_buff *skb = NULL;
d6532232
SH		 2383 u16 count = (status & GMR_FS_LEN) >> 16;
2384
2385#ifdef SKY2_VLAN_TAG_USED
2386 /* Account for vlan tag */
2387 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2388 count -= VLAN_HLEN;
2389#endif
cd28ab6a 2390
6c35abae
JP		 2391 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2392 "rx slot %u status 0x%x len %d\n",
2393 sky2->rx_next, status, length);
cd28ab6a 2394
793b883e 2395 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2396 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2397
3b12e014
SH		 2398 /* This chip has hardware problems that generates bogus status.
2399 * So do only marginal checking and expect higher level protocols
2400 * to handle crap frames.
2401 */
2402 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2403 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2404 length != count)
2405 goto okay;
2406
42eeea01 2407 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2408 goto error;
2409
42eeea01
SH		 2410 if (!(status & GMR_FS_RX_OK))
2411 goto resubmit;
2412
d6532232
SH		 2413 /* if length reported by DMA does not match PHY, packet was truncated */
2414 if (length != count)
3b12e014 2415 goto len_error;
71749531 2416
3b12e014 2417okay:
14d0263f
SH		 2418 if (length < copybreak)
2419 skb = receive_copy(sky2, re, length);
2420 else
2421 skb = receive_new(sky2, re, length);
90c30335
SH		 2422
2423 dev->stats.rx_dropped += (skb == NULL);
2424
793b883e 2425resubmit:
14d0263f 2426 sky2_rx_submit(sky2, re);
79e57d32 2427
cd28ab6a
SH		 2428 return skb;
2429
3b12e014 2430len_error:
71749531
SH		 2431 /* Truncation of overlength packets
2432 causes PHY length to not match MAC length */
7138a0f5 2433 ++dev->stats.rx_length_errors;
6c35abae
JP		 2434 if (net_ratelimit())
2435 netif_info(sky2, rx_err, dev,
2436 "rx length error: status %#x length %d\n",
2437 status, length);
d6532232 2438 goto resubmit;
71749531 2439
cd28ab6a 2440error:
7138a0f5 2441 ++dev->stats.rx_errors;
b6d77734 2442 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2443 dev->stats.rx_over_errors++;
b6d77734
SH		 2444 goto resubmit;
2445 }
6e15b712 2446
6c35abae
JP		 2447 if (net_ratelimit())
2448 netif_info(sky2, rx_err, dev,
2449 "rx error, status 0x%x length %d\n", status, length);
793b883e
SH		 2450
2451 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2452 dev->stats.rx_length_errors++;
cd28ab6a 2453 if (status & GMR_FS_FRAGMENT)
7138a0f5 2454 dev->stats.rx_frame_errors++;
cd28ab6a 2455 if (status & GMR_FS_CRC_ERR)
7138a0f5 2456 dev->stats.rx_crc_errors++;
79e57d32 2457
793b883e 2458 goto resubmit;
cd28ab6a
SH		 2459}
2460
e07b1aa8
SH		 2461/* Transmit complete */
2462static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2463{
e07b1aa8 2464 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2465
8a0c9228 2466 if (netif_running(dev)) {
e07b1aa8 2467 sky2_tx_complete(sky2, last);
8a0c9228
MM		 2468
2469 /* Wake unless it's detached, and called e.g. from sky2_down() */
2470 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2471 netif_wake_queue(dev);
2472 }
cd28ab6a
SH		 2473}
2474
37e5a243
SH		 2475static inline void sky2_skb_rx(const struct sky2_port *sky2,
2476 u32 status, struct sk_buff *skb)
2477{
2478#ifdef SKY2_VLAN_TAG_USED
2479 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2480 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2481 if (skb->ip_summed == CHECKSUM_NONE)
2482 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2483 else
2484 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2485 vlan_tag, skb);
2486 return;
2487 }
2488#endif
2489 if (skb->ip_summed == CHECKSUM_NONE)
2490 netif_receive_skb(skb);
2491 else
2492 napi_gro_receive(&sky2->hw->napi, skb);
2493}
2494
bf15fe99
SH		 2495static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2496 unsigned packets, unsigned bytes)
2497{
2498 if (packets) {
2499 struct net_device *dev = hw->dev[port];
2500
2501 dev->stats.rx_packets += packets;
2502 dev->stats.rx_bytes += bytes;
2503 dev->last_rx = jiffies;
2504 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2505 }
2506}
2507
375c5688 2508static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2509{
2510 /* If this happens then driver assuming wrong format for chip type */
2511 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2512
2513 /* Both checksum counters are programmed to start at
2514 * the same offset, so unless there is a problem they
2515 * should match. This failure is an early indication that
2516 * hardware receive checksumming won't work.
2517 */
2518 if (likely((u16)(status >> 16) == (u16)status)) {
2519 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2520 skb->ip_summed = CHECKSUM_COMPLETE;
2521 skb->csum = le16_to_cpu(status);
2522 } else {
2523 dev_notice(&sky2->hw->pdev->dev,
2524 "%s: receive checksum problem (status = %#x)\n",
2525 sky2->netdev->name, status);
2526
2527 /* Disable checksum offload */
2528 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2529 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2530 BMU_DIS_RX_CHKSUM);
2531 }
2532}
2533
e07b1aa8 2534/* Process status response ring */
26691830 2535static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2536{
e07b1aa8 2537 int work_done = 0;
bf15fe99
SH		 2538 unsigned int total_bytes[2] = { 0 };
2539 unsigned int total_packets[2] = { 0 };
a8fd6266 2540
af2a58ac 2541 rmb();
26691830 2542 do {
55c9dd35 2543 struct sky2_port *sky2;
13210ce5 2544 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2545 unsigned port;
13210ce5 2546 struct net_device *dev;
cd28ab6a 2547 struct sk_buff *skb;
cd28ab6a
SH		 2548 u32 status;
2549 u16 length;
ab5adecb
SH		 2550 u8 opcode = le->opcode;
2551
2552 if (!(opcode & HW_OWNER))
2553 break;
cd28ab6a 2554
cb5d9547 2555 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2556
ab5adecb 2557 port = le->css & CSS_LINK_BIT;
69161611 2558 dev = hw->dev[port];
13210ce5 2559 sky2 = netdev_priv(dev);
f65b138c
SH		 2560 length = le16_to_cpu(le->length);
2561 status = le32_to_cpu(le->status);
cd28ab6a 2562
ab5adecb
SH		 2563 le->opcode = 0;
2564 switch (opcode & ~HW_OWNER) {
cd28ab6a 2565 case OP_RXSTAT:
bf15fe99
SH		 2566 total_packets[port]++;
2567 total_bytes[port] += length;
90c30335 2568
497d7c86 2569 skb = sky2_receive(dev, length, status);
90c30335 2570 if (!skb)
55c9dd35 2571 break;
13210ce5 2572
69161611 2573 /* This chip reports checksum status differently */
05745c4a 2574 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2575 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2576 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2577 (le->css & CSS_TCPUDPCSOK))
2578 skb->ip_summed = CHECKSUM_UNNECESSARY;
2579 else
2580 skb->ip_summed = CHECKSUM_NONE;
2581 }
2582
13210ce5 2583 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2584
37e5a243 2585 sky2_skb_rx(sky2, status, skb);
13210ce5 2586
22e11703 2587 /* Stop after net poll weight */
13210ce5
SH		 2588 if (++work_done >= to_do)
2589 goto exit_loop;
cd28ab6a
SH		 2590 break;
2591
d1f13708
SH		 2592#ifdef SKY2_VLAN_TAG_USED
2593 case OP_RXVLAN:
2594 sky2->rx_tag = length;
2595 break;
2596
2597 case OP_RXCHKSVLAN:
2598 sky2->rx_tag = length;
2599 /* fall through */
2600#endif
cd28ab6a 2601 case OP_RXCHKS:
375c5688 2602 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2603 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2604 break;
2605
2606 case OP_TXINDEXLE:
13b97b74 2607 /* TX index reports status for both ports */
f55925d7 2608 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2609 if (hw->dev[1])
2610 sky2_tx_done(hw->dev[1],
2611 ((status >> 24) & 0xff)
2612 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2613 break;
2614
cd28ab6a
SH		 2615 default:
2616 if (net_ratelimit())
ada1db5c 2617 pr_warning("unknown status opcode 0x%x\n", opcode);
cd28ab6a 2618 }
26691830 2619 } while (hw->st_idx != idx);
cd28ab6a 2620
fe2a24df
SH		 2621 /* Fully processed status ring so clear irq */
2622 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2623
13210ce5 2624exit_loop:
bf15fe99
SH		 2625 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2626 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2627
e07b1aa8 2628 return work_done;
cd28ab6a
SH		 2629}
2630
2631static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2632{
2633 struct net_device *dev = hw->dev[port];
2634
3be92a70 2635 if (net_ratelimit())
ada1db5c 2636 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
cd28ab6a
SH		 2637
2638 if (status & Y2_IS_PAR_RD1) {
3be92a70 2639 if (net_ratelimit())
ada1db5c 2640 netdev_err(dev, "ram data read parity error\n");
cd28ab6a
SH		 2641 /* Clear IRQ */
2642 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2643 }
2644
2645 if (status & Y2_IS_PAR_WR1) {
3be92a70 2646 if (net_ratelimit())
ada1db5c 2647 netdev_err(dev, "ram data write parity error\n");
cd28ab6a
SH		 2648
2649 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2650 }
2651
2652 if (status & Y2_IS_PAR_MAC1) {
3be92a70 2653 if (net_ratelimit())
ada1db5c 2654 netdev_err(dev, "MAC parity error\n");
cd28ab6a
SH		 2655 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2656 }
2657
2658 if (status & Y2_IS_PAR_RX1) {
3be92a70 2659 if (net_ratelimit())
ada1db5c 2660 netdev_err(dev, "RX parity error\n");
cd28ab6a
SH		 2661 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2662 }
2663
2664 if (status & Y2_IS_TCP_TXA1) {
3be92a70 2665 if (net_ratelimit())
ada1db5c 2666 netdev_err(dev, "TCP segmentation error\n");
cd28ab6a
SH		 2667 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2668 }
2669}
2670
2671static void sky2_hw_intr(struct sky2_hw *hw)
2672{
555382cb 2673 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2674 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2675 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2676
2677 status &= hwmsk;
cd28ab6a 2678
793b883e 2679 if (status & Y2_IS_TIST_OV)
cd28ab6a 2680 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2681
2682 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2683 u16 pci_err;
2684
a40ccc68 2685 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2686 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2687 if (net_ratelimit())
555382cb 2688 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2689 pci_err);
cd28ab6a 2690
b32f40c4 2691 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2692 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2693 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2694 }
2695
2696 if (status & Y2_IS_PCI_EXP) {
d571b694 2697 /* PCI-Express uncorrectable Error occurred */
555382cb 2698 u32 err;
cd28ab6a 2699
a40ccc68 2700 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2701 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2702 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2703 0xfffffffful);
3be92a70 2704 if (net_ratelimit())
555382cb 2705 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2706
7782c8c4 2707 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2708 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2709 }
2710
2711 if (status & Y2_HWE_L1_MASK)
2712 sky2_hw_error(hw, 0, status);
2713 status >>= 8;
2714 if (status & Y2_HWE_L1_MASK)
2715 sky2_hw_error(hw, 1, status);
2716}
2717
2718static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2719{
2720 struct net_device *dev = hw->dev[port];
2721 struct sky2_port *sky2 = netdev_priv(dev);
2722 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2723
6c35abae 2724 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
cd28ab6a 2725
a3caeada
SH		 2726 if (status & GM_IS_RX_CO_OV)
2727 gma_read16(hw, port, GM_RX_IRQ_SRC);
2728
2729 if (status & GM_IS_TX_CO_OV)
2730 gma_read16(hw, port, GM_TX_IRQ_SRC);
2731
cd28ab6a 2732 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2733 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2734 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2735 }
2736
2737 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2738 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2739 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2740 }
cd28ab6a
SH		 2741}
2742
40b01727 2743/* This should never happen it is a bug. */
c119731d 2744static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2745{
2746 struct net_device *dev = hw->dev[port];
c119731d 2747 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2748
ada1db5c 2749 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
c119731d
SH		 2750 dev->name, (unsigned) q, (unsigned) idx,
2751 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2752
40b01727 2753 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2754}
cd28ab6a 2755
75e80683
SH		 2756static int sky2_rx_hung(struct net_device *dev)
2757{
2758 struct sky2_port *sky2 = netdev_priv(dev);
2759 struct sky2_hw *hw = sky2->hw;
2760 unsigned port = sky2->port;
2761 unsigned rxq = rxqaddr[port];
2762 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2763 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2764 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2765 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2766
2767 /* If idle and MAC or PCI is stuck */
2768 if (sky2->check.last == dev->last_rx &&
2769 ((mac_rp == sky2->check.mac_rp &&
2770 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2771 /* Check if the PCI RX hang */
2772 (fifo_rp == sky2->check.fifo_rp &&
2773 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
ada1db5c
JP		 2774 netdev_printk(KERN_DEBUG, dev,
2775 "hung mac %d:%d fifo %d (%d:%d)\n",
2776 mac_lev, mac_rp, fifo_lev,
2777 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
75e80683
SH		 2778 return 1;
2779 } else {
2780 sky2->check.last = dev->last_rx;
2781 sky2->check.mac_rp = mac_rp;
2782 sky2->check.mac_lev = mac_lev;
2783 sky2->check.fifo_rp = fifo_rp;
2784 sky2->check.fifo_lev = fifo_lev;
2785 return 0;
2786 }
2787}
2788
32c2c300 2789static void sky2_watchdog(unsigned long arg)
d27ed387 2790{
01bd7564 2791 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2792
75e80683 2793 /* Check for lost IRQ once a second */
32c2c300 2794 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2795 napi_schedule(&hw->napi);
75e80683
SH		 2796 } else {
2797 int i, active = 0;
2798
2799 for (i = 0; i < hw->ports; i++) {
bea3348e 2800 struct net_device *dev = hw->dev[i];
75e80683
SH		 2801 if (!netif_running(dev))
2802 continue;
2803 ++active;
2804
2805 /* For chips with Rx FIFO, check if stuck */
39dbd958 2806 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683 2807 sky2_rx_hung(dev)) {
ada1db5c 2808 netdev_info(dev, "receiver hang detected\n");
75e80683
SH		 2809 schedule_work(&hw->restart_work);
2810 return;
2811 }
2812 }
2813
2814 if (active == 0)
2815 return;
32c2c300 2816 }
01bd7564 2817
75e80683 2818 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2819}
2820
40b01727
SH		 2821/* Hardware/software error handling */
2822static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2823{
40b01727
SH		 2824 if (net_ratelimit())
2825 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2826
1e5f1283
SH		 2827 if (status & Y2_IS_HW_ERR)
2828 sky2_hw_intr(hw);
d257924e 2829
1e5f1283
SH		 2830 if (status & Y2_IS_IRQ_MAC1)
2831 sky2_mac_intr(hw, 0);
cd28ab6a 2832
1e5f1283
SH		 2833 if (status & Y2_IS_IRQ_MAC2)
2834 sky2_mac_intr(hw, 1);
cd28ab6a 2835
1e5f1283 2836 if (status & Y2_IS_CHK_RX1)
c119731d 2837 sky2_le_error(hw, 0, Q_R1);
d257924e 2838
1e5f1283 2839 if (status & Y2_IS_CHK_RX2)
c119731d 2840 sky2_le_error(hw, 1, Q_R2);
d257924e 2841
1e5f1283 2842 if (status & Y2_IS_CHK_TXA1)
c119731d 2843 sky2_le_error(hw, 0, Q_XA1);
d257924e 2844
1e5f1283 2845 if (status & Y2_IS_CHK_TXA2)
c119731d 2846 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2847}
2848
bea3348e 2849static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2850{
bea3348e 2851 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2852 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2853 int work_done = 0;
26691830 2854 u16 idx;
40b01727
SH		 2855
2856 if (unlikely(status & Y2_IS_ERROR))
2857 sky2_err_intr(hw, status);
2858
2859 if (status & Y2_IS_IRQ_PHY1)
2860 sky2_phy_intr(hw, 0);
2861
2862 if (status & Y2_IS_IRQ_PHY2)
2863 sky2_phy_intr(hw, 1);
cd28ab6a 2864
0f5aac70
SH		 2865 if (status & Y2_IS_PHY_QLNK)
2866 sky2_qlink_intr(hw);
2867
26691830
SH		 2868 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2869 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2870
2871 if (work_done >= work_limit)
26691830
SH		 2872 goto done;
2873 }
6f535763 2874
26691830
SH		 2875 napi_complete(napi);
2876 sky2_read32(hw, B0_Y2_SP_LISR);
2877done:
6f535763 2878
bea3348e 2879 return work_done;
e07b1aa8
SH		 2880}
2881
7d12e780 2882static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2883{
2884 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2885 u32 status;
2886
2887 /* Reading this mask interrupts as side effect */
2888 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2889 if (status == 0 || status == ~0)
2890 return IRQ_NONE;
793b883e 2891
e07b1aa8 2892 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2893
2894 napi_schedule(&hw->napi);
793b883e 2895
cd28ab6a
SH		 2896 return IRQ_HANDLED;
2897}
2898
2899#ifdef CONFIG_NET_POLL_CONTROLLER
2900static void sky2_netpoll(struct net_device *dev)
2901{
2902 struct sky2_port *sky2 = netdev_priv(dev);
2903
bea3348e 2904 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2905}
2906#endif
2907
2908/* Chip internal frequency for clock calculations */
05745c4a 2909static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2910{
793b883e 2911 switch (hw->chip_id) {
cd28ab6a 2912 case CHIP_ID_YUKON_EC:
5a5b1ea0 2913 case CHIP_ID_YUKON_EC_U:
93745494 2914 case CHIP_ID_YUKON_EX:
ed4d4161 2915 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2916 case CHIP_ID_YUKON_UL_2:
0f5aac70 2917 case CHIP_ID_YUKON_OPT:
05745c4a
SH		 2918 return 125;
2919
cd28ab6a 2920 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2921 return 100;
2922
2923 case CHIP_ID_YUKON_FE_P:
2924 return 50;
2925
2926 case CHIP_ID_YUKON_XL:
2927 return 156;
2928
2929 default:
2930 BUG();
cd28ab6a
SH		 2931 }
2932}
2933
fb17358f 2934static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2935{
fb17358f 2936 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2937}
2938
fb17358f 2939static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2940{
fb17358f 2941 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2942}
2943
fb17358f 2944
e3173832 2945static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2946{
b89165f2 2947 u8 t8;
cd28ab6a 2948
167f53d0 2949 /* Enable all clocks and check for bad PCI access */
b32f40c4 2950 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2951
cd28ab6a 2952 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2953
cd28ab6a 2954 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2955 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2956
2957 switch(hw->chip_id) {
2958 case CHIP_ID_YUKON_XL:
39dbd958 2959 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2960 break;
2961
2962 case CHIP_ID_YUKON_EC_U:
2963 hw->flags = SKY2_HW_GIGABIT
2964 | SKY2_HW_NEWER_PHY
2965 | SKY2_HW_ADV_POWER_CTL;
2966 break;
2967
2968 case CHIP_ID_YUKON_EX:
2969 hw->flags = SKY2_HW_GIGABIT
2970 | SKY2_HW_NEWER_PHY
2971 | SKY2_HW_NEW_LE
2972 | SKY2_HW_ADV_POWER_CTL;
2973
2974 /* New transmit checksum */
2975 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2976 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2977 break;
2978
2979 case CHIP_ID_YUKON_EC:
2980 /* This rev is really old, and requires untested workarounds */
2981 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2982 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2983 return -EOPNOTSUPP;
2984 }
39dbd958 2985 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2986 break;
2987
2988 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2989 break;
2990
05745c4a
SH		 2991 case CHIP_ID_YUKON_FE_P:
2992 hw->flags = SKY2_HW_NEWER_PHY
2993 | SKY2_HW_NEW_LE
2994 | SKY2_HW_AUTO_TX_SUM
2995 | SKY2_HW_ADV_POWER_CTL;
2996 break;
ed4d4161
SH		 2997
2998 case CHIP_ID_YUKON_SUPR:
2999 hw->flags = SKY2_HW_GIGABIT
3000 | SKY2_HW_NEWER_PHY
3001 | SKY2_HW_NEW_LE
3002 | SKY2_HW_AUTO_TX_SUM
3003 | SKY2_HW_ADV_POWER_CTL;
3004 break;
3005
0ce8b98d 3006 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 3007 hw->flags = SKY2_HW_GIGABIT
3008 | SKY2_HW_ADV_POWER_CTL;
3009 break;
3010
0f5aac70 3011 case CHIP_ID_YUKON_OPT:
0ce8b98d 3012 hw->flags = SKY2_HW_GIGABIT
b338682d 3013 | SKY2_HW_NEW_LE
0ce8b98d
SH		 3014 | SKY2_HW_ADV_POWER_CTL;
3015 break;
3016
ea76e635 3017 default:
b02a9258
SH		 3018 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3019 hw->chip_id);
cd28ab6a
SH		 3020 return -EOPNOTSUPP;
3021 }
3022
ea76e635
SH		 3023 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3024 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3025 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3026
e3173832
SH		 3027 hw->ports = 1;
3028 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3029 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3030 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3031 ++hw->ports;
3032 }
3033
74a61ebf
MM		 3034 if (sky2_read8(hw, B2_E_0))
3035 hw->flags |= SKY2_HW_RAM_BUFFER;
3036
e3173832
SH		 3037 return 0;
3038}
3039
3040static void sky2_reset(struct sky2_hw *hw)
3041{
555382cb 3042 struct pci_dev *pdev = hw->pdev;
e3173832 3043 u16 status;
555382cb
SH		 3044 int i, cap;
3045 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3046
cd28ab6a 3047 /* disable ASF */
acd12dde 3048 if (hw->chip_id == CHIP_ID_YUKON_EX
3049 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3050 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3051 status = sky2_read16(hw, HCU_CCSR);
3052 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3053 HCU_CCSR_UC_STATE_MSK);
acd12dde 3054 /*
3055 * CPU clock divider shouldn't be used because
3056 * - ASF firmware may malfunction
3057 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3058 */
3059 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3060 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3061 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3062 } else
3063 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3064 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3065
3066 /* do a SW reset */
3067 sky2_write8(hw, B0_CTST, CS_RST_SET);
3068 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3069
ac93a394
SH		 3070 /* allow writes to PCI config */
3071 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3072
cd28ab6a 3073 /* clear PCI errors, if any */
b32f40c4 3074 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3075 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3076 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3077
3078 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3079
555382cb
SH		 3080 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3081 if (cap) {
7782c8c4
SH		 3082 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3083 0xfffffffful);
555382cb
SH		 3084
3085 /* If error bit is stuck on ignore it */
3086 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3087 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3088 else
555382cb
SH		 3089 hwe_mask |= Y2_IS_PCI_EXP;
3090 }
cd28ab6a 3091
ae306cca 3092 sky2_power_on(hw);
a40ccc68 3093 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3094
3095 for (i = 0; i < hw->ports; i++) {
3096 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3097 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3098
ed4d4161
SH		 3099 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3100 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3101 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3102 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3103 | GMC_BYP_RETR_ON);
877c8570
SH		 3104
3105 }
3106
3107 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3108 /* enable MACSec clock gating */
3109 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3110 }
3111
0f5aac70
SH		 3112 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3113 u16 reg;
3114 u32 msk;
3115
3116 if (hw->chip_rev == 0) {
3117 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3118 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3119
3120 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3121 reg = 10;
3122 } else {
3123 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3124 reg = 3;
3125 }
3126
3127 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3128
3129 /* reset PHY Link Detect */
a40ccc68 3130 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3131 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3132 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3133 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3134
3135
3136 /* enable PHY Quick Link */
3137 msk = sky2_read32(hw, B0_IMSK);
3138 msk |= Y2_IS_PHY_QLNK;
3139 sky2_write32(hw, B0_IMSK, msk);
3140
3141 /* check if PSMv2 was running before */
3142 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3143 if (reg & PCI_EXP_LNKCTL_ASPMC) {
8b055431 3144 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
0f5aac70
SH		 3145 /* restore the PCIe Link Control register */
3146 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3147 }
a40ccc68 3148 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3149
3150 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3151 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3152 }
3153
793b883e
SH		 3154 /* Clear I2C IRQ noise */
3155 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3156
3157 /* turn off hardware timer (unused) */
3158 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3159 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3160
69634ee7
SH		 3161 /* Turn off descriptor polling */
3162 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3163
3164 /* Turn off receive timestamp */
3165 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3166 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3167
3168 /* enable the Tx Arbiters */
3169 for (i = 0; i < hw->ports; i++)
3170 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3171
3172 /* Initialize ram interface */
3173 for (i = 0; i < hw->ports; i++) {
793b883e 3174 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3175
3176 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3177 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3178 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3179 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3180 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3181 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3182 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3183 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3184 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3185 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3186 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3187 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3188 }
3189
555382cb 3190 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3191
cd28ab6a 3192 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3193 sky2_gmac_reset(hw, i);
cd28ab6a 3194
cd28ab6a
SH		 3195 memset(hw->st_le, 0, STATUS_LE_BYTES);
3196 hw->st_idx = 0;
3197
3198 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3199 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3200
3201 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3202 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3203
3204 /* Set the list last index */
793b883e 3205 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3206
290d4de5
SH		 3207 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3208 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3209
290d4de5
SH		 3210 /* set Status-FIFO ISR watermark */
3211 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3212 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3213 else
3214 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3215
290d4de5 3216 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3217 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3218 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3219
793b883e 3220 /* enable status unit */
cd28ab6a
SH		 3221 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3222
3223 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3224 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3225 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3226}
3227
af18d8b8
SH		 3228/* Take device down (offline).
3229 * Equivalent to doing dev_stop() but this does not
3230 * inform upper layers of the transistion.
3231 */
3232static void sky2_detach(struct net_device *dev)
3233{
3234 if (netif_running(dev)) {
c36531b9 3235 netif_tx_lock(dev);
af18d8b8 3236 netif_device_detach(dev); /* stop txq */
c36531b9 3237 netif_tx_unlock(dev);
af18d8b8
SH		 3238 sky2_down(dev);
3239 }
3240}
3241
3242/* Bring device back after doing sky2_detach */
3243static int sky2_reattach(struct net_device *dev)
3244{
3245 int err = 0;
3246
3247 if (netif_running(dev)) {
3248 err = sky2_up(dev);
3249 if (err) {
ada1db5c 3250 netdev_info(dev, "could not restart %d\n", err);
af18d8b8
SH		 3251 dev_close(dev);
3252 } else {
3253 netif_device_attach(dev);
3254 sky2_set_multicast(dev);
3255 }
3256 }
3257
3258 return err;
3259}
3260
81906791
SH		 3261static void sky2_restart(struct work_struct *work)
3262{
3263 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
8a0c9228 3264 u32 imask;
af18d8b8 3265 int i;
81906791 3266
81906791 3267 rtnl_lock();
81906791 3268
8cfcbe99 3269 napi_disable(&hw->napi);
8a0c9228
MM		 3270 synchronize_irq(hw->pdev->irq);
3271 imask = sky2_read32(hw, B0_IMSK);
8cfcbe99 3272 sky2_write32(hw, B0_IMSK, 0);
8a0c9228
MM		 3273
3274 for (i = 0; i < hw->ports; i++) {
3275 struct net_device *dev = hw->dev[i];
3276 struct sky2_port *sky2 = netdev_priv(dev);
3277
3278 if (!netif_running(dev))
3279 continue;
3280
3281 netif_carrier_off(dev);
3282 netif_tx_disable(dev);
3283 sky2_hw_down(sky2);
3284 }
3285
81906791 3286 sky2_reset(hw);
81906791 3287
8a0c9228
MM		 3288 for (i = 0; i < hw->ports; i++) {
3289 struct net_device *dev = hw->dev[i];
3290 struct sky2_port *sky2 = netdev_priv(dev);
3291
3292 if (!netif_running(dev))
3293 continue;
3294
3295 sky2_hw_up(sky2);
3296 netif_wake_queue(dev);
3297 }
3298
3299 sky2_write32(hw, B0_IMSK, imask);
3300 sky2_read32(hw, B0_IMSK);
3301
3302 sky2_read32(hw, B0_Y2_SP_LISR);
3303 napi_enable(&hw->napi);
81906791 3304
81906791
SH		 3305 rtnl_unlock();
3306}
3307
e3173832
SH		 3308static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3309{
3310 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3311}
3312
3313static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3314{
3315 const struct sky2_port *sky2 = netdev_priv(dev);
3316
3317 wol->supported = sky2_wol_supported(sky2->hw);
3318 wol->wolopts = sky2->wol;
3319}
3320
3321static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3322{
3323 struct sky2_port *sky2 = netdev_priv(dev);
3324 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3325
8e95a202
JP		 3326 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3327 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3328 return -EOPNOTSUPP;
3329
3330 sky2->wol = wol->wolopts;
cd28ab6a
SH		 3331 return 0;
3332}
3333
28bd181a 3334static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3335{
b89165f2
SH		 3336 if (sky2_is_copper(hw)) {
3337 u32 modes = SUPPORTED_10baseT_Half
3338 | SUPPORTED_10baseT_Full
3339 | SUPPORTED_100baseT_Half
3340 | SUPPORTED_100baseT_Full
3341 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3342
ea76e635 3343 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3344 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3345 | SUPPORTED_1000baseT_Full;
3346 return modes;
cd28ab6a 3347 } else
b89165f2
SH		 3348 return SUPPORTED_1000baseT_Half
3349 | SUPPORTED_1000baseT_Full
3350 | SUPPORTED_Autoneg
3351 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3352}
3353
793b883e 3354static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3355{
3356 struct sky2_port *sky2 = netdev_priv(dev);
3357 struct sky2_hw *hw = sky2->hw;
3358
3359 ecmd->transceiver = XCVR_INTERNAL;
3360 ecmd->supported = sky2_supported_modes(hw);
3361 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3362 if (sky2_is_copper(hw)) {
cd28ab6a 3363 ecmd->port = PORT_TP;
b89165f2
SH		 3364 ecmd->speed = sky2->speed;
3365 } else {
3366 ecmd->speed = SPEED_1000;
cd28ab6a 3367 ecmd->port = PORT_FIBRE;
b89165f2 3368 }
cd28ab6a
SH		 3369
3370 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3371 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3372 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3373 ecmd->duplex = sky2->duplex;
3374 return 0;
3375}
3376
3377static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3378{
3379 struct sky2_port *sky2 = netdev_priv(dev);
3380 const struct sky2_hw *hw = sky2->hw;
3381 u32 supported = sky2_supported_modes(hw);
3382
3383 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3384 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3385 ecmd->advertising = supported;
3386 sky2->duplex = -1;
3387 sky2->speed = -1;
3388 } else {
3389 u32 setting;
3390
793b883e 3391 switch (ecmd->speed) {
cd28ab6a
SH		 3392 case SPEED_1000:
3393 if (ecmd->duplex == DUPLEX_FULL)
3394 setting = SUPPORTED_1000baseT_Full;
3395 else if (ecmd->duplex == DUPLEX_HALF)
3396 setting = SUPPORTED_1000baseT_Half;
3397 else
3398 return -EINVAL;
3399 break;
3400 case SPEED_100:
3401 if (ecmd->duplex == DUPLEX_FULL)
3402 setting = SUPPORTED_100baseT_Full;
3403 else if (ecmd->duplex == DUPLEX_HALF)
3404 setting = SUPPORTED_100baseT_Half;
3405 else
3406 return -EINVAL;
3407 break;
3408
3409 case SPEED_10:
3410 if (ecmd->duplex == DUPLEX_FULL)
3411 setting = SUPPORTED_10baseT_Full;
3412 else if (ecmd->duplex == DUPLEX_HALF)
3413 setting = SUPPORTED_10baseT_Half;
3414 else
3415 return -EINVAL;
3416 break;
3417 default:
3418 return -EINVAL;
3419 }
3420
3421 if ((setting & supported) == 0)
3422 return -EINVAL;
3423
3424 sky2->speed = ecmd->speed;
3425 sky2->duplex = ecmd->duplex;
0ea065e5 3426 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3427 }
3428
cd28ab6a
SH		 3429 sky2->advertising = ecmd->advertising;
3430
d1b139c0 3431 if (netif_running(dev)) {
1b537565 3432 sky2_phy_reinit(sky2);
d1b139c0
SH		 3433 sky2_set_multicast(dev);
3434 }
cd28ab6a
SH		 3435
3436 return 0;
3437}
3438
3439static void sky2_get_drvinfo(struct net_device *dev,
3440 struct ethtool_drvinfo *info)
3441{
3442 struct sky2_port *sky2 = netdev_priv(dev);
3443
3444 strcpy(info->driver, DRV_NAME);
3445 strcpy(info->version, DRV_VERSION);
3446 strcpy(info->fw_version, "N/A");
3447 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3448}
3449
3450static const struct sky2_stat {
793b883e
SH		 3451 char name[ETH_GSTRING_LEN];
3452 u16 offset;
cd28ab6a
SH		 3453} sky2_stats[] = {
3454 { "tx_bytes", GM_TXO_OK_HI },
3455 { "rx_bytes", GM_RXO_OK_HI },
3456 { "tx_broadcast", GM_TXF_BC_OK },
3457 { "rx_broadcast", GM_RXF_BC_OK },
3458 { "tx_multicast", GM_TXF_MC_OK },
3459 { "rx_multicast", GM_RXF_MC_OK },
3460 { "tx_unicast", GM_TXF_UC_OK },
3461 { "rx_unicast", GM_RXF_UC_OK },
3462 { "tx_mac_pause", GM_TXF_MPAUSE },
3463 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3464 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3465 { "late_collision",GM_TXF_LAT_COL },
3466 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3467 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3468 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3469
d2604540 3470 { "rx_short", GM_RXF_SHT },
cd28ab6a 3471 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3472 { "rx_64_byte_packets", GM_RXF_64B },
3473 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3474 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3475 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3476 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3477 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3478 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3479 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3480 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3481 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3482 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3483
3484 { "tx_64_byte_packets", GM_TXF_64B },
3485 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3486 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3487 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3488 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3489 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3490 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3491 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3492};
3493
cd28ab6a
SH		 3494static u32 sky2_get_rx_csum(struct net_device *dev)
3495{
3496 struct sky2_port *sky2 = netdev_priv(dev);
3497
0ea065e5 3498 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3499}
3500
3501static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3502{
3503 struct sky2_port *sky2 = netdev_priv(dev);
3504
0ea065e5
SH		 3505 if (data)
3506 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3507 else
3508 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3509
cd28ab6a
SH		 3510 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3511 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3512
3513 return 0;
3514}
3515
3516static u32 sky2_get_msglevel(struct net_device *netdev)
3517{
3518 struct sky2_port *sky2 = netdev_priv(netdev);
3519 return sky2->msg_enable;
3520}
3521
9a7ae0a9
SH		 3522static int sky2_nway_reset(struct net_device *dev)
3523{
3524 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3525
0ea065e5 3526 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3527 return -EINVAL;
3528
1b537565 3529 sky2_phy_reinit(sky2);
d1b139c0 3530 sky2_set_multicast(dev);
9a7ae0a9
SH		 3531
3532 return 0;
3533}
3534
793b883e 3535static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3536{
3537 struct sky2_hw *hw = sky2->hw;
3538 unsigned port = sky2->port;
3539 int i;
3540
3541 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3542 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3543 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3544 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3545
793b883e 3546 for (i = 2; i < count; i++)
cd28ab6a
SH		 3547 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3548}
3549
cd28ab6a
SH		 3550static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3551{
3552 struct sky2_port *sky2 = netdev_priv(netdev);
3553 sky2->msg_enable = value;
3554}
3555
b9f2c044 3556static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3557{
b9f2c044
JG		 3558 switch (sset) {
3559 case ETH_SS_STATS:
3560 return ARRAY_SIZE(sky2_stats);
3561 default:
3562 return -EOPNOTSUPP;
3563 }
cd28ab6a
SH		 3564}
3565
3566static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3567 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3568{
3569 struct sky2_port *sky2 = netdev_priv(dev);
3570
793b883e 3571 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3572}
3573
793b883e 3574static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3575{
3576 int i;
3577
3578 switch (stringset) {
3579 case ETH_SS_STATS:
3580 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3581 memcpy(data + i * ETH_GSTRING_LEN,
3582 sky2_stats[i].name, ETH_GSTRING_LEN);
3583 break;
3584 }
3585}
3586
cd28ab6a
SH		 3587static int sky2_set_mac_address(struct net_device *dev, void *p)
3588{
3589 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3590 struct sky2_hw *hw = sky2->hw;
3591 unsigned port = sky2->port;
3592 const struct sockaddr *addr = p;
cd28ab6a
SH		 3593
3594 if (!is_valid_ether_addr(addr->sa_data))
3595 return -EADDRNOTAVAIL;
3596
cd28ab6a 3597 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3598 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3599 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3600 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3601 dev->dev_addr, ETH_ALEN);
1b537565 3602
a8ab1ec0
SH		 3603 /* virtual address for data */
3604 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3605
3606 /* physical address: used for pause frames */
3607 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3608
3609 return 0;
cd28ab6a
SH		 3610}
3611
a052b52f
SH		 3612static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3613{
3614 u32 bit;
3615
3616 bit = ether_crc(ETH_ALEN, addr) & 63;
3617 filter[bit >> 3] |= 1 << (bit & 7);
3618}
3619
cd28ab6a
SH		 3620static void sky2_set_multicast(struct net_device *dev)
3621{
3622 struct sky2_port *sky2 = netdev_priv(dev);
3623 struct sky2_hw *hw = sky2->hw;
3624 unsigned port = sky2->port;
5508590c 3625 struct dev_mc_list *list;
cd28ab6a
SH		 3626 u16 reg;
3627 u8 filter[8];
a052b52f
SH		 3628 int rx_pause;
3629 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3630
a052b52f 3631 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3632 memset(filter, 0, sizeof(filter));
3633
3634 reg = gma_read16(hw, port, GM_RX_CTRL);
3635 reg |= GM_RXCR_UCF_ENA;
3636
d571b694 3637 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3638 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3639 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3640 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3641 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3642 reg &= ~GM_RXCR_MCF_ENA;
3643 else {
cd28ab6a
SH		 3644 reg |= GM_RXCR_MCF_ENA;
3645
a052b52f
SH		 3646 if (rx_pause)
3647 sky2_add_filter(filter, pause_mc_addr);
3648
5508590c 3649 netdev_for_each_mc_addr(list, dev)
a052b52f 3650 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3651 }
3652
cd28ab6a 3653 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3654 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3655 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3656 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3657 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3658 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3659 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3660 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3661
3662 gma_write16(hw, port, GM_RX_CTRL, reg);
3663}
3664
3665/* Can have one global because blinking is controlled by
3666 * ethtool and that is always under RTNL mutex
3667 */
a84d0a3d 3668static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3669{
a84d0a3d
SH		 3670 struct sky2_hw *hw = sky2->hw;
3671 unsigned port = sky2->port;
793b883e 3672
a84d0a3d
SH		 3673 spin_lock_bh(&sky2->phy_lock);
3674 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3675 hw->chip_id == CHIP_ID_YUKON_EX ||
3676 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3677 u16 pg;
793b883e
SH		 3678 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3679 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3680
a84d0a3d
SH		 3681 switch (mode) {
3682 case MO_LED_OFF:
3683 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3684 PHY_M_LEDC_LOS_CTRL(8) |
3685 PHY_M_LEDC_INIT_CTRL(8) |
3686 PHY_M_LEDC_STA1_CTRL(8) |
3687 PHY_M_LEDC_STA0_CTRL(8));
3688 break;
3689 case MO_LED_ON:
3690 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3691 PHY_M_LEDC_LOS_CTRL(9) |
3692 PHY_M_LEDC_INIT_CTRL(9) |
3693 PHY_M_LEDC_STA1_CTRL(9) |
3694 PHY_M_LEDC_STA0_CTRL(9));
3695 break;
3696 case MO_LED_BLINK:
3697 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3698 PHY_M_LEDC_LOS_CTRL(0xa) |
3699 PHY_M_LEDC_INIT_CTRL(0xa) |
3700 PHY_M_LEDC_STA1_CTRL(0xa) |
3701 PHY_M_LEDC_STA0_CTRL(0xa));
3702 break;
3703 case MO_LED_NORM:
3704 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3705 PHY_M_LEDC_LOS_CTRL(1) |
3706 PHY_M_LEDC_INIT_CTRL(8) |
3707 PHY_M_LEDC_STA1_CTRL(7) |
3708 PHY_M_LEDC_STA0_CTRL(7));
3709 }
793b883e 3710
a84d0a3d
SH		 3711 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3712 } else
7d2e3cb7 3713 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3714 PHY_M_LED_MO_DUP(mode) |
3715 PHY_M_LED_MO_10(mode) |
3716 PHY_M_LED_MO_100(mode) |
3717 PHY_M_LED_MO_1000(mode) |
3718 PHY_M_LED_MO_RX(mode) |
3719 PHY_M_LED_MO_TX(mode));
3720
3721 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3722}
3723
3724/* blink LED's for finding board */
3725static int sky2_phys_id(struct net_device *dev, u32 data)
3726{
3727 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3728 unsigned int i;
cd28ab6a 3729
a84d0a3d
SH		 3730 if (data == 0)
3731 data = UINT_MAX;
cd28ab6a 3732
a84d0a3d
SH		 3733 for (i = 0; i < data; i++) {
3734 sky2_led(sky2, MO_LED_ON);
3735 if (msleep_interruptible(500))
3736 break;
3737 sky2_led(sky2, MO_LED_OFF);
3738 if (msleep_interruptible(500))
3739 break;
793b883e 3740 }
a84d0a3d 3741 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3742
3743 return 0;
3744}
3745
3746static void sky2_get_pauseparam(struct net_device *dev,
3747 struct ethtool_pauseparam *ecmd)
3748{
3749 struct sky2_port *sky2 = netdev_priv(dev);
3750
16ad91e1
SH		 3751 switch (sky2->flow_mode) {
3752 case FC_NONE:
3753 ecmd->tx_pause = ecmd->rx_pause = 0;
3754 break;
3755 case FC_TX:
3756 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3757 break;
3758 case FC_RX:
3759 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3760 break;
3761 case FC_BOTH:
3762 ecmd->tx_pause = ecmd->rx_pause = 1;
3763 }
3764
0ea065e5
SH		 3765 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3766 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3767}
3768
3769static int sky2_set_pauseparam(struct net_device *dev,
3770 struct ethtool_pauseparam *ecmd)
3771{
3772 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3773
0ea065e5
SH		 3774 if (ecmd->autoneg == AUTONEG_ENABLE)
3775 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3776 else
3777 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3778
16ad91e1 3779 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3780
16ad91e1
SH		 3781 if (netif_running(dev))
3782 sky2_phy_reinit(sky2);
cd28ab6a 3783
2eaba1a2 3784 return 0;
cd28ab6a
SH		 3785}
3786
fb17358f
SH		 3787static int sky2_get_coalesce(struct net_device *dev,
3788 struct ethtool_coalesce *ecmd)
3789{
3790 struct sky2_port *sky2 = netdev_priv(dev);
3791 struct sky2_hw *hw = sky2->hw;
3792
3793 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3794 ecmd->tx_coalesce_usecs = 0;
3795 else {
3796 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3797 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3798 }
3799 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3800
3801 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3802 ecmd->rx_coalesce_usecs = 0;
3803 else {
3804 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3805 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3806 }
3807 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3808
3809 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3810 ecmd->rx_coalesce_usecs_irq = 0;
3811 else {
3812 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3813 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3814 }
3815
3816 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3817
3818 return 0;
3819}
3820
3821/* Note: this affect both ports */
3822static int sky2_set_coalesce(struct net_device *dev,
3823 struct ethtool_coalesce *ecmd)
3824{
3825 struct sky2_port *sky2 = netdev_priv(dev);
3826 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3827 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3828
77b3d6a2
SH		 3829 if (ecmd->tx_coalesce_usecs > tmax ||
3830 ecmd->rx_coalesce_usecs > tmax ||
3831 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3832 return -EINVAL;
3833
ee5f68fe 3834 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3835 return -EINVAL;
ff81fbbe 3836 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3837 return -EINVAL;
ff81fbbe 3838 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3839 return -EINVAL;
3840
3841 if (ecmd->tx_coalesce_usecs == 0)
3842 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3843 else {
3844 sky2_write32(hw, STAT_TX_TIMER_INI,
3845 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3846 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3847 }
3848 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3849
3850 if (ecmd->rx_coalesce_usecs == 0)
3851 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3852 else {
3853 sky2_write32(hw, STAT_LEV_TIMER_INI,
3854 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3855 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3856 }
3857 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3858
3859 if (ecmd->rx_coalesce_usecs_irq == 0)
3860 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3861 else {
d28d4870 3862 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3863 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3864 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3865 }
3866 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3867 return 0;
3868}
3869
793b883e
SH		 3870static void sky2_get_ringparam(struct net_device *dev,
3871 struct ethtool_ringparam *ering)
3872{
3873 struct sky2_port *sky2 = netdev_priv(dev);
3874
3875 ering->rx_max_pending = RX_MAX_PENDING;
3876 ering->rx_mini_max_pending = 0;
3877 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3878 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3879
3880 ering->rx_pending = sky2->rx_pending;
3881 ering->rx_mini_pending = 0;
3882 ering->rx_jumbo_pending = 0;
3883 ering->tx_pending = sky2->tx_pending;
3884}
3885
3886static int sky2_set_ringparam(struct net_device *dev,
3887 struct ethtool_ringparam *ering)
3888{
3889 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3890
3891 if (ering->rx_pending > RX_MAX_PENDING ||
3892 ering->rx_pending < 8 ||
ee5f68fe
SH		 3893 ering->tx_pending < TX_MIN_PENDING ||
3894 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3895 return -EINVAL;
3896
af18d8b8 3897 sky2_detach(dev);
793b883e
SH		 3898
3899 sky2->rx_pending = ering->rx_pending;
3900 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3901 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3902
af18d8b8 3903 return sky2_reattach(dev);
793b883e
SH		 3904}
3905
793b883e
SH		 3906static int sky2_get_regs_len(struct net_device *dev)
3907{
6e4cbb34 3908 return 0x4000;
793b883e
SH		 3909}
3910
c32bbff8
MM		 3911static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3912{
3913 /* This complicated switch statement is to make sure and
3914 * only access regions that are unreserved.
3915 * Some blocks are only valid on dual port cards.
3916 */
3917 switch (b) {
3918 /* second port */
3919 case 5: /* Tx Arbiter 2 */
3920 case 9: /* RX2 */
3921 case 14 ... 15: /* TX2 */
3922 case 17: case 19: /* Ram Buffer 2 */
3923 case 22 ... 23: /* Tx Ram Buffer 2 */
3924 case 25: /* Rx MAC Fifo 1 */
3925 case 27: /* Tx MAC Fifo 2 */
3926 case 31: /* GPHY 2 */
3927 case 40 ... 47: /* Pattern Ram 2 */
3928 case 52: case 54: /* TCP Segmentation 2 */
3929 case 112 ... 116: /* GMAC 2 */
3930 return hw->ports > 1;
3931
3932 case 0: /* Control */
3933 case 2: /* Mac address */
3934 case 4: /* Tx Arbiter 1 */
3935 case 7: /* PCI express reg */
3936 case 8: /* RX1 */
3937 case 12 ... 13: /* TX1 */
3938 case 16: case 18:/* Rx Ram Buffer 1 */
3939 case 20 ... 21: /* Tx Ram Buffer 1 */
3940 case 24: /* Rx MAC Fifo 1 */
3941 case 26: /* Tx MAC Fifo 1 */
3942 case 28 ... 29: /* Descriptor and status unit */
3943 case 30: /* GPHY 1*/
3944 case 32 ... 39: /* Pattern Ram 1 */
3945 case 48: case 50: /* TCP Segmentation 1 */
3946 case 56 ... 60: /* PCI space */
3947 case 80 ... 84: /* GMAC 1 */
3948 return 1;
3949
3950 default:
3951 return 0;
3952 }
3953}
3954
793b883e
SH		 3955/*
3956 * Returns copy of control register region
3ead5db7 3957 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3958 */
3959static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3960 void *p)
3961{
3962 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3963 const void __iomem *io = sky2->hw->regs;
295b54c4 3964 unsigned int b;
793b883e
SH		 3965
3966 regs->version = 1;
793b883e 3967
295b54c4 3968 for (b = 0; b < 128; b++) {
c32bbff8
MM		 3969 /* skip poisonous diagnostic ram region in block 3 */
3970 if (b == 3)
295b54c4 3971 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 3972 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 3973 memcpy_fromio(p, io, 128);
c32bbff8 3974 else
295b54c4 3975 memset(p, 0, 128);
3ead5db7 3976
295b54c4
SH		 3977 p += 128;
3978 io += 128;
3979 }
793b883e 3980}
cd28ab6a 3981
b628ed98
SH		 3982/* In order to do Jumbo packets on these chips, need to turn off the
3983 * transmit store/forward. Therefore checksum offload won't work.
3984 */
3985static int no_tx_offload(struct net_device *dev)
3986{
3987 const struct sky2_port *sky2 = netdev_priv(dev);
3988 const struct sky2_hw *hw = sky2->hw;
3989
69161611 3990 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3991}
3992
3993static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3994{
3995 if (data && no_tx_offload(dev))
3996 return -EINVAL;
3997
3998 return ethtool_op_set_tx_csum(dev, data);
3999}
4000
4001
4002static int sky2_set_tso(struct net_device *dev, u32 data)
4003{
4004 if (data && no_tx_offload(dev))
4005 return -EINVAL;
4006
4007 return ethtool_op_set_tso(dev, data);
4008}
4009
f4331a6d
SH		 4010static int sky2_get_eeprom_len(struct net_device *dev)
4011{
4012 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 4013 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 4014 u16 reg2;
4015
b32f40c4 4016 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 4017 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4018}
4019
1413235c 4020static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 4021{
1413235c 4022 unsigned long start = jiffies;
f4331a6d 4023
1413235c
SH		 4024 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4025 /* Can take up to 10.6 ms for write */
4026 if (time_after(jiffies, start + HZ/4)) {
ada1db5c 4027 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
1413235c
SH		 4028 return -ETIMEDOUT;
4029 }
4030 mdelay(1);
4031 }
167f53d0 4032
1413235c
SH		 4033 return 0;
4034}
167f53d0 4035
1413235c
SH		 4036static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4037 u16 offset, size_t length)
4038{
4039 int rc = 0;
4040
4041 while (length > 0) {
4042 u32 val;
4043
4044 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4045 rc = sky2_vpd_wait(hw, cap, 0);
4046 if (rc)
4047 break;
4048
4049 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4050
4051 memcpy(data, &val, min(sizeof(val), length));
4052 offset += sizeof(u32);
4053 data += sizeof(u32);
4054 length -= sizeof(u32);
4055 }
4056
4057 return rc;
f4331a6d
SH		 4058}
4059
1413235c
SH		 4060static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4061 u16 offset, unsigned int length)
f4331a6d 4062{
1413235c
SH		 4063 unsigned int i;
4064 int rc = 0;
4065
4066 for (i = 0; i < length; i += sizeof(u32)) {
4067 u32 val = *(u32 *)(data + i);
4068
4069 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4070 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4071
4072 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4073 if (rc)
4074 break;
4075 }
4076 return rc;
f4331a6d
SH		 4077}
4078
4079static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4080 u8 *data)
4081{
4082 struct sky2_port *sky2 = netdev_priv(dev);
4083 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4084
4085 if (!cap)
4086 return -EINVAL;
4087
4088 eeprom->magic = SKY2_EEPROM_MAGIC;
4089
1413235c 4090 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4091}
4092
4093static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4094 u8 *data)
4095{
4096 struct sky2_port *sky2 = netdev_priv(dev);
4097 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4098
4099 if (!cap)
4100 return -EINVAL;
4101
4102 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4103 return -EINVAL;
4104
1413235c
SH		 4105 /* Partial writes not supported */
4106 if ((eeprom->offset & 3) || (eeprom->len & 3))
4107 return -EINVAL;
f4331a6d 4108
1413235c 4109 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4110}
4111
4112
7282d491 4113static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4114 .get_settings = sky2_get_settings,
4115 .set_settings = sky2_set_settings,
4116 .get_drvinfo = sky2_get_drvinfo,
4117 .get_wol = sky2_get_wol,
4118 .set_wol = sky2_set_wol,
4119 .get_msglevel = sky2_get_msglevel,
4120 .set_msglevel = sky2_set_msglevel,
4121 .nway_reset = sky2_nway_reset,
4122 .get_regs_len = sky2_get_regs_len,
4123 .get_regs = sky2_get_regs,
4124 .get_link = ethtool_op_get_link,
4125 .get_eeprom_len = sky2_get_eeprom_len,
4126 .get_eeprom = sky2_get_eeprom,
4127 .set_eeprom = sky2_set_eeprom,
f4331a6d 4128 .set_sg = ethtool_op_set_sg,
f4331a6d 4129 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 4130 .set_tso = sky2_set_tso,
4131 .get_rx_csum = sky2_get_rx_csum,
4132 .set_rx_csum = sky2_set_rx_csum,
4133 .get_strings = sky2_get_strings,
4134 .get_coalesce = sky2_get_coalesce,
4135 .set_coalesce = sky2_set_coalesce,
4136 .get_ringparam = sky2_get_ringparam,
4137 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4138 .get_pauseparam = sky2_get_pauseparam,
4139 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 4140 .phys_id = sky2_phys_id,
b9f2c044 4141 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 4142 .get_ethtool_stats = sky2_get_ethtool_stats,
4143};
4144
3cf26753
SH		 4145#ifdef CONFIG_SKY2_DEBUG
4146
4147static struct dentry *sky2_debug;
4148
e4c2abe2
SH		 4149
4150/*
4151 * Read and parse the first part of Vital Product Data
4152 */
4153#define VPD_SIZE 128
4154#define VPD_MAGIC 0x82
4155
4156static const struct vpd_tag {
4157 char tag[2];
4158 char *label;
4159} vpd_tags[] = {
4160 { "PN", "Part Number" },
4161 { "EC", "Engineering Level" },
4162 { "MN", "Manufacturer" },
4163 { "SN", "Serial Number" },
4164 { "YA", "Asset Tag" },
4165 { "VL", "First Error Log Message" },
4166 { "VF", "Second Error Log Message" },
4167 { "VB", "Boot Agent ROM Configuration" },
4168 { "VE", "EFI UNDI Configuration" },
4169};
4170
4171static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4172{
4173 size_t vpd_size;
4174 loff_t offs;
4175 u8 len;
4176 unsigned char *buf;
4177 u16 reg2;
4178
4179 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4180 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4181
4182 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4183 buf = kmalloc(vpd_size, GFP_KERNEL);
4184 if (!buf) {
4185 seq_puts(seq, "no memory!\n");
4186 return;
4187 }
4188
4189 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4190 seq_puts(seq, "VPD read failed\n");
4191 goto out;
4192 }
4193
4194 if (buf[0] != VPD_MAGIC) {
4195 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4196 goto out;
4197 }
4198 len = buf[1];
4199 if (len == 0 || len > vpd_size - 4) {
4200 seq_printf(seq, "Invalid id length: %d\n", len);
4201 goto out;
4202 }
4203
4204 seq_printf(seq, "%.*s\n", len, buf + 3);
4205 offs = len + 3;
4206
4207 while (offs < vpd_size - 4) {
4208 int i;
4209
4210 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4211 break;
4212 len = buf[offs + 2];
4213 if (offs + len + 3 >= vpd_size)
4214 break;
4215
4216 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4217 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4218 seq_printf(seq, " %s: %.*s\n",
4219 vpd_tags[i].label, len, buf + offs + 3);
4220 break;
4221 }
4222 }
4223 offs += len + 3;
4224 }
4225out:
4226 kfree(buf);
4227}
4228
3cf26753
SH		 4229static int sky2_debug_show(struct seq_file *seq, void *v)
4230{
4231 struct net_device *dev = seq->private;
4232 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4233 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4234 unsigned port = sky2->port;
4235 unsigned idx, last;
4236 int sop;
4237
e4c2abe2 4238 sky2_show_vpd(seq, hw);
3cf26753 4239
e4c2abe2 4240 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4241 sky2_read32(hw, B0_ISRC),
4242 sky2_read32(hw, B0_IMSK),
4243 sky2_read32(hw, B0_Y2_SP_ICR));
4244
e4c2abe2
SH		 4245 if (!netif_running(dev)) {
4246 seq_printf(seq, "network not running\n");
4247 return 0;
4248 }
4249
bea3348e 4250 napi_disable(&hw->napi);
3cf26753
SH		 4251 last = sky2_read16(hw, STAT_PUT_IDX);
4252
4253 if (hw->st_idx == last)
4254 seq_puts(seq, "Status ring (empty)\n");
4255 else {
4256 seq_puts(seq, "Status ring\n");
4257 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4258 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4259 const struct sky2_status_le *le = hw->st_le + idx;
4260 seq_printf(seq, "[%d] %#x %d %#x\n",
4261 idx, le->opcode, le->length, le->status);
4262 }
4263 seq_puts(seq, "\n");
4264 }
4265
4266 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4267 sky2->tx_cons, sky2->tx_prod,
4268 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4269 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4270
4271 /* Dump contents of tx ring */
4272 sop = 1;
ee5f68fe
SH		 4273 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4274 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4275 const struct sky2_tx_le *le = sky2->tx_le + idx;
4276 u32 a = le32_to_cpu(le->addr);
4277
4278 if (sop)
4279 seq_printf(seq, "%u:", idx);
4280 sop = 0;
4281
4282 switch(le->opcode & ~HW_OWNER) {
4283 case OP_ADDR64:
4284 seq_printf(seq, " %#x:", a);
4285 break;
4286 case OP_LRGLEN:
4287 seq_printf(seq, " mtu=%d", a);
4288 break;
4289 case OP_VLAN:
4290 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4291 break;
4292 case OP_TCPLISW:
4293 seq_printf(seq, " csum=%#x", a);
4294 break;
4295 case OP_LARGESEND:
4296 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4297 break;
4298 case OP_PACKET:
4299 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4300 break;
4301 case OP_BUFFER:
4302 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4303 break;
4304 default:
4305 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4306 a, le16_to_cpu(le->length));
4307 }
4308
4309 if (le->ctrl & EOP) {
4310 seq_putc(seq, '\n');
4311 sop = 1;
4312 }
4313 }
4314
4315 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4316 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4317 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4318 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4319
d1d08d12 4320 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4321 napi_enable(&hw->napi);
3cf26753
SH		 4322 return 0;
4323}
4324
4325static int sky2_debug_open(struct inode *inode, struct file *file)
4326{
4327 return single_open(file, sky2_debug_show, inode->i_private);
4328}
4329
4330static const struct file_operations sky2_debug_fops = {
4331 .owner = THIS_MODULE,
4332 .open = sky2_debug_open,
4333 .read = seq_read,
4334 .llseek = seq_lseek,
4335 .release = single_release,
4336};
4337
4338/*
4339 * Use network device events to create/remove/rename
4340 * debugfs file entries
4341 */
4342static int sky2_device_event(struct notifier_block *unused,
4343 unsigned long event, void *ptr)
4344{
4345 struct net_device *dev = ptr;
5b296bc9 4346 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4347
1436b301 4348 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4349 return NOTIFY_DONE;
3cf26753 4350
5b296bc9
SH		 4351 switch(event) {
4352 case NETDEV_CHANGENAME:
4353 if (sky2->debugfs) {
4354 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4355 sky2_debug, dev->name);
4356 }
4357 break;
3cf26753 4358
5b296bc9
SH		 4359 case NETDEV_GOING_DOWN:
4360 if (sky2->debugfs) {
ada1db5c 4361 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
5b296bc9
SH		 4362 debugfs_remove(sky2->debugfs);
4363 sky2->debugfs = NULL;
3cf26753 4364 }
5b296bc9
SH		 4365 break;
4366
4367 case NETDEV_UP:
4368 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4369 sky2_debug, dev,
4370 &sky2_debug_fops);
4371 if (IS_ERR(sky2->debugfs))
4372 sky2->debugfs = NULL;
3cf26753
SH		 4373 }
4374
4375 return NOTIFY_DONE;
4376}
4377
4378static struct notifier_block sky2_notifier = {
4379 .notifier_call = sky2_device_event,
4380};
4381
4382
4383static __init void sky2_debug_init(void)
4384{
4385 struct dentry *ent;
4386
4387 ent = debugfs_create_dir("sky2", NULL);
4388 if (!ent || IS_ERR(ent))
4389 return;
4390
4391 sky2_debug = ent;
4392 register_netdevice_notifier(&sky2_notifier);
4393}
4394
4395static __exit void sky2_debug_cleanup(void)
4396{
4397 if (sky2_debug) {
4398 unregister_netdevice_notifier(&sky2_notifier);
4399 debugfs_remove(sky2_debug);
4400 sky2_debug = NULL;
4401 }
4402}
4403
4404#else
4405#define sky2_debug_init()
4406#define sky2_debug_cleanup()
4407#endif
4408
1436b301
SH		 4409/* Two copies of network device operations to handle special case of
4410 not allowing netpoll on second port */
4411static const struct net_device_ops sky2_netdev_ops[2] = {
4412 {
4413 .ndo_open = sky2_up,
4414 .ndo_stop = sky2_down,
00829823 4415 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4416 .ndo_do_ioctl = sky2_ioctl,
4417 .ndo_validate_addr = eth_validate_addr,
4418 .ndo_set_mac_address = sky2_set_mac_address,
4419 .ndo_set_multicast_list = sky2_set_multicast,
4420 .ndo_change_mtu = sky2_change_mtu,
4421 .ndo_tx_timeout = sky2_tx_timeout,
4422#ifdef SKY2_VLAN_TAG_USED
4423 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4424#endif
4425#ifdef CONFIG_NET_POLL_CONTROLLER
4426 .ndo_poll_controller = sky2_netpoll,
4427#endif
4428 },
4429 {
4430 .ndo_open = sky2_up,
4431 .ndo_stop = sky2_down,
00829823 4432 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4433 .ndo_do_ioctl = sky2_ioctl,
4434 .ndo_validate_addr = eth_validate_addr,
4435 .ndo_set_mac_address = sky2_set_mac_address,
4436 .ndo_set_multicast_list = sky2_set_multicast,
4437 .ndo_change_mtu = sky2_change_mtu,
4438 .ndo_tx_timeout = sky2_tx_timeout,
4439#ifdef SKY2_VLAN_TAG_USED
4440 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4441#endif
4442 },
4443};
3cf26753 4444
cd28ab6a
SH		 4445/* Initialize network device */
4446static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4447 unsigned port,
be63a21c 4448 int highmem, int wol)
cd28ab6a
SH		 4449{
4450 struct sky2_port *sky2;
4451 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4452
4453 if (!dev) {
898eb71c 4454 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4455 return NULL;
4456 }
4457
cd28ab6a 4458 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4459 dev->irq = hw->pdev->irq;
cd28ab6a 4460 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4461 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4462 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4463
4464 sky2 = netdev_priv(dev);
4465 sky2->netdev = dev;
4466 sky2->hw = hw;
4467 sky2->msg_enable = netif_msg_init(debug, default_msg);
4468
cd28ab6a 4469 /* Auto speed and flow control */
0ea065e5
SH		 4470 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4471 if (hw->chip_id != CHIP_ID_YUKON_XL)
4472 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4473
16ad91e1
SH		 4474 sky2->flow_mode = FC_BOTH;
4475
cd28ab6a
SH		 4476 sky2->duplex = -1;
4477 sky2->speed = -1;
4478 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4479 sky2->wol = wol;
75d070c5 4480
e07b1aa8 4481 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4482
793b883e 4483 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4484 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4485 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4486
4487 hw->dev[port] = dev;
4488
4489 sky2->port = port;
4490
4a50a876 4491 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4492 if (highmem)
4493 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4494
d1f13708 4495#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4496 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4497 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4498 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4499 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4500 }
d1f13708
SH		 4501#endif
4502
cd28ab6a 4503 /* read the mac address */
793b883e 4504 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4505 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4506
cd28ab6a
SH		 4507 return dev;
4508}
4509
28bd181a 4510static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4511{
4512 const struct sky2_port *sky2 = netdev_priv(dev);
4513
6c35abae 4514 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
cd28ab6a
SH		 4515}
4516
fb2690a9 4517/* Handle software interrupt used during MSI test */
7d12e780 4518static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4519{
4520 struct sky2_hw *hw = dev_id;
4521 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4522
4523 if (status == 0)
4524 return IRQ_NONE;
4525
4526 if (status & Y2_IS_IRQ_SW) {
ea76e635 4527 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4528 wake_up(&hw->msi_wait);
4529 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4530 }
4531 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4532
4533 return IRQ_HANDLED;
4534}
4535
4536/* Test interrupt path by forcing a a software IRQ */
4537static int __devinit sky2_test_msi(struct sky2_hw *hw)
4538{
4539 struct pci_dev *pdev = hw->pdev;
4540 int err;
4541
bb507fe1
SH		 4542 init_waitqueue_head (&hw->msi_wait);
4543
fb2690a9
SH		 4544 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4545
b0a20ded 4546 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4547 if (err) {
b02a9258 4548 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4549 return err;
4550 }
4551
fb2690a9 4552 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4553 sky2_read8(hw, B0_CTST);
fb2690a9 4554
ea76e635 4555 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4556
ea76e635 4557 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4558 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4559 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4560 "switching to INTx mode.\n");
fb2690a9
SH		 4561
4562 err = -EOPNOTSUPP;
4563 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4564 }
4565
4566 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4567 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4568
4569 free_irq(pdev->irq, hw);
4570
4571 return err;
4572}
4573
c7127a34
SH		 4574/* This driver supports yukon2 chipset only */
4575static const char *sky2_name(u8 chipid, char *buf, int sz)
4576{
4577 const char *name[] = {
4578 "XL", /* 0xb3 */
4579 "EC Ultra", /* 0xb4 */
4580 "Extreme", /* 0xb5 */
4581 "EC", /* 0xb6 */
4582 "FE", /* 0xb7 */
4583 "FE+", /* 0xb8 */
4584 "Supreme", /* 0xb9 */
0ce8b98d 4585 "UL 2", /* 0xba */
0f5aac70
SH		 4586 "Unknown", /* 0xbb */
4587 "Optima", /* 0xbc */
c7127a34
SH		 4588 };
4589
dae3a511 4590 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
c7127a34
SH		 4591 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4592 else
4593 snprintf(buf, sz, "(chip %#x)", chipid);
4594 return buf;
4595}
4596
cd28ab6a
SH		 4597static int __devinit sky2_probe(struct pci_dev *pdev,
4598 const struct pci_device_id *ent)
4599{
7f60c64b 4600 struct net_device *dev;
cd28ab6a 4601 struct sky2_hw *hw;
be63a21c 4602 int err, using_dac = 0, wol_default;
3834507d 4603 u32 reg;
c7127a34 4604 char buf1[16];
cd28ab6a 4605
793b883e
SH		 4606 err = pci_enable_device(pdev);
4607 if (err) {
b02a9258 4608 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4609 goto err_out;
4610 }
4611
6cc90a5a
SH		 4612 /* Get configuration information
4613 * Note: only regular PCI config access once to test for HW issues
4614 * other PCI access through shared memory for speed and to
4615 * avoid MMCONFIG problems.
4616 */
4617 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4618 if (err) {
4619 dev_err(&pdev->dev, "PCI read config failed\n");
4620 goto err_out;
4621 }
4622
4623 if (~reg == 0) {
4624 dev_err(&pdev->dev, "PCI configuration read error\n");
4625 goto err_out;
4626 }
4627
793b883e
SH		 4628 err = pci_request_regions(pdev, DRV_NAME);
4629 if (err) {
b02a9258 4630 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4631 goto err_out_disable;
cd28ab6a
SH		 4632 }
4633
4634 pci_set_master(pdev);
4635
d1f3d4dd 4636 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4637 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4638 using_dac = 1;
6a35528a 4639 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4640 if (err < 0) {
b02a9258
SH		 4641 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4642 "for consistent allocations\n");
d1f3d4dd
SH		 4643 goto err_out_free_regions;
4644 }
d1f3d4dd 4645 } else {
284901a9 4646 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4647 if (err) {
b02a9258 4648 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4649 goto err_out_free_regions;
4650 }
4651 }
d1f3d4dd 4652
3834507d
SH		 4653
4654#ifdef __BIG_ENDIAN
4655 /* The sk98lin vendor driver uses hardware byte swapping but
4656 * this driver uses software swapping.
4657 */
4658 reg &= ~PCI_REV_DESC;
4659 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4660 if (err) {
4661 dev_err(&pdev->dev, "PCI write config failed\n");
4662 goto err_out_free_regions;
4663 }
4664#endif
4665
9d731d77 4666 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4667
cd28ab6a 4668 err = -ENOMEM;
66466797
SH		 4669
4670 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4671 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4672 if (!hw) {
b02a9258 4673 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4674 goto err_out_free_regions;
4675 }
4676
cd28ab6a 4677 hw->pdev = pdev;
66466797 4678 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4679
4680 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4681 if (!hw->regs) {
b02a9258 4682 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4683 goto err_out_free_hw;
4684 }
4685
08c06d8a 4686 /* ring for status responses */
167f53d0 4687 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4688 if (!hw->st_le)
4689 goto err_out_iounmap;
4690
e3173832 4691 err = sky2_init(hw);
cd28ab6a 4692 if (err)
793b883e 4693 goto err_out_iounmap;
cd28ab6a 4694
c844d483
SH		 4695 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4696 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4697
e3173832
SH		 4698 sky2_reset(hw);
4699
be63a21c 4700 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4701 if (!dev) {
4702 err = -ENOMEM;
cd28ab6a 4703 goto err_out_free_pci;
7f60c64b 4704 }
cd28ab6a 4705
9fa1b1f3
SH		 4706 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4707 err = sky2_test_msi(hw);
4708 if (err == -EOPNOTSUPP)
4709 pci_disable_msi(pdev);
4710 else if (err)
4711 goto err_out_free_netdev;
4712 }
4713
793b883e
SH		 4714 err = register_netdev(dev);
4715 if (err) {
b02a9258 4716 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4717 goto err_out_free_netdev;
4718 }
4719
33cb7d33
BP		 4720 netif_carrier_off(dev);
4721
6de16237
SH		 4722 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4723
ea76e635
SH		 4724 err = request_irq(pdev->irq, sky2_intr,
4725 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4726 hw->irq_name, hw);
9fa1b1f3 4727 if (err) {
b02a9258 4728 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4729 goto err_out_unregister;
4730 }
4731 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4732 napi_enable(&hw->napi);
9fa1b1f3 4733
cd28ab6a
SH		 4734 sky2_show_addr(dev);
4735
7f60c64b 4736 if (hw->ports > 1) {
4737 struct net_device *dev1;
4738
ca519274 4739 err = -ENOMEM;
be63a21c 4740 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4741 if (dev1 && (err = register_netdev(dev1)) == 0)
4742 sky2_show_addr(dev1);
4743 else {
b02a9258
SH		 4744 dev_warn(&pdev->dev,
4745 "register of second port failed (%d)\n", err);
cd28ab6a 4746 hw->dev[1] = NULL;
ca519274
SH		 4747 hw->ports = 1;
4748 if (dev1)
4749 free_netdev(dev1);
4750 }
cd28ab6a
SH		 4751 }
4752
32c2c300 4753 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4754 INIT_WORK(&hw->restart_work, sky2_restart);
4755
793b883e 4756 pci_set_drvdata(pdev, hw);
1ae861e6 4757 pdev->d3_delay = 150;
793b883e 4758
cd28ab6a
SH		 4759 return 0;
4760
793b883e 4761err_out_unregister:
ea76e635 4762 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4763 pci_disable_msi(pdev);
793b883e 4764 unregister_netdev(dev);
cd28ab6a
SH		 4765err_out_free_netdev:
4766 free_netdev(dev);
cd28ab6a 4767err_out_free_pci:
793b883e 4768 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4769 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4770err_out_iounmap:
4771 iounmap(hw->regs);
4772err_out_free_hw:
4773 kfree(hw);
4774err_out_free_regions:
4775 pci_release_regions(pdev);
44a1d2e5 4776err_out_disable:
cd28ab6a 4777 pci_disable_device(pdev);
cd28ab6a 4778err_out:
549a68c3 4779 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4780 return err;
4781}
4782
4783static void __devexit sky2_remove(struct pci_dev *pdev)
4784{
793b883e 4785 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4786 int i;
cd28ab6a 4787
793b883e 4788 if (!hw)
cd28ab6a
SH		 4789 return;
4790
32c2c300 4791 del_timer_sync(&hw->watchdog_timer);
6de16237 4792 cancel_work_sync(&hw->restart_work);
d27ed387 4793
b877fe28 4794 for (i = hw->ports-1; i >= 0; --i)
6de16237 4795 unregister_netdev(hw->dev[i]);
81906791 4796
d27ed387 4797 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4798
ae306cca
SH		 4799 sky2_power_aux(hw);
4800
793b883e 4801 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4802 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4803
4804 free_irq(pdev->irq, hw);
ea76e635 4805 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4806 pci_disable_msi(pdev);
793b883e 4807 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4808 pci_release_regions(pdev);
4809 pci_disable_device(pdev);
793b883e 4810
b877fe28 4811 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4812 free_netdev(hw->dev[i]);
4813
cd28ab6a
SH		 4814 iounmap(hw->regs);
4815 kfree(hw);
5afa0a9c 4816
cd28ab6a
SH		 4817 pci_set_drvdata(pdev, NULL);
4818}
4819
cd28ab6a
SH		 4820static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4821{
793b883e 4822 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4823 int i, wol = 0;
cd28ab6a 4824
549a68c3
SH		 4825 if (!hw)
4826 return 0;
4827
063a0b38
SH		 4828 del_timer_sync(&hw->watchdog_timer);
4829 cancel_work_sync(&hw->restart_work);
4830
19720737 4831 rtnl_lock();
f05267e7 4832 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4833 struct net_device *dev = hw->dev[i];
e3173832 4834 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4835
af18d8b8 4836 sky2_detach(dev);
e3173832
SH		 4837
4838 if (sky2->wol)
4839 sky2_wol_init(sky2);
4840
4841 wol |= sky2->wol;
cd28ab6a
SH		 4842 }
4843
5f8ae5c5 4844 device_set_wakeup_enable(&pdev->dev, wol != 0);
4845
8ab8fca2 4846 sky2_write32(hw, B0_IMSK, 0);
6de16237 4847 napi_disable(&hw->napi);
ae306cca 4848 sky2_power_aux(hw);
19720737 4849 rtnl_unlock();
e3173832 4850
d374c1c1 4851 pci_save_state(pdev);
e3173832 4852 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4853 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4854
2ccc99b7 4855 return 0;
cd28ab6a
SH		 4856}
4857
5f8ae5c5 4858#ifdef CONFIG_PM
cd28ab6a
SH		 4859static int sky2_resume(struct pci_dev *pdev)
4860{
793b883e 4861 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4862 int i, err;
cd28ab6a 4863
549a68c3
SH		 4864 if (!hw)
4865 return 0;
4866
2a400189 4867 rtnl_lock();
f71eb1a2
SH		 4868 err = pci_set_power_state(pdev, PCI_D0);
4869 if (err)
4870 goto out;
ae306cca
SH		 4871
4872 err = pci_restore_state(pdev);
4873 if (err)
4874 goto out;
4875
cd28ab6a 4876 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4877
4878 /* Re-enable all clocks */
a0db28b8 4879 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4880 if (err) {
4881 dev_err(&pdev->dev, "PCI write config failed\n");
4882 goto out;
4883 }
1ad5b4a5 4884
e3173832 4885 sky2_reset(hw);
8ab8fca2 4886 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4887 napi_enable(&hw->napi);
8ab8fca2 4888
f05267e7 4889 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4890 err = sky2_reattach(hw->dev[i]);
4891 if (err)
4892 goto out;
cd28ab6a 4893 }
af18d8b8 4894 rtnl_unlock();
eb35cf60 4895
ae306cca 4896 return 0;
08c06d8a 4897out:
af18d8b8
SH		 4898 rtnl_unlock();
4899
b02a9258 4900 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4901 pci_disable_device(pdev);
08c06d8a 4902 return err;
cd28ab6a
SH		 4903}
4904#endif
4905
e3173832
SH		 4906static void sky2_shutdown(struct pci_dev *pdev)
4907{
5f8ae5c5 4908 sky2_suspend(pdev, PMSG_SUSPEND);
e3173832
SH		 4909}
4910
cd28ab6a 4911static struct pci_driver sky2_driver = {
793b883e
SH		 4912 .name = DRV_NAME,
4913 .id_table = sky2_id_table,
4914 .probe = sky2_probe,
4915 .remove = __devexit_p(sky2_remove),
cd28ab6a 4916#ifdef CONFIG_PM
793b883e
SH		 4917 .suspend = sky2_suspend,
4918 .resume = sky2_resume,
cd28ab6a 4919#endif
e3173832 4920 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4921};
4922
4923static int __init sky2_init_module(void)
4924{
ada1db5c 4925 pr_info("driver version " DRV_VERSION "\n");
c844d483 4926
3cf26753 4927 sky2_debug_init();
50241c4c 4928 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4929}
4930
4931static void __exit sky2_cleanup_module(void)
4932{
4933 pci_unregister_driver(&sky2_driver);
3cf26753 4934 sky2_debug_cleanup();
cd28ab6a
SH		 4935}
4936
4937module_init(sky2_init_module);
4938module_exit(sky2_cleanup_module);
4939
4940MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4941MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4942MODULE_LICENSE("GPL");
5f4f9dc1 4943MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree