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Fix memory corruption in fec_mpc52xx
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
1e354787 54#define DRV_VERSION "1.20"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
cd28ab6a
SH		 138 { 0 }
139};
793b883e 140
cd28ab6a
SH		 141MODULE_DEVICE_TABLE(pci, sky2_id_table);
142
143/* Avoid conditionals by using array */
144static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
145static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 146static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 147
92f965e8
SH		 148/* This driver supports yukon2 chipset only */
149static const char *yukon2_name[] = {
150 "XL", /* 0xb3 */
151 "EC Ultra", /* 0xb4 */
93745494 152 "Extreme", /* 0xb5 */
92f965e8
SH		 153 "EC", /* 0xb6 */
154 "FE", /* 0xb7 */
05745c4a 155 "FE+", /* 0xb8 */
793b883e
SH		 156};
157
d1b139c0
SH		 158static void sky2_set_multicast(struct net_device *dev);
159
af043aa5 160/* Access to PHY via serial interconnect */
ef743d33 161static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 162{
163 int i;
164
165 gma_write16(hw, port, GM_SMI_DATA, val);
166 gma_write16(hw, port, GM_SMI_CTRL,
167 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
168
169 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 170 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
171 if (ctrl == 0xffff)
172 goto io_error;
173
174 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 175 return 0;
af043aa5
SH		 176
177 udelay(10);
cd28ab6a 178 }
ef743d33 179
af043aa5 180 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 181 return -ETIMEDOUT;
af043aa5
SH		 182
183io_error:
184 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
185 return -EIO;
cd28ab6a
SH		 186}
187
ef743d33 188static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 189{
190 int i;
191
793b883e 192 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 193 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
194
195 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 196 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
197 if (ctrl == 0xffff)
198 goto io_error;
199
200 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 201 *val = gma_read16(hw, port, GM_SMI_DATA);
202 return 0;
203 }
204
af043aa5 205 udelay(10);
cd28ab6a
SH		 206 }
207
af043aa5 208 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 209 return -ETIMEDOUT;
af043aa5
SH		 210io_error:
211 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
212 return -EIO;
ef743d33
SH		 213}
214
af043aa5 215static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 216{
217 u16 v;
af043aa5 218 __gm_phy_read(hw, port, reg, &v);
ef743d33 219 return v;
cd28ab6a
SH		 220}
221
5afa0a9c 222
ae306cca
SH		 223static void sky2_power_on(struct sky2_hw *hw)
224{
225 /* switch power to VCC (WA for VAUX problem) */
226 sky2_write8(hw, B0_POWER_CTRL,
227 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 228
ae306cca
SH		 229 /* disable Core Clock Division, */
230 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 231
ae306cca
SH		 232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
233 /* enable bits are inverted */
234 sky2_write8(hw, B2_Y2_CLK_GATE,
235 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
236 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
237 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
238 else
239 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 240
ea76e635 241 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 242 u32 reg;
5afa0a9c 243
b32f40c4 244 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 245
b32f40c4 246 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 247 /* set all bits to 0 except bits 15..12 and 8 */
248 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 249 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 250
b32f40c4 251 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 252 /* set all bits to 0 except bits 28 & 27 */
253 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 254 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 255
b32f40c4 256 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 257
258 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
259 reg = sky2_read32(hw, B2_GP_IO);
260 reg |= GLB_GPIO_STAT_RACE_DIS;
261 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 262
263 sky2_read32(hw, B2_GP_IO);
5afa0a9c 264 }
ae306cca 265}
5afa0a9c 266
ae306cca
SH		 267static void sky2_power_aux(struct sky2_hw *hw)
268{
269 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
270 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
271 else
272 /* enable bits are inverted */
273 sky2_write8(hw, B2_Y2_CLK_GATE,
274 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
275 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
276 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
277
278 /* switch power to VAUX */
279 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
280 sky2_write8(hw, B0_POWER_CTRL,
281 (PC_VAUX_ENA | PC_VCC_ENA |
282 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 283}
284
d3bcfbeb 285static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 286{
287 u16 reg;
288
289 /* disable all GMAC IRQ's */
290 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 291
cd28ab6a
SH		 292 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
293 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
296
297 reg = gma_read16(hw, port, GM_RX_CTRL);
298 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
299 gma_write16(hw, port, GM_RX_CTRL, reg);
300}
301
16ad91e1
SH		 302/* flow control to advertise bits */
303static const u16 copper_fc_adv[] = {
304 [FC_NONE] = 0,
305 [FC_TX] = PHY_M_AN_ASP,
306 [FC_RX] = PHY_M_AN_PC,
307 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
308};
309
310/* flow control to advertise bits when using 1000BaseX */
311static const u16 fiber_fc_adv[] = {
df3fe1f3 312 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 313 [FC_TX] = PHY_M_P_ASYM_MD_X,
314 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 315 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 316};
317
318/* flow control to GMA disable bits */
319static const u16 gm_fc_disable[] = {
320 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
321 [FC_TX] = GM_GPCR_FC_RX_DIS,
322 [FC_RX] = GM_GPCR_FC_TX_DIS,
323 [FC_BOTH] = 0,
324};
325
326
cd28ab6a
SH		 327static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
328{
329 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 330 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 331
ea76e635
SH		 332 if (sky2->autoneg == AUTONEG_ENABLE &&
333 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 334 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
335
336 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 337 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 338 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
339
53419c68 340 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 341 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 342 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 343 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
344 else
53419c68
SH		 345 /* set master & slave downshift counter to 1x */
346 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 347
348 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
349 }
350
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 352 if (sky2_is_copper(hw)) {
05745c4a 353 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 354 /* enable automatic crossover */
355 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 356
357 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
358 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
359 u16 spec;
360
361 /* Enable Class A driver for FE+ A0 */
362 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
363 spec |= PHY_M_FESC_SEL_CL_A;
364 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
365 }
cd28ab6a
SH		 366 } else {
367 /* disable energy detect */
368 ctrl &= ~PHY_M_PC_EN_DET_MSK;
369
370 /* enable automatic crossover */
371 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
372
53419c68 373 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 374 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 375 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 376 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 377 ctrl &= ~PHY_M_PC_DSC_MSK;
378 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
379 }
380 }
cd28ab6a
SH		 381 } else {
382 /* workaround for deviation #4.88 (CRC errors) */
383 /* disable Automatic Crossover */
384
385 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 386 }
cd28ab6a 387
b89165f2
SH		 388 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
389
390 /* special setup for PHY 88E1112 Fiber */
ea76e635 391 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 392 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 393
b89165f2
SH		 394 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
396 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
397 ctrl &= ~PHY_M_MAC_MD_MSK;
398 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
399 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
400
401 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 402 /* select page 1 to access Fiber registers */
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 404
405 /* for SFP-module set SIGDET polarity to low */
406 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
407 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 408 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 409 }
b89165f2
SH		 410
411 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 412 }
413
7800fddc 414 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 415 ct1000 = 0;
416 adv = PHY_AN_CSMA;
2eaba1a2 417 reg = 0;
cd28ab6a
SH		 418
419 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 420 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 421 if (sky2->advertising & ADVERTISED_1000baseT_Full)
422 ct1000 |= PHY_M_1000C_AFD;
423 if (sky2->advertising & ADVERTISED_1000baseT_Half)
424 ct1000 |= PHY_M_1000C_AHD;
425 if (sky2->advertising & ADVERTISED_100baseT_Full)
426 adv |= PHY_M_AN_100_FD;
427 if (sky2->advertising & ADVERTISED_100baseT_Half)
428 adv |= PHY_M_AN_100_HD;
429 if (sky2->advertising & ADVERTISED_10baseT_Full)
430 adv |= PHY_M_AN_10_FD;
431 if (sky2->advertising & ADVERTISED_10baseT_Half)
432 adv |= PHY_M_AN_10_HD;
709c6e7b 433
16ad91e1 434 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 435 } else { /* special defines for FIBER (88E1040S only) */
436 if (sky2->advertising & ADVERTISED_1000baseT_Full)
437 adv |= PHY_M_AN_1000X_AFD;
438 if (sky2->advertising & ADVERTISED_1000baseT_Half)
439 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 440
16ad91e1 441 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 442 }
cd28ab6a
SH		 443
444 /* Restart Auto-negotiation */
445 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
446 } else {
447 /* forced speed/duplex settings */
448 ct1000 = PHY_M_1000C_MSE;
449
2eaba1a2
SH		 450 /* Disable auto update for duplex flow control and speed */
451 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 452
453 switch (sky2->speed) {
454 case SPEED_1000:
455 ctrl |= PHY_CT_SP1000;
2eaba1a2 456 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 457 break;
458 case SPEED_100:
459 ctrl |= PHY_CT_SP100;
2eaba1a2 460 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 461 break;
462 }
463
2eaba1a2
SH		 464 if (sky2->duplex == DUPLEX_FULL) {
465 reg |= GM_GPCR_DUP_FULL;
466 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 467 } else if (sky2->speed < SPEED_1000)
468 sky2->flow_mode = FC_NONE;
2eaba1a2 469
2eaba1a2 470
16ad91e1 471 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 472
473 /* Forward pause packets to GMAC? */
16ad91e1 474 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 475 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
476 else
477 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 478 }
479
2eaba1a2
SH		 480 gma_write16(hw, port, GM_GP_CTRL, reg);
481
05745c4a 482 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 483 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
484
485 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
486 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
487
488 /* Setup Phy LED's */
489 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
490 ledover = 0;
491
492 switch (hw->chip_id) {
493 case CHIP_ID_YUKON_FE:
494 /* on 88E3082 these bits are at 11..9 (shifted left) */
495 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
496
497 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
498
499 /* delete ACT LED control bits */
500 ctrl &= ~PHY_M_FELP_LED1_MSK;
501 /* change ACT LED control to blink mode */
502 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
503 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
504 break;
505
05745c4a
SH		 506 case CHIP_ID_YUKON_FE_P:
507 /* Enable Link Partner Next Page */
508 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
509 ctrl |= PHY_M_PC_ENA_LIP_NP;
510
511 /* disable Energy Detect and enable scrambler */
512 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
513 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
514
515 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
516 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
517 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
518 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
519
520 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
521 break;
522
cd28ab6a 523 case CHIP_ID_YUKON_XL:
793b883e 524 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 525
526 /* select page 3 to access LED control register */
527 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
528
529 /* set LED Function Control register */
ed6d32c7
SH		 530 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
531 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
532 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
533 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
534 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 535
536 /* set Polarity Control register */
537 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 538 (PHY_M_POLC_LS1_P_MIX(4) |
539 PHY_M_POLC_IS0_P_MIX(4) |
540 PHY_M_POLC_LOS_CTRL(2) |
541 PHY_M_POLC_INIT_CTRL(2) |
542 PHY_M_POLC_STA1_CTRL(2) |
543 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 544
545 /* restore page register */
793b883e 546 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 547 break;
93745494 548
ed6d32c7 549 case CHIP_ID_YUKON_EC_U:
93745494 550 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 551 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
552
553 /* select page 3 to access LED control register */
554 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
555
556 /* set LED Function Control register */
557 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
558 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
559 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
560 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
561 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
562
563 /* set Blink Rate in LED Timer Control Register */
564 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
565 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
566 /* restore page register */
567 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
568 break;
cd28ab6a
SH		 569
570 default:
571 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
572 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
573 /* turn off the Rx LED (LED_RX) */
0efdf262 574 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 575 }
576
9467a8fc
SH		 577 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
578 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 579 /* apply fixes in PHY AFE */
ed6d32c7
SH		 580 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
581
977bdf06 582 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 583 gm_phy_write(hw, port, 0x18, 0xaa99);
584 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 585
977bdf06 586 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 587 gm_phy_write(hw, port, 0x18, 0xa204);
588 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 589
590 /* set page register to 0 */
9467a8fc 591 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 592 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
593 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
594 /* apply workaround for integrated resistors calibration */
595 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
596 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 597 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 598 /* no effect on Yukon-XL */
977bdf06 599 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 600
977bdf06
SH		 601 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
602 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 603 ledover |= PHY_M_LED_MO_100;
977bdf06 604 }
cd28ab6a 605
977bdf06
SH		 606 if (ledover)
607 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
608
609 }
2eaba1a2 610
d571b694 611 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 612 if (sky2->autoneg == AUTONEG_ENABLE)
613 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
614 else
615 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
616}
617
d3bcfbeb
SH		 618static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
619{
620 u32 reg1;
ff35164e
SH		 621 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
622 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
d3bcfbeb 623
b32f40c4 624 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
ff35164e 625 /* Turn on/off phy power saving */
d3bcfbeb 626 if (onoff)
d3bcfbeb
SH		 627 reg1 &= ~phy_power[port];
628 else
629 reg1 |= phy_power[port];
630
ff35164e
SH		 631 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
632 reg1 |= coma_mode[port];
633
b32f40c4
SH		 634 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
635 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
167f53d0 636
d3bcfbeb
SH		 637 udelay(100);
638}
639
1b537565
SH		 640/* Force a renegotiation */
641static void sky2_phy_reinit(struct sky2_port *sky2)
642{
e07b1aa8 643 spin_lock_bh(&sky2->phy_lock);
1b537565 644 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 645 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 646}
647
e3173832
SH		 648/* Put device in state to listen for Wake On Lan */
649static void sky2_wol_init(struct sky2_port *sky2)
650{
651 struct sky2_hw *hw = sky2->hw;
652 unsigned port = sky2->port;
653 enum flow_control save_mode;
654 u16 ctrl;
655 u32 reg1;
656
657 /* Bring hardware out of reset */
658 sky2_write16(hw, B0_CTST, CS_RST_CLR);
659 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
660
661 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
662 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
663
664 /* Force to 10/100
665 * sky2_reset will re-enable on resume
666 */
667 save_mode = sky2->flow_mode;
668 ctrl = sky2->advertising;
669
670 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
671 sky2->flow_mode = FC_NONE;
672 sky2_phy_power(hw, port, 1);
673 sky2_phy_reinit(sky2);
674
675 sky2->flow_mode = save_mode;
676 sky2->advertising = ctrl;
677
678 /* Set GMAC to no flow control and auto update for speed/duplex */
679 gma_write16(hw, port, GM_GP_CTRL,
680 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
681 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
682
683 /* Set WOL address */
684 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
685 sky2->netdev->dev_addr, ETH_ALEN);
686
687 /* Turn on appropriate WOL control bits */
688 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
689 ctrl = 0;
690 if (sky2->wol & WAKE_PHY)
691 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
692 else
693 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
694
695 if (sky2->wol & WAKE_MAGIC)
696 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
697 else
698 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
699
700 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
701 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
702
703 /* Turn on legacy PCI-Express PME mode */
b32f40c4 704 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 705 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 706 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 707
708 /* block receiver */
709 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
710
711}
712
69161611
SH		 713static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
714{
05745c4a
SH		 715 struct net_device *dev = hw->dev[port];
716
717 if (dev->mtu <= ETH_DATA_LEN)
69161611 718 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
05745c4a
SH		 719 TX_JUMBO_DIS | TX_STFW_ENA);
720
721 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
722 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
723 TX_STFW_ENA | TX_JUMBO_ENA);
724 else {
725 /* set Tx GMAC FIFO Almost Empty Threshold */
726 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
727 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 728
05745c4a
SH		 729 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
730 TX_JUMBO_ENA | TX_STFW_DIS);
69161611 731
05745c4a
SH		 732 /* Can't do offload because of lack of store/forward */
733 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
69161611
SH		 734 }
735}
736
cd28ab6a
SH		 737static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
738{
739 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
740 u16 reg;
25cccecc 741 u32 rx_reg;
cd28ab6a
SH		 742 int i;
743 const u8 *addr = hw->dev[port]->dev_addr;
744
f350339c
SH		 745 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
746 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 747
748 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
749
793b883e 750 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 751 /* WA DEV_472 -- looks like crossed wires on port 2 */
752 /* clear GMAC 1 Control reset */
753 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
754 do {
755 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
756 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
757 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
758 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
759 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
760 }
761
793b883e 762 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 763
2eaba1a2
SH		 764 /* Enable Transmit FIFO Underrun */
765 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
766
e07b1aa8 767 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 768 sky2_phy_init(hw, port);
e07b1aa8 769 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 770
771 /* MIB clear */
772 reg = gma_read16(hw, port, GM_PHY_ADDR);
773 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
774
43f2f104
SH		 775 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
776 gma_read16(hw, port, i);
cd28ab6a
SH		 777 gma_write16(hw, port, GM_PHY_ADDR, reg);
778
779 /* transmit control */
780 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
781
782 /* receive control reg: unicast + multicast + no FCS */
783 gma_write16(hw, port, GM_RX_CTRL,
793b883e 784 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 785
786 /* transmit flow control */
787 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
788
789 /* transmit parameter */
790 gma_write16(hw, port, GM_TX_PARAM,
791 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
792 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
793 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
794 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
795
796 /* serial mode register */
797 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 798 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 799
6b1a3aef 800 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 801 reg |= GM_SMOD_JUMBO_ENA;
802
803 gma_write16(hw, port, GM_SERIAL_MODE, reg);
804
cd28ab6a
SH		 805 /* virtual address for data */
806 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
807
793b883e
SH		 808 /* physical address: used for pause frames */
809 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
810
811 /* ignore counter overflows */
cd28ab6a
SH		 812 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
813 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
814 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
815
816 /* Configure Rx MAC FIFO */
817 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 818 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 819 if (hw->chip_id == CHIP_ID_YUKON_EX ||
820 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 821 rx_reg |= GMF_RX_OVER_ON;
69161611 822
25cccecc 823 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 824
d571b694 825 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 826 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 827
8df9a876 828 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 829 reg = RX_GMF_FL_THR_DEF + 1;
830 /* Another magic mystery workaround from sk98lin */
831 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
832 hw->chip_rev == CHIP_REV_YU_FE2_A0)
833 reg = 0x178;
834 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 835
836 /* Configure Tx MAC FIFO */
837 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
838 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 839
e0c28116
SH		 840 /* On chips without ram buffer, pause is controled by MAC level */
841 if (sky2_read8(hw, B2_E_0) == 0) {
8df9a876 842 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 843 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 844
69161611 845 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 846 }
847
e970d1f8
SH		 848 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
849 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
850 /* disable dynamic watermark */
851 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
852 reg &= ~TX_DYN_WM_ENA;
853 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
854 }
cd28ab6a
SH		 855}
856
67712901
SH		 857/* Assign Ram Buffer allocation to queue */
858static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 859{
67712901
SH		 860 u32 end;
861
862 /* convert from K bytes to qwords used for hw register */
863 start *= 1024/8;
864 space *= 1024/8;
865 end = start + space - 1;
793b883e 866
cd28ab6a
SH		 867 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
868 sky2_write32(hw, RB_ADDR(q, RB_START), start);
869 sky2_write32(hw, RB_ADDR(q, RB_END), end);
870 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
871 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
872
873 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 874 u32 tp = space - space/4;
793b883e 875
1c28f6ba
SH		 876 /* On receive queue's set the thresholds
877 * give receiver priority when > 3/4 full
878 * send pause when down to 2K
879 */
880 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
881 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 882
1c28f6ba
SH		 883 tp = space - 2048/8;
884 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
885 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 886 } else {
887 /* Enable store & forward on Tx queue's because
888 * Tx FIFO is only 1K on Yukon
889 */
890 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
891 }
892
893 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 894 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 895}
896
cd28ab6a 897/* Setup Bus Memory Interface */
af4ed7e6 898static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 899{
900 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
901 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
902 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 903 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 904}
905
cd28ab6a
SH		 906/* Setup prefetch unit registers. This is the interface between
907 * hardware and driver list elements
908 */
8cc048e3 909static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 910 u64 addr, u32 last)
911{
cd28ab6a
SH		 912 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
913 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
914 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
915 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
916 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
917 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 918
919 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 920}
921
793b883e
SH		 922static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
923{
924 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
925
cb5d9547 926 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 927 le->ctrl = 0;
793b883e
SH		 928 return le;
929}
cd28ab6a 930
88f5f0ca
SH		 931static void tx_init(struct sky2_port *sky2)
932{
933 struct sky2_tx_le *le;
934
935 sky2->tx_prod = sky2->tx_cons = 0;
936 sky2->tx_tcpsum = 0;
937 sky2->tx_last_mss = 0;
938
939 le = get_tx_le(sky2);
940 le->addr = 0;
941 le->opcode = OP_ADDR64 | HW_OWNER;
942 sky2->tx_addr64 = 0;
943}
944
291ea614
SH		 945static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
946 struct sky2_tx_le *le)
947{
948 return sky2->tx_ring + (le - sky2->tx_le);
949}
950
290d4de5
SH		 951/* Update chip's next pointer */
952static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 953{
50432cb5 954 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 955 wmb();
50432cb5
SH		 956 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
957
958 /* Synchronize I/O on since next processor may write to tail */
959 mmiowb();
cd28ab6a
SH		 960}
961
793b883e 962
cd28ab6a
SH		 963static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
964{
965 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 966 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 967 le->ctrl = 0;
cd28ab6a
SH		 968 return le;
969}
970
14d0263f
SH		 971/* Build description to hardware for one receive segment */
972static void sky2_rx_add(struct sky2_port *sky2, u8 op,
973 dma_addr_t map, unsigned len)
cd28ab6a
SH		 974{
975 struct sky2_rx_le *le;
36eb0c71 976 u32 hi = upper_32_bits(map);
cd28ab6a 977
793b883e 978 if (sky2->rx_addr64 != hi) {
cd28ab6a 979 le = sky2_next_rx(sky2);
793b883e 980 le->addr = cpu_to_le32(hi);
cd28ab6a 981 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 982 sky2->rx_addr64 = upper_32_bits(map + len);
cd28ab6a 983 }
793b883e 984
cd28ab6a 985 le = sky2_next_rx(sky2);
734d1868
SH		 986 le->addr = cpu_to_le32((u32) map);
987 le->length = cpu_to_le16(len);
14d0263f 988 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 989}
990
14d0263f
SH		 991/* Build description to hardware for one possibly fragmented skb */
992static void sky2_rx_submit(struct sky2_port *sky2,
993 const struct rx_ring_info *re)
994{
995 int i;
996
997 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
998
999 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1000 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1001}
1002
1003
1004static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1005 unsigned size)
1006{
1007 struct sk_buff *skb = re->skb;
1008 int i;
1009
1010 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1011 pci_unmap_len_set(re, data_size, size);
1012
1013 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1014 re->frag_addr[i] = pci_map_page(pdev,
1015 skb_shinfo(skb)->frags[i].page,
1016 skb_shinfo(skb)->frags[i].page_offset,
1017 skb_shinfo(skb)->frags[i].size,
1018 PCI_DMA_FROMDEVICE);
1019}
1020
1021static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1022{
1023 struct sk_buff *skb = re->skb;
1024 int i;
1025
1026 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1027 PCI_DMA_FROMDEVICE);
1028
1029 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1030 pci_unmap_page(pdev, re->frag_addr[i],
1031 skb_shinfo(skb)->frags[i].size,
1032 PCI_DMA_FROMDEVICE);
1033}
793b883e 1034
cd28ab6a
SH		 1035/* Tell chip where to start receive checksum.
1036 * Actually has two checksums, but set both same to avoid possible byte
1037 * order problems.
1038 */
793b883e 1039static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1040{
ea76e635 1041 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1042
ea76e635
SH		 1043 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1044 le->ctrl = 0;
1045 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1046
ea76e635
SH		 1047 sky2_write32(sky2->hw,
1048 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1049 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1050}
1051
6b1a3aef
SH		 1052/*
1053 * The RX Stop command will not work for Yukon-2 if the BMU does not
1054 * reach the end of packet and since we can't make sure that we have
1055 * incoming data, we must reset the BMU while it is not doing a DMA
1056 * transfer. Since it is possible that the RX path is still active,
1057 * the RX RAM buffer will be stopped first, so any possible incoming
1058 * data will not trigger a DMA. After the RAM buffer is stopped, the
1059 * BMU is polled until any DMA in progress is ended and only then it
1060 * will be reset.
1061 */
1062static void sky2_rx_stop(struct sky2_port *sky2)
1063{
1064 struct sky2_hw *hw = sky2->hw;
1065 unsigned rxq = rxqaddr[sky2->port];
1066 int i;
1067
1068 /* disable the RAM Buffer receive queue */
1069 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1070
1071 for (i = 0; i < 0xffff; i++)
1072 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1073 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1074 goto stopped;
1075
1076 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1077 sky2->netdev->name);
1078stopped:
1079 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1080
1081 /* reset the Rx prefetch unit */
1082 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1083 mmiowb();
6b1a3aef 1084}
793b883e 1085
d571b694 1086/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1087static void sky2_rx_clean(struct sky2_port *sky2)
1088{
1089 unsigned i;
1090
1091 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1092 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1093 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1094
1095 if (re->skb) {
14d0263f 1096 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1097 kfree_skb(re->skb);
1098 re->skb = NULL;
1099 }
1100 }
1101}
1102
ef743d33
SH		 1103/* Basic MII support */
1104static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1105{
1106 struct mii_ioctl_data *data = if_mii(ifr);
1107 struct sky2_port *sky2 = netdev_priv(dev);
1108 struct sky2_hw *hw = sky2->hw;
1109 int err = -EOPNOTSUPP;
1110
1111 if (!netif_running(dev))
1112 return -ENODEV; /* Phy still in reset */
1113
d89e1343 1114 switch (cmd) {
ef743d33
SH		 1115 case SIOCGMIIPHY:
1116 data->phy_id = PHY_ADDR_MARV;
1117
1118 /* fallthru */
1119 case SIOCGMIIREG: {
1120 u16 val = 0;
91c86df5 1121
e07b1aa8 1122 spin_lock_bh(&sky2->phy_lock);
ef743d33 1123 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1124 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1125
ef743d33
SH		 1126 data->val_out = val;
1127 break;
1128 }
1129
1130 case SIOCSMIIREG:
1131 if (!capable(CAP_NET_ADMIN))
1132 return -EPERM;
1133
e07b1aa8 1134 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1135 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1136 data->val_in);
e07b1aa8 1137 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1138 break;
1139 }
1140 return err;
1141}
1142
d1f13708
SH		 1143#ifdef SKY2_VLAN_TAG_USED
1144static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1145{
1146 struct sky2_port *sky2 = netdev_priv(dev);
1147 struct sky2_hw *hw = sky2->hw;
1148 u16 port = sky2->port;
d1f13708 1149
2bb8c262 1150 netif_tx_lock_bh(dev);
bea3348e 1151 napi_disable(&hw->napi);
d1f13708 1152
d1f13708 1153 sky2->vlgrp = grp;
3d4e66f5
SH		 1154 if (grp) {
1155 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1156 RX_VLAN_STRIP_ON);
1157 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1158 TX_VLAN_TAG_ON);
1159 } else {
1160 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1161 RX_VLAN_STRIP_OFF);
1162 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1163 TX_VLAN_TAG_OFF);
1164 }
d1f13708 1165
bea3348e 1166 napi_enable(&hw->napi);
2bb8c262 1167 netif_tx_unlock_bh(dev);
d1f13708
SH		 1168}
1169#endif
1170
82788c7a 1171/*
14d0263f
SH		 1172 * Allocate an skb for receiving. If the MTU is large enough
1173 * make the skb non-linear with a fragment list of pages.
1174 *
82788c7a
SH		 1175 * It appears the hardware has a bug in the FIFO logic that
1176 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1177 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1178 * aligned except if slab debugging is enabled.
82788c7a 1179 */
14d0263f 1180static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1181{
1182 struct sk_buff *skb;
14d0263f
SH		 1183 unsigned long p;
1184 int i;
82788c7a 1185
14d0263f
SH		 1186 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1187 if (!skb)
1188 goto nomem;
1189
1190 p = (unsigned long) skb->data;
1191 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1192
1193 for (i = 0; i < sky2->rx_nfrags; i++) {
1194 struct page *page = alloc_page(GFP_ATOMIC);
1195
1196 if (!page)
1197 goto free_partial;
1198 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1199 }
1200
1201 return skb;
14d0263f
SH		 1202free_partial:
1203 kfree_skb(skb);
1204nomem:
1205 return NULL;
82788c7a
SH		 1206}
1207
55c9dd35
SH		 1208static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1209{
1210 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1211}
1212
cd28ab6a
SH		 1213/*
1214 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1215 * Normal case this ends up creating one list element for skb
1216 * in the receive ring. Worst case if using large MTU and each
1217 * allocation falls on a different 64 bit region, that results
1218 * in 6 list elements per ring entry.
1219 * One element is used for checksum enable/disable, and one
1220 * extra to avoid wrap.
cd28ab6a 1221 */
6b1a3aef 1222static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1223{
6b1a3aef 1224 struct sky2_hw *hw = sky2->hw;
14d0263f 1225 struct rx_ring_info *re;
6b1a3aef 1226 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1227 unsigned i, size, space, thresh;
cd28ab6a 1228
6b1a3aef 1229 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1230 sky2_qset(hw, rxq);
977bdf06 1231
c3905bc4
SH		 1232 /* On PCI express lowering the watermark gives better performance */
1233 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1234 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1235
1236 /* These chips have no ram buffer?
1237 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1238 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1239 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1240 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1241 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1242
6b1a3aef
SH		 1243 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1244
ea76e635
SH		 1245 if (!(hw->flags & SKY2_HW_NEW_LE))
1246 rx_set_checksum(sky2);
14d0263f
SH		 1247
1248 /* Space needed for frame data + headers rounded up */
f957da2a 1249 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1250
1251 /* Stopping point for hardware truncation */
1252 thresh = (size - 8) / sizeof(u32);
1253
1254 /* Account for overhead of skb - to avoid order > 0 allocation */
1255 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1256 + sizeof(struct skb_shared_info);
1257
1258 sky2->rx_nfrags = space >> PAGE_SHIFT;
1259 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1260
1261 if (sky2->rx_nfrags != 0) {
1262 /* Compute residue after pages */
1263 space = sky2->rx_nfrags << PAGE_SHIFT;
1264
1265 if (space < size)
1266 size -= space;
1267 else
1268 size = 0;
1269
1270 /* Optimize to handle small packets and headers */
1271 if (size < copybreak)
1272 size = copybreak;
1273 if (size < ETH_HLEN)
1274 size = ETH_HLEN;
1275 }
1276 sky2->rx_data_size = size;
1277
1278 /* Fill Rx ring */
793b883e 1279 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1280 re = sky2->rx_ring + i;
cd28ab6a 1281
14d0263f 1282 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1283 if (!re->skb)
1284 goto nomem;
1285
14d0263f
SH		 1286 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1287 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1288 }
1289
a1433ac4
SH		 1290 /*
1291 * The receiver hangs if it receives frames larger than the
1292 * packet buffer. As a workaround, truncate oversize frames, but
1293 * the register is limited to 9 bits, so if you do frames > 2052
1294 * you better get the MTU right!
1295 */
a1433ac4
SH		 1296 if (thresh > 0x1ff)
1297 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1298 else {
1299 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1300 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1301 }
1302
6b1a3aef 1303 /* Tell chip about available buffers */
55c9dd35 1304 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1305 return 0;
1306nomem:
1307 sky2_rx_clean(sky2);
1308 return -ENOMEM;
1309}
1310
1311/* Bring up network interface. */
1312static int sky2_up(struct net_device *dev)
1313{
1314 struct sky2_port *sky2 = netdev_priv(dev);
1315 struct sky2_hw *hw = sky2->hw;
1316 unsigned port = sky2->port;
e0c28116 1317 u32 imask, ramsize;
ee7abb04 1318 int cap, err = -ENOMEM;
843a46f4 1319 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1320
ee7abb04
SH		 1321 /*
1322 * On dual port PCI-X card, there is an problem where status
1323 * can be received out of order due to split transactions
843a46f4 1324 */
ee7abb04
SH		 1325 if (otherdev && netif_running(otherdev) &&
1326 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1327 u16 cmd;
1328
b32f40c4 1329 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1330 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1331 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1332
ee7abb04 1333 }
843a46f4 1334
cd28ab6a
SH		 1335 if (netif_msg_ifup(sky2))
1336 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1337
55d7b4e6
SH		 1338 netif_carrier_off(dev);
1339
cd28ab6a
SH		 1340 /* must be power of 2 */
1341 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1342 TX_RING_SIZE *
1343 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1344 &sky2->tx_le_map);
1345 if (!sky2->tx_le)
1346 goto err_out;
1347
6cdbbdf3 1348 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1349 GFP_KERNEL);
1350 if (!sky2->tx_ring)
1351 goto err_out;
88f5f0ca
SH		 1352
1353 tx_init(sky2);
cd28ab6a
SH		 1354
1355 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1356 &sky2->rx_le_map);
1357 if (!sky2->rx_le)
1358 goto err_out;
1359 memset(sky2->rx_le, 0, RX_LE_BYTES);
1360
291ea614 1361 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1362 GFP_KERNEL);
1363 if (!sky2->rx_ring)
1364 goto err_out;
1365
d3bcfbeb
SH		 1366 sky2_phy_power(hw, port, 1);
1367
cd28ab6a
SH		 1368 sky2_mac_init(hw, port);
1369
e0c28116
SH		 1370 /* Register is number of 4K blocks on internal RAM buffer. */
1371 ramsize = sky2_read8(hw, B2_E_0) * 4;
1372 if (ramsize > 0) {
67712901 1373 u32 rxspace;
cd28ab6a 1374
e0c28116 1375 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1376 if (ramsize < 16)
1377 rxspace = ramsize / 2;
1378 else
1379 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1380
67712901
SH		 1381 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1382 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1383
1384 /* Make sure SyncQ is disabled */
1385 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1386 RB_RST_SET);
1387 }
793b883e 1388
af4ed7e6 1389 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1390
69161611
SH		 1391 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1392 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1393 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1394
977bdf06 1395 /* Set almost empty threshold */
c2716fb4
SH		 1396 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1397 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1398 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1399
6b1a3aef
SH		 1400 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1401 TX_RING_SIZE - 1);
cd28ab6a 1402
6b1a3aef 1403 err = sky2_rx_start(sky2);
6de16237 1404 if (err)
cd28ab6a
SH		 1405 goto err_out;
1406
cd28ab6a 1407 /* Enable interrupts from phy/mac for port */
e07b1aa8 1408 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1409 imask |= portirq_msk[port];
e07b1aa8
SH		 1410 sky2_write32(hw, B0_IMSK, imask);
1411
cd28ab6a
SH		 1412 return 0;
1413
1414err_out:
1b537565 1415 if (sky2->rx_le) {
cd28ab6a
SH		 1416 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1417 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1418 sky2->rx_le = NULL;
1419 }
1420 if (sky2->tx_le) {
cd28ab6a
SH		 1421 pci_free_consistent(hw->pdev,
1422 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1423 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1424 sky2->tx_le = NULL;
1425 }
1426 kfree(sky2->tx_ring);
1427 kfree(sky2->rx_ring);
cd28ab6a 1428
1b537565
SH		 1429 sky2->tx_ring = NULL;
1430 sky2->rx_ring = NULL;
cd28ab6a
SH		 1431 return err;
1432}
1433
793b883e
SH		 1434/* Modular subtraction in ring */
1435static inline int tx_dist(unsigned tail, unsigned head)
1436{
cb5d9547 1437 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1438}
cd28ab6a 1439
793b883e
SH		 1440/* Number of list elements available for next tx */
1441static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1442{
793b883e 1443 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1444}
1445
793b883e 1446/* Estimate of number of transmit list elements required */
28bd181a 1447static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1448{
793b883e
SH		 1449 unsigned count;
1450
1451 count = sizeof(dma_addr_t) / sizeof(u32);
1452 count += skb_shinfo(skb)->nr_frags * count;
1453
89114afd 1454 if (skb_is_gso(skb))
793b883e
SH		 1455 ++count;
1456
84fa7933 1457 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1458 ++count;
1459
1460 return count;
cd28ab6a
SH		 1461}
1462
793b883e
SH		 1463/*
1464 * Put one packet in ring for transmit.
1465 * A single packet can generate multiple list elements, and
1466 * the number of ring elements will probably be less than the number
1467 * of list elements used.
1468 */
cd28ab6a
SH		 1469static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1470{
1471 struct sky2_port *sky2 = netdev_priv(dev);
1472 struct sky2_hw *hw = sky2->hw;
d1f13708 1473 struct sky2_tx_le *le = NULL;
6cdbbdf3 1474 struct tx_ring_info *re;
cd28ab6a
SH		 1475 unsigned i, len;
1476 dma_addr_t mapping;
1477 u32 addr64;
1478 u16 mss;
1479 u8 ctrl;
1480
2bb8c262
SH		 1481 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1482 return NETDEV_TX_BUSY;
cd28ab6a 1483
793b883e 1484 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1485 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1486 dev->name, sky2->tx_prod, skb->len);
1487
cd28ab6a
SH		 1488 len = skb_headlen(skb);
1489 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
36eb0c71 1490 addr64 = upper_32_bits(mapping);
793b883e 1491
a018e330 1492 /* Send high bits if changed or crosses boundary */
36eb0c71
SH		 1493 if (addr64 != sky2->tx_addr64 ||
1494 upper_32_bits(mapping + len) != sky2->tx_addr64) {
793b883e 1495 le = get_tx_le(sky2);
f65b138c 1496 le->addr = cpu_to_le32(addr64);
793b883e 1497 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 1498 sky2->tx_addr64 = upper_32_bits(mapping + len);
793b883e 1499 }
cd28ab6a
SH		 1500
1501 /* Check for TCP Segmentation Offload */
7967168c 1502 mss = skb_shinfo(skb)->gso_size;
793b883e 1503 if (mss != 0) {
ea76e635
SH		 1504
1505 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1506 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1507
1508 if (mss != sky2->tx_last_mss) {
1509 le = get_tx_le(sky2);
1510 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1511
1512 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1513 le->opcode = OP_MSS | HW_OWNER;
1514 else
1515 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1516 sky2->tx_last_mss = mss;
1517 }
cd28ab6a
SH		 1518 }
1519
cd28ab6a 1520 ctrl = 0;
d1f13708
SH		 1521#ifdef SKY2_VLAN_TAG_USED
1522 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1523 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1524 if (!le) {
1525 le = get_tx_le(sky2);
f65b138c 1526 le->addr = 0;
d1f13708 1527 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1528 } else
1529 le->opcode |= OP_VLAN;
1530 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1531 ctrl |= INS_VLAN;
1532 }
1533#endif
1534
1535 /* Handle TCP checksum offload */
84fa7933 1536 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1537 /* On Yukon EX (some versions) encoding change. */
ea76e635 1538 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1539 ctrl |= CALSUM; /* auto checksum */
1540 else {
1541 const unsigned offset = skb_transport_offset(skb);
1542 u32 tcpsum;
1543
1544 tcpsum = offset << 16; /* sum start */
1545 tcpsum |= offset + skb->csum_offset; /* sum write */
1546
1547 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1548 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1549 ctrl |= UDPTCP;
1550
1551 if (tcpsum != sky2->tx_tcpsum) {
1552 sky2->tx_tcpsum = tcpsum;
1553
1554 le = get_tx_le(sky2);
1555 le->addr = cpu_to_le32(tcpsum);
1556 le->length = 0; /* initial checksum value */
1557 le->ctrl = 1; /* one packet */
1558 le->opcode = OP_TCPLISW | HW_OWNER;
1559 }
1d179332 1560 }
cd28ab6a
SH		 1561 }
1562
1563 le = get_tx_le(sky2);
f65b138c 1564 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1565 le->length = cpu_to_le16(len);
1566 le->ctrl = ctrl;
793b883e 1567 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1568
291ea614 1569 re = tx_le_re(sky2, le);
cd28ab6a 1570 re->skb = skb;
6cdbbdf3 1571 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1572 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1573
1574 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1575 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1576
1577 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1578 frag->size, PCI_DMA_TODEVICE);
36eb0c71 1579 addr64 = upper_32_bits(mapping);
793b883e
SH		 1580 if (addr64 != sky2->tx_addr64) {
1581 le = get_tx_le(sky2);
f65b138c 1582 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1583 le->ctrl = 0;
1584 le->opcode = OP_ADDR64 | HW_OWNER;
1585 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1586 }
1587
1588 le = get_tx_le(sky2);
f65b138c 1589 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1590 le->length = cpu_to_le16(frag->size);
1591 le->ctrl = ctrl;
793b883e 1592 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1593
291ea614
SH		 1594 re = tx_le_re(sky2, le);
1595 re->skb = skb;
1596 pci_unmap_addr_set(re, mapaddr, mapping);
1597 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1598 }
6cdbbdf3 1599
cd28ab6a
SH		 1600 le->ctrl |= EOP;
1601
97bda706
SH		 1602 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1603 netif_stop_queue(dev);
b19666d9 1604
290d4de5 1605 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1606
cd28ab6a
SH		 1607 dev->trans_start = jiffies;
1608 return NETDEV_TX_OK;
1609}
1610
cd28ab6a 1611/*
793b883e
SH		 1612 * Free ring elements from starting at tx_cons until "done"
1613 *
1614 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1615 * buffers so make sure not to free skb to early.
cd28ab6a 1616 */
d11c13e7 1617static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1618{
d11c13e7 1619 struct net_device *dev = sky2->netdev;
af2a58ac 1620 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1621 unsigned idx;
cd28ab6a 1622
0e3ff6aa 1623 BUG_ON(done >= TX_RING_SIZE);
2224795d 1624
291ea614
SH		 1625 for (idx = sky2->tx_cons; idx != done;
1626 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1627 struct sky2_tx_le *le = sky2->tx_le + idx;
1628 struct tx_ring_info *re = sky2->tx_ring + idx;
1629
1630 switch(le->opcode & ~HW_OWNER) {
1631 case OP_LARGESEND:
1632 case OP_PACKET:
1633 pci_unmap_single(pdev,
1634 pci_unmap_addr(re, mapaddr),
1635 pci_unmap_len(re, maplen),
1636 PCI_DMA_TODEVICE);
af2a58ac 1637 break;
291ea614
SH		 1638 case OP_BUFFER:
1639 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1640 pci_unmap_len(re, maplen),
734d1868 1641 PCI_DMA_TODEVICE);
291ea614
SH		 1642 break;
1643 }
1644
1645 if (le->ctrl & EOP) {
1646 if (unlikely(netif_msg_tx_done(sky2)))
1647 printk(KERN_DEBUG "%s: tx done %u\n",
1648 dev->name, idx);
3cf26753 1649
7138a0f5
SH		 1650 dev->stats.tx_packets++;
1651 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1652
794b2bd2 1653 dev_kfree_skb_any(re->skb);
3cf26753 1654 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1655 }
793b883e 1656 }
793b883e 1657
291ea614 1658 sky2->tx_cons = idx;
50432cb5
SH		 1659 smp_mb();
1660
22e11703 1661 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1662 netif_wake_queue(dev);
cd28ab6a
SH		 1663}
1664
1665/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1666static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1667{
2bb8c262
SH		 1668 struct sky2_port *sky2 = netdev_priv(dev);
1669
1670 netif_tx_lock_bh(dev);
d11c13e7 1671 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1672 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1673}
1674
1675/* Network shutdown */
1676static int sky2_down(struct net_device *dev)
1677{
1678 struct sky2_port *sky2 = netdev_priv(dev);
1679 struct sky2_hw *hw = sky2->hw;
1680 unsigned port = sky2->port;
1681 u16 ctrl;
e07b1aa8 1682 u32 imask;
cd28ab6a 1683
1b537565
SH		 1684 /* Never really got started! */
1685 if (!sky2->tx_le)
1686 return 0;
1687
cd28ab6a
SH		 1688 if (netif_msg_ifdown(sky2))
1689 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1690
018d1c66 1691 /* Stop more packets from being queued */
cd28ab6a
SH		 1692 netif_stop_queue(dev);
1693
ebc646f6
SH		 1694 /* Disable port IRQ */
1695 imask = sky2_read32(hw, B0_IMSK);
1696 imask &= ~portirq_msk[port];
1697 sky2_write32(hw, B0_IMSK, imask);
1698
6de16237
SH		 1699 synchronize_irq(hw->pdev->irq);
1700
d3bcfbeb 1701 sky2_gmac_reset(hw, port);
793b883e 1702
cd28ab6a
SH		 1703 /* Stop transmitter */
1704 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1705 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1706
1707 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1708 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1709
1710 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1711 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1712 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1713
6de16237
SH		 1714 /* Make sure no packets are pending */
1715 napi_synchronize(&hw->napi);
1716
cd28ab6a
SH		 1717 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1718
1719 /* Workaround shared GMAC reset */
793b883e
SH		 1720 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1721 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1722 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1723
1724 /* Disable Force Sync bit and Enable Alloc bit */
1725 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1726 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1727
1728 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1729 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1730 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1731
1732 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1733 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1734 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1735
1736 /* Reset the Tx prefetch units */
1737 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1738 PREF_UNIT_RST_SET);
1739
1740 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1741
6b1a3aef 1742 sky2_rx_stop(sky2);
cd28ab6a
SH		 1743
1744 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1745 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1746
d3bcfbeb
SH		 1747 sky2_phy_power(hw, port, 0);
1748
55d7b4e6
SH		 1749 netif_carrier_off(dev);
1750
d571b694 1751 /* turn off LED's */
cd28ab6a
SH		 1752 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1753
2bb8c262 1754 sky2_tx_clean(dev);
cd28ab6a
SH		 1755 sky2_rx_clean(sky2);
1756
1757 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1758 sky2->rx_le, sky2->rx_le_map);
1759 kfree(sky2->rx_ring);
1760
1761 pci_free_consistent(hw->pdev,
1762 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1763 sky2->tx_le, sky2->tx_le_map);
1764 kfree(sky2->tx_ring);
1765
1b537565
SH		 1766 sky2->tx_le = NULL;
1767 sky2->rx_le = NULL;
1768
1769 sky2->rx_ring = NULL;
1770 sky2->tx_ring = NULL;
1771
cd28ab6a
SH		 1772 return 0;
1773}
1774
1775static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1776{
ea76e635 1777 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1778 return SPEED_1000;
1779
05745c4a
SH		 1780 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1781 if (aux & PHY_M_PS_SPEED_100)
1782 return SPEED_100;
1783 else
1784 return SPEED_10;
1785 }
cd28ab6a
SH		 1786
1787 switch (aux & PHY_M_PS_SPEED_MSK) {
1788 case PHY_M_PS_SPEED_1000:
1789 return SPEED_1000;
1790 case PHY_M_PS_SPEED_100:
1791 return SPEED_100;
1792 default:
1793 return SPEED_10;
1794 }
1795}
1796
1797static void sky2_link_up(struct sky2_port *sky2)
1798{
1799 struct sky2_hw *hw = sky2->hw;
1800 unsigned port = sky2->port;
1801 u16 reg;
16ad91e1
SH		 1802 static const char *fc_name[] = {
1803 [FC_NONE] = "none",
1804 [FC_TX] = "tx",
1805 [FC_RX] = "rx",
1806 [FC_BOTH] = "both",
1807 };
cd28ab6a 1808
cd28ab6a 1809 /* enable Rx/Tx */
2eaba1a2 1810 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1811 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1812 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1813
1814 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1815
1816 netif_carrier_on(sky2->netdev);
cd28ab6a 1817
75e80683 1818 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1819
cd28ab6a 1820 /* Turn on link LED */
793b883e 1821 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1822 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1823
1824 if (netif_msg_link(sky2))
1825 printk(KERN_INFO PFX
d571b694 1826 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1827 sky2->netdev->name, sky2->speed,
1828 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1829 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1830}
1831
1832static void sky2_link_down(struct sky2_port *sky2)
1833{
1834 struct sky2_hw *hw = sky2->hw;
1835 unsigned port = sky2->port;
1836 u16 reg;
1837
1838 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1839
1840 reg = gma_read16(hw, port, GM_GP_CTRL);
1841 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1842 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1843
cd28ab6a 1844 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1845
1846 /* Turn on link LED */
1847 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1848
1849 if (netif_msg_link(sky2))
1850 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1851
cd28ab6a
SH		 1852 sky2_phy_init(hw, port);
1853}
1854
16ad91e1
SH		 1855static enum flow_control sky2_flow(int rx, int tx)
1856{
1857 if (rx)
1858 return tx ? FC_BOTH : FC_RX;
1859 else
1860 return tx ? FC_TX : FC_NONE;
1861}
1862
793b883e
SH		 1863static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1864{
1865 struct sky2_hw *hw = sky2->hw;
1866 unsigned port = sky2->port;
da4c1ff4 1867 u16 advert, lpa;
793b883e 1868
da4c1ff4 1869 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1870 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1871 if (lpa & PHY_M_AN_RF) {
1872 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1873 return -1;
1874 }
1875
793b883e
SH		 1876 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1877 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1878 sky2->netdev->name);
1879 return -1;
1880 }
1881
793b883e 1882 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1883 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1884
da4c1ff4
SH		 1885 /* Since the pause result bits seem to in different positions on
1886 * different chips. look at registers.
1887 */
ea76e635 1888 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1889 /* Shift for bits in fiber PHY */
1890 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1891 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1892
1893 if (advert & ADVERTISE_1000XPAUSE)
1894 advert |= ADVERTISE_PAUSE_CAP;
1895 if (advert & ADVERTISE_1000XPSE_ASYM)
1896 advert |= ADVERTISE_PAUSE_ASYM;
1897 if (lpa & LPA_1000XPAUSE)
1898 lpa |= LPA_PAUSE_CAP;
1899 if (lpa & LPA_1000XPAUSE_ASYM)
1900 lpa |= LPA_PAUSE_ASYM;
1901 }
793b883e 1902
da4c1ff4
SH		 1903 sky2->flow_status = FC_NONE;
1904 if (advert & ADVERTISE_PAUSE_CAP) {
1905 if (lpa & LPA_PAUSE_CAP)
1906 sky2->flow_status = FC_BOTH;
1907 else if (advert & ADVERTISE_PAUSE_ASYM)
1908 sky2->flow_status = FC_RX;
1909 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1910 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1911 sky2->flow_status = FC_TX;
1912 }
793b883e 1913
16ad91e1 1914 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1915 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1916 sky2->flow_status = FC_NONE;
2eaba1a2 1917
da4c1ff4 1918 if (sky2->flow_status & FC_TX)
793b883e
SH		 1919 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1920 else
1921 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1922
1923 return 0;
1924}
cd28ab6a 1925
e07b1aa8
SH		 1926/* Interrupt from PHY */
1927static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1928{
e07b1aa8
SH		 1929 struct net_device *dev = hw->dev[port];
1930 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1931 u16 istatus, phystat;
1932
ebc646f6
SH		 1933 if (!netif_running(dev))
1934 return;
1935
e07b1aa8
SH		 1936 spin_lock(&sky2->phy_lock);
1937 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1938 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1939
cd28ab6a
SH		 1940 if (netif_msg_intr(sky2))
1941 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1942 sky2->netdev->name, istatus, phystat);
1943
2eaba1a2 1944 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1945 if (sky2_autoneg_done(sky2, phystat) == 0)
1946 sky2_link_up(sky2);
1947 goto out;
1948 }
cd28ab6a 1949
793b883e
SH		 1950 if (istatus & PHY_M_IS_LSP_CHANGE)
1951 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1952
793b883e
SH		 1953 if (istatus & PHY_M_IS_DUP_CHANGE)
1954 sky2->duplex =
1955 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1956
793b883e
SH		 1957 if (istatus & PHY_M_IS_LST_CHANGE) {
1958 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1959 sky2_link_up(sky2);
793b883e
SH		 1960 else
1961 sky2_link_down(sky2);
cd28ab6a 1962 }
793b883e 1963out:
e07b1aa8 1964 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1965}
1966
62335ab0 1967/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1968 * and tx queue is full (stopped).
1969 */
cd28ab6a
SH		 1970static void sky2_tx_timeout(struct net_device *dev)
1971{
1972 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1973 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1974
1975 if (netif_msg_timer(sky2))
1976 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1977
8f24664d 1978 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1979 dev->name, sky2->tx_cons, sky2->tx_prod,
1980 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1981 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1982
81906791
SH		 1983 /* can't restart safely under softirq */
1984 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1985}
1986
1987static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1988{
6b1a3aef
SH		 1989 struct sky2_port *sky2 = netdev_priv(dev);
1990 struct sky2_hw *hw = sky2->hw;
b628ed98 1991 unsigned port = sky2->port;
6b1a3aef
SH		 1992 int err;
1993 u16 ctl, mode;
e07b1aa8 1994 u32 imask;
cd28ab6a
SH		 1995
1996 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1997 return -EINVAL;
1998
05745c4a
SH		 1999 if (new_mtu > ETH_DATA_LEN &&
2000 (hw->chip_id == CHIP_ID_YUKON_FE ||
2001 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2002 return -EINVAL;
2003
6b1a3aef
SH		 2004 if (!netif_running(dev)) {
2005 dev->mtu = new_mtu;
2006 return 0;
2007 }
2008
e07b1aa8 2009 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2010 sky2_write32(hw, B0_IMSK, 0);
2011
018d1c66
SH		 2012 dev->trans_start = jiffies; /* prevent tx timeout */
2013 netif_stop_queue(dev);
bea3348e 2014 napi_disable(&hw->napi);
018d1c66 2015
e07b1aa8
SH		 2016 synchronize_irq(hw->pdev->irq);
2017
e0c28116 2018 if (sky2_read8(hw, B2_E_0) == 0)
69161611 2019 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2020
2021 ctl = gma_read16(hw, port, GM_GP_CTRL);
2022 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2023 sky2_rx_stop(sky2);
2024 sky2_rx_clean(sky2);
cd28ab6a
SH		 2025
2026 dev->mtu = new_mtu;
14d0263f 2027
6b1a3aef
SH		 2028 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2029 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2030
2031 if (dev->mtu > ETH_DATA_LEN)
2032 mode |= GM_SMOD_JUMBO_ENA;
2033
b628ed98 2034 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2035
b628ed98 2036 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2037
6b1a3aef 2038 err = sky2_rx_start(sky2);
e07b1aa8 2039 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2040
bea3348e
SH		 2041 napi_enable(&hw->napi);
2042
1b537565
SH		 2043 if (err)
2044 dev_close(dev);
2045 else {
b628ed98 2046 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2047
1b537565
SH		 2048 netif_wake_queue(dev);
2049 }
2050
cd28ab6a
SH		 2051 return err;
2052}
2053
14d0263f
SH		 2054/* For small just reuse existing skb for next receive */
2055static struct sk_buff *receive_copy(struct sky2_port *sky2,
2056 const struct rx_ring_info *re,
2057 unsigned length)
2058{
2059 struct sk_buff *skb;
2060
2061 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2062 if (likely(skb)) {
2063 skb_reserve(skb, 2);
2064 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2065 length, PCI_DMA_FROMDEVICE);
d626f62b 2066 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2067 skb->ip_summed = re->skb->ip_summed;
2068 skb->csum = re->skb->csum;
2069 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2070 length, PCI_DMA_FROMDEVICE);
2071 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2072 skb_put(skb, length);
14d0263f
SH		 2073 }
2074 return skb;
2075}
2076
2077/* Adjust length of skb with fragments to match received data */
2078static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2079 unsigned int length)
2080{
2081 int i, num_frags;
2082 unsigned int size;
2083
2084 /* put header into skb */
2085 size = min(length, hdr_space);
2086 skb->tail += size;
2087 skb->len += size;
2088 length -= size;
2089
2090 num_frags = skb_shinfo(skb)->nr_frags;
2091 for (i = 0; i < num_frags; i++) {
2092 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2093
2094 if (length == 0) {
2095 /* don't need this page */
2096 __free_page(frag->page);
2097 --skb_shinfo(skb)->nr_frags;
2098 } else {
2099 size = min(length, (unsigned) PAGE_SIZE);
2100
2101 frag->size = size;
2102 skb->data_len += size;
2103 skb->truesize += size;
2104 skb->len += size;
2105 length -= size;
2106 }
2107 }
2108}
2109
2110/* Normal packet - take skb from ring element and put in a new one */
2111static struct sk_buff *receive_new(struct sky2_port *sky2,
2112 struct rx_ring_info *re,
2113 unsigned int length)
2114{
2115 struct sk_buff *skb, *nskb;
2116 unsigned hdr_space = sky2->rx_data_size;
2117
14d0263f
SH		 2118 /* Don't be tricky about reusing pages (yet) */
2119 nskb = sky2_rx_alloc(sky2);
2120 if (unlikely(!nskb))
2121 return NULL;
2122
2123 skb = re->skb;
2124 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2125
2126 prefetch(skb->data);
2127 re->skb = nskb;
2128 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2129
2130 if (skb_shinfo(skb)->nr_frags)
2131 skb_put_frags(skb, hdr_space, length);
2132 else
489b10c1 2133 skb_put(skb, length);
14d0263f
SH		 2134 return skb;
2135}
2136
cd28ab6a
SH		 2137/*
2138 * Receive one packet.
d571b694 2139 * For larger packets, get new buffer.
cd28ab6a 2140 */
497d7c86 2141static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2142 u16 length, u32 status)
2143{
497d7c86 2144 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2145 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2146 struct sk_buff *skb = NULL;
d6532232
SH		 2147 u16 count = (status & GMR_FS_LEN) >> 16;
2148
2149#ifdef SKY2_VLAN_TAG_USED
2150 /* Account for vlan tag */
2151 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2152 count -= VLAN_HLEN;
2153#endif
cd28ab6a
SH		 2154
2155 if (unlikely(netif_msg_rx_status(sky2)))
2156 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2157 dev->name, sky2->rx_next, status, length);
cd28ab6a 2158
793b883e 2159 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2160 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2161
3b12e014
SH		 2162 /* This chip has hardware problems that generates bogus status.
2163 * So do only marginal checking and expect higher level protocols
2164 * to handle crap frames.
2165 */
2166 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2167 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2168 length != count)
2169 goto okay;
2170
42eeea01 2171 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2172 goto error;
2173
42eeea01
SH		 2174 if (!(status & GMR_FS_RX_OK))
2175 goto resubmit;
2176
d6532232
SH		 2177 /* if length reported by DMA does not match PHY, packet was truncated */
2178 if (length != count)
3b12e014 2179 goto len_error;
71749531 2180
3b12e014 2181okay:
14d0263f
SH		 2182 if (length < copybreak)
2183 skb = receive_copy(sky2, re, length);
2184 else
2185 skb = receive_new(sky2, re, length);
793b883e 2186resubmit:
14d0263f 2187 sky2_rx_submit(sky2, re);
79e57d32 2188
cd28ab6a
SH		 2189 return skb;
2190
3b12e014 2191len_error:
71749531
SH		 2192 /* Truncation of overlength packets
2193 causes PHY length to not match MAC length */
7138a0f5 2194 ++dev->stats.rx_length_errors;
d6532232 2195 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2196 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2197 dev->name, status, length);
d6532232 2198 goto resubmit;
71749531 2199
cd28ab6a 2200error:
7138a0f5 2201 ++dev->stats.rx_errors;
b6d77734 2202 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2203 dev->stats.rx_over_errors++;
b6d77734
SH		 2204 goto resubmit;
2205 }
6e15b712 2206
3be92a70 2207 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2208 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2209 dev->name, status, length);
793b883e
SH		 2210
2211 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2212 dev->stats.rx_length_errors++;
cd28ab6a 2213 if (status & GMR_FS_FRAGMENT)
7138a0f5 2214 dev->stats.rx_frame_errors++;
cd28ab6a 2215 if (status & GMR_FS_CRC_ERR)
7138a0f5 2216 dev->stats.rx_crc_errors++;
79e57d32 2217
793b883e 2218 goto resubmit;
cd28ab6a
SH		 2219}
2220
e07b1aa8
SH		 2221/* Transmit complete */
2222static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2223{
e07b1aa8 2224 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2225
e07b1aa8 2226 if (netif_running(dev)) {
2bb8c262 2227 netif_tx_lock(dev);
e07b1aa8 2228 sky2_tx_complete(sky2, last);
2bb8c262 2229 netif_tx_unlock(dev);
2224795d 2230 }
cd28ab6a
SH		 2231}
2232
e07b1aa8 2233/* Process status response ring */
26691830 2234static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2235{
e07b1aa8 2236 int work_done = 0;
55c9dd35 2237 unsigned rx[2] = { 0, 0 };
a8fd6266 2238
af2a58ac 2239 rmb();
26691830 2240 do {
55c9dd35 2241 struct sky2_port *sky2;
13210ce5 2242 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2243 unsigned port;
13210ce5 2244 struct net_device *dev;
cd28ab6a 2245 struct sk_buff *skb;
cd28ab6a
SH		 2246 u32 status;
2247 u16 length;
ab5adecb
SH		 2248 u8 opcode = le->opcode;
2249
2250 if (!(opcode & HW_OWNER))
2251 break;
cd28ab6a 2252
cb5d9547 2253 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2254
ab5adecb 2255 port = le->css & CSS_LINK_BIT;
69161611 2256 dev = hw->dev[port];
13210ce5 2257 sky2 = netdev_priv(dev);
f65b138c
SH		 2258 length = le16_to_cpu(le->length);
2259 status = le32_to_cpu(le->status);
cd28ab6a 2260
ab5adecb
SH		 2261 le->opcode = 0;
2262 switch (opcode & ~HW_OWNER) {
cd28ab6a 2263 case OP_RXSTAT:
55c9dd35 2264 ++rx[port];
497d7c86 2265 skb = sky2_receive(dev, length, status);
3225b919 2266 if (unlikely(!skb)) {
7138a0f5 2267 dev->stats.rx_dropped++;
55c9dd35 2268 break;
3225b919 2269 }
13210ce5 2270
69161611 2271 /* This chip reports checksum status differently */
05745c4a 2272 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2273 if (sky2->rx_csum &&
2274 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2275 (le->css & CSS_TCPUDPCSOK))
2276 skb->ip_summed = CHECKSUM_UNNECESSARY;
2277 else
2278 skb->ip_summed = CHECKSUM_NONE;
2279 }
2280
13210ce5 2281 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2282 dev->stats.rx_packets++;
2283 dev->stats.rx_bytes += skb->len;
13210ce5
SH		 2284 dev->last_rx = jiffies;
2285
d1f13708
SH		 2286#ifdef SKY2_VLAN_TAG_USED
2287 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2288 vlan_hwaccel_receive_skb(skb,
2289 sky2->vlgrp,
2290 be16_to_cpu(sky2->rx_tag));
2291 } else
2292#endif
cd28ab6a 2293 netif_receive_skb(skb);
13210ce5 2294
22e11703 2295 /* Stop after net poll weight */
13210ce5
SH		 2296 if (++work_done >= to_do)
2297 goto exit_loop;
cd28ab6a
SH		 2298 break;
2299
d1f13708
SH		 2300#ifdef SKY2_VLAN_TAG_USED
2301 case OP_RXVLAN:
2302 sky2->rx_tag = length;
2303 break;
2304
2305 case OP_RXCHKSVLAN:
2306 sky2->rx_tag = length;
2307 /* fall through */
2308#endif
cd28ab6a 2309 case OP_RXCHKS:
87418307
SH		 2310 if (!sky2->rx_csum)
2311 break;
2312
05745c4a
SH		 2313 /* If this happens then driver assuming wrong format */
2314 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2315 if (net_ratelimit())
2316 printk(KERN_NOTICE "%s: unexpected"
2317 " checksum status\n",
2318 dev->name);
69161611 2319 break;
05745c4a 2320 }
69161611 2321
87418307
SH		 2322 /* Both checksum counters are programmed to start at
2323 * the same offset, so unless there is a problem they
2324 * should match. This failure is an early indication that
2325 * hardware receive checksumming won't work.
2326 */
2327 if (likely(status >> 16 == (status & 0xffff))) {
2328 skb = sky2->rx_ring[sky2->rx_next].skb;
2329 skb->ip_summed = CHECKSUM_COMPLETE;
2330 skb->csum = status & 0xffff;
2331 } else {
2332 printk(KERN_NOTICE PFX "%s: hardware receive "
2333 "checksum problem (status = %#x)\n",
2334 dev->name, status);
2335 sky2->rx_csum = 0;
2336 sky2_write32(sky2->hw,
69161611 2337 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2338 BMU_DIS_RX_CHKSUM);
2339 }
cd28ab6a
SH		 2340 break;
2341
2342 case OP_TXINDEXLE:
13b97b74 2343 /* TX index reports status for both ports */
f55925d7
SH		 2344 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2345 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2346 if (hw->dev[1])
2347 sky2_tx_done(hw->dev[1],
2348 ((status >> 24) & 0xff)
2349 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2350 break;
2351
cd28ab6a
SH		 2352 default:
2353 if (net_ratelimit())
793b883e 2354 printk(KERN_WARNING PFX
ab5adecb 2355 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2356 }
26691830 2357 } while (hw->st_idx != idx);
cd28ab6a 2358
fe2a24df
SH		 2359 /* Fully processed status ring so clear irq */
2360 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2361
13210ce5 2362exit_loop:
55c9dd35
SH		 2363 if (rx[0])
2364 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2365
55c9dd35
SH		 2366 if (rx[1])
2367 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2368
e07b1aa8 2369 return work_done;
cd28ab6a
SH		 2370}
2371
2372static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2373{
2374 struct net_device *dev = hw->dev[port];
2375
3be92a70
SH		 2376 if (net_ratelimit())
2377 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2378 dev->name, status);
cd28ab6a
SH		 2379
2380 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2381 if (net_ratelimit())
2382 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2383 dev->name);
cd28ab6a
SH		 2384 /* Clear IRQ */
2385 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2386 }
2387
2388 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2389 if (net_ratelimit())
2390 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2391 dev->name);
cd28ab6a
SH		 2392
2393 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2394 }
2395
2396 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2397 if (net_ratelimit())
2398 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2399 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2400 }
2401
2402 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2403 if (net_ratelimit())
2404 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2405 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2406 }
2407
2408 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2409 if (net_ratelimit())
2410 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2411 dev->name);
cd28ab6a
SH		 2412 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2413 }
2414}
2415
2416static void sky2_hw_intr(struct sky2_hw *hw)
2417{
555382cb 2418 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2419 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2420 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2421
2422 status &= hwmsk;
cd28ab6a 2423
793b883e 2424 if (status & Y2_IS_TIST_OV)
cd28ab6a 2425 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2426
2427 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2428 u16 pci_err;
2429
b32f40c4 2430 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2431 if (net_ratelimit())
555382cb 2432 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2433 pci_err);
cd28ab6a 2434
b32f40c4 2435 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2436 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2437 }
2438
2439 if (status & Y2_IS_PCI_EXP) {
d571b694 2440 /* PCI-Express uncorrectable Error occurred */
555382cb 2441 u32 err;
cd28ab6a 2442
7782c8c4
SH		 2443 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2444 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2445 0xfffffffful);
3be92a70 2446 if (net_ratelimit())
555382cb 2447 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2448
7782c8c4 2449 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
cd28ab6a
SH		 2450 }
2451
2452 if (status & Y2_HWE_L1_MASK)
2453 sky2_hw_error(hw, 0, status);
2454 status >>= 8;
2455 if (status & Y2_HWE_L1_MASK)
2456 sky2_hw_error(hw, 1, status);
2457}
2458
2459static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2460{
2461 struct net_device *dev = hw->dev[port];
2462 struct sky2_port *sky2 = netdev_priv(dev);
2463 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2464
2465 if (netif_msg_intr(sky2))
2466 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2467 dev->name, status);
2468
a3caeada
SH		 2469 if (status & GM_IS_RX_CO_OV)
2470 gma_read16(hw, port, GM_RX_IRQ_SRC);
2471
2472 if (status & GM_IS_TX_CO_OV)
2473 gma_read16(hw, port, GM_TX_IRQ_SRC);
2474
cd28ab6a 2475 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2476 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2477 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2478 }
2479
2480 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2481 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2482 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2483 }
cd28ab6a
SH		 2484}
2485
40b01727
SH		 2486/* This should never happen it is a bug. */
2487static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2488 u16 q, unsigned ring_size)
d257924e
SH		 2489{
2490 struct net_device *dev = hw->dev[port];
2491 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2492 unsigned idx;
2493 const u64 *le = (q == Q_R1 || q == Q_R2)
2494 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2495
40b01727
SH		 2496 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2497 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2498 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2499 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2500
40b01727 2501 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2502}
cd28ab6a 2503
75e80683
SH		 2504static int sky2_rx_hung(struct net_device *dev)
2505{
2506 struct sky2_port *sky2 = netdev_priv(dev);
2507 struct sky2_hw *hw = sky2->hw;
2508 unsigned port = sky2->port;
2509 unsigned rxq = rxqaddr[port];
2510 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2511 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2512 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2513 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2514
2515 /* If idle and MAC or PCI is stuck */
2516 if (sky2->check.last == dev->last_rx &&
2517 ((mac_rp == sky2->check.mac_rp &&
2518 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2519 /* Check if the PCI RX hang */
2520 (fifo_rp == sky2->check.fifo_rp &&
2521 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2522 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2523 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2524 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2525 return 1;
2526 } else {
2527 sky2->check.last = dev->last_rx;
2528 sky2->check.mac_rp = mac_rp;
2529 sky2->check.mac_lev = mac_lev;
2530 sky2->check.fifo_rp = fifo_rp;
2531 sky2->check.fifo_lev = fifo_lev;
2532 return 0;
2533 }
2534}
2535
32c2c300 2536static void sky2_watchdog(unsigned long arg)
d27ed387 2537{
01bd7564 2538 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2539
75e80683 2540 /* Check for lost IRQ once a second */
32c2c300 2541 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2542 napi_schedule(&hw->napi);
75e80683
SH		 2543 } else {
2544 int i, active = 0;
2545
2546 for (i = 0; i < hw->ports; i++) {
bea3348e 2547 struct net_device *dev = hw->dev[i];
75e80683
SH		 2548 if (!netif_running(dev))
2549 continue;
2550 ++active;
2551
2552 /* For chips with Rx FIFO, check if stuck */
e0c28116 2553 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
75e80683
SH		 2554 sky2_rx_hung(dev)) {
2555 pr_info(PFX "%s: receiver hang detected\n",
2556 dev->name);
2557 schedule_work(&hw->restart_work);
2558 return;
2559 }
2560 }
2561
2562 if (active == 0)
2563 return;
32c2c300 2564 }
01bd7564 2565
75e80683 2566 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2567}
2568
40b01727
SH		 2569/* Hardware/software error handling */
2570static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2571{
40b01727
SH		 2572 if (net_ratelimit())
2573 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2574
1e5f1283
SH		 2575 if (status & Y2_IS_HW_ERR)
2576 sky2_hw_intr(hw);
d257924e 2577
1e5f1283
SH		 2578 if (status & Y2_IS_IRQ_MAC1)
2579 sky2_mac_intr(hw, 0);
cd28ab6a 2580
1e5f1283
SH		 2581 if (status & Y2_IS_IRQ_MAC2)
2582 sky2_mac_intr(hw, 1);
cd28ab6a 2583
1e5f1283 2584 if (status & Y2_IS_CHK_RX1)
40b01727 2585 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2586
1e5f1283 2587 if (status & Y2_IS_CHK_RX2)
40b01727 2588 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2589
1e5f1283 2590 if (status & Y2_IS_CHK_TXA1)
40b01727 2591 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2592
1e5f1283 2593 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2594 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2595}
2596
bea3348e 2597static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2598{
bea3348e 2599 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2600 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2601 int work_done = 0;
26691830 2602 u16 idx;
40b01727
SH		 2603
2604 if (unlikely(status & Y2_IS_ERROR))
2605 sky2_err_intr(hw, status);
2606
2607 if (status & Y2_IS_IRQ_PHY1)
2608 sky2_phy_intr(hw, 0);
2609
2610 if (status & Y2_IS_IRQ_PHY2)
2611 sky2_phy_intr(hw, 1);
cd28ab6a 2612
26691830
SH		 2613 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2614 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2615
2616 if (work_done >= work_limit)
26691830
SH		 2617 goto done;
2618 }
6f535763 2619
26691830
SH		 2620 /* Bug/Errata workaround?
2621 * Need to kick the TX irq moderation timer.
2622 */
2623 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2624 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2625 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2626 }
26691830
SH		 2627 napi_complete(napi);
2628 sky2_read32(hw, B0_Y2_SP_LISR);
2629done:
6f535763 2630
bea3348e 2631 return work_done;
e07b1aa8
SH		 2632}
2633
7d12e780 2634static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2635{
2636 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2637 u32 status;
2638
2639 /* Reading this mask interrupts as side effect */
2640 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2641 if (status == 0 || status == ~0)
2642 return IRQ_NONE;
793b883e 2643
e07b1aa8 2644 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2645
2646 napi_schedule(&hw->napi);
793b883e 2647
cd28ab6a
SH		 2648 return IRQ_HANDLED;
2649}
2650
2651#ifdef CONFIG_NET_POLL_CONTROLLER
2652static void sky2_netpoll(struct net_device *dev)
2653{
2654 struct sky2_port *sky2 = netdev_priv(dev);
2655
bea3348e 2656 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2657}
2658#endif
2659
2660/* Chip internal frequency for clock calculations */
05745c4a 2661static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2662{
793b883e 2663 switch (hw->chip_id) {
cd28ab6a 2664 case CHIP_ID_YUKON_EC:
5a5b1ea0 2665 case CHIP_ID_YUKON_EC_U:
93745494 2666 case CHIP_ID_YUKON_EX:
05745c4a
SH		 2667 return 125;
2668
cd28ab6a 2669 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2670 return 100;
2671
2672 case CHIP_ID_YUKON_FE_P:
2673 return 50;
2674
2675 case CHIP_ID_YUKON_XL:
2676 return 156;
2677
2678 default:
2679 BUG();
cd28ab6a
SH		 2680 }
2681}
2682
fb17358f 2683static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2684{
fb17358f 2685 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2686}
2687
fb17358f 2688static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2689{
fb17358f 2690 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2691}
2692
fb17358f 2693
e3173832 2694static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2695{
b89165f2 2696 u8 t8;
cd28ab6a 2697
167f53d0 2698 /* Enable all clocks and check for bad PCI access */
b32f40c4 2699 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2700
cd28ab6a 2701 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2702
cd28ab6a 2703 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2704 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2705
2706 switch(hw->chip_id) {
2707 case CHIP_ID_YUKON_XL:
2708 hw->flags = SKY2_HW_GIGABIT
e0c28116
SH		 2709 | SKY2_HW_NEWER_PHY;
2710 if (hw->chip_rev < 3)
2711 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2712
ea76e635
SH		 2713 break;
2714
2715 case CHIP_ID_YUKON_EC_U:
2716 hw->flags = SKY2_HW_GIGABIT
2717 | SKY2_HW_NEWER_PHY
2718 | SKY2_HW_ADV_POWER_CTL;
2719 break;
2720
2721 case CHIP_ID_YUKON_EX:
2722 hw->flags = SKY2_HW_GIGABIT
2723 | SKY2_HW_NEWER_PHY
2724 | SKY2_HW_NEW_LE
2725 | SKY2_HW_ADV_POWER_CTL;
2726
2727 /* New transmit checksum */
2728 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2729 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2730 break;
2731
2732 case CHIP_ID_YUKON_EC:
2733 /* This rev is really old, and requires untested workarounds */
2734 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2735 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2736 return -EOPNOTSUPP;
2737 }
e0c28116 2738 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
ea76e635
SH		 2739 break;
2740
2741 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2742 break;
2743
05745c4a
SH		 2744 case CHIP_ID_YUKON_FE_P:
2745 hw->flags = SKY2_HW_NEWER_PHY
2746 | SKY2_HW_NEW_LE
2747 | SKY2_HW_AUTO_TX_SUM
2748 | SKY2_HW_ADV_POWER_CTL;
2749 break;
ea76e635 2750 default:
b02a9258
SH		 2751 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2752 hw->chip_id);
cd28ab6a
SH		 2753 return -EOPNOTSUPP;
2754 }
2755
ea76e635
SH		 2756 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2757 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2758 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2759
290d4de5 2760
e3173832
SH		 2761 hw->ports = 1;
2762 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2763 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2764 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2765 ++hw->ports;
2766 }
2767
2768 return 0;
2769}
2770
2771static void sky2_reset(struct sky2_hw *hw)
2772{
555382cb 2773 struct pci_dev *pdev = hw->pdev;
e3173832 2774 u16 status;
555382cb
SH		 2775 int i, cap;
2776 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2777
cd28ab6a 2778 /* disable ASF */
4f44d8ba
SH		 2779 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2780 status = sky2_read16(hw, HCU_CCSR);
2781 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2782 HCU_CCSR_UC_STATE_MSK);
2783 sky2_write16(hw, HCU_CCSR, status);
2784 } else
2785 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2786 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2787
2788 /* do a SW reset */
2789 sky2_write8(hw, B0_CTST, CS_RST_SET);
2790 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2791
ac93a394
SH		 2792 /* allow writes to PCI config */
2793 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2794
cd28ab6a 2795 /* clear PCI errors, if any */
b32f40c4 2796 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2797 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2798 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2799
2800 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2801
555382cb
SH		 2802 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2803 if (cap) {
7782c8c4
SH		 2804 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2805 0xfffffffful);
555382cb
SH		 2806
2807 /* If error bit is stuck on ignore it */
2808 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2809 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2810 else
555382cb
SH		 2811 hwe_mask |= Y2_IS_PCI_EXP;
2812 }
cd28ab6a 2813
ae306cca 2814 sky2_power_on(hw);
cd28ab6a
SH		 2815
2816 for (i = 0; i < hw->ports; i++) {
2817 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2818 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2819
2820 if (hw->chip_id == CHIP_ID_YUKON_EX)
2821 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2822 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2823 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2824 }
2825
793b883e
SH		 2826 /* Clear I2C IRQ noise */
2827 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2828
2829 /* turn off hardware timer (unused) */
2830 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2831 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2832
cd28ab6a
SH		 2833 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2834
69634ee7
SH		 2835 /* Turn off descriptor polling */
2836 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2837
2838 /* Turn off receive timestamp */
2839 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2840 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2841
2842 /* enable the Tx Arbiters */
2843 for (i = 0; i < hw->ports; i++)
2844 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2845
2846 /* Initialize ram interface */
2847 for (i = 0; i < hw->ports; i++) {
793b883e 2848 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2849
2850 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2851 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2852 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2853 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2854 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2855 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2856 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2857 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2858 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2859 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2860 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2861 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2862 }
2863
555382cb 2864 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2865
cd28ab6a 2866 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2867 sky2_gmac_reset(hw, i);
cd28ab6a 2868
cd28ab6a
SH		 2869 memset(hw->st_le, 0, STATUS_LE_BYTES);
2870 hw->st_idx = 0;
2871
2872 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2873 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2874
2875 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2876 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2877
2878 /* Set the list last index */
793b883e 2879 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2880
290d4de5
SH		 2881 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2882 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2883
290d4de5
SH		 2884 /* set Status-FIFO ISR watermark */
2885 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2886 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2887 else
2888 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2889
290d4de5 2890 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2891 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2892 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2893
793b883e 2894 /* enable status unit */
cd28ab6a
SH		 2895 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2896
2897 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2898 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2899 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2900}
2901
81906791
SH		 2902static void sky2_restart(struct work_struct *work)
2903{
2904 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2905 struct net_device *dev;
2906 int i, err;
2907
81906791
SH		 2908 rtnl_lock();
2909 sky2_write32(hw, B0_IMSK, 0);
2910 sky2_read32(hw, B0_IMSK);
6de16237 2911 napi_disable(&hw->napi);
81906791 2912
81906791
SH		 2913 for (i = 0; i < hw->ports; i++) {
2914 dev = hw->dev[i];
2915 if (netif_running(dev))
2916 sky2_down(dev);
2917 }
2918
2919 sky2_reset(hw);
2920 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 2921 napi_enable(&hw->napi);
81906791
SH		 2922
2923 for (i = 0; i < hw->ports; i++) {
2924 dev = hw->dev[i];
2925 if (netif_running(dev)) {
2926 err = sky2_up(dev);
2927 if (err) {
2928 printk(KERN_INFO PFX "%s: could not restart %d\n",
2929 dev->name, err);
2930 dev_close(dev);
2931 }
2932 }
2933 }
2934
81906791
SH		 2935 rtnl_unlock();
2936}
2937
e3173832
SH		 2938static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2939{
2940 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2941}
2942
2943static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2944{
2945 const struct sky2_port *sky2 = netdev_priv(dev);
2946
2947 wol->supported = sky2_wol_supported(sky2->hw);
2948 wol->wolopts = sky2->wol;
2949}
2950
2951static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2952{
2953 struct sky2_port *sky2 = netdev_priv(dev);
2954 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2955
e3173832
SH		 2956 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2957 return -EOPNOTSUPP;
2958
2959 sky2->wol = wol->wolopts;
2960
05745c4a
SH		 2961 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2962 hw->chip_id == CHIP_ID_YUKON_EX ||
2963 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 2964 sky2_write32(hw, B0_CTST, sky2->wol
2965 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2966
2967 if (!netif_running(dev))
2968 sky2_wol_init(sky2);
cd28ab6a
SH		 2969 return 0;
2970}
2971
28bd181a 2972static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2973{
b89165f2
SH		 2974 if (sky2_is_copper(hw)) {
2975 u32 modes = SUPPORTED_10baseT_Half
2976 | SUPPORTED_10baseT_Full
2977 | SUPPORTED_100baseT_Half
2978 | SUPPORTED_100baseT_Full
2979 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2980
ea76e635 2981 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 2982 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2983 | SUPPORTED_1000baseT_Full;
2984 return modes;
cd28ab6a 2985 } else
b89165f2
SH		 2986 return SUPPORTED_1000baseT_Half
2987 | SUPPORTED_1000baseT_Full
2988 | SUPPORTED_Autoneg
2989 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2990}
2991
793b883e 2992static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2993{
2994 struct sky2_port *sky2 = netdev_priv(dev);
2995 struct sky2_hw *hw = sky2->hw;
2996
2997 ecmd->transceiver = XCVR_INTERNAL;
2998 ecmd->supported = sky2_supported_modes(hw);
2999 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3000 if (sky2_is_copper(hw)) {
cd28ab6a 3001 ecmd->port = PORT_TP;
b89165f2
SH		 3002 ecmd->speed = sky2->speed;
3003 } else {
3004 ecmd->speed = SPEED_1000;
cd28ab6a 3005 ecmd->port = PORT_FIBRE;
b89165f2 3006 }
cd28ab6a
SH		 3007
3008 ecmd->advertising = sky2->advertising;
3009 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3010 ecmd->duplex = sky2->duplex;
3011 return 0;
3012}
3013
3014static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3015{
3016 struct sky2_port *sky2 = netdev_priv(dev);
3017 const struct sky2_hw *hw = sky2->hw;
3018 u32 supported = sky2_supported_modes(hw);
3019
3020 if (ecmd->autoneg == AUTONEG_ENABLE) {
3021 ecmd->advertising = supported;
3022 sky2->duplex = -1;
3023 sky2->speed = -1;
3024 } else {
3025 u32 setting;
3026
793b883e 3027 switch (ecmd->speed) {
cd28ab6a
SH		 3028 case SPEED_1000:
3029 if (ecmd->duplex == DUPLEX_FULL)
3030 setting = SUPPORTED_1000baseT_Full;
3031 else if (ecmd->duplex == DUPLEX_HALF)
3032 setting = SUPPORTED_1000baseT_Half;
3033 else
3034 return -EINVAL;
3035 break;
3036 case SPEED_100:
3037 if (ecmd->duplex == DUPLEX_FULL)
3038 setting = SUPPORTED_100baseT_Full;
3039 else if (ecmd->duplex == DUPLEX_HALF)
3040 setting = SUPPORTED_100baseT_Half;
3041 else
3042 return -EINVAL;
3043 break;
3044
3045 case SPEED_10:
3046 if (ecmd->duplex == DUPLEX_FULL)
3047 setting = SUPPORTED_10baseT_Full;
3048 else if (ecmd->duplex == DUPLEX_HALF)
3049 setting = SUPPORTED_10baseT_Half;
3050 else
3051 return -EINVAL;
3052 break;
3053 default:
3054 return -EINVAL;
3055 }
3056
3057 if ((setting & supported) == 0)
3058 return -EINVAL;
3059
3060 sky2->speed = ecmd->speed;
3061 sky2->duplex = ecmd->duplex;
3062 }
3063
3064 sky2->autoneg = ecmd->autoneg;
3065 sky2->advertising = ecmd->advertising;
3066
d1b139c0 3067 if (netif_running(dev)) {
1b537565 3068 sky2_phy_reinit(sky2);
d1b139c0
SH		 3069 sky2_set_multicast(dev);
3070 }
cd28ab6a
SH		 3071
3072 return 0;
3073}
3074
3075static void sky2_get_drvinfo(struct net_device *dev,
3076 struct ethtool_drvinfo *info)
3077{
3078 struct sky2_port *sky2 = netdev_priv(dev);
3079
3080 strcpy(info->driver, DRV_NAME);
3081 strcpy(info->version, DRV_VERSION);
3082 strcpy(info->fw_version, "N/A");
3083 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3084}
3085
3086static const struct sky2_stat {
793b883e
SH		 3087 char name[ETH_GSTRING_LEN];
3088 u16 offset;
cd28ab6a
SH		 3089} sky2_stats[] = {
3090 { "tx_bytes", GM_TXO_OK_HI },
3091 { "rx_bytes", GM_RXO_OK_HI },
3092 { "tx_broadcast", GM_TXF_BC_OK },
3093 { "rx_broadcast", GM_RXF_BC_OK },
3094 { "tx_multicast", GM_TXF_MC_OK },
3095 { "rx_multicast", GM_RXF_MC_OK },
3096 { "tx_unicast", GM_TXF_UC_OK },
3097 { "rx_unicast", GM_RXF_UC_OK },
3098 { "tx_mac_pause", GM_TXF_MPAUSE },
3099 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3100 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3101 { "late_collision",GM_TXF_LAT_COL },
3102 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3103 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3104 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3105
d2604540 3106 { "rx_short", GM_RXF_SHT },
cd28ab6a 3107 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3108 { "rx_64_byte_packets", GM_RXF_64B },
3109 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3110 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3111 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3112 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3113 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3114 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3115 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3116 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3117 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3118 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3119
3120 { "tx_64_byte_packets", GM_TXF_64B },
3121 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3122 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3123 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3124 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3125 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3126 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3127 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3128};
3129
cd28ab6a
SH		 3130static u32 sky2_get_rx_csum(struct net_device *dev)
3131{
3132 struct sky2_port *sky2 = netdev_priv(dev);
3133
3134 return sky2->rx_csum;
3135}
3136
3137static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3138{
3139 struct sky2_port *sky2 = netdev_priv(dev);
3140
3141 sky2->rx_csum = data;
793b883e 3142
cd28ab6a
SH		 3143 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3144 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3145
3146 return 0;
3147}
3148
3149static u32 sky2_get_msglevel(struct net_device *netdev)
3150{
3151 struct sky2_port *sky2 = netdev_priv(netdev);
3152 return sky2->msg_enable;
3153}
3154
9a7ae0a9
SH		 3155static int sky2_nway_reset(struct net_device *dev)
3156{
3157 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3158
16ad91e1 3159 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3160 return -EINVAL;
3161
1b537565 3162 sky2_phy_reinit(sky2);
d1b139c0 3163 sky2_set_multicast(dev);
9a7ae0a9
SH		 3164
3165 return 0;
3166}
3167
793b883e 3168static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3169{
3170 struct sky2_hw *hw = sky2->hw;
3171 unsigned port = sky2->port;
3172 int i;
3173
3174 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3175 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3176 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3177 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3178
793b883e 3179 for (i = 2; i < count; i++)
cd28ab6a
SH		 3180 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3181}
3182
cd28ab6a
SH		 3183static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3184{
3185 struct sky2_port *sky2 = netdev_priv(netdev);
3186 sky2->msg_enable = value;
3187}
3188
b9f2c044 3189static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3190{
b9f2c044
JG		 3191 switch (sset) {
3192 case ETH_SS_STATS:
3193 return ARRAY_SIZE(sky2_stats);
3194 default:
3195 return -EOPNOTSUPP;
3196 }
cd28ab6a
SH		 3197}
3198
3199static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3200 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3201{
3202 struct sky2_port *sky2 = netdev_priv(dev);
3203
793b883e 3204 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3205}
3206
793b883e 3207static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3208{
3209 int i;
3210
3211 switch (stringset) {
3212 case ETH_SS_STATS:
3213 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3214 memcpy(data + i * ETH_GSTRING_LEN,
3215 sky2_stats[i].name, ETH_GSTRING_LEN);
3216 break;
3217 }
3218}
3219
cd28ab6a
SH		 3220static int sky2_set_mac_address(struct net_device *dev, void *p)
3221{
3222 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3223 struct sky2_hw *hw = sky2->hw;
3224 unsigned port = sky2->port;
3225 const struct sockaddr *addr = p;
cd28ab6a
SH		 3226
3227 if (!is_valid_ether_addr(addr->sa_data))
3228 return -EADDRNOTAVAIL;
3229
cd28ab6a 3230 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3231 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3232 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3233 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3234 dev->dev_addr, ETH_ALEN);
1b537565 3235
a8ab1ec0
SH		 3236 /* virtual address for data */
3237 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3238
3239 /* physical address: used for pause frames */
3240 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3241
3242 return 0;
cd28ab6a
SH		 3243}
3244
a052b52f
SH		 3245static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3246{
3247 u32 bit;
3248
3249 bit = ether_crc(ETH_ALEN, addr) & 63;
3250 filter[bit >> 3] |= 1 << (bit & 7);
3251}
3252
cd28ab6a
SH		 3253static void sky2_set_multicast(struct net_device *dev)
3254{
3255 struct sky2_port *sky2 = netdev_priv(dev);
3256 struct sky2_hw *hw = sky2->hw;
3257 unsigned port = sky2->port;
3258 struct dev_mc_list *list = dev->mc_list;
3259 u16 reg;
3260 u8 filter[8];
a052b52f
SH		 3261 int rx_pause;
3262 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3263
a052b52f 3264 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3265 memset(filter, 0, sizeof(filter));
3266
3267 reg = gma_read16(hw, port, GM_RX_CTRL);
3268 reg |= GM_RXCR_UCF_ENA;
3269
d571b694 3270 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3271 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3272 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3273 memset(filter, 0xff, sizeof(filter));
a052b52f 3274 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3275 reg &= ~GM_RXCR_MCF_ENA;
3276 else {
3277 int i;
3278 reg |= GM_RXCR_MCF_ENA;
3279
a052b52f
SH		 3280 if (rx_pause)
3281 sky2_add_filter(filter, pause_mc_addr);
3282
3283 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3284 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3285 }
3286
cd28ab6a 3287 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3288 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3289 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3290 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3291 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3292 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3293 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3294 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3295
3296 gma_write16(hw, port, GM_RX_CTRL, reg);
3297}
3298
3299/* Can have one global because blinking is controlled by
3300 * ethtool and that is always under RTNL mutex
3301 */
91c86df5 3302static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3303{
793b883e
SH		 3304 u16 pg;
3305
793b883e
SH		 3306 switch (hw->chip_id) {
3307 case CHIP_ID_YUKON_XL:
3308 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3309 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3310 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3311 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3312 PHY_M_LEDC_INIT_CTRL(7) |
3313 PHY_M_LEDC_STA1_CTRL(7) |
3314 PHY_M_LEDC_STA0_CTRL(7))
3315 : 0);
3316
3317 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3318 break;
3319
3320 default:
3321 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3322 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3323 on ? PHY_M_LED_ALL : 0);
793b883e 3324 }
cd28ab6a
SH		 3325}
3326
3327/* blink LED's for finding board */
3328static int sky2_phys_id(struct net_device *dev, u32 data)
3329{
3330 struct sky2_port *sky2 = netdev_priv(dev);
3331 struct sky2_hw *hw = sky2->hw;
3332 unsigned port = sky2->port;
793b883e 3333 u16 ledctrl, ledover = 0;
cd28ab6a 3334 long ms;
91c86df5 3335 int interrupted;
cd28ab6a
SH		 3336 int onoff = 1;
3337
793b883e 3338 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3339 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3340 else
3341 ms = data * 1000;
3342
3343 /* save initial values */
e07b1aa8 3344 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3345 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3346 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3347 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3348 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3349 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3350 } else {
3351 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3352 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3353 }
cd28ab6a 3354
91c86df5
SH		 3355 interrupted = 0;
3356 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3357 sky2_led(hw, port, onoff);
3358 onoff = !onoff;
3359
e07b1aa8 3360 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3361 interrupted = msleep_interruptible(250);
e07b1aa8 3362 spin_lock_bh(&sky2->phy_lock);
91c86df5 3363
cd28ab6a
SH		 3364 ms -= 250;
3365 }
3366
3367 /* resume regularly scheduled programming */
793b883e
SH		 3368 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3369 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3370 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3371 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3372 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3373 } else {
3374 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3375 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3376 }
e07b1aa8 3377 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3378
3379 return 0;
3380}
3381
3382static void sky2_get_pauseparam(struct net_device *dev,
3383 struct ethtool_pauseparam *ecmd)
3384{
3385 struct sky2_port *sky2 = netdev_priv(dev);
3386
16ad91e1
SH		 3387 switch (sky2->flow_mode) {
3388 case FC_NONE:
3389 ecmd->tx_pause = ecmd->rx_pause = 0;
3390 break;
3391 case FC_TX:
3392 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3393 break;
3394 case FC_RX:
3395 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3396 break;
3397 case FC_BOTH:
3398 ecmd->tx_pause = ecmd->rx_pause = 1;
3399 }
3400
cd28ab6a
SH		 3401 ecmd->autoneg = sky2->autoneg;
3402}
3403
3404static int sky2_set_pauseparam(struct net_device *dev,
3405 struct ethtool_pauseparam *ecmd)
3406{
3407 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3408
3409 sky2->autoneg = ecmd->autoneg;
16ad91e1 3410 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3411
16ad91e1
SH		 3412 if (netif_running(dev))
3413 sky2_phy_reinit(sky2);
cd28ab6a 3414
2eaba1a2 3415 return 0;
cd28ab6a
SH		 3416}
3417
fb17358f
SH		 3418static int sky2_get_coalesce(struct net_device *dev,
3419 struct ethtool_coalesce *ecmd)
3420{
3421 struct sky2_port *sky2 = netdev_priv(dev);
3422 struct sky2_hw *hw = sky2->hw;
3423
3424 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3425 ecmd->tx_coalesce_usecs = 0;
3426 else {
3427 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3428 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3429 }
3430 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3431
3432 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3433 ecmd->rx_coalesce_usecs = 0;
3434 else {
3435 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3436 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3437 }
3438 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3439
3440 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3441 ecmd->rx_coalesce_usecs_irq = 0;
3442 else {
3443 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3444 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3445 }
3446
3447 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3448
3449 return 0;
3450}
3451
3452/* Note: this affect both ports */
3453static int sky2_set_coalesce(struct net_device *dev,
3454 struct ethtool_coalesce *ecmd)
3455{
3456 struct sky2_port *sky2 = netdev_priv(dev);
3457 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3458 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3459
77b3d6a2
SH		 3460 if (ecmd->tx_coalesce_usecs > tmax ||
3461 ecmd->rx_coalesce_usecs > tmax ||
3462 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3463 return -EINVAL;
3464
ff81fbbe 3465 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3466 return -EINVAL;
ff81fbbe 3467 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3468 return -EINVAL;
ff81fbbe 3469 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3470 return -EINVAL;
3471
3472 if (ecmd->tx_coalesce_usecs == 0)
3473 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3474 else {
3475 sky2_write32(hw, STAT_TX_TIMER_INI,
3476 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3477 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3478 }
3479 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3480
3481 if (ecmd->rx_coalesce_usecs == 0)
3482 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3483 else {
3484 sky2_write32(hw, STAT_LEV_TIMER_INI,
3485 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3486 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3487 }
3488 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3489
3490 if (ecmd->rx_coalesce_usecs_irq == 0)
3491 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3492 else {
d28d4870 3493 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3494 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3495 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3496 }
3497 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3498 return 0;
3499}
3500
793b883e
SH		 3501static void sky2_get_ringparam(struct net_device *dev,
3502 struct ethtool_ringparam *ering)
3503{
3504 struct sky2_port *sky2 = netdev_priv(dev);
3505
3506 ering->rx_max_pending = RX_MAX_PENDING;
3507 ering->rx_mini_max_pending = 0;
3508 ering->rx_jumbo_max_pending = 0;
3509 ering->tx_max_pending = TX_RING_SIZE - 1;
3510
3511 ering->rx_pending = sky2->rx_pending;
3512 ering->rx_mini_pending = 0;
3513 ering->rx_jumbo_pending = 0;
3514 ering->tx_pending = sky2->tx_pending;
3515}
3516
3517static int sky2_set_ringparam(struct net_device *dev,
3518 struct ethtool_ringparam *ering)
3519{
3520 struct sky2_port *sky2 = netdev_priv(dev);
3521 int err = 0;
3522
3523 if (ering->rx_pending > RX_MAX_PENDING ||
3524 ering->rx_pending < 8 ||
3525 ering->tx_pending < MAX_SKB_TX_LE ||
3526 ering->tx_pending > TX_RING_SIZE - 1)
3527 return -EINVAL;
3528
3529 if (netif_running(dev))
3530 sky2_down(dev);
3531
3532 sky2->rx_pending = ering->rx_pending;
3533 sky2->tx_pending = ering->tx_pending;
3534
1b537565 3535 if (netif_running(dev)) {
793b883e 3536 err = sky2_up(dev);
1b537565
SH		 3537 if (err)
3538 dev_close(dev);
6ed995bb
SH		 3539 else
3540 sky2_set_multicast(dev);
1b537565 3541 }
793b883e
SH		 3542
3543 return err;
3544}
3545
793b883e
SH		 3546static int sky2_get_regs_len(struct net_device *dev)
3547{
6e4cbb34 3548 return 0x4000;
793b883e
SH		 3549}
3550
3551/*
3552 * Returns copy of control register region
3ead5db7 3553 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3554 */
3555static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3556 void *p)
3557{
3558 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3559 const void __iomem *io = sky2->hw->regs;
295b54c4 3560 unsigned int b;
793b883e
SH		 3561
3562 regs->version = 1;
793b883e 3563
295b54c4
SH		 3564 for (b = 0; b < 128; b++) {
3565 /* This complicated switch statement is to make sure and
3566 * only access regions that are unreserved.
3567 * Some blocks are only valid on dual port cards.
3568 * and block 3 has some special diagnostic registers that
3569 * are poison.
3570 */
3571 switch (b) {
3572 case 3:
3573 /* skip diagnostic ram region */
3574 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3575 break;
3ead5db7 3576
295b54c4
SH		 3577 /* dual port cards only */
3578 case 5: /* Tx Arbiter 2 */
3579 case 9: /* RX2 */
3580 case 14 ... 15: /* TX2 */
3581 case 17: case 19: /* Ram Buffer 2 */
3582 case 22 ... 23: /* Tx Ram Buffer 2 */
3583 case 25: /* Rx MAC Fifo 1 */
3584 case 27: /* Tx MAC Fifo 2 */
3585 case 31: /* GPHY 2 */
3586 case 40 ... 47: /* Pattern Ram 2 */
3587 case 52: case 54: /* TCP Segmentation 2 */
3588 case 112 ... 116: /* GMAC 2 */
3589 if (sky2->hw->ports == 1)
3590 goto reserved;
3591 /* fall through */
3592 case 0: /* Control */
3593 case 2: /* Mac address */
3594 case 4: /* Tx Arbiter 1 */
3595 case 7: /* PCI express reg */
3596 case 8: /* RX1 */
3597 case 12 ... 13: /* TX1 */
3598 case 16: case 18:/* Rx Ram Buffer 1 */
3599 case 20 ... 21: /* Tx Ram Buffer 1 */
3600 case 24: /* Rx MAC Fifo 1 */
3601 case 26: /* Tx MAC Fifo 1 */
3602 case 28 ... 29: /* Descriptor and status unit */
3603 case 30: /* GPHY 1*/
3604 case 32 ... 39: /* Pattern Ram 1 */
3605 case 48: case 50: /* TCP Segmentation 1 */
3606 case 56 ... 60: /* PCI space */
3607 case 80 ... 84: /* GMAC 1 */
3608 memcpy_fromio(p, io, 128);
3609 break;
3610 default:
3611reserved:
3612 memset(p, 0, 128);
3613 }
3ead5db7 3614
295b54c4
SH		 3615 p += 128;
3616 io += 128;
3617 }
793b883e 3618}
cd28ab6a 3619
b628ed98
SH		 3620/* In order to do Jumbo packets on these chips, need to turn off the
3621 * transmit store/forward. Therefore checksum offload won't work.
3622 */
3623static int no_tx_offload(struct net_device *dev)
3624{
3625 const struct sky2_port *sky2 = netdev_priv(dev);
3626 const struct sky2_hw *hw = sky2->hw;
3627
69161611 3628 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3629}
3630
3631static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3632{
3633 if (data && no_tx_offload(dev))
3634 return -EINVAL;
3635
3636 return ethtool_op_set_tx_csum(dev, data);
3637}
3638
3639
3640static int sky2_set_tso(struct net_device *dev, u32 data)
3641{
3642 if (data && no_tx_offload(dev))
3643 return -EINVAL;
3644
3645 return ethtool_op_set_tso(dev, data);
3646}
3647
f4331a6d
SH		 3648static int sky2_get_eeprom_len(struct net_device *dev)
3649{
3650 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3651 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3652 u16 reg2;
3653
b32f40c4 3654 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3655 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3656}
3657
b32f40c4 3658static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
f4331a6d 3659{
167f53d0 3660 u32 val;
f4331a6d 3661
b32f40c4 3662 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
167f53d0
SH		 3663
3664 do {
b32f40c4 3665 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0
SH		 3666 } while (!(offset & PCI_VPD_ADDR_F));
3667
b32f40c4 3668 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
167f53d0 3669 return val;
f4331a6d
SH		 3670}
3671
b32f40c4 3672static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
f4331a6d 3673{
b32f40c4
SH		 3674 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3675 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
f4331a6d 3676 do {
b32f40c4 3677 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0 3678 } while (offset & PCI_VPD_ADDR_F);
f4331a6d
SH		 3679}
3680
3681static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3682 u8 *data)
3683{
3684 struct sky2_port *sky2 = netdev_priv(dev);
3685 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3686 int length = eeprom->len;
3687 u16 offset = eeprom->offset;
3688
3689 if (!cap)
3690 return -EINVAL;
3691
3692 eeprom->magic = SKY2_EEPROM_MAGIC;
3693
3694 while (length > 0) {
b32f40c4 3695 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3696 int n = min_t(int, length, sizeof(val));
3697
3698 memcpy(data, &val, n);
3699 length -= n;
3700 data += n;
3701 offset += n;
3702 }
3703 return 0;
3704}
3705
3706static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3707 u8 *data)
3708{
3709 struct sky2_port *sky2 = netdev_priv(dev);
3710 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3711 int length = eeprom->len;
3712 u16 offset = eeprom->offset;
3713
3714 if (!cap)
3715 return -EINVAL;
3716
3717 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3718 return -EINVAL;
3719
3720 while (length > 0) {
3721 u32 val;
3722 int n = min_t(int, length, sizeof(val));
3723
3724 if (n < sizeof(val))
b32f40c4 3725 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3726 memcpy(&val, data, n);
3727
b32f40c4 3728 sky2_vpd_write(sky2->hw, cap, offset, val);
f4331a6d
SH		 3729
3730 length -= n;
3731 data += n;
3732 offset += n;
3733 }
3734 return 0;
3735}
3736
3737
7282d491 3738static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3739 .get_settings = sky2_get_settings,
3740 .set_settings = sky2_set_settings,
3741 .get_drvinfo = sky2_get_drvinfo,
3742 .get_wol = sky2_get_wol,
3743 .set_wol = sky2_set_wol,
3744 .get_msglevel = sky2_get_msglevel,
3745 .set_msglevel = sky2_set_msglevel,
3746 .nway_reset = sky2_nway_reset,
3747 .get_regs_len = sky2_get_regs_len,
3748 .get_regs = sky2_get_regs,
3749 .get_link = ethtool_op_get_link,
3750 .get_eeprom_len = sky2_get_eeprom_len,
3751 .get_eeprom = sky2_get_eeprom,
3752 .set_eeprom = sky2_set_eeprom,
f4331a6d 3753 .set_sg = ethtool_op_set_sg,
f4331a6d 3754 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3755 .set_tso = sky2_set_tso,
3756 .get_rx_csum = sky2_get_rx_csum,
3757 .set_rx_csum = sky2_set_rx_csum,
3758 .get_strings = sky2_get_strings,
3759 .get_coalesce = sky2_get_coalesce,
3760 .set_coalesce = sky2_set_coalesce,
3761 .get_ringparam = sky2_get_ringparam,
3762 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3763 .get_pauseparam = sky2_get_pauseparam,
3764 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3765 .phys_id = sky2_phys_id,
b9f2c044 3766 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3767 .get_ethtool_stats = sky2_get_ethtool_stats,
3768};
3769
3cf26753
SH		 3770#ifdef CONFIG_SKY2_DEBUG
3771
3772static struct dentry *sky2_debug;
3773
3774static int sky2_debug_show(struct seq_file *seq, void *v)
3775{
3776 struct net_device *dev = seq->private;
3777 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3778 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3779 unsigned port = sky2->port;
3780 unsigned idx, last;
3781 int sop;
3782
3783 if (!netif_running(dev))
3784 return -ENETDOWN;
3785
3786 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3787 sky2_read32(hw, B0_ISRC),
3788 sky2_read32(hw, B0_IMSK),
3789 sky2_read32(hw, B0_Y2_SP_ICR));
3790
bea3348e 3791 napi_disable(&hw->napi);
3cf26753
SH		 3792 last = sky2_read16(hw, STAT_PUT_IDX);
3793
3794 if (hw->st_idx == last)
3795 seq_puts(seq, "Status ring (empty)\n");
3796 else {
3797 seq_puts(seq, "Status ring\n");
3798 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3799 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3800 const struct sky2_status_le *le = hw->st_le + idx;
3801 seq_printf(seq, "[%d] %#x %d %#x\n",
3802 idx, le->opcode, le->length, le->status);
3803 }
3804 seq_puts(seq, "\n");
3805 }
3806
3807 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3808 sky2->tx_cons, sky2->tx_prod,
3809 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3810 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3811
3812 /* Dump contents of tx ring */
3813 sop = 1;
3814 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3815 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3816 const struct sky2_tx_le *le = sky2->tx_le + idx;
3817 u32 a = le32_to_cpu(le->addr);
3818
3819 if (sop)
3820 seq_printf(seq, "%u:", idx);
3821 sop = 0;
3822
3823 switch(le->opcode & ~HW_OWNER) {
3824 case OP_ADDR64:
3825 seq_printf(seq, " %#x:", a);
3826 break;
3827 case OP_LRGLEN:
3828 seq_printf(seq, " mtu=%d", a);
3829 break;
3830 case OP_VLAN:
3831 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3832 break;
3833 case OP_TCPLISW:
3834 seq_printf(seq, " csum=%#x", a);
3835 break;
3836 case OP_LARGESEND:
3837 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3838 break;
3839 case OP_PACKET:
3840 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3841 break;
3842 case OP_BUFFER:
3843 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3844 break;
3845 default:
3846 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3847 a, le16_to_cpu(le->length));
3848 }
3849
3850 if (le->ctrl & EOP) {
3851 seq_putc(seq, '\n');
3852 sop = 1;
3853 }
3854 }
3855
3856 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3857 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3858 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3859 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3860
bea3348e 3861 napi_enable(&hw->napi);
3cf26753
SH		 3862 return 0;
3863}
3864
3865static int sky2_debug_open(struct inode *inode, struct file *file)
3866{
3867 return single_open(file, sky2_debug_show, inode->i_private);
3868}
3869
3870static const struct file_operations sky2_debug_fops = {
3871 .owner = THIS_MODULE,
3872 .open = sky2_debug_open,
3873 .read = seq_read,
3874 .llseek = seq_lseek,
3875 .release = single_release,
3876};
3877
3878/*
3879 * Use network device events to create/remove/rename
3880 * debugfs file entries
3881 */
3882static int sky2_device_event(struct notifier_block *unused,
3883 unsigned long event, void *ptr)
3884{
3885 struct net_device *dev = ptr;
5b296bc9 3886 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 3887
5b296bc9
SH		 3888 if (dev->open != sky2_up || !sky2_debug)
3889 return NOTIFY_DONE;
3cf26753 3890
5b296bc9
SH		 3891 switch(event) {
3892 case NETDEV_CHANGENAME:
3893 if (sky2->debugfs) {
3894 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3895 sky2_debug, dev->name);
3896 }
3897 break;
3cf26753 3898
5b296bc9
SH		 3899 case NETDEV_GOING_DOWN:
3900 if (sky2->debugfs) {
3901 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3902 dev->name);
3903 debugfs_remove(sky2->debugfs);
3904 sky2->debugfs = NULL;
3cf26753 3905 }
5b296bc9
SH		 3906 break;
3907
3908 case NETDEV_UP:
3909 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3910 sky2_debug, dev,
3911 &sky2_debug_fops);
3912 if (IS_ERR(sky2->debugfs))
3913 sky2->debugfs = NULL;
3cf26753
SH		 3914 }
3915
3916 return NOTIFY_DONE;
3917}
3918
3919static struct notifier_block sky2_notifier = {
3920 .notifier_call = sky2_device_event,
3921};
3922
3923
3924static __init void sky2_debug_init(void)
3925{
3926 struct dentry *ent;
3927
3928 ent = debugfs_create_dir("sky2", NULL);
3929 if (!ent || IS_ERR(ent))
3930 return;
3931
3932 sky2_debug = ent;
3933 register_netdevice_notifier(&sky2_notifier);
3934}
3935
3936static __exit void sky2_debug_cleanup(void)
3937{
3938 if (sky2_debug) {
3939 unregister_netdevice_notifier(&sky2_notifier);
3940 debugfs_remove(sky2_debug);
3941 sky2_debug = NULL;
3942 }
3943}
3944
3945#else
3946#define sky2_debug_init()
3947#define sky2_debug_cleanup()
3948#endif
3949
3950
cd28ab6a
SH		 3951/* Initialize network device */
3952static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3953 unsigned port,
3954 int highmem, int wol)
cd28ab6a
SH		 3955{
3956 struct sky2_port *sky2;
3957 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3958
3959 if (!dev) {
898eb71c 3960 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 3961 return NULL;
3962 }
3963
cd28ab6a 3964 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3965 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3966 dev->open = sky2_up;
3967 dev->stop = sky2_down;
ef743d33 3968 dev->do_ioctl = sky2_ioctl;
cd28ab6a 3969 dev->hard_start_xmit = sky2_xmit_frame;
cd28ab6a
SH		 3970 dev->set_multicast_list = sky2_set_multicast;
3971 dev->set_mac_address = sky2_set_mac_address;
3972 dev->change_mtu = sky2_change_mtu;
3973 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3974 dev->tx_timeout = sky2_tx_timeout;
3975 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 3976#ifdef CONFIG_NET_POLL_CONTROLLER
a5e68c02
SH		 3977 if (port == 0)
3978 dev->poll_controller = sky2_netpoll;
cd28ab6a 3979#endif
cd28ab6a
SH		 3980
3981 sky2 = netdev_priv(dev);
3982 sky2->netdev = dev;
3983 sky2->hw = hw;
3984 sky2->msg_enable = netif_msg_init(debug, default_msg);
3985
cd28ab6a
SH		 3986 /* Auto speed and flow control */
3987 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3988 sky2->flow_mode = FC_BOTH;
3989
cd28ab6a
SH		 3990 sky2->duplex = -1;
3991 sky2->speed = -1;
3992 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 3993 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
e3173832 3994 sky2->wol = wol;
75d070c5 3995
e07b1aa8 3996 spin_lock_init(&sky2->phy_lock);
793b883e 3997 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3998 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3999
4000 hw->dev[port] = dev;
4001
4002 sky2->port = port;
4003
4a50a876 4004 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4005 if (highmem)
4006 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4007
d1f13708 4008#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4009 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4010 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4011 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4012 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4013 dev->vlan_rx_register = sky2_vlan_rx_register;
4014 }
d1f13708
SH		 4015#endif
4016
cd28ab6a 4017 /* read the mac address */
793b883e 4018 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4019 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4020
cd28ab6a
SH		 4021 return dev;
4022}
4023
28bd181a 4024static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4025{
4026 const struct sky2_port *sky2 = netdev_priv(dev);
0795af57 4027 DECLARE_MAC_BUF(mac);
cd28ab6a
SH		 4028
4029 if (netif_msg_probe(sky2))
0795af57
JP		 4030 printk(KERN_INFO PFX "%s: addr %s\n",
4031 dev->name, print_mac(mac, dev->dev_addr));
cd28ab6a
SH		 4032}
4033
fb2690a9 4034/* Handle software interrupt used during MSI test */
7d12e780 4035static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4036{
4037 struct sky2_hw *hw = dev_id;
4038 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4039
4040 if (status == 0)
4041 return IRQ_NONE;
4042
4043 if (status & Y2_IS_IRQ_SW) {
ea76e635 4044 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4045 wake_up(&hw->msi_wait);
4046 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4047 }
4048 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4049
4050 return IRQ_HANDLED;
4051}
4052
4053/* Test interrupt path by forcing a a software IRQ */
4054static int __devinit sky2_test_msi(struct sky2_hw *hw)
4055{
4056 struct pci_dev *pdev = hw->pdev;
4057 int err;
4058
bb507fe1
SH		 4059 init_waitqueue_head (&hw->msi_wait);
4060
fb2690a9
SH		 4061 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4062
b0a20ded 4063 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4064 if (err) {
b02a9258 4065 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4066 return err;
4067 }
4068
fb2690a9 4069 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4070 sky2_read8(hw, B0_CTST);
fb2690a9 4071
ea76e635 4072 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4073
ea76e635 4074 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4075 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4076 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4077 "switching to INTx mode.\n");
fb2690a9
SH		 4078
4079 err = -EOPNOTSUPP;
4080 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4081 }
4082
4083 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4084 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4085
4086 free_irq(pdev->irq, hw);
4087
4088 return err;
4089}
4090
e3173832
SH		 4091static int __devinit pci_wake_enabled(struct pci_dev *dev)
4092{
4093 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4094 u16 value;
4095
4096 if (!pm)
4097 return 0;
4098 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4099 return 0;
4100 return value & PCI_PM_CTRL_PME_ENABLE;
4101}
4102
cd28ab6a
SH		 4103static int __devinit sky2_probe(struct pci_dev *pdev,
4104 const struct pci_device_id *ent)
4105{
7f60c64b 4106 struct net_device *dev;
cd28ab6a 4107 struct sky2_hw *hw;
e3173832 4108 int err, using_dac = 0, wol_default;
cd28ab6a 4109
793b883e
SH		 4110 err = pci_enable_device(pdev);
4111 if (err) {
b02a9258 4112 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4113 goto err_out;
4114 }
4115
793b883e
SH		 4116 err = pci_request_regions(pdev, DRV_NAME);
4117 if (err) {
b02a9258 4118 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4119 goto err_out_disable;
cd28ab6a
SH		 4120 }
4121
4122 pci_set_master(pdev);
4123
d1f3d4dd
SH		 4124 if (sizeof(dma_addr_t) > sizeof(u32) &&
4125 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4126 using_dac = 1;
4127 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4128 if (err < 0) {
b02a9258
SH		 4129 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4130 "for consistent allocations\n");
d1f3d4dd
SH		 4131 goto err_out_free_regions;
4132 }
d1f3d4dd 4133 } else {
cd28ab6a
SH		 4134 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4135 if (err) {
b02a9258 4136 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4137 goto err_out_free_regions;
4138 }
4139 }
d1f3d4dd 4140
e3173832
SH		 4141 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4142
cd28ab6a 4143 err = -ENOMEM;
6aad85d6 4144 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4145 if (!hw) {
b02a9258 4146 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4147 goto err_out_free_regions;
4148 }
4149
cd28ab6a 4150 hw->pdev = pdev;
cd28ab6a
SH		 4151
4152 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4153 if (!hw->regs) {
b02a9258 4154 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4155 goto err_out_free_hw;
4156 }
4157
56a645cc 4158#ifdef __BIG_ENDIAN
f65b138c
SH		 4159 /* The sk98lin vendor driver uses hardware byte swapping but
4160 * this driver uses software swapping.
4161 */
56a645cc
SH		 4162 {
4163 u32 reg;
b32f40c4 4164 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4165 reg &= ~PCI_REV_DESC;
b32f40c4 4166 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
56a645cc
SH		 4167 }
4168#endif
4169
08c06d8a 4170 /* ring for status responses */
167f53d0 4171 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4172 if (!hw->st_le)
4173 goto err_out_iounmap;
4174
e3173832 4175 err = sky2_init(hw);
cd28ab6a 4176 if (err)
793b883e 4177 goto err_out_iounmap;
cd28ab6a 4178
b02a9258 4179 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4180 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4181 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4182 hw->chip_id, hw->chip_rev);
cd28ab6a 4183
e3173832
SH		 4184 sky2_reset(hw);
4185
4186 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4187 if (!dev) {
4188 err = -ENOMEM;
cd28ab6a 4189 goto err_out_free_pci;
7f60c64b 4190 }
cd28ab6a 4191
9fa1b1f3
SH		 4192 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4193 err = sky2_test_msi(hw);
4194 if (err == -EOPNOTSUPP)
4195 pci_disable_msi(pdev);
4196 else if (err)
4197 goto err_out_free_netdev;
4198 }
4199
793b883e
SH		 4200 err = register_netdev(dev);
4201 if (err) {
b02a9258 4202 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4203 goto err_out_free_netdev;
4204 }
4205
6de16237
SH		 4206 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4207
ea76e635
SH		 4208 err = request_irq(pdev->irq, sky2_intr,
4209 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4210 dev->name, hw);
9fa1b1f3 4211 if (err) {
b02a9258 4212 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4213 goto err_out_unregister;
4214 }
4215 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4216 napi_enable(&hw->napi);
9fa1b1f3 4217
cd28ab6a
SH		 4218 sky2_show_addr(dev);
4219
7f60c64b 4220 if (hw->ports > 1) {
4221 struct net_device *dev1;
4222
e3173832 4223 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4224 if (!dev1)
4225 dev_warn(&pdev->dev, "allocation for second device failed\n");
4226 else if ((err = register_netdev(dev1))) {
4227 dev_warn(&pdev->dev,
4228 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4229 hw->dev[1] = NULL;
4230 free_netdev(dev1);
b02a9258
SH		 4231 } else
4232 sky2_show_addr(dev1);
cd28ab6a
SH		 4233 }
4234
32c2c300 4235 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4236 INIT_WORK(&hw->restart_work, sky2_restart);
4237
793b883e
SH		 4238 pci_set_drvdata(pdev, hw);
4239
cd28ab6a
SH		 4240 return 0;
4241
793b883e 4242err_out_unregister:
ea76e635 4243 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4244 pci_disable_msi(pdev);
793b883e 4245 unregister_netdev(dev);
cd28ab6a
SH		 4246err_out_free_netdev:
4247 free_netdev(dev);
cd28ab6a 4248err_out_free_pci:
793b883e 4249 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4250 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4251err_out_iounmap:
4252 iounmap(hw->regs);
4253err_out_free_hw:
4254 kfree(hw);
4255err_out_free_regions:
4256 pci_release_regions(pdev);
44a1d2e5 4257err_out_disable:
cd28ab6a 4258 pci_disable_device(pdev);
cd28ab6a 4259err_out:
549a68c3 4260 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4261 return err;
4262}
4263
4264static void __devexit sky2_remove(struct pci_dev *pdev)
4265{
793b883e 4266 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4267 int i;
cd28ab6a 4268
793b883e 4269 if (!hw)
cd28ab6a
SH		 4270 return;
4271
32c2c300 4272 del_timer_sync(&hw->watchdog_timer);
6de16237 4273 cancel_work_sync(&hw->restart_work);
d27ed387 4274
b877fe28 4275 for (i = hw->ports-1; i >= 0; --i)
6de16237 4276 unregister_netdev(hw->dev[i]);
81906791 4277
d27ed387 4278 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4279
ae306cca
SH		 4280 sky2_power_aux(hw);
4281
cd28ab6a 4282 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4283 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4284 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4285
4286 free_irq(pdev->irq, hw);
ea76e635 4287 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4288 pci_disable_msi(pdev);
793b883e 4289 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4290 pci_release_regions(pdev);
4291 pci_disable_device(pdev);
793b883e 4292
b877fe28 4293 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4294 free_netdev(hw->dev[i]);
4295
cd28ab6a
SH		 4296 iounmap(hw->regs);
4297 kfree(hw);
5afa0a9c 4298
cd28ab6a
SH		 4299 pci_set_drvdata(pdev, NULL);
4300}
4301
4302#ifdef CONFIG_PM
4303static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4304{
793b883e 4305 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4306 int i, wol = 0;
cd28ab6a 4307
549a68c3
SH		 4308 if (!hw)
4309 return 0;
4310
f05267e7 4311 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4312 struct net_device *dev = hw->dev[i];
e3173832 4313 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4314
e3173832 4315 if (netif_running(dev))
5afa0a9c 4316 sky2_down(dev);
e3173832
SH		 4317
4318 if (sky2->wol)
4319 sky2_wol_init(sky2);
4320
4321 wol |= sky2->wol;
cd28ab6a
SH		 4322 }
4323
8ab8fca2 4324 sky2_write32(hw, B0_IMSK, 0);
6de16237 4325 napi_disable(&hw->napi);
ae306cca 4326 sky2_power_aux(hw);
e3173832 4327
d374c1c1 4328 pci_save_state(pdev);
e3173832 4329 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4330 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4331
2ccc99b7 4332 return 0;
cd28ab6a
SH		 4333}
4334
4335static int sky2_resume(struct pci_dev *pdev)
4336{
793b883e 4337 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4338 int i, err;
cd28ab6a 4339
549a68c3
SH		 4340 if (!hw)
4341 return 0;
4342
ae306cca
SH		 4343 err = pci_set_power_state(pdev, PCI_D0);
4344 if (err)
4345 goto out;
4346
4347 err = pci_restore_state(pdev);
4348 if (err)
4349 goto out;
4350
cd28ab6a 4351 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4352
4353 /* Re-enable all clocks */
05745c4a
SH		 4354 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4355 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4356 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4357 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4358
e3173832 4359 sky2_reset(hw);
8ab8fca2 4360 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4361 napi_enable(&hw->napi);
8ab8fca2 4362
f05267e7 4363 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4364 struct net_device *dev = hw->dev[i];
6a5706b9 4365 if (netif_running(dev)) {
08c06d8a
SH		 4366 err = sky2_up(dev);
4367 if (err) {
4368 printk(KERN_ERR PFX "%s: could not up: %d\n",
4369 dev->name, err);
4370 dev_close(dev);
eb35cf60 4371 goto out;
5afa0a9c 4372 }
d1b139c0
SH		 4373
4374 sky2_set_multicast(dev);
cd28ab6a
SH		 4375 }
4376 }
eb35cf60 4377
ae306cca 4378 return 0;
08c06d8a 4379out:
b02a9258 4380 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4381 pci_disable_device(pdev);
08c06d8a 4382 return err;
cd28ab6a
SH		 4383}
4384#endif
4385
e3173832
SH		 4386static void sky2_shutdown(struct pci_dev *pdev)
4387{
4388 struct sky2_hw *hw = pci_get_drvdata(pdev);
4389 int i, wol = 0;
4390
549a68c3
SH		 4391 if (!hw)
4392 return;
4393
5c0d6b34 4394 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4395
4396 for (i = 0; i < hw->ports; i++) {
4397 struct net_device *dev = hw->dev[i];
4398 struct sky2_port *sky2 = netdev_priv(dev);
4399
4400 if (sky2->wol) {
4401 wol = 1;
4402 sky2_wol_init(sky2);
4403 }
4404 }
4405
4406 if (wol)
4407 sky2_power_aux(hw);
4408
4409 pci_enable_wake(pdev, PCI_D3hot, wol);
4410 pci_enable_wake(pdev, PCI_D3cold, wol);
4411
4412 pci_disable_device(pdev);
4413 pci_set_power_state(pdev, PCI_D3hot);
4414
4415}
4416
cd28ab6a 4417static struct pci_driver sky2_driver = {
793b883e
SH		 4418 .name = DRV_NAME,
4419 .id_table = sky2_id_table,
4420 .probe = sky2_probe,
4421 .remove = __devexit_p(sky2_remove),
cd28ab6a 4422#ifdef CONFIG_PM
793b883e
SH		 4423 .suspend = sky2_suspend,
4424 .resume = sky2_resume,
cd28ab6a 4425#endif
e3173832 4426 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4427};
4428
4429static int __init sky2_init_module(void)
4430{
3cf26753 4431 sky2_debug_init();
50241c4c 4432 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4433}
4434
4435static void __exit sky2_cleanup_module(void)
4436{
4437 pci_unregister_driver(&sky2_driver);
3cf26753 4438 sky2_debug_cleanup();
cd28ab6a
SH		 4439}
4440
4441module_init(sky2_init_module);
4442module_exit(sky2_cleanup_module);
4443
4444MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4445MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4446MODULE_LICENSE("GPL");
5f4f9dc1 4447MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree