]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/sky2.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sky2: add XL revisions
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
ada1db5c
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
793b883e 27#include <linux/crc32.h>
cd28ab6a 28#include <linux/kernel.h>
cd28ab6a
SH		 29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
c9bdd4b5 36#include <net/ip.h>
cd28ab6a
SH		 37#include <linux/tcp.h>
38#include <linux/in.h>
39#include <linux/delay.h>
91c86df5 40#include <linux/workqueue.h>
d1f13708 41#include <linux/if_vlan.h>
d70cd51a 42#include <linux/prefetch.h>
3cf26753 43#include <linux/debugfs.h>
ef743d33 44#include <linux/mii.h>
cd28ab6a
SH		 45
46#include <asm/irq.h>
47
d1f13708
SH		 48#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49#define SKY2_VLAN_TAG_USED 1
50#endif
51
cd28ab6a
SH		 52#include "sky2.h"
53
54#define DRV_NAME "sky2"
cfc0861b 55#define DRV_VERSION "1.27"
cd28ab6a
SH		 56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 67
ee5f68fe 68/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 69 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
70#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 71#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
ee5f68fe
SH		 72#define TX_MAX_PENDING 4096
73#define TX_DEF_PENDING 127
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 77#define TX_WATCHDOG (5 * HZ)
78#define NAPI_WEIGHT 64
79#define PHY_RETRIES 1000
80
f4331a6d
SH		 81#define SKY2_EEPROM_MAGIC 0x9955aabb
82
83
cb5d9547
SH		 84#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85
cd28ab6a 86static const u32 default_msg =
793b883e
SH		 87 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
88 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 89 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 90
793b883e 91static int debug = -1; /* defaults above */
cd28ab6a
SH		 92module_param(debug, int, 0);
93MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
14d0263f 95static int copybreak __read_mostly = 128;
bdb5c58e
SH		 96module_param(copybreak, int, 0);
97MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98
fb2690a9
SH		 99static int disable_msi = 0;
100module_param(disable_msi, int, 0);
101MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102
e6cac9ba 103static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 144 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 145 { 0 }
146};
793b883e 147
cd28ab6a
SH		 148MODULE_DEVICE_TABLE(pci, sky2_id_table);
149
150/* Avoid conditionals by using array */
151static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
152static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 153static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 154
d1b139c0
SH		 155static void sky2_set_multicast(struct net_device *dev);
156
af043aa5 157/* Access to PHY via serial interconnect */
ef743d33 158static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 159{
160 int i;
161
162 gma_write16(hw, port, GM_SMI_DATA, val);
163 gma_write16(hw, port, GM_SMI_CTRL,
164 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
165
166 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 167 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
168 if (ctrl == 0xffff)
169 goto io_error;
170
171 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 172 return 0;
af043aa5
SH		 173
174 udelay(10);
cd28ab6a 175 }
ef743d33 176
af043aa5 177 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 178 return -ETIMEDOUT;
af043aa5
SH		 179
180io_error:
181 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
182 return -EIO;
cd28ab6a
SH		 183}
184
ef743d33 185static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 186{
187 int i;
188
793b883e 189 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 190 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
191
192 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 193 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
194 if (ctrl == 0xffff)
195 goto io_error;
196
197 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 198 *val = gma_read16(hw, port, GM_SMI_DATA);
199 return 0;
200 }
201
af043aa5 202 udelay(10);
cd28ab6a
SH		 203 }
204
af043aa5 205 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 206 return -ETIMEDOUT;
af043aa5
SH		 207io_error:
208 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
209 return -EIO;
ef743d33
SH		 210}
211
af043aa5 212static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 213{
214 u16 v;
af043aa5 215 __gm_phy_read(hw, port, reg, &v);
ef743d33 216 return v;
cd28ab6a
SH		 217}
218
5afa0a9c 219
ae306cca
SH		 220static void sky2_power_on(struct sky2_hw *hw)
221{
222 /* switch power to VCC (WA for VAUX problem) */
223 sky2_write8(hw, B0_POWER_CTRL,
224 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 225
ae306cca
SH		 226 /* disable Core Clock Division, */
227 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 228
4b7c47aa 229 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 230 /* enable bits are inverted */
231 sky2_write8(hw, B2_Y2_CLK_GATE,
232 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
233 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
234 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
235 else
236 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 237
ea76e635 238 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 239 u32 reg;
5afa0a9c 240
b32f40c4 241 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 242
b32f40c4 243 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 244 /* set all bits to 0 except bits 15..12 and 8 */
245 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 247
b32f40c4 248 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 249 /* set all bits to 0 except bits 28 & 27 */
250 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 251 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 252
b32f40c4 253 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 254
5f8ae5c5 255 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
256
8f70920f
SH		 257 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
258 reg = sky2_read32(hw, B2_GP_IO);
259 reg |= GLB_GPIO_STAT_RACE_DIS;
260 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 261
262 sky2_read32(hw, B2_GP_IO);
5afa0a9c 263 }
10547ae2
SH		 264
265 /* Turn on "driver loaded" LED */
266 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 267}
5afa0a9c 268
ae306cca
SH		 269static void sky2_power_aux(struct sky2_hw *hw)
270{
4b7c47aa 271 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 272 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
273 else
274 /* enable bits are inverted */
275 sky2_write8(hw, B2_Y2_CLK_GATE,
276 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
277 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
278 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
279
c23ddf8f
SH		 280 /* switch power to VAUX if supported and PME from D3cold */
281 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
282 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 283 sky2_write8(hw, B0_POWER_CTRL,
284 (PC_VAUX_ENA | PC_VCC_ENA |
285 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 286
287 /* turn off "driver loaded LED" */
288 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c
SH		 289}
290
d3bcfbeb 291static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 292{
293 u16 reg;
294
295 /* disable all GMAC IRQ's */
296 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 297
cd28ab6a
SH		 298 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
299 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
300 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
301 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
302
303 reg = gma_read16(hw, port, GM_RX_CTRL);
304 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
305 gma_write16(hw, port, GM_RX_CTRL, reg);
306}
307
16ad91e1
SH		 308/* flow control to advertise bits */
309static const u16 copper_fc_adv[] = {
310 [FC_NONE] = 0,
311 [FC_TX] = PHY_M_AN_ASP,
312 [FC_RX] = PHY_M_AN_PC,
313 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
314};
315
316/* flow control to advertise bits when using 1000BaseX */
317static const u16 fiber_fc_adv[] = {
df3fe1f3 318 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 319 [FC_TX] = PHY_M_P_ASYM_MD_X,
320 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 321 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 322};
323
324/* flow control to GMA disable bits */
325static const u16 gm_fc_disable[] = {
326 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
327 [FC_TX] = GM_GPCR_FC_RX_DIS,
328 [FC_RX] = GM_GPCR_FC_TX_DIS,
329 [FC_BOTH] = 0,
330};
331
332
cd28ab6a
SH		 333static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
334{
335 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 336 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 337
0ea065e5 338 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 339 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 340 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
341
342 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 343 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 344 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
345
53419c68 346 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 347 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 348 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 349 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
350 else
53419c68
SH		 351 /* set master & slave downshift counter to 1x */
352 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 353
354 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
355 }
356
357 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 358 if (sky2_is_copper(hw)) {
05745c4a 359 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 360 /* enable automatic crossover */
361 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 362
363 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
364 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
365 u16 spec;
366
367 /* Enable Class A driver for FE+ A0 */
368 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
369 spec |= PHY_M_FESC_SEL_CL_A;
370 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
371 }
cd28ab6a
SH		 372 } else {
373 /* disable energy detect */
374 ctrl &= ~PHY_M_PC_EN_DET_MSK;
375
376 /* enable automatic crossover */
377 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
378
53419c68 379 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 380 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
381 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 382 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 383 ctrl &= ~PHY_M_PC_DSC_MSK;
384 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
385 }
386 }
cd28ab6a
SH		 387 } else {
388 /* workaround for deviation #4.88 (CRC errors) */
389 /* disable Automatic Crossover */
390
391 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 392 }
cd28ab6a 393
b89165f2
SH		 394 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
395
396 /* special setup for PHY 88E1112 Fiber */
ea76e635 397 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 398 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 399
b89165f2
SH		 400 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
401 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
402 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
403 ctrl &= ~PHY_M_MAC_MD_MSK;
404 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
405 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
406
407 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 408 /* select page 1 to access Fiber registers */
409 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 410
411 /* for SFP-module set SIGDET polarity to low */
412 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
413 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 414 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 415 }
b89165f2
SH		 416
417 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 418 }
419
7800fddc 420 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 421 ct1000 = 0;
422 adv = PHY_AN_CSMA;
2eaba1a2 423 reg = 0;
cd28ab6a 424
0ea065e5 425 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 426 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 427 if (sky2->advertising & ADVERTISED_1000baseT_Full)
428 ct1000 |= PHY_M_1000C_AFD;
429 if (sky2->advertising & ADVERTISED_1000baseT_Half)
430 ct1000 |= PHY_M_1000C_AHD;
431 if (sky2->advertising & ADVERTISED_100baseT_Full)
432 adv |= PHY_M_AN_100_FD;
433 if (sky2->advertising & ADVERTISED_100baseT_Half)
434 adv |= PHY_M_AN_100_HD;
435 if (sky2->advertising & ADVERTISED_10baseT_Full)
436 adv |= PHY_M_AN_10_FD;
437 if (sky2->advertising & ADVERTISED_10baseT_Half)
438 adv |= PHY_M_AN_10_HD;
709c6e7b 439
b89165f2
SH		 440 } else { /* special defines for FIBER (88E1040S only) */
441 if (sky2->advertising & ADVERTISED_1000baseT_Full)
442 adv |= PHY_M_AN_1000X_AFD;
443 if (sky2->advertising & ADVERTISED_1000baseT_Half)
444 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 445 }
cd28ab6a
SH		 446
447 /* Restart Auto-negotiation */
448 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
449 } else {
450 /* forced speed/duplex settings */
451 ct1000 = PHY_M_1000C_MSE;
452
0ea065e5
SH		 453 /* Disable auto update for duplex flow control and duplex */
454 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 455
456 switch (sky2->speed) {
457 case SPEED_1000:
458 ctrl |= PHY_CT_SP1000;
2eaba1a2 459 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 460 break;
461 case SPEED_100:
462 ctrl |= PHY_CT_SP100;
2eaba1a2 463 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 464 break;
465 }
466
2eaba1a2
SH		 467 if (sky2->duplex == DUPLEX_FULL) {
468 reg |= GM_GPCR_DUP_FULL;
469 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 470 } else if (sky2->speed < SPEED_1000)
471 sky2->flow_mode = FC_NONE;
0ea065e5 472 }
2eaba1a2 473
0ea065e5
SH		 474 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
475 if (sky2_is_copper(hw))
476 adv |= copper_fc_adv[sky2->flow_mode];
477 else
478 adv |= fiber_fc_adv[sky2->flow_mode];
479 } else {
480 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 481 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 482
483 /* Forward pause packets to GMAC? */
16ad91e1 484 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 485 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
486 else
487 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 488 }
489
2eaba1a2
SH		 490 gma_write16(hw, port, GM_GP_CTRL, reg);
491
05745c4a 492 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 493 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
494
495 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
496 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
497
498 /* Setup Phy LED's */
499 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
500 ledover = 0;
501
502 switch (hw->chip_id) {
503 case CHIP_ID_YUKON_FE:
504 /* on 88E3082 these bits are at 11..9 (shifted left) */
505 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
506
507 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
508
509 /* delete ACT LED control bits */
510 ctrl &= ~PHY_M_FELP_LED1_MSK;
511 /* change ACT LED control to blink mode */
512 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
513 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
514 break;
515
05745c4a
SH		 516 case CHIP_ID_YUKON_FE_P:
517 /* Enable Link Partner Next Page */
518 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
519 ctrl |= PHY_M_PC_ENA_LIP_NP;
520
521 /* disable Energy Detect and enable scrambler */
522 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
523 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
524
525 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
526 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
527 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
528 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
529
530 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
531 break;
532
cd28ab6a 533 case CHIP_ID_YUKON_XL:
793b883e 534 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 535
536 /* select page 3 to access LED control register */
537 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
538
539 /* set LED Function Control register */
ed6d32c7
SH		 540 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
541 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
542 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
543 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
544 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 545
546 /* set Polarity Control register */
547 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 548 (PHY_M_POLC_LS1_P_MIX(4) |
549 PHY_M_POLC_IS0_P_MIX(4) |
550 PHY_M_POLC_LOS_CTRL(2) |
551 PHY_M_POLC_INIT_CTRL(2) |
552 PHY_M_POLC_STA1_CTRL(2) |
553 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 554
555 /* restore page register */
793b883e 556 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 557 break;
93745494 558
ed6d32c7 559 case CHIP_ID_YUKON_EC_U:
93745494 560 case CHIP_ID_YUKON_EX:
ed4d4161 561 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 562 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
563
564 /* select page 3 to access LED control register */
565 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
566
567 /* set LED Function Control register */
568 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
569 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
570 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
571 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
572 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
573
574 /* set Blink Rate in LED Timer Control Register */
575 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
576 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
577 /* restore page register */
578 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
579 break;
cd28ab6a
SH		 580
581 default:
582 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
583 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 584
cd28ab6a 585 /* turn off the Rx LED (LED_RX) */
a84d0a3d 586 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 587 }
588
0ce8b98d 589 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 590 /* apply fixes in PHY AFE */
ed6d32c7
SH		 591 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
592
977bdf06 593 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 594 gm_phy_write(hw, port, 0x18, 0xaa99);
595 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 596
0ce8b98d
SH		 597 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
598 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
599 gm_phy_write(hw, port, 0x18, 0xa204);
600 gm_phy_write(hw, port, 0x17, 0x2002);
601 }
977bdf06
SH		 602
603 /* set page register to 0 */
9467a8fc 604 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 605 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
606 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
607 /* apply workaround for integrated resistors calibration */
608 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
609 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 610 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
611 /* apply fixes in PHY AFE */
612 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
613
614 /* apply RDAC termination workaround */
615 gm_phy_write(hw, port, 24, 0x2800);
616 gm_phy_write(hw, port, 23, 0x2001);
617
618 /* set page register back to 0 */
619 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 620 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
621 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 622 /* no effect on Yukon-XL */
977bdf06 623 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 624
8e95a202
JP		 625 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
626 sky2->speed == SPEED_100) {
977bdf06 627 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 628 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 629 }
cd28ab6a 630
977bdf06
SH		 631 if (ledover)
632 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
633
634 }
2eaba1a2 635
d571b694 636 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 637 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 638 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
639 else
640 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
641}
642
b96936da
SH		 643static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
644static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
645
646static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 647{
648 u32 reg1;
d3bcfbeb 649
a40ccc68 650 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 651 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 652 reg1 &= ~phy_power[port];
d3bcfbeb 653
4b7c47aa 654 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ff35164e
SH		 655 reg1 |= coma_mode[port];
656
b32f40c4 657 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 658 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 659 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 660
661 if (hw->chip_id == CHIP_ID_YUKON_FE)
662 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
663 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
664 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 665}
167f53d0 666
b96936da
SH		 667static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
668{
669 u32 reg1;
db99b988
SH		 670 u16 ctrl;
671
672 /* release GPHY Control reset */
673 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
674
675 /* release GMAC reset */
676 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
677
678 if (hw->flags & SKY2_HW_NEWER_PHY) {
679 /* select page 2 to access MAC control register */
680 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
681
682 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
683 /* allow GMII Power Down */
684 ctrl &= ~PHY_M_MAC_GMIF_PUP;
685 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
686
687 /* set page register back to 0 */
688 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
689 }
690
691 /* setup General Purpose Control Register */
692 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 693 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
694 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
695 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 696
697 if (hw->chip_id != CHIP_ID_YUKON_EC) {
698 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 699 /* select page 2 to access MAC control register */
700 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 701
e484d5f5 702 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 703 /* enable Power Down */
704 ctrl |= PHY_M_PC_POW_D_ENA;
705 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 706
707 /* set page register back to 0 */
708 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 709 }
710
711 /* set IEEE compatible Power Down Mode (dev. #4.99) */
712 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
713 }
b96936da 714
a40ccc68 715 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 716 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 717 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 718 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 719 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 720}
721
1b537565
SH		 722/* Force a renegotiation */
723static void sky2_phy_reinit(struct sky2_port *sky2)
724{
e07b1aa8 725 spin_lock_bh(&sky2->phy_lock);
1b537565 726 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 727 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 728}
729
e3173832
SH		 730/* Put device in state to listen for Wake On Lan */
731static void sky2_wol_init(struct sky2_port *sky2)
732{
733 struct sky2_hw *hw = sky2->hw;
734 unsigned port = sky2->port;
735 enum flow_control save_mode;
736 u16 ctrl;
e3173832
SH		 737
738 /* Bring hardware out of reset */
739 sky2_write16(hw, B0_CTST, CS_RST_CLR);
740 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
741
742 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
743 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
744
745 /* Force to 10/100
746 * sky2_reset will re-enable on resume
747 */
748 save_mode = sky2->flow_mode;
749 ctrl = sky2->advertising;
750
751 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
752 sky2->flow_mode = FC_NONE;
b96936da
SH		 753
754 spin_lock_bh(&sky2->phy_lock);
755 sky2_phy_power_up(hw, port);
756 sky2_phy_init(hw, port);
757 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 758
759 sky2->flow_mode = save_mode;
760 sky2->advertising = ctrl;
761
762 /* Set GMAC to no flow control and auto update for speed/duplex */
763 gma_write16(hw, port, GM_GP_CTRL,
764 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
765 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
766
767 /* Set WOL address */
768 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
769 sky2->netdev->dev_addr, ETH_ALEN);
770
771 /* Turn on appropriate WOL control bits */
772 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
773 ctrl = 0;
774 if (sky2->wol & WAKE_PHY)
775 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
776 else
777 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
778
779 if (sky2->wol & WAKE_MAGIC)
780 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
781 else
a419aef8 782 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 783
784 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
785 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
786
5f8ae5c5 787 /* Disable PiG firmware */
788 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
789
e3173832
SH		 790 /* block receiver */
791 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
e3173832
SH		 792}
793
69161611
SH		 794static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
795{
05745c4a
SH		 796 struct net_device *dev = hw->dev[port];
797
ed4d4161
SH		 798 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
799 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 800 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161 801 /* Yukon-Extreme B0 and further Extreme devices */
44dde56d 802 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
803 } else if (dev->mtu > ETH_DATA_LEN) {
804 /* set Tx GMAC FIFO Almost Empty Threshold */
805 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
806 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
05745c4a 807
44dde56d 808 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
809 } else
810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
69161611
SH		 811}
812
cd28ab6a
SH		 813static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
814{
815 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
816 u16 reg;
25cccecc 817 u32 rx_reg;
cd28ab6a
SH		 818 int i;
819 const u8 *addr = hw->dev[port]->dev_addr;
820
f350339c
SH		 821 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
822 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 823
824 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
825
4b7c47aa 826 if (hw->chip_id == CHIP_ID_YUKON_XL &&
827 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
828 port == 1) {
cd28ab6a
SH		 829 /* WA DEV_472 -- looks like crossed wires on port 2 */
830 /* clear GMAC 1 Control reset */
831 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
832 do {
833 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
834 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
835 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
836 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
837 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
838 }
839
793b883e 840 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 841
2eaba1a2
SH		 842 /* Enable Transmit FIFO Underrun */
843 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
844
e07b1aa8 845 spin_lock_bh(&sky2->phy_lock);
b96936da 846 sky2_phy_power_up(hw, port);
cd28ab6a 847 sky2_phy_init(hw, port);
e07b1aa8 848 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 849
850 /* MIB clear */
851 reg = gma_read16(hw, port, GM_PHY_ADDR);
852 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
853
43f2f104
SH		 854 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
855 gma_read16(hw, port, i);
cd28ab6a
SH		 856 gma_write16(hw, port, GM_PHY_ADDR, reg);
857
858 /* transmit control */
859 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
860
861 /* receive control reg: unicast + multicast + no FCS */
862 gma_write16(hw, port, GM_RX_CTRL,
793b883e 863 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 864
865 /* transmit flow control */
866 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
867
868 /* transmit parameter */
869 gma_write16(hw, port, GM_TX_PARAM,
870 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
871 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
872 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
873 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
874
875 /* serial mode register */
876 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 877 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 878
6b1a3aef 879 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 880 reg |= GM_SMOD_JUMBO_ENA;
881
c1cd0a85 882 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
883 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
884 reg |= GM_NEW_FLOW_CTRL;
885
cd28ab6a
SH		 886 gma_write16(hw, port, GM_SERIAL_MODE, reg);
887
cd28ab6a
SH		 888 /* virtual address for data */
889 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
890
793b883e
SH		 891 /* physical address: used for pause frames */
892 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
893
894 /* ignore counter overflows */
cd28ab6a
SH		 895 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
896 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
897 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
898
899 /* Configure Rx MAC FIFO */
900 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 901 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 902 if (hw->chip_id == CHIP_ID_YUKON_EX ||
903 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 904 rx_reg |= GMF_RX_OVER_ON;
69161611 905
25cccecc 906 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 907
798fdd07
SH		 908 if (hw->chip_id == CHIP_ID_YUKON_XL) {
909 /* Hardware errata - clear flush mask */
910 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
911 } else {
912 /* Flush Rx MAC FIFO on any flow control or error */
913 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
914 }
cd28ab6a 915
8df9a876 916 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 917 reg = RX_GMF_FL_THR_DEF + 1;
918 /* Another magic mystery workaround from sk98lin */
919 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
920 hw->chip_rev == CHIP_REV_YU_FE2_A0)
921 reg = 0x178;
922 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 923
924 /* Configure Tx MAC FIFO */
925 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
926 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 927
e0c28116 928 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 929 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 930 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 931 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
932 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 933 reg = 1568 / 8;
934 else
935 reg = 1024 / 8;
936 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
937 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 938
69161611 939 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 940 }
941
e970d1f8
SH		 942 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
943 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
944 /* disable dynamic watermark */
945 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
946 reg &= ~TX_DYN_WM_ENA;
947 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
948 }
cd28ab6a
SH		 949}
950
67712901
SH		 951/* Assign Ram Buffer allocation to queue */
952static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 953{
67712901
SH		 954 u32 end;
955
956 /* convert from K bytes to qwords used for hw register */
957 start *= 1024/8;
958 space *= 1024/8;
959 end = start + space - 1;
793b883e 960
cd28ab6a
SH		 961 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
962 sky2_write32(hw, RB_ADDR(q, RB_START), start);
963 sky2_write32(hw, RB_ADDR(q, RB_END), end);
964 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
965 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
966
967 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 968 u32 tp = space - space/4;
793b883e 969
1c28f6ba
SH		 970 /* On receive queue's set the thresholds
971 * give receiver priority when > 3/4 full
972 * send pause when down to 2K
973 */
974 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
975 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 976
1c28f6ba
SH		 977 tp = space - 2048/8;
978 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
979 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 980 } else {
981 /* Enable store & forward on Tx queue's because
982 * Tx FIFO is only 1K on Yukon
983 */
984 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
985 }
986
987 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 988 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 989}
990
cd28ab6a 991/* Setup Bus Memory Interface */
af4ed7e6 992static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 993{
994 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
995 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
996 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 997 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 998}
999
cd28ab6a
SH		 1000/* Setup prefetch unit registers. This is the interface between
1001 * hardware and driver list elements
1002 */
8cc048e3 1003static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 1004 dma_addr_t addr, u32 last)
cd28ab6a 1005{
cd28ab6a
SH		 1006 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1007 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1008 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1009 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1010 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1011 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1012
1013 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1014}
1015
9b289c33 1016static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1017{
9b289c33 1018 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1019
ee5f68fe 1020 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1021 le->ctrl = 0;
793b883e
SH		 1022 return le;
1023}
cd28ab6a 1024
88f5f0ca
SH		 1025static void tx_init(struct sky2_port *sky2)
1026{
1027 struct sky2_tx_le *le;
1028
1029 sky2->tx_prod = sky2->tx_cons = 0;
1030 sky2->tx_tcpsum = 0;
1031 sky2->tx_last_mss = 0;
1032
9b289c33 1033 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1034 le->addr = 0;
1035 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1036 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1037}
1038
290d4de5
SH		 1039/* Update chip's next pointer */
1040static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1041{
50432cb5 1042 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1043 wmb();
50432cb5
SH		 1044 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1045
1046 /* Synchronize I/O on since next processor may write to tail */
1047 mmiowb();
cd28ab6a
SH		 1048}
1049
793b883e 1050
cd28ab6a
SH		 1051static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1052{
1053 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1054 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1055 le->ctrl = 0;
cd28ab6a
SH		 1056 return le;
1057}
1058
39ef110b
MM		 1059static unsigned sky2_get_rx_threshold(struct sky2_port* sky2)
1060{
1061 unsigned size;
1062
1063 /* Space needed for frame data + headers rounded up */
1064 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1065
1066 /* Stopping point for hardware truncation */
1067 return (size - 8) / sizeof(u32);
1068}
1069
1070static unsigned sky2_get_rx_data_size(struct sky2_port* sky2)
1071{
1072 struct rx_ring_info *re;
1073 unsigned size;
1074
1075 /* Space needed for frame data + headers rounded up */
1076 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1077
1078 sky2->rx_nfrags = size >> PAGE_SHIFT;
1079 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1080
1081 /* Compute residue after pages */
1082 size -= sky2->rx_nfrags << PAGE_SHIFT;
1083
1084 /* Optimize to handle small packets and headers */
1085 if (size < copybreak)
1086 size = copybreak;
1087 if (size < ETH_HLEN)
1088 size = ETH_HLEN;
1089
1090 return size;
1091}
1092
14d0263f
SH		 1093/* Build description to hardware for one receive segment */
1094static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1095 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1096{
1097 struct sky2_rx_le *le;
1098
86c6887e 1099 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1100 le = sky2_next_rx(sky2);
86c6887e 1101 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1102 le->opcode = OP_ADDR64 | HW_OWNER;
1103 }
793b883e 1104
cd28ab6a 1105 le = sky2_next_rx(sky2);
d6e74b6b 1106 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1107 le->length = cpu_to_le16(len);
14d0263f 1108 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1109}
1110
14d0263f
SH		 1111/* Build description to hardware for one possibly fragmented skb */
1112static void sky2_rx_submit(struct sky2_port *sky2,
1113 const struct rx_ring_info *re)
1114{
1115 int i;
1116
1117 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1118
1119 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1120 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1121}
1122
1123
454e6cb6 1124static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1125 unsigned size)
1126{
1127 struct sk_buff *skb = re->skb;
1128 int i;
1129
1130 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1131 if (pci_dma_mapping_error(pdev, re->data_addr))
1132 goto mapping_error;
454e6cb6 1133
14d0263f
SH		 1134 pci_unmap_len_set(re, data_size, size);
1135
3fbd9187 1136 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1137 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1138
1139 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1140 frag->page_offset,
1141 frag->size,
14d0263f 1142 PCI_DMA_FROMDEVICE);
3fbd9187 1143
1144 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1145 goto map_page_error;
1146 }
454e6cb6 1147 return 0;
3fbd9187 1148
1149map_page_error:
1150 while (--i >= 0) {
1151 pci_unmap_page(pdev, re->frag_addr[i],
1152 skb_shinfo(skb)->frags[i].size,
1153 PCI_DMA_FROMDEVICE);
1154 }
1155
1156 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1157 PCI_DMA_FROMDEVICE);
1158
1159mapping_error:
1160 if (net_ratelimit())
1161 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1162 skb->dev->name);
1163 return -EIO;
14d0263f
SH		 1164}
1165
1166static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1167{
1168 struct sk_buff *skb = re->skb;
1169 int i;
1170
1171 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1172 PCI_DMA_FROMDEVICE);
1173
1174 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1175 pci_unmap_page(pdev, re->frag_addr[i],
1176 skb_shinfo(skb)->frags[i].size,
1177 PCI_DMA_FROMDEVICE);
1178}
793b883e 1179
cd28ab6a
SH		 1180/* Tell chip where to start receive checksum.
1181 * Actually has two checksums, but set both same to avoid possible byte
1182 * order problems.
1183 */
793b883e 1184static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1185{
ea76e635 1186 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1187
ea76e635
SH		 1188 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1189 le->ctrl = 0;
1190 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1191
ea76e635
SH		 1192 sky2_write32(sky2->hw,
1193 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1194 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1195 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1196}
1197
6b1a3aef
SH		 1198/*
1199 * The RX Stop command will not work for Yukon-2 if the BMU does not
1200 * reach the end of packet and since we can't make sure that we have
1201 * incoming data, we must reset the BMU while it is not doing a DMA
1202 * transfer. Since it is possible that the RX path is still active,
1203 * the RX RAM buffer will be stopped first, so any possible incoming
1204 * data will not trigger a DMA. After the RAM buffer is stopped, the
1205 * BMU is polled until any DMA in progress is ended and only then it
1206 * will be reset.
1207 */
1208static void sky2_rx_stop(struct sky2_port *sky2)
1209{
1210 struct sky2_hw *hw = sky2->hw;
1211 unsigned rxq = rxqaddr[sky2->port];
1212 int i;
1213
1214 /* disable the RAM Buffer receive queue */
1215 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1216
1217 for (i = 0; i < 0xffff; i++)
1218 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1219 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1220 goto stopped;
1221
ada1db5c 1222 netdev_warn(sky2->netdev, "receiver stop failed\n");
6b1a3aef
SH		 1223stopped:
1224 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1225
1226 /* reset the Rx prefetch unit */
1227 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1228 mmiowb();
6b1a3aef 1229}
793b883e 1230
d571b694 1231/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1232static void sky2_rx_clean(struct sky2_port *sky2)
1233{
1234 unsigned i;
1235
1236 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1237 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1238 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1239
1240 if (re->skb) {
14d0263f 1241 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1242 kfree_skb(re->skb);
1243 re->skb = NULL;
1244 }
1245 }
1246}
1247
ef743d33
SH		 1248/* Basic MII support */
1249static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1250{
1251 struct mii_ioctl_data *data = if_mii(ifr);
1252 struct sky2_port *sky2 = netdev_priv(dev);
1253 struct sky2_hw *hw = sky2->hw;
1254 int err = -EOPNOTSUPP;
1255
1256 if (!netif_running(dev))
1257 return -ENODEV; /* Phy still in reset */
1258
d89e1343 1259 switch (cmd) {
ef743d33
SH		 1260 case SIOCGMIIPHY:
1261 data->phy_id = PHY_ADDR_MARV;
1262
1263 /* fallthru */
1264 case SIOCGMIIREG: {
1265 u16 val = 0;
91c86df5 1266
e07b1aa8 1267 spin_lock_bh(&sky2->phy_lock);
ef743d33 1268 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1269 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1270
ef743d33
SH		 1271 data->val_out = val;
1272 break;
1273 }
1274
1275 case SIOCSMIIREG:
e07b1aa8 1276 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1277 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1278 data->val_in);
e07b1aa8 1279 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1280 break;
1281 }
1282 return err;
1283}
1284
d1f13708 1285#ifdef SKY2_VLAN_TAG_USED
d494eacd 1286static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1287{
d494eacd 1288 if (onoff) {
3d4e66f5
SH		 1289 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1290 RX_VLAN_STRIP_ON);
1291 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1292 TX_VLAN_TAG_ON);
1293 } else {
1294 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1295 RX_VLAN_STRIP_OFF);
1296 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1297 TX_VLAN_TAG_OFF);
1298 }
d494eacd
SH		 1299}
1300
1301static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1302{
1303 struct sky2_port *sky2 = netdev_priv(dev);
1304 struct sky2_hw *hw = sky2->hw;
1305 u16 port = sky2->port;
1306
1307 netif_tx_lock_bh(dev);
1308 napi_disable(&hw->napi);
1309
1310 sky2->vlgrp = grp;
1311 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1312
d1d08d12 1313 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1314 napi_enable(&hw->napi);
2bb8c262 1315 netif_tx_unlock_bh(dev);
d1f13708
SH		 1316}
1317#endif
1318
bd1c6869
SH		 1319/* Amount of required worst case padding in rx buffer */
1320static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1321{
1322 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1323}
1324
82788c7a 1325/*
14d0263f
SH		 1326 * Allocate an skb for receiving. If the MTU is large enough
1327 * make the skb non-linear with a fragment list of pages.
82788c7a 1328 */
14d0263f 1329static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1330{
1331 struct sk_buff *skb;
14d0263f 1332 int i;
82788c7a 1333
724b6942
SH		 1334 skb = netdev_alloc_skb(sky2->netdev,
1335 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1336 if (!skb)
1337 goto nomem;
1338
39dbd958 1339 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1340 unsigned char *start;
1341 /*
1342 * Workaround for a bug in FIFO that cause hang
1343 * if the FIFO if the receive buffer is not 64 byte aligned.
1344 * The buffer returned from netdev_alloc_skb is
1345 * aligned except if slab debugging is enabled.
1346 */
f03b8654
SH		 1347 start = PTR_ALIGN(skb->data, 8);
1348 skb_reserve(skb, start - skb->data);
bd1c6869 1349 } else
f03b8654 1350 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1351
1352 for (i = 0; i < sky2->rx_nfrags; i++) {
1353 struct page *page = alloc_page(GFP_ATOMIC);
1354
1355 if (!page)
1356 goto free_partial;
1357 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1358 }
1359
1360 return skb;
14d0263f
SH		 1361free_partial:
1362 kfree_skb(skb);
1363nomem:
1364 return NULL;
82788c7a
SH		 1365}
1366
55c9dd35
SH		 1367static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1368{
1369 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1370}
1371
200ac492
MM		 1372static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1373{
1374 struct sky2_hw *hw = sky2->hw;
1375 unsigned i;
1376
1377 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1378
1379 /* Fill Rx ring */
1380 for (i = 0; i < sky2->rx_pending; i++) {
1381 struct rx_ring_info *re = sky2->rx_ring + i;
1382
1383 re->skb = sky2_rx_alloc(sky2);
1384 if (!re->skb)
1385 return -ENOMEM;
1386
1387 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1388 dev_kfree_skb(re->skb);
1389 re->skb = NULL;
1390 return -ENOMEM;
1391 }
1392 }
1393 return 0;
1394}
1395
cd28ab6a 1396/*
200ac492 1397 * Setup receiver buffer pool.
14d0263f
SH		 1398 * Normal case this ends up creating one list element for skb
1399 * in the receive ring. Worst case if using large MTU and each
1400 * allocation falls on a different 64 bit region, that results
1401 * in 6 list elements per ring entry.
1402 * One element is used for checksum enable/disable, and one
1403 * extra to avoid wrap.
cd28ab6a 1404 */
200ac492 1405static void sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1406{
6b1a3aef 1407 struct sky2_hw *hw = sky2->hw;
14d0263f 1408 struct rx_ring_info *re;
6b1a3aef 1409 unsigned rxq = rxqaddr[sky2->port];
39ef110b 1410 unsigned i, thresh;
cd28ab6a 1411
6b1a3aef 1412 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1413 sky2_qset(hw, rxq);
977bdf06 1414
c3905bc4
SH		 1415 /* On PCI express lowering the watermark gives better performance */
1416 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1417 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1418
1419 /* These chips have no ram buffer?
1420 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1421 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c1cd0a85 1422 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
f449c7c1 1423 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1424
6b1a3aef
SH		 1425 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1426
ea76e635
SH		 1427 if (!(hw->flags & SKY2_HW_NEW_LE))
1428 rx_set_checksum(sky2);
14d0263f 1429
200ac492 1430 /* submit Rx ring */
793b883e 1431 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1432 re = sky2->rx_ring + i;
14d0263f 1433 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1434 }
1435
a1433ac4
SH		 1436 /*
1437 * The receiver hangs if it receives frames larger than the
1438 * packet buffer. As a workaround, truncate oversize frames, but
1439 * the register is limited to 9 bits, so if you do frames > 2052
1440 * you better get the MTU right!
1441 */
39ef110b 1442 thresh = sky2_get_rx_threshold(sky2);
a1433ac4
SH		 1443 if (thresh > 0x1ff)
1444 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1445 else {
1446 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1447 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1448 }
1449
6b1a3aef 1450 /* Tell chip about available buffers */
55c9dd35 1451 sky2_rx_update(sky2, rxq);
877c8570
SH		 1452
1453 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1454 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1455 /*
1456 * Disable flushing of non ASF packets;
1457 * must be done after initializing the BMUs;
1458 * drivers without ASF support should do this too, otherwise
1459 * it may happen that they cannot run on ASF devices;
1460 * remember that the MAC FIFO isn't reset during initialization.
1461 */
1462 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1463 }
1464
1465 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1466 /* Enable RX Home Address & Routing Header checksum fix */
1467 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1468 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1469
1470 /* Enable TX Home Address & Routing Header checksum fix */
1471 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1472 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1473 }
cd28ab6a
SH		 1474}
1475
90bbebb4
MM		 1476static int sky2_alloc_buffers(struct sky2_port *sky2)
1477{
1478 struct sky2_hw *hw = sky2->hw;
1479
1480 /* must be power of 2 */
1481 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1482 sky2->tx_ring_size *
1483 sizeof(struct sky2_tx_le),
1484 &sky2->tx_le_map);
1485 if (!sky2->tx_le)
1486 goto nomem;
1487
1488 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1489 GFP_KERNEL);
1490 if (!sky2->tx_ring)
1491 goto nomem;
1492
1493 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1494 &sky2->rx_le_map);
1495 if (!sky2->rx_le)
1496 goto nomem;
1497 memset(sky2->rx_le, 0, RX_LE_BYTES);
1498
1499 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1500 GFP_KERNEL);
1501 if (!sky2->rx_ring)
1502 goto nomem;
1503
200ac492 1504 return sky2_alloc_rx_skbs(sky2);
90bbebb4
MM		 1505nomem:
1506 return -ENOMEM;
1507}
1508
1509static void sky2_free_buffers(struct sky2_port *sky2)
1510{
1511 struct sky2_hw *hw = sky2->hw;
1512
200ac492
MM		 1513 sky2_rx_clean(sky2);
1514
90bbebb4
MM		 1515 if (sky2->rx_le) {
1516 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1517 sky2->rx_le, sky2->rx_le_map);
1518 sky2->rx_le = NULL;
1519 }
1520 if (sky2->tx_le) {
1521 pci_free_consistent(hw->pdev,
1522 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1523 sky2->tx_le, sky2->tx_le_map);
1524 sky2->tx_le = NULL;
1525 }
1526 kfree(sky2->tx_ring);
1527 kfree(sky2->rx_ring);
1528
1529 sky2->tx_ring = NULL;
1530 sky2->rx_ring = NULL;
1531}
1532
ea0f71e5 1533static void sky2_hw_up(struct sky2_port *sky2)
cd28ab6a 1534{
cd28ab6a
SH		 1535 struct sky2_hw *hw = sky2->hw;
1536 unsigned port = sky2->port;
ea0f71e5
MM		 1537 u32 ramsize;
1538 int cap;
843a46f4 1539 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1540
ea0f71e5
MM		 1541 tx_init(sky2);
1542
ee7abb04
SH		 1543 /*
1544 * On dual port PCI-X card, there is an problem where status
1545 * can be received out of order due to split transactions
843a46f4 1546 */
ee7abb04
SH		 1547 if (otherdev && netif_running(otherdev) &&
1548 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1549 u16 cmd;
1550
b32f40c4 1551 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1552 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4 1553 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
ea0f71e5 1554 }
cd28ab6a 1555
cd28ab6a
SH		 1556 sky2_mac_init(hw, port);
1557
e0c28116
SH		 1558 /* Register is number of 4K blocks on internal RAM buffer. */
1559 ramsize = sky2_read8(hw, B2_E_0) * 4;
1560 if (ramsize > 0) {
67712901 1561 u32 rxspace;
cd28ab6a 1562
ada1db5c 1563 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
67712901
SH		 1564 if (ramsize < 16)
1565 rxspace = ramsize / 2;
1566 else
1567 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1568
67712901
SH		 1569 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1570 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1571
1572 /* Make sure SyncQ is disabled */
1573 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1574 RB_RST_SET);
1575 }
793b883e 1576
af4ed7e6 1577 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1578
69161611
SH		 1579 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1580 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1581 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1582
977bdf06 1583 /* Set almost empty threshold */
8e95a202
JP		 1584 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1585 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1586 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1587
6b1a3aef 1588 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1589 sky2->tx_ring_size - 1);
cd28ab6a 1590
d494eacd
SH		 1591#ifdef SKY2_VLAN_TAG_USED
1592 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1593#endif
1594
200ac492 1595 sky2_rx_start(sky2);
ea0f71e5
MM		 1596}
1597
1598/* Bring up network interface. */
1599static int sky2_up(struct net_device *dev)
1600{
1601 struct sky2_port *sky2 = netdev_priv(dev);
1602 struct sky2_hw *hw = sky2->hw;
1603 unsigned port = sky2->port;
1604 u32 imask;
1605 int err;
1606
1607 netif_carrier_off(dev);
1608
1609 err = sky2_alloc_buffers(sky2);
1610 if (err)
1611 goto err_out;
1612
1613 sky2_hw_up(sky2);
cd28ab6a 1614
cd28ab6a 1615 /* Enable interrupts from phy/mac for port */
e07b1aa8 1616 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1617 imask |= portirq_msk[port];
e07b1aa8 1618 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1619 sky2_read32(hw, B0_IMSK);
e07b1aa8 1620
6c35abae 1621 netif_info(sky2, ifup, dev, "enabling interface\n");
af18d8b8 1622
cd28ab6a
SH		 1623 return 0;
1624
1625err_out:
90bbebb4 1626 sky2_free_buffers(sky2);
cd28ab6a
SH		 1627 return err;
1628}
1629
793b883e 1630/* Modular subtraction in ring */
ee5f68fe 1631static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1632{
ee5f68fe 1633 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1634}
cd28ab6a 1635
793b883e
SH		 1636/* Number of list elements available for next tx */
1637static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1638{
ee5f68fe 1639 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1640}
1641
793b883e 1642/* Estimate of number of transmit list elements required */
28bd181a 1643static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1644{
793b883e
SH		 1645 unsigned count;
1646
07e31637
SH		 1647 count = (skb_shinfo(skb)->nr_frags + 1)
1648 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1649
89114afd 1650 if (skb_is_gso(skb))
793b883e 1651 ++count;
07e31637
SH		 1652 else if (sizeof(dma_addr_t) == sizeof(u32))
1653 ++count; /* possible vlan */
793b883e 1654
84fa7933 1655 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1656 ++count;
1657
1658 return count;
cd28ab6a
SH		 1659}
1660
f6815077 1661static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1662{
1663 if (re->flags & TX_MAP_SINGLE)
1664 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1665 pci_unmap_len(re, maplen),
1666 PCI_DMA_TODEVICE);
1667 else if (re->flags & TX_MAP_PAGE)
1668 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1669 pci_unmap_len(re, maplen),
1670 PCI_DMA_TODEVICE);
f6815077 1671 re->flags = 0;
6b84daca
SH		 1672}
1673
793b883e
SH		 1674/*
1675 * Put one packet in ring for transmit.
1676 * A single packet can generate multiple list elements, and
1677 * the number of ring elements will probably be less than the number
1678 * of list elements used.
1679 */
61357325
SH		 1680static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1681 struct net_device *dev)
cd28ab6a
SH		 1682{
1683 struct sky2_port *sky2 = netdev_priv(dev);
1684 struct sky2_hw *hw = sky2->hw;
d1f13708 1685 struct sky2_tx_le *le = NULL;
6cdbbdf3 1686 struct tx_ring_info *re;
9b289c33 1687 unsigned i, len;
cd28ab6a 1688 dma_addr_t mapping;
5dce95e5
SH		 1689 u32 upper;
1690 u16 slot;
cd28ab6a
SH		 1691 u16 mss;
1692 u8 ctrl;
1693
2bb8c262
SH		 1694 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1695 return NETDEV_TX_BUSY;
cd28ab6a 1696
cd28ab6a
SH		 1697 len = skb_headlen(skb);
1698 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1699
454e6cb6
SH		 1700 if (pci_dma_mapping_error(hw->pdev, mapping))
1701 goto mapping_error;
1702
9b289c33 1703 slot = sky2->tx_prod;
6c35abae
JP		 1704 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1705 "tx queued, slot %u, len %d\n", slot, skb->len);
454e6cb6 1706
86c6887e 1707 /* Send high bits if needed */
5dce95e5
SH		 1708 upper = upper_32_bits(mapping);
1709 if (upper != sky2->tx_last_upper) {
9b289c33 1710 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1711 le->addr = cpu_to_le32(upper);
1712 sky2->tx_last_upper = upper;
793b883e 1713 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1714 }
cd28ab6a
SH		 1715
1716 /* Check for TCP Segmentation Offload */
7967168c 1717 mss = skb_shinfo(skb)->gso_size;
793b883e 1718 if (mss != 0) {
ea76e635
SH		 1719
1720 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1721 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1722
1723 if (mss != sky2->tx_last_mss) {
9b289c33 1724 le = get_tx_le(sky2, &slot);
69161611 1725 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1726
1727 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1728 le->opcode = OP_MSS | HW_OWNER;
1729 else
1730 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1731 sky2->tx_last_mss = mss;
1732 }
cd28ab6a
SH		 1733 }
1734
cd28ab6a 1735 ctrl = 0;
d1f13708
SH		 1736#ifdef SKY2_VLAN_TAG_USED
1737 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1738 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1739 if (!le) {
9b289c33 1740 le = get_tx_le(sky2, &slot);
f65b138c 1741 le->addr = 0;
d1f13708 1742 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1743 } else
1744 le->opcode |= OP_VLAN;
1745 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1746 ctrl |= INS_VLAN;
1747 }
1748#endif
1749
1750 /* Handle TCP checksum offload */
84fa7933 1751 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1752 /* On Yukon EX (some versions) encoding change. */
ea76e635 1753 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1754 ctrl |= CALSUM; /* auto checksum */
1755 else {
1756 const unsigned offset = skb_transport_offset(skb);
1757 u32 tcpsum;
1758
1759 tcpsum = offset << 16; /* sum start */
1760 tcpsum |= offset + skb->csum_offset; /* sum write */
1761
1762 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1763 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1764 ctrl |= UDPTCP;
1765
1766 if (tcpsum != sky2->tx_tcpsum) {
1767 sky2->tx_tcpsum = tcpsum;
1768
9b289c33 1769 le = get_tx_le(sky2, &slot);
69161611
SH		 1770 le->addr = cpu_to_le32(tcpsum);
1771 le->length = 0; /* initial checksum value */
1772 le->ctrl = 1; /* one packet */
1773 le->opcode = OP_TCPLISW | HW_OWNER;
1774 }
1d179332 1775 }
cd28ab6a
SH		 1776 }
1777
6b84daca
SH		 1778 re = sky2->tx_ring + slot;
1779 re->flags = TX_MAP_SINGLE;
1780 pci_unmap_addr_set(re, mapaddr, mapping);
1781 pci_unmap_len_set(re, maplen, len);
1782
9b289c33 1783 le = get_tx_le(sky2, &slot);
d6e74b6b 1784 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1785 le->length = cpu_to_le16(len);
1786 le->ctrl = ctrl;
793b883e 1787 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1788
cd28ab6a
SH		 1789
1790 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1791 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1792
1793 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1794 frag->size, PCI_DMA_TODEVICE);
86c6887e 1795
454e6cb6
SH		 1796 if (pci_dma_mapping_error(hw->pdev, mapping))
1797 goto mapping_unwind;
1798
5dce95e5
SH		 1799 upper = upper_32_bits(mapping);
1800 if (upper != sky2->tx_last_upper) {
9b289c33 1801 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1802 le->addr = cpu_to_le32(upper);
1803 sky2->tx_last_upper = upper;
793b883e 1804 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1805 }
1806
6b84daca
SH		 1807 re = sky2->tx_ring + slot;
1808 re->flags = TX_MAP_PAGE;
1809 pci_unmap_addr_set(re, mapaddr, mapping);
1810 pci_unmap_len_set(re, maplen, frag->size);
1811
9b289c33 1812 le = get_tx_le(sky2, &slot);
d6e74b6b 1813 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1814 le->length = cpu_to_le16(frag->size);
1815 le->ctrl = ctrl;
793b883e 1816 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1817 }
6cdbbdf3 1818
6b84daca 1819 re->skb = skb;
cd28ab6a
SH		 1820 le->ctrl |= EOP;
1821
9b289c33
MM		 1822 sky2->tx_prod = slot;
1823
97bda706
SH		 1824 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1825 netif_stop_queue(dev);
b19666d9 1826
290d4de5 1827 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1828
cd28ab6a 1829 return NETDEV_TX_OK;
454e6cb6
SH		 1830
1831mapping_unwind:
ee5f68fe 1832 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1833 re = sky2->tx_ring + i;
1834
6b84daca 1835 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1836 }
1837
454e6cb6
SH		 1838mapping_error:
1839 if (net_ratelimit())
1840 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1841 dev_kfree_skb(skb);
1842 return NETDEV_TX_OK;
cd28ab6a
SH		 1843}
1844
cd28ab6a 1845/*
793b883e
SH		 1846 * Free ring elements from starting at tx_cons until "done"
1847 *
481cea4a
SH		 1848 * NB:
1849 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1850 * buffers so make sure not to free skb to early.
481cea4a
SH		 1851 * 2. This may run in parallel start_xmit because the it only
1852 * looks at the tail of the queue of FIFO (tx_cons), not
1853 * the head (tx_prod)
cd28ab6a 1854 */
d11c13e7 1855static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1856{
d11c13e7 1857 struct net_device *dev = sky2->netdev;
291ea614 1858 unsigned idx;
cd28ab6a 1859
ee5f68fe 1860 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1861
291ea614 1862 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1863 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1864 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1865 struct sk_buff *skb = re->skb;
291ea614 1866
6b84daca 1867 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1868
6b84daca 1869 if (skb) {
6c35abae
JP		 1870 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1871 "tx done %u\n", idx);
3cf26753 1872
7138a0f5 1873 dev->stats.tx_packets++;
bd1c6869
SH		 1874 dev->stats.tx_bytes += skb->len;
1875
f6815077 1876 re->skb = NULL;
724b6942 1877 dev_kfree_skb_any(skb);
2bf56fe2 1878
ee5f68fe 1879 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1880 }
793b883e 1881 }
793b883e 1882
291ea614 1883 sky2->tx_cons = idx;
50432cb5 1884 smp_mb();
cd28ab6a
SH		 1885}
1886
264bb4fa 1887static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1888{
a510996b
MM		 1889 /* Disable Force Sync bit and Enable Alloc bit */
1890 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1891 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1892
1893 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1894 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1895 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1896
1897 /* Reset the PCI FIFO of the async Tx queue */
1898 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1899 BMU_RST_SET | BMU_FIFO_RST);
1900
1901 /* Reset the Tx prefetch units */
1902 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1903 PREF_UNIT_RST_SET);
1904
1905 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1906 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1907}
1908
f2b31cb3 1909static void sky2_hw_down(struct sky2_port *sky2)
cd28ab6a 1910{
cd28ab6a
SH		 1911 struct sky2_hw *hw = sky2->hw;
1912 unsigned port = sky2->port;
f2b31cb3 1913 u16 ctrl;
cd28ab6a 1914
d104acaf
SH		 1915 /* Force flow control off */
1916 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1917
cd28ab6a
SH		 1918 /* Stop transmitter */
1919 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1920 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1921
1922 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1923 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1924
1925 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1926 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1927 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1928
1929 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1930
1931 /* Workaround shared GMAC reset */
8e95a202
JP		 1932 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1933 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1934 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1935
cd28ab6a 1936 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1937
6c83504f
SH		 1938 /* Force any delayed status interrrupt and NAPI */
1939 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1940 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1941 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1942 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1943
a947a39d
MM		 1944 sky2_rx_stop(sky2);
1945
0da6d7b3 1946 spin_lock_bh(&sky2->phy_lock);
b96936da 1947 sky2_phy_power_down(hw, port);
0da6d7b3 1948 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1949
264bb4fa
MM		 1950 sky2_tx_reset(hw, port);
1951
481cea4a
SH		 1952 /* Free any pending frames stuck in HW queue */
1953 sky2_tx_complete(sky2, sky2->tx_prod);
f2b31cb3
MM		 1954}
1955
1956/* Network shutdown */
1957static int sky2_down(struct net_device *dev)
1958{
1959 struct sky2_port *sky2 = netdev_priv(dev);
8a0c9228 1960 struct sky2_hw *hw = sky2->hw;
f2b31cb3
MM		 1961
1962 /* Never really got started! */
1963 if (!sky2->tx_le)
1964 return 0;
1965
6c35abae 1966 netif_info(sky2, ifdown, dev, "disabling interface\n");
f2b31cb3 1967
8a0c9228
MM		 1968 /* Disable port IRQ */
1969 sky2_write32(hw, B0_IMSK,
1970 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
1971 sky2_read32(hw, B0_IMSK);
1972
1973 synchronize_irq(hw->pdev->irq);
1974 napi_synchronize(&hw->napi);
1975
f2b31cb3 1976 sky2_hw_down(sky2);
481cea4a 1977
90bbebb4 1978 sky2_free_buffers(sky2);
1b537565 1979
cd28ab6a
SH		 1980 return 0;
1981}
1982
1983static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1984{
ea76e635 1985 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1986 return SPEED_1000;
1987
05745c4a
SH		 1988 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1989 if (aux & PHY_M_PS_SPEED_100)
1990 return SPEED_100;
1991 else
1992 return SPEED_10;
1993 }
cd28ab6a
SH		 1994
1995 switch (aux & PHY_M_PS_SPEED_MSK) {
1996 case PHY_M_PS_SPEED_1000:
1997 return SPEED_1000;
1998 case PHY_M_PS_SPEED_100:
1999 return SPEED_100;
2000 default:
2001 return SPEED_10;
2002 }
2003}
2004
2005static void sky2_link_up(struct sky2_port *sky2)
2006{
2007 struct sky2_hw *hw = sky2->hw;
2008 unsigned port = sky2->port;
2009 u16 reg;
16ad91e1
SH		 2010 static const char *fc_name[] = {
2011 [FC_NONE] = "none",
2012 [FC_TX] = "tx",
2013 [FC_RX] = "rx",
2014 [FC_BOTH] = "both",
2015 };
cd28ab6a 2016
cd28ab6a 2017 /* enable Rx/Tx */
2eaba1a2 2018 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 2019 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2020 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 2021
2022 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2023
2024 netif_carrier_on(sky2->netdev);
cd28ab6a 2025
75e80683 2026 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 2027
cd28ab6a 2028 /* Turn on link LED */
793b883e 2029 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2030 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2031
6c35abae
JP		 2032 netif_info(sky2, link, sky2->netdev,
2033 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2034 sky2->speed,
2035 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2036 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2037}
2038
2039static void sky2_link_down(struct sky2_port *sky2)
2040{
2041 struct sky2_hw *hw = sky2->hw;
2042 unsigned port = sky2->port;
2043 u16 reg;
2044
2045 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2046
2047 reg = gma_read16(hw, port, GM_GP_CTRL);
2048 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2049 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2050
cd28ab6a 2051 netif_carrier_off(sky2->netdev);
cd28ab6a 2052
809aaaae 2053 /* Turn off link LED */
cd28ab6a
SH		 2054 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2055
6c35abae 2056 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2eaba1a2 2057
cd28ab6a
SH		 2058 sky2_phy_init(hw, port);
2059}
2060
16ad91e1
SH		 2061static enum flow_control sky2_flow(int rx, int tx)
2062{
2063 if (rx)
2064 return tx ? FC_BOTH : FC_RX;
2065 else
2066 return tx ? FC_TX : FC_NONE;
2067}
2068
793b883e
SH		 2069static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2070{
2071 struct sky2_hw *hw = sky2->hw;
2072 unsigned port = sky2->port;
da4c1ff4 2073 u16 advert, lpa;
793b883e 2074
da4c1ff4 2075 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2076 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e 2077 if (lpa & PHY_M_AN_RF) {
ada1db5c 2078 netdev_err(sky2->netdev, "remote fault\n");
793b883e
SH		 2079 return -1;
2080 }
2081
793b883e 2082 if (!(aux & PHY_M_PS_SPDUP_RES)) {
ada1db5c 2083 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
793b883e
SH		 2084 return -1;
2085 }
2086
793b883e 2087 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2088 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2089
da4c1ff4
SH		 2090 /* Since the pause result bits seem to in different positions on
2091 * different chips. look at registers.
2092 */
ea76e635 2093 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2094 /* Shift for bits in fiber PHY */
2095 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2096 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2097
2098 if (advert & ADVERTISE_1000XPAUSE)
2099 advert |= ADVERTISE_PAUSE_CAP;
2100 if (advert & ADVERTISE_1000XPSE_ASYM)
2101 advert |= ADVERTISE_PAUSE_ASYM;
2102 if (lpa & LPA_1000XPAUSE)
2103 lpa |= LPA_PAUSE_CAP;
2104 if (lpa & LPA_1000XPAUSE_ASYM)
2105 lpa |= LPA_PAUSE_ASYM;
2106 }
793b883e 2107
da4c1ff4
SH		 2108 sky2->flow_status = FC_NONE;
2109 if (advert & ADVERTISE_PAUSE_CAP) {
2110 if (lpa & LPA_PAUSE_CAP)
2111 sky2->flow_status = FC_BOTH;
2112 else if (advert & ADVERTISE_PAUSE_ASYM)
2113 sky2->flow_status = FC_RX;
2114 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2115 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2116 sky2->flow_status = FC_TX;
2117 }
793b883e 2118
8e95a202
JP		 2119 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2120 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2121 sky2->flow_status = FC_NONE;
2eaba1a2 2122
da4c1ff4 2123 if (sky2->flow_status & FC_TX)
793b883e
SH		 2124 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2125 else
2126 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2127
2128 return 0;
2129}
cd28ab6a 2130
e07b1aa8
SH		 2131/* Interrupt from PHY */
2132static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2133{
e07b1aa8
SH		 2134 struct net_device *dev = hw->dev[port];
2135 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2136 u16 istatus, phystat;
2137
ebc646f6
SH		 2138 if (!netif_running(dev))
2139 return;
2140
e07b1aa8
SH		 2141 spin_lock(&sky2->phy_lock);
2142 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2143 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2144
6c35abae
JP		 2145 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2146 istatus, phystat);
cd28ab6a 2147
0ea065e5 2148 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2149 if (sky2_autoneg_done(sky2, phystat) == 0)
2150 sky2_link_up(sky2);
2151 goto out;
2152 }
cd28ab6a 2153
793b883e
SH		 2154 if (istatus & PHY_M_IS_LSP_CHANGE)
2155 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2156
793b883e
SH		 2157 if (istatus & PHY_M_IS_DUP_CHANGE)
2158 sky2->duplex =
2159 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2160
793b883e
SH		 2161 if (istatus & PHY_M_IS_LST_CHANGE) {
2162 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2163 sky2_link_up(sky2);
793b883e
SH		 2164 else
2165 sky2_link_down(sky2);
cd28ab6a 2166 }
793b883e 2167out:
e07b1aa8 2168 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2169}
2170
0f5aac70
SH		 2171/* Special quick link interrupt (Yukon-2 Optima only) */
2172static void sky2_qlink_intr(struct sky2_hw *hw)
2173{
2174 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2175 u32 imask;
2176 u16 phy;
2177
2178 /* disable irq */
2179 imask = sky2_read32(hw, B0_IMSK);
2180 imask &= ~Y2_IS_PHY_QLNK;
2181 sky2_write32(hw, B0_IMSK, imask);
2182
2183 /* reset PHY Link Detect */
2184 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2185 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2186 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2187 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2188
2189 sky2_link_up(sky2);
2190}
2191
62335ab0 2192/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2193 * and tx queue is full (stopped).
2194 */
cd28ab6a
SH		 2195static void sky2_tx_timeout(struct net_device *dev)
2196{
2197 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2198 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2199
6c35abae 2200 netif_err(sky2, timer, dev, "tx timeout\n");
cd28ab6a 2201
ada1db5c
JP		 2202 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2203 sky2->tx_cons, sky2->tx_prod,
2204 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2205 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2206
81906791
SH		 2207 /* can't restart safely under softirq */
2208 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2209}
2210
2211static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2212{
6b1a3aef
SH		 2213 struct sky2_port *sky2 = netdev_priv(dev);
2214 struct sky2_hw *hw = sky2->hw;
b628ed98 2215 unsigned port = sky2->port;
6b1a3aef
SH		 2216 int err;
2217 u16 ctl, mode;
e07b1aa8 2218 u32 imask;
cd28ab6a 2219
44dde56d 2220 /* MTU size outside the spec */
cd28ab6a
SH		 2221 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2222 return -EINVAL;
2223
44dde56d 2224 /* MTU > 1500 on yukon FE and FE+ not allowed */
05745c4a
SH		 2225 if (new_mtu > ETH_DATA_LEN &&
2226 (hw->chip_id == CHIP_ID_YUKON_FE ||
2227 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2228 return -EINVAL;
2229
44dde56d 2230 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2231 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
2232 dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
2233
6b1a3aef
SH		 2234 if (!netif_running(dev)) {
2235 dev->mtu = new_mtu;
2236 return 0;
2237 }
2238
e07b1aa8 2239 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2240 sky2_write32(hw, B0_IMSK, 0);
2241
018d1c66
SH		 2242 dev->trans_start = jiffies; /* prevent tx timeout */
2243 netif_stop_queue(dev);
bea3348e 2244 napi_disable(&hw->napi);
018d1c66 2245
e07b1aa8
SH		 2246 synchronize_irq(hw->pdev->irq);
2247
39dbd958 2248 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2249 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2250
2251 ctl = gma_read16(hw, port, GM_GP_CTRL);
2252 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2253 sky2_rx_stop(sky2);
2254 sky2_rx_clean(sky2);
cd28ab6a
SH		 2255
2256 dev->mtu = new_mtu;
14d0263f 2257
6b1a3aef
SH		 2258 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2259 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2260
2261 if (dev->mtu > ETH_DATA_LEN)
2262 mode |= GM_SMOD_JUMBO_ENA;
2263
b628ed98 2264 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2265
b628ed98 2266 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2267
200ac492
MM		 2268 err = sky2_alloc_rx_skbs(sky2);
2269 if (!err)
2270 sky2_rx_start(sky2);
2271 else
2272 sky2_rx_clean(sky2);
e07b1aa8 2273 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2274
d1d08d12 2275 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2276 napi_enable(&hw->napi);
2277
1b537565
SH		 2278 if (err)
2279 dev_close(dev);
2280 else {
b628ed98 2281 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2282
1b537565
SH		 2283 netif_wake_queue(dev);
2284 }
2285
cd28ab6a
SH		 2286 return err;
2287}
2288
14d0263f
SH		 2289/* For small just reuse existing skb for next receive */
2290static struct sk_buff *receive_copy(struct sky2_port *sky2,
2291 const struct rx_ring_info *re,
2292 unsigned length)
2293{
2294 struct sk_buff *skb;
2295
89d71a66 2296 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2297 if (likely(skb)) {
14d0263f
SH		 2298 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2299 length, PCI_DMA_FROMDEVICE);
d626f62b 2300 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2301 skb->ip_summed = re->skb->ip_summed;
2302 skb->csum = re->skb->csum;
2303 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2304 length, PCI_DMA_FROMDEVICE);
2305 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2306 skb_put(skb, length);
14d0263f
SH		 2307 }
2308 return skb;
2309}
2310
2311/* Adjust length of skb with fragments to match received data */
2312static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2313 unsigned int length)
2314{
2315 int i, num_frags;
2316 unsigned int size;
2317
2318 /* put header into skb */
2319 size = min(length, hdr_space);
2320 skb->tail += size;
2321 skb->len += size;
2322 length -= size;
2323
2324 num_frags = skb_shinfo(skb)->nr_frags;
2325 for (i = 0; i < num_frags; i++) {
2326 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2327
2328 if (length == 0) {
2329 /* don't need this page */
2330 __free_page(frag->page);
2331 --skb_shinfo(skb)->nr_frags;
2332 } else {
2333 size = min(length, (unsigned) PAGE_SIZE);
2334
2335 frag->size = size;
2336 skb->data_len += size;
2337 skb->truesize += size;
2338 skb->len += size;
2339 length -= size;
2340 }
2341 }
2342}
2343
2344/* Normal packet - take skb from ring element and put in a new one */
2345static struct sk_buff *receive_new(struct sky2_port *sky2,
2346 struct rx_ring_info *re,
2347 unsigned int length)
2348{
3fbd9187 2349 struct sk_buff *skb;
2350 struct rx_ring_info nre;
14d0263f
SH		 2351 unsigned hdr_space = sky2->rx_data_size;
2352
3fbd9187 2353 nre.skb = sky2_rx_alloc(sky2);
2354 if (unlikely(!nre.skb))
2355 goto nobuf;
2356
2357 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2358 goto nomap;
14d0263f
SH		 2359
2360 skb = re->skb;
2361 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2362 prefetch(skb->data);
3fbd9187 2363 *re = nre;
14d0263f
SH		 2364
2365 if (skb_shinfo(skb)->nr_frags)
2366 skb_put_frags(skb, hdr_space, length);
2367 else
489b10c1 2368 skb_put(skb, length);
14d0263f 2369 return skb;
3fbd9187 2370
2371nomap:
2372 dev_kfree_skb(nre.skb);
2373nobuf:
2374 return NULL;
14d0263f
SH		 2375}
2376
cd28ab6a
SH		 2377/*
2378 * Receive one packet.
d571b694 2379 * For larger packets, get new buffer.
cd28ab6a 2380 */
497d7c86 2381static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2382 u16 length, u32 status)
2383{
497d7c86 2384 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2385 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2386 struct sk_buff *skb = NULL;
d6532232
SH		 2387 u16 count = (status & GMR_FS_LEN) >> 16;
2388
2389#ifdef SKY2_VLAN_TAG_USED
2390 /* Account for vlan tag */
2391 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2392 count -= VLAN_HLEN;
2393#endif
cd28ab6a 2394
6c35abae
JP		 2395 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2396 "rx slot %u status 0x%x len %d\n",
2397 sky2->rx_next, status, length);
cd28ab6a 2398
793b883e 2399 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2400 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2401
3b12e014
SH		 2402 /* This chip has hardware problems that generates bogus status.
2403 * So do only marginal checking and expect higher level protocols
2404 * to handle crap frames.
2405 */
2406 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2407 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2408 length != count)
2409 goto okay;
2410
42eeea01 2411 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2412 goto error;
2413
42eeea01
SH		 2414 if (!(status & GMR_FS_RX_OK))
2415 goto resubmit;
2416
d6532232
SH		 2417 /* if length reported by DMA does not match PHY, packet was truncated */
2418 if (length != count)
3b12e014 2419 goto len_error;
71749531 2420
3b12e014 2421okay:
14d0263f
SH		 2422 if (length < copybreak)
2423 skb = receive_copy(sky2, re, length);
2424 else
2425 skb = receive_new(sky2, re, length);
90c30335
SH		 2426
2427 dev->stats.rx_dropped += (skb == NULL);
2428
793b883e 2429resubmit:
14d0263f 2430 sky2_rx_submit(sky2, re);
79e57d32 2431
cd28ab6a
SH		 2432 return skb;
2433
3b12e014 2434len_error:
71749531
SH		 2435 /* Truncation of overlength packets
2436 causes PHY length to not match MAC length */
7138a0f5 2437 ++dev->stats.rx_length_errors;
6c35abae
JP		 2438 if (net_ratelimit())
2439 netif_info(sky2, rx_err, dev,
2440 "rx length error: status %#x length %d\n",
2441 status, length);
d6532232 2442 goto resubmit;
71749531 2443
cd28ab6a 2444error:
7138a0f5 2445 ++dev->stats.rx_errors;
b6d77734 2446 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2447 dev->stats.rx_over_errors++;
b6d77734
SH		 2448 goto resubmit;
2449 }
6e15b712 2450
6c35abae
JP		 2451 if (net_ratelimit())
2452 netif_info(sky2, rx_err, dev,
2453 "rx error, status 0x%x length %d\n", status, length);
793b883e
SH		 2454
2455 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2456 dev->stats.rx_length_errors++;
cd28ab6a 2457 if (status & GMR_FS_FRAGMENT)
7138a0f5 2458 dev->stats.rx_frame_errors++;
cd28ab6a 2459 if (status & GMR_FS_CRC_ERR)
7138a0f5 2460 dev->stats.rx_crc_errors++;
79e57d32 2461
793b883e 2462 goto resubmit;
cd28ab6a
SH		 2463}
2464
e07b1aa8
SH		 2465/* Transmit complete */
2466static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2467{
e07b1aa8 2468 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2469
8a0c9228 2470 if (netif_running(dev)) {
e07b1aa8 2471 sky2_tx_complete(sky2, last);
8a0c9228
MM		 2472
2473 /* Wake unless it's detached, and called e.g. from sky2_down() */
2474 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2475 netif_wake_queue(dev);
2476 }
cd28ab6a
SH		 2477}
2478
37e5a243
SH		 2479static inline void sky2_skb_rx(const struct sky2_port *sky2,
2480 u32 status, struct sk_buff *skb)
2481{
2482#ifdef SKY2_VLAN_TAG_USED
2483 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2484 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2485 if (skb->ip_summed == CHECKSUM_NONE)
2486 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2487 else
2488 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2489 vlan_tag, skb);
2490 return;
2491 }
2492#endif
2493 if (skb->ip_summed == CHECKSUM_NONE)
2494 netif_receive_skb(skb);
2495 else
2496 napi_gro_receive(&sky2->hw->napi, skb);
2497}
2498
bf15fe99
SH		 2499static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2500 unsigned packets, unsigned bytes)
2501{
2502 if (packets) {
2503 struct net_device *dev = hw->dev[port];
2504
2505 dev->stats.rx_packets += packets;
2506 dev->stats.rx_bytes += bytes;
2507 dev->last_rx = jiffies;
2508 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2509 }
2510}
2511
375c5688 2512static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2513{
2514 /* If this happens then driver assuming wrong format for chip type */
2515 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2516
2517 /* Both checksum counters are programmed to start at
2518 * the same offset, so unless there is a problem they
2519 * should match. This failure is an early indication that
2520 * hardware receive checksumming won't work.
2521 */
2522 if (likely((u16)(status >> 16) == (u16)status)) {
2523 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2524 skb->ip_summed = CHECKSUM_COMPLETE;
2525 skb->csum = le16_to_cpu(status);
2526 } else {
2527 dev_notice(&sky2->hw->pdev->dev,
2528 "%s: receive checksum problem (status = %#x)\n",
2529 sky2->netdev->name, status);
2530
2531 /* Disable checksum offload */
2532 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2533 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2534 BMU_DIS_RX_CHKSUM);
2535 }
2536}
2537
e07b1aa8 2538/* Process status response ring */
26691830 2539static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2540{
e07b1aa8 2541 int work_done = 0;
bf15fe99
SH		 2542 unsigned int total_bytes[2] = { 0 };
2543 unsigned int total_packets[2] = { 0 };
a8fd6266 2544
af2a58ac 2545 rmb();
26691830 2546 do {
55c9dd35 2547 struct sky2_port *sky2;
13210ce5 2548 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2549 unsigned port;
13210ce5 2550 struct net_device *dev;
cd28ab6a 2551 struct sk_buff *skb;
cd28ab6a
SH		 2552 u32 status;
2553 u16 length;
ab5adecb
SH		 2554 u8 opcode = le->opcode;
2555
2556 if (!(opcode & HW_OWNER))
2557 break;
cd28ab6a 2558
cb5d9547 2559 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2560
ab5adecb 2561 port = le->css & CSS_LINK_BIT;
69161611 2562 dev = hw->dev[port];
13210ce5 2563 sky2 = netdev_priv(dev);
f65b138c
SH		 2564 length = le16_to_cpu(le->length);
2565 status = le32_to_cpu(le->status);
cd28ab6a 2566
ab5adecb
SH		 2567 le->opcode = 0;
2568 switch (opcode & ~HW_OWNER) {
cd28ab6a 2569 case OP_RXSTAT:
bf15fe99
SH		 2570 total_packets[port]++;
2571 total_bytes[port] += length;
90c30335 2572
497d7c86 2573 skb = sky2_receive(dev, length, status);
90c30335 2574 if (!skb)
55c9dd35 2575 break;
13210ce5 2576
69161611 2577 /* This chip reports checksum status differently */
05745c4a 2578 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2579 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2580 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2581 (le->css & CSS_TCPUDPCSOK))
2582 skb->ip_summed = CHECKSUM_UNNECESSARY;
2583 else
2584 skb->ip_summed = CHECKSUM_NONE;
2585 }
2586
13210ce5 2587 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2588
37e5a243 2589 sky2_skb_rx(sky2, status, skb);
13210ce5 2590
22e11703 2591 /* Stop after net poll weight */
13210ce5
SH		 2592 if (++work_done >= to_do)
2593 goto exit_loop;
cd28ab6a
SH		 2594 break;
2595
d1f13708
SH		 2596#ifdef SKY2_VLAN_TAG_USED
2597 case OP_RXVLAN:
2598 sky2->rx_tag = length;
2599 break;
2600
2601 case OP_RXCHKSVLAN:
2602 sky2->rx_tag = length;
2603 /* fall through */
2604#endif
cd28ab6a 2605 case OP_RXCHKS:
375c5688 2606 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2607 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2608 break;
2609
2610 case OP_TXINDEXLE:
13b97b74 2611 /* TX index reports status for both ports */
f55925d7 2612 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2613 if (hw->dev[1])
2614 sky2_tx_done(hw->dev[1],
2615 ((status >> 24) & 0xff)
2616 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2617 break;
2618
cd28ab6a
SH		 2619 default:
2620 if (net_ratelimit())
ada1db5c 2621 pr_warning("unknown status opcode 0x%x\n", opcode);
cd28ab6a 2622 }
26691830 2623 } while (hw->st_idx != idx);
cd28ab6a 2624
fe2a24df
SH		 2625 /* Fully processed status ring so clear irq */
2626 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2627
13210ce5 2628exit_loop:
bf15fe99
SH		 2629 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2630 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2631
e07b1aa8 2632 return work_done;
cd28ab6a
SH		 2633}
2634
2635static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2636{
2637 struct net_device *dev = hw->dev[port];
2638
3be92a70 2639 if (net_ratelimit())
ada1db5c 2640 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
cd28ab6a
SH		 2641
2642 if (status & Y2_IS_PAR_RD1) {
3be92a70 2643 if (net_ratelimit())
ada1db5c 2644 netdev_err(dev, "ram data read parity error\n");
cd28ab6a
SH		 2645 /* Clear IRQ */
2646 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2647 }
2648
2649 if (status & Y2_IS_PAR_WR1) {
3be92a70 2650 if (net_ratelimit())
ada1db5c 2651 netdev_err(dev, "ram data write parity error\n");
cd28ab6a
SH		 2652
2653 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2654 }
2655
2656 if (status & Y2_IS_PAR_MAC1) {
3be92a70 2657 if (net_ratelimit())
ada1db5c 2658 netdev_err(dev, "MAC parity error\n");
cd28ab6a
SH		 2659 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2660 }
2661
2662 if (status & Y2_IS_PAR_RX1) {
3be92a70 2663 if (net_ratelimit())
ada1db5c 2664 netdev_err(dev, "RX parity error\n");
cd28ab6a
SH		 2665 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2666 }
2667
2668 if (status & Y2_IS_TCP_TXA1) {
3be92a70 2669 if (net_ratelimit())
ada1db5c 2670 netdev_err(dev, "TCP segmentation error\n");
cd28ab6a
SH		 2671 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2672 }
2673}
2674
2675static void sky2_hw_intr(struct sky2_hw *hw)
2676{
555382cb 2677 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2678 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2679 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2680
2681 status &= hwmsk;
cd28ab6a 2682
793b883e 2683 if (status & Y2_IS_TIST_OV)
cd28ab6a 2684 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2685
2686 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2687 u16 pci_err;
2688
a40ccc68 2689 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2690 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2691 if (net_ratelimit())
555382cb 2692 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2693 pci_err);
cd28ab6a 2694
b32f40c4 2695 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2696 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2697 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2698 }
2699
2700 if (status & Y2_IS_PCI_EXP) {
d571b694 2701 /* PCI-Express uncorrectable Error occurred */
555382cb 2702 u32 err;
cd28ab6a 2703
a40ccc68 2704 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2705 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2706 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2707 0xfffffffful);
3be92a70 2708 if (net_ratelimit())
555382cb 2709 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2710
7782c8c4 2711 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2712 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2713 }
2714
2715 if (status & Y2_HWE_L1_MASK)
2716 sky2_hw_error(hw, 0, status);
2717 status >>= 8;
2718 if (status & Y2_HWE_L1_MASK)
2719 sky2_hw_error(hw, 1, status);
2720}
2721
2722static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2723{
2724 struct net_device *dev = hw->dev[port];
2725 struct sky2_port *sky2 = netdev_priv(dev);
2726 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2727
6c35abae 2728 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
cd28ab6a 2729
a3caeada
SH		 2730 if (status & GM_IS_RX_CO_OV)
2731 gma_read16(hw, port, GM_RX_IRQ_SRC);
2732
2733 if (status & GM_IS_TX_CO_OV)
2734 gma_read16(hw, port, GM_TX_IRQ_SRC);
2735
cd28ab6a 2736 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2737 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2738 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2739 }
2740
2741 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2742 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2743 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2744 }
cd28ab6a
SH		 2745}
2746
40b01727 2747/* This should never happen it is a bug. */
c119731d 2748static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2749{
2750 struct net_device *dev = hw->dev[port];
c119731d 2751 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2752
ada1db5c 2753 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
c119731d
SH		 2754 dev->name, (unsigned) q, (unsigned) idx,
2755 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2756
40b01727 2757 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2758}
cd28ab6a 2759
75e80683
SH		 2760static int sky2_rx_hung(struct net_device *dev)
2761{
2762 struct sky2_port *sky2 = netdev_priv(dev);
2763 struct sky2_hw *hw = sky2->hw;
2764 unsigned port = sky2->port;
2765 unsigned rxq = rxqaddr[port];
2766 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2767 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2768 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2769 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2770
2771 /* If idle and MAC or PCI is stuck */
2772 if (sky2->check.last == dev->last_rx &&
2773 ((mac_rp == sky2->check.mac_rp &&
2774 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2775 /* Check if the PCI RX hang */
2776 (fifo_rp == sky2->check.fifo_rp &&
2777 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
ada1db5c
JP		 2778 netdev_printk(KERN_DEBUG, dev,
2779 "hung mac %d:%d fifo %d (%d:%d)\n",
2780 mac_lev, mac_rp, fifo_lev,
2781 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
75e80683
SH		 2782 return 1;
2783 } else {
2784 sky2->check.last = dev->last_rx;
2785 sky2->check.mac_rp = mac_rp;
2786 sky2->check.mac_lev = mac_lev;
2787 sky2->check.fifo_rp = fifo_rp;
2788 sky2->check.fifo_lev = fifo_lev;
2789 return 0;
2790 }
2791}
2792
32c2c300 2793static void sky2_watchdog(unsigned long arg)
d27ed387 2794{
01bd7564 2795 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2796
75e80683 2797 /* Check for lost IRQ once a second */
32c2c300 2798 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2799 napi_schedule(&hw->napi);
75e80683
SH		 2800 } else {
2801 int i, active = 0;
2802
2803 for (i = 0; i < hw->ports; i++) {
bea3348e 2804 struct net_device *dev = hw->dev[i];
75e80683
SH		 2805 if (!netif_running(dev))
2806 continue;
2807 ++active;
2808
2809 /* For chips with Rx FIFO, check if stuck */
39dbd958 2810 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683 2811 sky2_rx_hung(dev)) {
ada1db5c 2812 netdev_info(dev, "receiver hang detected\n");
75e80683
SH		 2813 schedule_work(&hw->restart_work);
2814 return;
2815 }
2816 }
2817
2818 if (active == 0)
2819 return;
32c2c300 2820 }
01bd7564 2821
75e80683 2822 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2823}
2824
40b01727
SH		 2825/* Hardware/software error handling */
2826static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2827{
40b01727
SH		 2828 if (net_ratelimit())
2829 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2830
1e5f1283
SH		 2831 if (status & Y2_IS_HW_ERR)
2832 sky2_hw_intr(hw);
d257924e 2833
1e5f1283
SH		 2834 if (status & Y2_IS_IRQ_MAC1)
2835 sky2_mac_intr(hw, 0);
cd28ab6a 2836
1e5f1283
SH		 2837 if (status & Y2_IS_IRQ_MAC2)
2838 sky2_mac_intr(hw, 1);
cd28ab6a 2839
1e5f1283 2840 if (status & Y2_IS_CHK_RX1)
c119731d 2841 sky2_le_error(hw, 0, Q_R1);
d257924e 2842
1e5f1283 2843 if (status & Y2_IS_CHK_RX2)
c119731d 2844 sky2_le_error(hw, 1, Q_R2);
d257924e 2845
1e5f1283 2846 if (status & Y2_IS_CHK_TXA1)
c119731d 2847 sky2_le_error(hw, 0, Q_XA1);
d257924e 2848
1e5f1283 2849 if (status & Y2_IS_CHK_TXA2)
c119731d 2850 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2851}
2852
bea3348e 2853static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2854{
bea3348e 2855 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2856 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2857 int work_done = 0;
26691830 2858 u16 idx;
40b01727
SH		 2859
2860 if (unlikely(status & Y2_IS_ERROR))
2861 sky2_err_intr(hw, status);
2862
2863 if (status & Y2_IS_IRQ_PHY1)
2864 sky2_phy_intr(hw, 0);
2865
2866 if (status & Y2_IS_IRQ_PHY2)
2867 sky2_phy_intr(hw, 1);
cd28ab6a 2868
0f5aac70
SH		 2869 if (status & Y2_IS_PHY_QLNK)
2870 sky2_qlink_intr(hw);
2871
26691830
SH		 2872 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2873 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2874
2875 if (work_done >= work_limit)
26691830
SH		 2876 goto done;
2877 }
6f535763 2878
26691830
SH		 2879 napi_complete(napi);
2880 sky2_read32(hw, B0_Y2_SP_LISR);
2881done:
6f535763 2882
bea3348e 2883 return work_done;
e07b1aa8
SH		 2884}
2885
7d12e780 2886static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2887{
2888 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2889 u32 status;
2890
2891 /* Reading this mask interrupts as side effect */
2892 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2893 if (status == 0 || status == ~0)
2894 return IRQ_NONE;
793b883e 2895
e07b1aa8 2896 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2897
2898 napi_schedule(&hw->napi);
793b883e 2899
cd28ab6a
SH		 2900 return IRQ_HANDLED;
2901}
2902
2903#ifdef CONFIG_NET_POLL_CONTROLLER
2904static void sky2_netpoll(struct net_device *dev)
2905{
2906 struct sky2_port *sky2 = netdev_priv(dev);
2907
bea3348e 2908 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2909}
2910#endif
2911
2912/* Chip internal frequency for clock calculations */
05745c4a 2913static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2914{
793b883e 2915 switch (hw->chip_id) {
cd28ab6a 2916 case CHIP_ID_YUKON_EC:
5a5b1ea0 2917 case CHIP_ID_YUKON_EC_U:
93745494 2918 case CHIP_ID_YUKON_EX:
ed4d4161 2919 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2920 case CHIP_ID_YUKON_UL_2:
0f5aac70 2921 case CHIP_ID_YUKON_OPT:
05745c4a
SH		 2922 return 125;
2923
cd28ab6a 2924 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2925 return 100;
2926
2927 case CHIP_ID_YUKON_FE_P:
2928 return 50;
2929
2930 case CHIP_ID_YUKON_XL:
2931 return 156;
2932
2933 default:
2934 BUG();
cd28ab6a
SH		 2935 }
2936}
2937
fb17358f 2938static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2939{
fb17358f 2940 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2941}
2942
fb17358f 2943static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2944{
fb17358f 2945 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2946}
2947
fb17358f 2948
e3173832 2949static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2950{
b89165f2 2951 u8 t8;
cd28ab6a 2952
167f53d0 2953 /* Enable all clocks and check for bad PCI access */
b32f40c4 2954 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2955
cd28ab6a 2956 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2957
cd28ab6a 2958 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2959 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2960
2961 switch(hw->chip_id) {
2962 case CHIP_ID_YUKON_XL:
39dbd958 2963 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2964 break;
2965
2966 case CHIP_ID_YUKON_EC_U:
2967 hw->flags = SKY2_HW_GIGABIT
2968 | SKY2_HW_NEWER_PHY
2969 | SKY2_HW_ADV_POWER_CTL;
2970 break;
2971
2972 case CHIP_ID_YUKON_EX:
2973 hw->flags = SKY2_HW_GIGABIT
2974 | SKY2_HW_NEWER_PHY
2975 | SKY2_HW_NEW_LE
2976 | SKY2_HW_ADV_POWER_CTL;
2977
2978 /* New transmit checksum */
2979 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2980 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2981 break;
2982
2983 case CHIP_ID_YUKON_EC:
2984 /* This rev is really old, and requires untested workarounds */
2985 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2986 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2987 return -EOPNOTSUPP;
2988 }
39dbd958 2989 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2990 break;
2991
2992 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2993 break;
2994
05745c4a
SH		 2995 case CHIP_ID_YUKON_FE_P:
2996 hw->flags = SKY2_HW_NEWER_PHY
2997 | SKY2_HW_NEW_LE
2998 | SKY2_HW_AUTO_TX_SUM
2999 | SKY2_HW_ADV_POWER_CTL;
3000 break;
ed4d4161
SH		 3001
3002 case CHIP_ID_YUKON_SUPR:
3003 hw->flags = SKY2_HW_GIGABIT
3004 | SKY2_HW_NEWER_PHY
3005 | SKY2_HW_NEW_LE
3006 | SKY2_HW_AUTO_TX_SUM
3007 | SKY2_HW_ADV_POWER_CTL;
3008 break;
3009
0ce8b98d 3010 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 3011 hw->flags = SKY2_HW_GIGABIT
3012 | SKY2_HW_ADV_POWER_CTL;
3013 break;
3014
0f5aac70 3015 case CHIP_ID_YUKON_OPT:
0ce8b98d 3016 hw->flags = SKY2_HW_GIGABIT
b338682d 3017 | SKY2_HW_NEW_LE
0ce8b98d
SH		 3018 | SKY2_HW_ADV_POWER_CTL;
3019 break;
3020
ea76e635 3021 default:
b02a9258
SH		 3022 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3023 hw->chip_id);
cd28ab6a
SH		 3024 return -EOPNOTSUPP;
3025 }
3026
ea76e635
SH		 3027 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3028 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3029 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3030
e3173832
SH		 3031 hw->ports = 1;
3032 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3033 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3034 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3035 ++hw->ports;
3036 }
3037
74a61ebf
MM		 3038 if (sky2_read8(hw, B2_E_0))
3039 hw->flags |= SKY2_HW_RAM_BUFFER;
3040
e3173832
SH		 3041 return 0;
3042}
3043
3044static void sky2_reset(struct sky2_hw *hw)
3045{
555382cb 3046 struct pci_dev *pdev = hw->pdev;
e3173832 3047 u16 status;
555382cb
SH		 3048 int i, cap;
3049 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3050
cd28ab6a 3051 /* disable ASF */
acd12dde 3052 if (hw->chip_id == CHIP_ID_YUKON_EX
3053 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3054 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3055 status = sky2_read16(hw, HCU_CCSR);
3056 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3057 HCU_CCSR_UC_STATE_MSK);
acd12dde 3058 /*
3059 * CPU clock divider shouldn't be used because
3060 * - ASF firmware may malfunction
3061 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3062 */
3063 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3064 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3065 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3066 } else
3067 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3068 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3069
3070 /* do a SW reset */
3071 sky2_write8(hw, B0_CTST, CS_RST_SET);
3072 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3073
ac93a394
SH		 3074 /* allow writes to PCI config */
3075 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3076
cd28ab6a 3077 /* clear PCI errors, if any */
b32f40c4 3078 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3079 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3080 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3081
3082 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3083
555382cb
SH		 3084 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3085 if (cap) {
7782c8c4
SH		 3086 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3087 0xfffffffful);
555382cb
SH		 3088
3089 /* If error bit is stuck on ignore it */
3090 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3091 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3092 else
555382cb
SH		 3093 hwe_mask |= Y2_IS_PCI_EXP;
3094 }
cd28ab6a 3095
ae306cca 3096 sky2_power_on(hw);
a40ccc68 3097 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3098
3099 for (i = 0; i < hw->ports; i++) {
3100 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3101 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3102
ed4d4161
SH		 3103 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3104 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3105 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3106 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3107 | GMC_BYP_RETR_ON);
877c8570
SH		 3108
3109 }
3110
3111 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3112 /* enable MACSec clock gating */
3113 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3114 }
3115
0f5aac70
SH		 3116 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3117 u16 reg;
3118 u32 msk;
3119
3120 if (hw->chip_rev == 0) {
3121 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3122 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3123
3124 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3125 reg = 10;
3126 } else {
3127 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3128 reg = 3;
3129 }
3130
3131 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3132
3133 /* reset PHY Link Detect */
a40ccc68 3134 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3135 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3136 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3137 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3138
3139
3140 /* enable PHY Quick Link */
3141 msk = sky2_read32(hw, B0_IMSK);
3142 msk |= Y2_IS_PHY_QLNK;
3143 sky2_write32(hw, B0_IMSK, msk);
3144
3145 /* check if PSMv2 was running before */
3146 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3147 if (reg & PCI_EXP_LNKCTL_ASPMC) {
8b055431 3148 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
0f5aac70
SH		 3149 /* restore the PCIe Link Control register */
3150 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3151 }
a40ccc68 3152 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3153
3154 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3155 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3156 }
3157
793b883e
SH		 3158 /* Clear I2C IRQ noise */
3159 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3160
3161 /* turn off hardware timer (unused) */
3162 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3163 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3164
69634ee7
SH		 3165 /* Turn off descriptor polling */
3166 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3167
3168 /* Turn off receive timestamp */
3169 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3170 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3171
3172 /* enable the Tx Arbiters */
3173 for (i = 0; i < hw->ports; i++)
3174 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3175
3176 /* Initialize ram interface */
3177 for (i = 0; i < hw->ports; i++) {
793b883e 3178 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3179
3180 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3181 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3182 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3183 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3184 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3185 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3186 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3187 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3188 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3189 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3190 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3191 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3192 }
3193
555382cb 3194 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3195
cd28ab6a 3196 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3197 sky2_gmac_reset(hw, i);
cd28ab6a 3198
cd28ab6a
SH		 3199 memset(hw->st_le, 0, STATUS_LE_BYTES);
3200 hw->st_idx = 0;
3201
3202 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3203 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3204
3205 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3206 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3207
3208 /* Set the list last index */
793b883e 3209 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3210
290d4de5
SH		 3211 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3212 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3213
290d4de5
SH		 3214 /* set Status-FIFO ISR watermark */
3215 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3216 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3217 else
3218 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3219
290d4de5 3220 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3221 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3222 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3223
793b883e 3224 /* enable status unit */
cd28ab6a
SH		 3225 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3226
3227 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3228 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3229 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3230}
3231
af18d8b8
SH		 3232/* Take device down (offline).
3233 * Equivalent to doing dev_stop() but this does not
3234 * inform upper layers of the transistion.
3235 */
3236static void sky2_detach(struct net_device *dev)
3237{
3238 if (netif_running(dev)) {
c36531b9 3239 netif_tx_lock(dev);
af18d8b8 3240 netif_device_detach(dev); /* stop txq */
c36531b9 3241 netif_tx_unlock(dev);
af18d8b8
SH		 3242 sky2_down(dev);
3243 }
3244}
3245
3246/* Bring device back after doing sky2_detach */
3247static int sky2_reattach(struct net_device *dev)
3248{
3249 int err = 0;
3250
3251 if (netif_running(dev)) {
3252 err = sky2_up(dev);
3253 if (err) {
ada1db5c 3254 netdev_info(dev, "could not restart %d\n", err);
af18d8b8
SH		 3255 dev_close(dev);
3256 } else {
3257 netif_device_attach(dev);
3258 sky2_set_multicast(dev);
3259 }
3260 }
3261
3262 return err;
3263}
3264
81906791
SH		 3265static void sky2_restart(struct work_struct *work)
3266{
3267 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
8a0c9228 3268 u32 imask;
af18d8b8 3269 int i;
81906791 3270
81906791 3271 rtnl_lock();
81906791 3272
8cfcbe99 3273 napi_disable(&hw->napi);
8a0c9228
MM		 3274 synchronize_irq(hw->pdev->irq);
3275 imask = sky2_read32(hw, B0_IMSK);
8cfcbe99 3276 sky2_write32(hw, B0_IMSK, 0);
8a0c9228
MM		 3277
3278 for (i = 0; i < hw->ports; i++) {
3279 struct net_device *dev = hw->dev[i];
3280 struct sky2_port *sky2 = netdev_priv(dev);
3281
3282 if (!netif_running(dev))
3283 continue;
3284
3285 netif_carrier_off(dev);
3286 netif_tx_disable(dev);
3287 sky2_hw_down(sky2);
3288 }
3289
81906791 3290 sky2_reset(hw);
81906791 3291
8a0c9228
MM		 3292 for (i = 0; i < hw->ports; i++) {
3293 struct net_device *dev = hw->dev[i];
3294 struct sky2_port *sky2 = netdev_priv(dev);
3295
3296 if (!netif_running(dev))
3297 continue;
3298
3299 sky2_hw_up(sky2);
3300 netif_wake_queue(dev);
3301 }
3302
3303 sky2_write32(hw, B0_IMSK, imask);
3304 sky2_read32(hw, B0_IMSK);
3305
3306 sky2_read32(hw, B0_Y2_SP_LISR);
3307 napi_enable(&hw->napi);
81906791 3308
81906791
SH		 3309 rtnl_unlock();
3310}
3311
e3173832
SH		 3312static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3313{
3314 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3315}
3316
3317static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3318{
3319 const struct sky2_port *sky2 = netdev_priv(dev);
3320
3321 wol->supported = sky2_wol_supported(sky2->hw);
3322 wol->wolopts = sky2->wol;
3323}
3324
3325static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3326{
3327 struct sky2_port *sky2 = netdev_priv(dev);
3328 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3329
8e95a202
JP		 3330 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3331 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3332 return -EOPNOTSUPP;
3333
3334 sky2->wol = wol->wolopts;
cd28ab6a
SH		 3335 return 0;
3336}
3337
28bd181a 3338static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3339{
b89165f2
SH		 3340 if (sky2_is_copper(hw)) {
3341 u32 modes = SUPPORTED_10baseT_Half
3342 | SUPPORTED_10baseT_Full
3343 | SUPPORTED_100baseT_Half
3344 | SUPPORTED_100baseT_Full
3345 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3346
ea76e635 3347 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3348 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3349 | SUPPORTED_1000baseT_Full;
3350 return modes;
cd28ab6a 3351 } else
b89165f2
SH		 3352 return SUPPORTED_1000baseT_Half
3353 | SUPPORTED_1000baseT_Full
3354 | SUPPORTED_Autoneg
3355 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3356}
3357
793b883e 3358static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3359{
3360 struct sky2_port *sky2 = netdev_priv(dev);
3361 struct sky2_hw *hw = sky2->hw;
3362
3363 ecmd->transceiver = XCVR_INTERNAL;
3364 ecmd->supported = sky2_supported_modes(hw);
3365 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3366 if (sky2_is_copper(hw)) {
cd28ab6a 3367 ecmd->port = PORT_TP;
b89165f2
SH		 3368 ecmd->speed = sky2->speed;
3369 } else {
3370 ecmd->speed = SPEED_1000;
cd28ab6a 3371 ecmd->port = PORT_FIBRE;
b89165f2 3372 }
cd28ab6a
SH		 3373
3374 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3375 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3376 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3377 ecmd->duplex = sky2->duplex;
3378 return 0;
3379}
3380
3381static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3382{
3383 struct sky2_port *sky2 = netdev_priv(dev);
3384 const struct sky2_hw *hw = sky2->hw;
3385 u32 supported = sky2_supported_modes(hw);
3386
3387 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3388 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3389 ecmd->advertising = supported;
3390 sky2->duplex = -1;
3391 sky2->speed = -1;
3392 } else {
3393 u32 setting;
3394
793b883e 3395 switch (ecmd->speed) {
cd28ab6a
SH		 3396 case SPEED_1000:
3397 if (ecmd->duplex == DUPLEX_FULL)
3398 setting = SUPPORTED_1000baseT_Full;
3399 else if (ecmd->duplex == DUPLEX_HALF)
3400 setting = SUPPORTED_1000baseT_Half;
3401 else
3402 return -EINVAL;
3403 break;
3404 case SPEED_100:
3405 if (ecmd->duplex == DUPLEX_FULL)
3406 setting = SUPPORTED_100baseT_Full;
3407 else if (ecmd->duplex == DUPLEX_HALF)
3408 setting = SUPPORTED_100baseT_Half;
3409 else
3410 return -EINVAL;
3411 break;
3412
3413 case SPEED_10:
3414 if (ecmd->duplex == DUPLEX_FULL)
3415 setting = SUPPORTED_10baseT_Full;
3416 else if (ecmd->duplex == DUPLEX_HALF)
3417 setting = SUPPORTED_10baseT_Half;
3418 else
3419 return -EINVAL;
3420 break;
3421 default:
3422 return -EINVAL;
3423 }
3424
3425 if ((setting & supported) == 0)
3426 return -EINVAL;
3427
3428 sky2->speed = ecmd->speed;
3429 sky2->duplex = ecmd->duplex;
0ea065e5 3430 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3431 }
3432
cd28ab6a
SH		 3433 sky2->advertising = ecmd->advertising;
3434
d1b139c0 3435 if (netif_running(dev)) {
1b537565 3436 sky2_phy_reinit(sky2);
d1b139c0
SH		 3437 sky2_set_multicast(dev);
3438 }
cd28ab6a
SH		 3439
3440 return 0;
3441}
3442
3443static void sky2_get_drvinfo(struct net_device *dev,
3444 struct ethtool_drvinfo *info)
3445{
3446 struct sky2_port *sky2 = netdev_priv(dev);
3447
3448 strcpy(info->driver, DRV_NAME);
3449 strcpy(info->version, DRV_VERSION);
3450 strcpy(info->fw_version, "N/A");
3451 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3452}
3453
3454static const struct sky2_stat {
793b883e
SH		 3455 char name[ETH_GSTRING_LEN];
3456 u16 offset;
cd28ab6a
SH		 3457} sky2_stats[] = {
3458 { "tx_bytes", GM_TXO_OK_HI },
3459 { "rx_bytes", GM_RXO_OK_HI },
3460 { "tx_broadcast", GM_TXF_BC_OK },
3461 { "rx_broadcast", GM_RXF_BC_OK },
3462 { "tx_multicast", GM_TXF_MC_OK },
3463 { "rx_multicast", GM_RXF_MC_OK },
3464 { "tx_unicast", GM_TXF_UC_OK },
3465 { "rx_unicast", GM_RXF_UC_OK },
3466 { "tx_mac_pause", GM_TXF_MPAUSE },
3467 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3468 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3469 { "late_collision",GM_TXF_LAT_COL },
3470 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3471 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3472 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3473
d2604540 3474 { "rx_short", GM_RXF_SHT },
cd28ab6a 3475 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3476 { "rx_64_byte_packets", GM_RXF_64B },
3477 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3478 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3479 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3480 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3481 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3482 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3483 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3484 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3485 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3486 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3487
3488 { "tx_64_byte_packets", GM_TXF_64B },
3489 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3490 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3491 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3492 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3493 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3494 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3495 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3496};
3497
cd28ab6a
SH		 3498static u32 sky2_get_rx_csum(struct net_device *dev)
3499{
3500 struct sky2_port *sky2 = netdev_priv(dev);
3501
0ea065e5 3502 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3503}
3504
3505static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3506{
3507 struct sky2_port *sky2 = netdev_priv(dev);
3508
0ea065e5
SH		 3509 if (data)
3510 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3511 else
3512 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3513
cd28ab6a
SH		 3514 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3515 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3516
3517 return 0;
3518}
3519
3520static u32 sky2_get_msglevel(struct net_device *netdev)
3521{
3522 struct sky2_port *sky2 = netdev_priv(netdev);
3523 return sky2->msg_enable;
3524}
3525
9a7ae0a9
SH		 3526static int sky2_nway_reset(struct net_device *dev)
3527{
3528 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3529
0ea065e5 3530 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3531 return -EINVAL;
3532
1b537565 3533 sky2_phy_reinit(sky2);
d1b139c0 3534 sky2_set_multicast(dev);
9a7ae0a9
SH		 3535
3536 return 0;
3537}
3538
793b883e 3539static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3540{
3541 struct sky2_hw *hw = sky2->hw;
3542 unsigned port = sky2->port;
3543 int i;
3544
3545 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3546 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3547 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3548 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3549
793b883e 3550 for (i = 2; i < count; i++)
cd28ab6a
SH		 3551 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3552}
3553
cd28ab6a
SH		 3554static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3555{
3556 struct sky2_port *sky2 = netdev_priv(netdev);
3557 sky2->msg_enable = value;
3558}
3559
b9f2c044 3560static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3561{
b9f2c044
JG		 3562 switch (sset) {
3563 case ETH_SS_STATS:
3564 return ARRAY_SIZE(sky2_stats);
3565 default:
3566 return -EOPNOTSUPP;
3567 }
cd28ab6a
SH		 3568}
3569
3570static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3571 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3572{
3573 struct sky2_port *sky2 = netdev_priv(dev);
3574
793b883e 3575 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3576}
3577
793b883e 3578static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3579{
3580 int i;
3581
3582 switch (stringset) {
3583 case ETH_SS_STATS:
3584 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3585 memcpy(data + i * ETH_GSTRING_LEN,
3586 sky2_stats[i].name, ETH_GSTRING_LEN);
3587 break;
3588 }
3589}
3590
cd28ab6a
SH		 3591static int sky2_set_mac_address(struct net_device *dev, void *p)
3592{
3593 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3594 struct sky2_hw *hw = sky2->hw;
3595 unsigned port = sky2->port;
3596 const struct sockaddr *addr = p;
cd28ab6a
SH		 3597
3598 if (!is_valid_ether_addr(addr->sa_data))
3599 return -EADDRNOTAVAIL;
3600
cd28ab6a 3601 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3602 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3603 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3604 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3605 dev->dev_addr, ETH_ALEN);
1b537565 3606
a8ab1ec0
SH		 3607 /* virtual address for data */
3608 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3609
3610 /* physical address: used for pause frames */
3611 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3612
3613 return 0;
cd28ab6a
SH		 3614}
3615
a052b52f
SH		 3616static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3617{
3618 u32 bit;
3619
3620 bit = ether_crc(ETH_ALEN, addr) & 63;
3621 filter[bit >> 3] |= 1 << (bit & 7);
3622}
3623
cd28ab6a
SH		 3624static void sky2_set_multicast(struct net_device *dev)
3625{
3626 struct sky2_port *sky2 = netdev_priv(dev);
3627 struct sky2_hw *hw = sky2->hw;
3628 unsigned port = sky2->port;
5508590c 3629 struct dev_mc_list *list;
cd28ab6a
SH		 3630 u16 reg;
3631 u8 filter[8];
a052b52f
SH		 3632 int rx_pause;
3633 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3634
a052b52f 3635 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3636 memset(filter, 0, sizeof(filter));
3637
3638 reg = gma_read16(hw, port, GM_RX_CTRL);
3639 reg |= GM_RXCR_UCF_ENA;
3640
d571b694 3641 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3642 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3643 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3644 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3645 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3646 reg &= ~GM_RXCR_MCF_ENA;
3647 else {
cd28ab6a
SH		 3648 reg |= GM_RXCR_MCF_ENA;
3649
a052b52f
SH		 3650 if (rx_pause)
3651 sky2_add_filter(filter, pause_mc_addr);
3652
5508590c 3653 netdev_for_each_mc_addr(list, dev)
a052b52f 3654 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3655 }
3656
cd28ab6a 3657 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3658 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3659 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3660 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3661 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3662 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3663 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3664 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3665
3666 gma_write16(hw, port, GM_RX_CTRL, reg);
3667}
3668
3669/* Can have one global because blinking is controlled by
3670 * ethtool and that is always under RTNL mutex
3671 */
a84d0a3d 3672static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3673{
a84d0a3d
SH		 3674 struct sky2_hw *hw = sky2->hw;
3675 unsigned port = sky2->port;
793b883e 3676
a84d0a3d
SH		 3677 spin_lock_bh(&sky2->phy_lock);
3678 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3679 hw->chip_id == CHIP_ID_YUKON_EX ||
3680 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3681 u16 pg;
793b883e
SH		 3682 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3683 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3684
a84d0a3d
SH		 3685 switch (mode) {
3686 case MO_LED_OFF:
3687 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3688 PHY_M_LEDC_LOS_CTRL(8) |
3689 PHY_M_LEDC_INIT_CTRL(8) |
3690 PHY_M_LEDC_STA1_CTRL(8) |
3691 PHY_M_LEDC_STA0_CTRL(8));
3692 break;
3693 case MO_LED_ON:
3694 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3695 PHY_M_LEDC_LOS_CTRL(9) |
3696 PHY_M_LEDC_INIT_CTRL(9) |
3697 PHY_M_LEDC_STA1_CTRL(9) |
3698 PHY_M_LEDC_STA0_CTRL(9));
3699 break;
3700 case MO_LED_BLINK:
3701 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3702 PHY_M_LEDC_LOS_CTRL(0xa) |
3703 PHY_M_LEDC_INIT_CTRL(0xa) |
3704 PHY_M_LEDC_STA1_CTRL(0xa) |
3705 PHY_M_LEDC_STA0_CTRL(0xa));
3706 break;
3707 case MO_LED_NORM:
3708 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3709 PHY_M_LEDC_LOS_CTRL(1) |
3710 PHY_M_LEDC_INIT_CTRL(8) |
3711 PHY_M_LEDC_STA1_CTRL(7) |
3712 PHY_M_LEDC_STA0_CTRL(7));
3713 }
793b883e 3714
a84d0a3d
SH		 3715 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3716 } else
7d2e3cb7 3717 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3718 PHY_M_LED_MO_DUP(mode) |
3719 PHY_M_LED_MO_10(mode) |
3720 PHY_M_LED_MO_100(mode) |
3721 PHY_M_LED_MO_1000(mode) |
3722 PHY_M_LED_MO_RX(mode) |
3723 PHY_M_LED_MO_TX(mode));
3724
3725 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3726}
3727
3728/* blink LED's for finding board */
3729static int sky2_phys_id(struct net_device *dev, u32 data)
3730{
3731 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3732 unsigned int i;
cd28ab6a 3733
a84d0a3d
SH		 3734 if (data == 0)
3735 data = UINT_MAX;
cd28ab6a 3736
a84d0a3d
SH		 3737 for (i = 0; i < data; i++) {
3738 sky2_led(sky2, MO_LED_ON);
3739 if (msleep_interruptible(500))
3740 break;
3741 sky2_led(sky2, MO_LED_OFF);
3742 if (msleep_interruptible(500))
3743 break;
793b883e 3744 }
a84d0a3d 3745 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3746
3747 return 0;
3748}
3749
3750static void sky2_get_pauseparam(struct net_device *dev,
3751 struct ethtool_pauseparam *ecmd)
3752{
3753 struct sky2_port *sky2 = netdev_priv(dev);
3754
16ad91e1
SH		 3755 switch (sky2->flow_mode) {
3756 case FC_NONE:
3757 ecmd->tx_pause = ecmd->rx_pause = 0;
3758 break;
3759 case FC_TX:
3760 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3761 break;
3762 case FC_RX:
3763 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3764 break;
3765 case FC_BOTH:
3766 ecmd->tx_pause = ecmd->rx_pause = 1;
3767 }
3768
0ea065e5
SH		 3769 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3770 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3771}
3772
3773static int sky2_set_pauseparam(struct net_device *dev,
3774 struct ethtool_pauseparam *ecmd)
3775{
3776 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3777
0ea065e5
SH		 3778 if (ecmd->autoneg == AUTONEG_ENABLE)
3779 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3780 else
3781 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3782
16ad91e1 3783 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3784
16ad91e1
SH		 3785 if (netif_running(dev))
3786 sky2_phy_reinit(sky2);
cd28ab6a 3787
2eaba1a2 3788 return 0;
cd28ab6a
SH		 3789}
3790
fb17358f
SH		 3791static int sky2_get_coalesce(struct net_device *dev,
3792 struct ethtool_coalesce *ecmd)
3793{
3794 struct sky2_port *sky2 = netdev_priv(dev);
3795 struct sky2_hw *hw = sky2->hw;
3796
3797 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3798 ecmd->tx_coalesce_usecs = 0;
3799 else {
3800 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3801 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3802 }
3803 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3804
3805 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3806 ecmd->rx_coalesce_usecs = 0;
3807 else {
3808 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3809 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3810 }
3811 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3812
3813 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3814 ecmd->rx_coalesce_usecs_irq = 0;
3815 else {
3816 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3817 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3818 }
3819
3820 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3821
3822 return 0;
3823}
3824
3825/* Note: this affect both ports */
3826static int sky2_set_coalesce(struct net_device *dev,
3827 struct ethtool_coalesce *ecmd)
3828{
3829 struct sky2_port *sky2 = netdev_priv(dev);
3830 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3831 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3832
77b3d6a2
SH		 3833 if (ecmd->tx_coalesce_usecs > tmax ||
3834 ecmd->rx_coalesce_usecs > tmax ||
3835 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3836 return -EINVAL;
3837
ee5f68fe 3838 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3839 return -EINVAL;
ff81fbbe 3840 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3841 return -EINVAL;
ff81fbbe 3842 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3843 return -EINVAL;
3844
3845 if (ecmd->tx_coalesce_usecs == 0)
3846 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3847 else {
3848 sky2_write32(hw, STAT_TX_TIMER_INI,
3849 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3850 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3851 }
3852 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3853
3854 if (ecmd->rx_coalesce_usecs == 0)
3855 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3856 else {
3857 sky2_write32(hw, STAT_LEV_TIMER_INI,
3858 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3859 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3860 }
3861 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3862
3863 if (ecmd->rx_coalesce_usecs_irq == 0)
3864 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3865 else {
d28d4870 3866 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3867 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3868 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3869 }
3870 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3871 return 0;
3872}
3873
793b883e
SH		 3874static void sky2_get_ringparam(struct net_device *dev,
3875 struct ethtool_ringparam *ering)
3876{
3877 struct sky2_port *sky2 = netdev_priv(dev);
3878
3879 ering->rx_max_pending = RX_MAX_PENDING;
3880 ering->rx_mini_max_pending = 0;
3881 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3882 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3883
3884 ering->rx_pending = sky2->rx_pending;
3885 ering->rx_mini_pending = 0;
3886 ering->rx_jumbo_pending = 0;
3887 ering->tx_pending = sky2->tx_pending;
3888}
3889
3890static int sky2_set_ringparam(struct net_device *dev,
3891 struct ethtool_ringparam *ering)
3892{
3893 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3894
3895 if (ering->rx_pending > RX_MAX_PENDING ||
3896 ering->rx_pending < 8 ||
ee5f68fe
SH		 3897 ering->tx_pending < TX_MIN_PENDING ||
3898 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3899 return -EINVAL;
3900
af18d8b8 3901 sky2_detach(dev);
793b883e
SH		 3902
3903 sky2->rx_pending = ering->rx_pending;
3904 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3905 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3906
af18d8b8 3907 return sky2_reattach(dev);
793b883e
SH		 3908}
3909
793b883e
SH		 3910static int sky2_get_regs_len(struct net_device *dev)
3911{
6e4cbb34 3912 return 0x4000;
793b883e
SH		 3913}
3914
c32bbff8
MM		 3915static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3916{
3917 /* This complicated switch statement is to make sure and
3918 * only access regions that are unreserved.
3919 * Some blocks are only valid on dual port cards.
3920 */
3921 switch (b) {
3922 /* second port */
3923 case 5: /* Tx Arbiter 2 */
3924 case 9: /* RX2 */
3925 case 14 ... 15: /* TX2 */
3926 case 17: case 19: /* Ram Buffer 2 */
3927 case 22 ... 23: /* Tx Ram Buffer 2 */
3928 case 25: /* Rx MAC Fifo 1 */
3929 case 27: /* Tx MAC Fifo 2 */
3930 case 31: /* GPHY 2 */
3931 case 40 ... 47: /* Pattern Ram 2 */
3932 case 52: case 54: /* TCP Segmentation 2 */
3933 case 112 ... 116: /* GMAC 2 */
3934 return hw->ports > 1;
3935
3936 case 0: /* Control */
3937 case 2: /* Mac address */
3938 case 4: /* Tx Arbiter 1 */
3939 case 7: /* PCI express reg */
3940 case 8: /* RX1 */
3941 case 12 ... 13: /* TX1 */
3942 case 16: case 18:/* Rx Ram Buffer 1 */
3943 case 20 ... 21: /* Tx Ram Buffer 1 */
3944 case 24: /* Rx MAC Fifo 1 */
3945 case 26: /* Tx MAC Fifo 1 */
3946 case 28 ... 29: /* Descriptor and status unit */
3947 case 30: /* GPHY 1*/
3948 case 32 ... 39: /* Pattern Ram 1 */
3949 case 48: case 50: /* TCP Segmentation 1 */
3950 case 56 ... 60: /* PCI space */
3951 case 80 ... 84: /* GMAC 1 */
3952 return 1;
3953
3954 default:
3955 return 0;
3956 }
3957}
3958
793b883e
SH		 3959/*
3960 * Returns copy of control register region
3ead5db7 3961 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3962 */
3963static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3964 void *p)
3965{
3966 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3967 const void __iomem *io = sky2->hw->regs;
295b54c4 3968 unsigned int b;
793b883e
SH		 3969
3970 regs->version = 1;
793b883e 3971
295b54c4 3972 for (b = 0; b < 128; b++) {
c32bbff8
MM		 3973 /* skip poisonous diagnostic ram region in block 3 */
3974 if (b == 3)
295b54c4 3975 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 3976 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 3977 memcpy_fromio(p, io, 128);
c32bbff8 3978 else
295b54c4 3979 memset(p, 0, 128);
3ead5db7 3980
295b54c4
SH		 3981 p += 128;
3982 io += 128;
3983 }
793b883e 3984}
cd28ab6a 3985
b628ed98
SH		 3986/* In order to do Jumbo packets on these chips, need to turn off the
3987 * transmit store/forward. Therefore checksum offload won't work.
3988 */
3989static int no_tx_offload(struct net_device *dev)
3990{
3991 const struct sky2_port *sky2 = netdev_priv(dev);
3992 const struct sky2_hw *hw = sky2->hw;
3993
69161611 3994 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3995}
3996
3997static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3998{
3999 if (data && no_tx_offload(dev))
4000 return -EINVAL;
4001
4002 return ethtool_op_set_tx_csum(dev, data);
4003}
4004
4005
4006static int sky2_set_tso(struct net_device *dev, u32 data)
4007{
4008 if (data && no_tx_offload(dev))
4009 return -EINVAL;
4010
4011 return ethtool_op_set_tso(dev, data);
4012}
4013
f4331a6d
SH		 4014static int sky2_get_eeprom_len(struct net_device *dev)
4015{
4016 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 4017 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 4018 u16 reg2;
4019
b32f40c4 4020 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 4021 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4022}
4023
1413235c 4024static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 4025{
1413235c 4026 unsigned long start = jiffies;
f4331a6d 4027
1413235c
SH		 4028 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4029 /* Can take up to 10.6 ms for write */
4030 if (time_after(jiffies, start + HZ/4)) {
ada1db5c 4031 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
1413235c
SH		 4032 return -ETIMEDOUT;
4033 }
4034 mdelay(1);
4035 }
167f53d0 4036
1413235c
SH		 4037 return 0;
4038}
167f53d0 4039
1413235c
SH		 4040static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4041 u16 offset, size_t length)
4042{
4043 int rc = 0;
4044
4045 while (length > 0) {
4046 u32 val;
4047
4048 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4049 rc = sky2_vpd_wait(hw, cap, 0);
4050 if (rc)
4051 break;
4052
4053 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4054
4055 memcpy(data, &val, min(sizeof(val), length));
4056 offset += sizeof(u32);
4057 data += sizeof(u32);
4058 length -= sizeof(u32);
4059 }
4060
4061 return rc;
f4331a6d
SH		 4062}
4063
1413235c
SH		 4064static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4065 u16 offset, unsigned int length)
f4331a6d 4066{
1413235c
SH		 4067 unsigned int i;
4068 int rc = 0;
4069
4070 for (i = 0; i < length; i += sizeof(u32)) {
4071 u32 val = *(u32 *)(data + i);
4072
4073 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4074 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4075
4076 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4077 if (rc)
4078 break;
4079 }
4080 return rc;
f4331a6d
SH		 4081}
4082
4083static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4084 u8 *data)
4085{
4086 struct sky2_port *sky2 = netdev_priv(dev);
4087 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4088
4089 if (!cap)
4090 return -EINVAL;
4091
4092 eeprom->magic = SKY2_EEPROM_MAGIC;
4093
1413235c 4094 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4095}
4096
4097static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4098 u8 *data)
4099{
4100 struct sky2_port *sky2 = netdev_priv(dev);
4101 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4102
4103 if (!cap)
4104 return -EINVAL;
4105
4106 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4107 return -EINVAL;
4108
1413235c
SH		 4109 /* Partial writes not supported */
4110 if ((eeprom->offset & 3) || (eeprom->len & 3))
4111 return -EINVAL;
f4331a6d 4112
1413235c 4113 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4114}
4115
4116
7282d491 4117static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4118 .get_settings = sky2_get_settings,
4119 .set_settings = sky2_set_settings,
4120 .get_drvinfo = sky2_get_drvinfo,
4121 .get_wol = sky2_get_wol,
4122 .set_wol = sky2_set_wol,
4123 .get_msglevel = sky2_get_msglevel,
4124 .set_msglevel = sky2_set_msglevel,
4125 .nway_reset = sky2_nway_reset,
4126 .get_regs_len = sky2_get_regs_len,
4127 .get_regs = sky2_get_regs,
4128 .get_link = ethtool_op_get_link,
4129 .get_eeprom_len = sky2_get_eeprom_len,
4130 .get_eeprom = sky2_get_eeprom,
4131 .set_eeprom = sky2_set_eeprom,
f4331a6d 4132 .set_sg = ethtool_op_set_sg,
f4331a6d 4133 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 4134 .set_tso = sky2_set_tso,
4135 .get_rx_csum = sky2_get_rx_csum,
4136 .set_rx_csum = sky2_set_rx_csum,
4137 .get_strings = sky2_get_strings,
4138 .get_coalesce = sky2_get_coalesce,
4139 .set_coalesce = sky2_set_coalesce,
4140 .get_ringparam = sky2_get_ringparam,
4141 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4142 .get_pauseparam = sky2_get_pauseparam,
4143 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 4144 .phys_id = sky2_phys_id,
b9f2c044 4145 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 4146 .get_ethtool_stats = sky2_get_ethtool_stats,
4147};
4148
3cf26753
SH		 4149#ifdef CONFIG_SKY2_DEBUG
4150
4151static struct dentry *sky2_debug;
4152
e4c2abe2
SH		 4153
4154/*
4155 * Read and parse the first part of Vital Product Data
4156 */
4157#define VPD_SIZE 128
4158#define VPD_MAGIC 0x82
4159
4160static const struct vpd_tag {
4161 char tag[2];
4162 char *label;
4163} vpd_tags[] = {
4164 { "PN", "Part Number" },
4165 { "EC", "Engineering Level" },
4166 { "MN", "Manufacturer" },
4167 { "SN", "Serial Number" },
4168 { "YA", "Asset Tag" },
4169 { "VL", "First Error Log Message" },
4170 { "VF", "Second Error Log Message" },
4171 { "VB", "Boot Agent ROM Configuration" },
4172 { "VE", "EFI UNDI Configuration" },
4173};
4174
4175static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4176{
4177 size_t vpd_size;
4178 loff_t offs;
4179 u8 len;
4180 unsigned char *buf;
4181 u16 reg2;
4182
4183 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4184 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4185
4186 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4187 buf = kmalloc(vpd_size, GFP_KERNEL);
4188 if (!buf) {
4189 seq_puts(seq, "no memory!\n");
4190 return;
4191 }
4192
4193 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4194 seq_puts(seq, "VPD read failed\n");
4195 goto out;
4196 }
4197
4198 if (buf[0] != VPD_MAGIC) {
4199 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4200 goto out;
4201 }
4202 len = buf[1];
4203 if (len == 0 || len > vpd_size - 4) {
4204 seq_printf(seq, "Invalid id length: %d\n", len);
4205 goto out;
4206 }
4207
4208 seq_printf(seq, "%.*s\n", len, buf + 3);
4209 offs = len + 3;
4210
4211 while (offs < vpd_size - 4) {
4212 int i;
4213
4214 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4215 break;
4216 len = buf[offs + 2];
4217 if (offs + len + 3 >= vpd_size)
4218 break;
4219
4220 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4221 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4222 seq_printf(seq, " %s: %.*s\n",
4223 vpd_tags[i].label, len, buf + offs + 3);
4224 break;
4225 }
4226 }
4227 offs += len + 3;
4228 }
4229out:
4230 kfree(buf);
4231}
4232
3cf26753
SH		 4233static int sky2_debug_show(struct seq_file *seq, void *v)
4234{
4235 struct net_device *dev = seq->private;
4236 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4237 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4238 unsigned port = sky2->port;
4239 unsigned idx, last;
4240 int sop;
4241
e4c2abe2 4242 sky2_show_vpd(seq, hw);
3cf26753 4243
e4c2abe2 4244 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4245 sky2_read32(hw, B0_ISRC),
4246 sky2_read32(hw, B0_IMSK),
4247 sky2_read32(hw, B0_Y2_SP_ICR));
4248
e4c2abe2
SH		 4249 if (!netif_running(dev)) {
4250 seq_printf(seq, "network not running\n");
4251 return 0;
4252 }
4253
bea3348e 4254 napi_disable(&hw->napi);
3cf26753
SH		 4255 last = sky2_read16(hw, STAT_PUT_IDX);
4256
4257 if (hw->st_idx == last)
4258 seq_puts(seq, "Status ring (empty)\n");
4259 else {
4260 seq_puts(seq, "Status ring\n");
4261 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4262 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4263 const struct sky2_status_le *le = hw->st_le + idx;
4264 seq_printf(seq, "[%d] %#x %d %#x\n",
4265 idx, le->opcode, le->length, le->status);
4266 }
4267 seq_puts(seq, "\n");
4268 }
4269
4270 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4271 sky2->tx_cons, sky2->tx_prod,
4272 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4273 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4274
4275 /* Dump contents of tx ring */
4276 sop = 1;
ee5f68fe
SH		 4277 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4278 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4279 const struct sky2_tx_le *le = sky2->tx_le + idx;
4280 u32 a = le32_to_cpu(le->addr);
4281
4282 if (sop)
4283 seq_printf(seq, "%u:", idx);
4284 sop = 0;
4285
4286 switch(le->opcode & ~HW_OWNER) {
4287 case OP_ADDR64:
4288 seq_printf(seq, " %#x:", a);
4289 break;
4290 case OP_LRGLEN:
4291 seq_printf(seq, " mtu=%d", a);
4292 break;
4293 case OP_VLAN:
4294 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4295 break;
4296 case OP_TCPLISW:
4297 seq_printf(seq, " csum=%#x", a);
4298 break;
4299 case OP_LARGESEND:
4300 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4301 break;
4302 case OP_PACKET:
4303 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4304 break;
4305 case OP_BUFFER:
4306 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4307 break;
4308 default:
4309 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4310 a, le16_to_cpu(le->length));
4311 }
4312
4313 if (le->ctrl & EOP) {
4314 seq_putc(seq, '\n');
4315 sop = 1;
4316 }
4317 }
4318
4319 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4320 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4321 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4322 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4323
d1d08d12 4324 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4325 napi_enable(&hw->napi);
3cf26753
SH		 4326 return 0;
4327}
4328
4329static int sky2_debug_open(struct inode *inode, struct file *file)
4330{
4331 return single_open(file, sky2_debug_show, inode->i_private);
4332}
4333
4334static const struct file_operations sky2_debug_fops = {
4335 .owner = THIS_MODULE,
4336 .open = sky2_debug_open,
4337 .read = seq_read,
4338 .llseek = seq_lseek,
4339 .release = single_release,
4340};
4341
4342/*
4343 * Use network device events to create/remove/rename
4344 * debugfs file entries
4345 */
4346static int sky2_device_event(struct notifier_block *unused,
4347 unsigned long event, void *ptr)
4348{
4349 struct net_device *dev = ptr;
5b296bc9 4350 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4351
1436b301 4352 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4353 return NOTIFY_DONE;
3cf26753 4354
5b296bc9
SH		 4355 switch(event) {
4356 case NETDEV_CHANGENAME:
4357 if (sky2->debugfs) {
4358 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4359 sky2_debug, dev->name);
4360 }
4361 break;
3cf26753 4362
5b296bc9
SH		 4363 case NETDEV_GOING_DOWN:
4364 if (sky2->debugfs) {
ada1db5c 4365 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
5b296bc9
SH		 4366 debugfs_remove(sky2->debugfs);
4367 sky2->debugfs = NULL;
3cf26753 4368 }
5b296bc9
SH		 4369 break;
4370
4371 case NETDEV_UP:
4372 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4373 sky2_debug, dev,
4374 &sky2_debug_fops);
4375 if (IS_ERR(sky2->debugfs))
4376 sky2->debugfs = NULL;
3cf26753
SH		 4377 }
4378
4379 return NOTIFY_DONE;
4380}
4381
4382static struct notifier_block sky2_notifier = {
4383 .notifier_call = sky2_device_event,
4384};
4385
4386
4387static __init void sky2_debug_init(void)
4388{
4389 struct dentry *ent;
4390
4391 ent = debugfs_create_dir("sky2", NULL);
4392 if (!ent || IS_ERR(ent))
4393 return;
4394
4395 sky2_debug = ent;
4396 register_netdevice_notifier(&sky2_notifier);
4397}
4398
4399static __exit void sky2_debug_cleanup(void)
4400{
4401 if (sky2_debug) {
4402 unregister_netdevice_notifier(&sky2_notifier);
4403 debugfs_remove(sky2_debug);
4404 sky2_debug = NULL;
4405 }
4406}
4407
4408#else
4409#define sky2_debug_init()
4410#define sky2_debug_cleanup()
4411#endif
4412
1436b301
SH		 4413/* Two copies of network device operations to handle special case of
4414 not allowing netpoll on second port */
4415static const struct net_device_ops sky2_netdev_ops[2] = {
4416 {
4417 .ndo_open = sky2_up,
4418 .ndo_stop = sky2_down,
00829823 4419 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4420 .ndo_do_ioctl = sky2_ioctl,
4421 .ndo_validate_addr = eth_validate_addr,
4422 .ndo_set_mac_address = sky2_set_mac_address,
4423 .ndo_set_multicast_list = sky2_set_multicast,
4424 .ndo_change_mtu = sky2_change_mtu,
4425 .ndo_tx_timeout = sky2_tx_timeout,
4426#ifdef SKY2_VLAN_TAG_USED
4427 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4428#endif
4429#ifdef CONFIG_NET_POLL_CONTROLLER
4430 .ndo_poll_controller = sky2_netpoll,
4431#endif
4432 },
4433 {
4434 .ndo_open = sky2_up,
4435 .ndo_stop = sky2_down,
00829823 4436 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4437 .ndo_do_ioctl = sky2_ioctl,
4438 .ndo_validate_addr = eth_validate_addr,
4439 .ndo_set_mac_address = sky2_set_mac_address,
4440 .ndo_set_multicast_list = sky2_set_multicast,
4441 .ndo_change_mtu = sky2_change_mtu,
4442 .ndo_tx_timeout = sky2_tx_timeout,
4443#ifdef SKY2_VLAN_TAG_USED
4444 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4445#endif
4446 },
4447};
3cf26753 4448
cd28ab6a
SH		 4449/* Initialize network device */
4450static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4451 unsigned port,
be63a21c 4452 int highmem, int wol)
cd28ab6a
SH		 4453{
4454 struct sky2_port *sky2;
4455 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4456
4457 if (!dev) {
898eb71c 4458 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4459 return NULL;
4460 }
4461
cd28ab6a 4462 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4463 dev->irq = hw->pdev->irq;
cd28ab6a 4464 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4465 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4466 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4467
4468 sky2 = netdev_priv(dev);
4469 sky2->netdev = dev;
4470 sky2->hw = hw;
4471 sky2->msg_enable = netif_msg_init(debug, default_msg);
4472
cd28ab6a 4473 /* Auto speed and flow control */
0ea065e5
SH		 4474 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4475 if (hw->chip_id != CHIP_ID_YUKON_XL)
4476 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4477
16ad91e1
SH		 4478 sky2->flow_mode = FC_BOTH;
4479
cd28ab6a
SH		 4480 sky2->duplex = -1;
4481 sky2->speed = -1;
4482 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4483 sky2->wol = wol;
75d070c5 4484
e07b1aa8 4485 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4486
793b883e 4487 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4488 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4489 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4490
4491 hw->dev[port] = dev;
4492
4493 sky2->port = port;
4494
4a50a876 4495 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4496 if (highmem)
4497 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4498
d1f13708 4499#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4500 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4501 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4502 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4503 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4504 }
d1f13708
SH		 4505#endif
4506
cd28ab6a 4507 /* read the mac address */
793b883e 4508 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4509 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4510
cd28ab6a
SH		 4511 return dev;
4512}
4513
28bd181a 4514static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4515{
4516 const struct sky2_port *sky2 = netdev_priv(dev);
4517
6c35abae 4518 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
cd28ab6a
SH		 4519}
4520
fb2690a9 4521/* Handle software interrupt used during MSI test */
7d12e780 4522static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4523{
4524 struct sky2_hw *hw = dev_id;
4525 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4526
4527 if (status == 0)
4528 return IRQ_NONE;
4529
4530 if (status & Y2_IS_IRQ_SW) {
ea76e635 4531 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4532 wake_up(&hw->msi_wait);
4533 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4534 }
4535 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4536
4537 return IRQ_HANDLED;
4538}
4539
4540/* Test interrupt path by forcing a a software IRQ */
4541static int __devinit sky2_test_msi(struct sky2_hw *hw)
4542{
4543 struct pci_dev *pdev = hw->pdev;
4544 int err;
4545
bb507fe1
SH		 4546 init_waitqueue_head (&hw->msi_wait);
4547
fb2690a9
SH		 4548 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4549
b0a20ded 4550 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4551 if (err) {
b02a9258 4552 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4553 return err;
4554 }
4555
fb2690a9 4556 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4557 sky2_read8(hw, B0_CTST);
fb2690a9 4558
ea76e635 4559 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4560
ea76e635 4561 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4562 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4563 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4564 "switching to INTx mode.\n");
fb2690a9
SH		 4565
4566 err = -EOPNOTSUPP;
4567 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4568 }
4569
4570 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4571 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4572
4573 free_irq(pdev->irq, hw);
4574
4575 return err;
4576}
4577
c7127a34
SH		 4578/* This driver supports yukon2 chipset only */
4579static const char *sky2_name(u8 chipid, char *buf, int sz)
4580{
4581 const char *name[] = {
4582 "XL", /* 0xb3 */
4583 "EC Ultra", /* 0xb4 */
4584 "Extreme", /* 0xb5 */
4585 "EC", /* 0xb6 */
4586 "FE", /* 0xb7 */
4587 "FE+", /* 0xb8 */
4588 "Supreme", /* 0xb9 */
0ce8b98d 4589 "UL 2", /* 0xba */
0f5aac70
SH		 4590 "Unknown", /* 0xbb */
4591 "Optima", /* 0xbc */
c7127a34
SH		 4592 };
4593
dae3a511 4594 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
c7127a34
SH		 4595 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4596 else
4597 snprintf(buf, sz, "(chip %#x)", chipid);
4598 return buf;
4599}
4600
cd28ab6a
SH		 4601static int __devinit sky2_probe(struct pci_dev *pdev,
4602 const struct pci_device_id *ent)
4603{
7f60c64b 4604 struct net_device *dev;
cd28ab6a 4605 struct sky2_hw *hw;
be63a21c 4606 int err, using_dac = 0, wol_default;
3834507d 4607 u32 reg;
c7127a34 4608 char buf1[16];
cd28ab6a 4609
793b883e
SH		 4610 err = pci_enable_device(pdev);
4611 if (err) {
b02a9258 4612 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4613 goto err_out;
4614 }
4615
6cc90a5a
SH		 4616 /* Get configuration information
4617 * Note: only regular PCI config access once to test for HW issues
4618 * other PCI access through shared memory for speed and to
4619 * avoid MMCONFIG problems.
4620 */
4621 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4622 if (err) {
4623 dev_err(&pdev->dev, "PCI read config failed\n");
4624 goto err_out;
4625 }
4626
4627 if (~reg == 0) {
4628 dev_err(&pdev->dev, "PCI configuration read error\n");
4629 goto err_out;
4630 }
4631
793b883e
SH		 4632 err = pci_request_regions(pdev, DRV_NAME);
4633 if (err) {
b02a9258 4634 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4635 goto err_out_disable;
cd28ab6a
SH		 4636 }
4637
4638 pci_set_master(pdev);
4639
d1f3d4dd 4640 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4641 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4642 using_dac = 1;
6a35528a 4643 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4644 if (err < 0) {
b02a9258
SH		 4645 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4646 "for consistent allocations\n");
d1f3d4dd
SH		 4647 goto err_out_free_regions;
4648 }
d1f3d4dd 4649 } else {
284901a9 4650 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4651 if (err) {
b02a9258 4652 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4653 goto err_out_free_regions;
4654 }
4655 }
d1f3d4dd 4656
3834507d
SH		 4657
4658#ifdef __BIG_ENDIAN
4659 /* The sk98lin vendor driver uses hardware byte swapping but
4660 * this driver uses software swapping.
4661 */
4662 reg &= ~PCI_REV_DESC;
4663 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4664 if (err) {
4665 dev_err(&pdev->dev, "PCI write config failed\n");
4666 goto err_out_free_regions;
4667 }
4668#endif
4669
9d731d77 4670 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4671
cd28ab6a 4672 err = -ENOMEM;
66466797
SH		 4673
4674 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4675 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4676 if (!hw) {
b02a9258 4677 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4678 goto err_out_free_regions;
4679 }
4680
cd28ab6a 4681 hw->pdev = pdev;
66466797 4682 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4683
4684 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4685 if (!hw->regs) {
b02a9258 4686 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4687 goto err_out_free_hw;
4688 }
4689
08c06d8a 4690 /* ring for status responses */
167f53d0 4691 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4692 if (!hw->st_le)
4693 goto err_out_iounmap;
4694
e3173832 4695 err = sky2_init(hw);
cd28ab6a 4696 if (err)
793b883e 4697 goto err_out_iounmap;
cd28ab6a 4698
c844d483
SH		 4699 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4700 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4701
e3173832
SH		 4702 sky2_reset(hw);
4703
be63a21c 4704 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4705 if (!dev) {
4706 err = -ENOMEM;
cd28ab6a 4707 goto err_out_free_pci;
7f60c64b 4708 }
cd28ab6a 4709
9fa1b1f3
SH		 4710 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4711 err = sky2_test_msi(hw);
4712 if (err == -EOPNOTSUPP)
4713 pci_disable_msi(pdev);
4714 else if (err)
4715 goto err_out_free_netdev;
4716 }
4717
793b883e
SH		 4718 err = register_netdev(dev);
4719 if (err) {
b02a9258 4720 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4721 goto err_out_free_netdev;
4722 }
4723
33cb7d33
BP		 4724 netif_carrier_off(dev);
4725
6de16237
SH		 4726 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4727
ea76e635
SH		 4728 err = request_irq(pdev->irq, sky2_intr,
4729 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4730 hw->irq_name, hw);
9fa1b1f3 4731 if (err) {
b02a9258 4732 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4733 goto err_out_unregister;
4734 }
4735 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4736 napi_enable(&hw->napi);
9fa1b1f3 4737
cd28ab6a
SH		 4738 sky2_show_addr(dev);
4739
7f60c64b 4740 if (hw->ports > 1) {
4741 struct net_device *dev1;
4742
ca519274 4743 err = -ENOMEM;
be63a21c 4744 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4745 if (dev1 && (err = register_netdev(dev1)) == 0)
4746 sky2_show_addr(dev1);
4747 else {
b02a9258
SH		 4748 dev_warn(&pdev->dev,
4749 "register of second port failed (%d)\n", err);
cd28ab6a 4750 hw->dev[1] = NULL;
ca519274
SH		 4751 hw->ports = 1;
4752 if (dev1)
4753 free_netdev(dev1);
4754 }
cd28ab6a
SH		 4755 }
4756
32c2c300 4757 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4758 INIT_WORK(&hw->restart_work, sky2_restart);
4759
793b883e 4760 pci_set_drvdata(pdev, hw);
1ae861e6 4761 pdev->d3_delay = 150;
793b883e 4762
cd28ab6a
SH		 4763 return 0;
4764
793b883e 4765err_out_unregister:
ea76e635 4766 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4767 pci_disable_msi(pdev);
793b883e 4768 unregister_netdev(dev);
cd28ab6a
SH		 4769err_out_free_netdev:
4770 free_netdev(dev);
cd28ab6a 4771err_out_free_pci:
793b883e 4772 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4773 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4774err_out_iounmap:
4775 iounmap(hw->regs);
4776err_out_free_hw:
4777 kfree(hw);
4778err_out_free_regions:
4779 pci_release_regions(pdev);
44a1d2e5 4780err_out_disable:
cd28ab6a 4781 pci_disable_device(pdev);
cd28ab6a 4782err_out:
549a68c3 4783 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4784 return err;
4785}
4786
4787static void __devexit sky2_remove(struct pci_dev *pdev)
4788{
793b883e 4789 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4790 int i;
cd28ab6a 4791
793b883e 4792 if (!hw)
cd28ab6a
SH		 4793 return;
4794
32c2c300 4795 del_timer_sync(&hw->watchdog_timer);
6de16237 4796 cancel_work_sync(&hw->restart_work);
d27ed387 4797
b877fe28 4798 for (i = hw->ports-1; i >= 0; --i)
6de16237 4799 unregister_netdev(hw->dev[i]);
81906791 4800
d27ed387 4801 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4802
ae306cca
SH		 4803 sky2_power_aux(hw);
4804
793b883e 4805 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4806 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4807
4808 free_irq(pdev->irq, hw);
ea76e635 4809 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4810 pci_disable_msi(pdev);
793b883e 4811 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4812 pci_release_regions(pdev);
4813 pci_disable_device(pdev);
793b883e 4814
b877fe28 4815 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4816 free_netdev(hw->dev[i]);
4817
cd28ab6a
SH		 4818 iounmap(hw->regs);
4819 kfree(hw);
5afa0a9c 4820
cd28ab6a
SH		 4821 pci_set_drvdata(pdev, NULL);
4822}
4823
cd28ab6a
SH		 4824static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4825{
793b883e 4826 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4827 int i, wol = 0;
cd28ab6a 4828
549a68c3
SH		 4829 if (!hw)
4830 return 0;
4831
063a0b38
SH		 4832 del_timer_sync(&hw->watchdog_timer);
4833 cancel_work_sync(&hw->restart_work);
4834
19720737 4835 rtnl_lock();
f05267e7 4836 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4837 struct net_device *dev = hw->dev[i];
e3173832 4838 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4839
af18d8b8 4840 sky2_detach(dev);
e3173832
SH		 4841
4842 if (sky2->wol)
4843 sky2_wol_init(sky2);
4844
4845 wol |= sky2->wol;
cd28ab6a
SH		 4846 }
4847
5f8ae5c5 4848 device_set_wakeup_enable(&pdev->dev, wol != 0);
4849
8ab8fca2 4850 sky2_write32(hw, B0_IMSK, 0);
6de16237 4851 napi_disable(&hw->napi);
ae306cca 4852 sky2_power_aux(hw);
19720737 4853 rtnl_unlock();
e3173832 4854
d374c1c1 4855 pci_save_state(pdev);
e3173832 4856 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4857 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4858
2ccc99b7 4859 return 0;
cd28ab6a
SH		 4860}
4861
5f8ae5c5 4862#ifdef CONFIG_PM
cd28ab6a
SH		 4863static int sky2_resume(struct pci_dev *pdev)
4864{
793b883e 4865 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4866 int i, err;
cd28ab6a 4867
549a68c3
SH		 4868 if (!hw)
4869 return 0;
4870
2a400189 4871 rtnl_lock();
f71eb1a2
SH		 4872 err = pci_set_power_state(pdev, PCI_D0);
4873 if (err)
4874 goto out;
ae306cca
SH		 4875
4876 err = pci_restore_state(pdev);
4877 if (err)
4878 goto out;
4879
cd28ab6a 4880 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4881
4882 /* Re-enable all clocks */
a0db28b8 4883 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4884 if (err) {
4885 dev_err(&pdev->dev, "PCI write config failed\n");
4886 goto out;
4887 }
1ad5b4a5 4888
e3173832 4889 sky2_reset(hw);
8ab8fca2 4890 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4891 napi_enable(&hw->napi);
8ab8fca2 4892
f05267e7 4893 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4894 err = sky2_reattach(hw->dev[i]);
4895 if (err)
4896 goto out;
cd28ab6a 4897 }
af18d8b8 4898 rtnl_unlock();
eb35cf60 4899
ae306cca 4900 return 0;
08c06d8a 4901out:
af18d8b8
SH		 4902 rtnl_unlock();
4903
b02a9258 4904 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4905 pci_disable_device(pdev);
08c06d8a 4906 return err;
cd28ab6a
SH		 4907}
4908#endif
4909
e3173832
SH		 4910static void sky2_shutdown(struct pci_dev *pdev)
4911{
5f8ae5c5 4912 sky2_suspend(pdev, PMSG_SUSPEND);
e3173832
SH		 4913}
4914
cd28ab6a 4915static struct pci_driver sky2_driver = {
793b883e
SH		 4916 .name = DRV_NAME,
4917 .id_table = sky2_id_table,
4918 .probe = sky2_probe,
4919 .remove = __devexit_p(sky2_remove),
cd28ab6a 4920#ifdef CONFIG_PM
793b883e
SH		 4921 .suspend = sky2_suspend,
4922 .resume = sky2_resume,
cd28ab6a 4923#endif
e3173832 4924 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4925};
4926
4927static int __init sky2_init_module(void)
4928{
ada1db5c 4929 pr_info("driver version " DRV_VERSION "\n");
c844d483 4930
3cf26753 4931 sky2_debug_init();
50241c4c 4932 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4933}
4934
4935static void __exit sky2_cleanup_module(void)
4936{
4937 pci_unregister_driver(&sky2_driver);
3cf26753 4938 sky2_debug_cleanup();
cd28ab6a
SH		 4939}
4940
4941module_init(sky2_init_module);
4942module_exit(sky2_cleanup_module);
4943
4944MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4945MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4946MODULE_LICENSE("GPL");
5f4f9dc1 4947MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree