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[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
793b883e 26#include <linux/crc32.h>
cd28ab6a
SH		 27#include <linux/kernel.h>
28#include <linux/version.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
c73a29da 53#define DRV_VERSION "1.9"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 66#define RX_SKB_ALIGN 8
22e11703 67#define RX_BUF_WRITE 16
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
cb5d9547
SH		 80#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
cd28ab6a 82static const u32 default_msg =
793b883e
SH		 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 86
793b883e 87static int debug = -1; /* defaults above */
cd28ab6a
SH		 88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
14d0263f 91static int copybreak __read_mostly = 128;
bdb5c58e
SH		 92module_param(copybreak, int, 0);
93MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
fb2690a9
SH		 95static int disable_msi = 0;
96module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
01bd7564
SH		 99static int idle_timeout = 100;
100module_param(idle_timeout, int, 0);
101MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
102
cd28ab6a 103static const struct pci_device_id sky2_id_table[] = {
793b883e 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
cd28ab6a
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
2f4a66ad 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
cd28ab6a
SH		 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
5f5d83fd 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
57fa442c
SH		 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
2f4a66ad 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
cd28ab6a
SH		 130 { 0 }
131};
793b883e 132
cd28ab6a
SH		 133MODULE_DEVICE_TABLE(pci, sky2_id_table);
134
135/* Avoid conditionals by using array */
136static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
137static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 138static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 139
92f965e8
SH		 140/* This driver supports yukon2 chipset only */
141static const char *yukon2_name[] = {
142 "XL", /* 0xb3 */
143 "EC Ultra", /* 0xb4 */
144 "UNKNOWN", /* 0xb5 */
145 "EC", /* 0xb6 */
146 "FE", /* 0xb7 */
793b883e
SH		 147};
148
793b883e 149/* Access to external PHY */
ef743d33 150static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 151{
152 int i;
153
154 gma_write16(hw, port, GM_SMI_DATA, val);
155 gma_write16(hw, port, GM_SMI_CTRL,
156 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
157
158 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 159 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 160 return 0;
793b883e 161 udelay(1);
cd28ab6a 162 }
ef743d33 163
793b883e 164 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 165 return -ETIMEDOUT;
cd28ab6a
SH		 166}
167
ef743d33 168static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 169{
170 int i;
171
793b883e 172 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 173 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
174
175 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 176 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
177 *val = gma_read16(hw, port, GM_SMI_DATA);
178 return 0;
179 }
180
793b883e 181 udelay(1);
cd28ab6a
SH		 182 }
183
ef743d33
SH		 184 return -ETIMEDOUT;
185}
186
187static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
188{
189 u16 v;
190
191 if (__gm_phy_read(hw, port, reg, &v) != 0)
192 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
193 return v;
cd28ab6a
SH		 194}
195
2ccc99b7 196static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c
SH		 197{
198 u16 power_control;
5afa0a9c 199 int vaux;
5afa0a9c
SH		 200
201 pr_debug("sky2_set_power_state %d\n", state);
202 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
203
56a645cc 204 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 205 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c
SH		 206 (power_control & PCI_PM_CAP_PME_D3cold);
207
56a645cc 208 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c
SH		 209
210 power_control |= PCI_PM_CTRL_PME_STATUS;
211 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
212
213 switch (state) {
214 case PCI_D0:
215 /* switch power to VCC (WA for VAUX problem) */
216 sky2_write8(hw, B0_POWER_CTRL,
217 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
218
219 /* disable Core Clock Division, */
220 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
221
222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
223 /* enable bits are inverted */
224 sky2_write8(hw, B2_Y2_CLK_GATE,
225 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
226 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
227 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
228 else
229 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
230
977bdf06 231 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
d3bcfbeb
SH		 232 u32 reg1;
233
56a645cc
SH		 234 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
235 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 236 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 237 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
238 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 239 }
240
5afa0a9c
SH		 241 break;
242
243 case PCI_D3hot:
244 case PCI_D3cold:
5afa0a9c
SH		 245 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
246 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
247 else
248 /* enable bits are inverted */
249 sky2_write8(hw, B2_Y2_CLK_GATE,
250 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
251 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
252 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
253
254 /* switch power to VAUX */
255 if (vaux && state != PCI_D3cold)
256 sky2_write8(hw, B0_POWER_CTRL,
257 (PC_VAUX_ENA | PC_VCC_ENA |
258 PC_VAUX_ON | PC_VCC_OFF));
259 break;
260 default:
261 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c
SH		 262 }
263
56a645cc 264 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 265 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c
SH		 266}
267
d3bcfbeb 268static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 269{
270 u16 reg;
271
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 276
cd28ab6a
SH		 277 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
278 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
281
282 reg = gma_read16(hw, port, GM_RX_CTRL);
283 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
284 gma_write16(hw, port, GM_RX_CTRL, reg);
285}
286
287static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
288{
289 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 290 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 291
ed6d32c7 292 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 293 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 294 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
295
296 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 297 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 298 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
299
300 if (hw->chip_id == CHIP_ID_YUKON_EC)
301 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
302 else
303 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
304
305 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
306 }
307
308 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 309 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 310 if (hw->chip_id == CHIP_ID_YUKON_FE) {
311 /* enable automatic crossover */
312 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
313 } else {
314 /* disable energy detect */
315 ctrl &= ~PHY_M_PC_EN_DET_MSK;
316
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
319
320 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 321 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 322 ctrl &= ~PHY_M_PC_DSC_MSK;
323 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
324 }
325 }
cd28ab6a
SH		 326 } else {
327 /* workaround for deviation #4.88 (CRC errors) */
328 /* disable Automatic Crossover */
329
330 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 331 }
cd28ab6a 332
b89165f2
SH		 333 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
334
335 /* special setup for PHY 88E1112 Fiber */
336 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
337 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 338
b89165f2
SH		 339 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
340 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
341 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
342 ctrl &= ~PHY_M_MAC_MD_MSK;
343 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
345
346 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 347 /* select page 1 to access Fiber registers */
348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 349
350 /* for SFP-module set SIGDET polarity to low */
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 ctrl |= PHY_M_FIB_SIGD_POL;
353 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 354 }
b89165f2
SH		 355
356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 357 }
358
359 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
360 if (sky2->autoneg == AUTONEG_DISABLE)
361 ctrl &= ~PHY_CT_ANE;
362 else
363 ctrl |= PHY_CT_ANE;
364
365 ctrl |= PHY_CT_RESET;
366 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
367
368 ctrl = 0;
369 ct1000 = 0;
370 adv = PHY_AN_CSMA;
2eaba1a2 371 reg = 0;
cd28ab6a
SH		 372
373 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 374 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 375 if (sky2->advertising & ADVERTISED_1000baseT_Full)
376 ct1000 |= PHY_M_1000C_AFD;
377 if (sky2->advertising & ADVERTISED_1000baseT_Half)
378 ct1000 |= PHY_M_1000C_AHD;
379 if (sky2->advertising & ADVERTISED_100baseT_Full)
380 adv |= PHY_M_AN_100_FD;
381 if (sky2->advertising & ADVERTISED_100baseT_Half)
382 adv |= PHY_M_AN_100_HD;
383 if (sky2->advertising & ADVERTISED_10baseT_Full)
384 adv |= PHY_M_AN_10_FD;
385 if (sky2->advertising & ADVERTISED_10baseT_Half)
386 adv |= PHY_M_AN_10_HD;
b89165f2
SH		 387 } else { /* special defines for FIBER (88E1040S only) */
388 if (sky2->advertising & ADVERTISED_1000baseT_Full)
389 adv |= PHY_M_AN_1000X_AFD;
390 if (sky2->advertising & ADVERTISED_1000baseT_Half)
391 adv |= PHY_M_AN_1000X_AHD;
392 }
cd28ab6a
SH		 393
394 /* Set Flow-control capabilities */
395 if (sky2->tx_pause && sky2->rx_pause)
793b883e 396 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 397 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 398 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 399 else if (!sky2->rx_pause && sky2->tx_pause)
400 adv |= PHY_AN_PAUSE_ASYM; /* local */
401
402 /* Restart Auto-negotiation */
403 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
404 } else {
405 /* forced speed/duplex settings */
406 ct1000 = PHY_M_1000C_MSE;
407
2eaba1a2
SH		 408 /* Disable auto update for duplex flow control and speed */
409 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 410
411 switch (sky2->speed) {
412 case SPEED_1000:
413 ctrl |= PHY_CT_SP1000;
2eaba1a2 414 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 415 break;
416 case SPEED_100:
417 ctrl |= PHY_CT_SP100;
2eaba1a2 418 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 419 break;
420 }
421
2eaba1a2
SH		 422 if (sky2->duplex == DUPLEX_FULL) {
423 reg |= GM_GPCR_DUP_FULL;
424 ctrl |= PHY_CT_DUP_MD;
425 } else if (sky2->speed != SPEED_1000 && hw->chip_id != CHIP_ID_YUKON_EC_U) {
426 /* Turn off flow control for 10/100mbps */
427 sky2->rx_pause = 0;
428 sky2->tx_pause = 0;
429 }
430
431 if (!sky2->rx_pause)
432 reg |= GM_GPCR_FC_RX_DIS;
433
434 if (!sky2->tx_pause)
435 reg |= GM_GPCR_FC_TX_DIS;
436
437 /* Forward pause packets to GMAC? */
438 if (sky2->tx_pause || sky2->rx_pause)
439 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
440 else
441 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
442
cd28ab6a
SH		 443 ctrl |= PHY_CT_RESET;
444 }
445
2eaba1a2
SH		 446 gma_write16(hw, port, GM_GP_CTRL, reg);
447
cd28ab6a
SH		 448 if (hw->chip_id != CHIP_ID_YUKON_FE)
449 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
450
451 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
452 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
453
454 /* Setup Phy LED's */
455 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
456 ledover = 0;
457
458 switch (hw->chip_id) {
459 case CHIP_ID_YUKON_FE:
460 /* on 88E3082 these bits are at 11..9 (shifted left) */
461 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
462
463 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
464
465 /* delete ACT LED control bits */
466 ctrl &= ~PHY_M_FELP_LED1_MSK;
467 /* change ACT LED control to blink mode */
468 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
469 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
470 break;
471
472 case CHIP_ID_YUKON_XL:
793b883e 473 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 474
475 /* select page 3 to access LED control register */
476 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
477
478 /* set LED Function Control register */
ed6d32c7
SH		 479 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
480 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
481 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
482 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
483 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 484
485 /* set Polarity Control register */
486 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 487 (PHY_M_POLC_LS1_P_MIX(4) |
488 PHY_M_POLC_IS0_P_MIX(4) |
489 PHY_M_POLC_LOS_CTRL(2) |
490 PHY_M_POLC_INIT_CTRL(2) |
491 PHY_M_POLC_STA1_CTRL(2) |
492 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 493
494 /* restore page register */
793b883e 495 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 496 break;
ed6d32c7
SH		 497 case CHIP_ID_YUKON_EC_U:
498 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
499
500 /* select page 3 to access LED control register */
501 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
502
503 /* set LED Function Control register */
504 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
505 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
506 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
507 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
508 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
509
510 /* set Blink Rate in LED Timer Control Register */
511 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
512 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
513 /* restore page register */
514 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
515 break;
cd28ab6a
SH		 516
517 default:
518 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
519 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
520 /* turn off the Rx LED (LED_RX) */
521 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
522 }
523
ed6d32c7 524 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 525 /* apply fixes in PHY AFE */
ed6d32c7
SH		 526 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
527 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
528
977bdf06 529 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 530 gm_phy_write(hw, port, 0x18, 0xaa99);
531 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 532
977bdf06 533 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 534 gm_phy_write(hw, port, 0x18, 0xa204);
535 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 536
537 /* set page register to 0 */
ed6d32c7 538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 539 } else {
540 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 541
977bdf06
SH		 542 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
543 /* turn on 100 Mbps LED (LED_LINK100) */
544 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
545 }
cd28ab6a 546
977bdf06
SH		 547 if (ledover)
548 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
549
550 }
2eaba1a2 551
d571b694 552 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 553 if (sky2->autoneg == AUTONEG_ENABLE)
554 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
555 else
556 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
557}
558
d3bcfbeb
SH		 559static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
560{
561 u32 reg1;
562 static const u32 phy_power[]
563 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
564
565 /* looks like this XL is back asswards .. */
566 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
567 onoff = !onoff;
568
569 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
570
571 if (onoff)
572 /* Turn off phy power saving */
573 reg1 &= ~phy_power[port];
574 else
575 reg1 |= phy_power[port];
576
577 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 578 sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 579 udelay(100);
580}
581
1b537565
SH		 582/* Force a renegotiation */
583static void sky2_phy_reinit(struct sky2_port *sky2)
584{
e07b1aa8 585 spin_lock_bh(&sky2->phy_lock);
1b537565 586 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 587 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 588}
589
cd28ab6a
SH		 590static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
591{
592 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
593 u16 reg;
594 int i;
595 const u8 *addr = hw->dev[port]->dev_addr;
596
42eeea01
SH		 597 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
598 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 599
600 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
601
793b883e 602 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 603 /* WA DEV_472 -- looks like crossed wires on port 2 */
604 /* clear GMAC 1 Control reset */
605 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
606 do {
607 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
608 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
609 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
610 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
611 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
612 }
613
793b883e 614 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 615
2eaba1a2
SH		 616 /* Enable Transmit FIFO Underrun */
617 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
618
e07b1aa8 619 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 620 sky2_phy_init(hw, port);
e07b1aa8 621 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 622
623 /* MIB clear */
624 reg = gma_read16(hw, port, GM_PHY_ADDR);
625 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
626
43f2f104
SH		 627 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
628 gma_read16(hw, port, i);
cd28ab6a
SH		 629 gma_write16(hw, port, GM_PHY_ADDR, reg);
630
631 /* transmit control */
632 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
633
634 /* receive control reg: unicast + multicast + no FCS */
635 gma_write16(hw, port, GM_RX_CTRL,
793b883e 636 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 637
638 /* transmit flow control */
639 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
640
641 /* transmit parameter */
642 gma_write16(hw, port, GM_TX_PARAM,
643 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
644 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
645 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
646 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
647
648 /* serial mode register */
649 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 650 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 651
6b1a3aef 652 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 653 reg |= GM_SMOD_JUMBO_ENA;
654
655 gma_write16(hw, port, GM_SERIAL_MODE, reg);
656
cd28ab6a
SH		 657 /* virtual address for data */
658 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
659
793b883e
SH		 660 /* physical address: used for pause frames */
661 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
662
663 /* ignore counter overflows */
cd28ab6a
SH		 664 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
665 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
666 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
667
668 /* Configure Rx MAC FIFO */
669 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 670 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
671 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 672
d571b694 673 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 674 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 675
793b883e
SH		 676 /* Set threshold to 0xa (64 bytes)
677 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 678 */
679 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
680
681 /* Configure Tx MAC FIFO */
682 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
683 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 684
685 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
6e532cfe 686 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 512/8);
5a5b1ea0
SH		 687 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
688 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
689 /* set Tx GMAC FIFO Almost Empty Threshold */
690 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
691 /* Disable Store & Forward mode for TX */
692 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
693 }
694 }
695
cd28ab6a
SH		 696}
697
1c28f6ba
SH		 698/* Assign Ram Buffer allocation.
699 * start and end are in units of 4k bytes
700 * ram registers are in units of 64bit words
701 */
702static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 703{
1c28f6ba 704 u32 start, end;
cd28ab6a 705
1c28f6ba
SH		 706 start = startk * 4096/8;
707 end = (endk * 4096/8) - 1;
793b883e 708
cd28ab6a
SH		 709 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
710 sky2_write32(hw, RB_ADDR(q, RB_START), start);
711 sky2_write32(hw, RB_ADDR(q, RB_END), end);
712 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
713 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
714
715 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 716 u32 space = (endk - startk) * 4096/8;
717 u32 tp = space - space/4;
793b883e 718
1c28f6ba
SH		 719 /* On receive queue's set the thresholds
720 * give receiver priority when > 3/4 full
721 * send pause when down to 2K
722 */
723 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
724 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 725
1c28f6ba
SH		 726 tp = space - 2048/8;
727 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
728 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 729 } else {
730 /* Enable store & forward on Tx queue's because
731 * Tx FIFO is only 1K on Yukon
732 */
733 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
734 }
735
736 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 737 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 738}
739
cd28ab6a 740/* Setup Bus Memory Interface */
af4ed7e6 741static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 742{
743 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
744 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
745 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 746 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 747}
748
cd28ab6a
SH		 749/* Setup prefetch unit registers. This is the interface between
750 * hardware and driver list elements
751 */
8cc048e3 752static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 753 u64 addr, u32 last)
754{
cd28ab6a
SH		 755 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
756 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
757 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
758 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
759 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
760 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 761
762 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 763}
764
793b883e
SH		 765static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
766{
767 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
768
cb5d9547 769 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 770 le->ctrl = 0;
793b883e
SH		 771 return le;
772}
cd28ab6a 773
291ea614
SH		 774static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
775 struct sky2_tx_le *le)
776{
777 return sky2->tx_ring + (le - sky2->tx_le);
778}
779
290d4de5
SH		 780/* Update chip's next pointer */
781static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 782{
98232f85 783 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 784 wmb();
98232f85
SH		 785 sky2_write16(hw, q, idx);
786 sky2_read16(hw, q);
cd28ab6a
SH		 787}
788
793b883e 789
cd28ab6a
SH		 790static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
791{
792 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 793 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 794 le->ctrl = 0;
cd28ab6a
SH		 795 return le;
796}
797
a018e330
SH		 798/* Return high part of DMA address (could be 32 or 64 bit) */
799static inline u32 high32(dma_addr_t a)
800{
a036119f 801 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 802}
803
14d0263f
SH		 804/* Build description to hardware for one receive segment */
805static void sky2_rx_add(struct sky2_port *sky2, u8 op,
806 dma_addr_t map, unsigned len)
cd28ab6a
SH		 807{
808 struct sky2_rx_le *le;
734d1868 809 u32 hi = high32(map);
cd28ab6a 810
793b883e 811 if (sky2->rx_addr64 != hi) {
cd28ab6a 812 le = sky2_next_rx(sky2);
793b883e 813 le->addr = cpu_to_le32(hi);
cd28ab6a 814 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 815 sky2->rx_addr64 = high32(map + len);
cd28ab6a 816 }
793b883e 817
cd28ab6a 818 le = sky2_next_rx(sky2);
734d1868
SH		 819 le->addr = cpu_to_le32((u32) map);
820 le->length = cpu_to_le16(len);
14d0263f 821 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 822}
823
14d0263f
SH		 824/* Build description to hardware for one possibly fragmented skb */
825static void sky2_rx_submit(struct sky2_port *sky2,
826 const struct rx_ring_info *re)
827{
828 int i;
829
830 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
831
832 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
833 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
834}
835
836
837static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
838 unsigned size)
839{
840 struct sk_buff *skb = re->skb;
841 int i;
842
843 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
844 pci_unmap_len_set(re, data_size, size);
845
846 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
847 re->frag_addr[i] = pci_map_page(pdev,
848 skb_shinfo(skb)->frags[i].page,
849 skb_shinfo(skb)->frags[i].page_offset,
850 skb_shinfo(skb)->frags[i].size,
851 PCI_DMA_FROMDEVICE);
852}
853
854static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
855{
856 struct sk_buff *skb = re->skb;
857 int i;
858
859 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
860 PCI_DMA_FROMDEVICE);
861
862 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
863 pci_unmap_page(pdev, re->frag_addr[i],
864 skb_shinfo(skb)->frags[i].size,
865 PCI_DMA_FROMDEVICE);
866}
793b883e 867
cd28ab6a
SH		 868/* Tell chip where to start receive checksum.
869 * Actually has two checksums, but set both same to avoid possible byte
870 * order problems.
871 */
793b883e 872static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 873{
874 struct sky2_rx_le *le;
875
cd28ab6a 876 le = sky2_next_rx(sky2);
f65b138c 877 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 878 le->ctrl = 0;
879 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 880
793b883e
SH		 881 sky2_write32(sky2->hw,
882 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
883 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 884
885}
886
6b1a3aef
SH		 887/*
888 * The RX Stop command will not work for Yukon-2 if the BMU does not
889 * reach the end of packet and since we can't make sure that we have
890 * incoming data, we must reset the BMU while it is not doing a DMA
891 * transfer. Since it is possible that the RX path is still active,
892 * the RX RAM buffer will be stopped first, so any possible incoming
893 * data will not trigger a DMA. After the RAM buffer is stopped, the
894 * BMU is polled until any DMA in progress is ended and only then it
895 * will be reset.
896 */
897static void sky2_rx_stop(struct sky2_port *sky2)
898{
899 struct sky2_hw *hw = sky2->hw;
900 unsigned rxq = rxqaddr[sky2->port];
901 int i;
902
903 /* disable the RAM Buffer receive queue */
904 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
905
906 for (i = 0; i < 0xffff; i++)
907 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
908 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
909 goto stopped;
910
911 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
912 sky2->netdev->name);
913stopped:
914 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
915
916 /* reset the Rx prefetch unit */
917 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
918}
793b883e 919
d571b694 920/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 921static void sky2_rx_clean(struct sky2_port *sky2)
922{
923 unsigned i;
924
925 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 926 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 927 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 928
929 if (re->skb) {
14d0263f 930 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 931 kfree_skb(re->skb);
932 re->skb = NULL;
933 }
934 }
935}
936
ef743d33
SH		 937/* Basic MII support */
938static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
939{
940 struct mii_ioctl_data *data = if_mii(ifr);
941 struct sky2_port *sky2 = netdev_priv(dev);
942 struct sky2_hw *hw = sky2->hw;
943 int err = -EOPNOTSUPP;
944
945 if (!netif_running(dev))
946 return -ENODEV; /* Phy still in reset */
947
d89e1343 948 switch (cmd) {
ef743d33
SH		 949 case SIOCGMIIPHY:
950 data->phy_id = PHY_ADDR_MARV;
951
952 /* fallthru */
953 case SIOCGMIIREG: {
954 u16 val = 0;
91c86df5 955
e07b1aa8 956 spin_lock_bh(&sky2->phy_lock);
ef743d33 957 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 958 spin_unlock_bh(&sky2->phy_lock);
91c86df5 959
ef743d33
SH		 960 data->val_out = val;
961 break;
962 }
963
964 case SIOCSMIIREG:
965 if (!capable(CAP_NET_ADMIN))
966 return -EPERM;
967
e07b1aa8 968 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 969 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
970 data->val_in);
e07b1aa8 971 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 972 break;
973 }
974 return err;
975}
976
d1f13708
SH		 977#ifdef SKY2_VLAN_TAG_USED
978static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
979{
980 struct sky2_port *sky2 = netdev_priv(dev);
981 struct sky2_hw *hw = sky2->hw;
982 u16 port = sky2->port;
d1f13708 983
2bb8c262 984 netif_tx_lock_bh(dev);
d1f13708
SH		 985
986 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
987 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
988 sky2->vlgrp = grp;
989
2bb8c262 990 netif_tx_unlock_bh(dev);
d1f13708
SH		 991}
992
993static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
994{
995 struct sky2_port *sky2 = netdev_priv(dev);
996 struct sky2_hw *hw = sky2->hw;
997 u16 port = sky2->port;
d1f13708 998
2bb8c262 999 netif_tx_lock_bh(dev);
d1f13708
SH		 1000
1001 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1002 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1003 if (sky2->vlgrp)
1004 sky2->vlgrp->vlan_devices[vid] = NULL;
1005
2bb8c262 1006 netif_tx_unlock_bh(dev);
d1f13708
SH		 1007}
1008#endif
1009
82788c7a 1010/*
14d0263f
SH		 1011 * Allocate an skb for receiving. If the MTU is large enough
1012 * make the skb non-linear with a fragment list of pages.
1013 *
82788c7a
SH		 1014 * It appears the hardware has a bug in the FIFO logic that
1015 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1016 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1017 * aligned except if slab debugging is enabled.
82788c7a 1018 */
14d0263f 1019static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1020{
1021 struct sk_buff *skb;
14d0263f
SH		 1022 unsigned long p;
1023 int i;
82788c7a 1024
14d0263f
SH		 1025 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1026 if (!skb)
1027 goto nomem;
1028
1029 p = (unsigned long) skb->data;
1030 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1031
1032 for (i = 0; i < sky2->rx_nfrags; i++) {
1033 struct page *page = alloc_page(GFP_ATOMIC);
1034
1035 if (!page)
1036 goto free_partial;
1037 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1038 }
1039
1040 return skb;
14d0263f
SH		 1041free_partial:
1042 kfree_skb(skb);
1043nomem:
1044 return NULL;
82788c7a
SH		 1045}
1046
cd28ab6a
SH		 1047/*
1048 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1049 * Normal case this ends up creating one list element for skb
1050 * in the receive ring. Worst case if using large MTU and each
1051 * allocation falls on a different 64 bit region, that results
1052 * in 6 list elements per ring entry.
1053 * One element is used for checksum enable/disable, and one
1054 * extra to avoid wrap.
cd28ab6a 1055 */
6b1a3aef 1056static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1057{
6b1a3aef 1058 struct sky2_hw *hw = sky2->hw;
14d0263f 1059 struct rx_ring_info *re;
6b1a3aef 1060 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1061 unsigned i, size, space, thresh;
cd28ab6a 1062
6b1a3aef 1063 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1064 sky2_qset(hw, rxq);
977bdf06
SH		 1065
1066 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
1067 /* MAC Rx RAM Read is controlled by hardware */
1068 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1069 }
1070
6b1a3aef
SH		 1071 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1072
1073 rx_set_checksum(sky2);
14d0263f
SH		 1074
1075 /* Space needed for frame data + headers rounded up */
1076 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1077 + 8;
1078
1079 /* Stopping point for hardware truncation */
1080 thresh = (size - 8) / sizeof(u32);
1081
1082 /* Account for overhead of skb - to avoid order > 0 allocation */
1083 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1084 + sizeof(struct skb_shared_info);
1085
1086 sky2->rx_nfrags = space >> PAGE_SHIFT;
1087 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1088
1089 if (sky2->rx_nfrags != 0) {
1090 /* Compute residue after pages */
1091 space = sky2->rx_nfrags << PAGE_SHIFT;
1092
1093 if (space < size)
1094 size -= space;
1095 else
1096 size = 0;
1097
1098 /* Optimize to handle small packets and headers */
1099 if (size < copybreak)
1100 size = copybreak;
1101 if (size < ETH_HLEN)
1102 size = ETH_HLEN;
1103 }
1104 sky2->rx_data_size = size;
1105
1106 /* Fill Rx ring */
793b883e 1107 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1108 re = sky2->rx_ring + i;
cd28ab6a 1109
14d0263f 1110 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1111 if (!re->skb)
1112 goto nomem;
1113
14d0263f
SH		 1114 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1115 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1116 }
1117
a1433ac4
SH		 1118 /*
1119 * The receiver hangs if it receives frames larger than the
1120 * packet buffer. As a workaround, truncate oversize frames, but
1121 * the register is limited to 9 bits, so if you do frames > 2052
1122 * you better get the MTU right!
1123 */
a1433ac4
SH		 1124 if (thresh > 0x1ff)
1125 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1126 else {
1127 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1128 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1129 }
1130
6b1a3aef
SH		 1131 /* Tell chip about available buffers */
1132 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1133 return 0;
1134nomem:
1135 sky2_rx_clean(sky2);
1136 return -ENOMEM;
1137}
1138
1139/* Bring up network interface. */
1140static int sky2_up(struct net_device *dev)
1141{
1142 struct sky2_port *sky2 = netdev_priv(dev);
1143 struct sky2_hw *hw = sky2->hw;
1144 unsigned port = sky2->port;
e07b1aa8 1145 u32 ramsize, rxspace, imask;
ee7abb04 1146 int cap, err = -ENOMEM;
843a46f4 1147 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1148
ee7abb04
SH		 1149 /*
1150 * On dual port PCI-X card, there is an problem where status
1151 * can be received out of order due to split transactions
843a46f4 1152 */
ee7abb04
SH		 1153 if (otherdev && netif_running(otherdev) &&
1154 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1155 struct sky2_port *osky2 = netdev_priv(otherdev);
1156 u16 cmd;
1157
1158 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1159 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1160 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1161
1162 sky2->rx_csum = 0;
1163 osky2->rx_csum = 0;
1164 }
843a46f4 1165
cd28ab6a
SH		 1166 if (netif_msg_ifup(sky2))
1167 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1168
1169 /* must be power of 2 */
1170 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1171 TX_RING_SIZE *
1172 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1173 &sky2->tx_le_map);
1174 if (!sky2->tx_le)
1175 goto err_out;
1176
6cdbbdf3 1177 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1178 GFP_KERNEL);
1179 if (!sky2->tx_ring)
1180 goto err_out;
1181 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1182
1183 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1184 &sky2->rx_le_map);
1185 if (!sky2->rx_le)
1186 goto err_out;
1187 memset(sky2->rx_le, 0, RX_LE_BYTES);
1188
291ea614 1189 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1190 GFP_KERNEL);
1191 if (!sky2->rx_ring)
1192 goto err_out;
1193
d3bcfbeb
SH		 1194 sky2_phy_power(hw, port, 1);
1195
cd28ab6a
SH		 1196 sky2_mac_init(hw, port);
1197
1c28f6ba
SH		 1198 /* Determine available ram buffer space (in 4K blocks).
1199 * Note: not sure about the FE setting below yet
1200 */
1201 if (hw->chip_id == CHIP_ID_YUKON_FE)
1202 ramsize = 4;
1203 else
1204 ramsize = sky2_read8(hw, B2_E_0);
1205
1206 /* Give transmitter one third (rounded up) */
1207 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1208
cd28ab6a 1209 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1210 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1211
793b883e
SH		 1212 /* Make sure SyncQ is disabled */
1213 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1214 RB_RST_SET);
1215
af4ed7e6 1216 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1217
977bdf06 1218 /* Set almost empty threshold */
c2716fb4
SH		 1219 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1220 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1221 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1222
6b1a3aef
SH		 1223 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1224 TX_RING_SIZE - 1);
cd28ab6a 1225
6b1a3aef 1226 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1227 if (err)
1228 goto err_out;
1229
cd28ab6a 1230 /* Enable interrupts from phy/mac for port */
e07b1aa8 1231 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1232 imask |= portirq_msk[port];
e07b1aa8
SH		 1233 sky2_write32(hw, B0_IMSK, imask);
1234
cd28ab6a
SH		 1235 return 0;
1236
1237err_out:
1b537565 1238 if (sky2->rx_le) {
cd28ab6a
SH		 1239 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1240 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1241 sky2->rx_le = NULL;
1242 }
1243 if (sky2->tx_le) {
cd28ab6a
SH		 1244 pci_free_consistent(hw->pdev,
1245 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1246 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1247 sky2->tx_le = NULL;
1248 }
1249 kfree(sky2->tx_ring);
1250 kfree(sky2->rx_ring);
cd28ab6a 1251
1b537565
SH		 1252 sky2->tx_ring = NULL;
1253 sky2->rx_ring = NULL;
cd28ab6a
SH		 1254 return err;
1255}
1256
793b883e
SH		 1257/* Modular subtraction in ring */
1258static inline int tx_dist(unsigned tail, unsigned head)
1259{
cb5d9547 1260 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1261}
cd28ab6a 1262
793b883e
SH		 1263/* Number of list elements available for next tx */
1264static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1265{
793b883e 1266 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1267}
1268
793b883e 1269/* Estimate of number of transmit list elements required */
28bd181a 1270static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1271{
793b883e
SH		 1272 unsigned count;
1273
1274 count = sizeof(dma_addr_t) / sizeof(u32);
1275 count += skb_shinfo(skb)->nr_frags * count;
1276
89114afd 1277 if (skb_is_gso(skb))
793b883e
SH		 1278 ++count;
1279
84fa7933 1280 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1281 ++count;
1282
1283 return count;
cd28ab6a
SH		 1284}
1285
793b883e
SH		 1286/*
1287 * Put one packet in ring for transmit.
1288 * A single packet can generate multiple list elements, and
1289 * the number of ring elements will probably be less than the number
1290 * of list elements used.
1291 */
cd28ab6a
SH		 1292static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1293{
1294 struct sky2_port *sky2 = netdev_priv(dev);
1295 struct sky2_hw *hw = sky2->hw;
d1f13708 1296 struct sky2_tx_le *le = NULL;
6cdbbdf3 1297 struct tx_ring_info *re;
cd28ab6a
SH		 1298 unsigned i, len;
1299 dma_addr_t mapping;
1300 u32 addr64;
1301 u16 mss;
1302 u8 ctrl;
1303
2bb8c262
SH		 1304 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1305 return NETDEV_TX_BUSY;
cd28ab6a 1306
793b883e 1307 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1308 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1309 dev->name, sky2->tx_prod, skb->len);
1310
cd28ab6a
SH		 1311 len = skb_headlen(skb);
1312 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1313 addr64 = high32(mapping);
793b883e 1314
a018e330
SH		 1315 /* Send high bits if changed or crosses boundary */
1316 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1317 le = get_tx_le(sky2);
f65b138c 1318 le->addr = cpu_to_le32(addr64);
793b883e 1319 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1320 sky2->tx_addr64 = high32(mapping + len);
793b883e 1321 }
cd28ab6a
SH		 1322
1323 /* Check for TCP Segmentation Offload */
7967168c 1324 mss = skb_shinfo(skb)->gso_size;
793b883e 1325 if (mss != 0) {
cd28ab6a
SH		 1326 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1327 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1328 mss += ETH_HLEN;
1329
e07560cd
SH		 1330 if (mss != sky2->tx_last_mss) {
1331 le = get_tx_le(sky2);
f65b138c 1332 le->addr = cpu_to_le32(mss);
e07560cd 1333 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1334 sky2->tx_last_mss = mss;
1335 }
cd28ab6a
SH		 1336 }
1337
cd28ab6a 1338 ctrl = 0;
d1f13708
SH		 1339#ifdef SKY2_VLAN_TAG_USED
1340 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1341 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1342 if (!le) {
1343 le = get_tx_le(sky2);
f65b138c 1344 le->addr = 0;
d1f13708 1345 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1346 } else
1347 le->opcode |= OP_VLAN;
1348 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1349 ctrl |= INS_VLAN;
1350 }
1351#endif
1352
1353 /* Handle TCP checksum offload */
84fa7933 1354 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1355 unsigned offset = skb->h.raw - skb->data;
1356 u32 tcpsum;
1357
1358 tcpsum = offset << 16; /* sum start */
1359 tcpsum |= offset + skb->csum; /* sum write */
cd28ab6a
SH		 1360
1361 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1362 if (skb->nh.iph->protocol == IPPROTO_UDP)
1363 ctrl |= UDPTCP;
1364
f65b138c
SH		 1365 if (tcpsum != sky2->tx_tcpsum) {
1366 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1367
1368 le = get_tx_le(sky2);
f65b138c 1369 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1370 le->length = 0; /* initial checksum value */
1371 le->ctrl = 1; /* one packet */
1372 le->opcode = OP_TCPLISW | HW_OWNER;
1373 }
cd28ab6a
SH		 1374 }
1375
1376 le = get_tx_le(sky2);
f65b138c 1377 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1378 le->length = cpu_to_le16(len);
1379 le->ctrl = ctrl;
793b883e 1380 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1381
291ea614 1382 re = tx_le_re(sky2, le);
cd28ab6a 1383 re->skb = skb;
6cdbbdf3 1384 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1385 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1386
1387 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1388 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1389
1390 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1391 frag->size, PCI_DMA_TODEVICE);
a036119f 1392 addr64 = high32(mapping);
793b883e
SH		 1393 if (addr64 != sky2->tx_addr64) {
1394 le = get_tx_le(sky2);
f65b138c 1395 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1396 le->ctrl = 0;
1397 le->opcode = OP_ADDR64 | HW_OWNER;
1398 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1399 }
1400
1401 le = get_tx_le(sky2);
f65b138c 1402 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1403 le->length = cpu_to_le16(frag->size);
1404 le->ctrl = ctrl;
793b883e 1405 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1406
291ea614
SH		 1407 re = tx_le_re(sky2, le);
1408 re->skb = skb;
1409 pci_unmap_addr_set(re, mapaddr, mapping);
1410 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1411 }
6cdbbdf3 1412
cd28ab6a
SH		 1413 le->ctrl |= EOP;
1414
97bda706
SH		 1415 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1416 netif_stop_queue(dev);
b19666d9 1417
290d4de5 1418 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1419
cd28ab6a
SH		 1420 dev->trans_start = jiffies;
1421 return NETDEV_TX_OK;
1422}
1423
cd28ab6a 1424/*
793b883e
SH		 1425 * Free ring elements from starting at tx_cons until "done"
1426 *
1427 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1428 * buffers so make sure not to free skb to early.
cd28ab6a 1429 */
d11c13e7 1430static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1431{
d11c13e7 1432 struct net_device *dev = sky2->netdev;
af2a58ac 1433 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1434 unsigned idx;
cd28ab6a 1435
0e3ff6aa 1436 BUG_ON(done >= TX_RING_SIZE);
2224795d 1437
291ea614
SH		 1438 for (idx = sky2->tx_cons; idx != done;
1439 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1440 struct sky2_tx_le *le = sky2->tx_le + idx;
1441 struct tx_ring_info *re = sky2->tx_ring + idx;
1442
1443 switch(le->opcode & ~HW_OWNER) {
1444 case OP_LARGESEND:
1445 case OP_PACKET:
1446 pci_unmap_single(pdev,
1447 pci_unmap_addr(re, mapaddr),
1448 pci_unmap_len(re, maplen),
1449 PCI_DMA_TODEVICE);
af2a58ac 1450 break;
291ea614
SH		 1451 case OP_BUFFER:
1452 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1453 pci_unmap_len(re, maplen),
734d1868 1454 PCI_DMA_TODEVICE);
291ea614
SH		 1455 break;
1456 }
1457
1458 if (le->ctrl & EOP) {
1459 if (unlikely(netif_msg_tx_done(sky2)))
1460 printk(KERN_DEBUG "%s: tx done %u\n",
1461 dev->name, idx);
1462 dev_kfree_skb(re->skb);
cd28ab6a
SH		 1463 }
1464
291ea614 1465 le->opcode = 0; /* paranoia */
793b883e 1466 }
793b883e 1467
291ea614 1468 sky2->tx_cons = idx;
22e11703 1469 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1470 netif_wake_queue(dev);
cd28ab6a
SH		 1471}
1472
1473/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1474static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1475{
2bb8c262
SH		 1476 struct sky2_port *sky2 = netdev_priv(dev);
1477
1478 netif_tx_lock_bh(dev);
d11c13e7 1479 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1480 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1481}
1482
1483/* Network shutdown */
1484static int sky2_down(struct net_device *dev)
1485{
1486 struct sky2_port *sky2 = netdev_priv(dev);
1487 struct sky2_hw *hw = sky2->hw;
1488 unsigned port = sky2->port;
1489 u16 ctrl;
e07b1aa8 1490 u32 imask;
cd28ab6a 1491
1b537565
SH		 1492 /* Never really got started! */
1493 if (!sky2->tx_le)
1494 return 0;
1495
cd28ab6a
SH		 1496 if (netif_msg_ifdown(sky2))
1497 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1498
018d1c66 1499 /* Stop more packets from being queued */
cd28ab6a
SH		 1500 netif_stop_queue(dev);
1501
d3bcfbeb 1502 sky2_gmac_reset(hw, port);
793b883e 1503
cd28ab6a
SH		 1504 /* Stop transmitter */
1505 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1506 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1507
1508 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1509 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1510
c2716fb4
SH		 1511 /* WA for dev. #4.209 */
1512 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1513 && hw->chip_rev == CHIP_REV_YU_EC_U_A1)
1514 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1515 sky2->speed != SPEED_1000 ?
1516 TX_STFW_ENA : TX_STFW_DIS);
1517
cd28ab6a 1518 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1519 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1520 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1521
1522 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1523
1524 /* Workaround shared GMAC reset */
793b883e
SH		 1525 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1526 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1527 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1528
1529 /* Disable Force Sync bit and Enable Alloc bit */
1530 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1531 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1532
1533 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1534 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1535 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1536
1537 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1538 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1539 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1540
1541 /* Reset the Tx prefetch units */
1542 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1543 PREF_UNIT_RST_SET);
1544
1545 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1546
6b1a3aef 1547 sky2_rx_stop(sky2);
cd28ab6a
SH		 1548
1549 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1550 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1551
e07b1aa8
SH		 1552 /* Disable port IRQ */
1553 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1554 imask &= ~portirq_msk[port];
e07b1aa8
SH		 1555 sky2_write32(hw, B0_IMSK, imask);
1556
d3bcfbeb
SH		 1557 sky2_phy_power(hw, port, 0);
1558
d571b694 1559 /* turn off LED's */
cd28ab6a
SH		 1560 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1561
018d1c66
SH		 1562 synchronize_irq(hw->pdev->irq);
1563
2bb8c262 1564 sky2_tx_clean(dev);
cd28ab6a
SH		 1565 sky2_rx_clean(sky2);
1566
1567 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1568 sky2->rx_le, sky2->rx_le_map);
1569 kfree(sky2->rx_ring);
1570
1571 pci_free_consistent(hw->pdev,
1572 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1573 sky2->tx_le, sky2->tx_le_map);
1574 kfree(sky2->tx_ring);
1575
1b537565
SH		 1576 sky2->tx_le = NULL;
1577 sky2->rx_le = NULL;
1578
1579 sky2->rx_ring = NULL;
1580 sky2->tx_ring = NULL;
1581
cd28ab6a
SH		 1582 return 0;
1583}
1584
1585static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1586{
b89165f2 1587 if (!sky2_is_copper(hw))
793b883e
SH		 1588 return SPEED_1000;
1589
cd28ab6a
SH		 1590 if (hw->chip_id == CHIP_ID_YUKON_FE)
1591 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1592
1593 switch (aux & PHY_M_PS_SPEED_MSK) {
1594 case PHY_M_PS_SPEED_1000:
1595 return SPEED_1000;
1596 case PHY_M_PS_SPEED_100:
1597 return SPEED_100;
1598 default:
1599 return SPEED_10;
1600 }
1601}
1602
1603static void sky2_link_up(struct sky2_port *sky2)
1604{
1605 struct sky2_hw *hw = sky2->hw;
1606 unsigned port = sky2->port;
1607 u16 reg;
1608
cd28ab6a 1609 /* enable Rx/Tx */
2eaba1a2 1610 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1611 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1612 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1613
1614 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1615
1616 netif_carrier_on(sky2->netdev);
1617 netif_wake_queue(sky2->netdev);
1618
1619 /* Turn on link LED */
793b883e 1620 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1621 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1622
ed6d32c7 1623 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1624 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1625 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1626
1627 switch(sky2->speed) {
1628 case SPEED_10:
1629 led |= PHY_M_LEDC_INIT_CTRL(7);
1630 break;
1631
1632 case SPEED_100:
1633 led |= PHY_M_LEDC_STA1_CTRL(7);
1634 break;
1635
1636 case SPEED_1000:
1637 led |= PHY_M_LEDC_STA0_CTRL(7);
1638 break;
1639 }
793b883e
SH		 1640
1641 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1642 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1643 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1644 }
1645
cd28ab6a
SH		 1646 if (netif_msg_link(sky2))
1647 printk(KERN_INFO PFX
d571b694 1648 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1649 sky2->netdev->name, sky2->speed,
1650 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1651 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1652 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1653}
1654
1655static void sky2_link_down(struct sky2_port *sky2)
1656{
1657 struct sky2_hw *hw = sky2->hw;
1658 unsigned port = sky2->port;
1659 u16 reg;
1660
1661 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1662
1663 reg = gma_read16(hw, port, GM_GP_CTRL);
1664 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1665 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1666
1667 if (sky2->rx_pause && !sky2->tx_pause) {
1668 /* restore Asymmetric Pause bit */
1669 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1670 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1671 | PHY_M_AN_ASP);
cd28ab6a
SH		 1672 }
1673
cd28ab6a
SH		 1674 netif_carrier_off(sky2->netdev);
1675 netif_stop_queue(sky2->netdev);
1676
1677 /* Turn on link LED */
1678 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1679
1680 if (netif_msg_link(sky2))
1681 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1682
cd28ab6a
SH		 1683 sky2_phy_init(hw, port);
1684}
1685
793b883e
SH		 1686static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1687{
1688 struct sky2_hw *hw = sky2->hw;
1689 unsigned port = sky2->port;
1690 u16 lpa;
1691
1692 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1693
1694 if (lpa & PHY_M_AN_RF) {
1695 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1696 return -1;
1697 }
1698
793b883e
SH		 1699 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1700 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1701 sky2->netdev->name);
1702 return -1;
1703 }
1704
793b883e 1705 sky2->speed = sky2_phy_speed(hw, aux);
e0ed5459
SH		 1706 if (sky2->speed == SPEED_1000) {
1707 u16 ctl2 = gm_phy_read(hw, port, PHY_MARV_1000T_CTRL);
1708 u16 lpa2 = gm_phy_read(hw, port, PHY_MARV_1000T_STAT);
1709 if (lpa2 & PHY_B_1000S_MSF) {
1710 printk(KERN_ERR PFX "%s: master/slave fault",
1711 sky2->netdev->name);
1712 return -1;
1713 }
1714
1715 if ((ctl2 & PHY_M_1000C_AFD) && (lpa2 & PHY_B_1000S_LP_FD))
1716 sky2->duplex = DUPLEX_FULL;
1717 else
1718 sky2->duplex = DUPLEX_HALF;
1719 } else {
1720 u16 adv = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1721 if ((aux & adv) & PHY_AN_FULL)
1722 sky2->duplex = DUPLEX_FULL;
1723 else
1724 sky2->duplex = DUPLEX_HALF;
1725 }
793b883e
SH		 1726
1727 /* Pause bits are offset (9..8) */
ed6d32c7 1728 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1729 aux >>= 6;
1730
1731 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1732 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1733
2eaba1a2
SH		 1734 if (sky2->duplex == DUPLEX_HALF && sky2->speed != SPEED_1000
1735 && hw->chip_id != CHIP_ID_YUKON_EC_U)
1736 sky2->rx_pause = sky2->tx_pause = 0;
1737
1738 if (sky2->rx_pause || sky2->tx_pause)
793b883e
SH		 1739 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1740 else
1741 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1742
1743 return 0;
1744}
cd28ab6a 1745
e07b1aa8
SH		 1746/* Interrupt from PHY */
1747static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1748{
e07b1aa8
SH		 1749 struct net_device *dev = hw->dev[port];
1750 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1751 u16 istatus, phystat;
1752
e07b1aa8
SH		 1753 spin_lock(&sky2->phy_lock);
1754 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1755 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1756
1757 if (!netif_running(dev))
1758 goto out;
cd28ab6a
SH		 1759
1760 if (netif_msg_intr(sky2))
1761 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1762 sky2->netdev->name, istatus, phystat);
1763
2eaba1a2 1764 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1765 if (sky2_autoneg_done(sky2, phystat) == 0)
1766 sky2_link_up(sky2);
1767 goto out;
1768 }
cd28ab6a 1769
793b883e
SH		 1770 if (istatus & PHY_M_IS_LSP_CHANGE)
1771 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1772
793b883e
SH		 1773 if (istatus & PHY_M_IS_DUP_CHANGE)
1774 sky2->duplex =
1775 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1776
793b883e
SH		 1777 if (istatus & PHY_M_IS_LST_CHANGE) {
1778 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1779 sky2_link_up(sky2);
793b883e
SH		 1780 else
1781 sky2_link_down(sky2);
cd28ab6a 1782 }
793b883e 1783out:
e07b1aa8 1784 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1785}
1786
302d1252
SH		 1787
1788/* Transmit timeout is only called if we are running, carries is up
1789 * and tx queue is full (stopped).
1790 */
cd28ab6a
SH		 1791static void sky2_tx_timeout(struct net_device *dev)
1792{
1793 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1794 struct sky2_hw *hw = sky2->hw;
1795 unsigned txq = txqaddr[sky2->port];
8f24664d 1796 u16 report, done;
cd28ab6a
SH		 1797
1798 if (netif_msg_timer(sky2))
1799 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1800
8f24664d
SH		 1801 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1802 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1803
8f24664d
SH		 1804 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1805 dev->name,
1806 sky2->tx_cons, sky2->tx_prod, report, done);
1807
1808 if (report != done) {
1809 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1810
1811 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1812 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1813 } else if (report != sky2->tx_cons) {
1814 printk(KERN_INFO PFX "status report lost?\n");
1815
2bb8c262 1816 netif_tx_lock_bh(dev);
8f24664d 1817 sky2_tx_complete(sky2, report);
2bb8c262 1818 netif_tx_unlock_bh(dev);
8f24664d
SH		 1819 } else {
1820 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1821
8f24664d
SH		 1822 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1823 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1824
2bb8c262 1825 sky2_tx_clean(dev);
8f24664d
SH		 1826
1827 sky2_qset(hw, txq);
1828 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1829 }
cd28ab6a
SH		 1830}
1831
1832static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1833{
6b1a3aef
SH		 1834 struct sky2_port *sky2 = netdev_priv(dev);
1835 struct sky2_hw *hw = sky2->hw;
1836 int err;
1837 u16 ctl, mode;
e07b1aa8 1838 u32 imask;
cd28ab6a
SH		 1839
1840 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1841 return -EINVAL;
1842
5a5b1ea0
SH		 1843 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1844 return -EINVAL;
1845
6b1a3aef
SH		 1846 if (!netif_running(dev)) {
1847 dev->mtu = new_mtu;
1848 return 0;
1849 }
1850
e07b1aa8 1851 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1852 sky2_write32(hw, B0_IMSK, 0);
1853
018d1c66
SH		 1854 dev->trans_start = jiffies; /* prevent tx timeout */
1855 netif_stop_queue(dev);
1856 netif_poll_disable(hw->dev[0]);
1857
e07b1aa8
SH		 1858 synchronize_irq(hw->pdev->irq);
1859
6b1a3aef
SH		 1860 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1861 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1862 sky2_rx_stop(sky2);
1863 sky2_rx_clean(sky2);
cd28ab6a
SH		 1864
1865 dev->mtu = new_mtu;
14d0263f 1866
6b1a3aef
SH		 1867 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1868 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1869
1870 if (dev->mtu > ETH_DATA_LEN)
1871 mode |= GM_SMOD_JUMBO_ENA;
1872
1873 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1874
6b1a3aef 1875 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1876
6b1a3aef 1877 err = sky2_rx_start(sky2);
e07b1aa8 1878 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1879
1b537565
SH		 1880 if (err)
1881 dev_close(dev);
1882 else {
1883 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1884
1885 netif_poll_enable(hw->dev[0]);
1886 netif_wake_queue(dev);
1887 }
1888
cd28ab6a
SH		 1889 return err;
1890}
1891
14d0263f
SH		 1892/* For small just reuse existing skb for next receive */
1893static struct sk_buff *receive_copy(struct sky2_port *sky2,
1894 const struct rx_ring_info *re,
1895 unsigned length)
1896{
1897 struct sk_buff *skb;
1898
1899 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1900 if (likely(skb)) {
1901 skb_reserve(skb, 2);
1902 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1903 length, PCI_DMA_FROMDEVICE);
1904 memcpy(skb->data, re->skb->data, length);
1905 skb->ip_summed = re->skb->ip_summed;
1906 skb->csum = re->skb->csum;
1907 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1908 length, PCI_DMA_FROMDEVICE);
1909 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1910 skb_put(skb, length);
14d0263f
SH		 1911 }
1912 return skb;
1913}
1914
1915/* Adjust length of skb with fragments to match received data */
1916static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1917 unsigned int length)
1918{
1919 int i, num_frags;
1920 unsigned int size;
1921
1922 /* put header into skb */
1923 size = min(length, hdr_space);
1924 skb->tail += size;
1925 skb->len += size;
1926 length -= size;
1927
1928 num_frags = skb_shinfo(skb)->nr_frags;
1929 for (i = 0; i < num_frags; i++) {
1930 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1931
1932 if (length == 0) {
1933 /* don't need this page */
1934 __free_page(frag->page);
1935 --skb_shinfo(skb)->nr_frags;
1936 } else {
1937 size = min(length, (unsigned) PAGE_SIZE);
1938
1939 frag->size = size;
1940 skb->data_len += size;
1941 skb->truesize += size;
1942 skb->len += size;
1943 length -= size;
1944 }
1945 }
1946}
1947
1948/* Normal packet - take skb from ring element and put in a new one */
1949static struct sk_buff *receive_new(struct sky2_port *sky2,
1950 struct rx_ring_info *re,
1951 unsigned int length)
1952{
1953 struct sk_buff *skb, *nskb;
1954 unsigned hdr_space = sky2->rx_data_size;
1955
1956 pr_debug(PFX "receive new length=%d\n", length);
1957
1958 /* Don't be tricky about reusing pages (yet) */
1959 nskb = sky2_rx_alloc(sky2);
1960 if (unlikely(!nskb))
1961 return NULL;
1962
1963 skb = re->skb;
1964 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1965
1966 prefetch(skb->data);
1967 re->skb = nskb;
1968 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
1969
1970 if (skb_shinfo(skb)->nr_frags)
1971 skb_put_frags(skb, hdr_space, length);
1972 else
489b10c1 1973 skb_put(skb, length);
14d0263f
SH		 1974 return skb;
1975}
1976
cd28ab6a
SH		 1977/*
1978 * Receive one packet.
d571b694 1979 * For larger packets, get new buffer.
cd28ab6a 1980 */
497d7c86 1981static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 1982 u16 length, u32 status)
1983{
497d7c86 1984 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 1985 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1986 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1987
1988 if (unlikely(netif_msg_rx_status(sky2)))
1989 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 1990 dev->name, sky2->rx_next, status, length);
cd28ab6a 1991
793b883e 1992 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1993 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1994
42eeea01 1995 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1996 goto error;
1997
42eeea01
SH		 1998 if (!(status & GMR_FS_RX_OK))
1999 goto resubmit;
2000
497d7c86 2001 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 2002 goto oversize;
2003
14d0263f
SH		 2004 if (length < copybreak)
2005 skb = receive_copy(sky2, re, length);
2006 else
2007 skb = receive_new(sky2, re, length);
793b883e 2008resubmit:
14d0263f 2009 sky2_rx_submit(sky2, re);
79e57d32 2010
cd28ab6a
SH		 2011 return skb;
2012
6e15b712
SH		 2013oversize:
2014 ++sky2->net_stats.rx_over_errors;
2015 goto resubmit;
2016
cd28ab6a 2017error:
6e15b712
SH		 2018 ++sky2->net_stats.rx_errors;
2019
3be92a70 2020 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2021 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2022 dev->name, status, length);
793b883e
SH		 2023
2024 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2025 sky2->net_stats.rx_length_errors++;
2026 if (status & GMR_FS_FRAGMENT)
2027 sky2->net_stats.rx_frame_errors++;
2028 if (status & GMR_FS_CRC_ERR)
2029 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 2030 if (status & GMR_FS_RX_FF_OV)
2031 sky2->net_stats.rx_fifo_errors++;
79e57d32 2032
793b883e 2033 goto resubmit;
cd28ab6a
SH		 2034}
2035
e07b1aa8
SH		 2036/* Transmit complete */
2037static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2038{
e07b1aa8 2039 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2040
e07b1aa8 2041 if (netif_running(dev)) {
2bb8c262 2042 netif_tx_lock(dev);
e07b1aa8 2043 sky2_tx_complete(sky2, last);
2bb8c262 2044 netif_tx_unlock(dev);
2224795d 2045 }
cd28ab6a
SH		 2046}
2047
e07b1aa8
SH		 2048/* Process status response ring */
2049static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2050{
22e11703 2051 struct sky2_port *sky2;
e07b1aa8 2052 int work_done = 0;
22e11703 2053 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2054 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2055
af2a58ac 2056 rmb();
bea86103 2057
e71ebd73 2058 while (hw->st_idx != hwidx) {
13210ce5
SH		 2059 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2060 struct net_device *dev;
cd28ab6a 2061 struct sk_buff *skb;
cd28ab6a
SH		 2062 u32 status;
2063 u16 length;
2064
cb5d9547 2065 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2066
e71ebd73
SH		 2067 BUG_ON(le->link >= 2);
2068 dev = hw->dev[le->link];
13210ce5
SH		 2069
2070 sky2 = netdev_priv(dev);
f65b138c
SH		 2071 length = le16_to_cpu(le->length);
2072 status = le32_to_cpu(le->status);
cd28ab6a 2073
e71ebd73 2074 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2075 case OP_RXSTAT:
497d7c86 2076 skb = sky2_receive(dev, length, status);
d1f13708
SH		 2077 if (!skb)
2078 break;
13210ce5 2079
13210ce5
SH		 2080 skb->protocol = eth_type_trans(skb, dev);
2081 dev->last_rx = jiffies;
2082
d1f13708
SH		 2083#ifdef SKY2_VLAN_TAG_USED
2084 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2085 vlan_hwaccel_receive_skb(skb,
2086 sky2->vlgrp,
2087 be16_to_cpu(sky2->rx_tag));
2088 } else
2089#endif
cd28ab6a 2090 netif_receive_skb(skb);
13210ce5 2091
22e11703
SH		 2092 /* Update receiver after 16 frames */
2093 if (++buf_write[le->link] == RX_BUF_WRITE) {
2094 sky2_put_idx(hw, rxqaddr[le->link],
2095 sky2->rx_put);
2096 buf_write[le->link] = 0;
2097 }
2098
2099 /* Stop after net poll weight */
13210ce5
SH		 2100 if (++work_done >= to_do)
2101 goto exit_loop;
cd28ab6a
SH		 2102 break;
2103
d1f13708
SH		 2104#ifdef SKY2_VLAN_TAG_USED
2105 case OP_RXVLAN:
2106 sky2->rx_tag = length;
2107 break;
2108
2109 case OP_RXCHKSVLAN:
2110 sky2->rx_tag = length;
2111 /* fall through */
2112#endif
cd28ab6a 2113 case OP_RXCHKS:
d11c13e7 2114 skb = sky2->rx_ring[sky2->rx_next].skb;
84fa7933 2115 skb->ip_summed = CHECKSUM_COMPLETE;
f65b138c 2116 skb->csum = status & 0xffff;
cd28ab6a
SH		 2117 break;
2118
2119 case OP_TXINDEXLE:
13b97b74 2120 /* TX index reports status for both ports */
f55925d7
SH		 2121 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2122 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2123 if (hw->dev[1])
2124 sky2_tx_done(hw->dev[1],
2125 ((status >> 24) & 0xff)
2126 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2127 break;
2128
cd28ab6a
SH		 2129 default:
2130 if (net_ratelimit())
793b883e 2131 printk(KERN_WARNING PFX
e71ebd73
SH		 2132 "unknown status opcode 0x%x\n", le->opcode);
2133 goto exit_loop;
cd28ab6a 2134 }
13210ce5 2135 }
cd28ab6a 2136
fe2a24df
SH		 2137 /* Fully processed status ring so clear irq */
2138 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2139
13210ce5 2140exit_loop:
22e11703
SH		 2141 if (buf_write[0]) {
2142 sky2 = netdev_priv(hw->dev[0]);
2143 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2144 }
2145
2146 if (buf_write[1]) {
2147 sky2 = netdev_priv(hw->dev[1]);
2148 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2149 }
2150
e07b1aa8 2151 return work_done;
cd28ab6a
SH		 2152}
2153
2154static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2155{
2156 struct net_device *dev = hw->dev[port];
2157
3be92a70
SH		 2158 if (net_ratelimit())
2159 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2160 dev->name, status);
cd28ab6a
SH		 2161
2162 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2163 if (net_ratelimit())
2164 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2165 dev->name);
cd28ab6a
SH		 2166 /* Clear IRQ */
2167 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2168 }
2169
2170 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2171 if (net_ratelimit())
2172 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2173 dev->name);
cd28ab6a
SH		 2174
2175 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2176 }
2177
2178 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2179 if (net_ratelimit())
2180 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2181 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2182 }
2183
2184 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2185 if (net_ratelimit())
2186 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2187 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2188 }
2189
2190 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2191 if (net_ratelimit())
2192 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2193 dev->name);
cd28ab6a
SH		 2194 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2195 }
2196}
2197
2198static void sky2_hw_intr(struct sky2_hw *hw)
2199{
2200 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2201
793b883e 2202 if (status & Y2_IS_TIST_OV)
cd28ab6a 2203 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2204
2205 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2206 u16 pci_err;
2207
56a645cc 2208 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2209 if (net_ratelimit())
2210 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2211 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2212
2213 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2214 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2215 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2216 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2217 }
2218
2219 if (status & Y2_IS_PCI_EXP) {
d571b694 2220 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2221 u32 pex_err;
2222
7bd656d1 2223 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2224
3be92a70
SH		 2225 if (net_ratelimit())
2226 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2227 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2228
2229 /* clear the interrupt */
2230 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2231 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2232 0xffffffffUL);
cd28ab6a
SH		 2233 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2234
7bd656d1 2235 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2236 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2237 hwmsk &= ~Y2_IS_PCI_EXP;
2238 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2239 }
2240 }
2241
2242 if (status & Y2_HWE_L1_MASK)
2243 sky2_hw_error(hw, 0, status);
2244 status >>= 8;
2245 if (status & Y2_HWE_L1_MASK)
2246 sky2_hw_error(hw, 1, status);
2247}
2248
2249static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2250{
2251 struct net_device *dev = hw->dev[port];
2252 struct sky2_port *sky2 = netdev_priv(dev);
2253 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2254
2255 if (netif_msg_intr(sky2))
2256 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2257 dev->name, status);
2258
2259 if (status & GM_IS_RX_FF_OR) {
2260 ++sky2->net_stats.rx_fifo_errors;
2261 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2262 }
2263
2264 if (status & GM_IS_TX_FF_UR) {
2265 ++sky2->net_stats.tx_fifo_errors;
2266 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2267 }
cd28ab6a
SH		 2268}
2269
d257924e
SH		 2270/* This should never happen it is a fatal situation */
2271static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2272 const char *rxtx, u32 mask)
2273{
2274 struct net_device *dev = hw->dev[port];
2275 struct sky2_port *sky2 = netdev_priv(dev);
2276 u32 imask;
2277
2278 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2279 dev ? dev->name : "<not registered>", rxtx);
2280
2281 imask = sky2_read32(hw, B0_IMSK);
2282 imask &= ~mask;
2283 sky2_write32(hw, B0_IMSK, imask);
2284
2285 if (dev) {
2286 spin_lock(&sky2->phy_lock);
2287 sky2_link_down(sky2);
2288 spin_unlock(&sky2->phy_lock);
2289 }
2290}
cd28ab6a 2291
d27ed387
SH		 2292/* If idle then force a fake soft NAPI poll once a second
2293 * to work around cases where sharing an edge triggered interrupt.
2294 */
eb35cf60
SH		 2295static inline void sky2_idle_start(struct sky2_hw *hw)
2296{
2297 if (idle_timeout > 0)
2298 mod_timer(&hw->idle_timer,
2299 jiffies + msecs_to_jiffies(idle_timeout));
2300}
2301
d27ed387
SH		 2302static void sky2_idle(unsigned long arg)
2303{
01bd7564
SH		 2304 struct sky2_hw *hw = (struct sky2_hw *) arg;
2305 struct net_device *dev = hw->dev[0];
d27ed387 2306
d27ed387
SH		 2307 if (__netif_rx_schedule_prep(dev))
2308 __netif_rx_schedule(dev);
01bd7564
SH		 2309
2310 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2311}
2312
2313
e07b1aa8 2314static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2315{
e07b1aa8
SH		 2316 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2317 int work_limit = min(dev0->quota, *budget);
2318 int work_done = 0;
fb2690a9 2319 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2320
1e5f1283
SH		 2321 if (status & Y2_IS_HW_ERR)
2322 sky2_hw_intr(hw);
d257924e 2323
1e5f1283
SH		 2324 if (status & Y2_IS_IRQ_PHY1)
2325 sky2_phy_intr(hw, 0);
cd28ab6a 2326
1e5f1283
SH		 2327 if (status & Y2_IS_IRQ_PHY2)
2328 sky2_phy_intr(hw, 1);
cd28ab6a 2329
1e5f1283
SH		 2330 if (status & Y2_IS_IRQ_MAC1)
2331 sky2_mac_intr(hw, 0);
cd28ab6a 2332
1e5f1283
SH		 2333 if (status & Y2_IS_IRQ_MAC2)
2334 sky2_mac_intr(hw, 1);
cd28ab6a 2335
1e5f1283
SH		 2336 if (status & Y2_IS_CHK_RX1)
2337 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2338
1e5f1283
SH		 2339 if (status & Y2_IS_CHK_RX2)
2340 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2341
1e5f1283
SH		 2342 if (status & Y2_IS_CHK_TXA1)
2343 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2344
1e5f1283
SH		 2345 if (status & Y2_IS_CHK_TXA2)
2346 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2347
1e5f1283 2348 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2349 if (work_done < work_limit) {
2350 netif_rx_complete(dev0);
86fba634 2351
fe2a24df
SH		 2352 sky2_read32(hw, B0_Y2_SP_LISR);
2353 return 0;
2354 } else {
2355 *budget -= work_done;
2356 dev0->quota -= work_done;
1e5f1283 2357 return 1;
fe2a24df 2358 }
e07b1aa8
SH		 2359}
2360
7d12e780 2361static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2362{
2363 struct sky2_hw *hw = dev_id;
2364 struct net_device *dev0 = hw->dev[0];
2365 u32 status;
2366
2367 /* Reading this mask interrupts as side effect */
2368 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2369 if (status == 0 || status == ~0)
2370 return IRQ_NONE;
793b883e 2371
e07b1aa8
SH		 2372 prefetch(&hw->st_le[hw->st_idx]);
2373 if (likely(__netif_rx_schedule_prep(dev0)))
2374 __netif_rx_schedule(dev0);
793b883e 2375
cd28ab6a
SH		 2376 return IRQ_HANDLED;
2377}
2378
2379#ifdef CONFIG_NET_POLL_CONTROLLER
2380static void sky2_netpoll(struct net_device *dev)
2381{
2382 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2383 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2384
88d11360
SH		 2385 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2386 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2387}
2388#endif
2389
2390/* Chip internal frequency for clock calculations */
fb17358f 2391static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2392{
793b883e 2393 switch (hw->chip_id) {
cd28ab6a 2394 case CHIP_ID_YUKON_EC:
5a5b1ea0 2395 case CHIP_ID_YUKON_EC_U:
fb17358f 2396 return 125; /* 125 Mhz */
cd28ab6a 2397 case CHIP_ID_YUKON_FE:
fb17358f 2398 return 100; /* 100 Mhz */
793b883e 2399 default: /* YUKON_XL */
fb17358f 2400 return 156; /* 156 Mhz */
cd28ab6a
SH		 2401 }
2402}
2403
fb17358f 2404static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2405{
fb17358f 2406 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2407}
2408
fb17358f 2409static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2410{
fb17358f 2411 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2412}
2413
fb17358f 2414
59139528 2415static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2416{
cd28ab6a 2417 u16 status;
b89165f2 2418 u8 t8;
56a645cc 2419 int i;
cd28ab6a 2420
cd28ab6a 2421 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2422
cd28ab6a
SH		 2423 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2424 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2425 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2426 pci_name(hw->pdev), hw->chip_id);
2427 return -EOPNOTSUPP;
2428 }
2429
290d4de5
SH		 2430 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2431
2432 /* This rev is really old, and requires untested workarounds */
2433 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2434 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2435 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2436 hw->chip_id, hw->chip_rev);
2437 return -EOPNOTSUPP;
2438 }
2439
cd28ab6a
SH		 2440 /* disable ASF */
2441 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2442 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2443 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2444 }
2445
2446 /* do a SW reset */
2447 sky2_write8(hw, B0_CTST, CS_RST_SET);
2448 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2449
2450 /* clear PCI errors, if any */
56a645cc 2451 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2452
cd28ab6a 2453 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2454 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2455
cd28ab6a
SH		 2456
2457 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2458
2459 /* clear any PEX errors */
7bd656d1
SH		 2460 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2461 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2462
cd28ab6a 2463
b89165f2 2464 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
cd28ab6a
SH		 2465 hw->ports = 1;
2466 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2467 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2468 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2469 ++hw->ports;
2470 }
cd28ab6a 2471
5afa0a9c 2472 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2473
2474 for (i = 0; i < hw->ports; i++) {
2475 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2476 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2477 }
2478
2479 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2480
793b883e
SH		 2481 /* Clear I2C IRQ noise */
2482 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2483
2484 /* turn off hardware timer (unused) */
2485 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2486 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2487
cd28ab6a
SH		 2488 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2489
69634ee7
SH		 2490 /* Turn off descriptor polling */
2491 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2492
2493 /* Turn off receive timestamp */
2494 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2495 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2496
2497 /* enable the Tx Arbiters */
2498 for (i = 0; i < hw->ports; i++)
2499 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2500
2501 /* Initialize ram interface */
2502 for (i = 0; i < hw->ports; i++) {
793b883e 2503 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2504
2505 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2506 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2507 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2508 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2509 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2510 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2511 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2512 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2513 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2514 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2515 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2516 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2517 }
2518
7bd656d1 2519 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2520
cd28ab6a 2521 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2522 sky2_gmac_reset(hw, i);
cd28ab6a 2523
cd28ab6a
SH		 2524 memset(hw->st_le, 0, STATUS_LE_BYTES);
2525 hw->st_idx = 0;
2526
2527 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2528 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2529
2530 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2531 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2532
2533 /* Set the list last index */
793b883e 2534 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2535
290d4de5
SH		 2536 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2537 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2538
290d4de5
SH		 2539 /* set Status-FIFO ISR watermark */
2540 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2541 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2542 else
2543 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2544
290d4de5 2545 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2546 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2547 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2548
793b883e 2549 /* enable status unit */
cd28ab6a
SH		 2550 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2551
2552 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2553 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2554 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2555
2556 return 0;
2557}
2558
28bd181a 2559static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2560{
b89165f2
SH		 2561 if (sky2_is_copper(hw)) {
2562 u32 modes = SUPPORTED_10baseT_Half
2563 | SUPPORTED_10baseT_Full
2564 | SUPPORTED_100baseT_Half
2565 | SUPPORTED_100baseT_Full
2566 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2567
2568 if (hw->chip_id != CHIP_ID_YUKON_FE)
2569 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2570 | SUPPORTED_1000baseT_Full;
2571 return modes;
cd28ab6a 2572 } else
b89165f2
SH		 2573 return SUPPORTED_1000baseT_Half
2574 | SUPPORTED_1000baseT_Full
2575 | SUPPORTED_Autoneg
2576 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2577}
2578
793b883e 2579static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2580{
2581 struct sky2_port *sky2 = netdev_priv(dev);
2582 struct sky2_hw *hw = sky2->hw;
2583
2584 ecmd->transceiver = XCVR_INTERNAL;
2585 ecmd->supported = sky2_supported_modes(hw);
2586 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2587 if (sky2_is_copper(hw)) {
cd28ab6a 2588 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2589 | SUPPORTED_10baseT_Full
2590 | SUPPORTED_100baseT_Half
2591 | SUPPORTED_100baseT_Full
2592 | SUPPORTED_1000baseT_Half
2593 | SUPPORTED_1000baseT_Full
2594 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2595 ecmd->port = PORT_TP;
b89165f2
SH		 2596 ecmd->speed = sky2->speed;
2597 } else {
2598 ecmd->speed = SPEED_1000;
cd28ab6a 2599 ecmd->port = PORT_FIBRE;
b89165f2 2600 }
cd28ab6a
SH		 2601
2602 ecmd->advertising = sky2->advertising;
2603 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2604 ecmd->duplex = sky2->duplex;
2605 return 0;
2606}
2607
2608static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2609{
2610 struct sky2_port *sky2 = netdev_priv(dev);
2611 const struct sky2_hw *hw = sky2->hw;
2612 u32 supported = sky2_supported_modes(hw);
2613
2614 if (ecmd->autoneg == AUTONEG_ENABLE) {
2615 ecmd->advertising = supported;
2616 sky2->duplex = -1;
2617 sky2->speed = -1;
2618 } else {
2619 u32 setting;
2620
793b883e 2621 switch (ecmd->speed) {
cd28ab6a
SH		 2622 case SPEED_1000:
2623 if (ecmd->duplex == DUPLEX_FULL)
2624 setting = SUPPORTED_1000baseT_Full;
2625 else if (ecmd->duplex == DUPLEX_HALF)
2626 setting = SUPPORTED_1000baseT_Half;
2627 else
2628 return -EINVAL;
2629 break;
2630 case SPEED_100:
2631 if (ecmd->duplex == DUPLEX_FULL)
2632 setting = SUPPORTED_100baseT_Full;
2633 else if (ecmd->duplex == DUPLEX_HALF)
2634 setting = SUPPORTED_100baseT_Half;
2635 else
2636 return -EINVAL;
2637 break;
2638
2639 case SPEED_10:
2640 if (ecmd->duplex == DUPLEX_FULL)
2641 setting = SUPPORTED_10baseT_Full;
2642 else if (ecmd->duplex == DUPLEX_HALF)
2643 setting = SUPPORTED_10baseT_Half;
2644 else
2645 return -EINVAL;
2646 break;
2647 default:
2648 return -EINVAL;
2649 }
2650
2651 if ((setting & supported) == 0)
2652 return -EINVAL;
2653
2654 sky2->speed = ecmd->speed;
2655 sky2->duplex = ecmd->duplex;
2656 }
2657
2658 sky2->autoneg = ecmd->autoneg;
2659 sky2->advertising = ecmd->advertising;
2660
1b537565
SH		 2661 if (netif_running(dev))
2662 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2663
2664 return 0;
2665}
2666
2667static void sky2_get_drvinfo(struct net_device *dev,
2668 struct ethtool_drvinfo *info)
2669{
2670 struct sky2_port *sky2 = netdev_priv(dev);
2671
2672 strcpy(info->driver, DRV_NAME);
2673 strcpy(info->version, DRV_VERSION);
2674 strcpy(info->fw_version, "N/A");
2675 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2676}
2677
2678static const struct sky2_stat {
793b883e
SH		 2679 char name[ETH_GSTRING_LEN];
2680 u16 offset;
cd28ab6a
SH		 2681} sky2_stats[] = {
2682 { "tx_bytes", GM_TXO_OK_HI },
2683 { "rx_bytes", GM_RXO_OK_HI },
2684 { "tx_broadcast", GM_TXF_BC_OK },
2685 { "rx_broadcast", GM_RXF_BC_OK },
2686 { "tx_multicast", GM_TXF_MC_OK },
2687 { "rx_multicast", GM_RXF_MC_OK },
2688 { "tx_unicast", GM_TXF_UC_OK },
2689 { "rx_unicast", GM_RXF_UC_OK },
2690 { "tx_mac_pause", GM_TXF_MPAUSE },
2691 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2692 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2693 { "late_collision",GM_TXF_LAT_COL },
2694 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2695 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2696 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2697
d2604540 2698 { "rx_short", GM_RXF_SHT },
cd28ab6a 2699 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2700 { "rx_64_byte_packets", GM_RXF_64B },
2701 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2702 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2703 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2704 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2705 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2706 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2707 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2708 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2709 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2710 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2711
2712 { "tx_64_byte_packets", GM_TXF_64B },
2713 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2714 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2715 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2716 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2717 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2718 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2719 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2720};
2721
cd28ab6a
SH		 2722static u32 sky2_get_rx_csum(struct net_device *dev)
2723{
2724 struct sky2_port *sky2 = netdev_priv(dev);
2725
2726 return sky2->rx_csum;
2727}
2728
2729static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2730{
2731 struct sky2_port *sky2 = netdev_priv(dev);
2732
2733 sky2->rx_csum = data;
793b883e 2734
cd28ab6a
SH		 2735 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2736 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2737
2738 return 0;
2739}
2740
2741static u32 sky2_get_msglevel(struct net_device *netdev)
2742{
2743 struct sky2_port *sky2 = netdev_priv(netdev);
2744 return sky2->msg_enable;
2745}
2746
9a7ae0a9
SH		 2747static int sky2_nway_reset(struct net_device *dev)
2748{
2749 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2750
2751 if (sky2->autoneg != AUTONEG_ENABLE)
2752 return -EINVAL;
2753
1b537565 2754 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2755
2756 return 0;
2757}
2758
793b883e 2759static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2760{
2761 struct sky2_hw *hw = sky2->hw;
2762 unsigned port = sky2->port;
2763 int i;
2764
2765 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2766 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2767 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2768 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2769
793b883e 2770 for (i = 2; i < count; i++)
cd28ab6a
SH		 2771 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2772}
2773
cd28ab6a
SH		 2774static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2775{
2776 struct sky2_port *sky2 = netdev_priv(netdev);
2777 sky2->msg_enable = value;
2778}
2779
2780static int sky2_get_stats_count(struct net_device *dev)
2781{
2782 return ARRAY_SIZE(sky2_stats);
2783}
2784
2785static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2786 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2787{
2788 struct sky2_port *sky2 = netdev_priv(dev);
2789
793b883e 2790 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2791}
2792
793b883e 2793static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2794{
2795 int i;
2796
2797 switch (stringset) {
2798 case ETH_SS_STATS:
2799 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2800 memcpy(data + i * ETH_GSTRING_LEN,
2801 sky2_stats[i].name, ETH_GSTRING_LEN);
2802 break;
2803 }
2804}
2805
2806/* Use hardware MIB variables for critical path statistics and
2807 * transmit feedback not reported at interrupt.
2808 * Other errors are accounted for in interrupt handler.
2809 */
2810static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2811{
2812 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2813 u64 data[13];
cd28ab6a 2814
793b883e 2815 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2816
2817 sky2->net_stats.tx_bytes = data[0];
2818 sky2->net_stats.rx_bytes = data[1];
2819 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2820 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2821 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2822 sky2->net_stats.collisions = data[10];
2823 sky2->net_stats.tx_aborted_errors = data[12];
2824
2825 return &sky2->net_stats;
2826}
2827
2828static int sky2_set_mac_address(struct net_device *dev, void *p)
2829{
2830 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2831 struct sky2_hw *hw = sky2->hw;
2832 unsigned port = sky2->port;
2833 const struct sockaddr *addr = p;
cd28ab6a
SH		 2834
2835 if (!is_valid_ether_addr(addr->sa_data))
2836 return -EADDRNOTAVAIL;
2837
cd28ab6a 2838 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2839 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2840 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2841 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2842 dev->dev_addr, ETH_ALEN);
1b537565 2843
a8ab1ec0
SH		 2844 /* virtual address for data */
2845 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2846
2847 /* physical address: used for pause frames */
2848 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2849
2850 return 0;
cd28ab6a
SH		 2851}
2852
2853static void sky2_set_multicast(struct net_device *dev)
2854{
2855 struct sky2_port *sky2 = netdev_priv(dev);
2856 struct sky2_hw *hw = sky2->hw;
2857 unsigned port = sky2->port;
2858 struct dev_mc_list *list = dev->mc_list;
2859 u16 reg;
2860 u8 filter[8];
2861
2862 memset(filter, 0, sizeof(filter));
2863
2864 reg = gma_read16(hw, port, GM_RX_CTRL);
2865 reg |= GM_RXCR_UCF_ENA;
2866
d571b694 2867 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2868 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2869 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2870 memset(filter, 0xff, sizeof(filter));
793b883e 2871 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2872 reg &= ~GM_RXCR_MCF_ENA;
2873 else {
2874 int i;
2875 reg |= GM_RXCR_MCF_ENA;
2876
2877 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2878 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2879 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2880 }
2881 }
2882
cd28ab6a 2883 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2884 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2885 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2886 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2887 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2888 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2889 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2890 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2891
2892 gma_write16(hw, port, GM_RX_CTRL, reg);
2893}
2894
2895/* Can have one global because blinking is controlled by
2896 * ethtool and that is always under RTNL mutex
2897 */
91c86df5 2898static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2899{
793b883e
SH		 2900 u16 pg;
2901
793b883e
SH		 2902 switch (hw->chip_id) {
2903 case CHIP_ID_YUKON_XL:
2904 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2905 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2906 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2907 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2908 PHY_M_LEDC_INIT_CTRL(7) |
2909 PHY_M_LEDC_STA1_CTRL(7) |
2910 PHY_M_LEDC_STA0_CTRL(7))
2911 : 0);
2912
2913 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2914 break;
2915
2916 default:
2917 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2918 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2919 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2920 PHY_M_LED_MO_10(MO_LED_ON) |
2921 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2922 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2923 PHY_M_LED_MO_RX(MO_LED_ON)
2924 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2925 PHY_M_LED_MO_10(MO_LED_OFF) |
2926 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2927 PHY_M_LED_MO_1000(MO_LED_OFF) |
2928 PHY_M_LED_MO_RX(MO_LED_OFF));
2929
793b883e 2930 }
cd28ab6a
SH		 2931}
2932
2933/* blink LED's for finding board */
2934static int sky2_phys_id(struct net_device *dev, u32 data)
2935{
2936 struct sky2_port *sky2 = netdev_priv(dev);
2937 struct sky2_hw *hw = sky2->hw;
2938 unsigned port = sky2->port;
793b883e 2939 u16 ledctrl, ledover = 0;
cd28ab6a 2940 long ms;
91c86df5 2941 int interrupted;
cd28ab6a
SH		 2942 int onoff = 1;
2943
793b883e 2944 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2945 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2946 else
2947 ms = data * 1000;
2948
2949 /* save initial values */
e07b1aa8 2950 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2951 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2952 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2953 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2954 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2955 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2956 } else {
2957 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2958 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2959 }
cd28ab6a 2960
91c86df5
SH		 2961 interrupted = 0;
2962 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2963 sky2_led(hw, port, onoff);
2964 onoff = !onoff;
2965
e07b1aa8 2966 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2967 interrupted = msleep_interruptible(250);
e07b1aa8 2968 spin_lock_bh(&sky2->phy_lock);
91c86df5 2969
cd28ab6a
SH		 2970 ms -= 250;
2971 }
2972
2973 /* resume regularly scheduled programming */
793b883e
SH		 2974 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2975 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2976 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2977 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2978 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2979 } else {
2980 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2981 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2982 }
e07b1aa8 2983 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2984
2985 return 0;
2986}
2987
2988static void sky2_get_pauseparam(struct net_device *dev,
2989 struct ethtool_pauseparam *ecmd)
2990{
2991 struct sky2_port *sky2 = netdev_priv(dev);
2992
2993 ecmd->tx_pause = sky2->tx_pause;
2994 ecmd->rx_pause = sky2->rx_pause;
2995 ecmd->autoneg = sky2->autoneg;
2996}
2997
2998static int sky2_set_pauseparam(struct net_device *dev,
2999 struct ethtool_pauseparam *ecmd)
3000{
3001 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3002
3003 sky2->autoneg = ecmd->autoneg;
3004 sky2->tx_pause = ecmd->tx_pause != 0;
3005 sky2->rx_pause = ecmd->rx_pause != 0;
3006
1b537565 3007 sky2_phy_reinit(sky2);
cd28ab6a 3008
2eaba1a2 3009 return 0;
cd28ab6a
SH		 3010}
3011
fb17358f
SH		 3012static int sky2_get_coalesce(struct net_device *dev,
3013 struct ethtool_coalesce *ecmd)
3014{
3015 struct sky2_port *sky2 = netdev_priv(dev);
3016 struct sky2_hw *hw = sky2->hw;
3017
3018 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3019 ecmd->tx_coalesce_usecs = 0;
3020 else {
3021 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3022 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3023 }
3024 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3025
3026 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3027 ecmd->rx_coalesce_usecs = 0;
3028 else {
3029 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3030 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3031 }
3032 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3033
3034 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3035 ecmd->rx_coalesce_usecs_irq = 0;
3036 else {
3037 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3038 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3039 }
3040
3041 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3042
3043 return 0;
3044}
3045
3046/* Note: this affect both ports */
3047static int sky2_set_coalesce(struct net_device *dev,
3048 struct ethtool_coalesce *ecmd)
3049{
3050 struct sky2_port *sky2 = netdev_priv(dev);
3051 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3052 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3053
77b3d6a2
SH		 3054 if (ecmd->tx_coalesce_usecs > tmax ||
3055 ecmd->rx_coalesce_usecs > tmax ||
3056 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3057 return -EINVAL;
3058
ff81fbbe 3059 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3060 return -EINVAL;
ff81fbbe 3061 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3062 return -EINVAL;
ff81fbbe 3063 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3064 return -EINVAL;
3065
3066 if (ecmd->tx_coalesce_usecs == 0)
3067 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3068 else {
3069 sky2_write32(hw, STAT_TX_TIMER_INI,
3070 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3071 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3072 }
3073 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3074
3075 if (ecmd->rx_coalesce_usecs == 0)
3076 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3077 else {
3078 sky2_write32(hw, STAT_LEV_TIMER_INI,
3079 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3080 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3081 }
3082 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3083
3084 if (ecmd->rx_coalesce_usecs_irq == 0)
3085 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3086 else {
d28d4870 3087 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3088 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3089 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3090 }
3091 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3092 return 0;
3093}
3094
793b883e
SH		 3095static void sky2_get_ringparam(struct net_device *dev,
3096 struct ethtool_ringparam *ering)
3097{
3098 struct sky2_port *sky2 = netdev_priv(dev);
3099
3100 ering->rx_max_pending = RX_MAX_PENDING;
3101 ering->rx_mini_max_pending = 0;
3102 ering->rx_jumbo_max_pending = 0;
3103 ering->tx_max_pending = TX_RING_SIZE - 1;
3104
3105 ering->rx_pending = sky2->rx_pending;
3106 ering->rx_mini_pending = 0;
3107 ering->rx_jumbo_pending = 0;
3108 ering->tx_pending = sky2->tx_pending;
3109}
3110
3111static int sky2_set_ringparam(struct net_device *dev,
3112 struct ethtool_ringparam *ering)
3113{
3114 struct sky2_port *sky2 = netdev_priv(dev);
3115 int err = 0;
3116
3117 if (ering->rx_pending > RX_MAX_PENDING ||
3118 ering->rx_pending < 8 ||
3119 ering->tx_pending < MAX_SKB_TX_LE ||
3120 ering->tx_pending > TX_RING_SIZE - 1)
3121 return -EINVAL;
3122
3123 if (netif_running(dev))
3124 sky2_down(dev);
3125
3126 sky2->rx_pending = ering->rx_pending;
3127 sky2->tx_pending = ering->tx_pending;
3128
1b537565 3129 if (netif_running(dev)) {
793b883e 3130 err = sky2_up(dev);
1b537565
SH		 3131 if (err)
3132 dev_close(dev);
6ed995bb
SH		 3133 else
3134 sky2_set_multicast(dev);
1b537565 3135 }
793b883e
SH		 3136
3137 return err;
3138}
3139
793b883e
SH		 3140static int sky2_get_regs_len(struct net_device *dev)
3141{
6e4cbb34 3142 return 0x4000;
793b883e
SH		 3143}
3144
3145/*
3146 * Returns copy of control register region
6e4cbb34 3147 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3148 */
3149static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3150 void *p)
3151{
3152 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3153 const void __iomem *io = sky2->hw->regs;
793b883e 3154
6e4cbb34 3155 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3156 regs->version = 1;
6e4cbb34 3157 memset(p, 0, regs->len);
793b883e 3158
6e4cbb34
SH		 3159 memcpy_fromio(p, io, B3_RAM_ADDR);
3160
3161 memcpy_fromio(p + B3_RI_WTO_R1,
3162 io + B3_RI_WTO_R1,
3163 regs->len - B3_RI_WTO_R1);
793b883e 3164}
cd28ab6a 3165
7282d491 3166static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3167 .get_settings = sky2_get_settings,
3168 .set_settings = sky2_set_settings,
3169 .get_drvinfo = sky2_get_drvinfo,
3170 .get_msglevel = sky2_get_msglevel,
3171 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3172 .nway_reset = sky2_nway_reset,
793b883e
SH		 3173 .get_regs_len = sky2_get_regs_len,
3174 .get_regs = sky2_get_regs,
3175 .get_link = ethtool_op_get_link,
3176 .get_sg = ethtool_op_get_sg,
3177 .set_sg = ethtool_op_set_sg,
3178 .get_tx_csum = ethtool_op_get_tx_csum,
3179 .set_tx_csum = ethtool_op_set_tx_csum,
3180 .get_tso = ethtool_op_get_tso,
3181 .set_tso = ethtool_op_set_tso,
3182 .get_rx_csum = sky2_get_rx_csum,
3183 .set_rx_csum = sky2_set_rx_csum,
3184 .get_strings = sky2_get_strings,
fb17358f
SH		 3185 .get_coalesce = sky2_get_coalesce,
3186 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3187 .get_ringparam = sky2_get_ringparam,
3188 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3189 .get_pauseparam = sky2_get_pauseparam,
3190 .set_pauseparam = sky2_set_pauseparam,
793b883e 3191 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3192 .get_stats_count = sky2_get_stats_count,
3193 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3194 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3195};
3196
3197/* Initialize network device */
3198static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3199 unsigned port, int highmem)
3200{
3201 struct sky2_port *sky2;
3202 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3203
3204 if (!dev) {
3205 printk(KERN_ERR "sky2 etherdev alloc failed");
3206 return NULL;
3207 }
3208
3209 SET_MODULE_OWNER(dev);
3210 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3211 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3212 dev->open = sky2_up;
3213 dev->stop = sky2_down;
ef743d33 3214 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3215 dev->hard_start_xmit = sky2_xmit_frame;
3216 dev->get_stats = sky2_get_stats;
3217 dev->set_multicast_list = sky2_set_multicast;
3218 dev->set_mac_address = sky2_set_mac_address;
3219 dev->change_mtu = sky2_change_mtu;
3220 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3221 dev->tx_timeout = sky2_tx_timeout;
3222 dev->watchdog_timeo = TX_WATCHDOG;
3223 if (port == 0)
3224 dev->poll = sky2_poll;
3225 dev->weight = NAPI_WEIGHT;
3226#ifdef CONFIG_NET_POLL_CONTROLLER
3227 dev->poll_controller = sky2_netpoll;
3228#endif
cd28ab6a
SH		 3229
3230 sky2 = netdev_priv(dev);
3231 sky2->netdev = dev;
3232 sky2->hw = hw;
3233 sky2->msg_enable = netif_msg_init(debug, default_msg);
3234
cd28ab6a
SH		 3235 /* Auto speed and flow control */
3236 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3237 sky2->tx_pause = 1;
cd28ab6a
SH		 3238 sky2->rx_pause = 1;
3239 sky2->duplex = -1;
3240 sky2->speed = -1;
3241 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3242 sky2->rx_csum = 1;
75d070c5 3243
e07b1aa8 3244 spin_lock_init(&sky2->phy_lock);
793b883e 3245 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3246 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3247
3248 hw->dev[port] = dev;
3249
3250 sky2->port = port;
3251
5a5b1ea0
SH		 3252 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3253 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3254 if (highmem)
3255 dev->features |= NETIF_F_HIGHDMA;
793b883e 3256 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3257
d1f13708
SH		 3258#ifdef SKY2_VLAN_TAG_USED
3259 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3260 dev->vlan_rx_register = sky2_vlan_rx_register;
3261 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3262#endif
3263
cd28ab6a 3264 /* read the mac address */
793b883e 3265 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3266 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3267
3268 /* device is off until link detection */
3269 netif_carrier_off(dev);
3270 netif_stop_queue(dev);
3271
3272 return dev;
3273}
3274
28bd181a 3275static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3276{
3277 const struct sky2_port *sky2 = netdev_priv(dev);
3278
3279 if (netif_msg_probe(sky2))
3280 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3281 dev->name,
3282 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3283 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3284}
3285
fb2690a9 3286/* Handle software interrupt used during MSI test */
7d12e780 3287static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3288{
3289 struct sky2_hw *hw = dev_id;
3290 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3291
3292 if (status == 0)
3293 return IRQ_NONE;
3294
3295 if (status & Y2_IS_IRQ_SW) {
3296 hw->msi_detected = 1;
3297 wake_up(&hw->msi_wait);
3298 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3299 }
3300 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3301
3302 return IRQ_HANDLED;
3303}
3304
3305/* Test interrupt path by forcing a a software IRQ */
3306static int __devinit sky2_test_msi(struct sky2_hw *hw)
3307{
3308 struct pci_dev *pdev = hw->pdev;
3309 int err;
3310
bb507fe1
SH		 3311 init_waitqueue_head (&hw->msi_wait);
3312
fb2690a9
SH		 3313 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3314
1fb9df5d 3315 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
fb2690a9
SH		 3316 if (err) {
3317 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3318 pci_name(pdev), pdev->irq);
3319 return err;
3320 }
3321
fb2690a9 3322 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3323 sky2_read8(hw, B0_CTST);
fb2690a9
SH		 3324
3325 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3326
3327 if (!hw->msi_detected) {
3328 /* MSI test failed, go back to INTx mode */
3329 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3330 "switching to INTx mode. Please report this failure to "
3331 "the PCI maintainer and include system chipset information.\n",
3332 pci_name(pdev));
3333
3334 err = -EOPNOTSUPP;
3335 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3336 }
3337
3338 sky2_write32(hw, B0_IMSK, 0);
3339
3340 free_irq(pdev->irq, hw);
3341
3342 return err;
3343}
3344
cd28ab6a
SH		 3345static int __devinit sky2_probe(struct pci_dev *pdev,
3346 const struct pci_device_id *ent)
3347{
793b883e 3348 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3349 struct sky2_hw *hw;
5afa0a9c 3350 int err, pm_cap, using_dac = 0;
cd28ab6a 3351
793b883e
SH		 3352 err = pci_enable_device(pdev);
3353 if (err) {
cd28ab6a
SH		 3354 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3355 pci_name(pdev));
3356 goto err_out;
3357 }
3358
793b883e
SH		 3359 err = pci_request_regions(pdev, DRV_NAME);
3360 if (err) {
cd28ab6a
SH		 3361 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3362 pci_name(pdev));
793b883e 3363 goto err_out;
cd28ab6a
SH		 3364 }
3365
3366 pci_set_master(pdev);
3367
5afa0a9c
SH		 3368 /* Find power-management capability. */
3369 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3370 if (pm_cap == 0) {
3371 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3372 "aborting.\n");
3373 err = -EIO;
3374 goto err_out_free_regions;
3375 }
3376
d1f3d4dd
SH		 3377 if (sizeof(dma_addr_t) > sizeof(u32) &&
3378 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3379 using_dac = 1;
3380 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3381 if (err < 0) {
3382 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3383 "for consistent allocations\n", pci_name(pdev));
3384 goto err_out_free_regions;
3385 }
cd28ab6a 3386
d1f3d4dd 3387 } else {
cd28ab6a
SH		 3388 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3389 if (err) {
3390 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3391 pci_name(pdev));
3392 goto err_out_free_regions;
3393 }
3394 }
d1f3d4dd 3395
cd28ab6a 3396 err = -ENOMEM;
6aad85d6 3397 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3398 if (!hw) {
3399 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3400 pci_name(pdev));
3401 goto err_out_free_regions;
3402 }
3403
cd28ab6a 3404 hw->pdev = pdev;
cd28ab6a
SH		 3405
3406 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3407 if (!hw->regs) {
3408 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3409 pci_name(pdev));
3410 goto err_out_free_hw;
3411 }
5afa0a9c 3412 hw->pm_cap = pm_cap;
cd28ab6a 3413
56a645cc 3414#ifdef __BIG_ENDIAN
f65b138c
SH		 3415 /* The sk98lin vendor driver uses hardware byte swapping but
3416 * this driver uses software swapping.
3417 */
56a645cc
SH		 3418 {
3419 u32 reg;
56a645cc 3420 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3421 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3422 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3423 }
3424#endif
3425
08c06d8a
SH		 3426 /* ring for status responses */
3427 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3428 &hw->st_dma);
3429 if (!hw->st_le)
3430 goto err_out_iounmap;
3431
cd28ab6a
SH		 3432 err = sky2_reset(hw);
3433 if (err)
793b883e 3434 goto err_out_iounmap;
cd28ab6a 3435
7c7459d1
GKH		 3436 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3437 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3438 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3439 hw->chip_id, hw->chip_rev);
cd28ab6a 3440
793b883e
SH		 3441 dev = sky2_init_netdev(hw, 0, using_dac);
3442 if (!dev)
cd28ab6a
SH		 3443 goto err_out_free_pci;
3444
9fa1b1f3
SH		 3445 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3446 err = sky2_test_msi(hw);
3447 if (err == -EOPNOTSUPP)
3448 pci_disable_msi(pdev);
3449 else if (err)
3450 goto err_out_free_netdev;
3451 }
3452
793b883e
SH		 3453 err = register_netdev(dev);
3454 if (err) {
cd28ab6a
SH		 3455 printk(KERN_ERR PFX "%s: cannot register net device\n",
3456 pci_name(pdev));
3457 goto err_out_free_netdev;
3458 }
3459
9fa1b1f3
SH		 3460 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, dev->name, hw);
3461 if (err) {
3462 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3463 pci_name(pdev), pdev->irq);
3464 goto err_out_unregister;
3465 }
3466 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3467
cd28ab6a
SH		 3468 sky2_show_addr(dev);
3469
3470 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3471 if (register_netdev(dev1) == 0)
3472 sky2_show_addr(dev1);
3473 else {
3474 /* Failure to register second port need not be fatal */
793b883e
SH		 3475 printk(KERN_WARNING PFX
3476 "register of second port failed\n");
cd28ab6a
SH		 3477 hw->dev[1] = NULL;
3478 free_netdev(dev1);
3479 }
3480 }
3481
01bd7564 3482 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3483 sky2_idle_start(hw);
d27ed387 3484
793b883e
SH		 3485 pci_set_drvdata(pdev, hw);
3486
cd28ab6a
SH		 3487 return 0;
3488
793b883e 3489err_out_unregister:
fb2690a9 3490 pci_disable_msi(pdev);
793b883e 3491 unregister_netdev(dev);
cd28ab6a
SH		 3492err_out_free_netdev:
3493 free_netdev(dev);
cd28ab6a 3494err_out_free_pci:
793b883e 3495 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3496 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3497err_out_iounmap:
3498 iounmap(hw->regs);
3499err_out_free_hw:
3500 kfree(hw);
3501err_out_free_regions:
3502 pci_release_regions(pdev);
cd28ab6a 3503 pci_disable_device(pdev);
cd28ab6a
SH		 3504err_out:
3505 return err;
3506}
3507
3508static void __devexit sky2_remove(struct pci_dev *pdev)
3509{
793b883e 3510 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3511 struct net_device *dev0, *dev1;
3512
793b883e 3513 if (!hw)
cd28ab6a
SH		 3514 return;
3515
d27ed387
SH		 3516 del_timer_sync(&hw->idle_timer);
3517
3518 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3519 synchronize_irq(hw->pdev->irq);
3520
cd28ab6a 3521 dev0 = hw->dev[0];
793b883e
SH		 3522 dev1 = hw->dev[1];
3523 if (dev1)
3524 unregister_netdev(dev1);
cd28ab6a
SH		 3525 unregister_netdev(dev0);
3526
5afa0a9c 3527 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3528 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3529 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3530 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3531
3532 free_irq(pdev->irq, hw);
fb2690a9 3533 pci_disable_msi(pdev);
793b883e 3534 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3535 pci_release_regions(pdev);
3536 pci_disable_device(pdev);
793b883e 3537
cd28ab6a
SH		 3538 if (dev1)
3539 free_netdev(dev1);
3540 free_netdev(dev0);
3541 iounmap(hw->regs);
3542 kfree(hw);
5afa0a9c 3543
cd28ab6a
SH		 3544 pci_set_drvdata(pdev, NULL);
3545}
3546
3547#ifdef CONFIG_PM
3548static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3549{
793b883e 3550 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3551 int i;
2ccc99b7
SH		 3552 pci_power_t pstate = pci_choose_state(pdev, state);
3553
3554 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3555 return -EINVAL;
cd28ab6a 3556
eb35cf60 3557 del_timer_sync(&hw->idle_timer);
6a5706b9 3558 netif_poll_disable(hw->dev[0]);
eb35cf60 3559
f05267e7 3560 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3561 struct net_device *dev = hw->dev[i];
3562
6a5706b9 3563 if (netif_running(dev)) {
5afa0a9c 3564 sky2_down(dev);
cd28ab6a 3565 netif_device_detach(dev);
cd28ab6a
SH		 3566 }
3567 }
3568
8ab8fca2 3569 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3570 pci_save_state(pdev);
2ccc99b7
SH		 3571 sky2_set_power_state(hw, pstate);
3572 return 0;
cd28ab6a
SH		 3573}
3574
3575static int sky2_resume(struct pci_dev *pdev)
3576{
793b883e 3577 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3578 int i, err;
cd28ab6a 3579
cd28ab6a
SH		 3580 pci_restore_state(pdev);
3581 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3582 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3583
08c06d8a
SH		 3584 err = sky2_reset(hw);
3585 if (err)
3586 goto out;
cd28ab6a 3587
8ab8fca2
SH		 3588 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3589
f05267e7 3590 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3591 struct net_device *dev = hw->dev[i];
6a5706b9 3592 if (netif_running(dev)) {
08c06d8a 3593 netif_device_attach(dev);
88d11360 3594
08c06d8a
SH		 3595 err = sky2_up(dev);
3596 if (err) {
3597 printk(KERN_ERR PFX "%s: could not up: %d\n",
3598 dev->name, err);
3599 dev_close(dev);
eb35cf60 3600 goto out;
5afa0a9c 3601 }
cd28ab6a
SH		 3602 }
3603 }
eb35cf60 3604
6a5706b9 3605 netif_poll_enable(hw->dev[0]);
eb35cf60 3606 sky2_idle_start(hw);
08c06d8a
SH		 3607out:
3608 return err;
cd28ab6a
SH		 3609}
3610#endif
3611
3612static struct pci_driver sky2_driver = {
793b883e
SH		 3613 .name = DRV_NAME,
3614 .id_table = sky2_id_table,
3615 .probe = sky2_probe,
3616 .remove = __devexit_p(sky2_remove),
cd28ab6a 3617#ifdef CONFIG_PM
793b883e
SH		 3618 .suspend = sky2_suspend,
3619 .resume = sky2_resume,
cd28ab6a
SH		 3620#endif
3621};
3622
3623static int __init sky2_init_module(void)
3624{
50241c4c 3625 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3626}
3627
3628static void __exit sky2_cleanup_module(void)
3629{
3630 pci_unregister_driver(&sky2_driver);
3631}
3632
3633module_init(sky2_init_module);
3634module_exit(sky2_cleanup_module);
3635
3636MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3637MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3638MODULE_LICENSE("GPL");
5f4f9dc1 3639MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree