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mlx4: don't use deprecated IRQ flags
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
93cd791e 53#define DRV_VERSION "1.14"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 66#define RX_SKB_ALIGN 8
22e11703 67#define RX_BUF_WRITE 16
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
cb5d9547
SH		 80#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
cd28ab6a 82static const u32 default_msg =
793b883e
SH		 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 86
793b883e 87static int debug = -1; /* defaults above */
cd28ab6a
SH		 88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
14d0263f 91static int copybreak __read_mostly = 128;
bdb5c58e
SH		 92module_param(copybreak, int, 0);
93MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
fb2690a9
SH		 95static int disable_msi = 0;
96module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
e561a83b 99static int idle_timeout = 0;
01bd7564 100module_param(idle_timeout, int, 0);
e561a83b 101MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 102
cd28ab6a 103static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 134 { 0 }
135};
793b883e 136
cd28ab6a
SH		 137MODULE_DEVICE_TABLE(pci, sky2_id_table);
138
139/* Avoid conditionals by using array */
140static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
141static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 142static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 143
92f965e8
SH		 144/* This driver supports yukon2 chipset only */
145static const char *yukon2_name[] = {
146 "XL", /* 0xb3 */
147 "EC Ultra", /* 0xb4 */
93745494 148 "Extreme", /* 0xb5 */
92f965e8
SH		 149 "EC", /* 0xb6 */
150 "FE", /* 0xb7 */
793b883e
SH		 151};
152
793b883e 153/* Access to external PHY */
ef743d33 154static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 155{
156 int i;
157
158 gma_write16(hw, port, GM_SMI_DATA, val);
159 gma_write16(hw, port, GM_SMI_CTRL,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161
162 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 163 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 164 return 0;
793b883e 165 udelay(1);
cd28ab6a 166 }
ef743d33 167
793b883e 168 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 169 return -ETIMEDOUT;
cd28ab6a
SH		 170}
171
ef743d33 172static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 173{
174 int i;
175
793b883e 176 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 177 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
178
179 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 180 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
181 *val = gma_read16(hw, port, GM_SMI_DATA);
182 return 0;
183 }
184
793b883e 185 udelay(1);
cd28ab6a
SH		 186 }
187
ef743d33
SH		 188 return -ETIMEDOUT;
189}
190
191static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
192{
193 u16 v;
194
195 if (__gm_phy_read(hw, port, reg, &v) != 0)
196 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
197 return v;
cd28ab6a
SH		 198}
199
5afa0a9c 200
ae306cca
SH		 201static void sky2_power_on(struct sky2_hw *hw)
202{
203 /* switch power to VCC (WA for VAUX problem) */
204 sky2_write8(hw, B0_POWER_CTRL,
205 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 206
ae306cca
SH		 207 /* disable Core Clock Division, */
208 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 209
ae306cca
SH		 210 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
211 /* enable bits are inverted */
212 sky2_write8(hw, B2_Y2_CLK_GATE,
213 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
214 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
215 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
216 else
217 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 218
93745494 219 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
ae306cca 220 u32 reg1;
5afa0a9c 221
ae306cca
SH		 222 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
223 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
224 reg1 &= P_ASPM_CONTROL_MSK;
225 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
226 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
5afa0a9c 227 }
ae306cca 228}
5afa0a9c 229
ae306cca
SH		 230static void sky2_power_aux(struct sky2_hw *hw)
231{
232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
233 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
234 else
235 /* enable bits are inverted */
236 sky2_write8(hw, B2_Y2_CLK_GATE,
237 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
238 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
239 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
240
241 /* switch power to VAUX */
242 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
243 sky2_write8(hw, B0_POWER_CTRL,
244 (PC_VAUX_ENA | PC_VCC_ENA |
245 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 246}
247
d3bcfbeb 248static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 249{
250 u16 reg;
251
252 /* disable all GMAC IRQ's */
253 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
254 /* disable PHY IRQs */
255 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 256
cd28ab6a
SH		 257 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
258 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
259 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
260 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
261
262 reg = gma_read16(hw, port, GM_RX_CTRL);
263 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
264 gma_write16(hw, port, GM_RX_CTRL, reg);
265}
266
16ad91e1
SH		 267/* flow control to advertise bits */
268static const u16 copper_fc_adv[] = {
269 [FC_NONE] = 0,
270 [FC_TX] = PHY_M_AN_ASP,
271 [FC_RX] = PHY_M_AN_PC,
272 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
273};
274
275/* flow control to advertise bits when using 1000BaseX */
276static const u16 fiber_fc_adv[] = {
277 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
278 [FC_TX] = PHY_M_P_ASYM_MD_X,
279 [FC_RX] = PHY_M_P_SYM_MD_X,
280 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
281};
282
283/* flow control to GMA disable bits */
284static const u16 gm_fc_disable[] = {
285 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
286 [FC_TX] = GM_GPCR_FC_RX_DIS,
287 [FC_RX] = GM_GPCR_FC_TX_DIS,
288 [FC_BOTH] = 0,
289};
290
291
cd28ab6a
SH		 292static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
293{
294 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 295 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 296
93745494
SH		 297 if (sky2->autoneg == AUTONEG_ENABLE
298 && !(hw->chip_id == CHIP_ID_YUKON_XL
299 || hw->chip_id == CHIP_ID_YUKON_EC_U
300 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 301 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
302
303 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 304 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 305 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
306
307 if (hw->chip_id == CHIP_ID_YUKON_EC)
308 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
309 else
310 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
311
312 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
313 }
314
315 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 316 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 317 if (hw->chip_id == CHIP_ID_YUKON_FE) {
318 /* enable automatic crossover */
319 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
320 } else {
321 /* disable energy detect */
322 ctrl &= ~PHY_M_PC_EN_DET_MSK;
323
324 /* enable automatic crossover */
325 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
326
93745494
SH		 327 if (sky2->autoneg == AUTONEG_ENABLE
328 && (hw->chip_id == CHIP_ID_YUKON_XL
329 || hw->chip_id == CHIP_ID_YUKON_EC_U
330 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 331 ctrl &= ~PHY_M_PC_DSC_MSK;
332 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
333 }
334 }
cd28ab6a
SH		 335 } else {
336 /* workaround for deviation #4.88 (CRC errors) */
337 /* disable Automatic Crossover */
338
339 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 340 }
cd28ab6a 341
b89165f2
SH		 342 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
343
344 /* special setup for PHY 88E1112 Fiber */
345 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
346 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 347
b89165f2
SH		 348 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
349 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
350 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
351 ctrl &= ~PHY_M_MAC_MD_MSK;
352 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
353 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
354
355 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 356 /* select page 1 to access Fiber registers */
357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 358
359 /* for SFP-module set SIGDET polarity to low */
360 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
361 ctrl |= PHY_M_FIB_SIGD_POL;
362 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 363 }
b89165f2
SH		 364
365 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 366 }
367
7800fddc 368 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 369 ct1000 = 0;
370 adv = PHY_AN_CSMA;
2eaba1a2 371 reg = 0;
cd28ab6a
SH		 372
373 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 374 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 375 if (sky2->advertising & ADVERTISED_1000baseT_Full)
376 ct1000 |= PHY_M_1000C_AFD;
377 if (sky2->advertising & ADVERTISED_1000baseT_Half)
378 ct1000 |= PHY_M_1000C_AHD;
379 if (sky2->advertising & ADVERTISED_100baseT_Full)
380 adv |= PHY_M_AN_100_FD;
381 if (sky2->advertising & ADVERTISED_100baseT_Half)
382 adv |= PHY_M_AN_100_HD;
383 if (sky2->advertising & ADVERTISED_10baseT_Full)
384 adv |= PHY_M_AN_10_FD;
385 if (sky2->advertising & ADVERTISED_10baseT_Half)
386 adv |= PHY_M_AN_10_HD;
709c6e7b 387
16ad91e1 388 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 389 } else { /* special defines for FIBER (88E1040S only) */
390 if (sky2->advertising & ADVERTISED_1000baseT_Full)
391 adv |= PHY_M_AN_1000X_AFD;
392 if (sky2->advertising & ADVERTISED_1000baseT_Half)
393 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 394
16ad91e1 395 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 396 }
cd28ab6a
SH		 397
398 /* Restart Auto-negotiation */
399 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
400 } else {
401 /* forced speed/duplex settings */
402 ct1000 = PHY_M_1000C_MSE;
403
2eaba1a2
SH		 404 /* Disable auto update for duplex flow control and speed */
405 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 406
407 switch (sky2->speed) {
408 case SPEED_1000:
409 ctrl |= PHY_CT_SP1000;
2eaba1a2 410 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 411 break;
412 case SPEED_100:
413 ctrl |= PHY_CT_SP100;
2eaba1a2 414 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 415 break;
416 }
417
2eaba1a2
SH		 418 if (sky2->duplex == DUPLEX_FULL) {
419 reg |= GM_GPCR_DUP_FULL;
420 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 421 } else if (sky2->speed < SPEED_1000)
422 sky2->flow_mode = FC_NONE;
2eaba1a2 423
2eaba1a2 424
16ad91e1 425 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 426
427 /* Forward pause packets to GMAC? */
16ad91e1 428 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 429 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
430 else
431 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 432 }
433
2eaba1a2
SH		 434 gma_write16(hw, port, GM_GP_CTRL, reg);
435
cd28ab6a
SH		 436 if (hw->chip_id != CHIP_ID_YUKON_FE)
437 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
438
439 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
440 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
441
442 /* Setup Phy LED's */
443 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
444 ledover = 0;
445
446 switch (hw->chip_id) {
447 case CHIP_ID_YUKON_FE:
448 /* on 88E3082 these bits are at 11..9 (shifted left) */
449 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
450
451 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
452
453 /* delete ACT LED control bits */
454 ctrl &= ~PHY_M_FELP_LED1_MSK;
455 /* change ACT LED control to blink mode */
456 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
457 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
458 break;
459
460 case CHIP_ID_YUKON_XL:
793b883e 461 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 462
463 /* select page 3 to access LED control register */
464 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
465
466 /* set LED Function Control register */
ed6d32c7
SH		 467 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
468 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
469 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
470 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
471 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 472
473 /* set Polarity Control register */
474 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 475 (PHY_M_POLC_LS1_P_MIX(4) |
476 PHY_M_POLC_IS0_P_MIX(4) |
477 PHY_M_POLC_LOS_CTRL(2) |
478 PHY_M_POLC_INIT_CTRL(2) |
479 PHY_M_POLC_STA1_CTRL(2) |
480 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 481
482 /* restore page register */
793b883e 483 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 484 break;
93745494 485
ed6d32c7 486 case CHIP_ID_YUKON_EC_U:
93745494 487 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 488 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
489
490 /* select page 3 to access LED control register */
491 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
492
493 /* set LED Function Control register */
494 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
495 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
496 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
497 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
498 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
499
500 /* set Blink Rate in LED Timer Control Register */
501 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
502 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
503 /* restore page register */
504 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
505 break;
cd28ab6a
SH		 506
507 default:
508 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
509 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
510 /* turn off the Rx LED (LED_RX) */
0efdf262 511 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 512 }
513
9467a8fc
SH		 514 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
515 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 516 /* apply fixes in PHY AFE */
ed6d32c7
SH		 517 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
518
977bdf06 519 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 520 gm_phy_write(hw, port, 0x18, 0xaa99);
521 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 522
977bdf06 523 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 524 gm_phy_write(hw, port, 0x18, 0xa204);
525 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 526
527 /* set page register to 0 */
9467a8fc 528 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
93745494 529 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 530 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 531
977bdf06
SH		 532 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
533 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 534 ledover |= PHY_M_LED_MO_100;
977bdf06 535 }
cd28ab6a 536
977bdf06
SH		 537 if (ledover)
538 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
539
540 }
2eaba1a2 541
d571b694 542 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 543 if (sky2->autoneg == AUTONEG_ENABLE)
544 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
545 else
546 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
547}
548
d3bcfbeb
SH		 549static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
550{
551 u32 reg1;
552 static const u32 phy_power[]
553 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
554
555 /* looks like this XL is back asswards .. */
556 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
557 onoff = !onoff;
558
aed2cec4 559 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 560 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 561 if (onoff)
562 /* Turn off phy power saving */
563 reg1 &= ~phy_power[port];
564 else
565 reg1 |= phy_power[port];
566
567 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 568 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 569 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 570 udelay(100);
571}
572
1b537565
SH		 573/* Force a renegotiation */
574static void sky2_phy_reinit(struct sky2_port *sky2)
575{
e07b1aa8 576 spin_lock_bh(&sky2->phy_lock);
1b537565 577 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 578 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 579}
580
e3173832
SH		 581/* Put device in state to listen for Wake On Lan */
582static void sky2_wol_init(struct sky2_port *sky2)
583{
584 struct sky2_hw *hw = sky2->hw;
585 unsigned port = sky2->port;
586 enum flow_control save_mode;
587 u16 ctrl;
588 u32 reg1;
589
590 /* Bring hardware out of reset */
591 sky2_write16(hw, B0_CTST, CS_RST_CLR);
592 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
593
594 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
595 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
596
597 /* Force to 10/100
598 * sky2_reset will re-enable on resume
599 */
600 save_mode = sky2->flow_mode;
601 ctrl = sky2->advertising;
602
603 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
604 sky2->flow_mode = FC_NONE;
605 sky2_phy_power(hw, port, 1);
606 sky2_phy_reinit(sky2);
607
608 sky2->flow_mode = save_mode;
609 sky2->advertising = ctrl;
610
611 /* Set GMAC to no flow control and auto update for speed/duplex */
612 gma_write16(hw, port, GM_GP_CTRL,
613 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
614 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
615
616 /* Set WOL address */
617 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
618 sky2->netdev->dev_addr, ETH_ALEN);
619
620 /* Turn on appropriate WOL control bits */
621 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
622 ctrl = 0;
623 if (sky2->wol & WAKE_PHY)
624 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
625 else
626 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
627
628 if (sky2->wol & WAKE_MAGIC)
629 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
630 else
631 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
632
633 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
634 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
635
636 /* Turn on legacy PCI-Express PME mode */
637 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
638 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
639 reg1 |= PCI_Y2_PME_LEGACY;
640 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
641 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
642
643 /* block receiver */
644 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
645
646}
647
cd28ab6a
SH		 648static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
649{
650 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
651 u16 reg;
652 int i;
653 const u8 *addr = hw->dev[port]->dev_addr;
654
42eeea01
SH		 655 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
656 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 657
658 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
659
793b883e 660 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 661 /* WA DEV_472 -- looks like crossed wires on port 2 */
662 /* clear GMAC 1 Control reset */
663 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
664 do {
665 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
666 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
667 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
668 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
669 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
670 }
671
793b883e 672 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 673
2eaba1a2
SH		 674 /* Enable Transmit FIFO Underrun */
675 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
676
e07b1aa8 677 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 678 sky2_phy_init(hw, port);
e07b1aa8 679 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 680
681 /* MIB clear */
682 reg = gma_read16(hw, port, GM_PHY_ADDR);
683 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
684
43f2f104
SH		 685 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
686 gma_read16(hw, port, i);
cd28ab6a
SH		 687 gma_write16(hw, port, GM_PHY_ADDR, reg);
688
689 /* transmit control */
690 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
691
692 /* receive control reg: unicast + multicast + no FCS */
693 gma_write16(hw, port, GM_RX_CTRL,
793b883e 694 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 695
696 /* transmit flow control */
697 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
698
699 /* transmit parameter */
700 gma_write16(hw, port, GM_TX_PARAM,
701 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
702 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
703 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
704 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
705
706 /* serial mode register */
707 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 708 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 709
6b1a3aef 710 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 711 reg |= GM_SMOD_JUMBO_ENA;
712
713 gma_write16(hw, port, GM_SERIAL_MODE, reg);
714
cd28ab6a
SH		 715 /* virtual address for data */
716 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
717
793b883e
SH		 718 /* physical address: used for pause frames */
719 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
720
721 /* ignore counter overflows */
cd28ab6a
SH		 722 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
723 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
724 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
725
726 /* Configure Rx MAC FIFO */
727 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 728 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
729 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 730
d571b694 731 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 732 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 733
8df9a876
SH		 734 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
735 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 736
737 /* Configure Tx MAC FIFO */
738 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
739 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 740
93745494 741 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 742 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 743 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98
SH		 744
745 /* set Tx GMAC FIFO Almost Empty Threshold */
746 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
747 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
748
749 if (hw->dev[port]->mtu > ETH_DATA_LEN)
750 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
751 TX_JUMBO_ENA | TX_STFW_DIS);
752 else
753 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
754 TX_JUMBO_DIS | TX_STFW_ENA);
5a5b1ea0
SH		 755 }
756
cd28ab6a
SH		 757}
758
67712901
SH		 759/* Assign Ram Buffer allocation to queue */
760static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 761{
67712901
SH		 762 u32 end;
763
764 /* convert from K bytes to qwords used for hw register */
765 start *= 1024/8;
766 space *= 1024/8;
767 end = start + space - 1;
793b883e 768
cd28ab6a
SH		 769 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
770 sky2_write32(hw, RB_ADDR(q, RB_START), start);
771 sky2_write32(hw, RB_ADDR(q, RB_END), end);
772 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
773 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
774
775 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 776 u32 tp = space - space/4;
793b883e 777
1c28f6ba
SH		 778 /* On receive queue's set the thresholds
779 * give receiver priority when > 3/4 full
780 * send pause when down to 2K
781 */
782 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
783 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 784
1c28f6ba
SH		 785 tp = space - 2048/8;
786 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
787 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 788 } else {
789 /* Enable store & forward on Tx queue's because
790 * Tx FIFO is only 1K on Yukon
791 */
792 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
793 }
794
795 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 796 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 797}
798
cd28ab6a 799/* Setup Bus Memory Interface */
af4ed7e6 800static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 801{
802 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
803 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
804 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 805 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 806}
807
cd28ab6a
SH		 808/* Setup prefetch unit registers. This is the interface between
809 * hardware and driver list elements
810 */
8cc048e3 811static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 812 u64 addr, u32 last)
813{
cd28ab6a
SH		 814 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
815 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
816 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
817 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
818 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
819 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 820
821 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 822}
823
793b883e
SH		 824static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
825{
826 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
827
cb5d9547 828 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 829 le->ctrl = 0;
793b883e
SH		 830 return le;
831}
cd28ab6a 832
291ea614
SH		 833static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
834 struct sky2_tx_le *le)
835{
836 return sky2->tx_ring + (le - sky2->tx_le);
837}
838
290d4de5
SH		 839/* Update chip's next pointer */
840static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 841{
98232f85 842 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 843 wmb();
98232f85
SH		 844 sky2_write16(hw, q, idx);
845 sky2_read16(hw, q);
cd28ab6a
SH		 846}
847
793b883e 848
cd28ab6a
SH		 849static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
850{
851 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 852 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 853 le->ctrl = 0;
cd28ab6a
SH		 854 return le;
855}
856
a018e330
SH		 857/* Return high part of DMA address (could be 32 or 64 bit) */
858static inline u32 high32(dma_addr_t a)
859{
a036119f 860 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 861}
862
14d0263f
SH		 863/* Build description to hardware for one receive segment */
864static void sky2_rx_add(struct sky2_port *sky2, u8 op,
865 dma_addr_t map, unsigned len)
cd28ab6a
SH		 866{
867 struct sky2_rx_le *le;
734d1868 868 u32 hi = high32(map);
cd28ab6a 869
793b883e 870 if (sky2->rx_addr64 != hi) {
cd28ab6a 871 le = sky2_next_rx(sky2);
793b883e 872 le->addr = cpu_to_le32(hi);
cd28ab6a 873 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 874 sky2->rx_addr64 = high32(map + len);
cd28ab6a 875 }
793b883e 876
cd28ab6a 877 le = sky2_next_rx(sky2);
734d1868
SH		 878 le->addr = cpu_to_le32((u32) map);
879 le->length = cpu_to_le16(len);
14d0263f 880 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 881}
882
14d0263f
SH		 883/* Build description to hardware for one possibly fragmented skb */
884static void sky2_rx_submit(struct sky2_port *sky2,
885 const struct rx_ring_info *re)
886{
887 int i;
888
889 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
890
891 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
892 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
893}
894
895
896static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
897 unsigned size)
898{
899 struct sk_buff *skb = re->skb;
900 int i;
901
902 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
903 pci_unmap_len_set(re, data_size, size);
904
905 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
906 re->frag_addr[i] = pci_map_page(pdev,
907 skb_shinfo(skb)->frags[i].page,
908 skb_shinfo(skb)->frags[i].page_offset,
909 skb_shinfo(skb)->frags[i].size,
910 PCI_DMA_FROMDEVICE);
911}
912
913static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
914{
915 struct sk_buff *skb = re->skb;
916 int i;
917
918 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
919 PCI_DMA_FROMDEVICE);
920
921 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
922 pci_unmap_page(pdev, re->frag_addr[i],
923 skb_shinfo(skb)->frags[i].size,
924 PCI_DMA_FROMDEVICE);
925}
793b883e 926
cd28ab6a
SH		 927/* Tell chip where to start receive checksum.
928 * Actually has two checksums, but set both same to avoid possible byte
929 * order problems.
930 */
793b883e 931static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 932{
933 struct sky2_rx_le *le;
934
cd28ab6a 935 le = sky2_next_rx(sky2);
f65b138c 936 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 937 le->ctrl = 0;
938 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 939
793b883e
SH		 940 sky2_write32(sky2->hw,
941 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
942 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 943
944}
945
6b1a3aef
SH		 946/*
947 * The RX Stop command will not work for Yukon-2 if the BMU does not
948 * reach the end of packet and since we can't make sure that we have
949 * incoming data, we must reset the BMU while it is not doing a DMA
950 * transfer. Since it is possible that the RX path is still active,
951 * the RX RAM buffer will be stopped first, so any possible incoming
952 * data will not trigger a DMA. After the RAM buffer is stopped, the
953 * BMU is polled until any DMA in progress is ended and only then it
954 * will be reset.
955 */
956static void sky2_rx_stop(struct sky2_port *sky2)
957{
958 struct sky2_hw *hw = sky2->hw;
959 unsigned rxq = rxqaddr[sky2->port];
960 int i;
961
962 /* disable the RAM Buffer receive queue */
963 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
964
965 for (i = 0; i < 0xffff; i++)
966 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
967 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
968 goto stopped;
969
970 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
971 sky2->netdev->name);
972stopped:
973 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
974
975 /* reset the Rx prefetch unit */
976 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
977}
793b883e 978
d571b694 979/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 980static void sky2_rx_clean(struct sky2_port *sky2)
981{
982 unsigned i;
983
984 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 985 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 986 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 987
988 if (re->skb) {
14d0263f 989 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 990 kfree_skb(re->skb);
991 re->skb = NULL;
992 }
993 }
994}
995
ef743d33
SH		 996/* Basic MII support */
997static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
998{
999 struct mii_ioctl_data *data = if_mii(ifr);
1000 struct sky2_port *sky2 = netdev_priv(dev);
1001 struct sky2_hw *hw = sky2->hw;
1002 int err = -EOPNOTSUPP;
1003
1004 if (!netif_running(dev))
1005 return -ENODEV; /* Phy still in reset */
1006
d89e1343 1007 switch (cmd) {
ef743d33
SH		 1008 case SIOCGMIIPHY:
1009 data->phy_id = PHY_ADDR_MARV;
1010
1011 /* fallthru */
1012 case SIOCGMIIREG: {
1013 u16 val = 0;
91c86df5 1014
e07b1aa8 1015 spin_lock_bh(&sky2->phy_lock);
ef743d33 1016 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1017 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1018
ef743d33
SH		 1019 data->val_out = val;
1020 break;
1021 }
1022
1023 case SIOCSMIIREG:
1024 if (!capable(CAP_NET_ADMIN))
1025 return -EPERM;
1026
e07b1aa8 1027 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1028 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1029 data->val_in);
e07b1aa8 1030 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1031 break;
1032 }
1033 return err;
1034}
1035
d1f13708
SH		 1036#ifdef SKY2_VLAN_TAG_USED
1037static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1038{
1039 struct sky2_port *sky2 = netdev_priv(dev);
1040 struct sky2_hw *hw = sky2->hw;
1041 u16 port = sky2->port;
d1f13708 1042
2bb8c262 1043 netif_tx_lock_bh(dev);
d1f13708
SH		 1044
1045 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1046 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1047 sky2->vlgrp = grp;
1048
2bb8c262 1049 netif_tx_unlock_bh(dev);
d1f13708
SH		 1050}
1051
1052static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1053{
1054 struct sky2_port *sky2 = netdev_priv(dev);
1055 struct sky2_hw *hw = sky2->hw;
1056 u16 port = sky2->port;
d1f13708 1057
2bb8c262 1058 netif_tx_lock_bh(dev);
d1f13708
SH		 1059
1060 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1061 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
5c15bdec 1062 vlan_group_set_device(sky2->vlgrp, vid, NULL);
d1f13708 1063
2bb8c262 1064 netif_tx_unlock_bh(dev);
d1f13708
SH		 1065}
1066#endif
1067
82788c7a 1068/*
14d0263f
SH		 1069 * Allocate an skb for receiving. If the MTU is large enough
1070 * make the skb non-linear with a fragment list of pages.
1071 *
82788c7a
SH		 1072 * It appears the hardware has a bug in the FIFO logic that
1073 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1074 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1075 * aligned except if slab debugging is enabled.
82788c7a 1076 */
14d0263f 1077static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1078{
1079 struct sk_buff *skb;
14d0263f
SH		 1080 unsigned long p;
1081 int i;
82788c7a 1082
14d0263f
SH		 1083 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1084 if (!skb)
1085 goto nomem;
1086
1087 p = (unsigned long) skb->data;
1088 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1089
1090 for (i = 0; i < sky2->rx_nfrags; i++) {
1091 struct page *page = alloc_page(GFP_ATOMIC);
1092
1093 if (!page)
1094 goto free_partial;
1095 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1096 }
1097
1098 return skb;
14d0263f
SH		 1099free_partial:
1100 kfree_skb(skb);
1101nomem:
1102 return NULL;
82788c7a
SH		 1103}
1104
cd28ab6a
SH		 1105/*
1106 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1107 * Normal case this ends up creating one list element for skb
1108 * in the receive ring. Worst case if using large MTU and each
1109 * allocation falls on a different 64 bit region, that results
1110 * in 6 list elements per ring entry.
1111 * One element is used for checksum enable/disable, and one
1112 * extra to avoid wrap.
cd28ab6a 1113 */
6b1a3aef 1114static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1115{
6b1a3aef 1116 struct sky2_hw *hw = sky2->hw;
14d0263f 1117 struct rx_ring_info *re;
6b1a3aef 1118 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1119 unsigned i, size, space, thresh;
cd28ab6a 1120
6b1a3aef 1121 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1122 sky2_qset(hw, rxq);
977bdf06 1123
c3905bc4
SH		 1124 /* On PCI express lowering the watermark gives better performance */
1125 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1126 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1127
1128 /* These chips have no ram buffer?
1129 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1130 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1131 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1132 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
977bdf06 1133 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
977bdf06 1134
6b1a3aef
SH		 1135 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1136
1137 rx_set_checksum(sky2);
14d0263f
SH		 1138
1139 /* Space needed for frame data + headers rounded up */
1140 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1141 + 8;
1142
1143 /* Stopping point for hardware truncation */
1144 thresh = (size - 8) / sizeof(u32);
1145
1146 /* Account for overhead of skb - to avoid order > 0 allocation */
1147 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1148 + sizeof(struct skb_shared_info);
1149
1150 sky2->rx_nfrags = space >> PAGE_SHIFT;
1151 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1152
1153 if (sky2->rx_nfrags != 0) {
1154 /* Compute residue after pages */
1155 space = sky2->rx_nfrags << PAGE_SHIFT;
1156
1157 if (space < size)
1158 size -= space;
1159 else
1160 size = 0;
1161
1162 /* Optimize to handle small packets and headers */
1163 if (size < copybreak)
1164 size = copybreak;
1165 if (size < ETH_HLEN)
1166 size = ETH_HLEN;
1167 }
1168 sky2->rx_data_size = size;
1169
1170 /* Fill Rx ring */
793b883e 1171 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1172 re = sky2->rx_ring + i;
cd28ab6a 1173
14d0263f 1174 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1175 if (!re->skb)
1176 goto nomem;
1177
14d0263f
SH		 1178 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1179 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1180 }
1181
a1433ac4
SH		 1182 /*
1183 * The receiver hangs if it receives frames larger than the
1184 * packet buffer. As a workaround, truncate oversize frames, but
1185 * the register is limited to 9 bits, so if you do frames > 2052
1186 * you better get the MTU right!
1187 */
a1433ac4
SH		 1188 if (thresh > 0x1ff)
1189 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1190 else {
1191 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1192 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1193 }
1194
6b1a3aef
SH		 1195 /* Tell chip about available buffers */
1196 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1197 return 0;
1198nomem:
1199 sky2_rx_clean(sky2);
1200 return -ENOMEM;
1201}
1202
1203/* Bring up network interface. */
1204static int sky2_up(struct net_device *dev)
1205{
1206 struct sky2_port *sky2 = netdev_priv(dev);
1207 struct sky2_hw *hw = sky2->hw;
1208 unsigned port = sky2->port;
67712901 1209 u32 ramsize, imask;
ee7abb04 1210 int cap, err = -ENOMEM;
843a46f4 1211 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1212
ee7abb04
SH		 1213 /*
1214 * On dual port PCI-X card, there is an problem where status
1215 * can be received out of order due to split transactions
843a46f4 1216 */
ee7abb04
SH		 1217 if (otherdev && netif_running(otherdev) &&
1218 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1219 struct sky2_port *osky2 = netdev_priv(otherdev);
1220 u16 cmd;
1221
1222 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1223 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1224 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1225
1226 sky2->rx_csum = 0;
1227 osky2->rx_csum = 0;
1228 }
843a46f4 1229
cd28ab6a
SH		 1230 if (netif_msg_ifup(sky2))
1231 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1232
1233 /* must be power of 2 */
1234 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1235 TX_RING_SIZE *
1236 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1237 &sky2->tx_le_map);
1238 if (!sky2->tx_le)
1239 goto err_out;
1240
6cdbbdf3 1241 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1242 GFP_KERNEL);
1243 if (!sky2->tx_ring)
1244 goto err_out;
1245 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1246
1247 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1248 &sky2->rx_le_map);
1249 if (!sky2->rx_le)
1250 goto err_out;
1251 memset(sky2->rx_le, 0, RX_LE_BYTES);
1252
291ea614 1253 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1254 GFP_KERNEL);
1255 if (!sky2->rx_ring)
1256 goto err_out;
1257
d3bcfbeb
SH		 1258 sky2_phy_power(hw, port, 1);
1259
cd28ab6a
SH		 1260 sky2_mac_init(hw, port);
1261
67712901
SH		 1262 /* Register is number of 4K blocks on internal RAM buffer. */
1263 ramsize = sky2_read8(hw, B2_E_0) * 4;
1264 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1265
67712901
SH		 1266 if (ramsize > 0) {
1267 u32 rxspace;
cd28ab6a 1268
67712901
SH		 1269 if (ramsize < 16)
1270 rxspace = ramsize / 2;
1271 else
1272 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1273
67712901
SH		 1274 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1275 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1276
1277 /* Make sure SyncQ is disabled */
1278 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1279 RB_RST_SET);
1280 }
793b883e 1281
af4ed7e6 1282 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1283
977bdf06 1284 /* Set almost empty threshold */
c2716fb4
SH		 1285 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1286 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1287 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1288
6b1a3aef
SH		 1289 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1290 TX_RING_SIZE - 1);
cd28ab6a 1291
6b1a3aef 1292 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1293 if (err)
1294 goto err_out;
1295
cd28ab6a 1296 /* Enable interrupts from phy/mac for port */
e07b1aa8 1297 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1298 imask |= portirq_msk[port];
e07b1aa8
SH		 1299 sky2_write32(hw, B0_IMSK, imask);
1300
cd28ab6a
SH		 1301 return 0;
1302
1303err_out:
1b537565 1304 if (sky2->rx_le) {
cd28ab6a
SH		 1305 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1306 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1307 sky2->rx_le = NULL;
1308 }
1309 if (sky2->tx_le) {
cd28ab6a
SH		 1310 pci_free_consistent(hw->pdev,
1311 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1312 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1313 sky2->tx_le = NULL;
1314 }
1315 kfree(sky2->tx_ring);
1316 kfree(sky2->rx_ring);
cd28ab6a 1317
1b537565
SH		 1318 sky2->tx_ring = NULL;
1319 sky2->rx_ring = NULL;
cd28ab6a
SH		 1320 return err;
1321}
1322
793b883e
SH		 1323/* Modular subtraction in ring */
1324static inline int tx_dist(unsigned tail, unsigned head)
1325{
cb5d9547 1326 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1327}
cd28ab6a 1328
793b883e
SH		 1329/* Number of list elements available for next tx */
1330static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1331{
793b883e 1332 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1333}
1334
793b883e 1335/* Estimate of number of transmit list elements required */
28bd181a 1336static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1337{
793b883e
SH		 1338 unsigned count;
1339
1340 count = sizeof(dma_addr_t) / sizeof(u32);
1341 count += skb_shinfo(skb)->nr_frags * count;
1342
89114afd 1343 if (skb_is_gso(skb))
793b883e
SH		 1344 ++count;
1345
84fa7933 1346 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1347 ++count;
1348
1349 return count;
cd28ab6a
SH		 1350}
1351
793b883e
SH		 1352/*
1353 * Put one packet in ring for transmit.
1354 * A single packet can generate multiple list elements, and
1355 * the number of ring elements will probably be less than the number
1356 * of list elements used.
1357 */
cd28ab6a
SH		 1358static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1359{
1360 struct sky2_port *sky2 = netdev_priv(dev);
1361 struct sky2_hw *hw = sky2->hw;
d1f13708 1362 struct sky2_tx_le *le = NULL;
6cdbbdf3 1363 struct tx_ring_info *re;
cd28ab6a
SH		 1364 unsigned i, len;
1365 dma_addr_t mapping;
1366 u32 addr64;
1367 u16 mss;
1368 u8 ctrl;
1369
2bb8c262
SH		 1370 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1371 return NETDEV_TX_BUSY;
cd28ab6a 1372
793b883e 1373 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1374 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1375 dev->name, sky2->tx_prod, skb->len);
1376
cd28ab6a
SH		 1377 len = skb_headlen(skb);
1378 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1379 addr64 = high32(mapping);
793b883e 1380
a018e330
SH		 1381 /* Send high bits if changed or crosses boundary */
1382 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1383 le = get_tx_le(sky2);
f65b138c 1384 le->addr = cpu_to_le32(addr64);
793b883e 1385 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1386 sky2->tx_addr64 = high32(mapping + len);
793b883e 1387 }
cd28ab6a
SH		 1388
1389 /* Check for TCP Segmentation Offload */
7967168c 1390 mss = skb_shinfo(skb)->gso_size;
793b883e 1391 if (mss != 0) {
ab6a5bb6 1392 mss += tcp_optlen(skb); /* TCP options */
c9bdd4b5 1393 mss += ip_hdrlen(skb) + sizeof(struct tcphdr);
cd28ab6a
SH		 1394 mss += ETH_HLEN;
1395
e07560cd
SH		 1396 if (mss != sky2->tx_last_mss) {
1397 le = get_tx_le(sky2);
f65b138c 1398 le->addr = cpu_to_le32(mss);
e07560cd 1399 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1400 sky2->tx_last_mss = mss;
1401 }
cd28ab6a
SH		 1402 }
1403
cd28ab6a 1404 ctrl = 0;
d1f13708
SH		 1405#ifdef SKY2_VLAN_TAG_USED
1406 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1407 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1408 if (!le) {
1409 le = get_tx_le(sky2);
f65b138c 1410 le->addr = 0;
d1f13708 1411 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1412 } else
1413 le->opcode |= OP_VLAN;
1414 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1415 ctrl |= INS_VLAN;
1416 }
1417#endif
1418
1419 /* Handle TCP checksum offload */
84fa7933 1420 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d 1421 const unsigned offset = skb_transport_offset(skb);
f65b138c
SH		 1422 u32 tcpsum;
1423
1424 tcpsum = offset << 16; /* sum start */
ff1dcadb 1425 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a
SH		 1426
1427 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
eddc9ec5 1428 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
cd28ab6a
SH		 1429 ctrl |= UDPTCP;
1430
f65b138c
SH		 1431 if (tcpsum != sky2->tx_tcpsum) {
1432 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1433
1434 le = get_tx_le(sky2);
f65b138c 1435 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1436 le->length = 0; /* initial checksum value */
1437 le->ctrl = 1; /* one packet */
1438 le->opcode = OP_TCPLISW | HW_OWNER;
1439 }
cd28ab6a
SH		 1440 }
1441
1442 le = get_tx_le(sky2);
f65b138c 1443 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1444 le->length = cpu_to_le16(len);
1445 le->ctrl = ctrl;
793b883e 1446 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1447
291ea614 1448 re = tx_le_re(sky2, le);
cd28ab6a 1449 re->skb = skb;
6cdbbdf3 1450 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1451 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1452
1453 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1454 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1455
1456 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1457 frag->size, PCI_DMA_TODEVICE);
a036119f 1458 addr64 = high32(mapping);
793b883e
SH		 1459 if (addr64 != sky2->tx_addr64) {
1460 le = get_tx_le(sky2);
f65b138c 1461 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1462 le->ctrl = 0;
1463 le->opcode = OP_ADDR64 | HW_OWNER;
1464 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1465 }
1466
1467 le = get_tx_le(sky2);
f65b138c 1468 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1469 le->length = cpu_to_le16(frag->size);
1470 le->ctrl = ctrl;
793b883e 1471 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1472
291ea614
SH		 1473 re = tx_le_re(sky2, le);
1474 re->skb = skb;
1475 pci_unmap_addr_set(re, mapaddr, mapping);
1476 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1477 }
6cdbbdf3 1478
cd28ab6a
SH		 1479 le->ctrl |= EOP;
1480
97bda706
SH		 1481 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1482 netif_stop_queue(dev);
b19666d9 1483
290d4de5 1484 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1485
cd28ab6a
SH		 1486 dev->trans_start = jiffies;
1487 return NETDEV_TX_OK;
1488}
1489
cd28ab6a 1490/*
793b883e
SH		 1491 * Free ring elements from starting at tx_cons until "done"
1492 *
1493 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1494 * buffers so make sure not to free skb to early.
cd28ab6a 1495 */
d11c13e7 1496static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1497{
d11c13e7 1498 struct net_device *dev = sky2->netdev;
af2a58ac 1499 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1500 unsigned idx;
cd28ab6a 1501
0e3ff6aa 1502 BUG_ON(done >= TX_RING_SIZE);
2224795d 1503
291ea614
SH		 1504 for (idx = sky2->tx_cons; idx != done;
1505 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1506 struct sky2_tx_le *le = sky2->tx_le + idx;
1507 struct tx_ring_info *re = sky2->tx_ring + idx;
1508
1509 switch(le->opcode & ~HW_OWNER) {
1510 case OP_LARGESEND:
1511 case OP_PACKET:
1512 pci_unmap_single(pdev,
1513 pci_unmap_addr(re, mapaddr),
1514 pci_unmap_len(re, maplen),
1515 PCI_DMA_TODEVICE);
af2a58ac 1516 break;
291ea614
SH		 1517 case OP_BUFFER:
1518 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1519 pci_unmap_len(re, maplen),
734d1868 1520 PCI_DMA_TODEVICE);
291ea614
SH		 1521 break;
1522 }
1523
1524 if (le->ctrl & EOP) {
1525 if (unlikely(netif_msg_tx_done(sky2)))
1526 printk(KERN_DEBUG "%s: tx done %u\n",
1527 dev->name, idx);
2bf56fe2 1528 sky2->net_stats.tx_packets++;
1529 sky2->net_stats.tx_bytes += re->skb->len;
1530
794b2bd2 1531 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1532 }
1533
291ea614 1534 le->opcode = 0; /* paranoia */
793b883e 1535 }
793b883e 1536
291ea614 1537 sky2->tx_cons = idx;
22e11703 1538 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1539 netif_wake_queue(dev);
cd28ab6a
SH		 1540}
1541
1542/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1543static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1544{
2bb8c262
SH		 1545 struct sky2_port *sky2 = netdev_priv(dev);
1546
1547 netif_tx_lock_bh(dev);
d11c13e7 1548 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1549 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1550}
1551
1552/* Network shutdown */
1553static int sky2_down(struct net_device *dev)
1554{
1555 struct sky2_port *sky2 = netdev_priv(dev);
1556 struct sky2_hw *hw = sky2->hw;
1557 unsigned port = sky2->port;
1558 u16 ctrl;
e07b1aa8 1559 u32 imask;
cd28ab6a 1560
1b537565
SH		 1561 /* Never really got started! */
1562 if (!sky2->tx_le)
1563 return 0;
1564
cd28ab6a
SH		 1565 if (netif_msg_ifdown(sky2))
1566 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1567
018d1c66 1568 /* Stop more packets from being queued */
cd28ab6a 1569 netif_stop_queue(dev);
9a87240c 1570 netif_carrier_off(dev);
cd28ab6a 1571
ebc646f6
SH		 1572 /* Disable port IRQ */
1573 imask = sky2_read32(hw, B0_IMSK);
1574 imask &= ~portirq_msk[port];
1575 sky2_write32(hw, B0_IMSK, imask);
1576
25d82d7a
SH		 1577 /*
1578 * Both ports share the NAPI poll on port 0, so if necessary undo the
1579 * the disable that is done in dev_close.
1580 */
1581 if (sky2->port == 0 && hw->ports > 1)
1582 netif_poll_enable(dev);
1583
d3bcfbeb 1584 sky2_gmac_reset(hw, port);
793b883e 1585
cd28ab6a
SH		 1586 /* Stop transmitter */
1587 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1588 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1589
1590 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1591 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1592
1593 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1594 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1595 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1596
1597 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1598
1599 /* Workaround shared GMAC reset */
793b883e
SH		 1600 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1601 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1602 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1603
1604 /* Disable Force Sync bit and Enable Alloc bit */
1605 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1606 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1607
1608 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1609 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1610 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1611
1612 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1613 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1614 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1615
1616 /* Reset the Tx prefetch units */
1617 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1618 PREF_UNIT_RST_SET);
1619
1620 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1621
6b1a3aef 1622 sky2_rx_stop(sky2);
cd28ab6a
SH		 1623
1624 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1625 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1626
d3bcfbeb
SH		 1627 sky2_phy_power(hw, port, 0);
1628
d571b694 1629 /* turn off LED's */
cd28ab6a
SH		 1630 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1631
018d1c66
SH		 1632 synchronize_irq(hw->pdev->irq);
1633
2bb8c262 1634 sky2_tx_clean(dev);
cd28ab6a
SH		 1635 sky2_rx_clean(sky2);
1636
1637 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1638 sky2->rx_le, sky2->rx_le_map);
1639 kfree(sky2->rx_ring);
1640
1641 pci_free_consistent(hw->pdev,
1642 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1643 sky2->tx_le, sky2->tx_le_map);
1644 kfree(sky2->tx_ring);
1645
1b537565
SH		 1646 sky2->tx_le = NULL;
1647 sky2->rx_le = NULL;
1648
1649 sky2->rx_ring = NULL;
1650 sky2->tx_ring = NULL;
1651
cd28ab6a
SH		 1652 return 0;
1653}
1654
1655static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1656{
b89165f2 1657 if (!sky2_is_copper(hw))
793b883e
SH		 1658 return SPEED_1000;
1659
cd28ab6a
SH		 1660 if (hw->chip_id == CHIP_ID_YUKON_FE)
1661 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1662
1663 switch (aux & PHY_M_PS_SPEED_MSK) {
1664 case PHY_M_PS_SPEED_1000:
1665 return SPEED_1000;
1666 case PHY_M_PS_SPEED_100:
1667 return SPEED_100;
1668 default:
1669 return SPEED_10;
1670 }
1671}
1672
1673static void sky2_link_up(struct sky2_port *sky2)
1674{
1675 struct sky2_hw *hw = sky2->hw;
1676 unsigned port = sky2->port;
1677 u16 reg;
16ad91e1
SH		 1678 static const char *fc_name[] = {
1679 [FC_NONE] = "none",
1680 [FC_TX] = "tx",
1681 [FC_RX] = "rx",
1682 [FC_BOTH] = "both",
1683 };
cd28ab6a 1684
cd28ab6a 1685 /* enable Rx/Tx */
2eaba1a2 1686 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1687 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1688 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1689
1690 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1691
1692 netif_carrier_on(sky2->netdev);
1693 netif_wake_queue(sky2->netdev);
1694
1695 /* Turn on link LED */
793b883e 1696 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1697 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1698
93745494
SH		 1699 if (hw->chip_id == CHIP_ID_YUKON_XL
1700 || hw->chip_id == CHIP_ID_YUKON_EC_U
1701 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1702 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1703 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1704
1705 switch(sky2->speed) {
1706 case SPEED_10:
1707 led |= PHY_M_LEDC_INIT_CTRL(7);
1708 break;
1709
1710 case SPEED_100:
1711 led |= PHY_M_LEDC_STA1_CTRL(7);
1712 break;
1713
1714 case SPEED_1000:
1715 led |= PHY_M_LEDC_STA0_CTRL(7);
1716 break;
1717 }
793b883e
SH		 1718
1719 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1720 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1721 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1722 }
1723
cd28ab6a
SH		 1724 if (netif_msg_link(sky2))
1725 printk(KERN_INFO PFX
d571b694 1726 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1727 sky2->netdev->name, sky2->speed,
1728 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1729 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1730}
1731
1732static void sky2_link_down(struct sky2_port *sky2)
1733{
1734 struct sky2_hw *hw = sky2->hw;
1735 unsigned port = sky2->port;
1736 u16 reg;
1737
1738 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1739
1740 reg = gma_read16(hw, port, GM_GP_CTRL);
1741 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1742 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1743
cd28ab6a
SH		 1744 netif_carrier_off(sky2->netdev);
1745 netif_stop_queue(sky2->netdev);
1746
1747 /* Turn on link LED */
1748 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1749
1750 if (netif_msg_link(sky2))
1751 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1752
cd28ab6a
SH		 1753 sky2_phy_init(hw, port);
1754}
1755
16ad91e1
SH		 1756static enum flow_control sky2_flow(int rx, int tx)
1757{
1758 if (rx)
1759 return tx ? FC_BOTH : FC_RX;
1760 else
1761 return tx ? FC_TX : FC_NONE;
1762}
1763
793b883e
SH		 1764static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1765{
1766 struct sky2_hw *hw = sky2->hw;
1767 unsigned port = sky2->port;
da4c1ff4 1768 u16 advert, lpa;
793b883e 1769
da4c1ff4 1770 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1771 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1772 if (lpa & PHY_M_AN_RF) {
1773 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1774 return -1;
1775 }
1776
793b883e
SH		 1777 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1778 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1779 sky2->netdev->name);
1780 return -1;
1781 }
1782
793b883e 1783 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1784 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1785
da4c1ff4
SH		 1786 /* Since the pause result bits seem to in different positions on
1787 * different chips. look at registers.
1788 */
1789 if (!sky2_is_copper(hw)) {
1790 /* Shift for bits in fiber PHY */
1791 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1792 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1793
1794 if (advert & ADVERTISE_1000XPAUSE)
1795 advert |= ADVERTISE_PAUSE_CAP;
1796 if (advert & ADVERTISE_1000XPSE_ASYM)
1797 advert |= ADVERTISE_PAUSE_ASYM;
1798 if (lpa & LPA_1000XPAUSE)
1799 lpa |= LPA_PAUSE_CAP;
1800 if (lpa & LPA_1000XPAUSE_ASYM)
1801 lpa |= LPA_PAUSE_ASYM;
1802 }
793b883e 1803
da4c1ff4
SH		 1804 sky2->flow_status = FC_NONE;
1805 if (advert & ADVERTISE_PAUSE_CAP) {
1806 if (lpa & LPA_PAUSE_CAP)
1807 sky2->flow_status = FC_BOTH;
1808 else if (advert & ADVERTISE_PAUSE_ASYM)
1809 sky2->flow_status = FC_RX;
1810 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1811 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1812 sky2->flow_status = FC_TX;
1813 }
793b883e 1814
16ad91e1 1815 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1816 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1817 sky2->flow_status = FC_NONE;
2eaba1a2 1818
da4c1ff4 1819 if (sky2->flow_status & FC_TX)
793b883e
SH		 1820 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1821 else
1822 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1823
1824 return 0;
1825}
cd28ab6a 1826
e07b1aa8
SH		 1827/* Interrupt from PHY */
1828static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1829{
e07b1aa8
SH		 1830 struct net_device *dev = hw->dev[port];
1831 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1832 u16 istatus, phystat;
1833
ebc646f6
SH		 1834 if (!netif_running(dev))
1835 return;
1836
e07b1aa8
SH		 1837 spin_lock(&sky2->phy_lock);
1838 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1839 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1840
cd28ab6a
SH		 1841 if (netif_msg_intr(sky2))
1842 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1843 sky2->netdev->name, istatus, phystat);
1844
2eaba1a2 1845 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1846 if (sky2_autoneg_done(sky2, phystat) == 0)
1847 sky2_link_up(sky2);
1848 goto out;
1849 }
cd28ab6a 1850
793b883e
SH		 1851 if (istatus & PHY_M_IS_LSP_CHANGE)
1852 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1853
793b883e
SH		 1854 if (istatus & PHY_M_IS_DUP_CHANGE)
1855 sky2->duplex =
1856 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1857
793b883e
SH		 1858 if (istatus & PHY_M_IS_LST_CHANGE) {
1859 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1860 sky2_link_up(sky2);
793b883e
SH		 1861 else
1862 sky2_link_down(sky2);
cd28ab6a 1863 }
793b883e 1864out:
e07b1aa8 1865 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1866}
1867
62335ab0 1868/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1869 * and tx queue is full (stopped).
1870 */
cd28ab6a
SH		 1871static void sky2_tx_timeout(struct net_device *dev)
1872{
1873 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1874 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1875
1876 if (netif_msg_timer(sky2))
1877 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1878
8f24664d 1879 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1880 dev->name, sky2->tx_cons, sky2->tx_prod,
1881 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1882 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1883
81906791
SH		 1884 /* can't restart safely under softirq */
1885 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1886}
1887
1888static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1889{
6b1a3aef
SH		 1890 struct sky2_port *sky2 = netdev_priv(dev);
1891 struct sky2_hw *hw = sky2->hw;
b628ed98 1892 unsigned port = sky2->port;
6b1a3aef
SH		 1893 int err;
1894 u16 ctl, mode;
e07b1aa8 1895 u32 imask;
cd28ab6a
SH		 1896
1897 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1898 return -EINVAL;
1899
d2adf4f6
SH		 1900 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1901 return -EINVAL;
1902
6b1a3aef
SH		 1903 if (!netif_running(dev)) {
1904 dev->mtu = new_mtu;
1905 return 0;
1906 }
1907
e07b1aa8 1908 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1909 sky2_write32(hw, B0_IMSK, 0);
1910
018d1c66
SH		 1911 dev->trans_start = jiffies; /* prevent tx timeout */
1912 netif_stop_queue(dev);
1913 netif_poll_disable(hw->dev[0]);
1914
e07b1aa8
SH		 1915 synchronize_irq(hw->pdev->irq);
1916
b628ed98
SH		 1917 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
1918 if (new_mtu > ETH_DATA_LEN) {
1919 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1920 TX_JUMBO_ENA | TX_STFW_DIS);
1921 dev->features &= NETIF_F_TSO | NETIF_F_SG | NETIF_F_IP_CSUM;
1922 } else
1923 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1924 TX_JUMBO_DIS | TX_STFW_ENA);
1925 }
1926
1927 ctl = gma_read16(hw, port, GM_GP_CTRL);
1928 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 1929 sky2_rx_stop(sky2);
1930 sky2_rx_clean(sky2);
cd28ab6a
SH		 1931
1932 dev->mtu = new_mtu;
14d0263f 1933
6b1a3aef
SH		 1934 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1935 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1936
1937 if (dev->mtu > ETH_DATA_LEN)
1938 mode |= GM_SMOD_JUMBO_ENA;
1939
b628ed98 1940 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 1941
b628ed98 1942 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1943
6b1a3aef 1944 err = sky2_rx_start(sky2);
e07b1aa8 1945 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1946
1b537565
SH		 1947 if (err)
1948 dev_close(dev);
1949 else {
b628ed98 1950 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 1951
1952 netif_poll_enable(hw->dev[0]);
1953 netif_wake_queue(dev);
1954 }
1955
cd28ab6a
SH		 1956 return err;
1957}
1958
14d0263f
SH		 1959/* For small just reuse existing skb for next receive */
1960static struct sk_buff *receive_copy(struct sky2_port *sky2,
1961 const struct rx_ring_info *re,
1962 unsigned length)
1963{
1964 struct sk_buff *skb;
1965
1966 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1967 if (likely(skb)) {
1968 skb_reserve(skb, 2);
1969 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1970 length, PCI_DMA_FROMDEVICE);
d626f62b 1971 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 1972 skb->ip_summed = re->skb->ip_summed;
1973 skb->csum = re->skb->csum;
1974 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1975 length, PCI_DMA_FROMDEVICE);
1976 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1977 skb_put(skb, length);
14d0263f
SH		 1978 }
1979 return skb;
1980}
1981
1982/* Adjust length of skb with fragments to match received data */
1983static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1984 unsigned int length)
1985{
1986 int i, num_frags;
1987 unsigned int size;
1988
1989 /* put header into skb */
1990 size = min(length, hdr_space);
1991 skb->tail += size;
1992 skb->len += size;
1993 length -= size;
1994
1995 num_frags = skb_shinfo(skb)->nr_frags;
1996 for (i = 0; i < num_frags; i++) {
1997 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1998
1999 if (length == 0) {
2000 /* don't need this page */
2001 __free_page(frag->page);
2002 --skb_shinfo(skb)->nr_frags;
2003 } else {
2004 size = min(length, (unsigned) PAGE_SIZE);
2005
2006 frag->size = size;
2007 skb->data_len += size;
2008 skb->truesize += size;
2009 skb->len += size;
2010 length -= size;
2011 }
2012 }
2013}
2014
2015/* Normal packet - take skb from ring element and put in a new one */
2016static struct sk_buff *receive_new(struct sky2_port *sky2,
2017 struct rx_ring_info *re,
2018 unsigned int length)
2019{
2020 struct sk_buff *skb, *nskb;
2021 unsigned hdr_space = sky2->rx_data_size;
2022
2023 pr_debug(PFX "receive new length=%d\n", length);
2024
2025 /* Don't be tricky about reusing pages (yet) */
2026 nskb = sky2_rx_alloc(sky2);
2027 if (unlikely(!nskb))
2028 return NULL;
2029
2030 skb = re->skb;
2031 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2032
2033 prefetch(skb->data);
2034 re->skb = nskb;
2035 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2036
2037 if (skb_shinfo(skb)->nr_frags)
2038 skb_put_frags(skb, hdr_space, length);
2039 else
489b10c1 2040 skb_put(skb, length);
14d0263f
SH		 2041 return skb;
2042}
2043
cd28ab6a
SH		 2044/*
2045 * Receive one packet.
d571b694 2046 * For larger packets, get new buffer.
cd28ab6a 2047 */
497d7c86 2048static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2049 u16 length, u32 status)
2050{
497d7c86 2051 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2052 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2053 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2054
2055 if (unlikely(netif_msg_rx_status(sky2)))
2056 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2057 dev->name, sky2->rx_next, status, length);
cd28ab6a 2058
793b883e 2059 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2060 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2061
42eeea01 2062 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2063 goto error;
2064
42eeea01
SH		 2065 if (!(status & GMR_FS_RX_OK))
2066 goto resubmit;
2067
14d0263f
SH		 2068 if (length < copybreak)
2069 skb = receive_copy(sky2, re, length);
2070 else
2071 skb = receive_new(sky2, re, length);
793b883e 2072resubmit:
14d0263f 2073 sky2_rx_submit(sky2, re);
79e57d32 2074
cd28ab6a
SH		 2075 return skb;
2076
2077error:
6e15b712 2078 ++sky2->net_stats.rx_errors;
b6d77734 2079 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2080 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2081 goto resubmit;
2082 }
6e15b712 2083
3be92a70 2084 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2085 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2086 dev->name, status, length);
793b883e
SH		 2087
2088 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2089 sky2->net_stats.rx_length_errors++;
2090 if (status & GMR_FS_FRAGMENT)
2091 sky2->net_stats.rx_frame_errors++;
2092 if (status & GMR_FS_CRC_ERR)
2093 sky2->net_stats.rx_crc_errors++;
79e57d32 2094
793b883e 2095 goto resubmit;
cd28ab6a
SH		 2096}
2097
e07b1aa8
SH		 2098/* Transmit complete */
2099static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2100{
e07b1aa8 2101 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2102
e07b1aa8 2103 if (netif_running(dev)) {
2bb8c262 2104 netif_tx_lock(dev);
e07b1aa8 2105 sky2_tx_complete(sky2, last);
2bb8c262 2106 netif_tx_unlock(dev);
2224795d 2107 }
cd28ab6a
SH		 2108}
2109
e07b1aa8
SH		 2110/* Process status response ring */
2111static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2112{
22e11703 2113 struct sky2_port *sky2;
e07b1aa8 2114 int work_done = 0;
22e11703 2115 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2116 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2117
af2a58ac 2118 rmb();
bea86103 2119
e71ebd73 2120 while (hw->st_idx != hwidx) {
13210ce5
SH		 2121 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2122 struct net_device *dev;
cd28ab6a 2123 struct sk_buff *skb;
cd28ab6a
SH		 2124 u32 status;
2125 u16 length;
2126
cb5d9547 2127 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2128
e71ebd73
SH		 2129 BUG_ON(le->link >= 2);
2130 dev = hw->dev[le->link];
13210ce5
SH		 2131
2132 sky2 = netdev_priv(dev);
f65b138c
SH		 2133 length = le16_to_cpu(le->length);
2134 status = le32_to_cpu(le->status);
cd28ab6a 2135
e71ebd73 2136 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2137 case OP_RXSTAT:
497d7c86 2138 skb = sky2_receive(dev, length, status);
d1f13708 2139 if (!skb)
5df79111 2140 goto force_update;
13210ce5 2141
13210ce5 2142 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2143 sky2->net_stats.rx_packets++;
2144 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2145 dev->last_rx = jiffies;
2146
d1f13708
SH		 2147#ifdef SKY2_VLAN_TAG_USED
2148 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2149 vlan_hwaccel_receive_skb(skb,
2150 sky2->vlgrp,
2151 be16_to_cpu(sky2->rx_tag));
2152 } else
2153#endif
cd28ab6a 2154 netif_receive_skb(skb);
13210ce5 2155
22e11703
SH		 2156 /* Update receiver after 16 frames */
2157 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2158force_update:
2159 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2160 buf_write[le->link] = 0;
2161 }
2162
2163 /* Stop after net poll weight */
13210ce5
SH		 2164 if (++work_done >= to_do)
2165 goto exit_loop;
cd28ab6a
SH		 2166 break;
2167
d1f13708
SH		 2168#ifdef SKY2_VLAN_TAG_USED
2169 case OP_RXVLAN:
2170 sky2->rx_tag = length;
2171 break;
2172
2173 case OP_RXCHKSVLAN:
2174 sky2->rx_tag = length;
2175 /* fall through */
2176#endif
cd28ab6a 2177 case OP_RXCHKS:
87418307
SH		 2178 if (!sky2->rx_csum)
2179 break;
2180
2181 /* Both checksum counters are programmed to start at
2182 * the same offset, so unless there is a problem they
2183 * should match. This failure is an early indication that
2184 * hardware receive checksumming won't work.
2185 */
2186 if (likely(status >> 16 == (status & 0xffff))) {
2187 skb = sky2->rx_ring[sky2->rx_next].skb;
2188 skb->ip_summed = CHECKSUM_COMPLETE;
2189 skb->csum = status & 0xffff;
2190 } else {
2191 printk(KERN_NOTICE PFX "%s: hardware receive "
2192 "checksum problem (status = %#x)\n",
2193 dev->name, status);
2194 sky2->rx_csum = 0;
2195 sky2_write32(sky2->hw,
2196 Q_ADDR(rxqaddr[le->link], Q_CSR),
2197 BMU_DIS_RX_CHKSUM);
2198 }
cd28ab6a
SH		 2199 break;
2200
2201 case OP_TXINDEXLE:
13b97b74 2202 /* TX index reports status for both ports */
f55925d7
SH		 2203 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2204 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2205 if (hw->dev[1])
2206 sky2_tx_done(hw->dev[1],
2207 ((status >> 24) & 0xff)
2208 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2209 break;
2210
cd28ab6a
SH		 2211 default:
2212 if (net_ratelimit())
793b883e 2213 printk(KERN_WARNING PFX
e71ebd73
SH		 2214 "unknown status opcode 0x%x\n", le->opcode);
2215 goto exit_loop;
cd28ab6a 2216 }
13210ce5 2217 }
cd28ab6a 2218
fe2a24df
SH		 2219 /* Fully processed status ring so clear irq */
2220 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2221
13210ce5 2222exit_loop:
22e11703
SH		 2223 if (buf_write[0]) {
2224 sky2 = netdev_priv(hw->dev[0]);
2225 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2226 }
2227
2228 if (buf_write[1]) {
2229 sky2 = netdev_priv(hw->dev[1]);
2230 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2231 }
2232
e07b1aa8 2233 return work_done;
cd28ab6a
SH		 2234}
2235
2236static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2237{
2238 struct net_device *dev = hw->dev[port];
2239
3be92a70
SH		 2240 if (net_ratelimit())
2241 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2242 dev->name, status);
cd28ab6a
SH		 2243
2244 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2245 if (net_ratelimit())
2246 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2247 dev->name);
cd28ab6a
SH		 2248 /* Clear IRQ */
2249 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2250 }
2251
2252 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2253 if (net_ratelimit())
2254 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2255 dev->name);
cd28ab6a
SH		 2256
2257 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2258 }
2259
2260 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2261 if (net_ratelimit())
2262 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2263 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2264 }
2265
2266 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2267 if (net_ratelimit())
2268 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2269 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2270 }
2271
2272 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2273 if (net_ratelimit())
2274 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2275 dev->name);
cd28ab6a
SH		 2276 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2277 }
2278}
2279
2280static void sky2_hw_intr(struct sky2_hw *hw)
2281{
2282 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2283
793b883e 2284 if (status & Y2_IS_TIST_OV)
cd28ab6a 2285 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2286
2287 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2288 u16 pci_err;
2289
56a645cc 2290 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2291 if (net_ratelimit())
b02a9258
SH		 2292 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2293 pci_err);
cd28ab6a
SH		 2294
2295 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2296 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2297 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2298 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2299 }
2300
2301 if (status & Y2_IS_PCI_EXP) {
d571b694 2302 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2303 u32 pex_err;
2304
7bd656d1 2305 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2306
3be92a70 2307 if (net_ratelimit())
b02a9258
SH		 2308 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2309 pex_err);
cd28ab6a
SH		 2310
2311 /* clear the interrupt */
2312 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2313 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2314 0xffffffffUL);
cd28ab6a
SH		 2315 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2316
7bd656d1 2317 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2318 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2319 hwmsk &= ~Y2_IS_PCI_EXP;
2320 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2321 }
2322 }
2323
2324 if (status & Y2_HWE_L1_MASK)
2325 sky2_hw_error(hw, 0, status);
2326 status >>= 8;
2327 if (status & Y2_HWE_L1_MASK)
2328 sky2_hw_error(hw, 1, status);
2329}
2330
2331static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2332{
2333 struct net_device *dev = hw->dev[port];
2334 struct sky2_port *sky2 = netdev_priv(dev);
2335 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2336
2337 if (netif_msg_intr(sky2))
2338 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2339 dev->name, status);
2340
2341 if (status & GM_IS_RX_FF_OR) {
2342 ++sky2->net_stats.rx_fifo_errors;
2343 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2344 }
2345
2346 if (status & GM_IS_TX_FF_UR) {
2347 ++sky2->net_stats.tx_fifo_errors;
2348 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2349 }
cd28ab6a
SH		 2350}
2351
40b01727
SH		 2352/* This should never happen it is a bug. */
2353static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2354 u16 q, unsigned ring_size)
d257924e
SH		 2355{
2356 struct net_device *dev = hw->dev[port];
2357 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2358 unsigned idx;
2359 const u64 *le = (q == Q_R1 || q == Q_R2)
2360 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2361
40b01727
SH		 2362 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2363 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2364 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2365 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2366
40b01727 2367 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2368}
cd28ab6a 2369
d27ed387
SH		 2370/* If idle then force a fake soft NAPI poll once a second
2371 * to work around cases where sharing an edge triggered interrupt.
2372 */
eb35cf60
SH		 2373static inline void sky2_idle_start(struct sky2_hw *hw)
2374{
2375 if (idle_timeout > 0)
2376 mod_timer(&hw->idle_timer,
2377 jiffies + msecs_to_jiffies(idle_timeout));
2378}
2379
d27ed387
SH		 2380static void sky2_idle(unsigned long arg)
2381{
01bd7564
SH		 2382 struct sky2_hw *hw = (struct sky2_hw *) arg;
2383 struct net_device *dev = hw->dev[0];
d27ed387 2384
d27ed387
SH		 2385 if (__netif_rx_schedule_prep(dev))
2386 __netif_rx_schedule(dev);
01bd7564
SH		 2387
2388 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2389}
2390
40b01727
SH		 2391/* Hardware/software error handling */
2392static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2393{
40b01727
SH		 2394 if (net_ratelimit())
2395 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2396
1e5f1283
SH		 2397 if (status & Y2_IS_HW_ERR)
2398 sky2_hw_intr(hw);
d257924e 2399
1e5f1283
SH		 2400 if (status & Y2_IS_IRQ_MAC1)
2401 sky2_mac_intr(hw, 0);
cd28ab6a 2402
1e5f1283
SH		 2403 if (status & Y2_IS_IRQ_MAC2)
2404 sky2_mac_intr(hw, 1);
cd28ab6a 2405
1e5f1283 2406 if (status & Y2_IS_CHK_RX1)
40b01727 2407 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2408
1e5f1283 2409 if (status & Y2_IS_CHK_RX2)
40b01727 2410 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2411
1e5f1283 2412 if (status & Y2_IS_CHK_TXA1)
40b01727 2413 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2414
1e5f1283 2415 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2416 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2417}
2418
2419static int sky2_poll(struct net_device *dev0, int *budget)
2420{
2421 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2422 int work_limit = min(dev0->quota, *budget);
2423 int work_done = 0;
2424 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2425
2426 if (unlikely(status & Y2_IS_ERROR))
2427 sky2_err_intr(hw, status);
2428
2429 if (status & Y2_IS_IRQ_PHY1)
2430 sky2_phy_intr(hw, 0);
2431
2432 if (status & Y2_IS_IRQ_PHY2)
2433 sky2_phy_intr(hw, 1);
cd28ab6a 2434
1e5f1283 2435 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2436 if (work_done < work_limit) {
2437 netif_rx_complete(dev0);
86fba634 2438
fe2a24df
SH		 2439 sky2_read32(hw, B0_Y2_SP_LISR);
2440 return 0;
2441 } else {
2442 *budget -= work_done;
2443 dev0->quota -= work_done;
1e5f1283 2444 return 1;
fe2a24df 2445 }
e07b1aa8
SH		 2446}
2447
7d12e780 2448static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2449{
2450 struct sky2_hw *hw = dev_id;
2451 struct net_device *dev0 = hw->dev[0];
2452 u32 status;
2453
2454 /* Reading this mask interrupts as side effect */
2455 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2456 if (status == 0 || status == ~0)
2457 return IRQ_NONE;
793b883e 2458
e07b1aa8
SH		 2459 prefetch(&hw->st_le[hw->st_idx]);
2460 if (likely(__netif_rx_schedule_prep(dev0)))
2461 __netif_rx_schedule(dev0);
793b883e 2462
cd28ab6a
SH		 2463 return IRQ_HANDLED;
2464}
2465
2466#ifdef CONFIG_NET_POLL_CONTROLLER
2467static void sky2_netpoll(struct net_device *dev)
2468{
2469 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2470 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2471
88d11360
SH		 2472 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2473 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2474}
2475#endif
2476
2477/* Chip internal frequency for clock calculations */
fb17358f 2478static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2479{
793b883e 2480 switch (hw->chip_id) {
cd28ab6a 2481 case CHIP_ID_YUKON_EC:
5a5b1ea0 2482 case CHIP_ID_YUKON_EC_U:
93745494 2483 case CHIP_ID_YUKON_EX:
fb17358f 2484 return 125; /* 125 Mhz */
cd28ab6a 2485 case CHIP_ID_YUKON_FE:
fb17358f 2486 return 100; /* 100 Mhz */
793b883e 2487 default: /* YUKON_XL */
fb17358f 2488 return 156; /* 156 Mhz */
cd28ab6a
SH		 2489 }
2490}
2491
fb17358f 2492static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2493{
fb17358f 2494 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2495}
2496
fb17358f 2497static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2498{
fb17358f 2499 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2500}
2501
fb17358f 2502
e3173832 2503static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2504{
b89165f2 2505 u8 t8;
cd28ab6a 2506
cd28ab6a 2507 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2508
cd28ab6a
SH		 2509 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2510 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2511 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2512 hw->chip_id);
cd28ab6a
SH		 2513 return -EOPNOTSUPP;
2514 }
2515
93745494
SH		 2516 if (hw->chip_id == CHIP_ID_YUKON_EX)
2517 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2518 "Please report success or failure to <netdev@vger.kernel.org>\n");
2519
2520 /* Make sure and enable all clocks */
2521 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2522 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2523
290d4de5
SH		 2524 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2525
2526 /* This rev is really old, and requires untested workarounds */
2527 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2528 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2529 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2530 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2531 return -EOPNOTSUPP;
2532 }
2533
e3173832
SH		 2534 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2535 hw->ports = 1;
2536 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2537 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2538 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2539 ++hw->ports;
2540 }
2541
2542 return 0;
2543}
2544
2545static void sky2_reset(struct sky2_hw *hw)
2546{
2547 u16 status;
2548 int i;
2549
cd28ab6a 2550 /* disable ASF */
4f44d8ba
SH		 2551 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2552 status = sky2_read16(hw, HCU_CCSR);
2553 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2554 HCU_CCSR_UC_STATE_MSK);
2555 sky2_write16(hw, HCU_CCSR, status);
2556 } else
2557 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2558 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2559
2560 /* do a SW reset */
2561 sky2_write8(hw, B0_CTST, CS_RST_SET);
2562 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2563
2564 /* clear PCI errors, if any */
56a645cc 2565 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2566
cd28ab6a 2567 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2568 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2569
cd28ab6a
SH		 2570
2571 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2572
2573 /* clear any PEX errors */
7bd656d1
SH		 2574 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2575 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2576
cd28ab6a 2577
ae306cca 2578 sky2_power_on(hw);
cd28ab6a
SH		 2579
2580 for (i = 0; i < hw->ports; i++) {
2581 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2582 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2583 }
2584
2585 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2586
793b883e
SH		 2587 /* Clear I2C IRQ noise */
2588 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2589
2590 /* turn off hardware timer (unused) */
2591 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2592 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2593
cd28ab6a
SH		 2594 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2595
69634ee7
SH		 2596 /* Turn off descriptor polling */
2597 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2598
2599 /* Turn off receive timestamp */
2600 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2601 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2602
2603 /* enable the Tx Arbiters */
2604 for (i = 0; i < hw->ports; i++)
2605 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2606
2607 /* Initialize ram interface */
2608 for (i = 0; i < hw->ports; i++) {
793b883e 2609 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2610
2611 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2612 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2613 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2614 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2615 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2616 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2617 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2618 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2619 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2620 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2621 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2622 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2623 }
2624
7bd656d1 2625 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2626
cd28ab6a 2627 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2628 sky2_gmac_reset(hw, i);
cd28ab6a 2629
cd28ab6a
SH		 2630 memset(hw->st_le, 0, STATUS_LE_BYTES);
2631 hw->st_idx = 0;
2632
2633 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2634 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2635
2636 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2637 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2638
2639 /* Set the list last index */
793b883e 2640 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2641
290d4de5
SH		 2642 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2643 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2644
290d4de5
SH		 2645 /* set Status-FIFO ISR watermark */
2646 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2647 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2648 else
2649 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2650
290d4de5 2651 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2652 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2653 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2654
793b883e 2655 /* enable status unit */
cd28ab6a
SH		 2656 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2657
2658 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2659 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2660 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2661}
2662
81906791
SH		 2663static void sky2_restart(struct work_struct *work)
2664{
2665 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2666 struct net_device *dev;
2667 int i, err;
2668
2669 dev_dbg(&hw->pdev->dev, "restarting\n");
2670
2671 del_timer_sync(&hw->idle_timer);
2672
2673 rtnl_lock();
2674 sky2_write32(hw, B0_IMSK, 0);
2675 sky2_read32(hw, B0_IMSK);
2676
2677 netif_poll_disable(hw->dev[0]);
2678
2679 for (i = 0; i < hw->ports; i++) {
2680 dev = hw->dev[i];
2681 if (netif_running(dev))
2682 sky2_down(dev);
2683 }
2684
2685 sky2_reset(hw);
2686 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2687 netif_poll_enable(hw->dev[0]);
2688
2689 for (i = 0; i < hw->ports; i++) {
2690 dev = hw->dev[i];
2691 if (netif_running(dev)) {
2692 err = sky2_up(dev);
2693 if (err) {
2694 printk(KERN_INFO PFX "%s: could not restart %d\n",
2695 dev->name, err);
2696 dev_close(dev);
2697 }
2698 }
2699 }
2700
2701 sky2_idle_start(hw);
2702
2703 rtnl_unlock();
2704}
2705
e3173832
SH		 2706static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2707{
2708 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2709}
2710
2711static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2712{
2713 const struct sky2_port *sky2 = netdev_priv(dev);
2714
2715 wol->supported = sky2_wol_supported(sky2->hw);
2716 wol->wolopts = sky2->wol;
2717}
2718
2719static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2720{
2721 struct sky2_port *sky2 = netdev_priv(dev);
2722 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2723
e3173832
SH		 2724 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2725 return -EOPNOTSUPP;
2726
2727 sky2->wol = wol->wolopts;
2728
2729 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2730 sky2_write32(hw, B0_CTST, sky2->wol
2731 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2732
2733 if (!netif_running(dev))
2734 sky2_wol_init(sky2);
cd28ab6a
SH		 2735 return 0;
2736}
2737
28bd181a 2738static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2739{
b89165f2
SH		 2740 if (sky2_is_copper(hw)) {
2741 u32 modes = SUPPORTED_10baseT_Half
2742 | SUPPORTED_10baseT_Full
2743 | SUPPORTED_100baseT_Half
2744 | SUPPORTED_100baseT_Full
2745 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2746
2747 if (hw->chip_id != CHIP_ID_YUKON_FE)
2748 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2749 | SUPPORTED_1000baseT_Full;
2750 return modes;
cd28ab6a 2751 } else
b89165f2
SH		 2752 return SUPPORTED_1000baseT_Half
2753 | SUPPORTED_1000baseT_Full
2754 | SUPPORTED_Autoneg
2755 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2756}
2757
793b883e 2758static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2759{
2760 struct sky2_port *sky2 = netdev_priv(dev);
2761 struct sky2_hw *hw = sky2->hw;
2762
2763 ecmd->transceiver = XCVR_INTERNAL;
2764 ecmd->supported = sky2_supported_modes(hw);
2765 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2766 if (sky2_is_copper(hw)) {
cd28ab6a 2767 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2768 | SUPPORTED_10baseT_Full
2769 | SUPPORTED_100baseT_Half
2770 | SUPPORTED_100baseT_Full
2771 | SUPPORTED_1000baseT_Half
2772 | SUPPORTED_1000baseT_Full
2773 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2774 ecmd->port = PORT_TP;
b89165f2
SH		 2775 ecmd->speed = sky2->speed;
2776 } else {
2777 ecmd->speed = SPEED_1000;
cd28ab6a 2778 ecmd->port = PORT_FIBRE;
b89165f2 2779 }
cd28ab6a
SH		 2780
2781 ecmd->advertising = sky2->advertising;
2782 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2783 ecmd->duplex = sky2->duplex;
2784 return 0;
2785}
2786
2787static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2788{
2789 struct sky2_port *sky2 = netdev_priv(dev);
2790 const struct sky2_hw *hw = sky2->hw;
2791 u32 supported = sky2_supported_modes(hw);
2792
2793 if (ecmd->autoneg == AUTONEG_ENABLE) {
2794 ecmd->advertising = supported;
2795 sky2->duplex = -1;
2796 sky2->speed = -1;
2797 } else {
2798 u32 setting;
2799
793b883e 2800 switch (ecmd->speed) {
cd28ab6a
SH		 2801 case SPEED_1000:
2802 if (ecmd->duplex == DUPLEX_FULL)
2803 setting = SUPPORTED_1000baseT_Full;
2804 else if (ecmd->duplex == DUPLEX_HALF)
2805 setting = SUPPORTED_1000baseT_Half;
2806 else
2807 return -EINVAL;
2808 break;
2809 case SPEED_100:
2810 if (ecmd->duplex == DUPLEX_FULL)
2811 setting = SUPPORTED_100baseT_Full;
2812 else if (ecmd->duplex == DUPLEX_HALF)
2813 setting = SUPPORTED_100baseT_Half;
2814 else
2815 return -EINVAL;
2816 break;
2817
2818 case SPEED_10:
2819 if (ecmd->duplex == DUPLEX_FULL)
2820 setting = SUPPORTED_10baseT_Full;
2821 else if (ecmd->duplex == DUPLEX_HALF)
2822 setting = SUPPORTED_10baseT_Half;
2823 else
2824 return -EINVAL;
2825 break;
2826 default:
2827 return -EINVAL;
2828 }
2829
2830 if ((setting & supported) == 0)
2831 return -EINVAL;
2832
2833 sky2->speed = ecmd->speed;
2834 sky2->duplex = ecmd->duplex;
2835 }
2836
2837 sky2->autoneg = ecmd->autoneg;
2838 sky2->advertising = ecmd->advertising;
2839
1b537565
SH		 2840 if (netif_running(dev))
2841 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2842
2843 return 0;
2844}
2845
2846static void sky2_get_drvinfo(struct net_device *dev,
2847 struct ethtool_drvinfo *info)
2848{
2849 struct sky2_port *sky2 = netdev_priv(dev);
2850
2851 strcpy(info->driver, DRV_NAME);
2852 strcpy(info->version, DRV_VERSION);
2853 strcpy(info->fw_version, "N/A");
2854 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2855}
2856
2857static const struct sky2_stat {
793b883e
SH		 2858 char name[ETH_GSTRING_LEN];
2859 u16 offset;
cd28ab6a
SH		 2860} sky2_stats[] = {
2861 { "tx_bytes", GM_TXO_OK_HI },
2862 { "rx_bytes", GM_RXO_OK_HI },
2863 { "tx_broadcast", GM_TXF_BC_OK },
2864 { "rx_broadcast", GM_RXF_BC_OK },
2865 { "tx_multicast", GM_TXF_MC_OK },
2866 { "rx_multicast", GM_RXF_MC_OK },
2867 { "tx_unicast", GM_TXF_UC_OK },
2868 { "rx_unicast", GM_RXF_UC_OK },
2869 { "tx_mac_pause", GM_TXF_MPAUSE },
2870 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2871 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2872 { "late_collision",GM_TXF_LAT_COL },
2873 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2874 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2875 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2876
d2604540 2877 { "rx_short", GM_RXF_SHT },
cd28ab6a 2878 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2879 { "rx_64_byte_packets", GM_RXF_64B },
2880 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2881 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2882 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2883 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2884 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2885 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2886 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2887 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2888 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2889 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2890
2891 { "tx_64_byte_packets", GM_TXF_64B },
2892 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2893 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2894 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2895 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2896 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2897 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2898 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2899};
2900
cd28ab6a
SH		 2901static u32 sky2_get_rx_csum(struct net_device *dev)
2902{
2903 struct sky2_port *sky2 = netdev_priv(dev);
2904
2905 return sky2->rx_csum;
2906}
2907
2908static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2909{
2910 struct sky2_port *sky2 = netdev_priv(dev);
2911
2912 sky2->rx_csum = data;
793b883e 2913
cd28ab6a
SH		 2914 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2915 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2916
2917 return 0;
2918}
2919
2920static u32 sky2_get_msglevel(struct net_device *netdev)
2921{
2922 struct sky2_port *sky2 = netdev_priv(netdev);
2923 return sky2->msg_enable;
2924}
2925
9a7ae0a9
SH		 2926static int sky2_nway_reset(struct net_device *dev)
2927{
2928 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2929
16ad91e1 2930 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2931 return -EINVAL;
2932
1b537565 2933 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2934
2935 return 0;
2936}
2937
793b883e 2938static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2939{
2940 struct sky2_hw *hw = sky2->hw;
2941 unsigned port = sky2->port;
2942 int i;
2943
2944 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2945 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2946 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2947 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2948
793b883e 2949 for (i = 2; i < count; i++)
cd28ab6a
SH		 2950 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2951}
2952
cd28ab6a
SH		 2953static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2954{
2955 struct sky2_port *sky2 = netdev_priv(netdev);
2956 sky2->msg_enable = value;
2957}
2958
2959static int sky2_get_stats_count(struct net_device *dev)
2960{
2961 return ARRAY_SIZE(sky2_stats);
2962}
2963
2964static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2965 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2966{
2967 struct sky2_port *sky2 = netdev_priv(dev);
2968
793b883e 2969 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2970}
2971
793b883e 2972static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2973{
2974 int i;
2975
2976 switch (stringset) {
2977 case ETH_SS_STATS:
2978 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2979 memcpy(data + i * ETH_GSTRING_LEN,
2980 sky2_stats[i].name, ETH_GSTRING_LEN);
2981 break;
2982 }
2983}
2984
cd28ab6a
SH		 2985static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2986{
2987 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2988 return &sky2->net_stats;
2989}
2990
2991static int sky2_set_mac_address(struct net_device *dev, void *p)
2992{
2993 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2994 struct sky2_hw *hw = sky2->hw;
2995 unsigned port = sky2->port;
2996 const struct sockaddr *addr = p;
cd28ab6a
SH		 2997
2998 if (!is_valid_ether_addr(addr->sa_data))
2999 return -EADDRNOTAVAIL;
3000
cd28ab6a 3001 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3002 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3003 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3004 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3005 dev->dev_addr, ETH_ALEN);
1b537565 3006
a8ab1ec0
SH		 3007 /* virtual address for data */
3008 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3009
3010 /* physical address: used for pause frames */
3011 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3012
3013 return 0;
cd28ab6a
SH		 3014}
3015
a052b52f
SH		 3016static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3017{
3018 u32 bit;
3019
3020 bit = ether_crc(ETH_ALEN, addr) & 63;
3021 filter[bit >> 3] |= 1 << (bit & 7);
3022}
3023
cd28ab6a
SH		 3024static void sky2_set_multicast(struct net_device *dev)
3025{
3026 struct sky2_port *sky2 = netdev_priv(dev);
3027 struct sky2_hw *hw = sky2->hw;
3028 unsigned port = sky2->port;
3029 struct dev_mc_list *list = dev->mc_list;
3030 u16 reg;
3031 u8 filter[8];
a052b52f
SH		 3032 int rx_pause;
3033 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3034
a052b52f 3035 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3036 memset(filter, 0, sizeof(filter));
3037
3038 reg = gma_read16(hw, port, GM_RX_CTRL);
3039 reg |= GM_RXCR_UCF_ENA;
3040
d571b694 3041 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3042 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3043 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3044 memset(filter, 0xff, sizeof(filter));
a052b52f 3045 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3046 reg &= ~GM_RXCR_MCF_ENA;
3047 else {
3048 int i;
3049 reg |= GM_RXCR_MCF_ENA;
3050
a052b52f
SH		 3051 if (rx_pause)
3052 sky2_add_filter(filter, pause_mc_addr);
3053
3054 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3055 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3056 }
3057
cd28ab6a 3058 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3059 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3060 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3061 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3062 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3063 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3064 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3065 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3066
3067 gma_write16(hw, port, GM_RX_CTRL, reg);
3068}
3069
3070/* Can have one global because blinking is controlled by
3071 * ethtool and that is always under RTNL mutex
3072 */
91c86df5 3073static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3074{
793b883e
SH		 3075 u16 pg;
3076
793b883e
SH		 3077 switch (hw->chip_id) {
3078 case CHIP_ID_YUKON_XL:
3079 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3080 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3081 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3082 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3083 PHY_M_LEDC_INIT_CTRL(7) |
3084 PHY_M_LEDC_STA1_CTRL(7) |
3085 PHY_M_LEDC_STA0_CTRL(7))
3086 : 0);
3087
3088 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3089 break;
3090
3091 default:
3092 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3093 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3094 on ? PHY_M_LED_ALL : 0);
793b883e 3095 }
cd28ab6a
SH		 3096}
3097
3098/* blink LED's for finding board */
3099static int sky2_phys_id(struct net_device *dev, u32 data)
3100{
3101 struct sky2_port *sky2 = netdev_priv(dev);
3102 struct sky2_hw *hw = sky2->hw;
3103 unsigned port = sky2->port;
793b883e 3104 u16 ledctrl, ledover = 0;
cd28ab6a 3105 long ms;
91c86df5 3106 int interrupted;
cd28ab6a
SH		 3107 int onoff = 1;
3108
793b883e 3109 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3110 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3111 else
3112 ms = data * 1000;
3113
3114 /* save initial values */
e07b1aa8 3115 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3116 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3117 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3118 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3119 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3120 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3121 } else {
3122 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3123 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3124 }
cd28ab6a 3125
91c86df5
SH		 3126 interrupted = 0;
3127 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3128 sky2_led(hw, port, onoff);
3129 onoff = !onoff;
3130
e07b1aa8 3131 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3132 interrupted = msleep_interruptible(250);
e07b1aa8 3133 spin_lock_bh(&sky2->phy_lock);
91c86df5 3134
cd28ab6a
SH		 3135 ms -= 250;
3136 }
3137
3138 /* resume regularly scheduled programming */
793b883e
SH		 3139 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3140 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3141 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3142 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3143 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3144 } else {
3145 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3146 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3147 }
e07b1aa8 3148 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3149
3150 return 0;
3151}
3152
3153static void sky2_get_pauseparam(struct net_device *dev,
3154 struct ethtool_pauseparam *ecmd)
3155{
3156 struct sky2_port *sky2 = netdev_priv(dev);
3157
16ad91e1
SH		 3158 switch (sky2->flow_mode) {
3159 case FC_NONE:
3160 ecmd->tx_pause = ecmd->rx_pause = 0;
3161 break;
3162 case FC_TX:
3163 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3164 break;
3165 case FC_RX:
3166 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3167 break;
3168 case FC_BOTH:
3169 ecmd->tx_pause = ecmd->rx_pause = 1;
3170 }
3171
cd28ab6a
SH		 3172 ecmd->autoneg = sky2->autoneg;
3173}
3174
3175static int sky2_set_pauseparam(struct net_device *dev,
3176 struct ethtool_pauseparam *ecmd)
3177{
3178 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3179
3180 sky2->autoneg = ecmd->autoneg;
16ad91e1 3181 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3182
16ad91e1
SH		 3183 if (netif_running(dev))
3184 sky2_phy_reinit(sky2);
cd28ab6a 3185
2eaba1a2 3186 return 0;
cd28ab6a
SH		 3187}
3188
fb17358f
SH		 3189static int sky2_get_coalesce(struct net_device *dev,
3190 struct ethtool_coalesce *ecmd)
3191{
3192 struct sky2_port *sky2 = netdev_priv(dev);
3193 struct sky2_hw *hw = sky2->hw;
3194
3195 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3196 ecmd->tx_coalesce_usecs = 0;
3197 else {
3198 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3199 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3200 }
3201 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3202
3203 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3204 ecmd->rx_coalesce_usecs = 0;
3205 else {
3206 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3207 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3208 }
3209 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3210
3211 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3212 ecmd->rx_coalesce_usecs_irq = 0;
3213 else {
3214 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3215 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3216 }
3217
3218 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3219
3220 return 0;
3221}
3222
3223/* Note: this affect both ports */
3224static int sky2_set_coalesce(struct net_device *dev,
3225 struct ethtool_coalesce *ecmd)
3226{
3227 struct sky2_port *sky2 = netdev_priv(dev);
3228 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3229 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3230
77b3d6a2
SH		 3231 if (ecmd->tx_coalesce_usecs > tmax ||
3232 ecmd->rx_coalesce_usecs > tmax ||
3233 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3234 return -EINVAL;
3235
ff81fbbe 3236 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3237 return -EINVAL;
ff81fbbe 3238 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3239 return -EINVAL;
ff81fbbe 3240 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3241 return -EINVAL;
3242
3243 if (ecmd->tx_coalesce_usecs == 0)
3244 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3245 else {
3246 sky2_write32(hw, STAT_TX_TIMER_INI,
3247 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3248 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3249 }
3250 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3251
3252 if (ecmd->rx_coalesce_usecs == 0)
3253 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3254 else {
3255 sky2_write32(hw, STAT_LEV_TIMER_INI,
3256 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3257 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3258 }
3259 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3260
3261 if (ecmd->rx_coalesce_usecs_irq == 0)
3262 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3263 else {
d28d4870 3264 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3265 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3266 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3267 }
3268 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3269 return 0;
3270}
3271
793b883e
SH		 3272static void sky2_get_ringparam(struct net_device *dev,
3273 struct ethtool_ringparam *ering)
3274{
3275 struct sky2_port *sky2 = netdev_priv(dev);
3276
3277 ering->rx_max_pending = RX_MAX_PENDING;
3278 ering->rx_mini_max_pending = 0;
3279 ering->rx_jumbo_max_pending = 0;
3280 ering->tx_max_pending = TX_RING_SIZE - 1;
3281
3282 ering->rx_pending = sky2->rx_pending;
3283 ering->rx_mini_pending = 0;
3284 ering->rx_jumbo_pending = 0;
3285 ering->tx_pending = sky2->tx_pending;
3286}
3287
3288static int sky2_set_ringparam(struct net_device *dev,
3289 struct ethtool_ringparam *ering)
3290{
3291 struct sky2_port *sky2 = netdev_priv(dev);
3292 int err = 0;
3293
3294 if (ering->rx_pending > RX_MAX_PENDING ||
3295 ering->rx_pending < 8 ||
3296 ering->tx_pending < MAX_SKB_TX_LE ||
3297 ering->tx_pending > TX_RING_SIZE - 1)
3298 return -EINVAL;
3299
3300 if (netif_running(dev))
3301 sky2_down(dev);
3302
3303 sky2->rx_pending = ering->rx_pending;
3304 sky2->tx_pending = ering->tx_pending;
3305
1b537565 3306 if (netif_running(dev)) {
793b883e 3307 err = sky2_up(dev);
1b537565
SH		 3308 if (err)
3309 dev_close(dev);
6ed995bb
SH		 3310 else
3311 sky2_set_multicast(dev);
1b537565 3312 }
793b883e
SH		 3313
3314 return err;
3315}
3316
793b883e
SH		 3317static int sky2_get_regs_len(struct net_device *dev)
3318{
6e4cbb34 3319 return 0x4000;
793b883e
SH		 3320}
3321
3322/*
3323 * Returns copy of control register region
6e4cbb34 3324 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3325 */
3326static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3327 void *p)
3328{
3329 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3330 const void __iomem *io = sky2->hw->regs;
793b883e 3331
6e4cbb34 3332 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3333 regs->version = 1;
6e4cbb34 3334 memset(p, 0, regs->len);
793b883e 3335
6e4cbb34
SH		 3336 memcpy_fromio(p, io, B3_RAM_ADDR);
3337
3338 memcpy_fromio(p + B3_RI_WTO_R1,
3339 io + B3_RI_WTO_R1,
3340 regs->len - B3_RI_WTO_R1);
793b883e 3341}
cd28ab6a 3342
b628ed98
SH		 3343/* In order to do Jumbo packets on these chips, need to turn off the
3344 * transmit store/forward. Therefore checksum offload won't work.
3345 */
3346static int no_tx_offload(struct net_device *dev)
3347{
3348 const struct sky2_port *sky2 = netdev_priv(dev);
3349 const struct sky2_hw *hw = sky2->hw;
3350
3351 return dev->mtu > ETH_DATA_LEN &&
3352 (hw->chip_id == CHIP_ID_YUKON_EX
3353 || hw->chip_id == CHIP_ID_YUKON_EC_U);
3354}
3355
3356static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3357{
3358 if (data && no_tx_offload(dev))
3359 return -EINVAL;
3360
3361 return ethtool_op_set_tx_csum(dev, data);
3362}
3363
3364
3365static int sky2_set_tso(struct net_device *dev, u32 data)
3366{
3367 if (data && no_tx_offload(dev))
3368 return -EINVAL;
3369
3370 return ethtool_op_set_tso(dev, data);
3371}
3372
7282d491 3373static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3374 .get_settings = sky2_get_settings,
3375 .set_settings = sky2_set_settings,
e3173832
SH		 3376 .get_drvinfo = sky2_get_drvinfo,
3377 .get_wol = sky2_get_wol,
3378 .set_wol = sky2_set_wol,
793b883e
SH		 3379 .get_msglevel = sky2_get_msglevel,
3380 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3381 .nway_reset = sky2_nway_reset,
793b883e
SH		 3382 .get_regs_len = sky2_get_regs_len,
3383 .get_regs = sky2_get_regs,
3384 .get_link = ethtool_op_get_link,
3385 .get_sg = ethtool_op_get_sg,
3386 .set_sg = ethtool_op_set_sg,
3387 .get_tx_csum = ethtool_op_get_tx_csum,
b628ed98 3388 .set_tx_csum = sky2_set_tx_csum,
793b883e 3389 .get_tso = ethtool_op_get_tso,
b628ed98 3390 .set_tso = sky2_set_tso,
793b883e
SH		 3391 .get_rx_csum = sky2_get_rx_csum,
3392 .set_rx_csum = sky2_set_rx_csum,
3393 .get_strings = sky2_get_strings,
fb17358f
SH		 3394 .get_coalesce = sky2_get_coalesce,
3395 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3396 .get_ringparam = sky2_get_ringparam,
3397 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3398 .get_pauseparam = sky2_get_pauseparam,
3399 .set_pauseparam = sky2_set_pauseparam,
793b883e 3400 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3401 .get_stats_count = sky2_get_stats_count,
3402 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3403 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3404};
3405
3406/* Initialize network device */
3407static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3408 unsigned port,
3409 int highmem, int wol)
cd28ab6a
SH		 3410{
3411 struct sky2_port *sky2;
3412 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3413
3414 if (!dev) {
b02a9258 3415 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3416 return NULL;
3417 }
3418
3419 SET_MODULE_OWNER(dev);
3420 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3421 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3422 dev->open = sky2_up;
3423 dev->stop = sky2_down;
ef743d33 3424 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3425 dev->hard_start_xmit = sky2_xmit_frame;
3426 dev->get_stats = sky2_get_stats;
3427 dev->set_multicast_list = sky2_set_multicast;
3428 dev->set_mac_address = sky2_set_mac_address;
3429 dev->change_mtu = sky2_change_mtu;
3430 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3431 dev->tx_timeout = sky2_tx_timeout;
3432 dev->watchdog_timeo = TX_WATCHDOG;
3433 if (port == 0)
3434 dev->poll = sky2_poll;
3435 dev->weight = NAPI_WEIGHT;
3436#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3437 /* Network console (only works on port 0)
3438 * because netpoll makes assumptions about NAPI
3439 */
3440 if (port == 0)
3441 dev->poll_controller = sky2_netpoll;
cd28ab6a 3442#endif
cd28ab6a
SH		 3443
3444 sky2 = netdev_priv(dev);
3445 sky2->netdev = dev;
3446 sky2->hw = hw;
3447 sky2->msg_enable = netif_msg_init(debug, default_msg);
3448
cd28ab6a
SH		 3449 /* Auto speed and flow control */
3450 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3451 sky2->flow_mode = FC_BOTH;
3452
cd28ab6a
SH		 3453 sky2->duplex = -1;
3454 sky2->speed = -1;
3455 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3456 sky2->rx_csum = 1;
e3173832 3457 sky2->wol = wol;
75d070c5 3458
e07b1aa8 3459 spin_lock_init(&sky2->phy_lock);
793b883e 3460 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3461 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3462
3463 hw->dev[port] = dev;
3464
3465 sky2->port = port;
3466
4a50a876 3467 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3468 if (highmem)
3469 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3470
d1f13708
SH		 3471#ifdef SKY2_VLAN_TAG_USED
3472 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3473 dev->vlan_rx_register = sky2_vlan_rx_register;
3474 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3475#endif
3476
cd28ab6a 3477 /* read the mac address */
793b883e 3478 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3479 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3480
3481 /* device is off until link detection */
3482 netif_carrier_off(dev);
3483 netif_stop_queue(dev);
3484
3485 return dev;
3486}
3487
28bd181a 3488static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3489{
3490 const struct sky2_port *sky2 = netdev_priv(dev);
3491
3492 if (netif_msg_probe(sky2))
3493 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3494 dev->name,
3495 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3496 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3497}
3498
fb2690a9 3499/* Handle software interrupt used during MSI test */
7d12e780 3500static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3501{
3502 struct sky2_hw *hw = dev_id;
3503 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3504
3505 if (status == 0)
3506 return IRQ_NONE;
3507
3508 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3509 hw->msi = 1;
fb2690a9
SH		 3510 wake_up(&hw->msi_wait);
3511 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3512 }
3513 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3514
3515 return IRQ_HANDLED;
3516}
3517
3518/* Test interrupt path by forcing a a software IRQ */
3519static int __devinit sky2_test_msi(struct sky2_hw *hw)
3520{
3521 struct pci_dev *pdev = hw->pdev;
3522 int err;
3523
bb507fe1
SH		 3524 init_waitqueue_head (&hw->msi_wait);
3525
fb2690a9
SH		 3526 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3527
b0a20ded 3528 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3529 if (err) {
b02a9258 3530 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3531 return err;
3532 }
3533
fb2690a9 3534 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3535 sky2_read8(hw, B0_CTST);
fb2690a9 3536
b0a20ded 3537 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3538
b0a20ded 3539 if (!hw->msi) {
fb2690a9 3540 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3541 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3542 "switching to INTx mode.\n");
fb2690a9
SH		 3543
3544 err = -EOPNOTSUPP;
3545 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3546 }
3547
3548 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3549 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3550
3551 free_irq(pdev->irq, hw);
3552
3553 return err;
3554}
3555
e3173832
SH		 3556static int __devinit pci_wake_enabled(struct pci_dev *dev)
3557{
3558 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3559 u16 value;
3560
3561 if (!pm)
3562 return 0;
3563 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3564 return 0;
3565 return value & PCI_PM_CTRL_PME_ENABLE;
3566}
3567
cd28ab6a
SH		 3568static int __devinit sky2_probe(struct pci_dev *pdev,
3569 const struct pci_device_id *ent)
3570{
7f60c64b 3571 struct net_device *dev;
cd28ab6a 3572 struct sky2_hw *hw;
e3173832 3573 int err, using_dac = 0, wol_default;
cd28ab6a 3574
793b883e
SH		 3575 err = pci_enable_device(pdev);
3576 if (err) {
b02a9258 3577 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3578 goto err_out;
3579 }
3580
44a1d2e5
SH		 3581 /* Some Gigabyte motherboards have 88e8056 but cause problems
3582 * There is some unresolved hardware related problem that causes
3583 * descriptor errors and receive data corruption.
3584 */
3585 if (pdev->vendor == PCI_VENDOR_ID_MARVELL &&
3586 pdev->device == 0x4364 && pdev->subsystem_vendor == 0x1458) {
3587 dev_err(&pdev->dev,
3588 "88E8056 on Gigabyte motherboards not supported\n");
3589 goto err_out_disable;
3590 }
3591
793b883e
SH		 3592 err = pci_request_regions(pdev, DRV_NAME);
3593 if (err) {
b02a9258 3594 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 3595 goto err_out_disable;
cd28ab6a
SH		 3596 }
3597
3598 pci_set_master(pdev);
3599
d1f3d4dd
SH		 3600 if (sizeof(dma_addr_t) > sizeof(u32) &&
3601 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3602 using_dac = 1;
3603 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3604 if (err < 0) {
b02a9258
SH		 3605 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3606 "for consistent allocations\n");
d1f3d4dd
SH		 3607 goto err_out_free_regions;
3608 }
d1f3d4dd 3609 } else {
cd28ab6a
SH		 3610 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3611 if (err) {
b02a9258 3612 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3613 goto err_out_free_regions;
3614 }
3615 }
d1f3d4dd 3616
e3173832
SH		 3617 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3618
cd28ab6a 3619 err = -ENOMEM;
6aad85d6 3620 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3621 if (!hw) {
b02a9258 3622 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3623 goto err_out_free_regions;
3624 }
3625
cd28ab6a 3626 hw->pdev = pdev;
cd28ab6a
SH		 3627
3628 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3629 if (!hw->regs) {
b02a9258 3630 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3631 goto err_out_free_hw;
3632 }
3633
56a645cc 3634#ifdef __BIG_ENDIAN
f65b138c
SH		 3635 /* The sk98lin vendor driver uses hardware byte swapping but
3636 * this driver uses software swapping.
3637 */
56a645cc
SH		 3638 {
3639 u32 reg;
56a645cc 3640 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3641 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3642 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3643 }
3644#endif
3645
08c06d8a
SH		 3646 /* ring for status responses */
3647 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3648 &hw->st_dma);
3649 if (!hw->st_le)
3650 goto err_out_iounmap;
3651
e3173832 3652 err = sky2_init(hw);
cd28ab6a 3653 if (err)
793b883e 3654 goto err_out_iounmap;
cd28ab6a 3655
b02a9258 3656 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3657 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3658 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3659 hw->chip_id, hw->chip_rev);
cd28ab6a 3660
e3173832
SH		 3661 sky2_reset(hw);
3662
3663 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3664 if (!dev) {
3665 err = -ENOMEM;
cd28ab6a 3666 goto err_out_free_pci;
7f60c64b 3667 }
cd28ab6a 3668
9fa1b1f3
SH		 3669 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3670 err = sky2_test_msi(hw);
3671 if (err == -EOPNOTSUPP)
3672 pci_disable_msi(pdev);
3673 else if (err)
3674 goto err_out_free_netdev;
3675 }
3676
793b883e
SH		 3677 err = register_netdev(dev);
3678 if (err) {
b02a9258 3679 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 3680 goto err_out_free_netdev;
3681 }
3682
b0a20ded
SH		 3683 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3684 dev->name, hw);
9fa1b1f3 3685 if (err) {
b02a9258 3686 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 3687 goto err_out_unregister;
3688 }
3689 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3690
cd28ab6a
SH		 3691 sky2_show_addr(dev);
3692
7f60c64b 3693 if (hw->ports > 1) {
3694 struct net_device *dev1;
3695
e3173832 3696 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 3697 if (!dev1)
3698 dev_warn(&pdev->dev, "allocation for second device failed\n");
3699 else if ((err = register_netdev(dev1))) {
3700 dev_warn(&pdev->dev,
3701 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 3702 hw->dev[1] = NULL;
3703 free_netdev(dev1);
b02a9258
SH		 3704 } else
3705 sky2_show_addr(dev1);
cd28ab6a
SH		 3706 }
3707
01bd7564 3708 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
81906791
SH		 3709 INIT_WORK(&hw->restart_work, sky2_restart);
3710
eb35cf60 3711 sky2_idle_start(hw);
d27ed387 3712
793b883e
SH		 3713 pci_set_drvdata(pdev, hw);
3714
cd28ab6a
SH		 3715 return 0;
3716
793b883e 3717err_out_unregister:
b0a20ded
SH		 3718 if (hw->msi)
3719 pci_disable_msi(pdev);
793b883e 3720 unregister_netdev(dev);
cd28ab6a
SH		 3721err_out_free_netdev:
3722 free_netdev(dev);
cd28ab6a 3723err_out_free_pci:
793b883e 3724 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3725 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3726err_out_iounmap:
3727 iounmap(hw->regs);
3728err_out_free_hw:
3729 kfree(hw);
3730err_out_free_regions:
3731 pci_release_regions(pdev);
44a1d2e5 3732err_out_disable:
cd28ab6a 3733 pci_disable_device(pdev);
cd28ab6a
SH		 3734err_out:
3735 return err;
3736}
3737
3738static void __devexit sky2_remove(struct pci_dev *pdev)
3739{
793b883e 3740 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3741 struct net_device *dev0, *dev1;
3742
793b883e 3743 if (!hw)
cd28ab6a
SH		 3744 return;
3745
d27ed387
SH		 3746 del_timer_sync(&hw->idle_timer);
3747
81906791
SH		 3748 flush_scheduled_work();
3749
d27ed387 3750 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3751 synchronize_irq(hw->pdev->irq);
3752
cd28ab6a 3753 dev0 = hw->dev[0];
793b883e
SH		 3754 dev1 = hw->dev[1];
3755 if (dev1)
3756 unregister_netdev(dev1);
cd28ab6a
SH		 3757 unregister_netdev(dev0);
3758
ae306cca
SH		 3759 sky2_power_aux(hw);
3760
cd28ab6a 3761 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3762 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3763 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3764
3765 free_irq(pdev->irq, hw);
b0a20ded
SH		 3766 if (hw->msi)
3767 pci_disable_msi(pdev);
793b883e 3768 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3769 pci_release_regions(pdev);
3770 pci_disable_device(pdev);
793b883e 3771
cd28ab6a
SH		 3772 if (dev1)
3773 free_netdev(dev1);
3774 free_netdev(dev0);
3775 iounmap(hw->regs);
3776 kfree(hw);
5afa0a9c 3777
cd28ab6a
SH		 3778 pci_set_drvdata(pdev, NULL);
3779}
3780
3781#ifdef CONFIG_PM
3782static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3783{
793b883e 3784 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 3785 int i, wol = 0;
cd28ab6a 3786
eb35cf60 3787 del_timer_sync(&hw->idle_timer);
6a5706b9 3788 netif_poll_disable(hw->dev[0]);
eb35cf60 3789
f05267e7 3790 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3791 struct net_device *dev = hw->dev[i];
e3173832 3792 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3793
e3173832 3794 if (netif_running(dev))
5afa0a9c 3795 sky2_down(dev);
e3173832
SH		 3796
3797 if (sky2->wol)
3798 sky2_wol_init(sky2);
3799
3800 wol |= sky2->wol;
cd28ab6a
SH		 3801 }
3802
8ab8fca2 3803 sky2_write32(hw, B0_IMSK, 0);
ae306cca 3804 sky2_power_aux(hw);
e3173832 3805
d374c1c1 3806 pci_save_state(pdev);
e3173832 3807 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 3808 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3809
2ccc99b7 3810 return 0;
cd28ab6a
SH		 3811}
3812
3813static int sky2_resume(struct pci_dev *pdev)
3814{
793b883e 3815 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3816 int i, err;
cd28ab6a 3817
ae306cca
SH		 3818 err = pci_set_power_state(pdev, PCI_D0);
3819 if (err)
3820 goto out;
3821
3822 err = pci_restore_state(pdev);
3823 if (err)
3824 goto out;
3825
cd28ab6a 3826 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 3827
3828 /* Re-enable all clocks */
3829 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3830 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3831
e3173832 3832 sky2_reset(hw);
cd28ab6a 3833
8ab8fca2
SH		 3834 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3835
f05267e7 3836 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3837 struct net_device *dev = hw->dev[i];
6a5706b9 3838 if (netif_running(dev)) {
08c06d8a
SH		 3839 err = sky2_up(dev);
3840 if (err) {
3841 printk(KERN_ERR PFX "%s: could not up: %d\n",
3842 dev->name, err);
3843 dev_close(dev);
eb35cf60 3844 goto out;
5afa0a9c 3845 }
cd28ab6a
SH		 3846 }
3847 }
eb35cf60 3848
6a5706b9 3849 netif_poll_enable(hw->dev[0]);
eb35cf60 3850 sky2_idle_start(hw);
ae306cca 3851 return 0;
08c06d8a 3852out:
b02a9258 3853 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 3854 pci_disable_device(pdev);
08c06d8a 3855 return err;
cd28ab6a
SH		 3856}
3857#endif
3858
e3173832
SH		 3859static void sky2_shutdown(struct pci_dev *pdev)
3860{
3861 struct sky2_hw *hw = pci_get_drvdata(pdev);
3862 int i, wol = 0;
3863
3864 del_timer_sync(&hw->idle_timer);
3865 netif_poll_disable(hw->dev[0]);
3866
3867 for (i = 0; i < hw->ports; i++) {
3868 struct net_device *dev = hw->dev[i];
3869 struct sky2_port *sky2 = netdev_priv(dev);
3870
3871 if (sky2->wol) {
3872 wol = 1;
3873 sky2_wol_init(sky2);
3874 }
3875 }
3876
3877 if (wol)
3878 sky2_power_aux(hw);
3879
3880 pci_enable_wake(pdev, PCI_D3hot, wol);
3881 pci_enable_wake(pdev, PCI_D3cold, wol);
3882
3883 pci_disable_device(pdev);
3884 pci_set_power_state(pdev, PCI_D3hot);
3885
3886}
3887
cd28ab6a 3888static struct pci_driver sky2_driver = {
793b883e
SH		 3889 .name = DRV_NAME,
3890 .id_table = sky2_id_table,
3891 .probe = sky2_probe,
3892 .remove = __devexit_p(sky2_remove),
cd28ab6a 3893#ifdef CONFIG_PM
793b883e
SH		 3894 .suspend = sky2_suspend,
3895 .resume = sky2_resume,
cd28ab6a 3896#endif
e3173832 3897 .shutdown = sky2_shutdown,
cd28ab6a
SH		 3898};
3899
3900static int __init sky2_init_module(void)
3901{
50241c4c 3902 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3903}
3904
3905static void __exit sky2_cleanup_module(void)
3906{
3907 pci_unregister_driver(&sky2_driver);
3908}
3909
3910module_init(sky2_init_module);
3911module_exit(sky2_cleanup_module);
3912
3913MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 3914MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 3915MODULE_LICENSE("GPL");
5f4f9dc1 3916MODULE_VERSION(DRV_VERSION);
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