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sky2: avoid reserved regions on ethtool reg dump
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
93cd791e 53#define DRV_VERSION "1.14"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 66#define RX_SKB_ALIGN 8
22e11703 67#define RX_BUF_WRITE 16
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
cb5d9547
SH		 80#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
cd28ab6a 82static const u32 default_msg =
793b883e
SH		 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 86
793b883e 87static int debug = -1; /* defaults above */
cd28ab6a
SH		 88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
14d0263f 91static int copybreak __read_mostly = 128;
bdb5c58e
SH		 92module_param(copybreak, int, 0);
93MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
fb2690a9
SH		 95static int disable_msi = 0;
96module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
e561a83b 99static int idle_timeout = 0;
01bd7564 100module_param(idle_timeout, int, 0);
e561a83b 101MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 102
cd28ab6a 103static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
78f0b62d 133// { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 134 { 0 }
135};
793b883e 136
cd28ab6a
SH		 137MODULE_DEVICE_TABLE(pci, sky2_id_table);
138
139/* Avoid conditionals by using array */
140static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
141static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 142static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 143
92f965e8
SH		 144/* This driver supports yukon2 chipset only */
145static const char *yukon2_name[] = {
146 "XL", /* 0xb3 */
147 "EC Ultra", /* 0xb4 */
93745494 148 "Extreme", /* 0xb5 */
92f965e8
SH		 149 "EC", /* 0xb6 */
150 "FE", /* 0xb7 */
793b883e
SH		 151};
152
793b883e 153/* Access to external PHY */
ef743d33 154static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 155{
156 int i;
157
158 gma_write16(hw, port, GM_SMI_DATA, val);
159 gma_write16(hw, port, GM_SMI_CTRL,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161
162 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 163 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 164 return 0;
793b883e 165 udelay(1);
cd28ab6a 166 }
ef743d33 167
793b883e 168 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 169 return -ETIMEDOUT;
cd28ab6a
SH		 170}
171
ef743d33 172static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 173{
174 int i;
175
793b883e 176 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 177 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
178
179 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 180 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
181 *val = gma_read16(hw, port, GM_SMI_DATA);
182 return 0;
183 }
184
793b883e 185 udelay(1);
cd28ab6a
SH		 186 }
187
ef743d33
SH		 188 return -ETIMEDOUT;
189}
190
191static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
192{
193 u16 v;
194
195 if (__gm_phy_read(hw, port, reg, &v) != 0)
196 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
197 return v;
cd28ab6a
SH		 198}
199
5afa0a9c 200
ae306cca
SH		 201static void sky2_power_on(struct sky2_hw *hw)
202{
203 /* switch power to VCC (WA for VAUX problem) */
204 sky2_write8(hw, B0_POWER_CTRL,
205 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 206
ae306cca
SH		 207 /* disable Core Clock Division, */
208 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 209
ae306cca
SH		 210 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
211 /* enable bits are inverted */
212 sky2_write8(hw, B2_Y2_CLK_GATE,
213 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
214 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
215 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
216 else
217 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 218
93745494 219 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
ae306cca 220 u32 reg1;
5afa0a9c 221
ae306cca
SH		 222 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
223 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
224 reg1 &= P_ASPM_CONTROL_MSK;
225 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
226 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
5afa0a9c 227 }
ae306cca 228}
5afa0a9c 229
ae306cca
SH		 230static void sky2_power_aux(struct sky2_hw *hw)
231{
232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
233 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
234 else
235 /* enable bits are inverted */
236 sky2_write8(hw, B2_Y2_CLK_GATE,
237 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
238 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
239 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
240
241 /* switch power to VAUX */
242 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
243 sky2_write8(hw, B0_POWER_CTRL,
244 (PC_VAUX_ENA | PC_VCC_ENA |
245 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 246}
247
d3bcfbeb 248static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 249{
250 u16 reg;
251
252 /* disable all GMAC IRQ's */
253 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
254 /* disable PHY IRQs */
255 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 256
cd28ab6a
SH		 257 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
258 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
259 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
260 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
261
262 reg = gma_read16(hw, port, GM_RX_CTRL);
263 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
264 gma_write16(hw, port, GM_RX_CTRL, reg);
265}
266
16ad91e1
SH		 267/* flow control to advertise bits */
268static const u16 copper_fc_adv[] = {
269 [FC_NONE] = 0,
270 [FC_TX] = PHY_M_AN_ASP,
271 [FC_RX] = PHY_M_AN_PC,
272 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
273};
274
275/* flow control to advertise bits when using 1000BaseX */
276static const u16 fiber_fc_adv[] = {
277 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
278 [FC_TX] = PHY_M_P_ASYM_MD_X,
279 [FC_RX] = PHY_M_P_SYM_MD_X,
280 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
281};
282
283/* flow control to GMA disable bits */
284static const u16 gm_fc_disable[] = {
285 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
286 [FC_TX] = GM_GPCR_FC_RX_DIS,
287 [FC_RX] = GM_GPCR_FC_TX_DIS,
288 [FC_BOTH] = 0,
289};
290
291
cd28ab6a
SH		 292static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
293{
294 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 295 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 296
93745494
SH		 297 if (sky2->autoneg == AUTONEG_ENABLE
298 && !(hw->chip_id == CHIP_ID_YUKON_XL
299 || hw->chip_id == CHIP_ID_YUKON_EC_U
300 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 301 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
302
303 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 304 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 305 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
306
53419c68 307 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 308 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 309 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 310 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
311 else
53419c68
SH		 312 /* set master & slave downshift counter to 1x */
313 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 314
315 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
316 }
317
318 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 319 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 320 if (hw->chip_id == CHIP_ID_YUKON_FE) {
321 /* enable automatic crossover */
322 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
323 } else {
324 /* disable energy detect */
325 ctrl &= ~PHY_M_PC_EN_DET_MSK;
326
327 /* enable automatic crossover */
328 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
329
53419c68 330 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494
SH		 331 if (sky2->autoneg == AUTONEG_ENABLE
332 && (hw->chip_id == CHIP_ID_YUKON_XL
333 || hw->chip_id == CHIP_ID_YUKON_EC_U
334 || hw->chip_id == CHIP_ID_YUKON_EX)) {
53419c68 335 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 336 ctrl &= ~PHY_M_PC_DSC_MSK;
337 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
338 }
339 }
cd28ab6a
SH		 340 } else {
341 /* workaround for deviation #4.88 (CRC errors) */
342 /* disable Automatic Crossover */
343
344 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 345 }
cd28ab6a 346
b89165f2
SH		 347 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
348
349 /* special setup for PHY 88E1112 Fiber */
350 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
351 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 352
b89165f2
SH		 353 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
354 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
355 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
356 ctrl &= ~PHY_M_MAC_MD_MSK;
357 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
358 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
359
360 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 361 /* select page 1 to access Fiber registers */
362 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 363
364 /* for SFP-module set SIGDET polarity to low */
365 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
366 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 367 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 368 }
b89165f2
SH		 369
370 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 371 }
372
7800fddc 373 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 374 ct1000 = 0;
375 adv = PHY_AN_CSMA;
2eaba1a2 376 reg = 0;
cd28ab6a
SH		 377
378 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 379 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 380 if (sky2->advertising & ADVERTISED_1000baseT_Full)
381 ct1000 |= PHY_M_1000C_AFD;
382 if (sky2->advertising & ADVERTISED_1000baseT_Half)
383 ct1000 |= PHY_M_1000C_AHD;
384 if (sky2->advertising & ADVERTISED_100baseT_Full)
385 adv |= PHY_M_AN_100_FD;
386 if (sky2->advertising & ADVERTISED_100baseT_Half)
387 adv |= PHY_M_AN_100_HD;
388 if (sky2->advertising & ADVERTISED_10baseT_Full)
389 adv |= PHY_M_AN_10_FD;
390 if (sky2->advertising & ADVERTISED_10baseT_Half)
391 adv |= PHY_M_AN_10_HD;
709c6e7b 392
16ad91e1 393 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 394 } else { /* special defines for FIBER (88E1040S only) */
395 if (sky2->advertising & ADVERTISED_1000baseT_Full)
396 adv |= PHY_M_AN_1000X_AFD;
397 if (sky2->advertising & ADVERTISED_1000baseT_Half)
398 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 399
16ad91e1 400 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 401 }
cd28ab6a
SH		 402
403 /* Restart Auto-negotiation */
404 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
405 } else {
406 /* forced speed/duplex settings */
407 ct1000 = PHY_M_1000C_MSE;
408
2eaba1a2
SH		 409 /* Disable auto update for duplex flow control and speed */
410 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 411
412 switch (sky2->speed) {
413 case SPEED_1000:
414 ctrl |= PHY_CT_SP1000;
2eaba1a2 415 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 416 break;
417 case SPEED_100:
418 ctrl |= PHY_CT_SP100;
2eaba1a2 419 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 420 break;
421 }
422
2eaba1a2
SH		 423 if (sky2->duplex == DUPLEX_FULL) {
424 reg |= GM_GPCR_DUP_FULL;
425 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 426 } else if (sky2->speed < SPEED_1000)
427 sky2->flow_mode = FC_NONE;
2eaba1a2 428
2eaba1a2 429
16ad91e1 430 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 431
432 /* Forward pause packets to GMAC? */
16ad91e1 433 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 434 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
435 else
436 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 437 }
438
2eaba1a2
SH		 439 gma_write16(hw, port, GM_GP_CTRL, reg);
440
cd28ab6a
SH		 441 if (hw->chip_id != CHIP_ID_YUKON_FE)
442 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
443
444 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
445 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
446
447 /* Setup Phy LED's */
448 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
449 ledover = 0;
450
451 switch (hw->chip_id) {
452 case CHIP_ID_YUKON_FE:
453 /* on 88E3082 these bits are at 11..9 (shifted left) */
454 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
455
456 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
457
458 /* delete ACT LED control bits */
459 ctrl &= ~PHY_M_FELP_LED1_MSK;
460 /* change ACT LED control to blink mode */
461 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
462 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
463 break;
464
465 case CHIP_ID_YUKON_XL:
793b883e 466 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 467
468 /* select page 3 to access LED control register */
469 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
470
471 /* set LED Function Control register */
ed6d32c7
SH		 472 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
473 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
474 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
475 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
476 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 477
478 /* set Polarity Control register */
479 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 480 (PHY_M_POLC_LS1_P_MIX(4) |
481 PHY_M_POLC_IS0_P_MIX(4) |
482 PHY_M_POLC_LOS_CTRL(2) |
483 PHY_M_POLC_INIT_CTRL(2) |
484 PHY_M_POLC_STA1_CTRL(2) |
485 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 486
487 /* restore page register */
793b883e 488 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 489 break;
93745494 490
ed6d32c7 491 case CHIP_ID_YUKON_EC_U:
93745494 492 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 493 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
494
495 /* select page 3 to access LED control register */
496 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
497
498 /* set LED Function Control register */
499 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
500 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
501 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
502 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
503 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
504
505 /* set Blink Rate in LED Timer Control Register */
506 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
507 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
508 /* restore page register */
509 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
510 break;
cd28ab6a
SH		 511
512 default:
513 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
514 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
515 /* turn off the Rx LED (LED_RX) */
0efdf262 516 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 517 }
518
9467a8fc
SH		 519 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
520 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 521 /* apply fixes in PHY AFE */
ed6d32c7
SH		 522 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
523
977bdf06 524 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 525 gm_phy_write(hw, port, 0x18, 0xaa99);
526 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 527
977bdf06 528 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 529 gm_phy_write(hw, port, 0x18, 0xa204);
530 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 531
532 /* set page register to 0 */
9467a8fc 533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
93745494 534 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 535 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 536
977bdf06
SH		 537 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
538 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 539 ledover |= PHY_M_LED_MO_100;
977bdf06 540 }
cd28ab6a 541
977bdf06
SH		 542 if (ledover)
543 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
544
545 }
2eaba1a2 546
d571b694 547 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 548 if (sky2->autoneg == AUTONEG_ENABLE)
549 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
550 else
551 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
552}
553
d3bcfbeb
SH		 554static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
555{
556 u32 reg1;
557 static const u32 phy_power[]
558 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
559
560 /* looks like this XL is back asswards .. */
561 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
562 onoff = !onoff;
563
aed2cec4 564 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 565 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 566 if (onoff)
567 /* Turn off phy power saving */
568 reg1 &= ~phy_power[port];
569 else
570 reg1 |= phy_power[port];
571
572 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 573 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 574 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 575 udelay(100);
576}
577
1b537565
SH		 578/* Force a renegotiation */
579static void sky2_phy_reinit(struct sky2_port *sky2)
580{
e07b1aa8 581 spin_lock_bh(&sky2->phy_lock);
1b537565 582 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 583 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 584}
585
e3173832
SH		 586/* Put device in state to listen for Wake On Lan */
587static void sky2_wol_init(struct sky2_port *sky2)
588{
589 struct sky2_hw *hw = sky2->hw;
590 unsigned port = sky2->port;
591 enum flow_control save_mode;
592 u16 ctrl;
593 u32 reg1;
594
595 /* Bring hardware out of reset */
596 sky2_write16(hw, B0_CTST, CS_RST_CLR);
597 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
598
599 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
600 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
601
602 /* Force to 10/100
603 * sky2_reset will re-enable on resume
604 */
605 save_mode = sky2->flow_mode;
606 ctrl = sky2->advertising;
607
608 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
609 sky2->flow_mode = FC_NONE;
610 sky2_phy_power(hw, port, 1);
611 sky2_phy_reinit(sky2);
612
613 sky2->flow_mode = save_mode;
614 sky2->advertising = ctrl;
615
616 /* Set GMAC to no flow control and auto update for speed/duplex */
617 gma_write16(hw, port, GM_GP_CTRL,
618 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
619 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
620
621 /* Set WOL address */
622 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
623 sky2->netdev->dev_addr, ETH_ALEN);
624
625 /* Turn on appropriate WOL control bits */
626 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
627 ctrl = 0;
628 if (sky2->wol & WAKE_PHY)
629 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
630 else
631 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
632
633 if (sky2->wol & WAKE_MAGIC)
634 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
635 else
636 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
637
638 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
639 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
640
641 /* Turn on legacy PCI-Express PME mode */
642 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
643 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
644 reg1 |= PCI_Y2_PME_LEGACY;
645 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
646 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
647
648 /* block receiver */
649 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
650
651}
652
cd28ab6a
SH		 653static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
654{
655 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
656 u16 reg;
657 int i;
658 const u8 *addr = hw->dev[port]->dev_addr;
659
42eeea01 660 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
b4ed372b 661 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 662
663 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
664
793b883e 665 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 666 /* WA DEV_472 -- looks like crossed wires on port 2 */
667 /* clear GMAC 1 Control reset */
668 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
669 do {
670 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
671 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
672 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
673 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
674 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
675 }
676
793b883e 677 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 678
2eaba1a2
SH		 679 /* Enable Transmit FIFO Underrun */
680 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
681
e07b1aa8 682 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 683 sky2_phy_init(hw, port);
e07b1aa8 684 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 685
686 /* MIB clear */
687 reg = gma_read16(hw, port, GM_PHY_ADDR);
688 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
689
43f2f104
SH		 690 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
691 gma_read16(hw, port, i);
cd28ab6a
SH		 692 gma_write16(hw, port, GM_PHY_ADDR, reg);
693
694 /* transmit control */
695 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
696
697 /* receive control reg: unicast + multicast + no FCS */
698 gma_write16(hw, port, GM_RX_CTRL,
793b883e 699 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 700
701 /* transmit flow control */
702 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
703
704 /* transmit parameter */
705 gma_write16(hw, port, GM_TX_PARAM,
706 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
707 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
708 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
709 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
710
711 /* serial mode register */
712 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 713 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 714
6b1a3aef 715 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 716 reg |= GM_SMOD_JUMBO_ENA;
717
718 gma_write16(hw, port, GM_SERIAL_MODE, reg);
719
cd28ab6a
SH		 720 /* virtual address for data */
721 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
722
793b883e
SH		 723 /* physical address: used for pause frames */
724 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
725
726 /* ignore counter overflows */
cd28ab6a
SH		 727 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
728 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
729 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
730
731 /* Configure Rx MAC FIFO */
732 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 733 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
734 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 735
d571b694 736 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 737 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 738
8df9a876
SH		 739 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
740 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 741
742 /* Configure Tx MAC FIFO */
743 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
744 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 745
93745494 746 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 747 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 748 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98
SH		 749
750 /* set Tx GMAC FIFO Almost Empty Threshold */
751 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
752 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
753
754 if (hw->dev[port]->mtu > ETH_DATA_LEN)
755 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
756 TX_JUMBO_ENA | TX_STFW_DIS);
757 else
758 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
759 TX_JUMBO_DIS | TX_STFW_ENA);
5a5b1ea0
SH		 760 }
761
cd28ab6a
SH		 762}
763
67712901
SH		 764/* Assign Ram Buffer allocation to queue */
765static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 766{
67712901
SH		 767 u32 end;
768
769 /* convert from K bytes to qwords used for hw register */
770 start *= 1024/8;
771 space *= 1024/8;
772 end = start + space - 1;
793b883e 773
cd28ab6a
SH		 774 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
775 sky2_write32(hw, RB_ADDR(q, RB_START), start);
776 sky2_write32(hw, RB_ADDR(q, RB_END), end);
777 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
778 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
779
780 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 781 u32 tp = space - space/4;
793b883e 782
1c28f6ba
SH		 783 /* On receive queue's set the thresholds
784 * give receiver priority when > 3/4 full
785 * send pause when down to 2K
786 */
787 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
788 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 789
1c28f6ba
SH		 790 tp = space - 2048/8;
791 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
792 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 793 } else {
794 /* Enable store & forward on Tx queue's because
795 * Tx FIFO is only 1K on Yukon
796 */
797 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
798 }
799
800 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 801 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 802}
803
cd28ab6a 804/* Setup Bus Memory Interface */
af4ed7e6 805static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 806{
807 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
808 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
809 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 810 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 811}
812
cd28ab6a
SH		 813/* Setup prefetch unit registers. This is the interface between
814 * hardware and driver list elements
815 */
8cc048e3 816static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 817 u64 addr, u32 last)
818{
cd28ab6a
SH		 819 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
820 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
821 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
822 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
823 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
824 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 825
826 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 827}
828
793b883e
SH		 829static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
830{
831 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
832
cb5d9547 833 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 834 le->ctrl = 0;
793b883e
SH		 835 return le;
836}
cd28ab6a 837
291ea614
SH		 838static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
839 struct sky2_tx_le *le)
840{
841 return sky2->tx_ring + (le - sky2->tx_le);
842}
843
290d4de5
SH		 844/* Update chip's next pointer */
845static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 846{
50432cb5 847 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 848 wmb();
50432cb5
SH		 849 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
850
851 /* Synchronize I/O on since next processor may write to tail */
852 mmiowb();
cd28ab6a
SH		 853}
854
793b883e 855
cd28ab6a
SH		 856static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
857{
858 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 859 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 860 le->ctrl = 0;
cd28ab6a
SH		 861 return le;
862}
863
a018e330
SH		 864/* Return high part of DMA address (could be 32 or 64 bit) */
865static inline u32 high32(dma_addr_t a)
866{
a036119f 867 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 868}
869
14d0263f
SH		 870/* Build description to hardware for one receive segment */
871static void sky2_rx_add(struct sky2_port *sky2, u8 op,
872 dma_addr_t map, unsigned len)
cd28ab6a
SH		 873{
874 struct sky2_rx_le *le;
734d1868 875 u32 hi = high32(map);
cd28ab6a 876
793b883e 877 if (sky2->rx_addr64 != hi) {
cd28ab6a 878 le = sky2_next_rx(sky2);
793b883e 879 le->addr = cpu_to_le32(hi);
cd28ab6a 880 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 881 sky2->rx_addr64 = high32(map + len);
cd28ab6a 882 }
793b883e 883
cd28ab6a 884 le = sky2_next_rx(sky2);
734d1868
SH		 885 le->addr = cpu_to_le32((u32) map);
886 le->length = cpu_to_le16(len);
14d0263f 887 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 888}
889
14d0263f
SH		 890/* Build description to hardware for one possibly fragmented skb */
891static void sky2_rx_submit(struct sky2_port *sky2,
892 const struct rx_ring_info *re)
893{
894 int i;
895
896 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
897
898 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
899 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
900}
901
902
903static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
904 unsigned size)
905{
906 struct sk_buff *skb = re->skb;
907 int i;
908
909 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
910 pci_unmap_len_set(re, data_size, size);
911
912 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
913 re->frag_addr[i] = pci_map_page(pdev,
914 skb_shinfo(skb)->frags[i].page,
915 skb_shinfo(skb)->frags[i].page_offset,
916 skb_shinfo(skb)->frags[i].size,
917 PCI_DMA_FROMDEVICE);
918}
919
920static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
921{
922 struct sk_buff *skb = re->skb;
923 int i;
924
925 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
926 PCI_DMA_FROMDEVICE);
927
928 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
929 pci_unmap_page(pdev, re->frag_addr[i],
930 skb_shinfo(skb)->frags[i].size,
931 PCI_DMA_FROMDEVICE);
932}
793b883e 933
cd28ab6a
SH		 934/* Tell chip where to start receive checksum.
935 * Actually has two checksums, but set both same to avoid possible byte
936 * order problems.
937 */
793b883e 938static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 939{
940 struct sky2_rx_le *le;
941
cd28ab6a 942 le = sky2_next_rx(sky2);
f65b138c 943 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 944 le->ctrl = 0;
945 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 946
793b883e
SH		 947 sky2_write32(sky2->hw,
948 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
949 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 950
951}
952
6b1a3aef
SH		 953/*
954 * The RX Stop command will not work for Yukon-2 if the BMU does not
955 * reach the end of packet and since we can't make sure that we have
956 * incoming data, we must reset the BMU while it is not doing a DMA
957 * transfer. Since it is possible that the RX path is still active,
958 * the RX RAM buffer will be stopped first, so any possible incoming
959 * data will not trigger a DMA. After the RAM buffer is stopped, the
960 * BMU is polled until any DMA in progress is ended and only then it
961 * will be reset.
962 */
963static void sky2_rx_stop(struct sky2_port *sky2)
964{
965 struct sky2_hw *hw = sky2->hw;
966 unsigned rxq = rxqaddr[sky2->port];
967 int i;
968
969 /* disable the RAM Buffer receive queue */
970 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
971
972 for (i = 0; i < 0xffff; i++)
973 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
974 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
975 goto stopped;
976
977 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
978 sky2->netdev->name);
979stopped:
980 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
981
982 /* reset the Rx prefetch unit */
983 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 984 mmiowb();
6b1a3aef 985}
793b883e 986
d571b694 987/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 988static void sky2_rx_clean(struct sky2_port *sky2)
989{
990 unsigned i;
991
992 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 993 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 994 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 995
996 if (re->skb) {
14d0263f 997 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 998 kfree_skb(re->skb);
999 re->skb = NULL;
1000 }
1001 }
1002}
1003
ef743d33
SH		 1004/* Basic MII support */
1005static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1006{
1007 struct mii_ioctl_data *data = if_mii(ifr);
1008 struct sky2_port *sky2 = netdev_priv(dev);
1009 struct sky2_hw *hw = sky2->hw;
1010 int err = -EOPNOTSUPP;
1011
1012 if (!netif_running(dev))
1013 return -ENODEV; /* Phy still in reset */
1014
d89e1343 1015 switch (cmd) {
ef743d33
SH		 1016 case SIOCGMIIPHY:
1017 data->phy_id = PHY_ADDR_MARV;
1018
1019 /* fallthru */
1020 case SIOCGMIIREG: {
1021 u16 val = 0;
91c86df5 1022
e07b1aa8 1023 spin_lock_bh(&sky2->phy_lock);
ef743d33 1024 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1025 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1026
ef743d33
SH		 1027 data->val_out = val;
1028 break;
1029 }
1030
1031 case SIOCSMIIREG:
1032 if (!capable(CAP_NET_ADMIN))
1033 return -EPERM;
1034
e07b1aa8 1035 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1036 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1037 data->val_in);
e07b1aa8 1038 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1039 break;
1040 }
1041 return err;
1042}
1043
d1f13708
SH		 1044#ifdef SKY2_VLAN_TAG_USED
1045static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1046{
1047 struct sky2_port *sky2 = netdev_priv(dev);
1048 struct sky2_hw *hw = sky2->hw;
1049 u16 port = sky2->port;
d1f13708 1050
2bb8c262 1051 netif_tx_lock_bh(dev);
3d4e66f5 1052 netif_poll_disable(sky2->hw->dev[0]);
d1f13708 1053
d1f13708 1054 sky2->vlgrp = grp;
3d4e66f5
SH		 1055 if (grp) {
1056 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1057 RX_VLAN_STRIP_ON);
1058 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1059 TX_VLAN_TAG_ON);
1060 } else {
1061 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1062 RX_VLAN_STRIP_OFF);
1063 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1064 TX_VLAN_TAG_OFF);
1065 }
d1f13708 1066
3d4e66f5 1067 netif_poll_enable(sky2->hw->dev[0]);
2bb8c262 1068 netif_tx_unlock_bh(dev);
d1f13708
SH		 1069}
1070#endif
1071
82788c7a 1072/*
14d0263f
SH		 1073 * Allocate an skb for receiving. If the MTU is large enough
1074 * make the skb non-linear with a fragment list of pages.
1075 *
82788c7a
SH		 1076 * It appears the hardware has a bug in the FIFO logic that
1077 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1078 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1079 * aligned except if slab debugging is enabled.
82788c7a 1080 */
14d0263f 1081static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1082{
1083 struct sk_buff *skb;
14d0263f
SH		 1084 unsigned long p;
1085 int i;
82788c7a 1086
14d0263f
SH		 1087 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1088 if (!skb)
1089 goto nomem;
1090
1091 p = (unsigned long) skb->data;
1092 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1093
1094 for (i = 0; i < sky2->rx_nfrags; i++) {
1095 struct page *page = alloc_page(GFP_ATOMIC);
1096
1097 if (!page)
1098 goto free_partial;
1099 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1100 }
1101
1102 return skb;
14d0263f
SH		 1103free_partial:
1104 kfree_skb(skb);
1105nomem:
1106 return NULL;
82788c7a
SH		 1107}
1108
cd28ab6a
SH		 1109/*
1110 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1111 * Normal case this ends up creating one list element for skb
1112 * in the receive ring. Worst case if using large MTU and each
1113 * allocation falls on a different 64 bit region, that results
1114 * in 6 list elements per ring entry.
1115 * One element is used for checksum enable/disable, and one
1116 * extra to avoid wrap.
cd28ab6a 1117 */
6b1a3aef 1118static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1119{
6b1a3aef 1120 struct sky2_hw *hw = sky2->hw;
14d0263f 1121 struct rx_ring_info *re;
6b1a3aef 1122 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1123 unsigned i, size, space, thresh;
cd28ab6a 1124
6b1a3aef 1125 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1126 sky2_qset(hw, rxq);
977bdf06 1127
c3905bc4
SH		 1128 /* On PCI express lowering the watermark gives better performance */
1129 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1130 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1131
1132 /* These chips have no ram buffer?
1133 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1134 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1135 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1136 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
977bdf06 1137 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
977bdf06 1138
6b1a3aef
SH		 1139 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1140
1141 rx_set_checksum(sky2);
14d0263f
SH		 1142
1143 /* Space needed for frame data + headers rounded up */
1144 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1145 + 8;
1146
1147 /* Stopping point for hardware truncation */
1148 thresh = (size - 8) / sizeof(u32);
1149
1150 /* Account for overhead of skb - to avoid order > 0 allocation */
1151 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1152 + sizeof(struct skb_shared_info);
1153
1154 sky2->rx_nfrags = space >> PAGE_SHIFT;
1155 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1156
1157 if (sky2->rx_nfrags != 0) {
1158 /* Compute residue after pages */
1159 space = sky2->rx_nfrags << PAGE_SHIFT;
1160
1161 if (space < size)
1162 size -= space;
1163 else
1164 size = 0;
1165
1166 /* Optimize to handle small packets and headers */
1167 if (size < copybreak)
1168 size = copybreak;
1169 if (size < ETH_HLEN)
1170 size = ETH_HLEN;
1171 }
1172 sky2->rx_data_size = size;
1173
1174 /* Fill Rx ring */
793b883e 1175 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1176 re = sky2->rx_ring + i;
cd28ab6a 1177
14d0263f 1178 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1179 if (!re->skb)
1180 goto nomem;
1181
14d0263f
SH		 1182 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1183 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1184 }
1185
a1433ac4
SH		 1186 /*
1187 * The receiver hangs if it receives frames larger than the
1188 * packet buffer. As a workaround, truncate oversize frames, but
1189 * the register is limited to 9 bits, so if you do frames > 2052
1190 * you better get the MTU right!
1191 */
a1433ac4
SH		 1192 if (thresh > 0x1ff)
1193 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1194 else {
1195 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1196 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1197 }
1198
6b1a3aef 1199 /* Tell chip about available buffers */
50432cb5 1200 sky2_put_idx(hw, rxq, sky2->rx_put);
cd28ab6a
SH		 1201 return 0;
1202nomem:
1203 sky2_rx_clean(sky2);
1204 return -ENOMEM;
1205}
1206
1207/* Bring up network interface. */
1208static int sky2_up(struct net_device *dev)
1209{
1210 struct sky2_port *sky2 = netdev_priv(dev);
1211 struct sky2_hw *hw = sky2->hw;
1212 unsigned port = sky2->port;
67712901 1213 u32 ramsize, imask;
ee7abb04 1214 int cap, err = -ENOMEM;
843a46f4 1215 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1216
ee7abb04
SH		 1217 /*
1218 * On dual port PCI-X card, there is an problem where status
1219 * can be received out of order due to split transactions
843a46f4 1220 */
ee7abb04
SH		 1221 if (otherdev && netif_running(otherdev) &&
1222 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1223 struct sky2_port *osky2 = netdev_priv(otherdev);
1224 u16 cmd;
1225
1226 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1227 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1228 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1229
1230 sky2->rx_csum = 0;
1231 osky2->rx_csum = 0;
1232 }
843a46f4 1233
cd28ab6a
SH		 1234 if (netif_msg_ifup(sky2))
1235 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1236
1237 /* must be power of 2 */
1238 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1239 TX_RING_SIZE *
1240 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1241 &sky2->tx_le_map);
1242 if (!sky2->tx_le)
1243 goto err_out;
1244
6cdbbdf3 1245 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1246 GFP_KERNEL);
1247 if (!sky2->tx_ring)
1248 goto err_out;
1249 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1250
1251 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1252 &sky2->rx_le_map);
1253 if (!sky2->rx_le)
1254 goto err_out;
1255 memset(sky2->rx_le, 0, RX_LE_BYTES);
1256
291ea614 1257 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1258 GFP_KERNEL);
1259 if (!sky2->rx_ring)
1260 goto err_out;
1261
d3bcfbeb
SH		 1262 sky2_phy_power(hw, port, 1);
1263
cd28ab6a
SH		 1264 sky2_mac_init(hw, port);
1265
67712901
SH		 1266 /* Register is number of 4K blocks on internal RAM buffer. */
1267 ramsize = sky2_read8(hw, B2_E_0) * 4;
1268 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1269
67712901
SH		 1270 if (ramsize > 0) {
1271 u32 rxspace;
cd28ab6a 1272
67712901
SH		 1273 if (ramsize < 16)
1274 rxspace = ramsize / 2;
1275 else
1276 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1277
67712901
SH		 1278 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1279 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1280
1281 /* Make sure SyncQ is disabled */
1282 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1283 RB_RST_SET);
1284 }
793b883e 1285
af4ed7e6 1286 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1287
977bdf06 1288 /* Set almost empty threshold */
c2716fb4
SH		 1289 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1290 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1291 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1292
6b1a3aef
SH		 1293 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1294 TX_RING_SIZE - 1);
cd28ab6a 1295
6b1a3aef 1296 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1297 if (err)
1298 goto err_out;
1299
cd28ab6a 1300 /* Enable interrupts from phy/mac for port */
e07b1aa8 1301 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1302 imask |= portirq_msk[port];
e07b1aa8
SH		 1303 sky2_write32(hw, B0_IMSK, imask);
1304
cd28ab6a
SH		 1305 return 0;
1306
1307err_out:
1b537565 1308 if (sky2->rx_le) {
cd28ab6a
SH		 1309 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1310 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1311 sky2->rx_le = NULL;
1312 }
1313 if (sky2->tx_le) {
cd28ab6a
SH		 1314 pci_free_consistent(hw->pdev,
1315 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1316 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1317 sky2->tx_le = NULL;
1318 }
1319 kfree(sky2->tx_ring);
1320 kfree(sky2->rx_ring);
cd28ab6a 1321
1b537565
SH		 1322 sky2->tx_ring = NULL;
1323 sky2->rx_ring = NULL;
cd28ab6a
SH		 1324 return err;
1325}
1326
793b883e
SH		 1327/* Modular subtraction in ring */
1328static inline int tx_dist(unsigned tail, unsigned head)
1329{
cb5d9547 1330 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1331}
cd28ab6a 1332
793b883e
SH		 1333/* Number of list elements available for next tx */
1334static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1335{
793b883e 1336 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1337}
1338
793b883e 1339/* Estimate of number of transmit list elements required */
28bd181a 1340static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1341{
793b883e
SH		 1342 unsigned count;
1343
1344 count = sizeof(dma_addr_t) / sizeof(u32);
1345 count += skb_shinfo(skb)->nr_frags * count;
1346
89114afd 1347 if (skb_is_gso(skb))
793b883e
SH		 1348 ++count;
1349
84fa7933 1350 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1351 ++count;
1352
1353 return count;
cd28ab6a
SH		 1354}
1355
793b883e
SH		 1356/*
1357 * Put one packet in ring for transmit.
1358 * A single packet can generate multiple list elements, and
1359 * the number of ring elements will probably be less than the number
1360 * of list elements used.
1361 */
cd28ab6a
SH		 1362static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1363{
1364 struct sky2_port *sky2 = netdev_priv(dev);
1365 struct sky2_hw *hw = sky2->hw;
d1f13708 1366 struct sky2_tx_le *le = NULL;
6cdbbdf3 1367 struct tx_ring_info *re;
cd28ab6a
SH		 1368 unsigned i, len;
1369 dma_addr_t mapping;
1370 u32 addr64;
1371 u16 mss;
1372 u8 ctrl;
1373
2bb8c262
SH		 1374 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1375 return NETDEV_TX_BUSY;
cd28ab6a 1376
793b883e 1377 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1378 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1379 dev->name, sky2->tx_prod, skb->len);
1380
cd28ab6a
SH		 1381 len = skb_headlen(skb);
1382 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1383 addr64 = high32(mapping);
793b883e 1384
a018e330
SH		 1385 /* Send high bits if changed or crosses boundary */
1386 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1387 le = get_tx_le(sky2);
f65b138c 1388 le->addr = cpu_to_le32(addr64);
793b883e 1389 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1390 sky2->tx_addr64 = high32(mapping + len);
793b883e 1391 }
cd28ab6a
SH		 1392
1393 /* Check for TCP Segmentation Offload */
7967168c 1394 mss = skb_shinfo(skb)->gso_size;
793b883e 1395 if (mss != 0) {
ab6a5bb6 1396 mss += tcp_optlen(skb); /* TCP options */
c9bdd4b5 1397 mss += ip_hdrlen(skb) + sizeof(struct tcphdr);
cd28ab6a
SH		 1398 mss += ETH_HLEN;
1399
e07560cd
SH		 1400 if (mss != sky2->tx_last_mss) {
1401 le = get_tx_le(sky2);
f65b138c 1402 le->addr = cpu_to_le32(mss);
e07560cd 1403 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1404 sky2->tx_last_mss = mss;
1405 }
cd28ab6a
SH		 1406 }
1407
cd28ab6a 1408 ctrl = 0;
d1f13708
SH		 1409#ifdef SKY2_VLAN_TAG_USED
1410 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1411 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1412 if (!le) {
1413 le = get_tx_le(sky2);
f65b138c 1414 le->addr = 0;
d1f13708 1415 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1416 } else
1417 le->opcode |= OP_VLAN;
1418 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1419 ctrl |= INS_VLAN;
1420 }
1421#endif
1422
1423 /* Handle TCP checksum offload */
84fa7933 1424 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d 1425 const unsigned offset = skb_transport_offset(skb);
f65b138c
SH		 1426 u32 tcpsum;
1427
1428 tcpsum = offset << 16; /* sum start */
ff1dcadb 1429 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a 1430
56069c0f 1431 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
eddc9ec5 1432 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
cd28ab6a
SH		 1433 ctrl |= UDPTCP;
1434
f65b138c
SH		 1435 if (tcpsum != sky2->tx_tcpsum) {
1436 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1437
1438 le = get_tx_le(sky2);
f65b138c 1439 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1440 le->length = 0; /* initial checksum value */
1441 le->ctrl = 1; /* one packet */
1442 le->opcode = OP_TCPLISW | HW_OWNER;
1443 }
cd28ab6a
SH		 1444 }
1445
1446 le = get_tx_le(sky2);
f65b138c 1447 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1448 le->length = cpu_to_le16(len);
1449 le->ctrl = ctrl;
793b883e 1450 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1451
291ea614 1452 re = tx_le_re(sky2, le);
cd28ab6a 1453 re->skb = skb;
6cdbbdf3 1454 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1455 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1456
1457 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1458 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1459
1460 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1461 frag->size, PCI_DMA_TODEVICE);
a036119f 1462 addr64 = high32(mapping);
793b883e
SH		 1463 if (addr64 != sky2->tx_addr64) {
1464 le = get_tx_le(sky2);
f65b138c 1465 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1466 le->ctrl = 0;
1467 le->opcode = OP_ADDR64 | HW_OWNER;
1468 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1469 }
1470
1471 le = get_tx_le(sky2);
f65b138c 1472 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1473 le->length = cpu_to_le16(frag->size);
1474 le->ctrl = ctrl;
793b883e 1475 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1476
291ea614
SH		 1477 re = tx_le_re(sky2, le);
1478 re->skb = skb;
1479 pci_unmap_addr_set(re, mapaddr, mapping);
1480 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1481 }
6cdbbdf3 1482
cd28ab6a
SH		 1483 le->ctrl |= EOP;
1484
97bda706
SH		 1485 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1486 netif_stop_queue(dev);
b19666d9 1487
290d4de5 1488 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1489
cd28ab6a
SH		 1490 dev->trans_start = jiffies;
1491 return NETDEV_TX_OK;
1492}
1493
cd28ab6a 1494/*
793b883e
SH		 1495 * Free ring elements from starting at tx_cons until "done"
1496 *
1497 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1498 * buffers so make sure not to free skb to early.
cd28ab6a 1499 */
d11c13e7 1500static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1501{
d11c13e7 1502 struct net_device *dev = sky2->netdev;
af2a58ac 1503 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1504 unsigned idx;
cd28ab6a 1505
0e3ff6aa 1506 BUG_ON(done >= TX_RING_SIZE);
2224795d 1507
291ea614
SH		 1508 for (idx = sky2->tx_cons; idx != done;
1509 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1510 struct sky2_tx_le *le = sky2->tx_le + idx;
1511 struct tx_ring_info *re = sky2->tx_ring + idx;
1512
1513 switch(le->opcode & ~HW_OWNER) {
1514 case OP_LARGESEND:
1515 case OP_PACKET:
1516 pci_unmap_single(pdev,
1517 pci_unmap_addr(re, mapaddr),
1518 pci_unmap_len(re, maplen),
1519 PCI_DMA_TODEVICE);
af2a58ac 1520 break;
291ea614
SH		 1521 case OP_BUFFER:
1522 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1523 pci_unmap_len(re, maplen),
734d1868 1524 PCI_DMA_TODEVICE);
291ea614
SH		 1525 break;
1526 }
1527
1528 if (le->ctrl & EOP) {
1529 if (unlikely(netif_msg_tx_done(sky2)))
1530 printk(KERN_DEBUG "%s: tx done %u\n",
1531 dev->name, idx);
2bf56fe2 1532 sky2->net_stats.tx_packets++;
1533 sky2->net_stats.tx_bytes += re->skb->len;
1534
794b2bd2 1535 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1536 }
1537
291ea614 1538 le->opcode = 0; /* paranoia */
793b883e 1539 }
793b883e 1540
291ea614 1541 sky2->tx_cons = idx;
50432cb5
SH		 1542 smp_mb();
1543
22e11703 1544 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1545 netif_wake_queue(dev);
cd28ab6a
SH		 1546}
1547
1548/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1549static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1550{
2bb8c262
SH		 1551 struct sky2_port *sky2 = netdev_priv(dev);
1552
1553 netif_tx_lock_bh(dev);
d11c13e7 1554 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1555 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1556}
1557
1558/* Network shutdown */
1559static int sky2_down(struct net_device *dev)
1560{
1561 struct sky2_port *sky2 = netdev_priv(dev);
1562 struct sky2_hw *hw = sky2->hw;
1563 unsigned port = sky2->port;
1564 u16 ctrl;
e07b1aa8 1565 u32 imask;
cd28ab6a 1566
1b537565
SH		 1567 /* Never really got started! */
1568 if (!sky2->tx_le)
1569 return 0;
1570
cd28ab6a
SH		 1571 if (netif_msg_ifdown(sky2))
1572 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1573
018d1c66 1574 /* Stop more packets from being queued */
cd28ab6a 1575 netif_stop_queue(dev);
9a87240c 1576 netif_carrier_off(dev);
cd28ab6a 1577
ebc646f6
SH		 1578 /* Disable port IRQ */
1579 imask = sky2_read32(hw, B0_IMSK);
1580 imask &= ~portirq_msk[port];
1581 sky2_write32(hw, B0_IMSK, imask);
1582
d3bcfbeb 1583 sky2_gmac_reset(hw, port);
793b883e 1584
cd28ab6a
SH		 1585 /* Stop transmitter */
1586 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1587 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1588
1589 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1590 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1591
1592 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1593 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1594 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1595
1596 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1597
1598 /* Workaround shared GMAC reset */
793b883e
SH		 1599 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1600 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1601 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1602
1603 /* Disable Force Sync bit and Enable Alloc bit */
1604 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1605 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1606
1607 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1608 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1609 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1610
1611 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1612 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1613 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1614
1615 /* Reset the Tx prefetch units */
1616 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1617 PREF_UNIT_RST_SET);
1618
1619 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1620
6b1a3aef 1621 sky2_rx_stop(sky2);
cd28ab6a
SH		 1622
1623 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1624 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1625
d3bcfbeb
SH		 1626 sky2_phy_power(hw, port, 0);
1627
d571b694 1628 /* turn off LED's */
cd28ab6a
SH		 1629 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1630
018d1c66
SH		 1631 synchronize_irq(hw->pdev->irq);
1632
2bb8c262 1633 sky2_tx_clean(dev);
cd28ab6a
SH		 1634 sky2_rx_clean(sky2);
1635
1636 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1637 sky2->rx_le, sky2->rx_le_map);
1638 kfree(sky2->rx_ring);
1639
1640 pci_free_consistent(hw->pdev,
1641 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1642 sky2->tx_le, sky2->tx_le_map);
1643 kfree(sky2->tx_ring);
1644
1b537565
SH		 1645 sky2->tx_le = NULL;
1646 sky2->rx_le = NULL;
1647
1648 sky2->rx_ring = NULL;
1649 sky2->tx_ring = NULL;
1650
cd28ab6a
SH		 1651 return 0;
1652}
1653
1654static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1655{
b89165f2 1656 if (!sky2_is_copper(hw))
793b883e
SH		 1657 return SPEED_1000;
1658
cd28ab6a
SH		 1659 if (hw->chip_id == CHIP_ID_YUKON_FE)
1660 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1661
1662 switch (aux & PHY_M_PS_SPEED_MSK) {
1663 case PHY_M_PS_SPEED_1000:
1664 return SPEED_1000;
1665 case PHY_M_PS_SPEED_100:
1666 return SPEED_100;
1667 default:
1668 return SPEED_10;
1669 }
1670}
1671
1672static void sky2_link_up(struct sky2_port *sky2)
1673{
1674 struct sky2_hw *hw = sky2->hw;
1675 unsigned port = sky2->port;
1676 u16 reg;
16ad91e1
SH		 1677 static const char *fc_name[] = {
1678 [FC_NONE] = "none",
1679 [FC_TX] = "tx",
1680 [FC_RX] = "rx",
1681 [FC_BOTH] = "both",
1682 };
cd28ab6a 1683
cd28ab6a 1684 /* enable Rx/Tx */
2eaba1a2 1685 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1686 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1687 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1688
1689 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1690
1691 netif_carrier_on(sky2->netdev);
1692 netif_wake_queue(sky2->netdev);
1693
1694 /* Turn on link LED */
793b883e 1695 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1696 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1697
93745494
SH		 1698 if (hw->chip_id == CHIP_ID_YUKON_XL
1699 || hw->chip_id == CHIP_ID_YUKON_EC_U
1700 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1701 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1702 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1703
1704 switch(sky2->speed) {
1705 case SPEED_10:
1706 led |= PHY_M_LEDC_INIT_CTRL(7);
1707 break;
1708
1709 case SPEED_100:
1710 led |= PHY_M_LEDC_STA1_CTRL(7);
1711 break;
1712
1713 case SPEED_1000:
1714 led |= PHY_M_LEDC_STA0_CTRL(7);
1715 break;
1716 }
793b883e
SH		 1717
1718 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1719 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1720 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1721 }
1722
cd28ab6a
SH		 1723 if (netif_msg_link(sky2))
1724 printk(KERN_INFO PFX
d571b694 1725 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1726 sky2->netdev->name, sky2->speed,
1727 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1728 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1729}
1730
1731static void sky2_link_down(struct sky2_port *sky2)
1732{
1733 struct sky2_hw *hw = sky2->hw;
1734 unsigned port = sky2->port;
1735 u16 reg;
1736
1737 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1738
1739 reg = gma_read16(hw, port, GM_GP_CTRL);
1740 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1741 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1742
cd28ab6a
SH		 1743 netif_carrier_off(sky2->netdev);
1744 netif_stop_queue(sky2->netdev);
1745
1746 /* Turn on link LED */
1747 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1748
1749 if (netif_msg_link(sky2))
1750 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1751
cd28ab6a
SH		 1752 sky2_phy_init(hw, port);
1753}
1754
16ad91e1
SH		 1755static enum flow_control sky2_flow(int rx, int tx)
1756{
1757 if (rx)
1758 return tx ? FC_BOTH : FC_RX;
1759 else
1760 return tx ? FC_TX : FC_NONE;
1761}
1762
793b883e
SH		 1763static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1764{
1765 struct sky2_hw *hw = sky2->hw;
1766 unsigned port = sky2->port;
da4c1ff4 1767 u16 advert, lpa;
793b883e 1768
da4c1ff4 1769 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1770 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1771 if (lpa & PHY_M_AN_RF) {
1772 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1773 return -1;
1774 }
1775
793b883e
SH		 1776 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1777 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1778 sky2->netdev->name);
1779 return -1;
1780 }
1781
793b883e 1782 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1783 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1784
da4c1ff4
SH		 1785 /* Since the pause result bits seem to in different positions on
1786 * different chips. look at registers.
1787 */
1788 if (!sky2_is_copper(hw)) {
1789 /* Shift for bits in fiber PHY */
1790 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1791 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1792
1793 if (advert & ADVERTISE_1000XPAUSE)
1794 advert |= ADVERTISE_PAUSE_CAP;
1795 if (advert & ADVERTISE_1000XPSE_ASYM)
1796 advert |= ADVERTISE_PAUSE_ASYM;
1797 if (lpa & LPA_1000XPAUSE)
1798 lpa |= LPA_PAUSE_CAP;
1799 if (lpa & LPA_1000XPAUSE_ASYM)
1800 lpa |= LPA_PAUSE_ASYM;
1801 }
793b883e 1802
da4c1ff4
SH		 1803 sky2->flow_status = FC_NONE;
1804 if (advert & ADVERTISE_PAUSE_CAP) {
1805 if (lpa & LPA_PAUSE_CAP)
1806 sky2->flow_status = FC_BOTH;
1807 else if (advert & ADVERTISE_PAUSE_ASYM)
1808 sky2->flow_status = FC_RX;
1809 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1810 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1811 sky2->flow_status = FC_TX;
1812 }
793b883e 1813
16ad91e1 1814 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1815 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1816 sky2->flow_status = FC_NONE;
2eaba1a2 1817
da4c1ff4 1818 if (sky2->flow_status & FC_TX)
793b883e
SH		 1819 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1820 else
1821 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1822
1823 return 0;
1824}
cd28ab6a 1825
e07b1aa8
SH		 1826/* Interrupt from PHY */
1827static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1828{
e07b1aa8
SH		 1829 struct net_device *dev = hw->dev[port];
1830 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1831 u16 istatus, phystat;
1832
ebc646f6
SH		 1833 if (!netif_running(dev))
1834 return;
1835
e07b1aa8
SH		 1836 spin_lock(&sky2->phy_lock);
1837 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1838 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1839
cd28ab6a
SH		 1840 if (netif_msg_intr(sky2))
1841 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1842 sky2->netdev->name, istatus, phystat);
1843
2eaba1a2 1844 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1845 if (sky2_autoneg_done(sky2, phystat) == 0)
1846 sky2_link_up(sky2);
1847 goto out;
1848 }
cd28ab6a 1849
793b883e
SH		 1850 if (istatus & PHY_M_IS_LSP_CHANGE)
1851 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1852
793b883e
SH		 1853 if (istatus & PHY_M_IS_DUP_CHANGE)
1854 sky2->duplex =
1855 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1856
793b883e
SH		 1857 if (istatus & PHY_M_IS_LST_CHANGE) {
1858 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1859 sky2_link_up(sky2);
793b883e
SH		 1860 else
1861 sky2_link_down(sky2);
cd28ab6a 1862 }
793b883e 1863out:
e07b1aa8 1864 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1865}
1866
62335ab0 1867/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1868 * and tx queue is full (stopped).
1869 */
cd28ab6a
SH		 1870static void sky2_tx_timeout(struct net_device *dev)
1871{
1872 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1873 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1874
1875 if (netif_msg_timer(sky2))
1876 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1877
8f24664d 1878 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1879 dev->name, sky2->tx_cons, sky2->tx_prod,
1880 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1881 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1882
81906791
SH		 1883 /* can't restart safely under softirq */
1884 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1885}
1886
1887static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1888{
6b1a3aef
SH		 1889 struct sky2_port *sky2 = netdev_priv(dev);
1890 struct sky2_hw *hw = sky2->hw;
b628ed98 1891 unsigned port = sky2->port;
6b1a3aef
SH		 1892 int err;
1893 u16 ctl, mode;
e07b1aa8 1894 u32 imask;
cd28ab6a
SH		 1895
1896 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1897 return -EINVAL;
1898
d2adf4f6
SH		 1899 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1900 return -EINVAL;
1901
6b1a3aef
SH		 1902 if (!netif_running(dev)) {
1903 dev->mtu = new_mtu;
1904 return 0;
1905 }
1906
e07b1aa8 1907 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1908 sky2_write32(hw, B0_IMSK, 0);
1909
018d1c66
SH		 1910 dev->trans_start = jiffies; /* prevent tx timeout */
1911 netif_stop_queue(dev);
1912 netif_poll_disable(hw->dev[0]);
1913
e07b1aa8
SH		 1914 synchronize_irq(hw->pdev->irq);
1915
b628ed98
SH		 1916 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
1917 if (new_mtu > ETH_DATA_LEN) {
1918 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1919 TX_JUMBO_ENA | TX_STFW_DIS);
1920 dev->features &= NETIF_F_TSO | NETIF_F_SG | NETIF_F_IP_CSUM;
1921 } else
1922 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1923 TX_JUMBO_DIS | TX_STFW_ENA);
1924 }
1925
1926 ctl = gma_read16(hw, port, GM_GP_CTRL);
1927 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 1928 sky2_rx_stop(sky2);
1929 sky2_rx_clean(sky2);
cd28ab6a
SH		 1930
1931 dev->mtu = new_mtu;
14d0263f 1932
6b1a3aef
SH		 1933 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1934 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1935
1936 if (dev->mtu > ETH_DATA_LEN)
1937 mode |= GM_SMOD_JUMBO_ENA;
1938
b628ed98 1939 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 1940
b628ed98 1941 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1942
6b1a3aef 1943 err = sky2_rx_start(sky2);
e07b1aa8 1944 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1945
1b537565
SH		 1946 if (err)
1947 dev_close(dev);
1948 else {
b628ed98 1949 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 1950
1951 netif_poll_enable(hw->dev[0]);
1952 netif_wake_queue(dev);
1953 }
1954
cd28ab6a
SH		 1955 return err;
1956}
1957
14d0263f
SH		 1958/* For small just reuse existing skb for next receive */
1959static struct sk_buff *receive_copy(struct sky2_port *sky2,
1960 const struct rx_ring_info *re,
1961 unsigned length)
1962{
1963 struct sk_buff *skb;
1964
1965 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1966 if (likely(skb)) {
1967 skb_reserve(skb, 2);
1968 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1969 length, PCI_DMA_FROMDEVICE);
d626f62b 1970 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 1971 skb->ip_summed = re->skb->ip_summed;
1972 skb->csum = re->skb->csum;
1973 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1974 length, PCI_DMA_FROMDEVICE);
1975 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1976 skb_put(skb, length);
14d0263f
SH		 1977 }
1978 return skb;
1979}
1980
1981/* Adjust length of skb with fragments to match received data */
1982static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1983 unsigned int length)
1984{
1985 int i, num_frags;
1986 unsigned int size;
1987
1988 /* put header into skb */
1989 size = min(length, hdr_space);
1990 skb->tail += size;
1991 skb->len += size;
1992 length -= size;
1993
1994 num_frags = skb_shinfo(skb)->nr_frags;
1995 for (i = 0; i < num_frags; i++) {
1996 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1997
1998 if (length == 0) {
1999 /* don't need this page */
2000 __free_page(frag->page);
2001 --skb_shinfo(skb)->nr_frags;
2002 } else {
2003 size = min(length, (unsigned) PAGE_SIZE);
2004
2005 frag->size = size;
2006 skb->data_len += size;
2007 skb->truesize += size;
2008 skb->len += size;
2009 length -= size;
2010 }
2011 }
2012}
2013
2014/* Normal packet - take skb from ring element and put in a new one */
2015static struct sk_buff *receive_new(struct sky2_port *sky2,
2016 struct rx_ring_info *re,
2017 unsigned int length)
2018{
2019 struct sk_buff *skb, *nskb;
2020 unsigned hdr_space = sky2->rx_data_size;
2021
2022 pr_debug(PFX "receive new length=%d\n", length);
2023
2024 /* Don't be tricky about reusing pages (yet) */
2025 nskb = sky2_rx_alloc(sky2);
2026 if (unlikely(!nskb))
2027 return NULL;
2028
2029 skb = re->skb;
2030 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2031
2032 prefetch(skb->data);
2033 re->skb = nskb;
2034 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2035
2036 if (skb_shinfo(skb)->nr_frags)
2037 skb_put_frags(skb, hdr_space, length);
2038 else
489b10c1 2039 skb_put(skb, length);
14d0263f
SH		 2040 return skb;
2041}
2042
cd28ab6a
SH		 2043/*
2044 * Receive one packet.
d571b694 2045 * For larger packets, get new buffer.
cd28ab6a 2046 */
497d7c86 2047static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2048 u16 length, u32 status)
2049{
497d7c86 2050 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2051 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2052 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2053
2054 if (unlikely(netif_msg_rx_status(sky2)))
2055 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2056 dev->name, sky2->rx_next, status, length);
cd28ab6a 2057
793b883e 2058 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2059 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2060
42eeea01 2061 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2062 goto error;
2063
42eeea01
SH		 2064 if (!(status & GMR_FS_RX_OK))
2065 goto resubmit;
2066
14d0263f
SH		 2067 if (length < copybreak)
2068 skb = receive_copy(sky2, re, length);
2069 else
2070 skb = receive_new(sky2, re, length);
793b883e 2071resubmit:
14d0263f 2072 sky2_rx_submit(sky2, re);
79e57d32 2073
cd28ab6a
SH		 2074 return skb;
2075
2076error:
6e15b712 2077 ++sky2->net_stats.rx_errors;
b6d77734 2078 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2079 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2080 goto resubmit;
2081 }
6e15b712 2082
3be92a70 2083 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2084 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2085 dev->name, status, length);
793b883e
SH		 2086
2087 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2088 sky2->net_stats.rx_length_errors++;
2089 if (status & GMR_FS_FRAGMENT)
2090 sky2->net_stats.rx_frame_errors++;
2091 if (status & GMR_FS_CRC_ERR)
2092 sky2->net_stats.rx_crc_errors++;
79e57d32 2093
793b883e 2094 goto resubmit;
cd28ab6a
SH		 2095}
2096
e07b1aa8
SH		 2097/* Transmit complete */
2098static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2099{
e07b1aa8 2100 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2101
e07b1aa8 2102 if (netif_running(dev)) {
2bb8c262 2103 netif_tx_lock(dev);
e07b1aa8 2104 sky2_tx_complete(sky2, last);
2bb8c262 2105 netif_tx_unlock(dev);
2224795d 2106 }
cd28ab6a
SH		 2107}
2108
e07b1aa8
SH		 2109/* Process status response ring */
2110static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2111{
22e11703 2112 struct sky2_port *sky2;
e07b1aa8 2113 int work_done = 0;
22e11703 2114 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2115 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2116
af2a58ac 2117 rmb();
bea86103 2118
e71ebd73 2119 while (hw->st_idx != hwidx) {
13210ce5
SH		 2120 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2121 struct net_device *dev;
cd28ab6a 2122 struct sk_buff *skb;
cd28ab6a
SH		 2123 u32 status;
2124 u16 length;
2125
cb5d9547 2126 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2127
e71ebd73
SH		 2128 BUG_ON(le->link >= 2);
2129 dev = hw->dev[le->link];
13210ce5
SH		 2130
2131 sky2 = netdev_priv(dev);
f65b138c
SH		 2132 length = le16_to_cpu(le->length);
2133 status = le32_to_cpu(le->status);
cd28ab6a 2134
e71ebd73 2135 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2136 case OP_RXSTAT:
497d7c86 2137 skb = sky2_receive(dev, length, status);
3225b919
SH		 2138 if (unlikely(!skb)) {
2139 sky2->net_stats.rx_dropped++;
5df79111 2140 goto force_update;
3225b919 2141 }
13210ce5 2142
13210ce5 2143 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2144 sky2->net_stats.rx_packets++;
2145 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2146 dev->last_rx = jiffies;
2147
d1f13708
SH		 2148#ifdef SKY2_VLAN_TAG_USED
2149 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2150 vlan_hwaccel_receive_skb(skb,
2151 sky2->vlgrp,
2152 be16_to_cpu(sky2->rx_tag));
2153 } else
2154#endif
cd28ab6a 2155 netif_receive_skb(skb);
13210ce5 2156
22e11703
SH		 2157 /* Update receiver after 16 frames */
2158 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2159force_update:
2160 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2161 buf_write[le->link] = 0;
2162 }
2163
2164 /* Stop after net poll weight */
13210ce5
SH		 2165 if (++work_done >= to_do)
2166 goto exit_loop;
cd28ab6a
SH		 2167 break;
2168
d1f13708
SH		 2169#ifdef SKY2_VLAN_TAG_USED
2170 case OP_RXVLAN:
2171 sky2->rx_tag = length;
2172 break;
2173
2174 case OP_RXCHKSVLAN:
2175 sky2->rx_tag = length;
2176 /* fall through */
2177#endif
cd28ab6a 2178 case OP_RXCHKS:
87418307
SH		 2179 if (!sky2->rx_csum)
2180 break;
2181
2182 /* Both checksum counters are programmed to start at
2183 * the same offset, so unless there is a problem they
2184 * should match. This failure is an early indication that
2185 * hardware receive checksumming won't work.
2186 */
2187 if (likely(status >> 16 == (status & 0xffff))) {
2188 skb = sky2->rx_ring[sky2->rx_next].skb;
2189 skb->ip_summed = CHECKSUM_COMPLETE;
2190 skb->csum = status & 0xffff;
2191 } else {
2192 printk(KERN_NOTICE PFX "%s: hardware receive "
2193 "checksum problem (status = %#x)\n",
2194 dev->name, status);
2195 sky2->rx_csum = 0;
2196 sky2_write32(sky2->hw,
2197 Q_ADDR(rxqaddr[le->link], Q_CSR),
2198 BMU_DIS_RX_CHKSUM);
2199 }
cd28ab6a
SH		 2200 break;
2201
2202 case OP_TXINDEXLE:
13b97b74 2203 /* TX index reports status for both ports */
f55925d7
SH		 2204 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2205 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2206 if (hw->dev[1])
2207 sky2_tx_done(hw->dev[1],
2208 ((status >> 24) & 0xff)
2209 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2210 break;
2211
cd28ab6a
SH		 2212 default:
2213 if (net_ratelimit())
793b883e 2214 printk(KERN_WARNING PFX
e71ebd73
SH		 2215 "unknown status opcode 0x%x\n", le->opcode);
2216 goto exit_loop;
cd28ab6a 2217 }
13210ce5 2218 }
cd28ab6a 2219
fe2a24df
SH		 2220 /* Fully processed status ring so clear irq */
2221 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
50432cb5 2222 mmiowb();
fe2a24df 2223
13210ce5 2224exit_loop:
22e11703
SH		 2225 if (buf_write[0]) {
2226 sky2 = netdev_priv(hw->dev[0]);
2227 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2228 }
2229
2230 if (buf_write[1]) {
2231 sky2 = netdev_priv(hw->dev[1]);
2232 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2233 }
2234
e07b1aa8 2235 return work_done;
cd28ab6a
SH		 2236}
2237
2238static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2239{
2240 struct net_device *dev = hw->dev[port];
2241
3be92a70
SH		 2242 if (net_ratelimit())
2243 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2244 dev->name, status);
cd28ab6a
SH		 2245
2246 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2247 if (net_ratelimit())
2248 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2249 dev->name);
cd28ab6a
SH		 2250 /* Clear IRQ */
2251 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2252 }
2253
2254 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2255 if (net_ratelimit())
2256 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2257 dev->name);
cd28ab6a
SH		 2258
2259 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2260 }
2261
2262 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2263 if (net_ratelimit())
2264 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2265 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2266 }
2267
2268 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2269 if (net_ratelimit())
2270 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2271 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2272 }
2273
2274 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2275 if (net_ratelimit())
2276 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2277 dev->name);
cd28ab6a
SH		 2278 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2279 }
2280}
2281
2282static void sky2_hw_intr(struct sky2_hw *hw)
2283{
2284 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2285
793b883e 2286 if (status & Y2_IS_TIST_OV)
cd28ab6a 2287 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2288
2289 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2290 u16 pci_err;
2291
56a645cc 2292 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2293 if (net_ratelimit())
b02a9258
SH		 2294 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2295 pci_err);
cd28ab6a
SH		 2296
2297 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2298 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2299 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2300 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2301 }
2302
2303 if (status & Y2_IS_PCI_EXP) {
d571b694 2304 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2305 u32 pex_err;
2306
7bd656d1 2307 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2308
3be92a70 2309 if (net_ratelimit())
b02a9258
SH		 2310 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2311 pex_err);
cd28ab6a
SH		 2312
2313 /* clear the interrupt */
2314 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2315 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2316 0xffffffffUL);
cd28ab6a
SH		 2317 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2318
7bd656d1 2319 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2320 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2321 hwmsk &= ~Y2_IS_PCI_EXP;
2322 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2323 }
2324 }
2325
2326 if (status & Y2_HWE_L1_MASK)
2327 sky2_hw_error(hw, 0, status);
2328 status >>= 8;
2329 if (status & Y2_HWE_L1_MASK)
2330 sky2_hw_error(hw, 1, status);
2331}
2332
2333static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2334{
2335 struct net_device *dev = hw->dev[port];
2336 struct sky2_port *sky2 = netdev_priv(dev);
2337 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2338
2339 if (netif_msg_intr(sky2))
2340 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2341 dev->name, status);
2342
a3caeada
SH		 2343 if (status & GM_IS_RX_CO_OV)
2344 gma_read16(hw, port, GM_RX_IRQ_SRC);
2345
2346 if (status & GM_IS_TX_CO_OV)
2347 gma_read16(hw, port, GM_TX_IRQ_SRC);
2348
cd28ab6a
SH		 2349 if (status & GM_IS_RX_FF_OR) {
2350 ++sky2->net_stats.rx_fifo_errors;
2351 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2352 }
2353
2354 if (status & GM_IS_TX_FF_UR) {
2355 ++sky2->net_stats.tx_fifo_errors;
2356 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2357 }
cd28ab6a
SH		 2358}
2359
40b01727
SH		 2360/* This should never happen it is a bug. */
2361static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2362 u16 q, unsigned ring_size)
d257924e
SH		 2363{
2364 struct net_device *dev = hw->dev[port];
2365 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2366 unsigned idx;
2367 const u64 *le = (q == Q_R1 || q == Q_R2)
2368 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2369
40b01727
SH		 2370 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2371 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2372 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2373 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2374
40b01727 2375 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2376}
cd28ab6a 2377
d27ed387
SH		 2378/* If idle then force a fake soft NAPI poll once a second
2379 * to work around cases where sharing an edge triggered interrupt.
2380 */
eb35cf60
SH		 2381static inline void sky2_idle_start(struct sky2_hw *hw)
2382{
2383 if (idle_timeout > 0)
2384 mod_timer(&hw->idle_timer,
2385 jiffies + msecs_to_jiffies(idle_timeout));
2386}
2387
d27ed387
SH		 2388static void sky2_idle(unsigned long arg)
2389{
01bd7564
SH		 2390 struct sky2_hw *hw = (struct sky2_hw *) arg;
2391 struct net_device *dev = hw->dev[0];
d27ed387 2392
d27ed387
SH		 2393 if (__netif_rx_schedule_prep(dev))
2394 __netif_rx_schedule(dev);
01bd7564
SH		 2395
2396 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2397}
2398
40b01727
SH		 2399/* Hardware/software error handling */
2400static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2401{
40b01727
SH		 2402 if (net_ratelimit())
2403 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2404
1e5f1283
SH		 2405 if (status & Y2_IS_HW_ERR)
2406 sky2_hw_intr(hw);
d257924e 2407
1e5f1283
SH		 2408 if (status & Y2_IS_IRQ_MAC1)
2409 sky2_mac_intr(hw, 0);
cd28ab6a 2410
1e5f1283
SH		 2411 if (status & Y2_IS_IRQ_MAC2)
2412 sky2_mac_intr(hw, 1);
cd28ab6a 2413
1e5f1283 2414 if (status & Y2_IS_CHK_RX1)
40b01727 2415 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2416
1e5f1283 2417 if (status & Y2_IS_CHK_RX2)
40b01727 2418 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2419
1e5f1283 2420 if (status & Y2_IS_CHK_TXA1)
40b01727 2421 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2422
1e5f1283 2423 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2424 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2425}
2426
2427static int sky2_poll(struct net_device *dev0, int *budget)
2428{
2429 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2430 int work_limit = min(dev0->quota, *budget);
2431 int work_done = 0;
2432 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2433
2434 if (unlikely(status & Y2_IS_ERROR))
2435 sky2_err_intr(hw, status);
2436
2437 if (status & Y2_IS_IRQ_PHY1)
2438 sky2_phy_intr(hw, 0);
2439
2440 if (status & Y2_IS_IRQ_PHY2)
2441 sky2_phy_intr(hw, 1);
cd28ab6a 2442
1e5f1283 2443 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2444 if (work_done < work_limit) {
2445 netif_rx_complete(dev0);
86fba634 2446
50432cb5 2447 /* end of interrupt, re-enables also acts as I/O synchronization */
fe2a24df
SH		 2448 sky2_read32(hw, B0_Y2_SP_LISR);
2449 return 0;
2450 } else {
2451 *budget -= work_done;
2452 dev0->quota -= work_done;
1e5f1283 2453 return 1;
fe2a24df 2454 }
e07b1aa8
SH		 2455}
2456
7d12e780 2457static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2458{
2459 struct sky2_hw *hw = dev_id;
2460 struct net_device *dev0 = hw->dev[0];
2461 u32 status;
2462
2463 /* Reading this mask interrupts as side effect */
2464 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2465 if (status == 0 || status == ~0)
2466 return IRQ_NONE;
793b883e 2467
e07b1aa8
SH		 2468 prefetch(&hw->st_le[hw->st_idx]);
2469 if (likely(__netif_rx_schedule_prep(dev0)))
2470 __netif_rx_schedule(dev0);
793b883e 2471
cd28ab6a
SH		 2472 return IRQ_HANDLED;
2473}
2474
2475#ifdef CONFIG_NET_POLL_CONTROLLER
2476static void sky2_netpoll(struct net_device *dev)
2477{
2478 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2479 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2480
88d11360
SH		 2481 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2482 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2483}
2484#endif
2485
2486/* Chip internal frequency for clock calculations */
fb17358f 2487static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2488{
793b883e 2489 switch (hw->chip_id) {
cd28ab6a 2490 case CHIP_ID_YUKON_EC:
5a5b1ea0 2491 case CHIP_ID_YUKON_EC_U:
93745494 2492 case CHIP_ID_YUKON_EX:
fb17358f 2493 return 125; /* 125 Mhz */
cd28ab6a 2494 case CHIP_ID_YUKON_FE:
fb17358f 2495 return 100; /* 100 Mhz */
793b883e 2496 default: /* YUKON_XL */
fb17358f 2497 return 156; /* 156 Mhz */
cd28ab6a
SH		 2498 }
2499}
2500
fb17358f 2501static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2502{
fb17358f 2503 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2504}
2505
fb17358f 2506static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2507{
fb17358f 2508 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2509}
2510
fb17358f 2511
e3173832 2512static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2513{
b89165f2 2514 u8 t8;
cd28ab6a 2515
cd28ab6a 2516 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2517
cd28ab6a
SH		 2518 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2519 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2520 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2521 hw->chip_id);
cd28ab6a
SH		 2522 return -EOPNOTSUPP;
2523 }
2524
93745494
SH		 2525 if (hw->chip_id == CHIP_ID_YUKON_EX)
2526 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2527 "Please report success or failure to <netdev@vger.kernel.org>\n");
2528
2529 /* Make sure and enable all clocks */
2530 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2531 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2532
290d4de5
SH		 2533 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2534
2535 /* This rev is really old, and requires untested workarounds */
2536 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2537 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2538 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2539 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2540 return -EOPNOTSUPP;
2541 }
2542
e3173832
SH		 2543 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2544 hw->ports = 1;
2545 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2546 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2547 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2548 ++hw->ports;
2549 }
2550
2551 return 0;
2552}
2553
2554static void sky2_reset(struct sky2_hw *hw)
2555{
2556 u16 status;
2557 int i;
2558
cd28ab6a 2559 /* disable ASF */
4f44d8ba
SH		 2560 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2561 status = sky2_read16(hw, HCU_CCSR);
2562 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2563 HCU_CCSR_UC_STATE_MSK);
2564 sky2_write16(hw, HCU_CCSR, status);
2565 } else
2566 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2567 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2568
2569 /* do a SW reset */
2570 sky2_write8(hw, B0_CTST, CS_RST_SET);
2571 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2572
2573 /* clear PCI errors, if any */
56a645cc 2574 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2575
cd28ab6a 2576 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2577 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2578
cd28ab6a
SH		 2579
2580 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2581
2582 /* clear any PEX errors */
7bd656d1
SH		 2583 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2584 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2585
cd28ab6a 2586
ae306cca 2587 sky2_power_on(hw);
cd28ab6a
SH		 2588
2589 for (i = 0; i < hw->ports; i++) {
2590 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2591 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2592 }
2593
2594 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2595
793b883e
SH		 2596 /* Clear I2C IRQ noise */
2597 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2598
2599 /* turn off hardware timer (unused) */
2600 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2601 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2602
cd28ab6a
SH		 2603 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2604
69634ee7
SH		 2605 /* Turn off descriptor polling */
2606 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2607
2608 /* Turn off receive timestamp */
2609 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2610 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2611
2612 /* enable the Tx Arbiters */
2613 for (i = 0; i < hw->ports; i++)
2614 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2615
2616 /* Initialize ram interface */
2617 for (i = 0; i < hw->ports; i++) {
793b883e 2618 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2619
2620 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2621 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2622 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2623 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2624 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2625 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2626 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2627 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2628 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2629 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2630 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2631 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2632 }
2633
7bd656d1 2634 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2635
cd28ab6a 2636 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2637 sky2_gmac_reset(hw, i);
cd28ab6a 2638
cd28ab6a
SH		 2639 memset(hw->st_le, 0, STATUS_LE_BYTES);
2640 hw->st_idx = 0;
2641
2642 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2643 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2644
2645 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2646 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2647
2648 /* Set the list last index */
793b883e 2649 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2650
290d4de5
SH		 2651 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2652 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2653
290d4de5
SH		 2654 /* set Status-FIFO ISR watermark */
2655 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2656 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2657 else
2658 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2659
290d4de5 2660 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2661 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2662 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2663
793b883e 2664 /* enable status unit */
cd28ab6a
SH		 2665 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2666
2667 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2668 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2669 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2670}
2671
81906791
SH		 2672static void sky2_restart(struct work_struct *work)
2673{
2674 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2675 struct net_device *dev;
2676 int i, err;
2677
2678 dev_dbg(&hw->pdev->dev, "restarting\n");
2679
2680 del_timer_sync(&hw->idle_timer);
2681
2682 rtnl_lock();
2683 sky2_write32(hw, B0_IMSK, 0);
2684 sky2_read32(hw, B0_IMSK);
2685
2686 netif_poll_disable(hw->dev[0]);
2687
2688 for (i = 0; i < hw->ports; i++) {
2689 dev = hw->dev[i];
2690 if (netif_running(dev))
2691 sky2_down(dev);
2692 }
2693
2694 sky2_reset(hw);
2695 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2696 netif_poll_enable(hw->dev[0]);
2697
2698 for (i = 0; i < hw->ports; i++) {
2699 dev = hw->dev[i];
2700 if (netif_running(dev)) {
2701 err = sky2_up(dev);
2702 if (err) {
2703 printk(KERN_INFO PFX "%s: could not restart %d\n",
2704 dev->name, err);
2705 dev_close(dev);
2706 }
2707 }
2708 }
2709
2710 sky2_idle_start(hw);
2711
2712 rtnl_unlock();
2713}
2714
e3173832
SH		 2715static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2716{
2717 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2718}
2719
2720static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2721{
2722 const struct sky2_port *sky2 = netdev_priv(dev);
2723
2724 wol->supported = sky2_wol_supported(sky2->hw);
2725 wol->wolopts = sky2->wol;
2726}
2727
2728static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2729{
2730 struct sky2_port *sky2 = netdev_priv(dev);
2731 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2732
e3173832
SH		 2733 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2734 return -EOPNOTSUPP;
2735
2736 sky2->wol = wol->wolopts;
2737
2738 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2739 sky2_write32(hw, B0_CTST, sky2->wol
2740 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2741
2742 if (!netif_running(dev))
2743 sky2_wol_init(sky2);
cd28ab6a
SH		 2744 return 0;
2745}
2746
28bd181a 2747static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2748{
b89165f2
SH		 2749 if (sky2_is_copper(hw)) {
2750 u32 modes = SUPPORTED_10baseT_Half
2751 | SUPPORTED_10baseT_Full
2752 | SUPPORTED_100baseT_Half
2753 | SUPPORTED_100baseT_Full
2754 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2755
2756 if (hw->chip_id != CHIP_ID_YUKON_FE)
2757 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2758 | SUPPORTED_1000baseT_Full;
2759 return modes;
cd28ab6a 2760 } else
b89165f2
SH		 2761 return SUPPORTED_1000baseT_Half
2762 | SUPPORTED_1000baseT_Full
2763 | SUPPORTED_Autoneg
2764 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2765}
2766
793b883e 2767static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2768{
2769 struct sky2_port *sky2 = netdev_priv(dev);
2770 struct sky2_hw *hw = sky2->hw;
2771
2772 ecmd->transceiver = XCVR_INTERNAL;
2773 ecmd->supported = sky2_supported_modes(hw);
2774 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2775 if (sky2_is_copper(hw)) {
cd28ab6a 2776 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2777 | SUPPORTED_10baseT_Full
2778 | SUPPORTED_100baseT_Half
2779 | SUPPORTED_100baseT_Full
2780 | SUPPORTED_1000baseT_Half
2781 | SUPPORTED_1000baseT_Full
2782 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2783 ecmd->port = PORT_TP;
b89165f2
SH		 2784 ecmd->speed = sky2->speed;
2785 } else {
2786 ecmd->speed = SPEED_1000;
cd28ab6a 2787 ecmd->port = PORT_FIBRE;
b89165f2 2788 }
cd28ab6a
SH		 2789
2790 ecmd->advertising = sky2->advertising;
2791 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2792 ecmd->duplex = sky2->duplex;
2793 return 0;
2794}
2795
2796static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2797{
2798 struct sky2_port *sky2 = netdev_priv(dev);
2799 const struct sky2_hw *hw = sky2->hw;
2800 u32 supported = sky2_supported_modes(hw);
2801
2802 if (ecmd->autoneg == AUTONEG_ENABLE) {
2803 ecmd->advertising = supported;
2804 sky2->duplex = -1;
2805 sky2->speed = -1;
2806 } else {
2807 u32 setting;
2808
793b883e 2809 switch (ecmd->speed) {
cd28ab6a
SH		 2810 case SPEED_1000:
2811 if (ecmd->duplex == DUPLEX_FULL)
2812 setting = SUPPORTED_1000baseT_Full;
2813 else if (ecmd->duplex == DUPLEX_HALF)
2814 setting = SUPPORTED_1000baseT_Half;
2815 else
2816 return -EINVAL;
2817 break;
2818 case SPEED_100:
2819 if (ecmd->duplex == DUPLEX_FULL)
2820 setting = SUPPORTED_100baseT_Full;
2821 else if (ecmd->duplex == DUPLEX_HALF)
2822 setting = SUPPORTED_100baseT_Half;
2823 else
2824 return -EINVAL;
2825 break;
2826
2827 case SPEED_10:
2828 if (ecmd->duplex == DUPLEX_FULL)
2829 setting = SUPPORTED_10baseT_Full;
2830 else if (ecmd->duplex == DUPLEX_HALF)
2831 setting = SUPPORTED_10baseT_Half;
2832 else
2833 return -EINVAL;
2834 break;
2835 default:
2836 return -EINVAL;
2837 }
2838
2839 if ((setting & supported) == 0)
2840 return -EINVAL;
2841
2842 sky2->speed = ecmd->speed;
2843 sky2->duplex = ecmd->duplex;
2844 }
2845
2846 sky2->autoneg = ecmd->autoneg;
2847 sky2->advertising = ecmd->advertising;
2848
1b537565
SH		 2849 if (netif_running(dev))
2850 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2851
2852 return 0;
2853}
2854
2855static void sky2_get_drvinfo(struct net_device *dev,
2856 struct ethtool_drvinfo *info)
2857{
2858 struct sky2_port *sky2 = netdev_priv(dev);
2859
2860 strcpy(info->driver, DRV_NAME);
2861 strcpy(info->version, DRV_VERSION);
2862 strcpy(info->fw_version, "N/A");
2863 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2864}
2865
2866static const struct sky2_stat {
793b883e
SH		 2867 char name[ETH_GSTRING_LEN];
2868 u16 offset;
cd28ab6a
SH		 2869} sky2_stats[] = {
2870 { "tx_bytes", GM_TXO_OK_HI },
2871 { "rx_bytes", GM_RXO_OK_HI },
2872 { "tx_broadcast", GM_TXF_BC_OK },
2873 { "rx_broadcast", GM_RXF_BC_OK },
2874 { "tx_multicast", GM_TXF_MC_OK },
2875 { "rx_multicast", GM_RXF_MC_OK },
2876 { "tx_unicast", GM_TXF_UC_OK },
2877 { "rx_unicast", GM_RXF_UC_OK },
2878 { "tx_mac_pause", GM_TXF_MPAUSE },
2879 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2880 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2881 { "late_collision",GM_TXF_LAT_COL },
2882 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2883 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2884 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2885
d2604540 2886 { "rx_short", GM_RXF_SHT },
cd28ab6a 2887 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2888 { "rx_64_byte_packets", GM_RXF_64B },
2889 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2890 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2891 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2892 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2893 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2894 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2895 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2896 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2897 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2898 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2899
2900 { "tx_64_byte_packets", GM_TXF_64B },
2901 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2902 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2903 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2904 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2905 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2906 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2907 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2908};
2909
cd28ab6a
SH		 2910static u32 sky2_get_rx_csum(struct net_device *dev)
2911{
2912 struct sky2_port *sky2 = netdev_priv(dev);
2913
2914 return sky2->rx_csum;
2915}
2916
2917static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2918{
2919 struct sky2_port *sky2 = netdev_priv(dev);
2920
2921 sky2->rx_csum = data;
793b883e 2922
cd28ab6a
SH		 2923 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2924 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2925
2926 return 0;
2927}
2928
2929static u32 sky2_get_msglevel(struct net_device *netdev)
2930{
2931 struct sky2_port *sky2 = netdev_priv(netdev);
2932 return sky2->msg_enable;
2933}
2934
9a7ae0a9
SH		 2935static int sky2_nway_reset(struct net_device *dev)
2936{
2937 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2938
16ad91e1 2939 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2940 return -EINVAL;
2941
1b537565 2942 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2943
2944 return 0;
2945}
2946
793b883e 2947static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2948{
2949 struct sky2_hw *hw = sky2->hw;
2950 unsigned port = sky2->port;
2951 int i;
2952
2953 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2954 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2955 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2956 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2957
793b883e 2958 for (i = 2; i < count; i++)
cd28ab6a
SH		 2959 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2960}
2961
cd28ab6a
SH		 2962static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2963{
2964 struct sky2_port *sky2 = netdev_priv(netdev);
2965 sky2->msg_enable = value;
2966}
2967
2968static int sky2_get_stats_count(struct net_device *dev)
2969{
2970 return ARRAY_SIZE(sky2_stats);
2971}
2972
2973static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2974 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2975{
2976 struct sky2_port *sky2 = netdev_priv(dev);
2977
793b883e 2978 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2979}
2980
793b883e 2981static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2982{
2983 int i;
2984
2985 switch (stringset) {
2986 case ETH_SS_STATS:
2987 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2988 memcpy(data + i * ETH_GSTRING_LEN,
2989 sky2_stats[i].name, ETH_GSTRING_LEN);
2990 break;
2991 }
2992}
2993
cd28ab6a
SH		 2994static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2995{
2996 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2997 return &sky2->net_stats;
2998}
2999
3000static int sky2_set_mac_address(struct net_device *dev, void *p)
3001{
3002 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3003 struct sky2_hw *hw = sky2->hw;
3004 unsigned port = sky2->port;
3005 const struct sockaddr *addr = p;
cd28ab6a
SH		 3006
3007 if (!is_valid_ether_addr(addr->sa_data))
3008 return -EADDRNOTAVAIL;
3009
cd28ab6a 3010 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3011 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3012 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3013 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3014 dev->dev_addr, ETH_ALEN);
1b537565 3015
a8ab1ec0
SH		 3016 /* virtual address for data */
3017 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3018
3019 /* physical address: used for pause frames */
3020 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3021
3022 return 0;
cd28ab6a
SH		 3023}
3024
a052b52f
SH		 3025static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3026{
3027 u32 bit;
3028
3029 bit = ether_crc(ETH_ALEN, addr) & 63;
3030 filter[bit >> 3] |= 1 << (bit & 7);
3031}
3032
cd28ab6a
SH		 3033static void sky2_set_multicast(struct net_device *dev)
3034{
3035 struct sky2_port *sky2 = netdev_priv(dev);
3036 struct sky2_hw *hw = sky2->hw;
3037 unsigned port = sky2->port;
3038 struct dev_mc_list *list = dev->mc_list;
3039 u16 reg;
3040 u8 filter[8];
a052b52f
SH		 3041 int rx_pause;
3042 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3043
a052b52f 3044 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3045 memset(filter, 0, sizeof(filter));
3046
3047 reg = gma_read16(hw, port, GM_RX_CTRL);
3048 reg |= GM_RXCR_UCF_ENA;
3049
d571b694 3050 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3051 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3052 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3053 memset(filter, 0xff, sizeof(filter));
a052b52f 3054 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3055 reg &= ~GM_RXCR_MCF_ENA;
3056 else {
3057 int i;
3058 reg |= GM_RXCR_MCF_ENA;
3059
a052b52f
SH		 3060 if (rx_pause)
3061 sky2_add_filter(filter, pause_mc_addr);
3062
3063 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3064 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3065 }
3066
cd28ab6a 3067 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3068 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3069 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3070 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3071 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3072 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3073 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3074 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3075
3076 gma_write16(hw, port, GM_RX_CTRL, reg);
3077}
3078
3079/* Can have one global because blinking is controlled by
3080 * ethtool and that is always under RTNL mutex
3081 */
91c86df5 3082static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3083{
793b883e
SH		 3084 u16 pg;
3085
793b883e
SH		 3086 switch (hw->chip_id) {
3087 case CHIP_ID_YUKON_XL:
3088 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3089 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3090 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3091 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3092 PHY_M_LEDC_INIT_CTRL(7) |
3093 PHY_M_LEDC_STA1_CTRL(7) |
3094 PHY_M_LEDC_STA0_CTRL(7))
3095 : 0);
3096
3097 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3098 break;
3099
3100 default:
3101 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3102 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3103 on ? PHY_M_LED_ALL : 0);
793b883e 3104 }
cd28ab6a
SH		 3105}
3106
3107/* blink LED's for finding board */
3108static int sky2_phys_id(struct net_device *dev, u32 data)
3109{
3110 struct sky2_port *sky2 = netdev_priv(dev);
3111 struct sky2_hw *hw = sky2->hw;
3112 unsigned port = sky2->port;
793b883e 3113 u16 ledctrl, ledover = 0;
cd28ab6a 3114 long ms;
91c86df5 3115 int interrupted;
cd28ab6a
SH		 3116 int onoff = 1;
3117
793b883e 3118 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3119 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3120 else
3121 ms = data * 1000;
3122
3123 /* save initial values */
e07b1aa8 3124 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3125 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3126 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3127 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3128 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3129 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3130 } else {
3131 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3132 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3133 }
cd28ab6a 3134
91c86df5
SH		 3135 interrupted = 0;
3136 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3137 sky2_led(hw, port, onoff);
3138 onoff = !onoff;
3139
e07b1aa8 3140 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3141 interrupted = msleep_interruptible(250);
e07b1aa8 3142 spin_lock_bh(&sky2->phy_lock);
91c86df5 3143
cd28ab6a
SH		 3144 ms -= 250;
3145 }
3146
3147 /* resume regularly scheduled programming */
793b883e
SH		 3148 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3149 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3150 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3151 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3152 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3153 } else {
3154 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3155 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3156 }
e07b1aa8 3157 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3158
3159 return 0;
3160}
3161
3162static void sky2_get_pauseparam(struct net_device *dev,
3163 struct ethtool_pauseparam *ecmd)
3164{
3165 struct sky2_port *sky2 = netdev_priv(dev);
3166
16ad91e1
SH		 3167 switch (sky2->flow_mode) {
3168 case FC_NONE:
3169 ecmd->tx_pause = ecmd->rx_pause = 0;
3170 break;
3171 case FC_TX:
3172 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3173 break;
3174 case FC_RX:
3175 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3176 break;
3177 case FC_BOTH:
3178 ecmd->tx_pause = ecmd->rx_pause = 1;
3179 }
3180
cd28ab6a
SH		 3181 ecmd->autoneg = sky2->autoneg;
3182}
3183
3184static int sky2_set_pauseparam(struct net_device *dev,
3185 struct ethtool_pauseparam *ecmd)
3186{
3187 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3188
3189 sky2->autoneg = ecmd->autoneg;
16ad91e1 3190 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3191
16ad91e1
SH		 3192 if (netif_running(dev))
3193 sky2_phy_reinit(sky2);
cd28ab6a 3194
2eaba1a2 3195 return 0;
cd28ab6a
SH		 3196}
3197
fb17358f
SH		 3198static int sky2_get_coalesce(struct net_device *dev,
3199 struct ethtool_coalesce *ecmd)
3200{
3201 struct sky2_port *sky2 = netdev_priv(dev);
3202 struct sky2_hw *hw = sky2->hw;
3203
3204 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3205 ecmd->tx_coalesce_usecs = 0;
3206 else {
3207 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3208 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3209 }
3210 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3211
3212 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3213 ecmd->rx_coalesce_usecs = 0;
3214 else {
3215 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3216 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3217 }
3218 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3219
3220 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3221 ecmd->rx_coalesce_usecs_irq = 0;
3222 else {
3223 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3224 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3225 }
3226
3227 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3228
3229 return 0;
3230}
3231
3232/* Note: this affect both ports */
3233static int sky2_set_coalesce(struct net_device *dev,
3234 struct ethtool_coalesce *ecmd)
3235{
3236 struct sky2_port *sky2 = netdev_priv(dev);
3237 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3238 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3239
77b3d6a2
SH		 3240 if (ecmd->tx_coalesce_usecs > tmax ||
3241 ecmd->rx_coalesce_usecs > tmax ||
3242 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3243 return -EINVAL;
3244
ff81fbbe 3245 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3246 return -EINVAL;
ff81fbbe 3247 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3248 return -EINVAL;
ff81fbbe 3249 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3250 return -EINVAL;
3251
3252 if (ecmd->tx_coalesce_usecs == 0)
3253 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3254 else {
3255 sky2_write32(hw, STAT_TX_TIMER_INI,
3256 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3257 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3258 }
3259 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3260
3261 if (ecmd->rx_coalesce_usecs == 0)
3262 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3263 else {
3264 sky2_write32(hw, STAT_LEV_TIMER_INI,
3265 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3266 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3267 }
3268 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3269
3270 if (ecmd->rx_coalesce_usecs_irq == 0)
3271 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3272 else {
d28d4870 3273 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3274 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3275 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3276 }
3277 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3278 return 0;
3279}
3280
793b883e
SH		 3281static void sky2_get_ringparam(struct net_device *dev,
3282 struct ethtool_ringparam *ering)
3283{
3284 struct sky2_port *sky2 = netdev_priv(dev);
3285
3286 ering->rx_max_pending = RX_MAX_PENDING;
3287 ering->rx_mini_max_pending = 0;
3288 ering->rx_jumbo_max_pending = 0;
3289 ering->tx_max_pending = TX_RING_SIZE - 1;
3290
3291 ering->rx_pending = sky2->rx_pending;
3292 ering->rx_mini_pending = 0;
3293 ering->rx_jumbo_pending = 0;
3294 ering->tx_pending = sky2->tx_pending;
3295}
3296
3297static int sky2_set_ringparam(struct net_device *dev,
3298 struct ethtool_ringparam *ering)
3299{
3300 struct sky2_port *sky2 = netdev_priv(dev);
3301 int err = 0;
3302
3303 if (ering->rx_pending > RX_MAX_PENDING ||
3304 ering->rx_pending < 8 ||
3305 ering->tx_pending < MAX_SKB_TX_LE ||
3306 ering->tx_pending > TX_RING_SIZE - 1)
3307 return -EINVAL;
3308
3309 if (netif_running(dev))
3310 sky2_down(dev);
3311
3312 sky2->rx_pending = ering->rx_pending;
3313 sky2->tx_pending = ering->tx_pending;
3314
1b537565 3315 if (netif_running(dev)) {
793b883e 3316 err = sky2_up(dev);
1b537565
SH		 3317 if (err)
3318 dev_close(dev);
6ed995bb
SH		 3319 else
3320 sky2_set_multicast(dev);
1b537565 3321 }
793b883e
SH		 3322
3323 return err;
3324}
3325
793b883e
SH		 3326static int sky2_get_regs_len(struct net_device *dev)
3327{
6e4cbb34 3328 return 0x4000;
793b883e
SH		 3329}
3330
3331/*
3332 * Returns copy of control register region
3ead5db7 3333 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3334 */
3335static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3336 void *p)
3337{
3338 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3339 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3340
3341 regs->version = 1;
6e4cbb34 3342 memset(p, 0, regs->len);
793b883e 3343
6e4cbb34
SH		 3344 memcpy_fromio(p, io, B3_RAM_ADDR);
3345
3ead5db7
SH		 3346 /* skip diagnostic ram region */
3347 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3348
3349 /* copy GMAC registers */
3350 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3351 if (sky2->hw->ports > 1)
3352 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3353
793b883e 3354}
cd28ab6a 3355
b628ed98
SH		 3356/* In order to do Jumbo packets on these chips, need to turn off the
3357 * transmit store/forward. Therefore checksum offload won't work.
3358 */
3359static int no_tx_offload(struct net_device *dev)
3360{
3361 const struct sky2_port *sky2 = netdev_priv(dev);
3362 const struct sky2_hw *hw = sky2->hw;
3363
3364 return dev->mtu > ETH_DATA_LEN &&
3365 (hw->chip_id == CHIP_ID_YUKON_EX
3366 || hw->chip_id == CHIP_ID_YUKON_EC_U);
3367}
3368
3369static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3370{
3371 if (data && no_tx_offload(dev))
3372 return -EINVAL;
3373
3374 return ethtool_op_set_tx_csum(dev, data);
3375}
3376
3377
3378static int sky2_set_tso(struct net_device *dev, u32 data)
3379{
3380 if (data && no_tx_offload(dev))
3381 return -EINVAL;
3382
3383 return ethtool_op_set_tso(dev, data);
3384}
3385
7282d491 3386static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3387 .get_settings = sky2_get_settings,
3388 .set_settings = sky2_set_settings,
e3173832
SH		 3389 .get_drvinfo = sky2_get_drvinfo,
3390 .get_wol = sky2_get_wol,
3391 .set_wol = sky2_set_wol,
793b883e
SH		 3392 .get_msglevel = sky2_get_msglevel,
3393 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3394 .nway_reset = sky2_nway_reset,
793b883e
SH		 3395 .get_regs_len = sky2_get_regs_len,
3396 .get_regs = sky2_get_regs,
3397 .get_link = ethtool_op_get_link,
3398 .get_sg = ethtool_op_get_sg,
3399 .set_sg = ethtool_op_set_sg,
3400 .get_tx_csum = ethtool_op_get_tx_csum,
b628ed98 3401 .set_tx_csum = sky2_set_tx_csum,
793b883e 3402 .get_tso = ethtool_op_get_tso,
b628ed98 3403 .set_tso = sky2_set_tso,
793b883e
SH		 3404 .get_rx_csum = sky2_get_rx_csum,
3405 .set_rx_csum = sky2_set_rx_csum,
3406 .get_strings = sky2_get_strings,
fb17358f
SH		 3407 .get_coalesce = sky2_get_coalesce,
3408 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3409 .get_ringparam = sky2_get_ringparam,
3410 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3411 .get_pauseparam = sky2_get_pauseparam,
3412 .set_pauseparam = sky2_set_pauseparam,
793b883e 3413 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3414 .get_stats_count = sky2_get_stats_count,
3415 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3416 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3417};
3418
3419/* Initialize network device */
3420static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3421 unsigned port,
3422 int highmem, int wol)
cd28ab6a
SH		 3423{
3424 struct sky2_port *sky2;
3425 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3426
3427 if (!dev) {
b02a9258 3428 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3429 return NULL;
3430 }
3431
3432 SET_MODULE_OWNER(dev);
3433 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3434 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3435 dev->open = sky2_up;
3436 dev->stop = sky2_down;
ef743d33 3437 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3438 dev->hard_start_xmit = sky2_xmit_frame;
3439 dev->get_stats = sky2_get_stats;
3440 dev->set_multicast_list = sky2_set_multicast;
3441 dev->set_mac_address = sky2_set_mac_address;
3442 dev->change_mtu = sky2_change_mtu;
3443 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3444 dev->tx_timeout = sky2_tx_timeout;
3445 dev->watchdog_timeo = TX_WATCHDOG;
3446 if (port == 0)
3447 dev->poll = sky2_poll;
3448 dev->weight = NAPI_WEIGHT;
3449#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3450 /* Network console (only works on port 0)
3451 * because netpoll makes assumptions about NAPI
3452 */
3453 if (port == 0)
3454 dev->poll_controller = sky2_netpoll;
cd28ab6a 3455#endif
cd28ab6a
SH		 3456
3457 sky2 = netdev_priv(dev);
3458 sky2->netdev = dev;
3459 sky2->hw = hw;
3460 sky2->msg_enable = netif_msg_init(debug, default_msg);
3461
cd28ab6a
SH		 3462 /* Auto speed and flow control */
3463 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3464 sky2->flow_mode = FC_BOTH;
3465
cd28ab6a
SH		 3466 sky2->duplex = -1;
3467 sky2->speed = -1;
3468 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3469 sky2->rx_csum = 1;
e3173832 3470 sky2->wol = wol;
75d070c5 3471
e07b1aa8 3472 spin_lock_init(&sky2->phy_lock);
793b883e 3473 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3474 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3475
3476 hw->dev[port] = dev;
3477
3478 sky2->port = port;
3479
4a50a876 3480 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3481 if (highmem)
3482 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3483
d1f13708
SH		 3484#ifdef SKY2_VLAN_TAG_USED
3485 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3486 dev->vlan_rx_register = sky2_vlan_rx_register;
d1f13708
SH		 3487#endif
3488
cd28ab6a 3489 /* read the mac address */
793b883e 3490 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3491 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3492
3493 /* device is off until link detection */
3494 netif_carrier_off(dev);
3495 netif_stop_queue(dev);
3496
3497 return dev;
3498}
3499
28bd181a 3500static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3501{
3502 const struct sky2_port *sky2 = netdev_priv(dev);
3503
3504 if (netif_msg_probe(sky2))
3505 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3506 dev->name,
3507 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3508 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3509}
3510
fb2690a9 3511/* Handle software interrupt used during MSI test */
7d12e780 3512static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3513{
3514 struct sky2_hw *hw = dev_id;
3515 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3516
3517 if (status == 0)
3518 return IRQ_NONE;
3519
3520 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3521 hw->msi = 1;
fb2690a9
SH		 3522 wake_up(&hw->msi_wait);
3523 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3524 }
3525 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3526
3527 return IRQ_HANDLED;
3528}
3529
3530/* Test interrupt path by forcing a a software IRQ */
3531static int __devinit sky2_test_msi(struct sky2_hw *hw)
3532{
3533 struct pci_dev *pdev = hw->pdev;
3534 int err;
3535
bb507fe1
SH		 3536 init_waitqueue_head (&hw->msi_wait);
3537
fb2690a9
SH		 3538 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3539
b0a20ded 3540 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3541 if (err) {
b02a9258 3542 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3543 return err;
3544 }
3545
fb2690a9 3546 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3547 sky2_read8(hw, B0_CTST);
fb2690a9 3548
b0a20ded 3549 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3550
b0a20ded 3551 if (!hw->msi) {
fb2690a9 3552 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3553 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3554 "switching to INTx mode.\n");
fb2690a9
SH		 3555
3556 err = -EOPNOTSUPP;
3557 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3558 }
3559
3560 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3561 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3562
3563 free_irq(pdev->irq, hw);
3564
3565 return err;
3566}
3567
e3173832
SH		 3568static int __devinit pci_wake_enabled(struct pci_dev *dev)
3569{
3570 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3571 u16 value;
3572
3573 if (!pm)
3574 return 0;
3575 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3576 return 0;
3577 return value & PCI_PM_CTRL_PME_ENABLE;
3578}
3579
cd28ab6a
SH		 3580static int __devinit sky2_probe(struct pci_dev *pdev,
3581 const struct pci_device_id *ent)
3582{
7f60c64b 3583 struct net_device *dev;
cd28ab6a 3584 struct sky2_hw *hw;
e3173832 3585 int err, using_dac = 0, wol_default;
cd28ab6a 3586
793b883e
SH		 3587 err = pci_enable_device(pdev);
3588 if (err) {
b02a9258 3589 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3590 goto err_out;
3591 }
3592
793b883e
SH		 3593 err = pci_request_regions(pdev, DRV_NAME);
3594 if (err) {
b02a9258 3595 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 3596 goto err_out_disable;
cd28ab6a
SH		 3597 }
3598
3599 pci_set_master(pdev);
3600
d1f3d4dd
SH		 3601 if (sizeof(dma_addr_t) > sizeof(u32) &&
3602 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3603 using_dac = 1;
3604 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3605 if (err < 0) {
b02a9258
SH		 3606 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3607 "for consistent allocations\n");
d1f3d4dd
SH		 3608 goto err_out_free_regions;
3609 }
d1f3d4dd 3610 } else {
cd28ab6a
SH		 3611 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3612 if (err) {
b02a9258 3613 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3614 goto err_out_free_regions;
3615 }
3616 }
d1f3d4dd 3617
e3173832
SH		 3618 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3619
cd28ab6a 3620 err = -ENOMEM;
6aad85d6 3621 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3622 if (!hw) {
b02a9258 3623 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3624 goto err_out_free_regions;
3625 }
3626
cd28ab6a 3627 hw->pdev = pdev;
cd28ab6a
SH		 3628
3629 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3630 if (!hw->regs) {
b02a9258 3631 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3632 goto err_out_free_hw;
3633 }
3634
56a645cc 3635#ifdef __BIG_ENDIAN
f65b138c
SH		 3636 /* The sk98lin vendor driver uses hardware byte swapping but
3637 * this driver uses software swapping.
3638 */
56a645cc
SH		 3639 {
3640 u32 reg;
56a645cc 3641 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3642 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3643 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3644 }
3645#endif
3646
08c06d8a
SH		 3647 /* ring for status responses */
3648 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3649 &hw->st_dma);
3650 if (!hw->st_le)
3651 goto err_out_iounmap;
3652
e3173832 3653 err = sky2_init(hw);
cd28ab6a 3654 if (err)
793b883e 3655 goto err_out_iounmap;
cd28ab6a 3656
b02a9258 3657 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3658 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3659 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3660 hw->chip_id, hw->chip_rev);
cd28ab6a 3661
e3173832
SH		 3662 sky2_reset(hw);
3663
3664 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3665 if (!dev) {
3666 err = -ENOMEM;
cd28ab6a 3667 goto err_out_free_pci;
7f60c64b 3668 }
cd28ab6a 3669
9fa1b1f3
SH		 3670 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3671 err = sky2_test_msi(hw);
3672 if (err == -EOPNOTSUPP)
3673 pci_disable_msi(pdev);
3674 else if (err)
3675 goto err_out_free_netdev;
3676 }
3677
793b883e
SH		 3678 err = register_netdev(dev);
3679 if (err) {
b02a9258 3680 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 3681 goto err_out_free_netdev;
3682 }
3683
b0a20ded
SH		 3684 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3685 dev->name, hw);
9fa1b1f3 3686 if (err) {
b02a9258 3687 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 3688 goto err_out_unregister;
3689 }
3690 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3691
cd28ab6a
SH		 3692 sky2_show_addr(dev);
3693
7f60c64b 3694 if (hw->ports > 1) {
3695 struct net_device *dev1;
3696
e3173832 3697 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 3698 if (!dev1)
3699 dev_warn(&pdev->dev, "allocation for second device failed\n");
3700 else if ((err = register_netdev(dev1))) {
3701 dev_warn(&pdev->dev,
3702 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 3703 hw->dev[1] = NULL;
3704 free_netdev(dev1);
b02a9258
SH		 3705 } else
3706 sky2_show_addr(dev1);
cd28ab6a
SH		 3707 }
3708
01bd7564 3709 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
81906791
SH		 3710 INIT_WORK(&hw->restart_work, sky2_restart);
3711
eb35cf60 3712 sky2_idle_start(hw);
d27ed387 3713
793b883e
SH		 3714 pci_set_drvdata(pdev, hw);
3715
cd28ab6a
SH		 3716 return 0;
3717
793b883e 3718err_out_unregister:
b0a20ded
SH		 3719 if (hw->msi)
3720 pci_disable_msi(pdev);
793b883e 3721 unregister_netdev(dev);
cd28ab6a
SH		 3722err_out_free_netdev:
3723 free_netdev(dev);
cd28ab6a 3724err_out_free_pci:
793b883e 3725 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3726 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3727err_out_iounmap:
3728 iounmap(hw->regs);
3729err_out_free_hw:
3730 kfree(hw);
3731err_out_free_regions:
3732 pci_release_regions(pdev);
44a1d2e5 3733err_out_disable:
cd28ab6a 3734 pci_disable_device(pdev);
cd28ab6a 3735err_out:
549a68c3 3736 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 3737 return err;
3738}
3739
3740static void __devexit sky2_remove(struct pci_dev *pdev)
3741{
793b883e 3742 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3743 struct net_device *dev0, *dev1;
3744
793b883e 3745 if (!hw)
cd28ab6a
SH		 3746 return;
3747
d27ed387
SH		 3748 del_timer_sync(&hw->idle_timer);
3749
81906791
SH		 3750 flush_scheduled_work();
3751
d27ed387 3752 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3753 synchronize_irq(hw->pdev->irq);
3754
cd28ab6a 3755 dev0 = hw->dev[0];
793b883e
SH		 3756 dev1 = hw->dev[1];
3757 if (dev1)
3758 unregister_netdev(dev1);
cd28ab6a
SH		 3759 unregister_netdev(dev0);
3760
ae306cca
SH		 3761 sky2_power_aux(hw);
3762
cd28ab6a 3763 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3764 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3765 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3766
3767 free_irq(pdev->irq, hw);
b0a20ded
SH		 3768 if (hw->msi)
3769 pci_disable_msi(pdev);
793b883e 3770 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3771 pci_release_regions(pdev);
3772 pci_disable_device(pdev);
793b883e 3773
cd28ab6a
SH		 3774 if (dev1)
3775 free_netdev(dev1);
3776 free_netdev(dev0);
3777 iounmap(hw->regs);
3778 kfree(hw);
5afa0a9c 3779
cd28ab6a
SH		 3780 pci_set_drvdata(pdev, NULL);
3781}
3782
3783#ifdef CONFIG_PM
3784static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3785{
793b883e 3786 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 3787 int i, wol = 0;
cd28ab6a 3788
549a68c3
SH		 3789 if (!hw)
3790 return 0;
3791
eb35cf60 3792 del_timer_sync(&hw->idle_timer);
6a5706b9 3793 netif_poll_disable(hw->dev[0]);
eb35cf60 3794
f05267e7 3795 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3796 struct net_device *dev = hw->dev[i];
e3173832 3797 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3798
e3173832 3799 if (netif_running(dev))
5afa0a9c 3800 sky2_down(dev);
e3173832
SH		 3801
3802 if (sky2->wol)
3803 sky2_wol_init(sky2);
3804
3805 wol |= sky2->wol;
cd28ab6a
SH		 3806 }
3807
8ab8fca2 3808 sky2_write32(hw, B0_IMSK, 0);
ae306cca 3809 sky2_power_aux(hw);
e3173832 3810
d374c1c1 3811 pci_save_state(pdev);
e3173832 3812 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 3813 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3814
2ccc99b7 3815 return 0;
cd28ab6a
SH		 3816}
3817
3818static int sky2_resume(struct pci_dev *pdev)
3819{
793b883e 3820 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3821 int i, err;
cd28ab6a 3822
549a68c3
SH		 3823 if (!hw)
3824 return 0;
3825
ae306cca
SH		 3826 err = pci_set_power_state(pdev, PCI_D0);
3827 if (err)
3828 goto out;
3829
3830 err = pci_restore_state(pdev);
3831 if (err)
3832 goto out;
3833
cd28ab6a 3834 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 3835
3836 /* Re-enable all clocks */
3837 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3838 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3839
e3173832 3840 sky2_reset(hw);
cd28ab6a 3841
8ab8fca2
SH		 3842 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3843
f05267e7 3844 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3845 struct net_device *dev = hw->dev[i];
6a5706b9 3846 if (netif_running(dev)) {
08c06d8a
SH		 3847 err = sky2_up(dev);
3848 if (err) {
3849 printk(KERN_ERR PFX "%s: could not up: %d\n",
3850 dev->name, err);
3851 dev_close(dev);
eb35cf60 3852 goto out;
5afa0a9c 3853 }
cd28ab6a
SH		 3854 }
3855 }
eb35cf60 3856
6a5706b9 3857 netif_poll_enable(hw->dev[0]);
eb35cf60 3858 sky2_idle_start(hw);
ae306cca 3859 return 0;
08c06d8a 3860out:
b02a9258 3861 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 3862 pci_disable_device(pdev);
08c06d8a 3863 return err;
cd28ab6a
SH		 3864}
3865#endif
3866
e3173832
SH		 3867static void sky2_shutdown(struct pci_dev *pdev)
3868{
3869 struct sky2_hw *hw = pci_get_drvdata(pdev);
3870 int i, wol = 0;
3871
549a68c3
SH		 3872 if (!hw)
3873 return;
3874
e3173832
SH		 3875 del_timer_sync(&hw->idle_timer);
3876 netif_poll_disable(hw->dev[0]);
3877
3878 for (i = 0; i < hw->ports; i++) {
3879 struct net_device *dev = hw->dev[i];
3880 struct sky2_port *sky2 = netdev_priv(dev);
3881
3882 if (sky2->wol) {
3883 wol = 1;
3884 sky2_wol_init(sky2);
3885 }
3886 }
3887
3888 if (wol)
3889 sky2_power_aux(hw);
3890
3891 pci_enable_wake(pdev, PCI_D3hot, wol);
3892 pci_enable_wake(pdev, PCI_D3cold, wol);
3893
3894 pci_disable_device(pdev);
3895 pci_set_power_state(pdev, PCI_D3hot);
3896
3897}
3898
cd28ab6a 3899static struct pci_driver sky2_driver = {
793b883e
SH		 3900 .name = DRV_NAME,
3901 .id_table = sky2_id_table,
3902 .probe = sky2_probe,
3903 .remove = __devexit_p(sky2_remove),
cd28ab6a 3904#ifdef CONFIG_PM
793b883e
SH		 3905 .suspend = sky2_suspend,
3906 .resume = sky2_resume,
cd28ab6a 3907#endif
e3173832 3908 .shutdown = sky2_shutdown,
cd28ab6a
SH		 3909};
3910
3911static int __init sky2_init_module(void)
3912{
50241c4c 3913 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3914}
3915
3916static void __exit sky2_cleanup_module(void)
3917{
3918 pci_unregister_driver(&sky2_driver);
3919}
3920
3921module_init(sky2_init_module);
3922module_exit(sky2_cleanup_module);
3923
3924MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 3925MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 3926MODULE_LICENSE("GPL");
5f4f9dc1 3927MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree