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sky2: Factor out code to calculate packet sizes
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
ac958154 53#define DRV_VERSION "1.26"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 66
ee5f68fe 67/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
ee5f68fe
SH		 71#define TX_MAX_PENDING 4096
72#define TX_DEF_PENDING 127
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
e6cac9ba 102static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 144 { 0 }
145};
793b883e 146
cd28ab6a
SH		 147MODULE_DEVICE_TABLE(pci, sky2_id_table);
148
149/* Avoid conditionals by using array */
150static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 152static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 153
d1b139c0
SH		 154static void sky2_set_multicast(struct net_device *dev);
155
af043aa5 156/* Access to PHY via serial interconnect */
ef743d33 157static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 158{
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 166 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
167 if (ctrl == 0xffff)
168 goto io_error;
169
170 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 171 return 0;
af043aa5
SH		 172
173 udelay(10);
cd28ab6a 174 }
ef743d33 175
af043aa5 176 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 177 return -ETIMEDOUT;
af043aa5
SH		 178
179io_error:
180 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
181 return -EIO;
cd28ab6a
SH		 182}
183
ef743d33 184static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 185{
186 int i;
187
793b883e 188 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 189 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
190
191 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 192 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
193 if (ctrl == 0xffff)
194 goto io_error;
195
196 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 197 *val = gma_read16(hw, port, GM_SMI_DATA);
198 return 0;
199 }
200
af043aa5 201 udelay(10);
cd28ab6a
SH		 202 }
203
af043aa5 204 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 205 return -ETIMEDOUT;
af043aa5
SH		 206io_error:
207 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
208 return -EIO;
ef743d33
SH		 209}
210
af043aa5 211static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 212{
213 u16 v;
af043aa5 214 __gm_phy_read(hw, port, reg, &v);
ef743d33 215 return v;
cd28ab6a
SH		 216}
217
5afa0a9c 218
ae306cca
SH		 219static void sky2_power_on(struct sky2_hw *hw)
220{
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw, B0_POWER_CTRL,
223 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 224
ae306cca
SH		 225 /* disable Core Clock Division, */
226 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 227
ae306cca
SH		 228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 /* enable bits are inverted */
230 sky2_write8(hw, B2_Y2_CLK_GATE,
231 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
232 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
233 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
234 else
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 236
ea76e635 237 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 238 u32 reg;
5afa0a9c 239
b32f40c4 240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 241
b32f40c4 242 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 245 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 246
b32f40c4 247 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 248 /* set all bits to 0 except bits 28 & 27 */
249 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 250 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 251
b32f40c4 252 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 253
5f8ae5c5 254 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
255
8f70920f
SH		 256 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
257 reg = sky2_read32(hw, B2_GP_IO);
258 reg |= GLB_GPIO_STAT_RACE_DIS;
259 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 260
261 sky2_read32(hw, B2_GP_IO);
5afa0a9c 262 }
10547ae2
SH		 263
264 /* Turn on "driver loaded" LED */
265 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 266}
5afa0a9c 267
ae306cca
SH		 268static void sky2_power_aux(struct sky2_hw *hw)
269{
270 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
271 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
272 else
273 /* enable bits are inverted */
274 sky2_write8(hw, B2_Y2_CLK_GATE,
275 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
276 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
277 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
278
c23ddf8f
SH		 279 /* switch power to VAUX if supported and PME from D3cold */
280 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
281 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 282 sky2_write8(hw, B0_POWER_CTRL,
283 (PC_VAUX_ENA | PC_VCC_ENA |
284 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 285
286 /* turn off "driver loaded LED" */
287 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c
SH		 288}
289
d3bcfbeb 290static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 291{
292 u16 reg;
293
294 /* disable all GMAC IRQ's */
295 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 296
cd28ab6a
SH		 297 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
298 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
299 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
300 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
301
302 reg = gma_read16(hw, port, GM_RX_CTRL);
303 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
304 gma_write16(hw, port, GM_RX_CTRL, reg);
305}
306
16ad91e1
SH		 307/* flow control to advertise bits */
308static const u16 copper_fc_adv[] = {
309 [FC_NONE] = 0,
310 [FC_TX] = PHY_M_AN_ASP,
311 [FC_RX] = PHY_M_AN_PC,
312 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
313};
314
315/* flow control to advertise bits when using 1000BaseX */
316static const u16 fiber_fc_adv[] = {
df3fe1f3 317 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 318 [FC_TX] = PHY_M_P_ASYM_MD_X,
319 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 320 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 321};
322
323/* flow control to GMA disable bits */
324static const u16 gm_fc_disable[] = {
325 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
326 [FC_TX] = GM_GPCR_FC_RX_DIS,
327 [FC_RX] = GM_GPCR_FC_TX_DIS,
328 [FC_BOTH] = 0,
329};
330
331
cd28ab6a
SH		 332static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
333{
334 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 335 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 336
0ea065e5 337 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 338 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 339 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
340
341 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 342 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 343 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
344
53419c68 345 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 346 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 347 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 348 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
349 else
53419c68
SH		 350 /* set master & slave downshift counter to 1x */
351 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 352
353 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
354 }
355
356 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 357 if (sky2_is_copper(hw)) {
05745c4a 358 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 359 /* enable automatic crossover */
360 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 361
362 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
363 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
364 u16 spec;
365
366 /* Enable Class A driver for FE+ A0 */
367 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
368 spec |= PHY_M_FESC_SEL_CL_A;
369 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
370 }
cd28ab6a
SH		 371 } else {
372 /* disable energy detect */
373 ctrl &= ~PHY_M_PC_EN_DET_MSK;
374
375 /* enable automatic crossover */
376 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
377
53419c68 378 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 379 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
380 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 381 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 382 ctrl &= ~PHY_M_PC_DSC_MSK;
383 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
384 }
385 }
cd28ab6a
SH		 386 } else {
387 /* workaround for deviation #4.88 (CRC errors) */
388 /* disable Automatic Crossover */
389
390 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 391 }
cd28ab6a 392
b89165f2
SH		 393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
394
395 /* special setup for PHY 88E1112 Fiber */
ea76e635 396 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 397 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 398
b89165f2
SH		 399 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
400 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
401 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
402 ctrl &= ~PHY_M_MAC_MD_MSK;
403 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
404 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
405
406 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 407 /* select page 1 to access Fiber registers */
408 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 409
410 /* for SFP-module set SIGDET polarity to low */
411 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
412 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 413 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 414 }
b89165f2
SH		 415
416 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 417 }
418
7800fddc 419 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 420 ct1000 = 0;
421 adv = PHY_AN_CSMA;
2eaba1a2 422 reg = 0;
cd28ab6a 423
0ea065e5 424 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 425 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 426 if (sky2->advertising & ADVERTISED_1000baseT_Full)
427 ct1000 |= PHY_M_1000C_AFD;
428 if (sky2->advertising & ADVERTISED_1000baseT_Half)
429 ct1000 |= PHY_M_1000C_AHD;
430 if (sky2->advertising & ADVERTISED_100baseT_Full)
431 adv |= PHY_M_AN_100_FD;
432 if (sky2->advertising & ADVERTISED_100baseT_Half)
433 adv |= PHY_M_AN_100_HD;
434 if (sky2->advertising & ADVERTISED_10baseT_Full)
435 adv |= PHY_M_AN_10_FD;
436 if (sky2->advertising & ADVERTISED_10baseT_Half)
437 adv |= PHY_M_AN_10_HD;
709c6e7b 438
b89165f2
SH		 439 } else { /* special defines for FIBER (88E1040S only) */
440 if (sky2->advertising & ADVERTISED_1000baseT_Full)
441 adv |= PHY_M_AN_1000X_AFD;
442 if (sky2->advertising & ADVERTISED_1000baseT_Half)
443 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 444 }
cd28ab6a
SH		 445
446 /* Restart Auto-negotiation */
447 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
448 } else {
449 /* forced speed/duplex settings */
450 ct1000 = PHY_M_1000C_MSE;
451
0ea065e5
SH		 452 /* Disable auto update for duplex flow control and duplex */
453 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 454
455 switch (sky2->speed) {
456 case SPEED_1000:
457 ctrl |= PHY_CT_SP1000;
2eaba1a2 458 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 459 break;
460 case SPEED_100:
461 ctrl |= PHY_CT_SP100;
2eaba1a2 462 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 463 break;
464 }
465
2eaba1a2
SH		 466 if (sky2->duplex == DUPLEX_FULL) {
467 reg |= GM_GPCR_DUP_FULL;
468 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 469 } else if (sky2->speed < SPEED_1000)
470 sky2->flow_mode = FC_NONE;
0ea065e5 471 }
2eaba1a2 472
0ea065e5
SH		 473 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
474 if (sky2_is_copper(hw))
475 adv |= copper_fc_adv[sky2->flow_mode];
476 else
477 adv |= fiber_fc_adv[sky2->flow_mode];
478 } else {
479 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 480 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 481
482 /* Forward pause packets to GMAC? */
16ad91e1 483 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 484 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
485 else
486 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 487 }
488
2eaba1a2
SH		 489 gma_write16(hw, port, GM_GP_CTRL, reg);
490
05745c4a 491 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 492 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
493
494 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
495 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
496
497 /* Setup Phy LED's */
498 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
499 ledover = 0;
500
501 switch (hw->chip_id) {
502 case CHIP_ID_YUKON_FE:
503 /* on 88E3082 these bits are at 11..9 (shifted left) */
504 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
505
506 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
507
508 /* delete ACT LED control bits */
509 ctrl &= ~PHY_M_FELP_LED1_MSK;
510 /* change ACT LED control to blink mode */
511 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
05745c4a
SH		 515 case CHIP_ID_YUKON_FE_P:
516 /* Enable Link Partner Next Page */
517 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
518 ctrl |= PHY_M_PC_ENA_LIP_NP;
519
520 /* disable Energy Detect and enable scrambler */
521 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
523
524 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
525 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
526 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
527 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
528
529 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
530 break;
531
cd28ab6a 532 case CHIP_ID_YUKON_XL:
793b883e 533 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 534
535 /* select page 3 to access LED control register */
536 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
537
538 /* set LED Function Control register */
ed6d32c7
SH		 539 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
540 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
541 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
542 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
543 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 544
545 /* set Polarity Control register */
546 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 547 (PHY_M_POLC_LS1_P_MIX(4) |
548 PHY_M_POLC_IS0_P_MIX(4) |
549 PHY_M_POLC_LOS_CTRL(2) |
550 PHY_M_POLC_INIT_CTRL(2) |
551 PHY_M_POLC_STA1_CTRL(2) |
552 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 553
554 /* restore page register */
793b883e 555 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 556 break;
93745494 557
ed6d32c7 558 case CHIP_ID_YUKON_EC_U:
93745494 559 case CHIP_ID_YUKON_EX:
ed4d4161 560 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 561 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
562
563 /* select page 3 to access LED control register */
564 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
565
566 /* set LED Function Control register */
567 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
568 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
569 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
570 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
571 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
572
573 /* set Blink Rate in LED Timer Control Register */
574 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
575 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
576 /* restore page register */
577 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
578 break;
cd28ab6a
SH		 579
580 default:
581 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
582 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 583
cd28ab6a 584 /* turn off the Rx LED (LED_RX) */
a84d0a3d 585 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 586 }
587
0ce8b98d 588 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 589 /* apply fixes in PHY AFE */
ed6d32c7
SH		 590 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
591
977bdf06 592 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 593 gm_phy_write(hw, port, 0x18, 0xaa99);
594 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 595
0ce8b98d
SH		 596 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
597 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
598 gm_phy_write(hw, port, 0x18, 0xa204);
599 gm_phy_write(hw, port, 0x17, 0x2002);
600 }
977bdf06
SH		 601
602 /* set page register to 0 */
9467a8fc 603 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 604 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
605 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
606 /* apply workaround for integrated resistors calibration */
607 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
608 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 609 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
610 /* apply fixes in PHY AFE */
611 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
612
613 /* apply RDAC termination workaround */
614 gm_phy_write(hw, port, 24, 0x2800);
615 gm_phy_write(hw, port, 23, 0x2001);
616
617 /* set page register back to 0 */
618 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 619 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
620 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 621 /* no effect on Yukon-XL */
977bdf06 622 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 623
8e95a202
JP		 624 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
625 sky2->speed == SPEED_100) {
977bdf06 626 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 627 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 628 }
cd28ab6a 629
977bdf06
SH		 630 if (ledover)
631 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
632
633 }
2eaba1a2 634
d571b694 635 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 636 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 637 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
638 else
639 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
640}
641
b96936da
SH		 642static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
643static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
644
645static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 646{
647 u32 reg1;
d3bcfbeb 648
a40ccc68 649 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 650 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 651 reg1 &= ~phy_power[port];
d3bcfbeb 652
b96936da 653 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 654 reg1 |= coma_mode[port];
655
b32f40c4 656 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 657 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 658 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 659
660 if (hw->chip_id == CHIP_ID_YUKON_FE)
661 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
662 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
663 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 664}
167f53d0 665
b96936da
SH		 666static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
667{
668 u32 reg1;
db99b988
SH		 669 u16 ctrl;
670
671 /* release GPHY Control reset */
672 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
673
674 /* release GMAC reset */
675 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
676
677 if (hw->flags & SKY2_HW_NEWER_PHY) {
678 /* select page 2 to access MAC control register */
679 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
680
681 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
682 /* allow GMII Power Down */
683 ctrl &= ~PHY_M_MAC_GMIF_PUP;
684 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
685
686 /* set page register back to 0 */
687 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
688 }
689
690 /* setup General Purpose Control Register */
691 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 692 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
693 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
694 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 695
696 if (hw->chip_id != CHIP_ID_YUKON_EC) {
697 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 698 /* select page 2 to access MAC control register */
699 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 700
e484d5f5 701 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 702 /* enable Power Down */
703 ctrl |= PHY_M_PC_POW_D_ENA;
704 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 705
706 /* set page register back to 0 */
707 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 708 }
709
710 /* set IEEE compatible Power Down Mode (dev. #4.99) */
711 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
712 }
b96936da 713
a40ccc68 714 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 715 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 716 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 717 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 718 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 719}
720
1b537565
SH		 721/* Force a renegotiation */
722static void sky2_phy_reinit(struct sky2_port *sky2)
723{
e07b1aa8 724 spin_lock_bh(&sky2->phy_lock);
1b537565 725 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 726 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 727}
728
e3173832
SH		 729/* Put device in state to listen for Wake On Lan */
730static void sky2_wol_init(struct sky2_port *sky2)
731{
732 struct sky2_hw *hw = sky2->hw;
733 unsigned port = sky2->port;
734 enum flow_control save_mode;
735 u16 ctrl;
e3173832
SH		 736
737 /* Bring hardware out of reset */
738 sky2_write16(hw, B0_CTST, CS_RST_CLR);
739 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
740
741 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
742 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
743
744 /* Force to 10/100
745 * sky2_reset will re-enable on resume
746 */
747 save_mode = sky2->flow_mode;
748 ctrl = sky2->advertising;
749
750 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
751 sky2->flow_mode = FC_NONE;
b96936da
SH		 752
753 spin_lock_bh(&sky2->phy_lock);
754 sky2_phy_power_up(hw, port);
755 sky2_phy_init(hw, port);
756 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 757
758 sky2->flow_mode = save_mode;
759 sky2->advertising = ctrl;
760
761 /* Set GMAC to no flow control and auto update for speed/duplex */
762 gma_write16(hw, port, GM_GP_CTRL,
763 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
764 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
765
766 /* Set WOL address */
767 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
768 sky2->netdev->dev_addr, ETH_ALEN);
769
770 /* Turn on appropriate WOL control bits */
771 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
772 ctrl = 0;
773 if (sky2->wol & WAKE_PHY)
774 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
775 else
776 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
777
778 if (sky2->wol & WAKE_MAGIC)
779 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
780 else
a419aef8 781 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 782
783 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
784 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
785
5f8ae5c5 786 /* Disable PiG firmware */
787 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
788
e3173832
SH		 789 /* block receiver */
790 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
e3173832
SH		 791}
792
69161611
SH		 793static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
794{
05745c4a
SH		 795 struct net_device *dev = hw->dev[port];
796
ed4d4161
SH		 797 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
798 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 799 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161 800 /* Yukon-Extreme B0 and further Extreme devices */
44dde56d 801 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
802 } else if (dev->mtu > ETH_DATA_LEN) {
803 /* set Tx GMAC FIFO Almost Empty Threshold */
804 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
805 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
05745c4a 806
44dde56d 807 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
808 } else
809 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
69161611
SH		 810}
811
cd28ab6a
SH		 812static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
813{
814 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
815 u16 reg;
25cccecc 816 u32 rx_reg;
cd28ab6a
SH		 817 int i;
818 const u8 *addr = hw->dev[port]->dev_addr;
819
f350339c
SH		 820 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
821 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 822
823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
824
793b883e 825 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 826 /* WA DEV_472 -- looks like crossed wires on port 2 */
827 /* clear GMAC 1 Control reset */
828 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
829 do {
830 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
831 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
832 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
833 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
834 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
835 }
836
793b883e 837 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 838
2eaba1a2
SH		 839 /* Enable Transmit FIFO Underrun */
840 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
841
e07b1aa8 842 spin_lock_bh(&sky2->phy_lock);
b96936da 843 sky2_phy_power_up(hw, port);
cd28ab6a 844 sky2_phy_init(hw, port);
e07b1aa8 845 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 846
847 /* MIB clear */
848 reg = gma_read16(hw, port, GM_PHY_ADDR);
849 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
850
43f2f104
SH		 851 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
852 gma_read16(hw, port, i);
cd28ab6a
SH		 853 gma_write16(hw, port, GM_PHY_ADDR, reg);
854
855 /* transmit control */
856 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
857
858 /* receive control reg: unicast + multicast + no FCS */
859 gma_write16(hw, port, GM_RX_CTRL,
793b883e 860 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 861
862 /* transmit flow control */
863 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
864
865 /* transmit parameter */
866 gma_write16(hw, port, GM_TX_PARAM,
867 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
868 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
869 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
870 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
871
872 /* serial mode register */
873 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 874 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 875
6b1a3aef 876 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 877 reg |= GM_SMOD_JUMBO_ENA;
878
879 gma_write16(hw, port, GM_SERIAL_MODE, reg);
880
cd28ab6a
SH		 881 /* virtual address for data */
882 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
883
793b883e
SH		 884 /* physical address: used for pause frames */
885 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
886
887 /* ignore counter overflows */
cd28ab6a
SH		 888 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
889 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
890 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
891
892 /* Configure Rx MAC FIFO */
893 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 894 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 895 if (hw->chip_id == CHIP_ID_YUKON_EX ||
896 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 897 rx_reg |= GMF_RX_OVER_ON;
69161611 898
25cccecc 899 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 900
798fdd07
SH		 901 if (hw->chip_id == CHIP_ID_YUKON_XL) {
902 /* Hardware errata - clear flush mask */
903 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
904 } else {
905 /* Flush Rx MAC FIFO on any flow control or error */
906 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
907 }
cd28ab6a 908
8df9a876 909 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 910 reg = RX_GMF_FL_THR_DEF + 1;
911 /* Another magic mystery workaround from sk98lin */
912 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
913 hw->chip_rev == CHIP_REV_YU_FE2_A0)
914 reg = 0x178;
915 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 916
917 /* Configure Tx MAC FIFO */
918 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
919 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 920
e0c28116 921 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 922 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 923 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 924 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
925 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 926 reg = 1568 / 8;
927 else
928 reg = 1024 / 8;
929 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
930 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 931
69161611 932 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 933 }
934
e970d1f8
SH		 935 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
936 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
937 /* disable dynamic watermark */
938 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
939 reg &= ~TX_DYN_WM_ENA;
940 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
941 }
cd28ab6a
SH		 942}
943
67712901
SH		 944/* Assign Ram Buffer allocation to queue */
945static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 946{
67712901
SH		 947 u32 end;
948
949 /* convert from K bytes to qwords used for hw register */
950 start *= 1024/8;
951 space *= 1024/8;
952 end = start + space - 1;
793b883e 953
cd28ab6a
SH		 954 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
955 sky2_write32(hw, RB_ADDR(q, RB_START), start);
956 sky2_write32(hw, RB_ADDR(q, RB_END), end);
957 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
958 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
959
960 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 961 u32 tp = space - space/4;
793b883e 962
1c28f6ba
SH		 963 /* On receive queue's set the thresholds
964 * give receiver priority when > 3/4 full
965 * send pause when down to 2K
966 */
967 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
968 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 969
1c28f6ba
SH		 970 tp = space - 2048/8;
971 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
972 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 973 } else {
974 /* Enable store & forward on Tx queue's because
975 * Tx FIFO is only 1K on Yukon
976 */
977 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
978 }
979
980 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 981 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 982}
983
cd28ab6a 984/* Setup Bus Memory Interface */
af4ed7e6 985static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 986{
987 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
988 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
989 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 990 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 991}
992
cd28ab6a
SH		 993/* Setup prefetch unit registers. This is the interface between
994 * hardware and driver list elements
995 */
8cc048e3 996static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 997 dma_addr_t addr, u32 last)
cd28ab6a 998{
cd28ab6a
SH		 999 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1000 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1001 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1002 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1003 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1004 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1005
1006 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1007}
1008
9b289c33 1009static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1010{
9b289c33 1011 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1012
ee5f68fe 1013 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1014 le->ctrl = 0;
793b883e
SH		 1015 return le;
1016}
cd28ab6a 1017
88f5f0ca
SH		 1018static void tx_init(struct sky2_port *sky2)
1019{
1020 struct sky2_tx_le *le;
1021
1022 sky2->tx_prod = sky2->tx_cons = 0;
1023 sky2->tx_tcpsum = 0;
1024 sky2->tx_last_mss = 0;
1025
9b289c33 1026 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1027 le->addr = 0;
1028 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1029 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1030}
1031
290d4de5
SH		 1032/* Update chip's next pointer */
1033static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1034{
50432cb5 1035 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1036 wmb();
50432cb5
SH		 1037 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1038
1039 /* Synchronize I/O on since next processor may write to tail */
1040 mmiowb();
cd28ab6a
SH		 1041}
1042
793b883e 1043
cd28ab6a
SH		 1044static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1045{
1046 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1047 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1048 le->ctrl = 0;
cd28ab6a
SH		 1049 return le;
1050}
1051
39ef110b
MM		 1052static unsigned sky2_get_rx_threshold(struct sky2_port* sky2)
1053{
1054 unsigned size;
1055
1056 /* Space needed for frame data + headers rounded up */
1057 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1058
1059 /* Stopping point for hardware truncation */
1060 return (size - 8) / sizeof(u32);
1061}
1062
1063static unsigned sky2_get_rx_data_size(struct sky2_port* sky2)
1064{
1065 struct rx_ring_info *re;
1066 unsigned size;
1067
1068 /* Space needed for frame data + headers rounded up */
1069 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1070
1071 sky2->rx_nfrags = size >> PAGE_SHIFT;
1072 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1073
1074 /* Compute residue after pages */
1075 size -= sky2->rx_nfrags << PAGE_SHIFT;
1076
1077 /* Optimize to handle small packets and headers */
1078 if (size < copybreak)
1079 size = copybreak;
1080 if (size < ETH_HLEN)
1081 size = ETH_HLEN;
1082
1083 return size;
1084}
1085
14d0263f
SH		 1086/* Build description to hardware for one receive segment */
1087static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1088 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1089{
1090 struct sky2_rx_le *le;
1091
86c6887e 1092 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1093 le = sky2_next_rx(sky2);
86c6887e 1094 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1095 le->opcode = OP_ADDR64 | HW_OWNER;
1096 }
793b883e 1097
cd28ab6a 1098 le = sky2_next_rx(sky2);
d6e74b6b 1099 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1100 le->length = cpu_to_le16(len);
14d0263f 1101 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1102}
1103
14d0263f
SH		 1104/* Build description to hardware for one possibly fragmented skb */
1105static void sky2_rx_submit(struct sky2_port *sky2,
1106 const struct rx_ring_info *re)
1107{
1108 int i;
1109
1110 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1111
1112 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1113 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1114}
1115
1116
454e6cb6 1117static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1118 unsigned size)
1119{
1120 struct sk_buff *skb = re->skb;
1121 int i;
1122
1123 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1124 if (pci_dma_mapping_error(pdev, re->data_addr))
1125 goto mapping_error;
454e6cb6 1126
14d0263f
SH		 1127 pci_unmap_len_set(re, data_size, size);
1128
3fbd9187 1129 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1130 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1131
1132 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1133 frag->page_offset,
1134 frag->size,
14d0263f 1135 PCI_DMA_FROMDEVICE);
3fbd9187 1136
1137 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1138 goto map_page_error;
1139 }
454e6cb6 1140 return 0;
3fbd9187 1141
1142map_page_error:
1143 while (--i >= 0) {
1144 pci_unmap_page(pdev, re->frag_addr[i],
1145 skb_shinfo(skb)->frags[i].size,
1146 PCI_DMA_FROMDEVICE);
1147 }
1148
1149 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1150 PCI_DMA_FROMDEVICE);
1151
1152mapping_error:
1153 if (net_ratelimit())
1154 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1155 skb->dev->name);
1156 return -EIO;
14d0263f
SH		 1157}
1158
1159static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1160{
1161 struct sk_buff *skb = re->skb;
1162 int i;
1163
1164 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1165 PCI_DMA_FROMDEVICE);
1166
1167 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1168 pci_unmap_page(pdev, re->frag_addr[i],
1169 skb_shinfo(skb)->frags[i].size,
1170 PCI_DMA_FROMDEVICE);
1171}
793b883e 1172
cd28ab6a
SH		 1173/* Tell chip where to start receive checksum.
1174 * Actually has two checksums, but set both same to avoid possible byte
1175 * order problems.
1176 */
793b883e 1177static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1178{
ea76e635 1179 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1180
ea76e635
SH		 1181 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1182 le->ctrl = 0;
1183 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1184
ea76e635
SH		 1185 sky2_write32(sky2->hw,
1186 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1187 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1188 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1189}
1190
6b1a3aef
SH		 1191/*
1192 * The RX Stop command will not work for Yukon-2 if the BMU does not
1193 * reach the end of packet and since we can't make sure that we have
1194 * incoming data, we must reset the BMU while it is not doing a DMA
1195 * transfer. Since it is possible that the RX path is still active,
1196 * the RX RAM buffer will be stopped first, so any possible incoming
1197 * data will not trigger a DMA. After the RAM buffer is stopped, the
1198 * BMU is polled until any DMA in progress is ended and only then it
1199 * will be reset.
1200 */
1201static void sky2_rx_stop(struct sky2_port *sky2)
1202{
1203 struct sky2_hw *hw = sky2->hw;
1204 unsigned rxq = rxqaddr[sky2->port];
1205 int i;
1206
1207 /* disable the RAM Buffer receive queue */
1208 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1209
1210 for (i = 0; i < 0xffff; i++)
1211 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1212 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1213 goto stopped;
1214
1215 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1216 sky2->netdev->name);
1217stopped:
1218 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1219
1220 /* reset the Rx prefetch unit */
1221 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1222 mmiowb();
6b1a3aef 1223}
793b883e 1224
d571b694 1225/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1226static void sky2_rx_clean(struct sky2_port *sky2)
1227{
1228 unsigned i;
1229
1230 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1231 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1232 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1233
1234 if (re->skb) {
14d0263f 1235 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1236 kfree_skb(re->skb);
1237 re->skb = NULL;
1238 }
1239 }
1240}
1241
ef743d33
SH		 1242/* Basic MII support */
1243static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1244{
1245 struct mii_ioctl_data *data = if_mii(ifr);
1246 struct sky2_port *sky2 = netdev_priv(dev);
1247 struct sky2_hw *hw = sky2->hw;
1248 int err = -EOPNOTSUPP;
1249
1250 if (!netif_running(dev))
1251 return -ENODEV; /* Phy still in reset */
1252
d89e1343 1253 switch (cmd) {
ef743d33
SH		 1254 case SIOCGMIIPHY:
1255 data->phy_id = PHY_ADDR_MARV;
1256
1257 /* fallthru */
1258 case SIOCGMIIREG: {
1259 u16 val = 0;
91c86df5 1260
e07b1aa8 1261 spin_lock_bh(&sky2->phy_lock);
ef743d33 1262 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1263 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1264
ef743d33
SH		 1265 data->val_out = val;
1266 break;
1267 }
1268
1269 case SIOCSMIIREG:
e07b1aa8 1270 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1271 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1272 data->val_in);
e07b1aa8 1273 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1274 break;
1275 }
1276 return err;
1277}
1278
d1f13708 1279#ifdef SKY2_VLAN_TAG_USED
d494eacd 1280static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1281{
d494eacd 1282 if (onoff) {
3d4e66f5
SH		 1283 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1284 RX_VLAN_STRIP_ON);
1285 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1286 TX_VLAN_TAG_ON);
1287 } else {
1288 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1289 RX_VLAN_STRIP_OFF);
1290 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1291 TX_VLAN_TAG_OFF);
1292 }
d494eacd
SH		 1293}
1294
1295static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1296{
1297 struct sky2_port *sky2 = netdev_priv(dev);
1298 struct sky2_hw *hw = sky2->hw;
1299 u16 port = sky2->port;
1300
1301 netif_tx_lock_bh(dev);
1302 napi_disable(&hw->napi);
1303
1304 sky2->vlgrp = grp;
1305 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1306
d1d08d12 1307 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1308 napi_enable(&hw->napi);
2bb8c262 1309 netif_tx_unlock_bh(dev);
d1f13708
SH		 1310}
1311#endif
1312
bd1c6869
SH		 1313/* Amount of required worst case padding in rx buffer */
1314static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1315{
1316 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1317}
1318
82788c7a 1319/*
14d0263f
SH		 1320 * Allocate an skb for receiving. If the MTU is large enough
1321 * make the skb non-linear with a fragment list of pages.
82788c7a 1322 */
14d0263f 1323static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1324{
1325 struct sk_buff *skb;
14d0263f 1326 int i;
82788c7a 1327
724b6942
SH		 1328 skb = netdev_alloc_skb(sky2->netdev,
1329 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1330 if (!skb)
1331 goto nomem;
1332
39dbd958 1333 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1334 unsigned char *start;
1335 /*
1336 * Workaround for a bug in FIFO that cause hang
1337 * if the FIFO if the receive buffer is not 64 byte aligned.
1338 * The buffer returned from netdev_alloc_skb is
1339 * aligned except if slab debugging is enabled.
1340 */
f03b8654
SH		 1341 start = PTR_ALIGN(skb->data, 8);
1342 skb_reserve(skb, start - skb->data);
bd1c6869 1343 } else
f03b8654 1344 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1345
1346 for (i = 0; i < sky2->rx_nfrags; i++) {
1347 struct page *page = alloc_page(GFP_ATOMIC);
1348
1349 if (!page)
1350 goto free_partial;
1351 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1352 }
1353
1354 return skb;
14d0263f
SH		 1355free_partial:
1356 kfree_skb(skb);
1357nomem:
1358 return NULL;
82788c7a
SH		 1359}
1360
55c9dd35
SH		 1361static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1362{
1363 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1364}
1365
cd28ab6a
SH		 1366/*
1367 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1368 * Normal case this ends up creating one list element for skb
1369 * in the receive ring. Worst case if using large MTU and each
1370 * allocation falls on a different 64 bit region, that results
1371 * in 6 list elements per ring entry.
1372 * One element is used for checksum enable/disable, and one
1373 * extra to avoid wrap.
cd28ab6a 1374 */
6b1a3aef 1375static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1376{
6b1a3aef 1377 struct sky2_hw *hw = sky2->hw;
14d0263f 1378 struct rx_ring_info *re;
6b1a3aef 1379 unsigned rxq = rxqaddr[sky2->port];
39ef110b 1380 unsigned i, thresh;
cd28ab6a 1381
6b1a3aef 1382 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1383 sky2_qset(hw, rxq);
977bdf06 1384
c3905bc4
SH		 1385 /* On PCI express lowering the watermark gives better performance */
1386 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1387 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1388
1389 /* These chips have no ram buffer?
1390 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1391 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
8e95a202
JP		 1392 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1393 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1394 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1395
6b1a3aef
SH		 1396 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1397
ea76e635
SH		 1398 if (!(hw->flags & SKY2_HW_NEW_LE))
1399 rx_set_checksum(sky2);
14d0263f 1400
39ef110b 1401 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
14d0263f
SH		 1402
1403 /* Fill Rx ring */
793b883e 1404 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1405 re = sky2->rx_ring + i;
cd28ab6a 1406
14d0263f 1407 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1408 if (!re->skb)
1409 goto nomem;
1410
454e6cb6
SH		 1411 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1412 dev_kfree_skb(re->skb);
1413 re->skb = NULL;
1414 goto nomem;
1415 }
1416
14d0263f 1417 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1418 }
1419
a1433ac4
SH		 1420 /*
1421 * The receiver hangs if it receives frames larger than the
1422 * packet buffer. As a workaround, truncate oversize frames, but
1423 * the register is limited to 9 bits, so if you do frames > 2052
1424 * you better get the MTU right!
1425 */
39ef110b 1426 thresh = sky2_get_rx_threshold(sky2);
a1433ac4
SH		 1427 if (thresh > 0x1ff)
1428 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1429 else {
1430 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1431 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1432 }
1433
6b1a3aef 1434 /* Tell chip about available buffers */
55c9dd35 1435 sky2_rx_update(sky2, rxq);
877c8570
SH		 1436
1437 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1438 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1439 /*
1440 * Disable flushing of non ASF packets;
1441 * must be done after initializing the BMUs;
1442 * drivers without ASF support should do this too, otherwise
1443 * it may happen that they cannot run on ASF devices;
1444 * remember that the MAC FIFO isn't reset during initialization.
1445 */
1446 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1447 }
1448
1449 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1450 /* Enable RX Home Address & Routing Header checksum fix */
1451 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1452 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1453
1454 /* Enable TX Home Address & Routing Header checksum fix */
1455 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1456 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1457 }
1458
1459
1460
cd28ab6a
SH		 1461 return 0;
1462nomem:
1463 sky2_rx_clean(sky2);
1464 return -ENOMEM;
1465}
1466
90bbebb4
MM		 1467static int sky2_alloc_buffers(struct sky2_port *sky2)
1468{
1469 struct sky2_hw *hw = sky2->hw;
1470
1471 /* must be power of 2 */
1472 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1473 sky2->tx_ring_size *
1474 sizeof(struct sky2_tx_le),
1475 &sky2->tx_le_map);
1476 if (!sky2->tx_le)
1477 goto nomem;
1478
1479 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1480 GFP_KERNEL);
1481 if (!sky2->tx_ring)
1482 goto nomem;
1483
1484 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1485 &sky2->rx_le_map);
1486 if (!sky2->rx_le)
1487 goto nomem;
1488 memset(sky2->rx_le, 0, RX_LE_BYTES);
1489
1490 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1491 GFP_KERNEL);
1492 if (!sky2->rx_ring)
1493 goto nomem;
1494
1495 return 0;
1496nomem:
1497 return -ENOMEM;
1498}
1499
1500static void sky2_free_buffers(struct sky2_port *sky2)
1501{
1502 struct sky2_hw *hw = sky2->hw;
1503
1504 if (sky2->rx_le) {
1505 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1506 sky2->rx_le, sky2->rx_le_map);
1507 sky2->rx_le = NULL;
1508 }
1509 if (sky2->tx_le) {
1510 pci_free_consistent(hw->pdev,
1511 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1512 sky2->tx_le, sky2->tx_le_map);
1513 sky2->tx_le = NULL;
1514 }
1515 kfree(sky2->tx_ring);
1516 kfree(sky2->rx_ring);
1517
1518 sky2->tx_ring = NULL;
1519 sky2->rx_ring = NULL;
1520}
1521
cd28ab6a
SH		 1522/* Bring up network interface. */
1523static int sky2_up(struct net_device *dev)
1524{
1525 struct sky2_port *sky2 = netdev_priv(dev);
1526 struct sky2_hw *hw = sky2->hw;
1527 unsigned port = sky2->port;
e0c28116 1528 u32 imask, ramsize;
90bbebb4 1529 int cap, err;
843a46f4 1530 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1531
ee7abb04
SH		 1532 /*
1533 * On dual port PCI-X card, there is an problem where status
1534 * can be received out of order due to split transactions
843a46f4 1535 */
ee7abb04
SH		 1536 if (otherdev && netif_running(otherdev) &&
1537 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1538 u16 cmd;
1539
b32f40c4 1540 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1541 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1542 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1543
ee7abb04 1544 }
843a46f4 1545
55d7b4e6
SH		 1546 netif_carrier_off(dev);
1547
90bbebb4
MM		 1548 err = sky2_alloc_buffers(sky2);
1549 if (err)
cd28ab6a 1550 goto err_out;
88f5f0ca
SH		 1551
1552 tx_init(sky2);
cd28ab6a 1553
cd28ab6a
SH		 1554 sky2_mac_init(hw, port);
1555
e0c28116
SH		 1556 /* Register is number of 4K blocks on internal RAM buffer. */
1557 ramsize = sky2_read8(hw, B2_E_0) * 4;
1558 if (ramsize > 0) {
67712901 1559 u32 rxspace;
cd28ab6a 1560
e0c28116 1561 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1562 if (ramsize < 16)
1563 rxspace = ramsize / 2;
1564 else
1565 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1566
67712901
SH		 1567 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1568 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1569
1570 /* Make sure SyncQ is disabled */
1571 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1572 RB_RST_SET);
1573 }
793b883e 1574
af4ed7e6 1575 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1576
69161611
SH		 1577 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1578 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1579 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1580
977bdf06 1581 /* Set almost empty threshold */
8e95a202
JP		 1582 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1583 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1584 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1585
6b1a3aef 1586 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1587 sky2->tx_ring_size - 1);
cd28ab6a 1588
d494eacd
SH		 1589#ifdef SKY2_VLAN_TAG_USED
1590 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1591#endif
1592
6b1a3aef 1593 err = sky2_rx_start(sky2);
6de16237 1594 if (err)
cd28ab6a
SH		 1595 goto err_out;
1596
cd28ab6a 1597 /* Enable interrupts from phy/mac for port */
e07b1aa8 1598 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1599 imask |= portirq_msk[port];
e07b1aa8 1600 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1601 sky2_read32(hw, B0_IMSK);
e07b1aa8 1602
a11da890
AD		 1603 if (netif_msg_ifup(sky2))
1604 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
af18d8b8 1605
cd28ab6a
SH		 1606 return 0;
1607
1608err_out:
90bbebb4 1609 sky2_free_buffers(sky2);
cd28ab6a
SH		 1610 return err;
1611}
1612
793b883e 1613/* Modular subtraction in ring */
ee5f68fe 1614static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1615{
ee5f68fe 1616 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1617}
cd28ab6a 1618
793b883e
SH		 1619/* Number of list elements available for next tx */
1620static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1621{
ee5f68fe 1622 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1623}
1624
793b883e 1625/* Estimate of number of transmit list elements required */
28bd181a 1626static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1627{
793b883e
SH		 1628 unsigned count;
1629
07e31637
SH		 1630 count = (skb_shinfo(skb)->nr_frags + 1)
1631 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1632
89114afd 1633 if (skb_is_gso(skb))
793b883e 1634 ++count;
07e31637
SH		 1635 else if (sizeof(dma_addr_t) == sizeof(u32))
1636 ++count; /* possible vlan */
793b883e 1637
84fa7933 1638 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1639 ++count;
1640
1641 return count;
cd28ab6a
SH		 1642}
1643
f6815077 1644static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1645{
1646 if (re->flags & TX_MAP_SINGLE)
1647 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1648 pci_unmap_len(re, maplen),
1649 PCI_DMA_TODEVICE);
1650 else if (re->flags & TX_MAP_PAGE)
1651 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1652 pci_unmap_len(re, maplen),
1653 PCI_DMA_TODEVICE);
f6815077 1654 re->flags = 0;
6b84daca
SH		 1655}
1656
793b883e
SH		 1657/*
1658 * Put one packet in ring for transmit.
1659 * A single packet can generate multiple list elements, and
1660 * the number of ring elements will probably be less than the number
1661 * of list elements used.
1662 */
61357325
SH		 1663static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1664 struct net_device *dev)
cd28ab6a
SH		 1665{
1666 struct sky2_port *sky2 = netdev_priv(dev);
1667 struct sky2_hw *hw = sky2->hw;
d1f13708 1668 struct sky2_tx_le *le = NULL;
6cdbbdf3 1669 struct tx_ring_info *re;
9b289c33 1670 unsigned i, len;
cd28ab6a 1671 dma_addr_t mapping;
5dce95e5
SH		 1672 u32 upper;
1673 u16 slot;
cd28ab6a
SH		 1674 u16 mss;
1675 u8 ctrl;
1676
2bb8c262
SH		 1677 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1678 return NETDEV_TX_BUSY;
cd28ab6a 1679
cd28ab6a
SH		 1680 len = skb_headlen(skb);
1681 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1682
454e6cb6
SH		 1683 if (pci_dma_mapping_error(hw->pdev, mapping))
1684 goto mapping_error;
1685
9b289c33 1686 slot = sky2->tx_prod;
454e6cb6
SH		 1687 if (unlikely(netif_msg_tx_queued(sky2)))
1688 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
9b289c33 1689 dev->name, slot, skb->len);
454e6cb6 1690
86c6887e 1691 /* Send high bits if needed */
5dce95e5
SH		 1692 upper = upper_32_bits(mapping);
1693 if (upper != sky2->tx_last_upper) {
9b289c33 1694 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1695 le->addr = cpu_to_le32(upper);
1696 sky2->tx_last_upper = upper;
793b883e 1697 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1698 }
cd28ab6a
SH		 1699
1700 /* Check for TCP Segmentation Offload */
7967168c 1701 mss = skb_shinfo(skb)->gso_size;
793b883e 1702 if (mss != 0) {
ea76e635
SH		 1703
1704 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1705 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1706
1707 if (mss != sky2->tx_last_mss) {
9b289c33 1708 le = get_tx_le(sky2, &slot);
69161611 1709 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1710
1711 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1712 le->opcode = OP_MSS | HW_OWNER;
1713 else
1714 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1715 sky2->tx_last_mss = mss;
1716 }
cd28ab6a
SH		 1717 }
1718
cd28ab6a 1719 ctrl = 0;
d1f13708
SH		 1720#ifdef SKY2_VLAN_TAG_USED
1721 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1722 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1723 if (!le) {
9b289c33 1724 le = get_tx_le(sky2, &slot);
f65b138c 1725 le->addr = 0;
d1f13708 1726 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1727 } else
1728 le->opcode |= OP_VLAN;
1729 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1730 ctrl |= INS_VLAN;
1731 }
1732#endif
1733
1734 /* Handle TCP checksum offload */
84fa7933 1735 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1736 /* On Yukon EX (some versions) encoding change. */
ea76e635 1737 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1738 ctrl |= CALSUM; /* auto checksum */
1739 else {
1740 const unsigned offset = skb_transport_offset(skb);
1741 u32 tcpsum;
1742
1743 tcpsum = offset << 16; /* sum start */
1744 tcpsum |= offset + skb->csum_offset; /* sum write */
1745
1746 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1747 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1748 ctrl |= UDPTCP;
1749
1750 if (tcpsum != sky2->tx_tcpsum) {
1751 sky2->tx_tcpsum = tcpsum;
1752
9b289c33 1753 le = get_tx_le(sky2, &slot);
69161611
SH		 1754 le->addr = cpu_to_le32(tcpsum);
1755 le->length = 0; /* initial checksum value */
1756 le->ctrl = 1; /* one packet */
1757 le->opcode = OP_TCPLISW | HW_OWNER;
1758 }
1d179332 1759 }
cd28ab6a
SH		 1760 }
1761
6b84daca
SH		 1762 re = sky2->tx_ring + slot;
1763 re->flags = TX_MAP_SINGLE;
1764 pci_unmap_addr_set(re, mapaddr, mapping);
1765 pci_unmap_len_set(re, maplen, len);
1766
9b289c33 1767 le = get_tx_le(sky2, &slot);
d6e74b6b 1768 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1769 le->length = cpu_to_le16(len);
1770 le->ctrl = ctrl;
793b883e 1771 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1772
cd28ab6a
SH		 1773
1774 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1775 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1776
1777 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1778 frag->size, PCI_DMA_TODEVICE);
86c6887e 1779
454e6cb6
SH		 1780 if (pci_dma_mapping_error(hw->pdev, mapping))
1781 goto mapping_unwind;
1782
5dce95e5
SH		 1783 upper = upper_32_bits(mapping);
1784 if (upper != sky2->tx_last_upper) {
9b289c33 1785 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1786 le->addr = cpu_to_le32(upper);
1787 sky2->tx_last_upper = upper;
793b883e 1788 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1789 }
1790
6b84daca
SH		 1791 re = sky2->tx_ring + slot;
1792 re->flags = TX_MAP_PAGE;
1793 pci_unmap_addr_set(re, mapaddr, mapping);
1794 pci_unmap_len_set(re, maplen, frag->size);
1795
9b289c33 1796 le = get_tx_le(sky2, &slot);
d6e74b6b 1797 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1798 le->length = cpu_to_le16(frag->size);
1799 le->ctrl = ctrl;
793b883e 1800 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1801 }
6cdbbdf3 1802
6b84daca 1803 re->skb = skb;
cd28ab6a
SH		 1804 le->ctrl |= EOP;
1805
9b289c33
MM		 1806 sky2->tx_prod = slot;
1807
97bda706
SH		 1808 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1809 netif_stop_queue(dev);
b19666d9 1810
290d4de5 1811 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1812
cd28ab6a 1813 return NETDEV_TX_OK;
454e6cb6
SH		 1814
1815mapping_unwind:
ee5f68fe 1816 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1817 re = sky2->tx_ring + i;
1818
6b84daca 1819 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1820 }
1821
454e6cb6
SH		 1822mapping_error:
1823 if (net_ratelimit())
1824 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1825 dev_kfree_skb(skb);
1826 return NETDEV_TX_OK;
cd28ab6a
SH		 1827}
1828
cd28ab6a 1829/*
793b883e
SH		 1830 * Free ring elements from starting at tx_cons until "done"
1831 *
481cea4a
SH		 1832 * NB:
1833 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1834 * buffers so make sure not to free skb to early.
481cea4a
SH		 1835 * 2. This may run in parallel start_xmit because the it only
1836 * looks at the tail of the queue of FIFO (tx_cons), not
1837 * the head (tx_prod)
cd28ab6a 1838 */
d11c13e7 1839static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1840{
d11c13e7 1841 struct net_device *dev = sky2->netdev;
291ea614 1842 unsigned idx;
cd28ab6a 1843
ee5f68fe 1844 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1845
291ea614 1846 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1847 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1848 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1849 struct sk_buff *skb = re->skb;
291ea614 1850
6b84daca 1851 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1852
6b84daca 1853 if (skb) {
291ea614
SH		 1854 if (unlikely(netif_msg_tx_done(sky2)))
1855 printk(KERN_DEBUG "%s: tx done %u\n",
1856 dev->name, idx);
3cf26753 1857
7138a0f5 1858 dev->stats.tx_packets++;
bd1c6869
SH		 1859 dev->stats.tx_bytes += skb->len;
1860
f6815077 1861 re->skb = NULL;
724b6942 1862 dev_kfree_skb_any(skb);
2bf56fe2 1863
ee5f68fe 1864 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1865 }
793b883e 1866 }
793b883e 1867
291ea614 1868 sky2->tx_cons = idx;
50432cb5
SH		 1869 smp_mb();
1870
9db2f1be
JP		 1871 /* Wake unless it's detached, and called e.g. from sky2_down() */
1872 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4 && netif_device_present(dev))
cd28ab6a 1873 netif_wake_queue(dev);
cd28ab6a
SH		 1874}
1875
264bb4fa 1876static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1877{
a510996b
MM		 1878 /* Disable Force Sync bit and Enable Alloc bit */
1879 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1880 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1881
1882 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1883 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1884 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1885
1886 /* Reset the PCI FIFO of the async Tx queue */
1887 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1888 BMU_RST_SET | BMU_FIFO_RST);
1889
1890 /* Reset the Tx prefetch units */
1891 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1892 PREF_UNIT_RST_SET);
1893
1894 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1895 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1896}
1897
cd28ab6a
SH		 1898/* Network shutdown */
1899static int sky2_down(struct net_device *dev)
1900{
1901 struct sky2_port *sky2 = netdev_priv(dev);
1902 struct sky2_hw *hw = sky2->hw;
1903 unsigned port = sky2->port;
1904 u16 ctrl;
e07b1aa8 1905 u32 imask;
cd28ab6a 1906
1b537565
SH		 1907 /* Never really got started! */
1908 if (!sky2->tx_le)
1909 return 0;
1910
cd28ab6a
SH		 1911 if (netif_msg_ifdown(sky2))
1912 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1913
d104acaf
SH		 1914 /* Force flow control off */
1915 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1916
cd28ab6a
SH		 1917 /* Stop transmitter */
1918 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1919 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1920
1921 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1922 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1923
1924 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1925 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1926 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1927
1928 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1929
1930 /* Workaround shared GMAC reset */
8e95a202
JP		 1931 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1932 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1933 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1934
cd28ab6a 1935 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1936
6c83504f
SH		 1937 /* Force any delayed status interrrupt and NAPI */
1938 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1939 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1940 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1941 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1942
a947a39d
MM		 1943 sky2_rx_stop(sky2);
1944
1945 /* Disable port IRQ */
1946 imask = sky2_read32(hw, B0_IMSK);
1947 imask &= ~portirq_msk[port];
1948 sky2_write32(hw, B0_IMSK, imask);
1949 sky2_read32(hw, B0_IMSK);
1950
6c83504f
SH		 1951 synchronize_irq(hw->pdev->irq);
1952 napi_synchronize(&hw->napi);
1953
0da6d7b3 1954 spin_lock_bh(&sky2->phy_lock);
b96936da 1955 sky2_phy_power_down(hw, port);
0da6d7b3 1956 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1957
264bb4fa
MM		 1958 sky2_tx_reset(hw, port);
1959
481cea4a
SH		 1960 /* Free any pending frames stuck in HW queue */
1961 sky2_tx_complete(sky2, sky2->tx_prod);
1962
cd28ab6a
SH		 1963 sky2_rx_clean(sky2);
1964
90bbebb4 1965 sky2_free_buffers(sky2);
1b537565 1966
cd28ab6a
SH		 1967 return 0;
1968}
1969
1970static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1971{
ea76e635 1972 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1973 return SPEED_1000;
1974
05745c4a
SH		 1975 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1976 if (aux & PHY_M_PS_SPEED_100)
1977 return SPEED_100;
1978 else
1979 return SPEED_10;
1980 }
cd28ab6a
SH		 1981
1982 switch (aux & PHY_M_PS_SPEED_MSK) {
1983 case PHY_M_PS_SPEED_1000:
1984 return SPEED_1000;
1985 case PHY_M_PS_SPEED_100:
1986 return SPEED_100;
1987 default:
1988 return SPEED_10;
1989 }
1990}
1991
1992static void sky2_link_up(struct sky2_port *sky2)
1993{
1994 struct sky2_hw *hw = sky2->hw;
1995 unsigned port = sky2->port;
1996 u16 reg;
16ad91e1
SH		 1997 static const char *fc_name[] = {
1998 [FC_NONE] = "none",
1999 [FC_TX] = "tx",
2000 [FC_RX] = "rx",
2001 [FC_BOTH] = "both",
2002 };
cd28ab6a 2003
cd28ab6a 2004 /* enable Rx/Tx */
2eaba1a2 2005 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 2006 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2007 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 2008
2009 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2010
2011 netif_carrier_on(sky2->netdev);
cd28ab6a 2012
75e80683 2013 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 2014
cd28ab6a 2015 /* Turn on link LED */
793b883e 2016 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2017 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2018
2019 if (netif_msg_link(sky2))
2020 printk(KERN_INFO PFX
d571b694 2021 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 2022 sky2->netdev->name, sky2->speed,
2023 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 2024 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2025}
2026
2027static void sky2_link_down(struct sky2_port *sky2)
2028{
2029 struct sky2_hw *hw = sky2->hw;
2030 unsigned port = sky2->port;
2031 u16 reg;
2032
2033 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2034
2035 reg = gma_read16(hw, port, GM_GP_CTRL);
2036 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2037 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2038
cd28ab6a 2039 netif_carrier_off(sky2->netdev);
cd28ab6a 2040
809aaaae 2041 /* Turn off link LED */
cd28ab6a
SH		 2042 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2043
2044 if (netif_msg_link(sky2))
2045 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 2046
cd28ab6a
SH		 2047 sky2_phy_init(hw, port);
2048}
2049
16ad91e1
SH		 2050static enum flow_control sky2_flow(int rx, int tx)
2051{
2052 if (rx)
2053 return tx ? FC_BOTH : FC_RX;
2054 else
2055 return tx ? FC_TX : FC_NONE;
2056}
2057
793b883e
SH		 2058static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2059{
2060 struct sky2_hw *hw = sky2->hw;
2061 unsigned port = sky2->port;
da4c1ff4 2062 u16 advert, lpa;
793b883e 2063
da4c1ff4 2064 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2065 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 2066 if (lpa & PHY_M_AN_RF) {
2067 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2068 return -1;
2069 }
2070
793b883e
SH		 2071 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2072 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2073 sky2->netdev->name);
2074 return -1;
2075 }
2076
793b883e 2077 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2078 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2079
da4c1ff4
SH		 2080 /* Since the pause result bits seem to in different positions on
2081 * different chips. look at registers.
2082 */
ea76e635 2083 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2084 /* Shift for bits in fiber PHY */
2085 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2086 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2087
2088 if (advert & ADVERTISE_1000XPAUSE)
2089 advert |= ADVERTISE_PAUSE_CAP;
2090 if (advert & ADVERTISE_1000XPSE_ASYM)
2091 advert |= ADVERTISE_PAUSE_ASYM;
2092 if (lpa & LPA_1000XPAUSE)
2093 lpa |= LPA_PAUSE_CAP;
2094 if (lpa & LPA_1000XPAUSE_ASYM)
2095 lpa |= LPA_PAUSE_ASYM;
2096 }
793b883e 2097
da4c1ff4
SH		 2098 sky2->flow_status = FC_NONE;
2099 if (advert & ADVERTISE_PAUSE_CAP) {
2100 if (lpa & LPA_PAUSE_CAP)
2101 sky2->flow_status = FC_BOTH;
2102 else if (advert & ADVERTISE_PAUSE_ASYM)
2103 sky2->flow_status = FC_RX;
2104 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2105 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2106 sky2->flow_status = FC_TX;
2107 }
793b883e 2108
8e95a202
JP		 2109 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2110 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2111 sky2->flow_status = FC_NONE;
2eaba1a2 2112
da4c1ff4 2113 if (sky2->flow_status & FC_TX)
793b883e
SH		 2114 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2115 else
2116 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2117
2118 return 0;
2119}
cd28ab6a 2120
e07b1aa8
SH		 2121/* Interrupt from PHY */
2122static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2123{
e07b1aa8
SH		 2124 struct net_device *dev = hw->dev[port];
2125 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2126 u16 istatus, phystat;
2127
ebc646f6
SH		 2128 if (!netif_running(dev))
2129 return;
2130
e07b1aa8
SH		 2131 spin_lock(&sky2->phy_lock);
2132 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2133 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2134
cd28ab6a
SH		 2135 if (netif_msg_intr(sky2))
2136 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2137 sky2->netdev->name, istatus, phystat);
2138
0ea065e5 2139 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2140 if (sky2_autoneg_done(sky2, phystat) == 0)
2141 sky2_link_up(sky2);
2142 goto out;
2143 }
cd28ab6a 2144
793b883e
SH		 2145 if (istatus & PHY_M_IS_LSP_CHANGE)
2146 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2147
793b883e
SH		 2148 if (istatus & PHY_M_IS_DUP_CHANGE)
2149 sky2->duplex =
2150 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2151
793b883e
SH		 2152 if (istatus & PHY_M_IS_LST_CHANGE) {
2153 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2154 sky2_link_up(sky2);
793b883e
SH		 2155 else
2156 sky2_link_down(sky2);
cd28ab6a 2157 }
793b883e 2158out:
e07b1aa8 2159 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2160}
2161
0f5aac70
SH		 2162/* Special quick link interrupt (Yukon-2 Optima only) */
2163static void sky2_qlink_intr(struct sky2_hw *hw)
2164{
2165 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2166 u32 imask;
2167 u16 phy;
2168
2169 /* disable irq */
2170 imask = sky2_read32(hw, B0_IMSK);
2171 imask &= ~Y2_IS_PHY_QLNK;
2172 sky2_write32(hw, B0_IMSK, imask);
2173
2174 /* reset PHY Link Detect */
2175 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2176 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2177 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2178 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2179
2180 sky2_link_up(sky2);
2181}
2182
62335ab0 2183/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2184 * and tx queue is full (stopped).
2185 */
cd28ab6a
SH		 2186static void sky2_tx_timeout(struct net_device *dev)
2187{
2188 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2189 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2190
2191 if (netif_msg_timer(sky2))
2192 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2193
8f24664d 2194 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2195 dev->name, sky2->tx_cons, sky2->tx_prod,
2196 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2197 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2198
81906791
SH		 2199 /* can't restart safely under softirq */
2200 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2201}
2202
2203static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2204{
6b1a3aef
SH		 2205 struct sky2_port *sky2 = netdev_priv(dev);
2206 struct sky2_hw *hw = sky2->hw;
b628ed98 2207 unsigned port = sky2->port;
6b1a3aef
SH		 2208 int err;
2209 u16 ctl, mode;
e07b1aa8 2210 u32 imask;
cd28ab6a 2211
44dde56d 2212 /* MTU size outside the spec */
cd28ab6a
SH		 2213 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2214 return -EINVAL;
2215
44dde56d 2216 /* MTU > 1500 on yukon FE and FE+ not allowed */
05745c4a
SH		 2217 if (new_mtu > ETH_DATA_LEN &&
2218 (hw->chip_id == CHIP_ID_YUKON_FE ||
2219 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2220 return -EINVAL;
2221
44dde56d 2222 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2223 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
2224 dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
2225
6b1a3aef
SH		 2226 if (!netif_running(dev)) {
2227 dev->mtu = new_mtu;
2228 return 0;
2229 }
2230
e07b1aa8 2231 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2232 sky2_write32(hw, B0_IMSK, 0);
2233
018d1c66
SH		 2234 dev->trans_start = jiffies; /* prevent tx timeout */
2235 netif_stop_queue(dev);
bea3348e 2236 napi_disable(&hw->napi);
018d1c66 2237
e07b1aa8
SH		 2238 synchronize_irq(hw->pdev->irq);
2239
39dbd958 2240 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2241 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2242
2243 ctl = gma_read16(hw, port, GM_GP_CTRL);
2244 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2245 sky2_rx_stop(sky2);
2246 sky2_rx_clean(sky2);
cd28ab6a
SH		 2247
2248 dev->mtu = new_mtu;
14d0263f 2249
6b1a3aef
SH		 2250 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2251 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2252
2253 if (dev->mtu > ETH_DATA_LEN)
2254 mode |= GM_SMOD_JUMBO_ENA;
2255
b628ed98 2256 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2257
b628ed98 2258 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2259
6b1a3aef 2260 err = sky2_rx_start(sky2);
e07b1aa8 2261 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2262
d1d08d12 2263 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2264 napi_enable(&hw->napi);
2265
1b537565
SH		 2266 if (err)
2267 dev_close(dev);
2268 else {
b628ed98 2269 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2270
1b537565
SH		 2271 netif_wake_queue(dev);
2272 }
2273
cd28ab6a
SH		 2274 return err;
2275}
2276
14d0263f
SH		 2277/* For small just reuse existing skb for next receive */
2278static struct sk_buff *receive_copy(struct sky2_port *sky2,
2279 const struct rx_ring_info *re,
2280 unsigned length)
2281{
2282 struct sk_buff *skb;
2283
89d71a66 2284 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2285 if (likely(skb)) {
14d0263f
SH		 2286 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2287 length, PCI_DMA_FROMDEVICE);
d626f62b 2288 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2289 skb->ip_summed = re->skb->ip_summed;
2290 skb->csum = re->skb->csum;
2291 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2292 length, PCI_DMA_FROMDEVICE);
2293 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2294 skb_put(skb, length);
14d0263f
SH		 2295 }
2296 return skb;
2297}
2298
2299/* Adjust length of skb with fragments to match received data */
2300static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2301 unsigned int length)
2302{
2303 int i, num_frags;
2304 unsigned int size;
2305
2306 /* put header into skb */
2307 size = min(length, hdr_space);
2308 skb->tail += size;
2309 skb->len += size;
2310 length -= size;
2311
2312 num_frags = skb_shinfo(skb)->nr_frags;
2313 for (i = 0; i < num_frags; i++) {
2314 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2315
2316 if (length == 0) {
2317 /* don't need this page */
2318 __free_page(frag->page);
2319 --skb_shinfo(skb)->nr_frags;
2320 } else {
2321 size = min(length, (unsigned) PAGE_SIZE);
2322
2323 frag->size = size;
2324 skb->data_len += size;
2325 skb->truesize += size;
2326 skb->len += size;
2327 length -= size;
2328 }
2329 }
2330}
2331
2332/* Normal packet - take skb from ring element and put in a new one */
2333static struct sk_buff *receive_new(struct sky2_port *sky2,
2334 struct rx_ring_info *re,
2335 unsigned int length)
2336{
3fbd9187 2337 struct sk_buff *skb;
2338 struct rx_ring_info nre;
14d0263f
SH		 2339 unsigned hdr_space = sky2->rx_data_size;
2340
3fbd9187 2341 nre.skb = sky2_rx_alloc(sky2);
2342 if (unlikely(!nre.skb))
2343 goto nobuf;
2344
2345 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2346 goto nomap;
14d0263f
SH		 2347
2348 skb = re->skb;
2349 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2350 prefetch(skb->data);
3fbd9187 2351 *re = nre;
14d0263f
SH		 2352
2353 if (skb_shinfo(skb)->nr_frags)
2354 skb_put_frags(skb, hdr_space, length);
2355 else
489b10c1 2356 skb_put(skb, length);
14d0263f 2357 return skb;
3fbd9187 2358
2359nomap:
2360 dev_kfree_skb(nre.skb);
2361nobuf:
2362 return NULL;
14d0263f
SH		 2363}
2364
cd28ab6a
SH		 2365/*
2366 * Receive one packet.
d571b694 2367 * For larger packets, get new buffer.
cd28ab6a 2368 */
497d7c86 2369static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2370 u16 length, u32 status)
2371{
497d7c86 2372 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2373 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2374 struct sk_buff *skb = NULL;
d6532232
SH		 2375 u16 count = (status & GMR_FS_LEN) >> 16;
2376
2377#ifdef SKY2_VLAN_TAG_USED
2378 /* Account for vlan tag */
2379 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2380 count -= VLAN_HLEN;
2381#endif
cd28ab6a
SH		 2382
2383 if (unlikely(netif_msg_rx_status(sky2)))
2384 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2385 dev->name, sky2->rx_next, status, length);
cd28ab6a 2386
793b883e 2387 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2388 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2389
3b12e014
SH		 2390 /* This chip has hardware problems that generates bogus status.
2391 * So do only marginal checking and expect higher level protocols
2392 * to handle crap frames.
2393 */
2394 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2395 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2396 length != count)
2397 goto okay;
2398
42eeea01 2399 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2400 goto error;
2401
42eeea01
SH		 2402 if (!(status & GMR_FS_RX_OK))
2403 goto resubmit;
2404
d6532232
SH		 2405 /* if length reported by DMA does not match PHY, packet was truncated */
2406 if (length != count)
3b12e014 2407 goto len_error;
71749531 2408
3b12e014 2409okay:
14d0263f
SH		 2410 if (length < copybreak)
2411 skb = receive_copy(sky2, re, length);
2412 else
2413 skb = receive_new(sky2, re, length);
90c30335
SH		 2414
2415 dev->stats.rx_dropped += (skb == NULL);
2416
793b883e 2417resubmit:
14d0263f 2418 sky2_rx_submit(sky2, re);
79e57d32 2419
cd28ab6a
SH		 2420 return skb;
2421
3b12e014 2422len_error:
71749531
SH		 2423 /* Truncation of overlength packets
2424 causes PHY length to not match MAC length */
7138a0f5 2425 ++dev->stats.rx_length_errors;
d6532232 2426 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2427 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2428 dev->name, status, length);
d6532232 2429 goto resubmit;
71749531 2430
cd28ab6a 2431error:
7138a0f5 2432 ++dev->stats.rx_errors;
b6d77734 2433 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2434 dev->stats.rx_over_errors++;
b6d77734
SH		 2435 goto resubmit;
2436 }
6e15b712 2437
3be92a70 2438 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2439 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2440 dev->name, status, length);
793b883e
SH		 2441
2442 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2443 dev->stats.rx_length_errors++;
cd28ab6a 2444 if (status & GMR_FS_FRAGMENT)
7138a0f5 2445 dev->stats.rx_frame_errors++;
cd28ab6a 2446 if (status & GMR_FS_CRC_ERR)
7138a0f5 2447 dev->stats.rx_crc_errors++;
79e57d32 2448
793b883e 2449 goto resubmit;
cd28ab6a
SH		 2450}
2451
e07b1aa8
SH		 2452/* Transmit complete */
2453static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2454{
e07b1aa8 2455 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2456
49d4b8ba 2457 if (netif_running(dev))
e07b1aa8 2458 sky2_tx_complete(sky2, last);
cd28ab6a
SH		 2459}
2460
37e5a243
SH		 2461static inline void sky2_skb_rx(const struct sky2_port *sky2,
2462 u32 status, struct sk_buff *skb)
2463{
2464#ifdef SKY2_VLAN_TAG_USED
2465 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2466 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2467 if (skb->ip_summed == CHECKSUM_NONE)
2468 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2469 else
2470 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2471 vlan_tag, skb);
2472 return;
2473 }
2474#endif
2475 if (skb->ip_summed == CHECKSUM_NONE)
2476 netif_receive_skb(skb);
2477 else
2478 napi_gro_receive(&sky2->hw->napi, skb);
2479}
2480
bf15fe99
SH		 2481static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2482 unsigned packets, unsigned bytes)
2483{
2484 if (packets) {
2485 struct net_device *dev = hw->dev[port];
2486
2487 dev->stats.rx_packets += packets;
2488 dev->stats.rx_bytes += bytes;
2489 dev->last_rx = jiffies;
2490 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2491 }
2492}
2493
375c5688 2494static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2495{
2496 /* If this happens then driver assuming wrong format for chip type */
2497 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2498
2499 /* Both checksum counters are programmed to start at
2500 * the same offset, so unless there is a problem they
2501 * should match. This failure is an early indication that
2502 * hardware receive checksumming won't work.
2503 */
2504 if (likely((u16)(status >> 16) == (u16)status)) {
2505 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2506 skb->ip_summed = CHECKSUM_COMPLETE;
2507 skb->csum = le16_to_cpu(status);
2508 } else {
2509 dev_notice(&sky2->hw->pdev->dev,
2510 "%s: receive checksum problem (status = %#x)\n",
2511 sky2->netdev->name, status);
2512
2513 /* Disable checksum offload */
2514 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2515 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2516 BMU_DIS_RX_CHKSUM);
2517 }
2518}
2519
e07b1aa8 2520/* Process status response ring */
26691830 2521static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2522{
e07b1aa8 2523 int work_done = 0;
bf15fe99
SH		 2524 unsigned int total_bytes[2] = { 0 };
2525 unsigned int total_packets[2] = { 0 };
a8fd6266 2526
af2a58ac 2527 rmb();
26691830 2528 do {
55c9dd35 2529 struct sky2_port *sky2;
13210ce5 2530 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2531 unsigned port;
13210ce5 2532 struct net_device *dev;
cd28ab6a 2533 struct sk_buff *skb;
cd28ab6a
SH		 2534 u32 status;
2535 u16 length;
ab5adecb
SH		 2536 u8 opcode = le->opcode;
2537
2538 if (!(opcode & HW_OWNER))
2539 break;
cd28ab6a 2540
cb5d9547 2541 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2542
ab5adecb 2543 port = le->css & CSS_LINK_BIT;
69161611 2544 dev = hw->dev[port];
13210ce5 2545 sky2 = netdev_priv(dev);
f65b138c
SH		 2546 length = le16_to_cpu(le->length);
2547 status = le32_to_cpu(le->status);
cd28ab6a 2548
ab5adecb
SH		 2549 le->opcode = 0;
2550 switch (opcode & ~HW_OWNER) {
cd28ab6a 2551 case OP_RXSTAT:
bf15fe99
SH		 2552 total_packets[port]++;
2553 total_bytes[port] += length;
90c30335 2554
497d7c86 2555 skb = sky2_receive(dev, length, status);
90c30335 2556 if (!skb)
55c9dd35 2557 break;
13210ce5 2558
69161611 2559 /* This chip reports checksum status differently */
05745c4a 2560 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2561 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2562 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2563 (le->css & CSS_TCPUDPCSOK))
2564 skb->ip_summed = CHECKSUM_UNNECESSARY;
2565 else
2566 skb->ip_summed = CHECKSUM_NONE;
2567 }
2568
13210ce5 2569 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2570
37e5a243 2571 sky2_skb_rx(sky2, status, skb);
13210ce5 2572
22e11703 2573 /* Stop after net poll weight */
13210ce5
SH		 2574 if (++work_done >= to_do)
2575 goto exit_loop;
cd28ab6a
SH		 2576 break;
2577
d1f13708
SH		 2578#ifdef SKY2_VLAN_TAG_USED
2579 case OP_RXVLAN:
2580 sky2->rx_tag = length;
2581 break;
2582
2583 case OP_RXCHKSVLAN:
2584 sky2->rx_tag = length;
2585 /* fall through */
2586#endif
cd28ab6a 2587 case OP_RXCHKS:
375c5688 2588 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2589 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2590 break;
2591
2592 case OP_TXINDEXLE:
13b97b74 2593 /* TX index reports status for both ports */
f55925d7 2594 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2595 if (hw->dev[1])
2596 sky2_tx_done(hw->dev[1],
2597 ((status >> 24) & 0xff)
2598 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2599 break;
2600
cd28ab6a
SH		 2601 default:
2602 if (net_ratelimit())
793b883e 2603 printk(KERN_WARNING PFX
ab5adecb 2604 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2605 }
26691830 2606 } while (hw->st_idx != idx);
cd28ab6a 2607
fe2a24df
SH		 2608 /* Fully processed status ring so clear irq */
2609 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2610
13210ce5 2611exit_loop:
bf15fe99
SH		 2612 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2613 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2614
e07b1aa8 2615 return work_done;
cd28ab6a
SH		 2616}
2617
2618static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2619{
2620 struct net_device *dev = hw->dev[port];
2621
3be92a70
SH		 2622 if (net_ratelimit())
2623 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2624 dev->name, status);
cd28ab6a
SH		 2625
2626 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2627 if (net_ratelimit())
2628 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2629 dev->name);
cd28ab6a
SH		 2630 /* Clear IRQ */
2631 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2632 }
2633
2634 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2635 if (net_ratelimit())
2636 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2637 dev->name);
cd28ab6a
SH		 2638
2639 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2640 }
2641
2642 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2643 if (net_ratelimit())
2644 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2645 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2646 }
2647
2648 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2649 if (net_ratelimit())
2650 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2651 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2652 }
2653
2654 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2655 if (net_ratelimit())
2656 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2657 dev->name);
cd28ab6a
SH		 2658 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2659 }
2660}
2661
2662static void sky2_hw_intr(struct sky2_hw *hw)
2663{
555382cb 2664 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2665 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2666 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2667
2668 status &= hwmsk;
cd28ab6a 2669
793b883e 2670 if (status & Y2_IS_TIST_OV)
cd28ab6a 2671 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2672
2673 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2674 u16 pci_err;
2675
a40ccc68 2676 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2677 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2678 if (net_ratelimit())
555382cb 2679 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2680 pci_err);
cd28ab6a 2681
b32f40c4 2682 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2683 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2685 }
2686
2687 if (status & Y2_IS_PCI_EXP) {
d571b694 2688 /* PCI-Express uncorrectable Error occurred */
555382cb 2689 u32 err;
cd28ab6a 2690
a40ccc68 2691 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2692 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2693 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2694 0xfffffffful);
3be92a70 2695 if (net_ratelimit())
555382cb 2696 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2697
7782c8c4 2698 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2699 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2700 }
2701
2702 if (status & Y2_HWE_L1_MASK)
2703 sky2_hw_error(hw, 0, status);
2704 status >>= 8;
2705 if (status & Y2_HWE_L1_MASK)
2706 sky2_hw_error(hw, 1, status);
2707}
2708
2709static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2710{
2711 struct net_device *dev = hw->dev[port];
2712 struct sky2_port *sky2 = netdev_priv(dev);
2713 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2714
2715 if (netif_msg_intr(sky2))
2716 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2717 dev->name, status);
2718
a3caeada
SH		 2719 if (status & GM_IS_RX_CO_OV)
2720 gma_read16(hw, port, GM_RX_IRQ_SRC);
2721
2722 if (status & GM_IS_TX_CO_OV)
2723 gma_read16(hw, port, GM_TX_IRQ_SRC);
2724
cd28ab6a 2725 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2726 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2727 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2728 }
2729
2730 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2731 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2732 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2733 }
cd28ab6a
SH		 2734}
2735
40b01727 2736/* This should never happen it is a bug. */
c119731d 2737static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2738{
2739 struct net_device *dev = hw->dev[port];
c119731d 2740 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2741
c119731d
SH		 2742 dev_err(&hw->pdev->dev, PFX
2743 "%s: descriptor error q=%#x get=%u put=%u\n",
2744 dev->name, (unsigned) q, (unsigned) idx,
2745 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2746
40b01727 2747 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2748}
cd28ab6a 2749
75e80683
SH		 2750static int sky2_rx_hung(struct net_device *dev)
2751{
2752 struct sky2_port *sky2 = netdev_priv(dev);
2753 struct sky2_hw *hw = sky2->hw;
2754 unsigned port = sky2->port;
2755 unsigned rxq = rxqaddr[port];
2756 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2757 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2758 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2759 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2760
2761 /* If idle and MAC or PCI is stuck */
2762 if (sky2->check.last == dev->last_rx &&
2763 ((mac_rp == sky2->check.mac_rp &&
2764 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2765 /* Check if the PCI RX hang */
2766 (fifo_rp == sky2->check.fifo_rp &&
2767 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2768 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2769 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2770 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2771 return 1;
2772 } else {
2773 sky2->check.last = dev->last_rx;
2774 sky2->check.mac_rp = mac_rp;
2775 sky2->check.mac_lev = mac_lev;
2776 sky2->check.fifo_rp = fifo_rp;
2777 sky2->check.fifo_lev = fifo_lev;
2778 return 0;
2779 }
2780}
2781
32c2c300 2782static void sky2_watchdog(unsigned long arg)
d27ed387 2783{
01bd7564 2784 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2785
75e80683 2786 /* Check for lost IRQ once a second */
32c2c300 2787 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2788 napi_schedule(&hw->napi);
75e80683
SH		 2789 } else {
2790 int i, active = 0;
2791
2792 for (i = 0; i < hw->ports; i++) {
bea3348e 2793 struct net_device *dev = hw->dev[i];
75e80683
SH		 2794 if (!netif_running(dev))
2795 continue;
2796 ++active;
2797
2798 /* For chips with Rx FIFO, check if stuck */
39dbd958 2799 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2800 sky2_rx_hung(dev)) {
2801 pr_info(PFX "%s: receiver hang detected\n",
2802 dev->name);
2803 schedule_work(&hw->restart_work);
2804 return;
2805 }
2806 }
2807
2808 if (active == 0)
2809 return;
32c2c300 2810 }
01bd7564 2811
75e80683 2812 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2813}
2814
40b01727
SH		 2815/* Hardware/software error handling */
2816static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2817{
40b01727
SH		 2818 if (net_ratelimit())
2819 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2820
1e5f1283
SH		 2821 if (status & Y2_IS_HW_ERR)
2822 sky2_hw_intr(hw);
d257924e 2823
1e5f1283
SH		 2824 if (status & Y2_IS_IRQ_MAC1)
2825 sky2_mac_intr(hw, 0);
cd28ab6a 2826
1e5f1283
SH		 2827 if (status & Y2_IS_IRQ_MAC2)
2828 sky2_mac_intr(hw, 1);
cd28ab6a 2829
1e5f1283 2830 if (status & Y2_IS_CHK_RX1)
c119731d 2831 sky2_le_error(hw, 0, Q_R1);
d257924e 2832
1e5f1283 2833 if (status & Y2_IS_CHK_RX2)
c119731d 2834 sky2_le_error(hw, 1, Q_R2);
d257924e 2835
1e5f1283 2836 if (status & Y2_IS_CHK_TXA1)
c119731d 2837 sky2_le_error(hw, 0, Q_XA1);
d257924e 2838
1e5f1283 2839 if (status & Y2_IS_CHK_TXA2)
c119731d 2840 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2841}
2842
bea3348e 2843static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2844{
bea3348e 2845 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2846 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2847 int work_done = 0;
26691830 2848 u16 idx;
40b01727
SH		 2849
2850 if (unlikely(status & Y2_IS_ERROR))
2851 sky2_err_intr(hw, status);
2852
2853 if (status & Y2_IS_IRQ_PHY1)
2854 sky2_phy_intr(hw, 0);
2855
2856 if (status & Y2_IS_IRQ_PHY2)
2857 sky2_phy_intr(hw, 1);
cd28ab6a 2858
0f5aac70
SH		 2859 if (status & Y2_IS_PHY_QLNK)
2860 sky2_qlink_intr(hw);
2861
26691830
SH		 2862 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2863 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2864
2865 if (work_done >= work_limit)
26691830
SH		 2866 goto done;
2867 }
6f535763 2868
26691830
SH		 2869 napi_complete(napi);
2870 sky2_read32(hw, B0_Y2_SP_LISR);
2871done:
6f535763 2872
bea3348e 2873 return work_done;
e07b1aa8
SH		 2874}
2875
7d12e780 2876static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2877{
2878 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2879 u32 status;
2880
2881 /* Reading this mask interrupts as side effect */
2882 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2883 if (status == 0 || status == ~0)
2884 return IRQ_NONE;
793b883e 2885
e07b1aa8 2886 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2887
2888 napi_schedule(&hw->napi);
793b883e 2889
cd28ab6a
SH		 2890 return IRQ_HANDLED;
2891}
2892
2893#ifdef CONFIG_NET_POLL_CONTROLLER
2894static void sky2_netpoll(struct net_device *dev)
2895{
2896 struct sky2_port *sky2 = netdev_priv(dev);
2897
bea3348e 2898 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2899}
2900#endif
2901
2902/* Chip internal frequency for clock calculations */
05745c4a 2903static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2904{
793b883e 2905 switch (hw->chip_id) {
cd28ab6a 2906 case CHIP_ID_YUKON_EC:
5a5b1ea0 2907 case CHIP_ID_YUKON_EC_U:
93745494 2908 case CHIP_ID_YUKON_EX:
ed4d4161 2909 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2910 case CHIP_ID_YUKON_UL_2:
0f5aac70 2911 case CHIP_ID_YUKON_OPT:
05745c4a
SH		 2912 return 125;
2913
cd28ab6a 2914 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2915 return 100;
2916
2917 case CHIP_ID_YUKON_FE_P:
2918 return 50;
2919
2920 case CHIP_ID_YUKON_XL:
2921 return 156;
2922
2923 default:
2924 BUG();
cd28ab6a
SH		 2925 }
2926}
2927
fb17358f 2928static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2929{
fb17358f 2930 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2931}
2932
fb17358f 2933static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2934{
fb17358f 2935 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2936}
2937
fb17358f 2938
e3173832 2939static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2940{
b89165f2 2941 u8 t8;
cd28ab6a 2942
167f53d0 2943 /* Enable all clocks and check for bad PCI access */
b32f40c4 2944 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2945
cd28ab6a 2946 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2947
cd28ab6a 2948 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2949 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2950
2951 switch(hw->chip_id) {
2952 case CHIP_ID_YUKON_XL:
39dbd958 2953 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2954 break;
2955
2956 case CHIP_ID_YUKON_EC_U:
2957 hw->flags = SKY2_HW_GIGABIT
2958 | SKY2_HW_NEWER_PHY
2959 | SKY2_HW_ADV_POWER_CTL;
2960 break;
2961
2962 case CHIP_ID_YUKON_EX:
2963 hw->flags = SKY2_HW_GIGABIT
2964 | SKY2_HW_NEWER_PHY
2965 | SKY2_HW_NEW_LE
2966 | SKY2_HW_ADV_POWER_CTL;
2967
2968 /* New transmit checksum */
2969 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2970 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2971 break;
2972
2973 case CHIP_ID_YUKON_EC:
2974 /* This rev is really old, and requires untested workarounds */
2975 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2976 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2977 return -EOPNOTSUPP;
2978 }
39dbd958 2979 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2980 break;
2981
2982 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2983 break;
2984
05745c4a
SH		 2985 case CHIP_ID_YUKON_FE_P:
2986 hw->flags = SKY2_HW_NEWER_PHY
2987 | SKY2_HW_NEW_LE
2988 | SKY2_HW_AUTO_TX_SUM
2989 | SKY2_HW_ADV_POWER_CTL;
2990 break;
ed4d4161
SH		 2991
2992 case CHIP_ID_YUKON_SUPR:
2993 hw->flags = SKY2_HW_GIGABIT
2994 | SKY2_HW_NEWER_PHY
2995 | SKY2_HW_NEW_LE
2996 | SKY2_HW_AUTO_TX_SUM
2997 | SKY2_HW_ADV_POWER_CTL;
2998 break;
2999
0ce8b98d 3000 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 3001 hw->flags = SKY2_HW_GIGABIT
3002 | SKY2_HW_ADV_POWER_CTL;
3003 break;
3004
0f5aac70 3005 case CHIP_ID_YUKON_OPT:
0ce8b98d 3006 hw->flags = SKY2_HW_GIGABIT
b338682d 3007 | SKY2_HW_NEW_LE
0ce8b98d
SH		 3008 | SKY2_HW_ADV_POWER_CTL;
3009 break;
3010
ea76e635 3011 default:
b02a9258
SH		 3012 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3013 hw->chip_id);
cd28ab6a
SH		 3014 return -EOPNOTSUPP;
3015 }
3016
ea76e635
SH		 3017 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3018 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3019 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3020
e3173832
SH		 3021 hw->ports = 1;
3022 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3023 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3024 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3025 ++hw->ports;
3026 }
3027
74a61ebf
MM		 3028 if (sky2_read8(hw, B2_E_0))
3029 hw->flags |= SKY2_HW_RAM_BUFFER;
3030
e3173832
SH		 3031 return 0;
3032}
3033
3034static void sky2_reset(struct sky2_hw *hw)
3035{
555382cb 3036 struct pci_dev *pdev = hw->pdev;
e3173832 3037 u16 status;
555382cb
SH		 3038 int i, cap;
3039 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3040
cd28ab6a 3041 /* disable ASF */
acd12dde 3042 if (hw->chip_id == CHIP_ID_YUKON_EX
3043 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3044 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3045 status = sky2_read16(hw, HCU_CCSR);
3046 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3047 HCU_CCSR_UC_STATE_MSK);
acd12dde 3048 /*
3049 * CPU clock divider shouldn't be used because
3050 * - ASF firmware may malfunction
3051 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3052 */
3053 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3054 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3055 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3056 } else
3057 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3058 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3059
3060 /* do a SW reset */
3061 sky2_write8(hw, B0_CTST, CS_RST_SET);
3062 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3063
ac93a394
SH		 3064 /* allow writes to PCI config */
3065 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3066
cd28ab6a 3067 /* clear PCI errors, if any */
b32f40c4 3068 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3069 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3070 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3071
3072 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3073
555382cb
SH		 3074 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3075 if (cap) {
7782c8c4
SH		 3076 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3077 0xfffffffful);
555382cb
SH		 3078
3079 /* If error bit is stuck on ignore it */
3080 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3081 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3082 else
555382cb
SH		 3083 hwe_mask |= Y2_IS_PCI_EXP;
3084 }
cd28ab6a 3085
ae306cca 3086 sky2_power_on(hw);
a40ccc68 3087 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3088
3089 for (i = 0; i < hw->ports; i++) {
3090 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3091 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3092
ed4d4161
SH		 3093 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3094 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3095 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3096 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3097 | GMC_BYP_RETR_ON);
877c8570
SH		 3098
3099 }
3100
3101 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3102 /* enable MACSec clock gating */
3103 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3104 }
3105
0f5aac70
SH		 3106 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3107 u16 reg;
3108 u32 msk;
3109
3110 if (hw->chip_rev == 0) {
3111 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3112 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3113
3114 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3115 reg = 10;
3116 } else {
3117 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3118 reg = 3;
3119 }
3120
3121 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3122
3123 /* reset PHY Link Detect */
a40ccc68 3124 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3125 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3126 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3127 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3128
3129
3130 /* enable PHY Quick Link */
3131 msk = sky2_read32(hw, B0_IMSK);
3132 msk |= Y2_IS_PHY_QLNK;
3133 sky2_write32(hw, B0_IMSK, msk);
3134
3135 /* check if PSMv2 was running before */
3136 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3137 if (reg & PCI_EXP_LNKCTL_ASPMC) {
8b055431 3138 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
0f5aac70
SH		 3139 /* restore the PCIe Link Control register */
3140 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3141 }
a40ccc68 3142 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3143
3144 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3145 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3146 }
3147
793b883e
SH		 3148 /* Clear I2C IRQ noise */
3149 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3150
3151 /* turn off hardware timer (unused) */
3152 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3153 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3154
69634ee7
SH		 3155 /* Turn off descriptor polling */
3156 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3157
3158 /* Turn off receive timestamp */
3159 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3160 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3161
3162 /* enable the Tx Arbiters */
3163 for (i = 0; i < hw->ports; i++)
3164 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3165
3166 /* Initialize ram interface */
3167 for (i = 0; i < hw->ports; i++) {
793b883e 3168 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3169
3170 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3171 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3172 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3173 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3174 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3175 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3176 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3177 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3178 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3179 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3180 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3181 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3182 }
3183
555382cb 3184 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3185
cd28ab6a 3186 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3187 sky2_gmac_reset(hw, i);
cd28ab6a 3188
cd28ab6a
SH		 3189 memset(hw->st_le, 0, STATUS_LE_BYTES);
3190 hw->st_idx = 0;
3191
3192 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3193 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3194
3195 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3196 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3197
3198 /* Set the list last index */
793b883e 3199 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3200
290d4de5
SH		 3201 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3202 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3203
290d4de5
SH		 3204 /* set Status-FIFO ISR watermark */
3205 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3206 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3207 else
3208 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3209
290d4de5 3210 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3211 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3212 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3213
793b883e 3214 /* enable status unit */
cd28ab6a
SH		 3215 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3216
3217 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3218 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3219 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3220}
3221
af18d8b8
SH		 3222/* Take device down (offline).
3223 * Equivalent to doing dev_stop() but this does not
3224 * inform upper layers of the transistion.
3225 */
3226static void sky2_detach(struct net_device *dev)
3227{
3228 if (netif_running(dev)) {
c36531b9 3229 netif_tx_lock(dev);
af18d8b8 3230 netif_device_detach(dev); /* stop txq */
c36531b9 3231 netif_tx_unlock(dev);
af18d8b8
SH		 3232 sky2_down(dev);
3233 }
3234}
3235
3236/* Bring device back after doing sky2_detach */
3237static int sky2_reattach(struct net_device *dev)
3238{
3239 int err = 0;
3240
3241 if (netif_running(dev)) {
3242 err = sky2_up(dev);
3243 if (err) {
3244 printk(KERN_INFO PFX "%s: could not restart %d\n",
3245 dev->name, err);
3246 dev_close(dev);
3247 } else {
3248 netif_device_attach(dev);
3249 sky2_set_multicast(dev);
3250 }
3251 }
3252
3253 return err;
3254}
3255
81906791
SH		 3256static void sky2_restart(struct work_struct *work)
3257{
3258 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
af18d8b8 3259 int i;
81906791 3260
81906791 3261 rtnl_lock();
af18d8b8
SH		 3262 for (i = 0; i < hw->ports; i++)
3263 sky2_detach(hw->dev[i]);
81906791 3264
8cfcbe99
SH		 3265 napi_disable(&hw->napi);
3266 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3267 sky2_reset(hw);
3268 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3269 napi_enable(&hw->napi);
81906791 3270
af18d8b8
SH		 3271 for (i = 0; i < hw->ports; i++)
3272 sky2_reattach(hw->dev[i]);
81906791 3273
81906791
SH		 3274 rtnl_unlock();
3275}
3276
e3173832
SH		 3277static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3278{
3279 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3280}
3281
3282static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3283{
3284 const struct sky2_port *sky2 = netdev_priv(dev);
3285
3286 wol->supported = sky2_wol_supported(sky2->hw);
3287 wol->wolopts = sky2->wol;
3288}
3289
3290static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3291{
3292 struct sky2_port *sky2 = netdev_priv(dev);
3293 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3294
8e95a202
JP		 3295 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3296 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3297 return -EOPNOTSUPP;
3298
3299 sky2->wol = wol->wolopts;
cd28ab6a
SH		 3300 return 0;
3301}
3302
28bd181a 3303static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3304{
b89165f2
SH		 3305 if (sky2_is_copper(hw)) {
3306 u32 modes = SUPPORTED_10baseT_Half
3307 | SUPPORTED_10baseT_Full
3308 | SUPPORTED_100baseT_Half
3309 | SUPPORTED_100baseT_Full
3310 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3311
ea76e635 3312 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3313 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3314 | SUPPORTED_1000baseT_Full;
3315 return modes;
cd28ab6a 3316 } else
b89165f2
SH		 3317 return SUPPORTED_1000baseT_Half
3318 | SUPPORTED_1000baseT_Full
3319 | SUPPORTED_Autoneg
3320 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3321}
3322
793b883e 3323static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3324{
3325 struct sky2_port *sky2 = netdev_priv(dev);
3326 struct sky2_hw *hw = sky2->hw;
3327
3328 ecmd->transceiver = XCVR_INTERNAL;
3329 ecmd->supported = sky2_supported_modes(hw);
3330 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3331 if (sky2_is_copper(hw)) {
cd28ab6a 3332 ecmd->port = PORT_TP;
b89165f2
SH		 3333 ecmd->speed = sky2->speed;
3334 } else {
3335 ecmd->speed = SPEED_1000;
cd28ab6a 3336 ecmd->port = PORT_FIBRE;
b89165f2 3337 }
cd28ab6a
SH		 3338
3339 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3340 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3341 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3342 ecmd->duplex = sky2->duplex;
3343 return 0;
3344}
3345
3346static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3347{
3348 struct sky2_port *sky2 = netdev_priv(dev);
3349 const struct sky2_hw *hw = sky2->hw;
3350 u32 supported = sky2_supported_modes(hw);
3351
3352 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3353 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3354 ecmd->advertising = supported;
3355 sky2->duplex = -1;
3356 sky2->speed = -1;
3357 } else {
3358 u32 setting;
3359
793b883e 3360 switch (ecmd->speed) {
cd28ab6a
SH		 3361 case SPEED_1000:
3362 if (ecmd->duplex == DUPLEX_FULL)
3363 setting = SUPPORTED_1000baseT_Full;
3364 else if (ecmd->duplex == DUPLEX_HALF)
3365 setting = SUPPORTED_1000baseT_Half;
3366 else
3367 return -EINVAL;
3368 break;
3369 case SPEED_100:
3370 if (ecmd->duplex == DUPLEX_FULL)
3371 setting = SUPPORTED_100baseT_Full;
3372 else if (ecmd->duplex == DUPLEX_HALF)
3373 setting = SUPPORTED_100baseT_Half;
3374 else
3375 return -EINVAL;
3376 break;
3377
3378 case SPEED_10:
3379 if (ecmd->duplex == DUPLEX_FULL)
3380 setting = SUPPORTED_10baseT_Full;
3381 else if (ecmd->duplex == DUPLEX_HALF)
3382 setting = SUPPORTED_10baseT_Half;
3383 else
3384 return -EINVAL;
3385 break;
3386 default:
3387 return -EINVAL;
3388 }
3389
3390 if ((setting & supported) == 0)
3391 return -EINVAL;
3392
3393 sky2->speed = ecmd->speed;
3394 sky2->duplex = ecmd->duplex;
0ea065e5 3395 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3396 }
3397
cd28ab6a
SH		 3398 sky2->advertising = ecmd->advertising;
3399
d1b139c0 3400 if (netif_running(dev)) {
1b537565 3401 sky2_phy_reinit(sky2);
d1b139c0
SH		 3402 sky2_set_multicast(dev);
3403 }
cd28ab6a
SH		 3404
3405 return 0;
3406}
3407
3408static void sky2_get_drvinfo(struct net_device *dev,
3409 struct ethtool_drvinfo *info)
3410{
3411 struct sky2_port *sky2 = netdev_priv(dev);
3412
3413 strcpy(info->driver, DRV_NAME);
3414 strcpy(info->version, DRV_VERSION);
3415 strcpy(info->fw_version, "N/A");
3416 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3417}
3418
3419static const struct sky2_stat {
793b883e
SH		 3420 char name[ETH_GSTRING_LEN];
3421 u16 offset;
cd28ab6a
SH		 3422} sky2_stats[] = {
3423 { "tx_bytes", GM_TXO_OK_HI },
3424 { "rx_bytes", GM_RXO_OK_HI },
3425 { "tx_broadcast", GM_TXF_BC_OK },
3426 { "rx_broadcast", GM_RXF_BC_OK },
3427 { "tx_multicast", GM_TXF_MC_OK },
3428 { "rx_multicast", GM_RXF_MC_OK },
3429 { "tx_unicast", GM_TXF_UC_OK },
3430 { "rx_unicast", GM_RXF_UC_OK },
3431 { "tx_mac_pause", GM_TXF_MPAUSE },
3432 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3433 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3434 { "late_collision",GM_TXF_LAT_COL },
3435 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3436 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3437 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3438
d2604540 3439 { "rx_short", GM_RXF_SHT },
cd28ab6a 3440 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3441 { "rx_64_byte_packets", GM_RXF_64B },
3442 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3443 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3444 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3445 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3446 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3447 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3448 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3449 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3450 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3451 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3452
3453 { "tx_64_byte_packets", GM_TXF_64B },
3454 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3455 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3456 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3457 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3458 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3459 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3460 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3461};
3462
cd28ab6a
SH		 3463static u32 sky2_get_rx_csum(struct net_device *dev)
3464{
3465 struct sky2_port *sky2 = netdev_priv(dev);
3466
0ea065e5 3467 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3468}
3469
3470static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3471{
3472 struct sky2_port *sky2 = netdev_priv(dev);
3473
0ea065e5
SH		 3474 if (data)
3475 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3476 else
3477 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3478
cd28ab6a
SH		 3479 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3480 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3481
3482 return 0;
3483}
3484
3485static u32 sky2_get_msglevel(struct net_device *netdev)
3486{
3487 struct sky2_port *sky2 = netdev_priv(netdev);
3488 return sky2->msg_enable;
3489}
3490
9a7ae0a9
SH		 3491static int sky2_nway_reset(struct net_device *dev)
3492{
3493 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3494
0ea065e5 3495 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3496 return -EINVAL;
3497
1b537565 3498 sky2_phy_reinit(sky2);
d1b139c0 3499 sky2_set_multicast(dev);
9a7ae0a9
SH		 3500
3501 return 0;
3502}
3503
793b883e 3504static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3505{
3506 struct sky2_hw *hw = sky2->hw;
3507 unsigned port = sky2->port;
3508 int i;
3509
3510 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3511 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3512 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3513 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3514
793b883e 3515 for (i = 2; i < count; i++)
cd28ab6a
SH		 3516 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3517}
3518
cd28ab6a
SH		 3519static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3520{
3521 struct sky2_port *sky2 = netdev_priv(netdev);
3522 sky2->msg_enable = value;
3523}
3524
b9f2c044 3525static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3526{
b9f2c044
JG		 3527 switch (sset) {
3528 case ETH_SS_STATS:
3529 return ARRAY_SIZE(sky2_stats);
3530 default:
3531 return -EOPNOTSUPP;
3532 }
cd28ab6a
SH		 3533}
3534
3535static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3536 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3537{
3538 struct sky2_port *sky2 = netdev_priv(dev);
3539
793b883e 3540 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3541}
3542
793b883e 3543static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3544{
3545 int i;
3546
3547 switch (stringset) {
3548 case ETH_SS_STATS:
3549 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3550 memcpy(data + i * ETH_GSTRING_LEN,
3551 sky2_stats[i].name, ETH_GSTRING_LEN);
3552 break;
3553 }
3554}
3555
cd28ab6a
SH		 3556static int sky2_set_mac_address(struct net_device *dev, void *p)
3557{
3558 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3559 struct sky2_hw *hw = sky2->hw;
3560 unsigned port = sky2->port;
3561 const struct sockaddr *addr = p;
cd28ab6a
SH		 3562
3563 if (!is_valid_ether_addr(addr->sa_data))
3564 return -EADDRNOTAVAIL;
3565
cd28ab6a 3566 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3567 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3568 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3569 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3570 dev->dev_addr, ETH_ALEN);
1b537565 3571
a8ab1ec0
SH		 3572 /* virtual address for data */
3573 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3574
3575 /* physical address: used for pause frames */
3576 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3577
3578 return 0;
cd28ab6a
SH		 3579}
3580
a052b52f
SH		 3581static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3582{
3583 u32 bit;
3584
3585 bit = ether_crc(ETH_ALEN, addr) & 63;
3586 filter[bit >> 3] |= 1 << (bit & 7);
3587}
3588
cd28ab6a
SH		 3589static void sky2_set_multicast(struct net_device *dev)
3590{
3591 struct sky2_port *sky2 = netdev_priv(dev);
3592 struct sky2_hw *hw = sky2->hw;
3593 unsigned port = sky2->port;
3594 struct dev_mc_list *list = dev->mc_list;
3595 u16 reg;
3596 u8 filter[8];
a052b52f
SH		 3597 int rx_pause;
3598 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3599
a052b52f 3600 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3601 memset(filter, 0, sizeof(filter));
3602
3603 reg = gma_read16(hw, port, GM_RX_CTRL);
3604 reg |= GM_RXCR_UCF_ENA;
3605
d571b694 3606 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3607 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3608 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3609 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3610 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3611 reg &= ~GM_RXCR_MCF_ENA;
3612 else {
3613 int i;
3614 reg |= GM_RXCR_MCF_ENA;
3615
a052b52f
SH		 3616 if (rx_pause)
3617 sky2_add_filter(filter, pause_mc_addr);
3618
4cd24eaf 3619 for (i = 0; list && i < netdev_mc_count(dev); i++, list = list->next)
a052b52f 3620 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3621 }
3622
cd28ab6a 3623 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3624 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3625 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3626 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3627 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3628 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3629 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3630 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3631
3632 gma_write16(hw, port, GM_RX_CTRL, reg);
3633}
3634
3635/* Can have one global because blinking is controlled by
3636 * ethtool and that is always under RTNL mutex
3637 */
a84d0a3d 3638static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3639{
a84d0a3d
SH		 3640 struct sky2_hw *hw = sky2->hw;
3641 unsigned port = sky2->port;
793b883e 3642
a84d0a3d
SH		 3643 spin_lock_bh(&sky2->phy_lock);
3644 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3645 hw->chip_id == CHIP_ID_YUKON_EX ||
3646 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3647 u16 pg;
793b883e
SH		 3648 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3649 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3650
a84d0a3d
SH		 3651 switch (mode) {
3652 case MO_LED_OFF:
3653 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3654 PHY_M_LEDC_LOS_CTRL(8) |
3655 PHY_M_LEDC_INIT_CTRL(8) |
3656 PHY_M_LEDC_STA1_CTRL(8) |
3657 PHY_M_LEDC_STA0_CTRL(8));
3658 break;
3659 case MO_LED_ON:
3660 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3661 PHY_M_LEDC_LOS_CTRL(9) |
3662 PHY_M_LEDC_INIT_CTRL(9) |
3663 PHY_M_LEDC_STA1_CTRL(9) |
3664 PHY_M_LEDC_STA0_CTRL(9));
3665 break;
3666 case MO_LED_BLINK:
3667 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3668 PHY_M_LEDC_LOS_CTRL(0xa) |
3669 PHY_M_LEDC_INIT_CTRL(0xa) |
3670 PHY_M_LEDC_STA1_CTRL(0xa) |
3671 PHY_M_LEDC_STA0_CTRL(0xa));
3672 break;
3673 case MO_LED_NORM:
3674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3675 PHY_M_LEDC_LOS_CTRL(1) |
3676 PHY_M_LEDC_INIT_CTRL(8) |
3677 PHY_M_LEDC_STA1_CTRL(7) |
3678 PHY_M_LEDC_STA0_CTRL(7));
3679 }
793b883e 3680
a84d0a3d
SH		 3681 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3682 } else
7d2e3cb7 3683 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3684 PHY_M_LED_MO_DUP(mode) |
3685 PHY_M_LED_MO_10(mode) |
3686 PHY_M_LED_MO_100(mode) |
3687 PHY_M_LED_MO_1000(mode) |
3688 PHY_M_LED_MO_RX(mode) |
3689 PHY_M_LED_MO_TX(mode));
3690
3691 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3692}
3693
3694/* blink LED's for finding board */
3695static int sky2_phys_id(struct net_device *dev, u32 data)
3696{
3697 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3698 unsigned int i;
cd28ab6a 3699
a84d0a3d
SH		 3700 if (data == 0)
3701 data = UINT_MAX;
cd28ab6a 3702
a84d0a3d
SH		 3703 for (i = 0; i < data; i++) {
3704 sky2_led(sky2, MO_LED_ON);
3705 if (msleep_interruptible(500))
3706 break;
3707 sky2_led(sky2, MO_LED_OFF);
3708 if (msleep_interruptible(500))
3709 break;
793b883e 3710 }
a84d0a3d 3711 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3712
3713 return 0;
3714}
3715
3716static void sky2_get_pauseparam(struct net_device *dev,
3717 struct ethtool_pauseparam *ecmd)
3718{
3719 struct sky2_port *sky2 = netdev_priv(dev);
3720
16ad91e1
SH		 3721 switch (sky2->flow_mode) {
3722 case FC_NONE:
3723 ecmd->tx_pause = ecmd->rx_pause = 0;
3724 break;
3725 case FC_TX:
3726 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3727 break;
3728 case FC_RX:
3729 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3730 break;
3731 case FC_BOTH:
3732 ecmd->tx_pause = ecmd->rx_pause = 1;
3733 }
3734
0ea065e5
SH		 3735 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3736 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3737}
3738
3739static int sky2_set_pauseparam(struct net_device *dev,
3740 struct ethtool_pauseparam *ecmd)
3741{
3742 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3743
0ea065e5
SH		 3744 if (ecmd->autoneg == AUTONEG_ENABLE)
3745 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3746 else
3747 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3748
16ad91e1 3749 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3750
16ad91e1
SH		 3751 if (netif_running(dev))
3752 sky2_phy_reinit(sky2);
cd28ab6a 3753
2eaba1a2 3754 return 0;
cd28ab6a
SH		 3755}
3756
fb17358f
SH		 3757static int sky2_get_coalesce(struct net_device *dev,
3758 struct ethtool_coalesce *ecmd)
3759{
3760 struct sky2_port *sky2 = netdev_priv(dev);
3761 struct sky2_hw *hw = sky2->hw;
3762
3763 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3764 ecmd->tx_coalesce_usecs = 0;
3765 else {
3766 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3767 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3768 }
3769 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3770
3771 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3772 ecmd->rx_coalesce_usecs = 0;
3773 else {
3774 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3775 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3776 }
3777 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3778
3779 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3780 ecmd->rx_coalesce_usecs_irq = 0;
3781 else {
3782 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3783 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3784 }
3785
3786 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3787
3788 return 0;
3789}
3790
3791/* Note: this affect both ports */
3792static int sky2_set_coalesce(struct net_device *dev,
3793 struct ethtool_coalesce *ecmd)
3794{
3795 struct sky2_port *sky2 = netdev_priv(dev);
3796 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3797 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3798
77b3d6a2
SH		 3799 if (ecmd->tx_coalesce_usecs > tmax ||
3800 ecmd->rx_coalesce_usecs > tmax ||
3801 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3802 return -EINVAL;
3803
ee5f68fe 3804 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3805 return -EINVAL;
ff81fbbe 3806 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3807 return -EINVAL;
ff81fbbe 3808 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3809 return -EINVAL;
3810
3811 if (ecmd->tx_coalesce_usecs == 0)
3812 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3813 else {
3814 sky2_write32(hw, STAT_TX_TIMER_INI,
3815 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3816 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3817 }
3818 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3819
3820 if (ecmd->rx_coalesce_usecs == 0)
3821 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3822 else {
3823 sky2_write32(hw, STAT_LEV_TIMER_INI,
3824 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3825 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3826 }
3827 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3828
3829 if (ecmd->rx_coalesce_usecs_irq == 0)
3830 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3831 else {
d28d4870 3832 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3833 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3834 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3835 }
3836 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3837 return 0;
3838}
3839
793b883e
SH		 3840static void sky2_get_ringparam(struct net_device *dev,
3841 struct ethtool_ringparam *ering)
3842{
3843 struct sky2_port *sky2 = netdev_priv(dev);
3844
3845 ering->rx_max_pending = RX_MAX_PENDING;
3846 ering->rx_mini_max_pending = 0;
3847 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3848 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3849
3850 ering->rx_pending = sky2->rx_pending;
3851 ering->rx_mini_pending = 0;
3852 ering->rx_jumbo_pending = 0;
3853 ering->tx_pending = sky2->tx_pending;
3854}
3855
3856static int sky2_set_ringparam(struct net_device *dev,
3857 struct ethtool_ringparam *ering)
3858{
3859 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3860
3861 if (ering->rx_pending > RX_MAX_PENDING ||
3862 ering->rx_pending < 8 ||
ee5f68fe
SH		 3863 ering->tx_pending < TX_MIN_PENDING ||
3864 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3865 return -EINVAL;
3866
af18d8b8 3867 sky2_detach(dev);
793b883e
SH		 3868
3869 sky2->rx_pending = ering->rx_pending;
3870 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3871 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3872
af18d8b8 3873 return sky2_reattach(dev);
793b883e
SH		 3874}
3875
793b883e
SH		 3876static int sky2_get_regs_len(struct net_device *dev)
3877{
6e4cbb34 3878 return 0x4000;
793b883e
SH		 3879}
3880
c32bbff8
MM		 3881static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3882{
3883 /* This complicated switch statement is to make sure and
3884 * only access regions that are unreserved.
3885 * Some blocks are only valid on dual port cards.
3886 */
3887 switch (b) {
3888 /* second port */
3889 case 5: /* Tx Arbiter 2 */
3890 case 9: /* RX2 */
3891 case 14 ... 15: /* TX2 */
3892 case 17: case 19: /* Ram Buffer 2 */
3893 case 22 ... 23: /* Tx Ram Buffer 2 */
3894 case 25: /* Rx MAC Fifo 1 */
3895 case 27: /* Tx MAC Fifo 2 */
3896 case 31: /* GPHY 2 */
3897 case 40 ... 47: /* Pattern Ram 2 */
3898 case 52: case 54: /* TCP Segmentation 2 */
3899 case 112 ... 116: /* GMAC 2 */
3900 return hw->ports > 1;
3901
3902 case 0: /* Control */
3903 case 2: /* Mac address */
3904 case 4: /* Tx Arbiter 1 */
3905 case 7: /* PCI express reg */
3906 case 8: /* RX1 */
3907 case 12 ... 13: /* TX1 */
3908 case 16: case 18:/* Rx Ram Buffer 1 */
3909 case 20 ... 21: /* Tx Ram Buffer 1 */
3910 case 24: /* Rx MAC Fifo 1 */
3911 case 26: /* Tx MAC Fifo 1 */
3912 case 28 ... 29: /* Descriptor and status unit */
3913 case 30: /* GPHY 1*/
3914 case 32 ... 39: /* Pattern Ram 1 */
3915 case 48: case 50: /* TCP Segmentation 1 */
3916 case 56 ... 60: /* PCI space */
3917 case 80 ... 84: /* GMAC 1 */
3918 return 1;
3919
3920 default:
3921 return 0;
3922 }
3923}
3924
793b883e
SH		 3925/*
3926 * Returns copy of control register region
3ead5db7 3927 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3928 */
3929static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3930 void *p)
3931{
3932 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3933 const void __iomem *io = sky2->hw->regs;
295b54c4 3934 unsigned int b;
793b883e
SH		 3935
3936 regs->version = 1;
793b883e 3937
295b54c4 3938 for (b = 0; b < 128; b++) {
c32bbff8
MM		 3939 /* skip poisonous diagnostic ram region in block 3 */
3940 if (b == 3)
295b54c4 3941 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 3942 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 3943 memcpy_fromio(p, io, 128);
c32bbff8 3944 else
295b54c4 3945 memset(p, 0, 128);
3ead5db7 3946
295b54c4
SH		 3947 p += 128;
3948 io += 128;
3949 }
793b883e 3950}
cd28ab6a 3951
b628ed98
SH		 3952/* In order to do Jumbo packets on these chips, need to turn off the
3953 * transmit store/forward. Therefore checksum offload won't work.
3954 */
3955static int no_tx_offload(struct net_device *dev)
3956{
3957 const struct sky2_port *sky2 = netdev_priv(dev);
3958 const struct sky2_hw *hw = sky2->hw;
3959
69161611 3960 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3961}
3962
3963static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3964{
3965 if (data && no_tx_offload(dev))
3966 return -EINVAL;
3967
3968 return ethtool_op_set_tx_csum(dev, data);
3969}
3970
3971
3972static int sky2_set_tso(struct net_device *dev, u32 data)
3973{
3974 if (data && no_tx_offload(dev))
3975 return -EINVAL;
3976
3977 return ethtool_op_set_tso(dev, data);
3978}
3979
f4331a6d
SH		 3980static int sky2_get_eeprom_len(struct net_device *dev)
3981{
3982 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3983 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3984 u16 reg2;
3985
b32f40c4 3986 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3987 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3988}
3989
1413235c 3990static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3991{
1413235c 3992 unsigned long start = jiffies;
f4331a6d 3993
1413235c
SH		 3994 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3995 /* Can take up to 10.6 ms for write */
3996 if (time_after(jiffies, start + HZ/4)) {
3997 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3998 return -ETIMEDOUT;
3999 }
4000 mdelay(1);
4001 }
167f53d0 4002
1413235c
SH		 4003 return 0;
4004}
167f53d0 4005
1413235c
SH		 4006static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4007 u16 offset, size_t length)
4008{
4009 int rc = 0;
4010
4011 while (length > 0) {
4012 u32 val;
4013
4014 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4015 rc = sky2_vpd_wait(hw, cap, 0);
4016 if (rc)
4017 break;
4018
4019 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4020
4021 memcpy(data, &val, min(sizeof(val), length));
4022 offset += sizeof(u32);
4023 data += sizeof(u32);
4024 length -= sizeof(u32);
4025 }
4026
4027 return rc;
f4331a6d
SH		 4028}
4029
1413235c
SH		 4030static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4031 u16 offset, unsigned int length)
f4331a6d 4032{
1413235c
SH		 4033 unsigned int i;
4034 int rc = 0;
4035
4036 for (i = 0; i < length; i += sizeof(u32)) {
4037 u32 val = *(u32 *)(data + i);
4038
4039 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4040 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4041
4042 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4043 if (rc)
4044 break;
4045 }
4046 return rc;
f4331a6d
SH		 4047}
4048
4049static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4050 u8 *data)
4051{
4052 struct sky2_port *sky2 = netdev_priv(dev);
4053 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4054
4055 if (!cap)
4056 return -EINVAL;
4057
4058 eeprom->magic = SKY2_EEPROM_MAGIC;
4059
1413235c 4060 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4061}
4062
4063static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4064 u8 *data)
4065{
4066 struct sky2_port *sky2 = netdev_priv(dev);
4067 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4068
4069 if (!cap)
4070 return -EINVAL;
4071
4072 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4073 return -EINVAL;
4074
1413235c
SH		 4075 /* Partial writes not supported */
4076 if ((eeprom->offset & 3) || (eeprom->len & 3))
4077 return -EINVAL;
f4331a6d 4078
1413235c 4079 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4080}
4081
4082
7282d491 4083static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4084 .get_settings = sky2_get_settings,
4085 .set_settings = sky2_set_settings,
4086 .get_drvinfo = sky2_get_drvinfo,
4087 .get_wol = sky2_get_wol,
4088 .set_wol = sky2_set_wol,
4089 .get_msglevel = sky2_get_msglevel,
4090 .set_msglevel = sky2_set_msglevel,
4091 .nway_reset = sky2_nway_reset,
4092 .get_regs_len = sky2_get_regs_len,
4093 .get_regs = sky2_get_regs,
4094 .get_link = ethtool_op_get_link,
4095 .get_eeprom_len = sky2_get_eeprom_len,
4096 .get_eeprom = sky2_get_eeprom,
4097 .set_eeprom = sky2_set_eeprom,
f4331a6d 4098 .set_sg = ethtool_op_set_sg,
f4331a6d 4099 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 4100 .set_tso = sky2_set_tso,
4101 .get_rx_csum = sky2_get_rx_csum,
4102 .set_rx_csum = sky2_set_rx_csum,
4103 .get_strings = sky2_get_strings,
4104 .get_coalesce = sky2_get_coalesce,
4105 .set_coalesce = sky2_set_coalesce,
4106 .get_ringparam = sky2_get_ringparam,
4107 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4108 .get_pauseparam = sky2_get_pauseparam,
4109 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 4110 .phys_id = sky2_phys_id,
b9f2c044 4111 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 4112 .get_ethtool_stats = sky2_get_ethtool_stats,
4113};
4114
3cf26753
SH		 4115#ifdef CONFIG_SKY2_DEBUG
4116
4117static struct dentry *sky2_debug;
4118
e4c2abe2
SH		 4119
4120/*
4121 * Read and parse the first part of Vital Product Data
4122 */
4123#define VPD_SIZE 128
4124#define VPD_MAGIC 0x82
4125
4126static const struct vpd_tag {
4127 char tag[2];
4128 char *label;
4129} vpd_tags[] = {
4130 { "PN", "Part Number" },
4131 { "EC", "Engineering Level" },
4132 { "MN", "Manufacturer" },
4133 { "SN", "Serial Number" },
4134 { "YA", "Asset Tag" },
4135 { "VL", "First Error Log Message" },
4136 { "VF", "Second Error Log Message" },
4137 { "VB", "Boot Agent ROM Configuration" },
4138 { "VE", "EFI UNDI Configuration" },
4139};
4140
4141static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4142{
4143 size_t vpd_size;
4144 loff_t offs;
4145 u8 len;
4146 unsigned char *buf;
4147 u16 reg2;
4148
4149 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4150 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4151
4152 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4153 buf = kmalloc(vpd_size, GFP_KERNEL);
4154 if (!buf) {
4155 seq_puts(seq, "no memory!\n");
4156 return;
4157 }
4158
4159 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4160 seq_puts(seq, "VPD read failed\n");
4161 goto out;
4162 }
4163
4164 if (buf[0] != VPD_MAGIC) {
4165 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4166 goto out;
4167 }
4168 len = buf[1];
4169 if (len == 0 || len > vpd_size - 4) {
4170 seq_printf(seq, "Invalid id length: %d\n", len);
4171 goto out;
4172 }
4173
4174 seq_printf(seq, "%.*s\n", len, buf + 3);
4175 offs = len + 3;
4176
4177 while (offs < vpd_size - 4) {
4178 int i;
4179
4180 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4181 break;
4182 len = buf[offs + 2];
4183 if (offs + len + 3 >= vpd_size)
4184 break;
4185
4186 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4187 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4188 seq_printf(seq, " %s: %.*s\n",
4189 vpd_tags[i].label, len, buf + offs + 3);
4190 break;
4191 }
4192 }
4193 offs += len + 3;
4194 }
4195out:
4196 kfree(buf);
4197}
4198
3cf26753
SH		 4199static int sky2_debug_show(struct seq_file *seq, void *v)
4200{
4201 struct net_device *dev = seq->private;
4202 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4203 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4204 unsigned port = sky2->port;
4205 unsigned idx, last;
4206 int sop;
4207
e4c2abe2 4208 sky2_show_vpd(seq, hw);
3cf26753 4209
e4c2abe2 4210 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4211 sky2_read32(hw, B0_ISRC),
4212 sky2_read32(hw, B0_IMSK),
4213 sky2_read32(hw, B0_Y2_SP_ICR));
4214
e4c2abe2
SH		 4215 if (!netif_running(dev)) {
4216 seq_printf(seq, "network not running\n");
4217 return 0;
4218 }
4219
bea3348e 4220 napi_disable(&hw->napi);
3cf26753
SH		 4221 last = sky2_read16(hw, STAT_PUT_IDX);
4222
4223 if (hw->st_idx == last)
4224 seq_puts(seq, "Status ring (empty)\n");
4225 else {
4226 seq_puts(seq, "Status ring\n");
4227 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4228 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4229 const struct sky2_status_le *le = hw->st_le + idx;
4230 seq_printf(seq, "[%d] %#x %d %#x\n",
4231 idx, le->opcode, le->length, le->status);
4232 }
4233 seq_puts(seq, "\n");
4234 }
4235
4236 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4237 sky2->tx_cons, sky2->tx_prod,
4238 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4239 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4240
4241 /* Dump contents of tx ring */
4242 sop = 1;
ee5f68fe
SH		 4243 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4244 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4245 const struct sky2_tx_le *le = sky2->tx_le + idx;
4246 u32 a = le32_to_cpu(le->addr);
4247
4248 if (sop)
4249 seq_printf(seq, "%u:", idx);
4250 sop = 0;
4251
4252 switch(le->opcode & ~HW_OWNER) {
4253 case OP_ADDR64:
4254 seq_printf(seq, " %#x:", a);
4255 break;
4256 case OP_LRGLEN:
4257 seq_printf(seq, " mtu=%d", a);
4258 break;
4259 case OP_VLAN:
4260 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4261 break;
4262 case OP_TCPLISW:
4263 seq_printf(seq, " csum=%#x", a);
4264 break;
4265 case OP_LARGESEND:
4266 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4267 break;
4268 case OP_PACKET:
4269 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4270 break;
4271 case OP_BUFFER:
4272 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4273 break;
4274 default:
4275 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4276 a, le16_to_cpu(le->length));
4277 }
4278
4279 if (le->ctrl & EOP) {
4280 seq_putc(seq, '\n');
4281 sop = 1;
4282 }
4283 }
4284
4285 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4286 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4287 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4288 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4289
d1d08d12 4290 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4291 napi_enable(&hw->napi);
3cf26753
SH		 4292 return 0;
4293}
4294
4295static int sky2_debug_open(struct inode *inode, struct file *file)
4296{
4297 return single_open(file, sky2_debug_show, inode->i_private);
4298}
4299
4300static const struct file_operations sky2_debug_fops = {
4301 .owner = THIS_MODULE,
4302 .open = sky2_debug_open,
4303 .read = seq_read,
4304 .llseek = seq_lseek,
4305 .release = single_release,
4306};
4307
4308/*
4309 * Use network device events to create/remove/rename
4310 * debugfs file entries
4311 */
4312static int sky2_device_event(struct notifier_block *unused,
4313 unsigned long event, void *ptr)
4314{
4315 struct net_device *dev = ptr;
5b296bc9 4316 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4317
1436b301 4318 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4319 return NOTIFY_DONE;
3cf26753 4320
5b296bc9
SH		 4321 switch(event) {
4322 case NETDEV_CHANGENAME:
4323 if (sky2->debugfs) {
4324 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4325 sky2_debug, dev->name);
4326 }
4327 break;
3cf26753 4328
5b296bc9
SH		 4329 case NETDEV_GOING_DOWN:
4330 if (sky2->debugfs) {
4331 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4332 dev->name);
4333 debugfs_remove(sky2->debugfs);
4334 sky2->debugfs = NULL;
3cf26753 4335 }
5b296bc9
SH		 4336 break;
4337
4338 case NETDEV_UP:
4339 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4340 sky2_debug, dev,
4341 &sky2_debug_fops);
4342 if (IS_ERR(sky2->debugfs))
4343 sky2->debugfs = NULL;
3cf26753
SH		 4344 }
4345
4346 return NOTIFY_DONE;
4347}
4348
4349static struct notifier_block sky2_notifier = {
4350 .notifier_call = sky2_device_event,
4351};
4352
4353
4354static __init void sky2_debug_init(void)
4355{
4356 struct dentry *ent;
4357
4358 ent = debugfs_create_dir("sky2", NULL);
4359 if (!ent || IS_ERR(ent))
4360 return;
4361
4362 sky2_debug = ent;
4363 register_netdevice_notifier(&sky2_notifier);
4364}
4365
4366static __exit void sky2_debug_cleanup(void)
4367{
4368 if (sky2_debug) {
4369 unregister_netdevice_notifier(&sky2_notifier);
4370 debugfs_remove(sky2_debug);
4371 sky2_debug = NULL;
4372 }
4373}
4374
4375#else
4376#define sky2_debug_init()
4377#define sky2_debug_cleanup()
4378#endif
4379
1436b301
SH		 4380/* Two copies of network device operations to handle special case of
4381 not allowing netpoll on second port */
4382static const struct net_device_ops sky2_netdev_ops[2] = {
4383 {
4384 .ndo_open = sky2_up,
4385 .ndo_stop = sky2_down,
00829823 4386 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4387 .ndo_do_ioctl = sky2_ioctl,
4388 .ndo_validate_addr = eth_validate_addr,
4389 .ndo_set_mac_address = sky2_set_mac_address,
4390 .ndo_set_multicast_list = sky2_set_multicast,
4391 .ndo_change_mtu = sky2_change_mtu,
4392 .ndo_tx_timeout = sky2_tx_timeout,
4393#ifdef SKY2_VLAN_TAG_USED
4394 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4395#endif
4396#ifdef CONFIG_NET_POLL_CONTROLLER
4397 .ndo_poll_controller = sky2_netpoll,
4398#endif
4399 },
4400 {
4401 .ndo_open = sky2_up,
4402 .ndo_stop = sky2_down,
00829823 4403 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4404 .ndo_do_ioctl = sky2_ioctl,
4405 .ndo_validate_addr = eth_validate_addr,
4406 .ndo_set_mac_address = sky2_set_mac_address,
4407 .ndo_set_multicast_list = sky2_set_multicast,
4408 .ndo_change_mtu = sky2_change_mtu,
4409 .ndo_tx_timeout = sky2_tx_timeout,
4410#ifdef SKY2_VLAN_TAG_USED
4411 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4412#endif
4413 },
4414};
3cf26753 4415
cd28ab6a
SH		 4416/* Initialize network device */
4417static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4418 unsigned port,
be63a21c 4419 int highmem, int wol)
cd28ab6a
SH		 4420{
4421 struct sky2_port *sky2;
4422 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4423
4424 if (!dev) {
898eb71c 4425 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4426 return NULL;
4427 }
4428
cd28ab6a 4429 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4430 dev->irq = hw->pdev->irq;
cd28ab6a 4431 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4432 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4433 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4434
4435 sky2 = netdev_priv(dev);
4436 sky2->netdev = dev;
4437 sky2->hw = hw;
4438 sky2->msg_enable = netif_msg_init(debug, default_msg);
4439
cd28ab6a 4440 /* Auto speed and flow control */
0ea065e5
SH		 4441 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4442 if (hw->chip_id != CHIP_ID_YUKON_XL)
4443 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4444
16ad91e1
SH		 4445 sky2->flow_mode = FC_BOTH;
4446
cd28ab6a
SH		 4447 sky2->duplex = -1;
4448 sky2->speed = -1;
4449 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4450 sky2->wol = wol;
75d070c5 4451
e07b1aa8 4452 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4453
793b883e 4454 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4455 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4456 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4457
4458 hw->dev[port] = dev;
4459
4460 sky2->port = port;
4461
4a50a876 4462 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4463 if (highmem)
4464 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4465
d1f13708 4466#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4467 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4468 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4469 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4470 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4471 }
d1f13708
SH		 4472#endif
4473
cd28ab6a 4474 /* read the mac address */
793b883e 4475 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4476 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4477
cd28ab6a
SH		 4478 return dev;
4479}
4480
28bd181a 4481static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4482{
4483 const struct sky2_port *sky2 = netdev_priv(dev);
4484
4485 if (netif_msg_probe(sky2))
e174961c
JB		 4486 printk(KERN_INFO PFX "%s: addr %pM\n",
4487 dev->name, dev->dev_addr);
cd28ab6a
SH		 4488}
4489
fb2690a9 4490/* Handle software interrupt used during MSI test */
7d12e780 4491static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4492{
4493 struct sky2_hw *hw = dev_id;
4494 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4495
4496 if (status == 0)
4497 return IRQ_NONE;
4498
4499 if (status & Y2_IS_IRQ_SW) {
ea76e635 4500 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4501 wake_up(&hw->msi_wait);
4502 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4503 }
4504 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4505
4506 return IRQ_HANDLED;
4507}
4508
4509/* Test interrupt path by forcing a a software IRQ */
4510static int __devinit sky2_test_msi(struct sky2_hw *hw)
4511{
4512 struct pci_dev *pdev = hw->pdev;
4513 int err;
4514
bb507fe1
SH		 4515 init_waitqueue_head (&hw->msi_wait);
4516
fb2690a9
SH		 4517 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4518
b0a20ded 4519 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4520 if (err) {
b02a9258 4521 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4522 return err;
4523 }
4524
fb2690a9 4525 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4526 sky2_read8(hw, B0_CTST);
fb2690a9 4527
ea76e635 4528 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4529
ea76e635 4530 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4531 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4532 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4533 "switching to INTx mode.\n");
fb2690a9
SH		 4534
4535 err = -EOPNOTSUPP;
4536 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4537 }
4538
4539 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4540 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4541
4542 free_irq(pdev->irq, hw);
4543
4544 return err;
4545}
4546
c7127a34
SH		 4547/* This driver supports yukon2 chipset only */
4548static const char *sky2_name(u8 chipid, char *buf, int sz)
4549{
4550 const char *name[] = {
4551 "XL", /* 0xb3 */
4552 "EC Ultra", /* 0xb4 */
4553 "Extreme", /* 0xb5 */
4554 "EC", /* 0xb6 */
4555 "FE", /* 0xb7 */
4556 "FE+", /* 0xb8 */
4557 "Supreme", /* 0xb9 */
0ce8b98d 4558 "UL 2", /* 0xba */
0f5aac70
SH		 4559 "Unknown", /* 0xbb */
4560 "Optima", /* 0xbc */
c7127a34
SH		 4561 };
4562
dae3a511 4563 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
c7127a34
SH		 4564 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4565 else
4566 snprintf(buf, sz, "(chip %#x)", chipid);
4567 return buf;
4568}
4569
cd28ab6a
SH		 4570static int __devinit sky2_probe(struct pci_dev *pdev,
4571 const struct pci_device_id *ent)
4572{
7f60c64b 4573 struct net_device *dev;
cd28ab6a 4574 struct sky2_hw *hw;
be63a21c 4575 int err, using_dac = 0, wol_default;
3834507d 4576 u32 reg;
c7127a34 4577 char buf1[16];
cd28ab6a 4578
793b883e
SH		 4579 err = pci_enable_device(pdev);
4580 if (err) {
b02a9258 4581 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4582 goto err_out;
4583 }
4584
6cc90a5a
SH		 4585 /* Get configuration information
4586 * Note: only regular PCI config access once to test for HW issues
4587 * other PCI access through shared memory for speed and to
4588 * avoid MMCONFIG problems.
4589 */
4590 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4591 if (err) {
4592 dev_err(&pdev->dev, "PCI read config failed\n");
4593 goto err_out;
4594 }
4595
4596 if (~reg == 0) {
4597 dev_err(&pdev->dev, "PCI configuration read error\n");
4598 goto err_out;
4599 }
4600
793b883e
SH		 4601 err = pci_request_regions(pdev, DRV_NAME);
4602 if (err) {
b02a9258 4603 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4604 goto err_out_disable;
cd28ab6a
SH		 4605 }
4606
4607 pci_set_master(pdev);
4608
d1f3d4dd 4609 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4610 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4611 using_dac = 1;
6a35528a 4612 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4613 if (err < 0) {
b02a9258
SH		 4614 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4615 "for consistent allocations\n");
d1f3d4dd
SH		 4616 goto err_out_free_regions;
4617 }
d1f3d4dd 4618 } else {
284901a9 4619 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4620 if (err) {
b02a9258 4621 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4622 goto err_out_free_regions;
4623 }
4624 }
d1f3d4dd 4625
3834507d
SH		 4626
4627#ifdef __BIG_ENDIAN
4628 /* The sk98lin vendor driver uses hardware byte swapping but
4629 * this driver uses software swapping.
4630 */
4631 reg &= ~PCI_REV_DESC;
4632 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4633 if (err) {
4634 dev_err(&pdev->dev, "PCI write config failed\n");
4635 goto err_out_free_regions;
4636 }
4637#endif
4638
9d731d77 4639 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4640
cd28ab6a 4641 err = -ENOMEM;
66466797
SH		 4642
4643 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4644 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4645 if (!hw) {
b02a9258 4646 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4647 goto err_out_free_regions;
4648 }
4649
cd28ab6a 4650 hw->pdev = pdev;
66466797 4651 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4652
4653 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4654 if (!hw->regs) {
b02a9258 4655 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4656 goto err_out_free_hw;
4657 }
4658
08c06d8a 4659 /* ring for status responses */
167f53d0 4660 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4661 if (!hw->st_le)
4662 goto err_out_iounmap;
4663
e3173832 4664 err = sky2_init(hw);
cd28ab6a 4665 if (err)
793b883e 4666 goto err_out_iounmap;
cd28ab6a 4667
c844d483
SH		 4668 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4669 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4670
e3173832
SH		 4671 sky2_reset(hw);
4672
be63a21c 4673 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4674 if (!dev) {
4675 err = -ENOMEM;
cd28ab6a 4676 goto err_out_free_pci;
7f60c64b 4677 }
cd28ab6a 4678
9fa1b1f3
SH		 4679 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4680 err = sky2_test_msi(hw);
4681 if (err == -EOPNOTSUPP)
4682 pci_disable_msi(pdev);
4683 else if (err)
4684 goto err_out_free_netdev;
4685 }
4686
793b883e
SH		 4687 err = register_netdev(dev);
4688 if (err) {
b02a9258 4689 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4690 goto err_out_free_netdev;
4691 }
4692
33cb7d33
BP		 4693 netif_carrier_off(dev);
4694
6de16237
SH		 4695 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4696
ea76e635
SH		 4697 err = request_irq(pdev->irq, sky2_intr,
4698 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4699 hw->irq_name, hw);
9fa1b1f3 4700 if (err) {
b02a9258 4701 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4702 goto err_out_unregister;
4703 }
4704 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4705 napi_enable(&hw->napi);
9fa1b1f3 4706
cd28ab6a
SH		 4707 sky2_show_addr(dev);
4708
7f60c64b 4709 if (hw->ports > 1) {
4710 struct net_device *dev1;
4711
ca519274 4712 err = -ENOMEM;
be63a21c 4713 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4714 if (dev1 && (err = register_netdev(dev1)) == 0)
4715 sky2_show_addr(dev1);
4716 else {
b02a9258
SH		 4717 dev_warn(&pdev->dev,
4718 "register of second port failed (%d)\n", err);
cd28ab6a 4719 hw->dev[1] = NULL;
ca519274
SH		 4720 hw->ports = 1;
4721 if (dev1)
4722 free_netdev(dev1);
4723 }
cd28ab6a
SH		 4724 }
4725
32c2c300 4726 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4727 INIT_WORK(&hw->restart_work, sky2_restart);
4728
793b883e 4729 pci_set_drvdata(pdev, hw);
1ae861e6 4730 pdev->d3_delay = 150;
793b883e 4731
cd28ab6a
SH		 4732 return 0;
4733
793b883e 4734err_out_unregister:
ea76e635 4735 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4736 pci_disable_msi(pdev);
793b883e 4737 unregister_netdev(dev);
cd28ab6a
SH		 4738err_out_free_netdev:
4739 free_netdev(dev);
cd28ab6a 4740err_out_free_pci:
793b883e 4741 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4742 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4743err_out_iounmap:
4744 iounmap(hw->regs);
4745err_out_free_hw:
4746 kfree(hw);
4747err_out_free_regions:
4748 pci_release_regions(pdev);
44a1d2e5 4749err_out_disable:
cd28ab6a 4750 pci_disable_device(pdev);
cd28ab6a 4751err_out:
549a68c3 4752 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4753 return err;
4754}
4755
4756static void __devexit sky2_remove(struct pci_dev *pdev)
4757{
793b883e 4758 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4759 int i;
cd28ab6a 4760
793b883e 4761 if (!hw)
cd28ab6a
SH		 4762 return;
4763
32c2c300 4764 del_timer_sync(&hw->watchdog_timer);
6de16237 4765 cancel_work_sync(&hw->restart_work);
d27ed387 4766
b877fe28 4767 for (i = hw->ports-1; i >= 0; --i)
6de16237 4768 unregister_netdev(hw->dev[i]);
81906791 4769
d27ed387 4770 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4771
ae306cca
SH		 4772 sky2_power_aux(hw);
4773
793b883e 4774 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4775 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4776
4777 free_irq(pdev->irq, hw);
ea76e635 4778 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4779 pci_disable_msi(pdev);
793b883e 4780 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4781 pci_release_regions(pdev);
4782 pci_disable_device(pdev);
793b883e 4783
b877fe28 4784 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4785 free_netdev(hw->dev[i]);
4786
cd28ab6a
SH		 4787 iounmap(hw->regs);
4788 kfree(hw);
5afa0a9c 4789
cd28ab6a
SH		 4790 pci_set_drvdata(pdev, NULL);
4791}
4792
cd28ab6a
SH		 4793static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4794{
793b883e 4795 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4796 int i, wol = 0;
cd28ab6a 4797
549a68c3
SH		 4798 if (!hw)
4799 return 0;
4800
063a0b38
SH		 4801 del_timer_sync(&hw->watchdog_timer);
4802 cancel_work_sync(&hw->restart_work);
4803
19720737 4804 rtnl_lock();
f05267e7 4805 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4806 struct net_device *dev = hw->dev[i];
e3173832 4807 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4808
af18d8b8 4809 sky2_detach(dev);
e3173832
SH		 4810
4811 if (sky2->wol)
4812 sky2_wol_init(sky2);
4813
4814 wol |= sky2->wol;
cd28ab6a
SH		 4815 }
4816
5f8ae5c5 4817 device_set_wakeup_enable(&pdev->dev, wol != 0);
4818
8ab8fca2 4819 sky2_write32(hw, B0_IMSK, 0);
6de16237 4820 napi_disable(&hw->napi);
ae306cca 4821 sky2_power_aux(hw);
19720737 4822 rtnl_unlock();
e3173832 4823
d374c1c1 4824 pci_save_state(pdev);
e3173832 4825 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4826 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4827
2ccc99b7 4828 return 0;
cd28ab6a
SH		 4829}
4830
5f8ae5c5 4831#ifdef CONFIG_PM
cd28ab6a
SH		 4832static int sky2_resume(struct pci_dev *pdev)
4833{
793b883e 4834 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4835 int i, err;
cd28ab6a 4836
549a68c3
SH		 4837 if (!hw)
4838 return 0;
4839
f71eb1a2
SH		 4840 err = pci_set_power_state(pdev, PCI_D0);
4841 if (err)
4842 goto out;
ae306cca
SH		 4843
4844 err = pci_restore_state(pdev);
4845 if (err)
4846 goto out;
4847
cd28ab6a 4848 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4849
4850 /* Re-enable all clocks */
a0db28b8 4851 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4852 if (err) {
4853 dev_err(&pdev->dev, "PCI write config failed\n");
4854 goto out;
4855 }
1ad5b4a5 4856
e3173832 4857 sky2_reset(hw);
8ab8fca2 4858 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4859 napi_enable(&hw->napi);
8ab8fca2 4860
af18d8b8 4861 rtnl_lock();
f05267e7 4862 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4863 err = sky2_reattach(hw->dev[i]);
4864 if (err)
4865 goto out;
cd28ab6a 4866 }
af18d8b8 4867 rtnl_unlock();
eb35cf60 4868
ae306cca 4869 return 0;
08c06d8a 4870out:
af18d8b8
SH		 4871 rtnl_unlock();
4872
b02a9258 4873 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4874 pci_disable_device(pdev);
08c06d8a 4875 return err;
cd28ab6a
SH		 4876}
4877#endif
4878
e3173832
SH		 4879static void sky2_shutdown(struct pci_dev *pdev)
4880{
5f8ae5c5 4881 sky2_suspend(pdev, PMSG_SUSPEND);
e3173832
SH		 4882}
4883
cd28ab6a 4884static struct pci_driver sky2_driver = {
793b883e
SH		 4885 .name = DRV_NAME,
4886 .id_table = sky2_id_table,
4887 .probe = sky2_probe,
4888 .remove = __devexit_p(sky2_remove),
cd28ab6a 4889#ifdef CONFIG_PM
793b883e
SH		 4890 .suspend = sky2_suspend,
4891 .resume = sky2_resume,
cd28ab6a 4892#endif
e3173832 4893 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4894};
4895
4896static int __init sky2_init_module(void)
4897{
c844d483
SH		 4898 pr_info(PFX "driver version " DRV_VERSION "\n");
4899
3cf26753 4900 sky2_debug_init();
50241c4c 4901 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4902}
4903
4904static void __exit sky2_cleanup_module(void)
4905{
4906 pci_unregister_driver(&sky2_driver);
3cf26753 4907 sky2_debug_cleanup();
cd28ab6a
SH		 4908}
4909
4910module_init(sky2_init_module);
4911module_exit(sky2_cleanup_module);
4912
4913MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4914MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4915MODULE_LICENSE("GPL");
5f4f9dc1 4916MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree