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[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
cd28ab6a 26#include <linux/config.h>
793b883e 27#include <linux/crc32.h>
cd28ab6a
SH		 28#include <linux/kernel.h>
29#include <linux/version.h>
30#include <linux/module.h>
31#include <linux/netdevice.h>
d0bbccfa 32#include <linux/dma-mapping.h>
cd28ab6a
SH		 33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/in.h>
39#include <linux/delay.h>
91c86df5 40#include <linux/workqueue.h>
d1f13708 41#include <linux/if_vlan.h>
d70cd51a 42#include <linux/prefetch.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
c9b84dca 54#define DRV_VERSION "1.4"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
62 */
63
13210ce5 64#define RX_LE_SIZE 512
cd28ab6a 65#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 66#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 67#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 68#define RX_SKB_ALIGN 8
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
bdb5c58e
SH		 93static int copybreak __read_mostly = 256;
94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
01bd7564
SH		 101static int idle_timeout = 100;
102module_param(idle_timeout, int, 0);
103MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
cd28ab6a 105static const struct pci_device_id sky2_id_table[] = {
793b883e 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
2d2a3871 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
cd28ab6a
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 124 { 0 }
125};
793b883e 126
cd28ab6a
SH		 127MODULE_DEVICE_TABLE(pci, sky2_id_table);
128
129/* Avoid conditionals by using array */
130static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
131static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 132static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 133
92f965e8
SH		 134/* This driver supports yukon2 chipset only */
135static const char *yukon2_name[] = {
136 "XL", /* 0xb3 */
137 "EC Ultra", /* 0xb4 */
138 "UNKNOWN", /* 0xb5 */
139 "EC", /* 0xb6 */
140 "FE", /* 0xb7 */
793b883e
SH		 141};
142
793b883e 143/* Access to external PHY */
ef743d33 144static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 145{
146 int i;
147
148 gma_write16(hw, port, GM_SMI_DATA, val);
149 gma_write16(hw, port, GM_SMI_CTRL,
150 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
151
152 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 153 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 154 return 0;
793b883e 155 udelay(1);
cd28ab6a 156 }
ef743d33 157
793b883e 158 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 159 return -ETIMEDOUT;
cd28ab6a
SH		 160}
161
ef743d33 162static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 163{
164 int i;
165
793b883e 166 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 167 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
168
169 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 170 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
171 *val = gma_read16(hw, port, GM_SMI_DATA);
172 return 0;
173 }
174
793b883e 175 udelay(1);
cd28ab6a
SH		 176 }
177
ef743d33
SH		 178 return -ETIMEDOUT;
179}
180
181static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
182{
183 u16 v;
184
185 if (__gm_phy_read(hw, port, reg, &v) != 0)
186 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
187 return v;
cd28ab6a
SH		 188}
189
5afa0a9c
SH		 190static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
191{
192 u16 power_control;
193 u32 reg1;
194 int vaux;
195 int ret = 0;
196
197 pr_debug("sky2_set_power_state %d\n", state);
198 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
199
56a645cc 200 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 201 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c
SH		 202 (power_control & PCI_PM_CAP_PME_D3cold);
203
56a645cc 204 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c
SH		 205
206 power_control |= PCI_PM_CTRL_PME_STATUS;
207 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
208
209 switch (state) {
210 case PCI_D0:
211 /* switch power to VCC (WA for VAUX problem) */
212 sky2_write8(hw, B0_POWER_CTRL,
213 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
214
215 /* disable Core Clock Division, */
216 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
217
218 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
219 /* enable bits are inverted */
220 sky2_write8(hw, B2_Y2_CLK_GATE,
221 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
222 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
223 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
224 else
225 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
226
227 /* Turn off phy power saving */
56a645cc 228 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c
SH		 229 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
230
d571b694 231 /* looks like this XL is back asswards .. */
5afa0a9c
SH		 232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
233 reg1 |= PCI_Y2_PHY1_COMA;
234 if (hw->ports > 1)
235 reg1 |= PCI_Y2_PHY2_COMA;
236 }
977bdf06
SH		 237
238 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
86a31a75 239 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
56a645cc
SH		 240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
241 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 242 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 243 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
244 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 245 }
246
56a645cc 247 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
977bdf06 248
5afa0a9c
SH		 249 break;
250
251 case PCI_D3hot:
252 case PCI_D3cold:
253 /* Turn on phy power saving */
56a645cc 254 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c
SH		 255 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
256 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
257 else
258 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
56a645cc 259 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
5afa0a9c
SH		 260
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (vaux && state != PCI_D3cold)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
275 break;
276 default:
277 printk(KERN_ERR PFX "Unknown power state %d\n", state);
278 ret = -1;
279 }
280
56a645cc 281 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c
SH		 282 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
283 return ret;
284}
285
cd28ab6a
SH		 286static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
287{
288 u16 reg;
289
290 /* disable all GMAC IRQ's */
291 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
292 /* disable PHY IRQs */
293 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 294
cd28ab6a
SH		 295 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
296 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
299
300 reg = gma_read16(hw, port, GM_RX_CTRL);
301 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
302 gma_write16(hw, port, GM_RX_CTRL, reg);
303}
304
305static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
306{
307 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 308 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 309
ed6d32c7 310 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 311 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 312 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
313
314 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 315 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 316 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
317
318 if (hw->chip_id == CHIP_ID_YUKON_EC)
319 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
320 else
321 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
322
323 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
324 }
325
326 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
327 if (hw->copper) {
328 if (hw->chip_id == CHIP_ID_YUKON_FE) {
329 /* enable automatic crossover */
330 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
331 } else {
332 /* disable energy detect */
333 ctrl &= ~PHY_M_PC_EN_DET_MSK;
334
335 /* enable automatic crossover */
336 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
337
338 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 339 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 340 ctrl &= ~PHY_M_PC_DSC_MSK;
341 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
342 }
343 }
344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
345 } else {
346 /* workaround for deviation #4.88 (CRC errors) */
347 /* disable Automatic Crossover */
348
349 ctrl &= ~PHY_M_PC_MDIX_MSK;
350 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
351
352 if (hw->chip_id == CHIP_ID_YUKON_XL) {
353 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
354 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
355 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
356 ctrl &= ~PHY_M_MAC_MD_MSK;
357 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
358 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
359
360 /* select page 1 to access Fiber registers */
361 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
362 }
cd28ab6a
SH		 363 }
364
365 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
366 if (sky2->autoneg == AUTONEG_DISABLE)
367 ctrl &= ~PHY_CT_ANE;
368 else
369 ctrl |= PHY_CT_ANE;
370
371 ctrl |= PHY_CT_RESET;
372 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
373
374 ctrl = 0;
375 ct1000 = 0;
376 adv = PHY_AN_CSMA;
377
378 if (sky2->autoneg == AUTONEG_ENABLE) {
379 if (hw->copper) {
380 if (sky2->advertising & ADVERTISED_1000baseT_Full)
381 ct1000 |= PHY_M_1000C_AFD;
382 if (sky2->advertising & ADVERTISED_1000baseT_Half)
383 ct1000 |= PHY_M_1000C_AHD;
384 if (sky2->advertising & ADVERTISED_100baseT_Full)
385 adv |= PHY_M_AN_100_FD;
386 if (sky2->advertising & ADVERTISED_100baseT_Half)
387 adv |= PHY_M_AN_100_HD;
388 if (sky2->advertising & ADVERTISED_10baseT_Full)
389 adv |= PHY_M_AN_10_FD;
390 if (sky2->advertising & ADVERTISED_10baseT_Half)
391 adv |= PHY_M_AN_10_HD;
793b883e 392 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 393 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
394
395 /* Set Flow-control capabilities */
396 if (sky2->tx_pause && sky2->rx_pause)
793b883e 397 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 398 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 399 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 400 else if (!sky2->rx_pause && sky2->tx_pause)
401 adv |= PHY_AN_PAUSE_ASYM; /* local */
402
403 /* Restart Auto-negotiation */
404 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
405 } else {
406 /* forced speed/duplex settings */
407 ct1000 = PHY_M_1000C_MSE;
408
409 if (sky2->duplex == DUPLEX_FULL)
410 ctrl |= PHY_CT_DUP_MD;
411
412 switch (sky2->speed) {
413 case SPEED_1000:
414 ctrl |= PHY_CT_SP1000;
415 break;
416 case SPEED_100:
417 ctrl |= PHY_CT_SP100;
418 break;
419 }
420
421 ctrl |= PHY_CT_RESET;
422 }
423
424 if (hw->chip_id != CHIP_ID_YUKON_FE)
425 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
426
427 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
428 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
429
430 /* Setup Phy LED's */
431 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
432 ledover = 0;
433
434 switch (hw->chip_id) {
435 case CHIP_ID_YUKON_FE:
436 /* on 88E3082 these bits are at 11..9 (shifted left) */
437 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
438
439 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
440
441 /* delete ACT LED control bits */
442 ctrl &= ~PHY_M_FELP_LED1_MSK;
443 /* change ACT LED control to blink mode */
444 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
445 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
446 break;
447
448 case CHIP_ID_YUKON_XL:
793b883e 449 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 450
451 /* select page 3 to access LED control register */
452 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
453
454 /* set LED Function Control register */
ed6d32c7
SH		 455 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
456 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
457 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
458 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
459 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 460
461 /* set Polarity Control register */
462 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 463 (PHY_M_POLC_LS1_P_MIX(4) |
464 PHY_M_POLC_IS0_P_MIX(4) |
465 PHY_M_POLC_LOS_CTRL(2) |
466 PHY_M_POLC_INIT_CTRL(2) |
467 PHY_M_POLC_STA1_CTRL(2) |
468 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 469
470 /* restore page register */
793b883e 471 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 472 break;
ed6d32c7
SH		 473 case CHIP_ID_YUKON_EC_U:
474 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
475
476 /* select page 3 to access LED control register */
477 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
478
479 /* set LED Function Control register */
480 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
481 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
482 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
483 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
484 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
485
486 /* set Blink Rate in LED Timer Control Register */
487 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
488 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
489 /* restore page register */
490 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
491 break;
cd28ab6a
SH		 492
493 default:
494 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
495 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
496 /* turn off the Rx LED (LED_RX) */
497 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
498 }
499
ed6d32c7 500 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 501 /* apply fixes in PHY AFE */
ed6d32c7
SH		 502 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
503 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
504
977bdf06 505 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 506 gm_phy_write(hw, port, 0x18, 0xaa99);
507 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 508
977bdf06 509 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 510 gm_phy_write(hw, port, 0x18, 0xa204);
511 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 512
513 /* set page register to 0 */
ed6d32c7 514 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 515 } else {
516 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 517
977bdf06
SH		 518 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
519 /* turn on 100 Mbps LED (LED_LINK100) */
520 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
521 }
cd28ab6a 522
977bdf06
SH		 523 if (ledover)
524 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
525
526 }
d571b694 527 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 528 if (sky2->autoneg == AUTONEG_ENABLE)
529 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
530 else
531 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
532}
533
1b537565
SH		 534/* Force a renegotiation */
535static void sky2_phy_reinit(struct sky2_port *sky2)
536{
e07b1aa8 537 spin_lock_bh(&sky2->phy_lock);
1b537565 538 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 539 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 540}
541
cd28ab6a
SH		 542static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
543{
544 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
545 u16 reg;
546 int i;
547 const u8 *addr = hw->dev[port]->dev_addr;
548
42eeea01
SH		 549 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
550 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 551
552 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
553
793b883e 554 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 555 /* WA DEV_472 -- looks like crossed wires on port 2 */
556 /* clear GMAC 1 Control reset */
557 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
558 do {
559 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
560 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
561 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
562 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
563 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
564 }
565
cd28ab6a
SH		 566 if (sky2->autoneg == AUTONEG_DISABLE) {
567 reg = gma_read16(hw, port, GM_GP_CTRL);
568 reg |= GM_GPCR_AU_ALL_DIS;
569 gma_write16(hw, port, GM_GP_CTRL, reg);
570 gma_read16(hw, port, GM_GP_CTRL);
571
cd28ab6a
SH		 572 switch (sky2->speed) {
573 case SPEED_1000:
6f4c56b2 574 reg &= ~GM_GPCR_SPEED_100;
cd28ab6a 575 reg |= GM_GPCR_SPEED_1000;
6f4c56b2 576 break;
cd28ab6a 577 case SPEED_100:
6f4c56b2 578 reg &= ~GM_GPCR_SPEED_1000;
cd28ab6a 579 reg |= GM_GPCR_SPEED_100;
6f4c56b2
SH		 580 break;
581 case SPEED_10:
582 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
583 break;
cd28ab6a
SH		 584 }
585
586 if (sky2->duplex == DUPLEX_FULL)
587 reg |= GM_GPCR_DUP_FULL;
ed6d32c7
SH		 588
589 /* turn off pause in 10/100mbps half duplex */
590 else if (sky2->speed != SPEED_1000 &&
591 hw->chip_id != CHIP_ID_YUKON_EC_U)
592 sky2->tx_pause = sky2->rx_pause = 0;
cd28ab6a
SH		 593 } else
594 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
595
596 if (!sky2->tx_pause && !sky2->rx_pause) {
597 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 598 reg |=
599 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
600 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 601 /* disable Rx flow-control */
602 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
603 }
604
605 gma_write16(hw, port, GM_GP_CTRL, reg);
606
793b883e 607 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 608
e07b1aa8 609 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 610 sky2_phy_init(hw, port);
e07b1aa8 611 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 612
613 /* MIB clear */
614 reg = gma_read16(hw, port, GM_PHY_ADDR);
615 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
616
43f2f104
SH		 617 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
618 gma_read16(hw, port, i);
cd28ab6a
SH		 619 gma_write16(hw, port, GM_PHY_ADDR, reg);
620
621 /* transmit control */
622 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
623
624 /* receive control reg: unicast + multicast + no FCS */
625 gma_write16(hw, port, GM_RX_CTRL,
793b883e 626 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 627
628 /* transmit flow control */
629 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
630
631 /* transmit parameter */
632 gma_write16(hw, port, GM_TX_PARAM,
633 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
634 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
635 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
636 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
637
638 /* serial mode register */
639 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 640 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 641
6b1a3aef 642 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 643 reg |= GM_SMOD_JUMBO_ENA;
644
645 gma_write16(hw, port, GM_SERIAL_MODE, reg);
646
cd28ab6a
SH		 647 /* virtual address for data */
648 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
649
793b883e
SH		 650 /* physical address: used for pause frames */
651 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
652
653 /* ignore counter overflows */
cd28ab6a
SH		 654 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
655 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
656 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
657
658 /* Configure Rx MAC FIFO */
659 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 660 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
661 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 662
d571b694 663 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 664 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 665
793b883e
SH		 666 /* Set threshold to 0xa (64 bytes)
667 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 668 */
669 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
670
671 /* Configure Tx MAC FIFO */
672 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
673 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 674
675 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
676 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
677 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
678 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
679 /* set Tx GMAC FIFO Almost Empty Threshold */
680 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
681 /* Disable Store & Forward mode for TX */
682 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
683 }
684 }
685
cd28ab6a
SH		 686}
687
1c28f6ba
SH		 688/* Assign Ram Buffer allocation.
689 * start and end are in units of 4k bytes
690 * ram registers are in units of 64bit words
691 */
692static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 693{
1c28f6ba 694 u32 start, end;
cd28ab6a 695
1c28f6ba
SH		 696 start = startk * 4096/8;
697 end = (endk * 4096/8) - 1;
793b883e 698
cd28ab6a
SH		 699 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
700 sky2_write32(hw, RB_ADDR(q, RB_START), start);
701 sky2_write32(hw, RB_ADDR(q, RB_END), end);
702 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
703 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
704
705 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 706 u32 space = (endk - startk) * 4096/8;
707 u32 tp = space - space/4;
793b883e 708
1c28f6ba
SH		 709 /* On receive queue's set the thresholds
710 * give receiver priority when > 3/4 full
711 * send pause when down to 2K
712 */
713 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
714 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 715
1c28f6ba
SH		 716 tp = space - 2048/8;
717 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
718 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 719 } else {
720 /* Enable store & forward on Tx queue's because
721 * Tx FIFO is only 1K on Yukon
722 */
723 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
724 }
725
726 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 727 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 728}
729
cd28ab6a 730/* Setup Bus Memory Interface */
af4ed7e6 731static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 732{
733 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
734 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
735 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 736 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 737}
738
cd28ab6a
SH		 739/* Setup prefetch unit registers. This is the interface between
740 * hardware and driver list elements
741 */
8cc048e3 742static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 743 u64 addr, u32 last)
744{
cd28ab6a
SH		 745 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
746 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
747 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
748 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
749 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
750 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 751
752 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 753}
754
793b883e
SH		 755static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
756{
757 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
758
cb5d9547 759 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
793b883e
SH		 760 return le;
761}
cd28ab6a 762
290d4de5
SH		 763/* Update chip's next pointer */
764static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 765{
762c2de2 766 wmb();
290d4de5 767 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
762c2de2 768 mmiowb();
cd28ab6a
SH		 769}
770
793b883e 771
cd28ab6a
SH		 772static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
773{
774 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 775 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
cd28ab6a
SH		 776 return le;
777}
778
a018e330
SH		 779/* Return high part of DMA address (could be 32 or 64 bit) */
780static inline u32 high32(dma_addr_t a)
781{
a036119f 782 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 783}
784
793b883e 785/* Build description to hardware about buffer */
28bd181a 786static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 787{
788 struct sky2_rx_le *le;
734d1868
SH		 789 u32 hi = high32(map);
790 u16 len = sky2->rx_bufsize;
cd28ab6a 791
793b883e 792 if (sky2->rx_addr64 != hi) {
cd28ab6a 793 le = sky2_next_rx(sky2);
793b883e 794 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 795 le->ctrl = 0;
796 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 797 sky2->rx_addr64 = high32(map + len);
cd28ab6a 798 }
793b883e 799
cd28ab6a 800 le = sky2_next_rx(sky2);
734d1868
SH		 801 le->addr = cpu_to_le32((u32) map);
802 le->length = cpu_to_le16(len);
cd28ab6a
SH		 803 le->ctrl = 0;
804 le->opcode = OP_PACKET | HW_OWNER;
805}
806
793b883e 807
cd28ab6a
SH		 808/* Tell chip where to start receive checksum.
809 * Actually has two checksums, but set both same to avoid possible byte
810 * order problems.
811 */
793b883e 812static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 813{
814 struct sky2_rx_le *le;
815
cd28ab6a 816 le = sky2_next_rx(sky2);
793b883e 817 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 818 le->ctrl = 0;
819 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 820
793b883e
SH		 821 sky2_write32(sky2->hw,
822 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
823 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 824
825}
826
6b1a3aef
SH		 827/*
828 * The RX Stop command will not work for Yukon-2 if the BMU does not
829 * reach the end of packet and since we can't make sure that we have
830 * incoming data, we must reset the BMU while it is not doing a DMA
831 * transfer. Since it is possible that the RX path is still active,
832 * the RX RAM buffer will be stopped first, so any possible incoming
833 * data will not trigger a DMA. After the RAM buffer is stopped, the
834 * BMU is polled until any DMA in progress is ended and only then it
835 * will be reset.
836 */
837static void sky2_rx_stop(struct sky2_port *sky2)
838{
839 struct sky2_hw *hw = sky2->hw;
840 unsigned rxq = rxqaddr[sky2->port];
841 int i;
842
843 /* disable the RAM Buffer receive queue */
844 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
845
846 for (i = 0; i < 0xffff; i++)
847 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
848 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
849 goto stopped;
850
851 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
852 sky2->netdev->name);
853stopped:
854 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
855
856 /* reset the Rx prefetch unit */
857 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
858}
793b883e 859
d571b694 860/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 861static void sky2_rx_clean(struct sky2_port *sky2)
862{
863 unsigned i;
864
865 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 866 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 867 struct ring_info *re = sky2->rx_ring + i;
868
869 if (re->skb) {
793b883e 870 pci_unmap_single(sky2->hw->pdev,
734d1868 871 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 872 PCI_DMA_FROMDEVICE);
873 kfree_skb(re->skb);
874 re->skb = NULL;
875 }
876 }
877}
878
ef743d33
SH		 879/* Basic MII support */
880static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
881{
882 struct mii_ioctl_data *data = if_mii(ifr);
883 struct sky2_port *sky2 = netdev_priv(dev);
884 struct sky2_hw *hw = sky2->hw;
885 int err = -EOPNOTSUPP;
886
887 if (!netif_running(dev))
888 return -ENODEV; /* Phy still in reset */
889
d89e1343 890 switch (cmd) {
ef743d33
SH		 891 case SIOCGMIIPHY:
892 data->phy_id = PHY_ADDR_MARV;
893
894 /* fallthru */
895 case SIOCGMIIREG: {
896 u16 val = 0;
91c86df5 897
e07b1aa8 898 spin_lock_bh(&sky2->phy_lock);
ef743d33 899 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 900 spin_unlock_bh(&sky2->phy_lock);
91c86df5 901
ef743d33
SH		 902 data->val_out = val;
903 break;
904 }
905
906 case SIOCSMIIREG:
907 if (!capable(CAP_NET_ADMIN))
908 return -EPERM;
909
e07b1aa8 910 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 911 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
912 data->val_in);
e07b1aa8 913 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 914 break;
915 }
916 return err;
917}
918
d1f13708
SH		 919#ifdef SKY2_VLAN_TAG_USED
920static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
921{
922 struct sky2_port *sky2 = netdev_priv(dev);
923 struct sky2_hw *hw = sky2->hw;
924 u16 port = sky2->port;
d1f13708 925
302d1252 926 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 927
928 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
929 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
930 sky2->vlgrp = grp;
931
302d1252 932 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 933}
934
935static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
936{
937 struct sky2_port *sky2 = netdev_priv(dev);
938 struct sky2_hw *hw = sky2->hw;
939 u16 port = sky2->port;
d1f13708 940
302d1252 941 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 942
943 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
944 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
945 if (sky2->vlgrp)
946 sky2->vlgrp->vlan_devices[vid] = NULL;
947
302d1252 948 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 949}
950#endif
951
82788c7a
SH		 952/*
953 * It appears the hardware has a bug in the FIFO logic that
954 * cause it to hang if the FIFO gets overrun and the receive buffer
955 * is not aligned. ALso alloc_skb() won't align properly if slab
956 * debugging is enabled.
957 */
958static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
959{
960 struct sk_buff *skb;
961
962 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
963 if (likely(skb)) {
964 unsigned long p = (unsigned long) skb->data;
4a15d56f 965 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
82788c7a
SH		 966 }
967
968 return skb;
969}
970
cd28ab6a
SH		 971/*
972 * Allocate and setup receiver buffer pool.
973 * In case of 64 bit dma, there are 2X as many list elements
974 * available as ring entries
975 * and need to reserve one list element so we don't wrap around.
976 */
6b1a3aef 977static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 978{
6b1a3aef 979 struct sky2_hw *hw = sky2->hw;
6b1a3aef
SH		 980 unsigned rxq = rxqaddr[sky2->port];
981 int i;
cd28ab6a 982
6b1a3aef 983 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 984 sky2_qset(hw, rxq);
977bdf06
SH		 985
986 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
987 /* MAC Rx RAM Read is controlled by hardware */
988 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
989 }
990
6b1a3aef
SH		 991 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
992
993 rx_set_checksum(sky2);
793b883e 994 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 995 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 996
82788c7a 997 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
cd28ab6a
SH		 998 if (!re->skb)
999 goto nomem;
1000
6b1a3aef 1001 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 1002 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1003 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 1004 }
1005
70f1be48
SH		 1006 /* Truncate oversize frames */
1007 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
1008 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1009
6b1a3aef
SH		 1010 /* Tell chip about available buffers */
1011 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1012 return 0;
1013nomem:
1014 sky2_rx_clean(sky2);
1015 return -ENOMEM;
1016}
1017
1018/* Bring up network interface. */
1019static int sky2_up(struct net_device *dev)
1020{
1021 struct sky2_port *sky2 = netdev_priv(dev);
1022 struct sky2_hw *hw = sky2->hw;
1023 unsigned port = sky2->port;
e07b1aa8 1024 u32 ramsize, rxspace, imask;
ee7abb04 1025 int cap, err = -ENOMEM;
843a46f4 1026 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1027
ee7abb04
SH		 1028 /*
1029 * On dual port PCI-X card, there is an problem where status
1030 * can be received out of order due to split transactions
843a46f4 1031 */
ee7abb04
SH		 1032 if (otherdev && netif_running(otherdev) &&
1033 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1034 struct sky2_port *osky2 = netdev_priv(otherdev);
1035 u16 cmd;
1036
1037 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1038 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1039 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1040
1041 sky2->rx_csum = 0;
1042 osky2->rx_csum = 0;
1043 }
843a46f4 1044
cd28ab6a
SH		 1045 if (netif_msg_ifup(sky2))
1046 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1047
1048 /* must be power of 2 */
1049 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1050 TX_RING_SIZE *
1051 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1052 &sky2->tx_le_map);
1053 if (!sky2->tx_le)
1054 goto err_out;
1055
6cdbbdf3 1056 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1057 GFP_KERNEL);
1058 if (!sky2->tx_ring)
1059 goto err_out;
1060 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1061
1062 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1063 &sky2->rx_le_map);
1064 if (!sky2->rx_le)
1065 goto err_out;
1066 memset(sky2->rx_le, 0, RX_LE_BYTES);
1067
6cdbbdf3 1068 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 1069 GFP_KERNEL);
1070 if (!sky2->rx_ring)
1071 goto err_out;
1072
1073 sky2_mac_init(hw, port);
1074
1c28f6ba
SH		 1075 /* Determine available ram buffer space (in 4K blocks).
1076 * Note: not sure about the FE setting below yet
1077 */
1078 if (hw->chip_id == CHIP_ID_YUKON_FE)
1079 ramsize = 4;
1080 else
1081 ramsize = sky2_read8(hw, B2_E_0);
1082
1083 /* Give transmitter one third (rounded up) */
1084 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1085
cd28ab6a 1086 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1087 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1088
793b883e
SH		 1089 /* Make sure SyncQ is disabled */
1090 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1091 RB_RST_SET);
1092
af4ed7e6 1093 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1094
977bdf06
SH		 1095 /* Set almost empty threshold */
1096 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1097 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1098
6b1a3aef
SH		 1099 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1100 TX_RING_SIZE - 1);
cd28ab6a 1101
6b1a3aef 1102 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1103 if (err)
1104 goto err_out;
1105
cd28ab6a 1106 /* Enable interrupts from phy/mac for port */
e07b1aa8 1107 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1108 imask |= portirq_msk[port];
e07b1aa8
SH		 1109 sky2_write32(hw, B0_IMSK, imask);
1110
cd28ab6a
SH		 1111 return 0;
1112
1113err_out:
1b537565 1114 if (sky2->rx_le) {
cd28ab6a
SH		 1115 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1116 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1117 sky2->rx_le = NULL;
1118 }
1119 if (sky2->tx_le) {
cd28ab6a
SH		 1120 pci_free_consistent(hw->pdev,
1121 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1122 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1123 sky2->tx_le = NULL;
1124 }
1125 kfree(sky2->tx_ring);
1126 kfree(sky2->rx_ring);
cd28ab6a 1127
1b537565
SH		 1128 sky2->tx_ring = NULL;
1129 sky2->rx_ring = NULL;
cd28ab6a
SH		 1130 return err;
1131}
1132
793b883e
SH		 1133/* Modular subtraction in ring */
1134static inline int tx_dist(unsigned tail, unsigned head)
1135{
cb5d9547 1136 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1137}
cd28ab6a 1138
793b883e
SH		 1139/* Number of list elements available for next tx */
1140static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1141{
793b883e 1142 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1143}
1144
793b883e 1145/* Estimate of number of transmit list elements required */
28bd181a 1146static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1147{
793b883e
SH		 1148 unsigned count;
1149
1150 count = sizeof(dma_addr_t) / sizeof(u32);
1151 count += skb_shinfo(skb)->nr_frags * count;
1152
1153 if (skb_shinfo(skb)->tso_size)
1154 ++count;
1155
0e3ff6aa 1156 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1157 ++count;
1158
1159 return count;
cd28ab6a
SH		 1160}
1161
793b883e
SH		 1162/*
1163 * Put one packet in ring for transmit.
1164 * A single packet can generate multiple list elements, and
1165 * the number of ring elements will probably be less than the number
1166 * of list elements used.
f2e46561
SH		 1167 *
1168 * No BH disabling for tx_lock here (like tg3)
793b883e 1169 */
cd28ab6a
SH		 1170static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1171{
1172 struct sky2_port *sky2 = netdev_priv(dev);
1173 struct sky2_hw *hw = sky2->hw;
d1f13708 1174 struct sky2_tx_le *le = NULL;
6cdbbdf3 1175 struct tx_ring_info *re;
cd28ab6a 1176 unsigned i, len;
b19666d9 1177 int avail;
cd28ab6a
SH		 1178 dma_addr_t mapping;
1179 u32 addr64;
1180 u16 mss;
1181 u8 ctrl;
1182
302d1252
SH		 1183 /* No BH disabling for tx_lock here. We are running in BH disabled
1184 * context and TX reclaim runs via poll inside of a software
1185 * interrupt, and no related locks in IRQ processing.
1186 */
f2e46561 1187 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1188 return NETDEV_TX_LOCKED;
1189
793b883e 1190 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1191 /* There is a known but harmless race with lockless tx
1192 * and netif_stop_queue.
1193 */
1194 if (!netif_queue_stopped(dev)) {
1195 netif_stop_queue(dev);
3be92a70
SH		 1196 if (net_ratelimit())
1197 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1198 dev->name);
8c463ef7 1199 }
f2e46561 1200 spin_unlock(&sky2->tx_lock);
cd28ab6a 1201
cd28ab6a
SH		 1202 return NETDEV_TX_BUSY;
1203 }
1204
793b883e 1205 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1206 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1207 dev->name, sky2->tx_prod, skb->len);
1208
cd28ab6a
SH		 1209 len = skb_headlen(skb);
1210 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1211 addr64 = high32(mapping);
793b883e
SH		 1212
1213 re = sky2->tx_ring + sky2->tx_prod;
1214
a018e330
SH		 1215 /* Send high bits if changed or crosses boundary */
1216 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1217 le = get_tx_le(sky2);
1218 le->tx.addr = cpu_to_le32(addr64);
1219 le->ctrl = 0;
1220 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1221 sky2->tx_addr64 = high32(mapping + len);
793b883e 1222 }
cd28ab6a
SH		 1223
1224 /* Check for TCP Segmentation Offload */
1225 mss = skb_shinfo(skb)->tso_size;
793b883e 1226 if (mss != 0) {
cd28ab6a
SH		 1227 /* just drop the packet if non-linear expansion fails */
1228 if (skb_header_cloned(skb) &&
1229 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
15240072 1230 dev_kfree_skb(skb);
793b883e 1231 goto out_unlock;
cd28ab6a
SH		 1232 }
1233
1234 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1235 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1236 mss += ETH_HLEN;
793b883e 1237 }
cd28ab6a 1238
793b883e 1239 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1240 le = get_tx_le(sky2);
1241 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1242 le->tx.tso.rsvd = 0;
cd28ab6a 1243 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1244 le->ctrl = 0;
793b883e 1245 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1246 }
1247
cd28ab6a 1248 ctrl = 0;
d1f13708
SH		 1249#ifdef SKY2_VLAN_TAG_USED
1250 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1251 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1252 if (!le) {
1253 le = get_tx_le(sky2);
1254 le->tx.addr = 0;
1255 le->opcode = OP_VLAN|HW_OWNER;
1256 le->ctrl = 0;
1257 } else
1258 le->opcode |= OP_VLAN;
1259 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1260 ctrl |= INS_VLAN;
1261 }
1262#endif
1263
1264 /* Handle TCP checksum offload */
cd28ab6a 1265 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1266 u16 hdr = skb->h.raw - skb->data;
1267 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1268
1269 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1270 if (skb->nh.iph->protocol == IPPROTO_UDP)
1271 ctrl |= UDPTCP;
1272
1273 le = get_tx_le(sky2);
1274 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1275 le->tx.csum.offset = cpu_to_le16(offset);
1276 le->length = 0; /* initial checksum value */
cd28ab6a 1277 le->ctrl = 1; /* one packet */
793b883e 1278 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1279 }
1280
1281 le = get_tx_le(sky2);
1282 le->tx.addr = cpu_to_le32((u32) mapping);
1283 le->length = cpu_to_le16(len);
1284 le->ctrl = ctrl;
793b883e 1285 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1286
793b883e 1287 /* Record the transmit mapping info */
cd28ab6a 1288 re->skb = skb;
6cdbbdf3 1289 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1290
1291 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1292 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1293 struct tx_ring_info *fre;
cd28ab6a
SH		 1294
1295 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1296 frag->size, PCI_DMA_TODEVICE);
a036119f 1297 addr64 = high32(mapping);
793b883e
SH		 1298 if (addr64 != sky2->tx_addr64) {
1299 le = get_tx_le(sky2);
1300 le->tx.addr = cpu_to_le32(addr64);
1301 le->ctrl = 0;
1302 le->opcode = OP_ADDR64 | HW_OWNER;
1303 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1304 }
1305
1306 le = get_tx_le(sky2);
1307 le->tx.addr = cpu_to_le32((u32) mapping);
1308 le->length = cpu_to_le16(frag->size);
1309 le->ctrl = ctrl;
793b883e 1310 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1311
793b883e 1312 fre = sky2->tx_ring
cb5d9547 1313 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
6cdbbdf3 1314 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1315 }
6cdbbdf3 1316
793b883e 1317 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1318 le->ctrl |= EOP;
1319
b19666d9
SH		 1320 avail = tx_avail(sky2);
1321 if (mss != 0 || avail < TX_MIN_PENDING) {
1322 le->ctrl |= FRC_STAT;
1323 if (avail <= MAX_SKB_TX_LE)
1324 netif_stop_queue(dev);
1325 }
1326
290d4de5 1327 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1328
793b883e 1329out_unlock:
f2e46561 1330 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1331
1332 dev->trans_start = jiffies;
1333 return NETDEV_TX_OK;
1334}
1335
cd28ab6a 1336/*
793b883e
SH		 1337 * Free ring elements from starting at tx_cons until "done"
1338 *
1339 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1340 * buffers; these are deferred until completion.
cd28ab6a 1341 */
d11c13e7 1342static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1343{
d11c13e7 1344 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1345 struct pci_dev *pdev = sky2->hw->pdev;
1346 u16 nxt, put;
793b883e 1347 unsigned i;
cd28ab6a 1348
0e3ff6aa 1349 BUG_ON(done >= TX_RING_SIZE);
2224795d 1350
d11c13e7 1351 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1352 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1353 dev->name, done);
cd28ab6a 1354
af2a58ac
SH		 1355 for (put = sky2->tx_cons; put != done; put = nxt) {
1356 struct tx_ring_info *re = sky2->tx_ring + put;
1357 struct sk_buff *skb = re->skb;
cd28ab6a 1358
d89e1343 1359 nxt = re->idx;
af2a58ac 1360 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1361 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1362
793b883e 1363 /* Check for partial status */
af2a58ac
SH		 1364 if (tx_dist(put, done) < tx_dist(put, nxt))
1365 break;
793b883e
SH		 1366
1367 skb = re->skb;
af2a58ac 1368 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1369 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1370
1371 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1372 struct tx_ring_info *fre;
cb5d9547 1373 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
af2a58ac 1374 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
d89e1343 1375 skb_shinfo(skb)->frags[i].size,
734d1868 1376 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1377 }
1378
15240072 1379 dev_kfree_skb(skb);
793b883e 1380 }
793b883e 1381
af2a58ac 1382 sky2->tx_cons = put;
8f24664d 1383 if (tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a 1384 netif_wake_queue(dev);
cd28ab6a
SH		 1385}
1386
1387/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1388static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1389{
302d1252 1390 spin_lock_bh(&sky2->tx_lock);
d11c13e7 1391 sky2_tx_complete(sky2, sky2->tx_prod);
302d1252 1392 spin_unlock_bh(&sky2->tx_lock);
cd28ab6a
SH		 1393}
1394
1395/* Network shutdown */
1396static int sky2_down(struct net_device *dev)
1397{
1398 struct sky2_port *sky2 = netdev_priv(dev);
1399 struct sky2_hw *hw = sky2->hw;
1400 unsigned port = sky2->port;
1401 u16 ctrl;
e07b1aa8 1402 u32 imask;
cd28ab6a 1403
1b537565
SH		 1404 /* Never really got started! */
1405 if (!sky2->tx_le)
1406 return 0;
1407
cd28ab6a
SH		 1408 if (netif_msg_ifdown(sky2))
1409 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1410
018d1c66 1411 /* Stop more packets from being queued */
cd28ab6a
SH		 1412 netif_stop_queue(dev);
1413
793b883e
SH		 1414 sky2_phy_reset(hw, port);
1415
cd28ab6a
SH		 1416 /* Stop transmitter */
1417 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1418 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1419
1420 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1421 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1422
1423 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1424 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1425 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1426
1427 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1428
1429 /* Workaround shared GMAC reset */
793b883e
SH		 1430 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1431 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1432 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1433
1434 /* Disable Force Sync bit and Enable Alloc bit */
1435 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1436 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1437
1438 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1439 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1440 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1441
1442 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1443 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1444 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1445
1446 /* Reset the Tx prefetch units */
1447 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1448 PREF_UNIT_RST_SET);
1449
1450 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1451
6b1a3aef 1452 sky2_rx_stop(sky2);
cd28ab6a
SH		 1453
1454 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1455 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1456
e07b1aa8
SH		 1457 /* Disable port IRQ */
1458 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1459 imask &= ~portirq_msk[port];
e07b1aa8
SH		 1460 sky2_write32(hw, B0_IMSK, imask);
1461
d571b694 1462 /* turn off LED's */
cd28ab6a
SH		 1463 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1464
018d1c66
SH		 1465 synchronize_irq(hw->pdev->irq);
1466
cd28ab6a
SH		 1467 sky2_tx_clean(sky2);
1468 sky2_rx_clean(sky2);
1469
1470 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1471 sky2->rx_le, sky2->rx_le_map);
1472 kfree(sky2->rx_ring);
1473
1474 pci_free_consistent(hw->pdev,
1475 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1476 sky2->tx_le, sky2->tx_le_map);
1477 kfree(sky2->tx_ring);
1478
1b537565
SH		 1479 sky2->tx_le = NULL;
1480 sky2->rx_le = NULL;
1481
1482 sky2->rx_ring = NULL;
1483 sky2->tx_ring = NULL;
1484
cd28ab6a
SH		 1485 return 0;
1486}
1487
1488static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1489{
793b883e
SH		 1490 if (!hw->copper)
1491 return SPEED_1000;
1492
cd28ab6a
SH		 1493 if (hw->chip_id == CHIP_ID_YUKON_FE)
1494 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1495
1496 switch (aux & PHY_M_PS_SPEED_MSK) {
1497 case PHY_M_PS_SPEED_1000:
1498 return SPEED_1000;
1499 case PHY_M_PS_SPEED_100:
1500 return SPEED_100;
1501 default:
1502 return SPEED_10;
1503 }
1504}
1505
1506static void sky2_link_up(struct sky2_port *sky2)
1507{
1508 struct sky2_hw *hw = sky2->hw;
1509 unsigned port = sky2->port;
1510 u16 reg;
1511
1512 /* Enable Transmit FIFO Underrun */
793b883e 1513 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1514
1515 reg = gma_read16(hw, port, GM_GP_CTRL);
6f4c56b2
SH		 1516 if (sky2->autoneg == AUTONEG_DISABLE) {
1517 reg |= GM_GPCR_AU_ALL_DIS;
1518
1519 /* Is write/read necessary? Copied from sky2_mac_init */
1520 gma_write16(hw, port, GM_GP_CTRL, reg);
1521 gma_read16(hw, port, GM_GP_CTRL);
1522
1523 switch (sky2->speed) {
1524 case SPEED_1000:
1525 reg &= ~GM_GPCR_SPEED_100;
1526 reg |= GM_GPCR_SPEED_1000;
1527 break;
1528 case SPEED_100:
1529 reg &= ~GM_GPCR_SPEED_1000;
1530 reg |= GM_GPCR_SPEED_100;
1531 break;
1532 case SPEED_10:
1533 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1534 break;
1535 }
1536 } else
1537 reg &= ~GM_GPCR_AU_ALL_DIS;
1538
cd28ab6a
SH		 1539 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1540 reg |= GM_GPCR_DUP_FULL;
1541
cd28ab6a
SH		 1542 /* enable Rx/Tx */
1543 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1544 gma_write16(hw, port, GM_GP_CTRL, reg);
1545 gma_read16(hw, port, GM_GP_CTRL);
1546
1547 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1548
1549 netif_carrier_on(sky2->netdev);
1550 netif_wake_queue(sky2->netdev);
1551
1552 /* Turn on link LED */
793b883e 1553 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1554 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1555
ed6d32c7 1556 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1557 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1558 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1559
1560 switch(sky2->speed) {
1561 case SPEED_10:
1562 led |= PHY_M_LEDC_INIT_CTRL(7);
1563 break;
1564
1565 case SPEED_100:
1566 led |= PHY_M_LEDC_STA1_CTRL(7);
1567 break;
1568
1569 case SPEED_1000:
1570 led |= PHY_M_LEDC_STA0_CTRL(7);
1571 break;
1572 }
793b883e
SH		 1573
1574 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1575 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1576 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1577 }
1578
cd28ab6a
SH		 1579 if (netif_msg_link(sky2))
1580 printk(KERN_INFO PFX
d571b694 1581 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1582 sky2->netdev->name, sky2->speed,
1583 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1584 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1585 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1586}
1587
1588static void sky2_link_down(struct sky2_port *sky2)
1589{
1590 struct sky2_hw *hw = sky2->hw;
1591 unsigned port = sky2->port;
1592 u16 reg;
1593
1594 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1595
1596 reg = gma_read16(hw, port, GM_GP_CTRL);
1597 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1598 gma_write16(hw, port, GM_GP_CTRL, reg);
1599 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1600
1601 if (sky2->rx_pause && !sky2->tx_pause) {
1602 /* restore Asymmetric Pause bit */
1603 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1604 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1605 | PHY_M_AN_ASP);
cd28ab6a
SH		 1606 }
1607
cd28ab6a
SH		 1608 netif_carrier_off(sky2->netdev);
1609 netif_stop_queue(sky2->netdev);
1610
1611 /* Turn on link LED */
1612 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1613
1614 if (netif_msg_link(sky2))
1615 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1616 sky2_phy_init(hw, port);
1617}
1618
793b883e
SH		 1619static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1620{
1621 struct sky2_hw *hw = sky2->hw;
1622 unsigned port = sky2->port;
1623 u16 lpa;
1624
1625 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1626
1627 if (lpa & PHY_M_AN_RF) {
1628 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1629 return -1;
1630 }
1631
1632 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1633 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1634 printk(KERN_ERR PFX "%s: master/slave fault",
1635 sky2->netdev->name);
1636 return -1;
1637 }
1638
1639 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1640 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1641 sky2->netdev->name);
1642 return -1;
1643 }
1644
1645 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1646
1647 sky2->speed = sky2_phy_speed(hw, aux);
1648
1649 /* Pause bits are offset (9..8) */
ed6d32c7 1650 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1651 aux >>= 6;
1652
1653 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1654 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1655
1656 if ((sky2->tx_pause || sky2->rx_pause)
1657 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1658 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1659 else
1660 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1661
1662 return 0;
1663}
cd28ab6a 1664
e07b1aa8
SH		 1665/* Interrupt from PHY */
1666static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1667{
e07b1aa8
SH		 1668 struct net_device *dev = hw->dev[port];
1669 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1670 u16 istatus, phystat;
1671
e07b1aa8
SH		 1672 spin_lock(&sky2->phy_lock);
1673 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1674 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1675
1676 if (!netif_running(dev))
1677 goto out;
cd28ab6a
SH		 1678
1679 if (netif_msg_intr(sky2))
1680 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1681 sky2->netdev->name, istatus, phystat);
1682
1683 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1684 if (sky2_autoneg_done(sky2, phystat) == 0)
1685 sky2_link_up(sky2);
1686 goto out;
1687 }
cd28ab6a 1688
793b883e
SH		 1689 if (istatus & PHY_M_IS_LSP_CHANGE)
1690 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1691
793b883e
SH		 1692 if (istatus & PHY_M_IS_DUP_CHANGE)
1693 sky2->duplex =
1694 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1695
793b883e
SH		 1696 if (istatus & PHY_M_IS_LST_CHANGE) {
1697 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1698 sky2_link_up(sky2);
793b883e
SH		 1699 else
1700 sky2_link_down(sky2);
cd28ab6a 1701 }
793b883e 1702out:
e07b1aa8 1703 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1704}
1705
302d1252
SH		 1706
1707/* Transmit timeout is only called if we are running, carries is up
1708 * and tx queue is full (stopped).
1709 */
cd28ab6a
SH		 1710static void sky2_tx_timeout(struct net_device *dev)
1711{
1712 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1713 struct sky2_hw *hw = sky2->hw;
1714 unsigned txq = txqaddr[sky2->port];
8f24664d 1715 u16 report, done;
cd28ab6a
SH		 1716
1717 if (netif_msg_timer(sky2))
1718 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1719
8f24664d
SH		 1720 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1721 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1722
8f24664d
SH		 1723 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1724 dev->name,
1725 sky2->tx_cons, sky2->tx_prod, report, done);
1726
1727 if (report != done) {
1728 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1729
1730 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1731 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1732 } else if (report != sky2->tx_cons) {
1733 printk(KERN_INFO PFX "status report lost?\n");
1734
1735 spin_lock_bh(&sky2->tx_lock);
1736 sky2_tx_complete(sky2, report);
1737 spin_unlock_bh(&sky2->tx_lock);
1738 } else {
1739 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1740
8f24664d
SH		 1741 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1742 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1743
1744 sky2_tx_clean(sky2);
1745
1746 sky2_qset(hw, txq);
1747 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1748 }
cd28ab6a
SH		 1749}
1750
734d1868 1751
70f1be48
SH		 1752/* Want receive buffer size to be multiple of 64 bits
1753 * and incl room for vlan and truncation
1754 */
734d1868
SH		 1755static inline unsigned sky2_buf_size(int mtu)
1756{
4a15d56f 1757 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
734d1868
SH		 1758}
1759
cd28ab6a
SH		 1760static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1761{
6b1a3aef
SH		 1762 struct sky2_port *sky2 = netdev_priv(dev);
1763 struct sky2_hw *hw = sky2->hw;
1764 int err;
1765 u16 ctl, mode;
e07b1aa8 1766 u32 imask;
cd28ab6a
SH		 1767
1768 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1769 return -EINVAL;
1770
5a5b1ea0
SH		 1771 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1772 return -EINVAL;
1773
6b1a3aef
SH		 1774 if (!netif_running(dev)) {
1775 dev->mtu = new_mtu;
1776 return 0;
1777 }
1778
e07b1aa8 1779 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1780 sky2_write32(hw, B0_IMSK, 0);
1781
018d1c66
SH		 1782 dev->trans_start = jiffies; /* prevent tx timeout */
1783 netif_stop_queue(dev);
1784 netif_poll_disable(hw->dev[0]);
1785
e07b1aa8
SH		 1786 synchronize_irq(hw->pdev->irq);
1787
6b1a3aef
SH		 1788 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1789 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1790 sky2_rx_stop(sky2);
1791 sky2_rx_clean(sky2);
cd28ab6a
SH		 1792
1793 dev->mtu = new_mtu;
734d1868 1794 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef
SH		 1795 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1796 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1797
1798 if (dev->mtu > ETH_DATA_LEN)
1799 mode |= GM_SMOD_JUMBO_ENA;
1800
1801 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1802
6b1a3aef 1803 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1804
6b1a3aef 1805 err = sky2_rx_start(sky2);
e07b1aa8 1806 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1807
1b537565
SH		 1808 if (err)
1809 dev_close(dev);
1810 else {
1811 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1812
1813 netif_poll_enable(hw->dev[0]);
1814 netif_wake_queue(dev);
1815 }
1816
cd28ab6a
SH		 1817 return err;
1818}
1819
1820/*
1821 * Receive one packet.
1822 * For small packets or errors, just reuse existing skb.
d571b694 1823 * For larger packets, get new buffer.
cd28ab6a 1824 */
d11c13e7 1825static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1826 u16 length, u32 status)
1827{
cd28ab6a 1828 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1829 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1830
1831 if (unlikely(netif_msg_rx_status(sky2)))
1832 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1833 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1834
793b883e 1835 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1836 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1837
42eeea01 1838 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1839 goto error;
1840
42eeea01
SH		 1841 if (!(status & GMR_FS_RX_OK))
1842 goto resubmit;
1843
70f1be48 1844 if (length > sky2->netdev->mtu + ETH_HLEN)
6e15b712
SH		 1845 goto oversize;
1846
bdb5c58e 1847 if (length < copybreak) {
79e57d32
SH		 1848 skb = alloc_skb(length + 2, GFP_ATOMIC);
1849 if (!skb)
793b883e
SH		 1850 goto resubmit;
1851
79e57d32 1852 skb_reserve(skb, 2);
793b883e
SH		 1853 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1854 length, PCI_DMA_FROMDEVICE);
79e57d32 1855 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1856 skb->ip_summed = re->skb->ip_summed;
1857 skb->csum = re->skb->csum;
793b883e
SH		 1858 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1859 length, PCI_DMA_FROMDEVICE);
793b883e 1860 } else {
79e57d32
SH		 1861 struct sk_buff *nskb;
1862
82788c7a 1863 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1864 if (!nskb)
1865 goto resubmit;
cd28ab6a 1866
793b883e 1867 skb = re->skb;
79e57d32 1868 re->skb = nskb;
793b883e 1869 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1870 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1871 prefetch(skb->data);
cd28ab6a 1872
793b883e 1873 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1874 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1875 }
cd28ab6a 1876
79e57d32 1877 skb_put(skb, length);
793b883e 1878resubmit:
d11c13e7 1879 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1880 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1881
bea86103 1882 /* Tell receiver about new buffers. */
290d4de5 1883 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
bea86103 1884
cd28ab6a
SH		 1885 return skb;
1886
6e15b712
SH		 1887oversize:
1888 ++sky2->net_stats.rx_over_errors;
1889 goto resubmit;
1890
cd28ab6a 1891error:
6e15b712
SH		 1892 ++sky2->net_stats.rx_errors;
1893
3be92a70 1894 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a
SH		 1895 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1896 sky2->netdev->name, status, length);
793b883e
SH		 1897
1898 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1899 sky2->net_stats.rx_length_errors++;
1900 if (status & GMR_FS_FRAGMENT)
1901 sky2->net_stats.rx_frame_errors++;
1902 if (status & GMR_FS_CRC_ERR)
1903 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1904 if (status & GMR_FS_RX_FF_OV)
1905 sky2->net_stats.rx_fifo_errors++;
79e57d32 1906
793b883e 1907 goto resubmit;
cd28ab6a
SH		 1908}
1909
e07b1aa8
SH		 1910/* Transmit complete */
1911static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 1912{
e07b1aa8 1913 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 1914
e07b1aa8
SH		 1915 if (netif_running(dev)) {
1916 spin_lock(&sky2->tx_lock);
1917 sky2_tx_complete(sky2, last);
1918 spin_unlock(&sky2->tx_lock);
2224795d 1919 }
cd28ab6a
SH		 1920}
1921
86fba634
SH		 1922/* Is status ring empty or is there more to do? */
1923static inline int sky2_more_work(const struct sky2_hw *hw)
1924{
1925 return (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX));
1926}
1927
e07b1aa8
SH		 1928/* Process status response ring */
1929static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 1930{
e07b1aa8 1931 int work_done = 0;
e71ebd73 1932 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 1933
af2a58ac 1934 rmb();
bea86103 1935
e71ebd73 1936 while (hw->st_idx != hwidx) {
13210ce5
SH		 1937 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1938 struct net_device *dev;
d11c13e7 1939 struct sky2_port *sky2;
cd28ab6a 1940 struct sk_buff *skb;
cd28ab6a
SH		 1941 u32 status;
1942 u16 length;
1943
cb5d9547 1944 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 1945
e71ebd73
SH		 1946 BUG_ON(le->link >= 2);
1947 dev = hw->dev[le->link];
13210ce5
SH		 1948
1949 sky2 = netdev_priv(dev);
e07b1aa8
SH		 1950 length = le->length;
1951 status = le->status;
cd28ab6a 1952
e71ebd73 1953 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1954 case OP_RXSTAT:
d11c13e7 1955 skb = sky2_receive(sky2, length, status);
d1f13708
SH		 1956 if (!skb)
1957 break;
13210ce5
SH		 1958
1959 skb->dev = dev;
1960 skb->protocol = eth_type_trans(skb, dev);
1961 dev->last_rx = jiffies;
1962
d1f13708
SH		 1963#ifdef SKY2_VLAN_TAG_USED
1964 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1965 vlan_hwaccel_receive_skb(skb,
1966 sky2->vlgrp,
1967 be16_to_cpu(sky2->rx_tag));
1968 } else
1969#endif
cd28ab6a 1970 netif_receive_skb(skb);
13210ce5
SH		 1971
1972 if (++work_done >= to_do)
1973 goto exit_loop;
cd28ab6a
SH		 1974 break;
1975
d1f13708
SH		 1976#ifdef SKY2_VLAN_TAG_USED
1977 case OP_RXVLAN:
1978 sky2->rx_tag = length;
1979 break;
1980
1981 case OP_RXCHKSVLAN:
1982 sky2->rx_tag = length;
1983 /* fall through */
1984#endif
cd28ab6a 1985 case OP_RXCHKS:
d11c13e7
SH		 1986 skb = sky2->rx_ring[sky2->rx_next].skb;
1987 skb->ip_summed = CHECKSUM_HW;
1988 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1989 break;
1990
1991 case OP_TXINDEXLE:
13b97b74 1992 /* TX index reports status for both ports */
f55925d7
SH		 1993 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
1994 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 1995 if (hw->dev[1])
1996 sky2_tx_done(hw->dev[1],
1997 ((status >> 24) & 0xff)
1998 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 1999 break;
2000
cd28ab6a
SH		 2001 default:
2002 if (net_ratelimit())
793b883e 2003 printk(KERN_WARNING PFX
e71ebd73
SH		 2004 "unknown status opcode 0x%x\n", le->opcode);
2005 goto exit_loop;
cd28ab6a 2006 }
13210ce5 2007 }
cd28ab6a 2008
13210ce5 2009exit_loop:
e07b1aa8 2010 return work_done;
cd28ab6a
SH		 2011}
2012
2013static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2014{
2015 struct net_device *dev = hw->dev[port];
2016
3be92a70
SH		 2017 if (net_ratelimit())
2018 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2019 dev->name, status);
cd28ab6a
SH		 2020
2021 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2022 if (net_ratelimit())
2023 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2024 dev->name);
cd28ab6a
SH		 2025 /* Clear IRQ */
2026 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2027 }
2028
2029 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2030 if (net_ratelimit())
2031 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2032 dev->name);
cd28ab6a
SH		 2033
2034 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2035 }
2036
2037 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2038 if (net_ratelimit())
2039 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2040 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2041 }
2042
2043 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2044 if (net_ratelimit())
2045 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2046 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2047 }
2048
2049 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2050 if (net_ratelimit())
2051 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2052 dev->name);
cd28ab6a
SH		 2053 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2054 }
2055}
2056
2057static void sky2_hw_intr(struct sky2_hw *hw)
2058{
2059 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2060
793b883e 2061 if (status & Y2_IS_TIST_OV)
cd28ab6a 2062 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2063
2064 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2065 u16 pci_err;
2066
56a645cc 2067 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2068 if (net_ratelimit())
2069 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2070 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2071
2072 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2073 sky2_pci_write16(hw, PCI_STATUS,
793b883e 2074 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2075 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2076 }
2077
2078 if (status & Y2_IS_PCI_EXP) {
d571b694 2079 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2080 u32 pex_err;
2081
56a645cc 2082 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2083
3be92a70
SH		 2084 if (net_ratelimit())
2085 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2086 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2087
2088 /* clear the interrupt */
2089 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2090 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
793b883e 2091 0xffffffffUL);
cd28ab6a
SH		 2092 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2093
2094 if (pex_err & PEX_FATAL_ERRORS) {
2095 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2096 hwmsk &= ~Y2_IS_PCI_EXP;
2097 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2098 }
2099 }
2100
2101 if (status & Y2_HWE_L1_MASK)
2102 sky2_hw_error(hw, 0, status);
2103 status >>= 8;
2104 if (status & Y2_HWE_L1_MASK)
2105 sky2_hw_error(hw, 1, status);
2106}
2107
2108static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2109{
2110 struct net_device *dev = hw->dev[port];
2111 struct sky2_port *sky2 = netdev_priv(dev);
2112 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2113
2114 if (netif_msg_intr(sky2))
2115 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2116 dev->name, status);
2117
2118 if (status & GM_IS_RX_FF_OR) {
2119 ++sky2->net_stats.rx_fifo_errors;
2120 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2121 }
2122
2123 if (status & GM_IS_TX_FF_UR) {
2124 ++sky2->net_stats.tx_fifo_errors;
2125 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2126 }
cd28ab6a
SH		 2127}
2128
d257924e
SH		 2129/* This should never happen it is a fatal situation */
2130static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2131 const char *rxtx, u32 mask)
2132{
2133 struct net_device *dev = hw->dev[port];
2134 struct sky2_port *sky2 = netdev_priv(dev);
2135 u32 imask;
2136
2137 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2138 dev ? dev->name : "<not registered>", rxtx);
2139
2140 imask = sky2_read32(hw, B0_IMSK);
2141 imask &= ~mask;
2142 sky2_write32(hw, B0_IMSK, imask);
2143
2144 if (dev) {
2145 spin_lock(&sky2->phy_lock);
2146 sky2_link_down(sky2);
2147 spin_unlock(&sky2->phy_lock);
2148 }
2149}
cd28ab6a 2150
d27ed387
SH		 2151/* If idle then force a fake soft NAPI poll once a second
2152 * to work around cases where sharing an edge triggered interrupt.
2153 */
2154static void sky2_idle(unsigned long arg)
2155{
01bd7564
SH		 2156 struct sky2_hw *hw = (struct sky2_hw *) arg;
2157 struct net_device *dev = hw->dev[0];
d27ed387 2158
d27ed387
SH		 2159 if (__netif_rx_schedule_prep(dev))
2160 __netif_rx_schedule(dev);
01bd7564
SH		 2161
2162 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2163}
2164
2165
e07b1aa8 2166static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2167{
e07b1aa8
SH		 2168 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2169 int work_limit = min(dev0->quota, *budget);
2170 int work_done = 0;
fb2690a9 2171 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2172
1e5f1283
SH		 2173 if (status & Y2_IS_HW_ERR)
2174 sky2_hw_intr(hw);
d257924e 2175
1e5f1283
SH		 2176 if (status & Y2_IS_IRQ_PHY1)
2177 sky2_phy_intr(hw, 0);
cd28ab6a 2178
1e5f1283
SH		 2179 if (status & Y2_IS_IRQ_PHY2)
2180 sky2_phy_intr(hw, 1);
cd28ab6a 2181
1e5f1283
SH		 2182 if (status & Y2_IS_IRQ_MAC1)
2183 sky2_mac_intr(hw, 0);
cd28ab6a 2184
1e5f1283
SH		 2185 if (status & Y2_IS_IRQ_MAC2)
2186 sky2_mac_intr(hw, 1);
cd28ab6a 2187
1e5f1283
SH		 2188 if (status & Y2_IS_CHK_RX1)
2189 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2190
1e5f1283
SH		 2191 if (status & Y2_IS_CHK_RX2)
2192 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2193
1e5f1283
SH		 2194 if (status & Y2_IS_CHK_TXA1)
2195 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2196
1e5f1283
SH		 2197 if (status & Y2_IS_CHK_TXA2)
2198 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2199
1e5f1283
SH		 2200 work_done = sky2_status_intr(hw, work_limit);
2201 *budget -= work_done;
2202 dev0->quota -= work_done;
e07b1aa8 2203
86fba634
SH		 2204 if (status & Y2_IS_STAT_BMU)
2205 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2206
2207 if (sky2_more_work(hw))
1e5f1283 2208 return 1;
e07b1aa8 2209
d3240312 2210 netif_rx_complete(dev0);
e07b1aa8 2211
86fba634 2212 sky2_read32(hw, B0_Y2_SP_LISR);
e07b1aa8
SH		 2213 return 0;
2214}
2215
2216static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2217{
2218 struct sky2_hw *hw = dev_id;
2219 struct net_device *dev0 = hw->dev[0];
2220 u32 status;
2221
2222 /* Reading this mask interrupts as side effect */
2223 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2224 if (status == 0 || status == ~0)
2225 return IRQ_NONE;
793b883e 2226
e07b1aa8
SH		 2227 prefetch(&hw->st_le[hw->st_idx]);
2228 if (likely(__netif_rx_schedule_prep(dev0)))
2229 __netif_rx_schedule(dev0);
793b883e 2230
cd28ab6a
SH		 2231 return IRQ_HANDLED;
2232}
2233
2234#ifdef CONFIG_NET_POLL_CONTROLLER
2235static void sky2_netpoll(struct net_device *dev)
2236{
2237 struct sky2_port *sky2 = netdev_priv(dev);
2238
793b883e 2239 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 2240}
2241#endif
2242
2243/* Chip internal frequency for clock calculations */
fb17358f 2244static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2245{
793b883e 2246 switch (hw->chip_id) {
cd28ab6a 2247 case CHIP_ID_YUKON_EC:
5a5b1ea0 2248 case CHIP_ID_YUKON_EC_U:
fb17358f 2249 return 125; /* 125 Mhz */
cd28ab6a 2250 case CHIP_ID_YUKON_FE:
fb17358f 2251 return 100; /* 100 Mhz */
793b883e 2252 default: /* YUKON_XL */
fb17358f 2253 return 156; /* 156 Mhz */
cd28ab6a
SH		 2254 }
2255}
2256
fb17358f 2257static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2258{
fb17358f 2259 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2260}
2261
fb17358f 2262static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2263{
fb17358f 2264 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2265}
2266
fb17358f 2267
98712e5e 2268static int __devinit sky2_reset(struct sky2_hw *hw)
cd28ab6a 2269{
cd28ab6a
SH		 2270 u16 status;
2271 u8 t8, pmd_type;
56a645cc 2272 int i;
cd28ab6a 2273
cd28ab6a 2274 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2275
cd28ab6a
SH		 2276 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2277 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2278 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2279 pci_name(hw->pdev), hw->chip_id);
2280 return -EOPNOTSUPP;
2281 }
2282
290d4de5
SH		 2283 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2284
2285 /* This rev is really old, and requires untested workarounds */
2286 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2287 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2288 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2289 hw->chip_id, hw->chip_rev);
2290 return -EOPNOTSUPP;
2291 }
2292
cd28ab6a
SH		 2293 /* disable ASF */
2294 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2295 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2296 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2297 }
2298
2299 /* do a SW reset */
2300 sky2_write8(hw, B0_CTST, CS_RST_SET);
2301 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2302
2303 /* clear PCI errors, if any */
56a645cc 2304 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2305
cd28ab6a 2306 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2307 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2308
cd28ab6a
SH		 2309
2310 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2311
2312 /* clear any PEX errors */
d89e1343 2313 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
56a645cc
SH		 2314 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2315
cd28ab6a
SH		 2316
2317 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2318 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2319
2320 hw->ports = 1;
2321 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2322 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2323 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2324 ++hw->ports;
2325 }
cd28ab6a 2326
5afa0a9c 2327 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2328
2329 for (i = 0; i < hw->ports; i++) {
2330 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2331 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2332 }
2333
2334 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2335
793b883e
SH		 2336 /* Clear I2C IRQ noise */
2337 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2338
2339 /* turn off hardware timer (unused) */
2340 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2341 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2342
cd28ab6a
SH		 2343 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2344
69634ee7
SH		 2345 /* Turn off descriptor polling */
2346 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2347
2348 /* Turn off receive timestamp */
2349 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2350 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2351
2352 /* enable the Tx Arbiters */
2353 for (i = 0; i < hw->ports; i++)
2354 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2355
2356 /* Initialize ram interface */
2357 for (i = 0; i < hw->ports; i++) {
793b883e 2358 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2359
2360 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2361 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2362 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2363 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2364 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2365 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2366 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2367 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2368 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2369 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2370 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2371 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2372 }
2373
cd28ab6a
SH		 2374 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2375
cd28ab6a
SH		 2376 for (i = 0; i < hw->ports; i++)
2377 sky2_phy_reset(hw, i);
cd28ab6a 2378
cd28ab6a
SH		 2379 memset(hw->st_le, 0, STATUS_LE_BYTES);
2380 hw->st_idx = 0;
2381
2382 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2383 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2384
2385 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2386 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2387
2388 /* Set the list last index */
793b883e 2389 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2390
290d4de5
SH		 2391 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2392 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2393
290d4de5
SH		 2394 /* set Status-FIFO ISR watermark */
2395 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2396 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2397 else
2398 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2399
290d4de5 2400 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2401 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2402 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2403
793b883e 2404 /* enable status unit */
cd28ab6a
SH		 2405 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2406
2407 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2408 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2409 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2410
2411 return 0;
2412}
2413
28bd181a 2414static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a
SH		 2415{
2416 u32 modes;
2417 if (hw->copper) {
793b883e
SH		 2418 modes = SUPPORTED_10baseT_Half
2419 | SUPPORTED_10baseT_Full
2420 | SUPPORTED_100baseT_Half
2421 | SUPPORTED_100baseT_Full
2422 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2423
2424 if (hw->chip_id != CHIP_ID_YUKON_FE)
2425 modes |= SUPPORTED_1000baseT_Half
793b883e 2426 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2427 } else
2428 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2429 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2430 return modes;
2431}
2432
793b883e 2433static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2434{
2435 struct sky2_port *sky2 = netdev_priv(dev);
2436 struct sky2_hw *hw = sky2->hw;
2437
2438 ecmd->transceiver = XCVR_INTERNAL;
2439 ecmd->supported = sky2_supported_modes(hw);
2440 ecmd->phy_address = PHY_ADDR_MARV;
2441 if (hw->copper) {
2442 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2443 | SUPPORTED_10baseT_Full
2444 | SUPPORTED_100baseT_Half
2445 | SUPPORTED_100baseT_Full
2446 | SUPPORTED_1000baseT_Half
2447 | SUPPORTED_1000baseT_Full
2448 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2449 ecmd->port = PORT_TP;
2450 } else
2451 ecmd->port = PORT_FIBRE;
2452
2453 ecmd->advertising = sky2->advertising;
2454 ecmd->autoneg = sky2->autoneg;
2455 ecmd->speed = sky2->speed;
2456 ecmd->duplex = sky2->duplex;
2457 return 0;
2458}
2459
2460static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2461{
2462 struct sky2_port *sky2 = netdev_priv(dev);
2463 const struct sky2_hw *hw = sky2->hw;
2464 u32 supported = sky2_supported_modes(hw);
2465
2466 if (ecmd->autoneg == AUTONEG_ENABLE) {
2467 ecmd->advertising = supported;
2468 sky2->duplex = -1;
2469 sky2->speed = -1;
2470 } else {
2471 u32 setting;
2472
793b883e 2473 switch (ecmd->speed) {
cd28ab6a
SH		 2474 case SPEED_1000:
2475 if (ecmd->duplex == DUPLEX_FULL)
2476 setting = SUPPORTED_1000baseT_Full;
2477 else if (ecmd->duplex == DUPLEX_HALF)
2478 setting = SUPPORTED_1000baseT_Half;
2479 else
2480 return -EINVAL;
2481 break;
2482 case SPEED_100:
2483 if (ecmd->duplex == DUPLEX_FULL)
2484 setting = SUPPORTED_100baseT_Full;
2485 else if (ecmd->duplex == DUPLEX_HALF)
2486 setting = SUPPORTED_100baseT_Half;
2487 else
2488 return -EINVAL;
2489 break;
2490
2491 case SPEED_10:
2492 if (ecmd->duplex == DUPLEX_FULL)
2493 setting = SUPPORTED_10baseT_Full;
2494 else if (ecmd->duplex == DUPLEX_HALF)
2495 setting = SUPPORTED_10baseT_Half;
2496 else
2497 return -EINVAL;
2498 break;
2499 default:
2500 return -EINVAL;
2501 }
2502
2503 if ((setting & supported) == 0)
2504 return -EINVAL;
2505
2506 sky2->speed = ecmd->speed;
2507 sky2->duplex = ecmd->duplex;
2508 }
2509
2510 sky2->autoneg = ecmd->autoneg;
2511 sky2->advertising = ecmd->advertising;
2512
1b537565
SH		 2513 if (netif_running(dev))
2514 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2515
2516 return 0;
2517}
2518
2519static void sky2_get_drvinfo(struct net_device *dev,
2520 struct ethtool_drvinfo *info)
2521{
2522 struct sky2_port *sky2 = netdev_priv(dev);
2523
2524 strcpy(info->driver, DRV_NAME);
2525 strcpy(info->version, DRV_VERSION);
2526 strcpy(info->fw_version, "N/A");
2527 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2528}
2529
2530static const struct sky2_stat {
793b883e
SH		 2531 char name[ETH_GSTRING_LEN];
2532 u16 offset;
cd28ab6a
SH		 2533} sky2_stats[] = {
2534 { "tx_bytes", GM_TXO_OK_HI },
2535 { "rx_bytes", GM_RXO_OK_HI },
2536 { "tx_broadcast", GM_TXF_BC_OK },
2537 { "rx_broadcast", GM_RXF_BC_OK },
2538 { "tx_multicast", GM_TXF_MC_OK },
2539 { "rx_multicast", GM_RXF_MC_OK },
2540 { "tx_unicast", GM_TXF_UC_OK },
2541 { "rx_unicast", GM_RXF_UC_OK },
2542 { "tx_mac_pause", GM_TXF_MPAUSE },
2543 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2544 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2545 { "late_collision",GM_TXF_LAT_COL },
2546 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2547 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2548 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2549
d2604540 2550 { "rx_short", GM_RXF_SHT },
cd28ab6a 2551 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2552 { "rx_64_byte_packets", GM_RXF_64B },
2553 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2554 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2555 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2556 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2557 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2558 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2559 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2560 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2561 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2562 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2563
2564 { "tx_64_byte_packets", GM_TXF_64B },
2565 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2566 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2567 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2568 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2569 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2570 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2571 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2572};
2573
cd28ab6a
SH		 2574static u32 sky2_get_rx_csum(struct net_device *dev)
2575{
2576 struct sky2_port *sky2 = netdev_priv(dev);
2577
2578 return sky2->rx_csum;
2579}
2580
2581static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2582{
2583 struct sky2_port *sky2 = netdev_priv(dev);
2584
2585 sky2->rx_csum = data;
793b883e 2586
cd28ab6a
SH		 2587 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2588 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2589
2590 return 0;
2591}
2592
2593static u32 sky2_get_msglevel(struct net_device *netdev)
2594{
2595 struct sky2_port *sky2 = netdev_priv(netdev);
2596 return sky2->msg_enable;
2597}
2598
9a7ae0a9
SH		 2599static int sky2_nway_reset(struct net_device *dev)
2600{
2601 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2602
2603 if (sky2->autoneg != AUTONEG_ENABLE)
2604 return -EINVAL;
2605
1b537565 2606 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2607
2608 return 0;
2609}
2610
793b883e 2611static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2612{
2613 struct sky2_hw *hw = sky2->hw;
2614 unsigned port = sky2->port;
2615 int i;
2616
2617 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2618 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2619 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2620 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2621
793b883e 2622 for (i = 2; i < count; i++)
cd28ab6a
SH		 2623 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2624}
2625
cd28ab6a
SH		 2626static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2627{
2628 struct sky2_port *sky2 = netdev_priv(netdev);
2629 sky2->msg_enable = value;
2630}
2631
2632static int sky2_get_stats_count(struct net_device *dev)
2633{
2634 return ARRAY_SIZE(sky2_stats);
2635}
2636
2637static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2638 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2639{
2640 struct sky2_port *sky2 = netdev_priv(dev);
2641
793b883e 2642 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2643}
2644
793b883e 2645static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2646{
2647 int i;
2648
2649 switch (stringset) {
2650 case ETH_SS_STATS:
2651 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2652 memcpy(data + i * ETH_GSTRING_LEN,
2653 sky2_stats[i].name, ETH_GSTRING_LEN);
2654 break;
2655 }
2656}
2657
2658/* Use hardware MIB variables for critical path statistics and
2659 * transmit feedback not reported at interrupt.
2660 * Other errors are accounted for in interrupt handler.
2661 */
2662static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2663{
2664 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2665 u64 data[13];
cd28ab6a 2666
793b883e 2667 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2668
2669 sky2->net_stats.tx_bytes = data[0];
2670 sky2->net_stats.rx_bytes = data[1];
2671 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2672 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2673 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2674 sky2->net_stats.collisions = data[10];
2675 sky2->net_stats.tx_aborted_errors = data[12];
2676
2677 return &sky2->net_stats;
2678}
2679
2680static int sky2_set_mac_address(struct net_device *dev, void *p)
2681{
2682 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2683 struct sky2_hw *hw = sky2->hw;
2684 unsigned port = sky2->port;
2685 const struct sockaddr *addr = p;
cd28ab6a
SH		 2686
2687 if (!is_valid_ether_addr(addr->sa_data))
2688 return -EADDRNOTAVAIL;
2689
cd28ab6a 2690 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2691 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2692 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2693 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2694 dev->dev_addr, ETH_ALEN);
1b537565 2695
a8ab1ec0
SH		 2696 /* virtual address for data */
2697 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2698
2699 /* physical address: used for pause frames */
2700 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2701
2702 return 0;
cd28ab6a
SH		 2703}
2704
2705static void sky2_set_multicast(struct net_device *dev)
2706{
2707 struct sky2_port *sky2 = netdev_priv(dev);
2708 struct sky2_hw *hw = sky2->hw;
2709 unsigned port = sky2->port;
2710 struct dev_mc_list *list = dev->mc_list;
2711 u16 reg;
2712 u8 filter[8];
2713
2714 memset(filter, 0, sizeof(filter));
2715
2716 reg = gma_read16(hw, port, GM_RX_CTRL);
2717 reg |= GM_RXCR_UCF_ENA;
2718
d571b694 2719 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2720 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2721 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2722 memset(filter, 0xff, sizeof(filter));
793b883e 2723 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2724 reg &= ~GM_RXCR_MCF_ENA;
2725 else {
2726 int i;
2727 reg |= GM_RXCR_MCF_ENA;
2728
2729 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2730 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2731 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2732 }
2733 }
2734
cd28ab6a 2735 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2736 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2737 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2738 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2739 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2740 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2741 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2742 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2743
2744 gma_write16(hw, port, GM_RX_CTRL, reg);
2745}
2746
2747/* Can have one global because blinking is controlled by
2748 * ethtool and that is always under RTNL mutex
2749 */
91c86df5 2750static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2751{
793b883e
SH		 2752 u16 pg;
2753
793b883e
SH		 2754 switch (hw->chip_id) {
2755 case CHIP_ID_YUKON_XL:
2756 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2757 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2758 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2759 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2760 PHY_M_LEDC_INIT_CTRL(7) |
2761 PHY_M_LEDC_STA1_CTRL(7) |
2762 PHY_M_LEDC_STA0_CTRL(7))
2763 : 0);
2764
2765 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2766 break;
2767
2768 default:
2769 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2770 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2771 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2772 PHY_M_LED_MO_10(MO_LED_ON) |
2773 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2774 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2775 PHY_M_LED_MO_RX(MO_LED_ON)
2776 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2777 PHY_M_LED_MO_10(MO_LED_OFF) |
2778 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2779 PHY_M_LED_MO_1000(MO_LED_OFF) |
2780 PHY_M_LED_MO_RX(MO_LED_OFF));
2781
793b883e 2782 }
cd28ab6a
SH		 2783}
2784
2785/* blink LED's for finding board */
2786static int sky2_phys_id(struct net_device *dev, u32 data)
2787{
2788 struct sky2_port *sky2 = netdev_priv(dev);
2789 struct sky2_hw *hw = sky2->hw;
2790 unsigned port = sky2->port;
793b883e 2791 u16 ledctrl, ledover = 0;
cd28ab6a 2792 long ms;
91c86df5 2793 int interrupted;
cd28ab6a
SH		 2794 int onoff = 1;
2795
793b883e 2796 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2797 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2798 else
2799 ms = data * 1000;
2800
2801 /* save initial values */
e07b1aa8 2802 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2803 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2804 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2805 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2806 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2807 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2808 } else {
2809 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2810 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2811 }
cd28ab6a 2812
91c86df5
SH		 2813 interrupted = 0;
2814 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2815 sky2_led(hw, port, onoff);
2816 onoff = !onoff;
2817
e07b1aa8 2818 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2819 interrupted = msleep_interruptible(250);
e07b1aa8 2820 spin_lock_bh(&sky2->phy_lock);
91c86df5 2821
cd28ab6a
SH		 2822 ms -= 250;
2823 }
2824
2825 /* resume regularly scheduled programming */
793b883e
SH		 2826 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2827 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2828 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2829 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2830 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2831 } else {
2832 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2833 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2834 }
e07b1aa8 2835 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2836
2837 return 0;
2838}
2839
2840static void sky2_get_pauseparam(struct net_device *dev,
2841 struct ethtool_pauseparam *ecmd)
2842{
2843 struct sky2_port *sky2 = netdev_priv(dev);
2844
2845 ecmd->tx_pause = sky2->tx_pause;
2846 ecmd->rx_pause = sky2->rx_pause;
2847 ecmd->autoneg = sky2->autoneg;
2848}
2849
2850static int sky2_set_pauseparam(struct net_device *dev,
2851 struct ethtool_pauseparam *ecmd)
2852{
2853 struct sky2_port *sky2 = netdev_priv(dev);
2854 int err = 0;
2855
2856 sky2->autoneg = ecmd->autoneg;
2857 sky2->tx_pause = ecmd->tx_pause != 0;
2858 sky2->rx_pause = ecmd->rx_pause != 0;
2859
1b537565 2860 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2861
2862 return err;
2863}
2864
fb17358f
SH		 2865static int sky2_get_coalesce(struct net_device *dev,
2866 struct ethtool_coalesce *ecmd)
2867{
2868 struct sky2_port *sky2 = netdev_priv(dev);
2869 struct sky2_hw *hw = sky2->hw;
2870
2871 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2872 ecmd->tx_coalesce_usecs = 0;
2873 else {
2874 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2875 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2876 }
2877 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2878
2879 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2880 ecmd->rx_coalesce_usecs = 0;
2881 else {
2882 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2883 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2884 }
2885 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2886
2887 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2888 ecmd->rx_coalesce_usecs_irq = 0;
2889 else {
2890 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2891 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2892 }
2893
2894 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2895
2896 return 0;
2897}
2898
2899/* Note: this affect both ports */
2900static int sky2_set_coalesce(struct net_device *dev,
2901 struct ethtool_coalesce *ecmd)
2902{
2903 struct sky2_port *sky2 = netdev_priv(dev);
2904 struct sky2_hw *hw = sky2->hw;
77b3d6a2 2905 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 2906
77b3d6a2
SH		 2907 if (ecmd->tx_coalesce_usecs > tmax ||
2908 ecmd->rx_coalesce_usecs > tmax ||
2909 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 2910 return -EINVAL;
2911
ff81fbbe 2912 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 2913 return -EINVAL;
ff81fbbe 2914 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 2915 return -EINVAL;
ff81fbbe 2916 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 2917 return -EINVAL;
2918
2919 if (ecmd->tx_coalesce_usecs == 0)
2920 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2921 else {
2922 sky2_write32(hw, STAT_TX_TIMER_INI,
2923 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2924 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2925 }
2926 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2927
2928 if (ecmd->rx_coalesce_usecs == 0)
2929 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2930 else {
2931 sky2_write32(hw, STAT_LEV_TIMER_INI,
2932 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2933 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2934 }
2935 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2936
2937 if (ecmd->rx_coalesce_usecs_irq == 0)
2938 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2939 else {
d28d4870 2940 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 2941 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2942 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2943 }
2944 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2945 return 0;
2946}
2947
793b883e
SH		 2948static void sky2_get_ringparam(struct net_device *dev,
2949 struct ethtool_ringparam *ering)
2950{
2951 struct sky2_port *sky2 = netdev_priv(dev);
2952
2953 ering->rx_max_pending = RX_MAX_PENDING;
2954 ering->rx_mini_max_pending = 0;
2955 ering->rx_jumbo_max_pending = 0;
2956 ering->tx_max_pending = TX_RING_SIZE - 1;
2957
2958 ering->rx_pending = sky2->rx_pending;
2959 ering->rx_mini_pending = 0;
2960 ering->rx_jumbo_pending = 0;
2961 ering->tx_pending = sky2->tx_pending;
2962}
2963
2964static int sky2_set_ringparam(struct net_device *dev,
2965 struct ethtool_ringparam *ering)
2966{
2967 struct sky2_port *sky2 = netdev_priv(dev);
2968 int err = 0;
2969
2970 if (ering->rx_pending > RX_MAX_PENDING ||
2971 ering->rx_pending < 8 ||
2972 ering->tx_pending < MAX_SKB_TX_LE ||
2973 ering->tx_pending > TX_RING_SIZE - 1)
2974 return -EINVAL;
2975
2976 if (netif_running(dev))
2977 sky2_down(dev);
2978
2979 sky2->rx_pending = ering->rx_pending;
2980 sky2->tx_pending = ering->tx_pending;
2981
1b537565 2982 if (netif_running(dev)) {
793b883e 2983 err = sky2_up(dev);
1b537565
SH		 2984 if (err)
2985 dev_close(dev);
6ed995bb
SH		 2986 else
2987 sky2_set_multicast(dev);
1b537565 2988 }
793b883e
SH		 2989
2990 return err;
2991}
2992
793b883e
SH		 2993static int sky2_get_regs_len(struct net_device *dev)
2994{
6e4cbb34 2995 return 0x4000;
793b883e
SH		 2996}
2997
2998/*
2999 * Returns copy of control register region
6e4cbb34 3000 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3001 */
3002static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3003 void *p)
3004{
3005 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3006 const void __iomem *io = sky2->hw->regs;
793b883e 3007
6e4cbb34 3008 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3009 regs->version = 1;
6e4cbb34 3010 memset(p, 0, regs->len);
793b883e 3011
6e4cbb34
SH		 3012 memcpy_fromio(p, io, B3_RAM_ADDR);
3013
3014 memcpy_fromio(p + B3_RI_WTO_R1,
3015 io + B3_RI_WTO_R1,
3016 regs->len - B3_RI_WTO_R1);
793b883e 3017}
cd28ab6a
SH		 3018
3019static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3020 .get_settings = sky2_get_settings,
3021 .set_settings = sky2_set_settings,
3022 .get_drvinfo = sky2_get_drvinfo,
3023 .get_msglevel = sky2_get_msglevel,
3024 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3025 .nway_reset = sky2_nway_reset,
793b883e
SH		 3026 .get_regs_len = sky2_get_regs_len,
3027 .get_regs = sky2_get_regs,
3028 .get_link = ethtool_op_get_link,
3029 .get_sg = ethtool_op_get_sg,
3030 .set_sg = ethtool_op_set_sg,
3031 .get_tx_csum = ethtool_op_get_tx_csum,
3032 .set_tx_csum = ethtool_op_set_tx_csum,
3033 .get_tso = ethtool_op_get_tso,
3034 .set_tso = ethtool_op_set_tso,
3035 .get_rx_csum = sky2_get_rx_csum,
3036 .set_rx_csum = sky2_set_rx_csum,
3037 .get_strings = sky2_get_strings,
fb17358f
SH		 3038 .get_coalesce = sky2_get_coalesce,
3039 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3040 .get_ringparam = sky2_get_ringparam,
3041 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3042 .get_pauseparam = sky2_get_pauseparam,
3043 .set_pauseparam = sky2_set_pauseparam,
793b883e 3044 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3045 .get_stats_count = sky2_get_stats_count,
3046 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3047 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3048};
3049
3050/* Initialize network device */
3051static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3052 unsigned port, int highmem)
3053{
3054 struct sky2_port *sky2;
3055 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3056
3057 if (!dev) {
3058 printk(KERN_ERR "sky2 etherdev alloc failed");
3059 return NULL;
3060 }
3061
3062 SET_MODULE_OWNER(dev);
3063 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3064 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3065 dev->open = sky2_up;
3066 dev->stop = sky2_down;
ef743d33 3067 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3068 dev->hard_start_xmit = sky2_xmit_frame;
3069 dev->get_stats = sky2_get_stats;
3070 dev->set_multicast_list = sky2_set_multicast;
3071 dev->set_mac_address = sky2_set_mac_address;
3072 dev->change_mtu = sky2_change_mtu;
3073 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3074 dev->tx_timeout = sky2_tx_timeout;
3075 dev->watchdog_timeo = TX_WATCHDOG;
3076 if (port == 0)
3077 dev->poll = sky2_poll;
3078 dev->weight = NAPI_WEIGHT;
3079#ifdef CONFIG_NET_POLL_CONTROLLER
3080 dev->poll_controller = sky2_netpoll;
3081#endif
cd28ab6a
SH		 3082
3083 sky2 = netdev_priv(dev);
3084 sky2->netdev = dev;
3085 sky2->hw = hw;
3086 sky2->msg_enable = netif_msg_init(debug, default_msg);
3087
3088 spin_lock_init(&sky2->tx_lock);
3089 /* Auto speed and flow control */
3090 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3091 sky2->tx_pause = 1;
cd28ab6a
SH		 3092 sky2->rx_pause = 1;
3093 sky2->duplex = -1;
3094 sky2->speed = -1;
3095 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3096 sky2->rx_csum = 1;
75d070c5 3097
e07b1aa8 3098 spin_lock_init(&sky2->phy_lock);
793b883e 3099 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3100 sky2->rx_pending = RX_DEF_PENDING;
734d1868 3101 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 3102
3103 hw->dev[port] = dev;
3104
3105 sky2->port = port;
3106
5a5b1ea0
SH		 3107 dev->features |= NETIF_F_LLTX;
3108 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3109 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3110 if (highmem)
3111 dev->features |= NETIF_F_HIGHDMA;
793b883e 3112 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3113
d1f13708
SH		 3114#ifdef SKY2_VLAN_TAG_USED
3115 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3116 dev->vlan_rx_register = sky2_vlan_rx_register;
3117 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3118#endif
3119
cd28ab6a 3120 /* read the mac address */
793b883e 3121 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3122 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3123
3124 /* device is off until link detection */
3125 netif_carrier_off(dev);
3126 netif_stop_queue(dev);
3127
3128 return dev;
3129}
3130
28bd181a 3131static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3132{
3133 const struct sky2_port *sky2 = netdev_priv(dev);
3134
3135 if (netif_msg_probe(sky2))
3136 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3137 dev->name,
3138 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3139 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3140}
3141
fb2690a9
SH		 3142/* Handle software interrupt used during MSI test */
3143static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3144 struct pt_regs *regs)
3145{
3146 struct sky2_hw *hw = dev_id;
3147 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3148
3149 if (status == 0)
3150 return IRQ_NONE;
3151
3152 if (status & Y2_IS_IRQ_SW) {
3153 hw->msi_detected = 1;
3154 wake_up(&hw->msi_wait);
3155 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3156 }
3157 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3158
3159 return IRQ_HANDLED;
3160}
3161
3162/* Test interrupt path by forcing a a software IRQ */
3163static int __devinit sky2_test_msi(struct sky2_hw *hw)
3164{
3165 struct pci_dev *pdev = hw->pdev;
3166 int err;
3167
3168 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3169
3170 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3171 if (err) {
3172 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3173 pci_name(pdev), pdev->irq);
3174 return err;
3175 }
3176
3177 init_waitqueue_head (&hw->msi_wait);
3178
3179 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3180 wmb();
3181
3182 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3183
3184 if (!hw->msi_detected) {
3185 /* MSI test failed, go back to INTx mode */
3186 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3187 "switching to INTx mode. Please report this failure to "
3188 "the PCI maintainer and include system chipset information.\n",
3189 pci_name(pdev));
3190
3191 err = -EOPNOTSUPP;
3192 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3193 }
3194
3195 sky2_write32(hw, B0_IMSK, 0);
3196
3197 free_irq(pdev->irq, hw);
3198
3199 return err;
3200}
3201
cd28ab6a
SH		 3202static int __devinit sky2_probe(struct pci_dev *pdev,
3203 const struct pci_device_id *ent)
3204{
793b883e 3205 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3206 struct sky2_hw *hw;
5afa0a9c 3207 int err, pm_cap, using_dac = 0;
cd28ab6a 3208
793b883e
SH		 3209 err = pci_enable_device(pdev);
3210 if (err) {
cd28ab6a
SH		 3211 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3212 pci_name(pdev));
3213 goto err_out;
3214 }
3215
793b883e
SH		 3216 err = pci_request_regions(pdev, DRV_NAME);
3217 if (err) {
cd28ab6a
SH		 3218 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3219 pci_name(pdev));
793b883e 3220 goto err_out;
cd28ab6a
SH		 3221 }
3222
3223 pci_set_master(pdev);
3224
5afa0a9c
SH		 3225 /* Find power-management capability. */
3226 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3227 if (pm_cap == 0) {
3228 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3229 "aborting.\n");
3230 err = -EIO;
3231 goto err_out_free_regions;
3232 }
3233
d1f3d4dd
SH		 3234 if (sizeof(dma_addr_t) > sizeof(u32) &&
3235 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3236 using_dac = 1;
3237 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3238 if (err < 0) {
3239 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3240 "for consistent allocations\n", pci_name(pdev));
3241 goto err_out_free_regions;
3242 }
cd28ab6a 3243
d1f3d4dd 3244 } else {
cd28ab6a
SH		 3245 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3246 if (err) {
3247 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3248 pci_name(pdev));
3249 goto err_out_free_regions;
3250 }
3251 }
d1f3d4dd 3252
cd28ab6a 3253 err = -ENOMEM;
6aad85d6 3254 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3255 if (!hw) {
3256 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3257 pci_name(pdev));
3258 goto err_out_free_regions;
3259 }
3260
cd28ab6a 3261 hw->pdev = pdev;
cd28ab6a
SH		 3262
3263 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3264 if (!hw->regs) {
3265 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3266 pci_name(pdev));
3267 goto err_out_free_hw;
3268 }
5afa0a9c 3269 hw->pm_cap = pm_cap;
cd28ab6a 3270
56a645cc
SH		 3271#ifdef __BIG_ENDIAN
3272 /* byte swap descriptors in hardware */
3273 {
3274 u32 reg;
3275
3276 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3277 reg |= PCI_REV_DESC;
3278 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3279 }
3280#endif
3281
08c06d8a
SH		 3282 /* ring for status responses */
3283 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3284 &hw->st_dma);
3285 if (!hw->st_le)
3286 goto err_out_iounmap;
3287
cd28ab6a
SH		 3288 err = sky2_reset(hw);
3289 if (err)
793b883e 3290 goto err_out_iounmap;
cd28ab6a 3291
5f4f9dc1
SH		 3292 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3293 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
92f965e8 3294 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3295 hw->chip_id, hw->chip_rev);
cd28ab6a 3296
793b883e
SH		 3297 dev = sky2_init_netdev(hw, 0, using_dac);
3298 if (!dev)
cd28ab6a
SH		 3299 goto err_out_free_pci;
3300
793b883e
SH		 3301 err = register_netdev(dev);
3302 if (err) {
cd28ab6a
SH		 3303 printk(KERN_ERR PFX "%s: cannot register net device\n",
3304 pci_name(pdev));
3305 goto err_out_free_netdev;
3306 }
3307
3308 sky2_show_addr(dev);
3309
3310 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3311 if (register_netdev(dev1) == 0)
3312 sky2_show_addr(dev1);
3313 else {
3314 /* Failure to register second port need not be fatal */
793b883e
SH		 3315 printk(KERN_WARNING PFX
3316 "register of second port failed\n");
cd28ab6a
SH		 3317 hw->dev[1] = NULL;
3318 free_netdev(dev1);
3319 }
3320 }
3321
fb2690a9
SH		 3322 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3323 err = sky2_test_msi(hw);
3324 if (err == -EOPNOTSUPP)
3325 pci_disable_msi(pdev);
3326 else if (err)
3327 goto err_out_unregister;
3328 }
3329
3330 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
793b883e
SH		 3331 if (err) {
3332 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3333 pci_name(pdev), pdev->irq);
3334 goto err_out_unregister;
3335 }
3336
e07b1aa8 3337 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
793b883e 3338
01bd7564
SH		 3339 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3340 if (idle_timeout > 0)
3341 mod_timer(&hw->idle_timer,
3342 jiffies + msecs_to_jiffies(idle_timeout));
d27ed387 3343
793b883e
SH		 3344 pci_set_drvdata(pdev, hw);
3345
cd28ab6a
SH		 3346 return 0;
3347
793b883e 3348err_out_unregister:
fb2690a9 3349 pci_disable_msi(pdev);
793b883e
SH		 3350 if (dev1) {
3351 unregister_netdev(dev1);
3352 free_netdev(dev1);
3353 }
3354 unregister_netdev(dev);
cd28ab6a
SH		 3355err_out_free_netdev:
3356 free_netdev(dev);
cd28ab6a 3357err_out_free_pci:
793b883e 3358 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3359 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3360err_out_iounmap:
3361 iounmap(hw->regs);
3362err_out_free_hw:
3363 kfree(hw);
3364err_out_free_regions:
3365 pci_release_regions(pdev);
cd28ab6a 3366 pci_disable_device(pdev);
cd28ab6a
SH		 3367err_out:
3368 return err;
3369}
3370
3371static void __devexit sky2_remove(struct pci_dev *pdev)
3372{
793b883e 3373 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3374 struct net_device *dev0, *dev1;
3375
793b883e 3376 if (!hw)
cd28ab6a
SH		 3377 return;
3378
d27ed387
SH		 3379 del_timer_sync(&hw->idle_timer);
3380
3381 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3382 synchronize_irq(hw->pdev->irq);
3383
cd28ab6a 3384 dev0 = hw->dev[0];
793b883e
SH		 3385 dev1 = hw->dev[1];
3386 if (dev1)
3387 unregister_netdev(dev1);
cd28ab6a
SH		 3388 unregister_netdev(dev0);
3389
5afa0a9c 3390 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3391 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3392 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3393 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3394
3395 free_irq(pdev->irq, hw);
fb2690a9 3396 pci_disable_msi(pdev);
793b883e 3397 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3398 pci_release_regions(pdev);
3399 pci_disable_device(pdev);
793b883e 3400
cd28ab6a
SH		 3401 if (dev1)
3402 free_netdev(dev1);
3403 free_netdev(dev0);
3404 iounmap(hw->regs);
3405 kfree(hw);
5afa0a9c 3406
cd28ab6a
SH		 3407 pci_set_drvdata(pdev, NULL);
3408}
3409
3410#ifdef CONFIG_PM
3411static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3412{
793b883e 3413 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3414 int i;
cd28ab6a
SH		 3415
3416 for (i = 0; i < 2; i++) {
3417 struct net_device *dev = hw->dev[i];
3418
3419 if (dev) {
5afa0a9c
SH		 3420 if (!netif_running(dev))
3421 continue;
3422
3423 sky2_down(dev);
cd28ab6a 3424 netif_device_detach(dev);
cd28ab6a
SH		 3425 }
3426 }
3427
5afa0a9c 3428 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 3429}
3430
3431static int sky2_resume(struct pci_dev *pdev)
3432{
793b883e 3433 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3434 int i, err;
cd28ab6a 3435
cd28ab6a
SH		 3436 pci_restore_state(pdev);
3437 pci_enable_wake(pdev, PCI_D0, 0);
08c06d8a
SH		 3438 err = sky2_set_power_state(hw, PCI_D0);
3439 if (err)
3440 goto out;
cd28ab6a 3441
08c06d8a
SH		 3442 err = sky2_reset(hw);
3443 if (err)
3444 goto out;
cd28ab6a
SH		 3445
3446 for (i = 0; i < 2; i++) {
3447 struct net_device *dev = hw->dev[i];
08c06d8a
SH		 3448 if (dev && netif_running(dev)) {
3449 netif_device_attach(dev);
3450 err = sky2_up(dev);
3451 if (err) {
3452 printk(KERN_ERR PFX "%s: could not up: %d\n",
3453 dev->name, err);
3454 dev_close(dev);
3455 break;
5afa0a9c 3456 }
cd28ab6a
SH		 3457 }
3458 }
08c06d8a
SH		 3459out:
3460 return err;
cd28ab6a
SH		 3461}
3462#endif
3463
3464static struct pci_driver sky2_driver = {
793b883e
SH		 3465 .name = DRV_NAME,
3466 .id_table = sky2_id_table,
3467 .probe = sky2_probe,
3468 .remove = __devexit_p(sky2_remove),
cd28ab6a 3469#ifdef CONFIG_PM
793b883e
SH		 3470 .suspend = sky2_suspend,
3471 .resume = sky2_resume,
cd28ab6a
SH		 3472#endif
3473};
3474
3475static int __init sky2_init_module(void)
3476{
50241c4c 3477 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3478}
3479
3480static void __exit sky2_cleanup_module(void)
3481{
3482 pci_unregister_driver(&sky2_driver);
3483}
3484
3485module_init(sky2_init_module);
3486module_exit(sky2_cleanup_module);
3487
3488MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3489MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3490MODULE_LICENSE("GPL");
5f4f9dc1 3491MODULE_VERSION(DRV_VERSION);
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