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[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
793b883e 26#include <linux/crc32.h>
cd28ab6a
SH		 27#include <linux/kernel.h>
28#include <linux/version.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
52c89cac 53#define DRV_VERSION "1.10"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 66#define RX_SKB_ALIGN 8
22e11703 67#define RX_BUF_WRITE 16
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
cb5d9547
SH		 80#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
cd28ab6a 82static const u32 default_msg =
793b883e
SH		 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 86
793b883e 87static int debug = -1; /* defaults above */
cd28ab6a
SH		 88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
14d0263f 91static int copybreak __read_mostly = 128;
bdb5c58e
SH		 92module_param(copybreak, int, 0);
93MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
fb2690a9
SH		 95static int disable_msi = 0;
96module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
e561a83b 99static int idle_timeout = 0;
01bd7564 100module_param(idle_timeout, int, 0);
e561a83b 101MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 102
cd28ab6a 103static const struct pci_device_id sky2_id_table[] = {
793b883e 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
cd28ab6a
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
2f4a66ad 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
cd28ab6a
SH		 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
5f5d83fd 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
57fa442c
SH		 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
2f4a66ad 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
cd28ab6a
SH		 130 { 0 }
131};
793b883e 132
cd28ab6a
SH		 133MODULE_DEVICE_TABLE(pci, sky2_id_table);
134
135/* Avoid conditionals by using array */
136static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
137static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 138static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 139
92f965e8
SH		 140/* This driver supports yukon2 chipset only */
141static const char *yukon2_name[] = {
142 "XL", /* 0xb3 */
143 "EC Ultra", /* 0xb4 */
144 "UNKNOWN", /* 0xb5 */
145 "EC", /* 0xb6 */
146 "FE", /* 0xb7 */
793b883e
SH		 147};
148
793b883e 149/* Access to external PHY */
ef743d33 150static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 151{
152 int i;
153
154 gma_write16(hw, port, GM_SMI_DATA, val);
155 gma_write16(hw, port, GM_SMI_CTRL,
156 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
157
158 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 159 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 160 return 0;
793b883e 161 udelay(1);
cd28ab6a 162 }
ef743d33 163
793b883e 164 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 165 return -ETIMEDOUT;
cd28ab6a
SH		 166}
167
ef743d33 168static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 169{
170 int i;
171
793b883e 172 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 173 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
174
175 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 176 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
177 *val = gma_read16(hw, port, GM_SMI_DATA);
178 return 0;
179 }
180
793b883e 181 udelay(1);
cd28ab6a
SH		 182 }
183
ef743d33
SH		 184 return -ETIMEDOUT;
185}
186
187static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
188{
189 u16 v;
190
191 if (__gm_phy_read(hw, port, reg, &v) != 0)
192 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
193 return v;
cd28ab6a
SH		 194}
195
2ccc99b7 196static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c
SH		 197{
198 u16 power_control;
5afa0a9c 199 int vaux;
5afa0a9c
SH		 200
201 pr_debug("sky2_set_power_state %d\n", state);
202 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
203
56a645cc 204 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 205 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c
SH		 206 (power_control & PCI_PM_CAP_PME_D3cold);
207
56a645cc 208 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c
SH		 209
210 power_control |= PCI_PM_CTRL_PME_STATUS;
211 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
212
213 switch (state) {
214 case PCI_D0:
215 /* switch power to VCC (WA for VAUX problem) */
216 sky2_write8(hw, B0_POWER_CTRL,
217 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
218
219 /* disable Core Clock Division, */
220 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
221
222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
223 /* enable bits are inverted */
224 sky2_write8(hw, B2_Y2_CLK_GATE,
225 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
226 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
227 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
228 else
229 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
230
977bdf06 231 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
d3bcfbeb
SH		 232 u32 reg1;
233
56a645cc
SH		 234 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
235 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 236 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 237 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
238 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 239 }
240
5afa0a9c
SH		 241 break;
242
243 case PCI_D3hot:
244 case PCI_D3cold:
5afa0a9c
SH		 245 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
246 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
247 else
248 /* enable bits are inverted */
249 sky2_write8(hw, B2_Y2_CLK_GATE,
250 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
251 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
252 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
253
254 /* switch power to VAUX */
255 if (vaux && state != PCI_D3cold)
256 sky2_write8(hw, B0_POWER_CTRL,
257 (PC_VAUX_ENA | PC_VCC_ENA |
258 PC_VAUX_ON | PC_VCC_OFF));
259 break;
260 default:
261 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c
SH		 262 }
263
56a645cc 264 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 265 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c
SH		 266}
267
d3bcfbeb 268static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 269{
270 u16 reg;
271
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 276
cd28ab6a
SH		 277 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
278 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
281
282 reg = gma_read16(hw, port, GM_RX_CTRL);
283 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
284 gma_write16(hw, port, GM_RX_CTRL, reg);
285}
286
16ad91e1
SH		 287/* flow control to advertise bits */
288static const u16 copper_fc_adv[] = {
289 [FC_NONE] = 0,
290 [FC_TX] = PHY_M_AN_ASP,
291 [FC_RX] = PHY_M_AN_PC,
292 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
293};
294
295/* flow control to advertise bits when using 1000BaseX */
296static const u16 fiber_fc_adv[] = {
297 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
298 [FC_TX] = PHY_M_P_ASYM_MD_X,
299 [FC_RX] = PHY_M_P_SYM_MD_X,
300 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
301};
302
303/* flow control to GMA disable bits */
304static const u16 gm_fc_disable[] = {
305 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
306 [FC_TX] = GM_GPCR_FC_RX_DIS,
307 [FC_RX] = GM_GPCR_FC_TX_DIS,
308 [FC_BOTH] = 0,
309};
310
311
cd28ab6a
SH		 312static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
313{
314 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 315 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 316
ed6d32c7 317 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 318 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 319 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
320
321 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 322 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 323 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
324
325 if (hw->chip_id == CHIP_ID_YUKON_EC)
326 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
327 else
328 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
329
330 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
331 }
332
333 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 334 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 335 if (hw->chip_id == CHIP_ID_YUKON_FE) {
336 /* enable automatic crossover */
337 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
338 } else {
339 /* disable energy detect */
340 ctrl &= ~PHY_M_PC_EN_DET_MSK;
341
342 /* enable automatic crossover */
343 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
344
345 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 346 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 347 ctrl &= ~PHY_M_PC_DSC_MSK;
348 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
349 }
350 }
cd28ab6a
SH		 351 } else {
352 /* workaround for deviation #4.88 (CRC errors) */
353 /* disable Automatic Crossover */
354
355 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 356 }
cd28ab6a 357
b89165f2
SH		 358 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
359
360 /* special setup for PHY 88E1112 Fiber */
361 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
362 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 363
b89165f2
SH		 364 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
365 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
366 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
367 ctrl &= ~PHY_M_MAC_MD_MSK;
368 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
369 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
370
371 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 372 /* select page 1 to access Fiber registers */
373 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 374
375 /* for SFP-module set SIGDET polarity to low */
376 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
377 ctrl |= PHY_M_FIB_SIGD_POL;
378 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 379 }
b89165f2
SH		 380
381 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 382 }
383
7800fddc 384 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 385 ct1000 = 0;
386 adv = PHY_AN_CSMA;
2eaba1a2 387 reg = 0;
cd28ab6a
SH		 388
389 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 390 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 391 if (sky2->advertising & ADVERTISED_1000baseT_Full)
392 ct1000 |= PHY_M_1000C_AFD;
393 if (sky2->advertising & ADVERTISED_1000baseT_Half)
394 ct1000 |= PHY_M_1000C_AHD;
395 if (sky2->advertising & ADVERTISED_100baseT_Full)
396 adv |= PHY_M_AN_100_FD;
397 if (sky2->advertising & ADVERTISED_100baseT_Half)
398 adv |= PHY_M_AN_100_HD;
399 if (sky2->advertising & ADVERTISED_10baseT_Full)
400 adv |= PHY_M_AN_10_FD;
401 if (sky2->advertising & ADVERTISED_10baseT_Half)
402 adv |= PHY_M_AN_10_HD;
709c6e7b 403
16ad91e1 404 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 405 } else { /* special defines for FIBER (88E1040S only) */
406 if (sky2->advertising & ADVERTISED_1000baseT_Full)
407 adv |= PHY_M_AN_1000X_AFD;
408 if (sky2->advertising & ADVERTISED_1000baseT_Half)
409 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 410
16ad91e1 411 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 412 }
cd28ab6a
SH		 413
414 /* Restart Auto-negotiation */
415 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
416 } else {
417 /* forced speed/duplex settings */
418 ct1000 = PHY_M_1000C_MSE;
419
2eaba1a2
SH		 420 /* Disable auto update for duplex flow control and speed */
421 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 422
423 switch (sky2->speed) {
424 case SPEED_1000:
425 ctrl |= PHY_CT_SP1000;
2eaba1a2 426 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 427 break;
428 case SPEED_100:
429 ctrl |= PHY_CT_SP100;
2eaba1a2 430 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 431 break;
432 }
433
2eaba1a2
SH		 434 if (sky2->duplex == DUPLEX_FULL) {
435 reg |= GM_GPCR_DUP_FULL;
436 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 437 } else if (sky2->speed < SPEED_1000)
438 sky2->flow_mode = FC_NONE;
2eaba1a2 439
2eaba1a2 440
16ad91e1 441 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 442
443 /* Forward pause packets to GMAC? */
16ad91e1 444 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 445 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
446 else
447 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 448 }
449
2eaba1a2
SH		 450 gma_write16(hw, port, GM_GP_CTRL, reg);
451
cd28ab6a
SH		 452 if (hw->chip_id != CHIP_ID_YUKON_FE)
453 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
454
455 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
456 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
457
458 /* Setup Phy LED's */
459 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
460 ledover = 0;
461
462 switch (hw->chip_id) {
463 case CHIP_ID_YUKON_FE:
464 /* on 88E3082 these bits are at 11..9 (shifted left) */
465 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
466
467 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
468
469 /* delete ACT LED control bits */
470 ctrl &= ~PHY_M_FELP_LED1_MSK;
471 /* change ACT LED control to blink mode */
472 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
473 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
474 break;
475
476 case CHIP_ID_YUKON_XL:
793b883e 477 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 478
479 /* select page 3 to access LED control register */
480 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
481
482 /* set LED Function Control register */
ed6d32c7
SH		 483 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
484 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
485 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
486 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
487 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 488
489 /* set Polarity Control register */
490 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 491 (PHY_M_POLC_LS1_P_MIX(4) |
492 PHY_M_POLC_IS0_P_MIX(4) |
493 PHY_M_POLC_LOS_CTRL(2) |
494 PHY_M_POLC_INIT_CTRL(2) |
495 PHY_M_POLC_STA1_CTRL(2) |
496 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 497
498 /* restore page register */
793b883e 499 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 500 break;
ed6d32c7
SH		 501 case CHIP_ID_YUKON_EC_U:
502 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
503
504 /* select page 3 to access LED control register */
505 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
506
507 /* set LED Function Control register */
508 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
509 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
510 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
511 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
512 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
513
514 /* set Blink Rate in LED Timer Control Register */
515 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
516 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
517 /* restore page register */
518 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
519 break;
cd28ab6a
SH		 520
521 default:
522 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
523 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
524 /* turn off the Rx LED (LED_RX) */
525 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
526 }
527
ed6d32c7 528 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 529 /* apply fixes in PHY AFE */
ed6d32c7
SH		 530 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
532
977bdf06 533 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 534 gm_phy_write(hw, port, 0x18, 0xaa99);
535 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 536
977bdf06 537 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 538 gm_phy_write(hw, port, 0x18, 0xa204);
539 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 540
541 /* set page register to 0 */
ed6d32c7 542 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 543 } else {
544 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 545
977bdf06
SH		 546 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
547 /* turn on 100 Mbps LED (LED_LINK100) */
548 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
549 }
cd28ab6a 550
977bdf06
SH		 551 if (ledover)
552 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
553
554 }
2eaba1a2 555
d571b694 556 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 557 if (sky2->autoneg == AUTONEG_ENABLE)
558 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
559 else
560 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
561}
562
d3bcfbeb
SH		 563static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
564{
565 u32 reg1;
566 static const u32 phy_power[]
567 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
568
569 /* looks like this XL is back asswards .. */
570 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
571 onoff = !onoff;
572
573 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
574
575 if (onoff)
576 /* Turn off phy power saving */
577 reg1 &= ~phy_power[port];
578 else
579 reg1 |= phy_power[port];
580
581 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 582 sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 583 udelay(100);
584}
585
1b537565
SH		 586/* Force a renegotiation */
587static void sky2_phy_reinit(struct sky2_port *sky2)
588{
e07b1aa8 589 spin_lock_bh(&sky2->phy_lock);
1b537565 590 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 591 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 592}
593
cd28ab6a
SH		 594static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
595{
596 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
597 u16 reg;
598 int i;
599 const u8 *addr = hw->dev[port]->dev_addr;
600
42eeea01
SH		 601 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
602 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 603
604 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
605
793b883e 606 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 607 /* WA DEV_472 -- looks like crossed wires on port 2 */
608 /* clear GMAC 1 Control reset */
609 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
610 do {
611 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
612 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
613 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
614 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
615 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
616 }
617
793b883e 618 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 619
2eaba1a2
SH		 620 /* Enable Transmit FIFO Underrun */
621 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
622
e07b1aa8 623 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 624 sky2_phy_init(hw, port);
e07b1aa8 625 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 626
627 /* MIB clear */
628 reg = gma_read16(hw, port, GM_PHY_ADDR);
629 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
630
43f2f104
SH		 631 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
632 gma_read16(hw, port, i);
cd28ab6a
SH		 633 gma_write16(hw, port, GM_PHY_ADDR, reg);
634
635 /* transmit control */
636 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
637
638 /* receive control reg: unicast + multicast + no FCS */
639 gma_write16(hw, port, GM_RX_CTRL,
793b883e 640 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 641
642 /* transmit flow control */
643 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
644
645 /* transmit parameter */
646 gma_write16(hw, port, GM_TX_PARAM,
647 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
648 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
649 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
650 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
651
652 /* serial mode register */
653 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 654 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 655
6b1a3aef 656 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 657 reg |= GM_SMOD_JUMBO_ENA;
658
659 gma_write16(hw, port, GM_SERIAL_MODE, reg);
660
cd28ab6a
SH		 661 /* virtual address for data */
662 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
663
793b883e
SH		 664 /* physical address: used for pause frames */
665 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
666
667 /* ignore counter overflows */
cd28ab6a
SH		 668 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
669 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
670 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
671
672 /* Configure Rx MAC FIFO */
673 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 674 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
675 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 676
d571b694 677 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 678 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 679
793b883e
SH		 680 /* Set threshold to 0xa (64 bytes)
681 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 682 */
683 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
684
685 /* Configure Tx MAC FIFO */
686 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
687 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 688
689 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
6e532cfe 690 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 512/8);
5a5b1ea0
SH		 691 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
692 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
693 /* set Tx GMAC FIFO Almost Empty Threshold */
694 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
695 /* Disable Store & Forward mode for TX */
696 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
697 }
698 }
699
cd28ab6a
SH		 700}
701
470ea7eb
SH		 702/* Assign Ram Buffer allocation in units of 64bit (8 bytes) */
703static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 end)
cd28ab6a 704{
470ea7eb 705 pr_debug(PFX "q %d %#x %#x\n", q, start, end);
793b883e 706
cd28ab6a
SH		 707 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
708 sky2_write32(hw, RB_ADDR(q, RB_START), start);
709 sky2_write32(hw, RB_ADDR(q, RB_END), end);
710 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
711 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
712
713 if (q == Q_R1 || q == Q_R2) {
470ea7eb 714 u32 space = end - start + 1;
1c28f6ba 715 u32 tp = space - space/4;
793b883e 716
1c28f6ba
SH		 717 /* On receive queue's set the thresholds
718 * give receiver priority when > 3/4 full
719 * send pause when down to 2K
720 */
721 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
722 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 723
1c28f6ba
SH		 724 tp = space - 2048/8;
725 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
726 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 727 } else {
728 /* Enable store & forward on Tx queue's because
729 * Tx FIFO is only 1K on Yukon
730 */
731 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
732 }
733
734 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 735 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 736}
737
cd28ab6a 738/* Setup Bus Memory Interface */
af4ed7e6 739static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 740{
741 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
742 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
743 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 744 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 745}
746
cd28ab6a
SH		 747/* Setup prefetch unit registers. This is the interface between
748 * hardware and driver list elements
749 */
8cc048e3 750static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 751 u64 addr, u32 last)
752{
cd28ab6a
SH		 753 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
754 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
755 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
756 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
757 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
758 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 759
760 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 761}
762
793b883e
SH		 763static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
764{
765 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
766
cb5d9547 767 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 768 le->ctrl = 0;
793b883e
SH		 769 return le;
770}
cd28ab6a 771
291ea614
SH		 772static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
773 struct sky2_tx_le *le)
774{
775 return sky2->tx_ring + (le - sky2->tx_le);
776}
777
290d4de5
SH		 778/* Update chip's next pointer */
779static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 780{
98232f85 781 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 782 wmb();
98232f85
SH		 783 sky2_write16(hw, q, idx);
784 sky2_read16(hw, q);
cd28ab6a
SH		 785}
786
793b883e 787
cd28ab6a
SH		 788static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
789{
790 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 791 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 792 le->ctrl = 0;
cd28ab6a
SH		 793 return le;
794}
795
a018e330
SH		 796/* Return high part of DMA address (could be 32 or 64 bit) */
797static inline u32 high32(dma_addr_t a)
798{
a036119f 799 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 800}
801
14d0263f
SH		 802/* Build description to hardware for one receive segment */
803static void sky2_rx_add(struct sky2_port *sky2, u8 op,
804 dma_addr_t map, unsigned len)
cd28ab6a
SH		 805{
806 struct sky2_rx_le *le;
734d1868 807 u32 hi = high32(map);
cd28ab6a 808
793b883e 809 if (sky2->rx_addr64 != hi) {
cd28ab6a 810 le = sky2_next_rx(sky2);
793b883e 811 le->addr = cpu_to_le32(hi);
cd28ab6a 812 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 813 sky2->rx_addr64 = high32(map + len);
cd28ab6a 814 }
793b883e 815
cd28ab6a 816 le = sky2_next_rx(sky2);
734d1868
SH		 817 le->addr = cpu_to_le32((u32) map);
818 le->length = cpu_to_le16(len);
14d0263f 819 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 820}
821
14d0263f
SH		 822/* Build description to hardware for one possibly fragmented skb */
823static void sky2_rx_submit(struct sky2_port *sky2,
824 const struct rx_ring_info *re)
825{
826 int i;
827
828 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
829
830 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
831 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
832}
833
834
835static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
836 unsigned size)
837{
838 struct sk_buff *skb = re->skb;
839 int i;
840
841 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
842 pci_unmap_len_set(re, data_size, size);
843
844 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
845 re->frag_addr[i] = pci_map_page(pdev,
846 skb_shinfo(skb)->frags[i].page,
847 skb_shinfo(skb)->frags[i].page_offset,
848 skb_shinfo(skb)->frags[i].size,
849 PCI_DMA_FROMDEVICE);
850}
851
852static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
853{
854 struct sk_buff *skb = re->skb;
855 int i;
856
857 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
858 PCI_DMA_FROMDEVICE);
859
860 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
861 pci_unmap_page(pdev, re->frag_addr[i],
862 skb_shinfo(skb)->frags[i].size,
863 PCI_DMA_FROMDEVICE);
864}
793b883e 865
cd28ab6a
SH		 866/* Tell chip where to start receive checksum.
867 * Actually has two checksums, but set both same to avoid possible byte
868 * order problems.
869 */
793b883e 870static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 871{
872 struct sky2_rx_le *le;
873
cd28ab6a 874 le = sky2_next_rx(sky2);
f65b138c 875 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 876 le->ctrl = 0;
877 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 878
793b883e
SH		 879 sky2_write32(sky2->hw,
880 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
881 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 882
883}
884
6b1a3aef
SH		 885/*
886 * The RX Stop command will not work for Yukon-2 if the BMU does not
887 * reach the end of packet and since we can't make sure that we have
888 * incoming data, we must reset the BMU while it is not doing a DMA
889 * transfer. Since it is possible that the RX path is still active,
890 * the RX RAM buffer will be stopped first, so any possible incoming
891 * data will not trigger a DMA. After the RAM buffer is stopped, the
892 * BMU is polled until any DMA in progress is ended and only then it
893 * will be reset.
894 */
895static void sky2_rx_stop(struct sky2_port *sky2)
896{
897 struct sky2_hw *hw = sky2->hw;
898 unsigned rxq = rxqaddr[sky2->port];
899 int i;
900
901 /* disable the RAM Buffer receive queue */
902 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
903
904 for (i = 0; i < 0xffff; i++)
905 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
906 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
907 goto stopped;
908
909 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
910 sky2->netdev->name);
911stopped:
912 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
913
914 /* reset the Rx prefetch unit */
915 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
916}
793b883e 917
d571b694 918/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 919static void sky2_rx_clean(struct sky2_port *sky2)
920{
921 unsigned i;
922
923 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 924 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 925 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 926
927 if (re->skb) {
14d0263f 928 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 929 kfree_skb(re->skb);
930 re->skb = NULL;
931 }
932 }
933}
934
ef743d33
SH		 935/* Basic MII support */
936static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
937{
938 struct mii_ioctl_data *data = if_mii(ifr);
939 struct sky2_port *sky2 = netdev_priv(dev);
940 struct sky2_hw *hw = sky2->hw;
941 int err = -EOPNOTSUPP;
942
943 if (!netif_running(dev))
944 return -ENODEV; /* Phy still in reset */
945
d89e1343 946 switch (cmd) {
ef743d33
SH		 947 case SIOCGMIIPHY:
948 data->phy_id = PHY_ADDR_MARV;
949
950 /* fallthru */
951 case SIOCGMIIREG: {
952 u16 val = 0;
91c86df5 953
e07b1aa8 954 spin_lock_bh(&sky2->phy_lock);
ef743d33 955 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 956 spin_unlock_bh(&sky2->phy_lock);
91c86df5 957
ef743d33
SH		 958 data->val_out = val;
959 break;
960 }
961
962 case SIOCSMIIREG:
963 if (!capable(CAP_NET_ADMIN))
964 return -EPERM;
965
e07b1aa8 966 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 967 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
968 data->val_in);
e07b1aa8 969 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 970 break;
971 }
972 return err;
973}
974
d1f13708
SH		 975#ifdef SKY2_VLAN_TAG_USED
976static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
977{
978 struct sky2_port *sky2 = netdev_priv(dev);
979 struct sky2_hw *hw = sky2->hw;
980 u16 port = sky2->port;
d1f13708 981
2bb8c262 982 netif_tx_lock_bh(dev);
d1f13708
SH		 983
984 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
985 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
986 sky2->vlgrp = grp;
987
2bb8c262 988 netif_tx_unlock_bh(dev);
d1f13708
SH		 989}
990
991static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
992{
993 struct sky2_port *sky2 = netdev_priv(dev);
994 struct sky2_hw *hw = sky2->hw;
995 u16 port = sky2->port;
d1f13708 996
2bb8c262 997 netif_tx_lock_bh(dev);
d1f13708
SH		 998
999 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1000 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1001 if (sky2->vlgrp)
1002 sky2->vlgrp->vlan_devices[vid] = NULL;
1003
2bb8c262 1004 netif_tx_unlock_bh(dev);
d1f13708
SH		 1005}
1006#endif
1007
82788c7a 1008/*
14d0263f
SH		 1009 * Allocate an skb for receiving. If the MTU is large enough
1010 * make the skb non-linear with a fragment list of pages.
1011 *
82788c7a
SH		 1012 * It appears the hardware has a bug in the FIFO logic that
1013 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1014 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1015 * aligned except if slab debugging is enabled.
82788c7a 1016 */
14d0263f 1017static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1018{
1019 struct sk_buff *skb;
14d0263f
SH		 1020 unsigned long p;
1021 int i;
82788c7a 1022
14d0263f
SH		 1023 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1024 if (!skb)
1025 goto nomem;
1026
1027 p = (unsigned long) skb->data;
1028 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1029
1030 for (i = 0; i < sky2->rx_nfrags; i++) {
1031 struct page *page = alloc_page(GFP_ATOMIC);
1032
1033 if (!page)
1034 goto free_partial;
1035 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1036 }
1037
1038 return skb;
14d0263f
SH		 1039free_partial:
1040 kfree_skb(skb);
1041nomem:
1042 return NULL;
82788c7a
SH		 1043}
1044
cd28ab6a
SH		 1045/*
1046 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1047 * Normal case this ends up creating one list element for skb
1048 * in the receive ring. Worst case if using large MTU and each
1049 * allocation falls on a different 64 bit region, that results
1050 * in 6 list elements per ring entry.
1051 * One element is used for checksum enable/disable, and one
1052 * extra to avoid wrap.
cd28ab6a 1053 */
6b1a3aef 1054static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1055{
6b1a3aef 1056 struct sky2_hw *hw = sky2->hw;
14d0263f 1057 struct rx_ring_info *re;
6b1a3aef 1058 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1059 unsigned i, size, space, thresh;
cd28ab6a 1060
6b1a3aef 1061 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1062 sky2_qset(hw, rxq);
977bdf06
SH		 1063
1064 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
1065 /* MAC Rx RAM Read is controlled by hardware */
1066 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1067 }
1068
6b1a3aef
SH		 1069 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1070
1071 rx_set_checksum(sky2);
14d0263f
SH		 1072
1073 /* Space needed for frame data + headers rounded up */
1074 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1075 + 8;
1076
1077 /* Stopping point for hardware truncation */
1078 thresh = (size - 8) / sizeof(u32);
1079
1080 /* Account for overhead of skb - to avoid order > 0 allocation */
1081 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1082 + sizeof(struct skb_shared_info);
1083
1084 sky2->rx_nfrags = space >> PAGE_SHIFT;
1085 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1086
1087 if (sky2->rx_nfrags != 0) {
1088 /* Compute residue after pages */
1089 space = sky2->rx_nfrags << PAGE_SHIFT;
1090
1091 if (space < size)
1092 size -= space;
1093 else
1094 size = 0;
1095
1096 /* Optimize to handle small packets and headers */
1097 if (size < copybreak)
1098 size = copybreak;
1099 if (size < ETH_HLEN)
1100 size = ETH_HLEN;
1101 }
1102 sky2->rx_data_size = size;
1103
1104 /* Fill Rx ring */
793b883e 1105 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1106 re = sky2->rx_ring + i;
cd28ab6a 1107
14d0263f 1108 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1109 if (!re->skb)
1110 goto nomem;
1111
14d0263f
SH		 1112 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1113 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1114 }
1115
a1433ac4
SH		 1116 /*
1117 * The receiver hangs if it receives frames larger than the
1118 * packet buffer. As a workaround, truncate oversize frames, but
1119 * the register is limited to 9 bits, so if you do frames > 2052
1120 * you better get the MTU right!
1121 */
a1433ac4
SH		 1122 if (thresh > 0x1ff)
1123 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1124 else {
1125 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1126 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1127 }
1128
6b1a3aef
SH		 1129 /* Tell chip about available buffers */
1130 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1131 return 0;
1132nomem:
1133 sky2_rx_clean(sky2);
1134 return -ENOMEM;
1135}
1136
1137/* Bring up network interface. */
1138static int sky2_up(struct net_device *dev)
1139{
1140 struct sky2_port *sky2 = netdev_priv(dev);
1141 struct sky2_hw *hw = sky2->hw;
1142 unsigned port = sky2->port;
e07b1aa8 1143 u32 ramsize, rxspace, imask;
ee7abb04 1144 int cap, err = -ENOMEM;
843a46f4 1145 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1146
ee7abb04
SH		 1147 /*
1148 * On dual port PCI-X card, there is an problem where status
1149 * can be received out of order due to split transactions
843a46f4 1150 */
ee7abb04
SH		 1151 if (otherdev && netif_running(otherdev) &&
1152 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1153 struct sky2_port *osky2 = netdev_priv(otherdev);
1154 u16 cmd;
1155
1156 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1157 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1158 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1159
1160 sky2->rx_csum = 0;
1161 osky2->rx_csum = 0;
1162 }
843a46f4 1163
cd28ab6a
SH		 1164 if (netif_msg_ifup(sky2))
1165 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1166
1167 /* must be power of 2 */
1168 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1169 TX_RING_SIZE *
1170 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1171 &sky2->tx_le_map);
1172 if (!sky2->tx_le)
1173 goto err_out;
1174
6cdbbdf3 1175 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1176 GFP_KERNEL);
1177 if (!sky2->tx_ring)
1178 goto err_out;
1179 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1180
1181 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1182 &sky2->rx_le_map);
1183 if (!sky2->rx_le)
1184 goto err_out;
1185 memset(sky2->rx_le, 0, RX_LE_BYTES);
1186
291ea614 1187 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1188 GFP_KERNEL);
1189 if (!sky2->rx_ring)
1190 goto err_out;
1191
d3bcfbeb
SH		 1192 sky2_phy_power(hw, port, 1);
1193
cd28ab6a
SH		 1194 sky2_mac_init(hw, port);
1195
470ea7eb
SH		 1196 /* Determine available ram buffer space in qwords. */
1197 ramsize = sky2_read8(hw, B2_E_0) * 4096/8;
1c28f6ba 1198
470ea7eb
SH		 1199 if (ramsize > 6*1024/8)
1200 rxspace = ramsize - (ramsize + 2) / 3;
1201 else
1202 rxspace = ramsize / 2;
cd28ab6a 1203
470ea7eb
SH		 1204 sky2_ramset(hw, rxqaddr[port], 0, rxspace-1);
1205 sky2_ramset(hw, txqaddr[port], rxspace, ramsize-1);
cd28ab6a 1206
793b883e
SH		 1207 /* Make sure SyncQ is disabled */
1208 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1209 RB_RST_SET);
1210
af4ed7e6 1211 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1212
977bdf06 1213 /* Set almost empty threshold */
c2716fb4
SH		 1214 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1215 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1216 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1217
6b1a3aef
SH		 1218 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1219 TX_RING_SIZE - 1);
cd28ab6a 1220
6b1a3aef 1221 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1222 if (err)
1223 goto err_out;
1224
cd28ab6a 1225 /* Enable interrupts from phy/mac for port */
e07b1aa8 1226 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1227 imask |= portirq_msk[port];
e07b1aa8
SH		 1228 sky2_write32(hw, B0_IMSK, imask);
1229
cd28ab6a
SH		 1230 return 0;
1231
1232err_out:
1b537565 1233 if (sky2->rx_le) {
cd28ab6a
SH		 1234 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1235 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1236 sky2->rx_le = NULL;
1237 }
1238 if (sky2->tx_le) {
cd28ab6a
SH		 1239 pci_free_consistent(hw->pdev,
1240 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1241 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1242 sky2->tx_le = NULL;
1243 }
1244 kfree(sky2->tx_ring);
1245 kfree(sky2->rx_ring);
cd28ab6a 1246
1b537565
SH		 1247 sky2->tx_ring = NULL;
1248 sky2->rx_ring = NULL;
cd28ab6a
SH		 1249 return err;
1250}
1251
793b883e
SH		 1252/* Modular subtraction in ring */
1253static inline int tx_dist(unsigned tail, unsigned head)
1254{
cb5d9547 1255 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1256}
cd28ab6a 1257
793b883e
SH		 1258/* Number of list elements available for next tx */
1259static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1260{
793b883e 1261 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1262}
1263
793b883e 1264/* Estimate of number of transmit list elements required */
28bd181a 1265static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1266{
793b883e
SH		 1267 unsigned count;
1268
1269 count = sizeof(dma_addr_t) / sizeof(u32);
1270 count += skb_shinfo(skb)->nr_frags * count;
1271
89114afd 1272 if (skb_is_gso(skb))
793b883e
SH		 1273 ++count;
1274
84fa7933 1275 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1276 ++count;
1277
1278 return count;
cd28ab6a
SH		 1279}
1280
793b883e
SH		 1281/*
1282 * Put one packet in ring for transmit.
1283 * A single packet can generate multiple list elements, and
1284 * the number of ring elements will probably be less than the number
1285 * of list elements used.
1286 */
cd28ab6a
SH		 1287static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1288{
1289 struct sky2_port *sky2 = netdev_priv(dev);
1290 struct sky2_hw *hw = sky2->hw;
d1f13708 1291 struct sky2_tx_le *le = NULL;
6cdbbdf3 1292 struct tx_ring_info *re;
cd28ab6a
SH		 1293 unsigned i, len;
1294 dma_addr_t mapping;
1295 u32 addr64;
1296 u16 mss;
1297 u8 ctrl;
1298
2bb8c262
SH		 1299 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1300 return NETDEV_TX_BUSY;
cd28ab6a 1301
793b883e 1302 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1303 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1304 dev->name, sky2->tx_prod, skb->len);
1305
cd28ab6a
SH		 1306 len = skb_headlen(skb);
1307 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1308 addr64 = high32(mapping);
793b883e 1309
a018e330
SH		 1310 /* Send high bits if changed or crosses boundary */
1311 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1312 le = get_tx_le(sky2);
f65b138c 1313 le->addr = cpu_to_le32(addr64);
793b883e 1314 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1315 sky2->tx_addr64 = high32(mapping + len);
793b883e 1316 }
cd28ab6a
SH		 1317
1318 /* Check for TCP Segmentation Offload */
7967168c 1319 mss = skb_shinfo(skb)->gso_size;
793b883e 1320 if (mss != 0) {
cd28ab6a
SH		 1321 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1322 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1323 mss += ETH_HLEN;
1324
e07560cd
SH		 1325 if (mss != sky2->tx_last_mss) {
1326 le = get_tx_le(sky2);
f65b138c 1327 le->addr = cpu_to_le32(mss);
e07560cd 1328 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1329 sky2->tx_last_mss = mss;
1330 }
cd28ab6a
SH		 1331 }
1332
cd28ab6a 1333 ctrl = 0;
d1f13708
SH		 1334#ifdef SKY2_VLAN_TAG_USED
1335 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1336 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1337 if (!le) {
1338 le = get_tx_le(sky2);
f65b138c 1339 le->addr = 0;
d1f13708 1340 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1341 } else
1342 le->opcode |= OP_VLAN;
1343 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1344 ctrl |= INS_VLAN;
1345 }
1346#endif
1347
1348 /* Handle TCP checksum offload */
84fa7933 1349 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1350 unsigned offset = skb->h.raw - skb->data;
1351 u32 tcpsum;
1352
1353 tcpsum = offset << 16; /* sum start */
1354 tcpsum |= offset + skb->csum; /* sum write */
cd28ab6a
SH		 1355
1356 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1357 if (skb->nh.iph->protocol == IPPROTO_UDP)
1358 ctrl |= UDPTCP;
1359
f65b138c
SH		 1360 if (tcpsum != sky2->tx_tcpsum) {
1361 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1362
1363 le = get_tx_le(sky2);
f65b138c 1364 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1365 le->length = 0; /* initial checksum value */
1366 le->ctrl = 1; /* one packet */
1367 le->opcode = OP_TCPLISW | HW_OWNER;
1368 }
cd28ab6a
SH		 1369 }
1370
1371 le = get_tx_le(sky2);
f65b138c 1372 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1373 le->length = cpu_to_le16(len);
1374 le->ctrl = ctrl;
793b883e 1375 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1376
291ea614 1377 re = tx_le_re(sky2, le);
cd28ab6a 1378 re->skb = skb;
6cdbbdf3 1379 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1380 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1381
1382 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1383 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1384
1385 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1386 frag->size, PCI_DMA_TODEVICE);
a036119f 1387 addr64 = high32(mapping);
793b883e
SH		 1388 if (addr64 != sky2->tx_addr64) {
1389 le = get_tx_le(sky2);
f65b138c 1390 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1391 le->ctrl = 0;
1392 le->opcode = OP_ADDR64 | HW_OWNER;
1393 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1394 }
1395
1396 le = get_tx_le(sky2);
f65b138c 1397 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1398 le->length = cpu_to_le16(frag->size);
1399 le->ctrl = ctrl;
793b883e 1400 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1401
291ea614
SH		 1402 re = tx_le_re(sky2, le);
1403 re->skb = skb;
1404 pci_unmap_addr_set(re, mapaddr, mapping);
1405 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1406 }
6cdbbdf3 1407
cd28ab6a
SH		 1408 le->ctrl |= EOP;
1409
97bda706
SH		 1410 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1411 netif_stop_queue(dev);
b19666d9 1412
290d4de5 1413 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1414
cd28ab6a
SH		 1415 dev->trans_start = jiffies;
1416 return NETDEV_TX_OK;
1417}
1418
cd28ab6a 1419/*
793b883e
SH		 1420 * Free ring elements from starting at tx_cons until "done"
1421 *
1422 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1423 * buffers so make sure not to free skb to early.
cd28ab6a 1424 */
d11c13e7 1425static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1426{
d11c13e7 1427 struct net_device *dev = sky2->netdev;
af2a58ac 1428 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1429 unsigned idx;
cd28ab6a 1430
0e3ff6aa 1431 BUG_ON(done >= TX_RING_SIZE);
2224795d 1432
291ea614
SH		 1433 for (idx = sky2->tx_cons; idx != done;
1434 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1435 struct sky2_tx_le *le = sky2->tx_le + idx;
1436 struct tx_ring_info *re = sky2->tx_ring + idx;
1437
1438 switch(le->opcode & ~HW_OWNER) {
1439 case OP_LARGESEND:
1440 case OP_PACKET:
1441 pci_unmap_single(pdev,
1442 pci_unmap_addr(re, mapaddr),
1443 pci_unmap_len(re, maplen),
1444 PCI_DMA_TODEVICE);
af2a58ac 1445 break;
291ea614
SH		 1446 case OP_BUFFER:
1447 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1448 pci_unmap_len(re, maplen),
734d1868 1449 PCI_DMA_TODEVICE);
291ea614
SH		 1450 break;
1451 }
1452
1453 if (le->ctrl & EOP) {
1454 if (unlikely(netif_msg_tx_done(sky2)))
1455 printk(KERN_DEBUG "%s: tx done %u\n",
1456 dev->name, idx);
1457 dev_kfree_skb(re->skb);
cd28ab6a
SH		 1458 }
1459
291ea614 1460 le->opcode = 0; /* paranoia */
793b883e 1461 }
793b883e 1462
291ea614 1463 sky2->tx_cons = idx;
22e11703 1464 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1465 netif_wake_queue(dev);
cd28ab6a
SH		 1466}
1467
1468/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1469static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1470{
2bb8c262
SH		 1471 struct sky2_port *sky2 = netdev_priv(dev);
1472
1473 netif_tx_lock_bh(dev);
d11c13e7 1474 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1475 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1476}
1477
1478/* Network shutdown */
1479static int sky2_down(struct net_device *dev)
1480{
1481 struct sky2_port *sky2 = netdev_priv(dev);
1482 struct sky2_hw *hw = sky2->hw;
1483 unsigned port = sky2->port;
1484 u16 ctrl;
e07b1aa8 1485 u32 imask;
cd28ab6a 1486
1b537565
SH		 1487 /* Never really got started! */
1488 if (!sky2->tx_le)
1489 return 0;
1490
cd28ab6a
SH		 1491 if (netif_msg_ifdown(sky2))
1492 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1493
018d1c66 1494 /* Stop more packets from being queued */
cd28ab6a
SH		 1495 netif_stop_queue(dev);
1496
ebc646f6
SH		 1497 /* Disable port IRQ */
1498 imask = sky2_read32(hw, B0_IMSK);
1499 imask &= ~portirq_msk[port];
1500 sky2_write32(hw, B0_IMSK, imask);
1501
d3bcfbeb 1502 sky2_gmac_reset(hw, port);
793b883e 1503
cd28ab6a
SH		 1504 /* Stop transmitter */
1505 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1506 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1507
1508 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1509 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1510
c2716fb4
SH		 1511 /* WA for dev. #4.209 */
1512 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1513 && hw->chip_rev == CHIP_REV_YU_EC_U_A1)
1514 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1515 sky2->speed != SPEED_1000 ?
1516 TX_STFW_ENA : TX_STFW_DIS);
1517
cd28ab6a 1518 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1519 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1520 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1521
1522 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1523
1524 /* Workaround shared GMAC reset */
793b883e
SH		 1525 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1526 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1527 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1528
1529 /* Disable Force Sync bit and Enable Alloc bit */
1530 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1531 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1532
1533 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1534 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1535 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1536
1537 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1538 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1539 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1540
1541 /* Reset the Tx prefetch units */
1542 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1543 PREF_UNIT_RST_SET);
1544
1545 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1546
6b1a3aef 1547 sky2_rx_stop(sky2);
cd28ab6a
SH		 1548
1549 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1550 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1551
d3bcfbeb
SH		 1552 sky2_phy_power(hw, port, 0);
1553
d571b694 1554 /* turn off LED's */
cd28ab6a
SH		 1555 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1556
018d1c66
SH		 1557 synchronize_irq(hw->pdev->irq);
1558
2bb8c262 1559 sky2_tx_clean(dev);
cd28ab6a
SH		 1560 sky2_rx_clean(sky2);
1561
1562 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1563 sky2->rx_le, sky2->rx_le_map);
1564 kfree(sky2->rx_ring);
1565
1566 pci_free_consistent(hw->pdev,
1567 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1568 sky2->tx_le, sky2->tx_le_map);
1569 kfree(sky2->tx_ring);
1570
1b537565
SH		 1571 sky2->tx_le = NULL;
1572 sky2->rx_le = NULL;
1573
1574 sky2->rx_ring = NULL;
1575 sky2->tx_ring = NULL;
1576
cd28ab6a
SH		 1577 return 0;
1578}
1579
1580static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1581{
b89165f2 1582 if (!sky2_is_copper(hw))
793b883e
SH		 1583 return SPEED_1000;
1584
cd28ab6a
SH		 1585 if (hw->chip_id == CHIP_ID_YUKON_FE)
1586 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1587
1588 switch (aux & PHY_M_PS_SPEED_MSK) {
1589 case PHY_M_PS_SPEED_1000:
1590 return SPEED_1000;
1591 case PHY_M_PS_SPEED_100:
1592 return SPEED_100;
1593 default:
1594 return SPEED_10;
1595 }
1596}
1597
1598static void sky2_link_up(struct sky2_port *sky2)
1599{
1600 struct sky2_hw *hw = sky2->hw;
1601 unsigned port = sky2->port;
1602 u16 reg;
16ad91e1
SH		 1603 static const char *fc_name[] = {
1604 [FC_NONE] = "none",
1605 [FC_TX] = "tx",
1606 [FC_RX] = "rx",
1607 [FC_BOTH] = "both",
1608 };
cd28ab6a 1609
cd28ab6a 1610 /* enable Rx/Tx */
2eaba1a2 1611 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1612 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1613 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1614
1615 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1616
1617 netif_carrier_on(sky2->netdev);
1618 netif_wake_queue(sky2->netdev);
1619
1620 /* Turn on link LED */
793b883e 1621 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1622 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1623
ed6d32c7 1624 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1625 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1626 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1627
1628 switch(sky2->speed) {
1629 case SPEED_10:
1630 led |= PHY_M_LEDC_INIT_CTRL(7);
1631 break;
1632
1633 case SPEED_100:
1634 led |= PHY_M_LEDC_STA1_CTRL(7);
1635 break;
1636
1637 case SPEED_1000:
1638 led |= PHY_M_LEDC_STA0_CTRL(7);
1639 break;
1640 }
793b883e
SH		 1641
1642 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1643 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1644 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1645 }
1646
cd28ab6a
SH		 1647 if (netif_msg_link(sky2))
1648 printk(KERN_INFO PFX
d571b694 1649 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1650 sky2->netdev->name, sky2->speed,
1651 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1652 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1653}
1654
1655static void sky2_link_down(struct sky2_port *sky2)
1656{
1657 struct sky2_hw *hw = sky2->hw;
1658 unsigned port = sky2->port;
1659 u16 reg;
1660
1661 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1662
1663 reg = gma_read16(hw, port, GM_GP_CTRL);
1664 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1665 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1666
16ad91e1 1667 if (sky2->flow_status == FC_RX) {
cd28ab6a
SH		 1668 /* restore Asymmetric Pause bit */
1669 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1670 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1671 | PHY_M_AN_ASP);
cd28ab6a
SH		 1672 }
1673
cd28ab6a
SH		 1674 netif_carrier_off(sky2->netdev);
1675 netif_stop_queue(sky2->netdev);
1676
1677 /* Turn on link LED */
1678 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1679
1680 if (netif_msg_link(sky2))
1681 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1682
cd28ab6a
SH		 1683 sky2_phy_init(hw, port);
1684}
1685
16ad91e1
SH		 1686static enum flow_control sky2_flow(int rx, int tx)
1687{
1688 if (rx)
1689 return tx ? FC_BOTH : FC_RX;
1690 else
1691 return tx ? FC_TX : FC_NONE;
1692}
1693
793b883e
SH		 1694static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1695{
1696 struct sky2_hw *hw = sky2->hw;
1697 unsigned port = sky2->port;
1698 u16 lpa;
1699
1700 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1701
1702 if (lpa & PHY_M_AN_RF) {
1703 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1704 return -1;
1705 }
1706
793b883e
SH		 1707 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1708 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1709 sky2->netdev->name);
1710 return -1;
1711 }
1712
793b883e 1713 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1714 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e
SH		 1715
1716 /* Pause bits are offset (9..8) */
ed6d32c7 1717 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1718 aux >>= 6;
1719
16ad91e1
SH		 1720 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1721 aux & PHY_M_PS_TX_P_EN);
793b883e 1722
16ad91e1 1723 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2eaba1a2 1724 && hw->chip_id != CHIP_ID_YUKON_EC_U)
16ad91e1 1725 sky2->flow_status = FC_NONE;
2eaba1a2 1726
16ad91e1 1727 if (aux & PHY_M_PS_RX_P_EN)
793b883e
SH		 1728 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1729 else
1730 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1731
1732 return 0;
1733}
cd28ab6a 1734
e07b1aa8
SH		 1735/* Interrupt from PHY */
1736static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1737{
e07b1aa8
SH		 1738 struct net_device *dev = hw->dev[port];
1739 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1740 u16 istatus, phystat;
1741
ebc646f6
SH		 1742 if (!netif_running(dev))
1743 return;
1744
e07b1aa8
SH		 1745 spin_lock(&sky2->phy_lock);
1746 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1747 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1748
cd28ab6a
SH		 1749 if (netif_msg_intr(sky2))
1750 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1751 sky2->netdev->name, istatus, phystat);
1752
2eaba1a2 1753 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1754 if (sky2_autoneg_done(sky2, phystat) == 0)
1755 sky2_link_up(sky2);
1756 goto out;
1757 }
cd28ab6a 1758
793b883e
SH		 1759 if (istatus & PHY_M_IS_LSP_CHANGE)
1760 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1761
793b883e
SH		 1762 if (istatus & PHY_M_IS_DUP_CHANGE)
1763 sky2->duplex =
1764 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1765
793b883e
SH		 1766 if (istatus & PHY_M_IS_LST_CHANGE) {
1767 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1768 sky2_link_up(sky2);
793b883e
SH		 1769 else
1770 sky2_link_down(sky2);
cd28ab6a 1771 }
793b883e 1772out:
e07b1aa8 1773 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1774}
1775
302d1252
SH		 1776
1777/* Transmit timeout is only called if we are running, carries is up
1778 * and tx queue is full (stopped).
1779 */
cd28ab6a
SH		 1780static void sky2_tx_timeout(struct net_device *dev)
1781{
1782 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1783 struct sky2_hw *hw = sky2->hw;
1784 unsigned txq = txqaddr[sky2->port];
8f24664d 1785 u16 report, done;
cd28ab6a
SH		 1786
1787 if (netif_msg_timer(sky2))
1788 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1789
8f24664d
SH		 1790 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1791 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1792
8f24664d
SH		 1793 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1794 dev->name,
1795 sky2->tx_cons, sky2->tx_prod, report, done);
1796
1797 if (report != done) {
1798 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1799
1800 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1801 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1802 } else if (report != sky2->tx_cons) {
1803 printk(KERN_INFO PFX "status report lost?\n");
1804
2bb8c262 1805 netif_tx_lock_bh(dev);
8f24664d 1806 sky2_tx_complete(sky2, report);
2bb8c262 1807 netif_tx_unlock_bh(dev);
8f24664d
SH		 1808 } else {
1809 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1810
8f24664d
SH		 1811 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1812 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1813
2bb8c262 1814 sky2_tx_clean(dev);
8f24664d
SH		 1815
1816 sky2_qset(hw, txq);
1817 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1818 }
cd28ab6a
SH		 1819}
1820
1821static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1822{
6b1a3aef
SH		 1823 struct sky2_port *sky2 = netdev_priv(dev);
1824 struct sky2_hw *hw = sky2->hw;
1825 int err;
1826 u16 ctl, mode;
e07b1aa8 1827 u32 imask;
cd28ab6a
SH		 1828
1829 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1830 return -EINVAL;
1831
5a5b1ea0
SH		 1832 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1833 return -EINVAL;
1834
6b1a3aef
SH		 1835 if (!netif_running(dev)) {
1836 dev->mtu = new_mtu;
1837 return 0;
1838 }
1839
e07b1aa8 1840 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1841 sky2_write32(hw, B0_IMSK, 0);
1842
018d1c66
SH		 1843 dev->trans_start = jiffies; /* prevent tx timeout */
1844 netif_stop_queue(dev);
1845 netif_poll_disable(hw->dev[0]);
1846
e07b1aa8
SH		 1847 synchronize_irq(hw->pdev->irq);
1848
6b1a3aef
SH		 1849 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1850 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1851 sky2_rx_stop(sky2);
1852 sky2_rx_clean(sky2);
cd28ab6a
SH		 1853
1854 dev->mtu = new_mtu;
14d0263f 1855
6b1a3aef
SH		 1856 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1857 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1858
1859 if (dev->mtu > ETH_DATA_LEN)
1860 mode |= GM_SMOD_JUMBO_ENA;
1861
1862 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1863
6b1a3aef 1864 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1865
6b1a3aef 1866 err = sky2_rx_start(sky2);
e07b1aa8 1867 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1868
1b537565
SH		 1869 if (err)
1870 dev_close(dev);
1871 else {
1872 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1873
1874 netif_poll_enable(hw->dev[0]);
1875 netif_wake_queue(dev);
1876 }
1877
cd28ab6a
SH		 1878 return err;
1879}
1880
14d0263f
SH		 1881/* For small just reuse existing skb for next receive */
1882static struct sk_buff *receive_copy(struct sky2_port *sky2,
1883 const struct rx_ring_info *re,
1884 unsigned length)
1885{
1886 struct sk_buff *skb;
1887
1888 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1889 if (likely(skb)) {
1890 skb_reserve(skb, 2);
1891 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1892 length, PCI_DMA_FROMDEVICE);
1893 memcpy(skb->data, re->skb->data, length);
1894 skb->ip_summed = re->skb->ip_summed;
1895 skb->csum = re->skb->csum;
1896 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1897 length, PCI_DMA_FROMDEVICE);
1898 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1899 skb_put(skb, length);
14d0263f
SH		 1900 }
1901 return skb;
1902}
1903
1904/* Adjust length of skb with fragments to match received data */
1905static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1906 unsigned int length)
1907{
1908 int i, num_frags;
1909 unsigned int size;
1910
1911 /* put header into skb */
1912 size = min(length, hdr_space);
1913 skb->tail += size;
1914 skb->len += size;
1915 length -= size;
1916
1917 num_frags = skb_shinfo(skb)->nr_frags;
1918 for (i = 0; i < num_frags; i++) {
1919 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1920
1921 if (length == 0) {
1922 /* don't need this page */
1923 __free_page(frag->page);
1924 --skb_shinfo(skb)->nr_frags;
1925 } else {
1926 size = min(length, (unsigned) PAGE_SIZE);
1927
1928 frag->size = size;
1929 skb->data_len += size;
1930 skb->truesize += size;
1931 skb->len += size;
1932 length -= size;
1933 }
1934 }
1935}
1936
1937/* Normal packet - take skb from ring element and put in a new one */
1938static struct sk_buff *receive_new(struct sky2_port *sky2,
1939 struct rx_ring_info *re,
1940 unsigned int length)
1941{
1942 struct sk_buff *skb, *nskb;
1943 unsigned hdr_space = sky2->rx_data_size;
1944
1945 pr_debug(PFX "receive new length=%d\n", length);
1946
1947 /* Don't be tricky about reusing pages (yet) */
1948 nskb = sky2_rx_alloc(sky2);
1949 if (unlikely(!nskb))
1950 return NULL;
1951
1952 skb = re->skb;
1953 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1954
1955 prefetch(skb->data);
1956 re->skb = nskb;
1957 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
1958
1959 if (skb_shinfo(skb)->nr_frags)
1960 skb_put_frags(skb, hdr_space, length);
1961 else
489b10c1 1962 skb_put(skb, length);
14d0263f
SH		 1963 return skb;
1964}
1965
cd28ab6a
SH		 1966/*
1967 * Receive one packet.
d571b694 1968 * For larger packets, get new buffer.
cd28ab6a 1969 */
497d7c86 1970static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 1971 u16 length, u32 status)
1972{
497d7c86 1973 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 1974 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1975 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1976
1977 if (unlikely(netif_msg_rx_status(sky2)))
1978 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 1979 dev->name, sky2->rx_next, status, length);
cd28ab6a 1980
793b883e 1981 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1982 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1983
42eeea01 1984 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1985 goto error;
1986
42eeea01
SH		 1987 if (!(status & GMR_FS_RX_OK))
1988 goto resubmit;
1989
497d7c86 1990 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 1991 goto oversize;
1992
14d0263f
SH		 1993 if (length < copybreak)
1994 skb = receive_copy(sky2, re, length);
1995 else
1996 skb = receive_new(sky2, re, length);
793b883e 1997resubmit:
14d0263f 1998 sky2_rx_submit(sky2, re);
79e57d32 1999
cd28ab6a
SH		 2000 return skb;
2001
6e15b712
SH		 2002oversize:
2003 ++sky2->net_stats.rx_over_errors;
2004 goto resubmit;
2005
cd28ab6a 2006error:
6e15b712 2007 ++sky2->net_stats.rx_errors;
b6d77734
SH		 2008 if (status & GMR_FS_RX_FF_OV) {
2009 sky2->net_stats.rx_fifo_errors++;
2010 goto resubmit;
2011 }
6e15b712 2012
3be92a70 2013 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2014 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2015 dev->name, status, length);
793b883e
SH		 2016
2017 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2018 sky2->net_stats.rx_length_errors++;
2019 if (status & GMR_FS_FRAGMENT)
2020 sky2->net_stats.rx_frame_errors++;
2021 if (status & GMR_FS_CRC_ERR)
2022 sky2->net_stats.rx_crc_errors++;
79e57d32 2023
793b883e 2024 goto resubmit;
cd28ab6a
SH		 2025}
2026
e07b1aa8
SH		 2027/* Transmit complete */
2028static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2029{
e07b1aa8 2030 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2031
e07b1aa8 2032 if (netif_running(dev)) {
2bb8c262 2033 netif_tx_lock(dev);
e07b1aa8 2034 sky2_tx_complete(sky2, last);
2bb8c262 2035 netif_tx_unlock(dev);
2224795d 2036 }
cd28ab6a
SH		 2037}
2038
e07b1aa8
SH		 2039/* Process status response ring */
2040static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2041{
22e11703 2042 struct sky2_port *sky2;
e07b1aa8 2043 int work_done = 0;
22e11703 2044 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2045 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2046
af2a58ac 2047 rmb();
bea86103 2048
e71ebd73 2049 while (hw->st_idx != hwidx) {
13210ce5
SH		 2050 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2051 struct net_device *dev;
cd28ab6a 2052 struct sk_buff *skb;
cd28ab6a
SH		 2053 u32 status;
2054 u16 length;
2055
cb5d9547 2056 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2057
e71ebd73
SH		 2058 BUG_ON(le->link >= 2);
2059 dev = hw->dev[le->link];
13210ce5
SH		 2060
2061 sky2 = netdev_priv(dev);
f65b138c
SH		 2062 length = le16_to_cpu(le->length);
2063 status = le32_to_cpu(le->status);
cd28ab6a 2064
e71ebd73 2065 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2066 case OP_RXSTAT:
497d7c86 2067 skb = sky2_receive(dev, length, status);
d1f13708
SH		 2068 if (!skb)
2069 break;
13210ce5 2070
13210ce5
SH		 2071 skb->protocol = eth_type_trans(skb, dev);
2072 dev->last_rx = jiffies;
2073
d1f13708
SH		 2074#ifdef SKY2_VLAN_TAG_USED
2075 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2076 vlan_hwaccel_receive_skb(skb,
2077 sky2->vlgrp,
2078 be16_to_cpu(sky2->rx_tag));
2079 } else
2080#endif
cd28ab6a 2081 netif_receive_skb(skb);
13210ce5 2082
22e11703
SH		 2083 /* Update receiver after 16 frames */
2084 if (++buf_write[le->link] == RX_BUF_WRITE) {
2085 sky2_put_idx(hw, rxqaddr[le->link],
2086 sky2->rx_put);
2087 buf_write[le->link] = 0;
2088 }
2089
2090 /* Stop after net poll weight */
13210ce5
SH		 2091 if (++work_done >= to_do)
2092 goto exit_loop;
cd28ab6a
SH		 2093 break;
2094
d1f13708
SH		 2095#ifdef SKY2_VLAN_TAG_USED
2096 case OP_RXVLAN:
2097 sky2->rx_tag = length;
2098 break;
2099
2100 case OP_RXCHKSVLAN:
2101 sky2->rx_tag = length;
2102 /* fall through */
2103#endif
cd28ab6a 2104 case OP_RXCHKS:
d11c13e7 2105 skb = sky2->rx_ring[sky2->rx_next].skb;
84fa7933 2106 skb->ip_summed = CHECKSUM_COMPLETE;
f65b138c 2107 skb->csum = status & 0xffff;
cd28ab6a
SH		 2108 break;
2109
2110 case OP_TXINDEXLE:
13b97b74 2111 /* TX index reports status for both ports */
f55925d7
SH		 2112 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2113 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2114 if (hw->dev[1])
2115 sky2_tx_done(hw->dev[1],
2116 ((status >> 24) & 0xff)
2117 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2118 break;
2119
cd28ab6a
SH		 2120 default:
2121 if (net_ratelimit())
793b883e 2122 printk(KERN_WARNING PFX
e71ebd73
SH		 2123 "unknown status opcode 0x%x\n", le->opcode);
2124 goto exit_loop;
cd28ab6a 2125 }
13210ce5 2126 }
cd28ab6a 2127
fe2a24df
SH		 2128 /* Fully processed status ring so clear irq */
2129 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2130
13210ce5 2131exit_loop:
22e11703
SH		 2132 if (buf_write[0]) {
2133 sky2 = netdev_priv(hw->dev[0]);
2134 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2135 }
2136
2137 if (buf_write[1]) {
2138 sky2 = netdev_priv(hw->dev[1]);
2139 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2140 }
2141
e07b1aa8 2142 return work_done;
cd28ab6a
SH		 2143}
2144
2145static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2146{
2147 struct net_device *dev = hw->dev[port];
2148
3be92a70
SH		 2149 if (net_ratelimit())
2150 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2151 dev->name, status);
cd28ab6a
SH		 2152
2153 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2154 if (net_ratelimit())
2155 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2156 dev->name);
cd28ab6a
SH		 2157 /* Clear IRQ */
2158 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2159 }
2160
2161 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2162 if (net_ratelimit())
2163 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2164 dev->name);
cd28ab6a
SH		 2165
2166 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2167 }
2168
2169 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2170 if (net_ratelimit())
2171 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2172 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2173 }
2174
2175 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2176 if (net_ratelimit())
2177 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2178 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2179 }
2180
2181 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2182 if (net_ratelimit())
2183 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2184 dev->name);
cd28ab6a
SH		 2185 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2186 }
2187}
2188
2189static void sky2_hw_intr(struct sky2_hw *hw)
2190{
2191 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2192
793b883e 2193 if (status & Y2_IS_TIST_OV)
cd28ab6a 2194 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2195
2196 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2197 u16 pci_err;
2198
56a645cc 2199 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2200 if (net_ratelimit())
2201 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2202 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2203
2204 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2205 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2206 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2207 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2208 }
2209
2210 if (status & Y2_IS_PCI_EXP) {
d571b694 2211 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2212 u32 pex_err;
2213
7bd656d1 2214 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2215
3be92a70
SH		 2216 if (net_ratelimit())
2217 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2218 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2219
2220 /* clear the interrupt */
2221 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2222 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2223 0xffffffffUL);
cd28ab6a
SH		 2224 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2225
7bd656d1 2226 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2227 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2228 hwmsk &= ~Y2_IS_PCI_EXP;
2229 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2230 }
2231 }
2232
2233 if (status & Y2_HWE_L1_MASK)
2234 sky2_hw_error(hw, 0, status);
2235 status >>= 8;
2236 if (status & Y2_HWE_L1_MASK)
2237 sky2_hw_error(hw, 1, status);
2238}
2239
2240static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2241{
2242 struct net_device *dev = hw->dev[port];
2243 struct sky2_port *sky2 = netdev_priv(dev);
2244 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2245
2246 if (netif_msg_intr(sky2))
2247 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2248 dev->name, status);
2249
2250 if (status & GM_IS_RX_FF_OR) {
2251 ++sky2->net_stats.rx_fifo_errors;
2252 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2253 }
2254
2255 if (status & GM_IS_TX_FF_UR) {
2256 ++sky2->net_stats.tx_fifo_errors;
2257 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2258 }
cd28ab6a
SH		 2259}
2260
d257924e
SH		 2261/* This should never happen it is a fatal situation */
2262static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2263 const char *rxtx, u32 mask)
2264{
2265 struct net_device *dev = hw->dev[port];
2266 struct sky2_port *sky2 = netdev_priv(dev);
2267 u32 imask;
2268
2269 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2270 dev ? dev->name : "<not registered>", rxtx);
2271
2272 imask = sky2_read32(hw, B0_IMSK);
2273 imask &= ~mask;
2274 sky2_write32(hw, B0_IMSK, imask);
2275
2276 if (dev) {
2277 spin_lock(&sky2->phy_lock);
2278 sky2_link_down(sky2);
2279 spin_unlock(&sky2->phy_lock);
2280 }
2281}
cd28ab6a 2282
d27ed387
SH		 2283/* If idle then force a fake soft NAPI poll once a second
2284 * to work around cases where sharing an edge triggered interrupt.
2285 */
eb35cf60
SH		 2286static inline void sky2_idle_start(struct sky2_hw *hw)
2287{
2288 if (idle_timeout > 0)
2289 mod_timer(&hw->idle_timer,
2290 jiffies + msecs_to_jiffies(idle_timeout));
2291}
2292
d27ed387
SH		 2293static void sky2_idle(unsigned long arg)
2294{
01bd7564
SH		 2295 struct sky2_hw *hw = (struct sky2_hw *) arg;
2296 struct net_device *dev = hw->dev[0];
d27ed387 2297
d27ed387
SH		 2298 if (__netif_rx_schedule_prep(dev))
2299 __netif_rx_schedule(dev);
01bd7564
SH		 2300
2301 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2302}
2303
2304
e07b1aa8 2305static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2306{
e07b1aa8
SH		 2307 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2308 int work_limit = min(dev0->quota, *budget);
2309 int work_done = 0;
fb2690a9 2310 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2311
1e5f1283
SH		 2312 if (status & Y2_IS_HW_ERR)
2313 sky2_hw_intr(hw);
d257924e 2314
1e5f1283
SH		 2315 if (status & Y2_IS_IRQ_PHY1)
2316 sky2_phy_intr(hw, 0);
cd28ab6a 2317
1e5f1283
SH		 2318 if (status & Y2_IS_IRQ_PHY2)
2319 sky2_phy_intr(hw, 1);
cd28ab6a 2320
1e5f1283
SH		 2321 if (status & Y2_IS_IRQ_MAC1)
2322 sky2_mac_intr(hw, 0);
cd28ab6a 2323
1e5f1283
SH		 2324 if (status & Y2_IS_IRQ_MAC2)
2325 sky2_mac_intr(hw, 1);
cd28ab6a 2326
1e5f1283
SH		 2327 if (status & Y2_IS_CHK_RX1)
2328 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2329
1e5f1283
SH		 2330 if (status & Y2_IS_CHK_RX2)
2331 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2332
1e5f1283
SH		 2333 if (status & Y2_IS_CHK_TXA1)
2334 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2335
1e5f1283
SH		 2336 if (status & Y2_IS_CHK_TXA2)
2337 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2338
1e5f1283 2339 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2340 if (work_done < work_limit) {
2341 netif_rx_complete(dev0);
86fba634 2342
fe2a24df
SH		 2343 sky2_read32(hw, B0_Y2_SP_LISR);
2344 return 0;
2345 } else {
2346 *budget -= work_done;
2347 dev0->quota -= work_done;
1e5f1283 2348 return 1;
fe2a24df 2349 }
e07b1aa8
SH		 2350}
2351
7d12e780 2352static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2353{
2354 struct sky2_hw *hw = dev_id;
2355 struct net_device *dev0 = hw->dev[0];
2356 u32 status;
2357
2358 /* Reading this mask interrupts as side effect */
2359 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2360 if (status == 0 || status == ~0)
2361 return IRQ_NONE;
793b883e 2362
e07b1aa8
SH		 2363 prefetch(&hw->st_le[hw->st_idx]);
2364 if (likely(__netif_rx_schedule_prep(dev0)))
2365 __netif_rx_schedule(dev0);
793b883e 2366
cd28ab6a
SH		 2367 return IRQ_HANDLED;
2368}
2369
2370#ifdef CONFIG_NET_POLL_CONTROLLER
2371static void sky2_netpoll(struct net_device *dev)
2372{
2373 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2374 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2375
88d11360
SH		 2376 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2377 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2378}
2379#endif
2380
2381/* Chip internal frequency for clock calculations */
fb17358f 2382static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2383{
793b883e 2384 switch (hw->chip_id) {
cd28ab6a 2385 case CHIP_ID_YUKON_EC:
5a5b1ea0 2386 case CHIP_ID_YUKON_EC_U:
fb17358f 2387 return 125; /* 125 Mhz */
cd28ab6a 2388 case CHIP_ID_YUKON_FE:
fb17358f 2389 return 100; /* 100 Mhz */
793b883e 2390 default: /* YUKON_XL */
fb17358f 2391 return 156; /* 156 Mhz */
cd28ab6a
SH		 2392 }
2393}
2394
fb17358f 2395static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2396{
fb17358f 2397 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2398}
2399
fb17358f 2400static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2401{
fb17358f 2402 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2403}
2404
fb17358f 2405
59139528 2406static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2407{
cd28ab6a 2408 u16 status;
b89165f2 2409 u8 t8;
56a645cc 2410 int i;
cd28ab6a 2411
cd28ab6a 2412 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2413
cd28ab6a
SH		 2414 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2415 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2416 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2417 pci_name(hw->pdev), hw->chip_id);
2418 return -EOPNOTSUPP;
2419 }
2420
290d4de5
SH		 2421 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2422
2423 /* This rev is really old, and requires untested workarounds */
2424 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2425 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2426 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2427 hw->chip_id, hw->chip_rev);
2428 return -EOPNOTSUPP;
2429 }
2430
cd28ab6a
SH		 2431 /* disable ASF */
2432 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2433 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2434 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2435 }
2436
2437 /* do a SW reset */
2438 sky2_write8(hw, B0_CTST, CS_RST_SET);
2439 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2440
2441 /* clear PCI errors, if any */
56a645cc 2442 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2443
cd28ab6a 2444 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2445 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2446
cd28ab6a
SH		 2447
2448 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2449
2450 /* clear any PEX errors */
7bd656d1
SH		 2451 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2452 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2453
cd28ab6a 2454
b89165f2 2455 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
cd28ab6a
SH		 2456 hw->ports = 1;
2457 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2458 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2459 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2460 ++hw->ports;
2461 }
cd28ab6a 2462
5afa0a9c 2463 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2464
2465 for (i = 0; i < hw->ports; i++) {
2466 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2467 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2468 }
2469
2470 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2471
793b883e
SH		 2472 /* Clear I2C IRQ noise */
2473 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2474
2475 /* turn off hardware timer (unused) */
2476 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2477 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2478
cd28ab6a
SH		 2479 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2480
69634ee7
SH		 2481 /* Turn off descriptor polling */
2482 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2483
2484 /* Turn off receive timestamp */
2485 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2486 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2487
2488 /* enable the Tx Arbiters */
2489 for (i = 0; i < hw->ports; i++)
2490 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2491
2492 /* Initialize ram interface */
2493 for (i = 0; i < hw->ports; i++) {
793b883e 2494 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2495
2496 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2497 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2498 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2499 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2500 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2501 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2502 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2503 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2504 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2505 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2506 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2507 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2508 }
2509
7bd656d1 2510 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2511
cd28ab6a 2512 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2513 sky2_gmac_reset(hw, i);
cd28ab6a 2514
cd28ab6a
SH		 2515 memset(hw->st_le, 0, STATUS_LE_BYTES);
2516 hw->st_idx = 0;
2517
2518 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2519 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2520
2521 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2522 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2523
2524 /* Set the list last index */
793b883e 2525 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2526
290d4de5
SH		 2527 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2528 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2529
290d4de5
SH		 2530 /* set Status-FIFO ISR watermark */
2531 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2532 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2533 else
2534 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2535
290d4de5 2536 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2537 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2538 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2539
793b883e 2540 /* enable status unit */
cd28ab6a
SH		 2541 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2542
2543 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2544 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2545 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2546
2547 return 0;
2548}
2549
28bd181a 2550static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2551{
b89165f2
SH		 2552 if (sky2_is_copper(hw)) {
2553 u32 modes = SUPPORTED_10baseT_Half
2554 | SUPPORTED_10baseT_Full
2555 | SUPPORTED_100baseT_Half
2556 | SUPPORTED_100baseT_Full
2557 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2558
2559 if (hw->chip_id != CHIP_ID_YUKON_FE)
2560 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2561 | SUPPORTED_1000baseT_Full;
2562 return modes;
cd28ab6a 2563 } else
b89165f2
SH		 2564 return SUPPORTED_1000baseT_Half
2565 | SUPPORTED_1000baseT_Full
2566 | SUPPORTED_Autoneg
2567 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2568}
2569
793b883e 2570static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2571{
2572 struct sky2_port *sky2 = netdev_priv(dev);
2573 struct sky2_hw *hw = sky2->hw;
2574
2575 ecmd->transceiver = XCVR_INTERNAL;
2576 ecmd->supported = sky2_supported_modes(hw);
2577 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2578 if (sky2_is_copper(hw)) {
cd28ab6a 2579 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2580 | SUPPORTED_10baseT_Full
2581 | SUPPORTED_100baseT_Half
2582 | SUPPORTED_100baseT_Full
2583 | SUPPORTED_1000baseT_Half
2584 | SUPPORTED_1000baseT_Full
2585 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2586 ecmd->port = PORT_TP;
b89165f2
SH		 2587 ecmd->speed = sky2->speed;
2588 } else {
2589 ecmd->speed = SPEED_1000;
cd28ab6a 2590 ecmd->port = PORT_FIBRE;
b89165f2 2591 }
cd28ab6a
SH		 2592
2593 ecmd->advertising = sky2->advertising;
2594 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2595 ecmd->duplex = sky2->duplex;
2596 return 0;
2597}
2598
2599static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2600{
2601 struct sky2_port *sky2 = netdev_priv(dev);
2602 const struct sky2_hw *hw = sky2->hw;
2603 u32 supported = sky2_supported_modes(hw);
2604
2605 if (ecmd->autoneg == AUTONEG_ENABLE) {
2606 ecmd->advertising = supported;
2607 sky2->duplex = -1;
2608 sky2->speed = -1;
2609 } else {
2610 u32 setting;
2611
793b883e 2612 switch (ecmd->speed) {
cd28ab6a
SH		 2613 case SPEED_1000:
2614 if (ecmd->duplex == DUPLEX_FULL)
2615 setting = SUPPORTED_1000baseT_Full;
2616 else if (ecmd->duplex == DUPLEX_HALF)
2617 setting = SUPPORTED_1000baseT_Half;
2618 else
2619 return -EINVAL;
2620 break;
2621 case SPEED_100:
2622 if (ecmd->duplex == DUPLEX_FULL)
2623 setting = SUPPORTED_100baseT_Full;
2624 else if (ecmd->duplex == DUPLEX_HALF)
2625 setting = SUPPORTED_100baseT_Half;
2626 else
2627 return -EINVAL;
2628 break;
2629
2630 case SPEED_10:
2631 if (ecmd->duplex == DUPLEX_FULL)
2632 setting = SUPPORTED_10baseT_Full;
2633 else if (ecmd->duplex == DUPLEX_HALF)
2634 setting = SUPPORTED_10baseT_Half;
2635 else
2636 return -EINVAL;
2637 break;
2638 default:
2639 return -EINVAL;
2640 }
2641
2642 if ((setting & supported) == 0)
2643 return -EINVAL;
2644
2645 sky2->speed = ecmd->speed;
2646 sky2->duplex = ecmd->duplex;
2647 }
2648
2649 sky2->autoneg = ecmd->autoneg;
2650 sky2->advertising = ecmd->advertising;
2651
1b537565
SH		 2652 if (netif_running(dev))
2653 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2654
2655 return 0;
2656}
2657
2658static void sky2_get_drvinfo(struct net_device *dev,
2659 struct ethtool_drvinfo *info)
2660{
2661 struct sky2_port *sky2 = netdev_priv(dev);
2662
2663 strcpy(info->driver, DRV_NAME);
2664 strcpy(info->version, DRV_VERSION);
2665 strcpy(info->fw_version, "N/A");
2666 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2667}
2668
2669static const struct sky2_stat {
793b883e
SH		 2670 char name[ETH_GSTRING_LEN];
2671 u16 offset;
cd28ab6a
SH		 2672} sky2_stats[] = {
2673 { "tx_bytes", GM_TXO_OK_HI },
2674 { "rx_bytes", GM_RXO_OK_HI },
2675 { "tx_broadcast", GM_TXF_BC_OK },
2676 { "rx_broadcast", GM_RXF_BC_OK },
2677 { "tx_multicast", GM_TXF_MC_OK },
2678 { "rx_multicast", GM_RXF_MC_OK },
2679 { "tx_unicast", GM_TXF_UC_OK },
2680 { "rx_unicast", GM_RXF_UC_OK },
2681 { "tx_mac_pause", GM_TXF_MPAUSE },
2682 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2683 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2684 { "late_collision",GM_TXF_LAT_COL },
2685 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2686 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2687 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2688
d2604540 2689 { "rx_short", GM_RXF_SHT },
cd28ab6a 2690 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2691 { "rx_64_byte_packets", GM_RXF_64B },
2692 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2693 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2694 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2695 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2696 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2697 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2698 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2699 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2700 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2701 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2702
2703 { "tx_64_byte_packets", GM_TXF_64B },
2704 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2705 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2706 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2707 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2708 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2709 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2710 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2711};
2712
cd28ab6a
SH		 2713static u32 sky2_get_rx_csum(struct net_device *dev)
2714{
2715 struct sky2_port *sky2 = netdev_priv(dev);
2716
2717 return sky2->rx_csum;
2718}
2719
2720static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2721{
2722 struct sky2_port *sky2 = netdev_priv(dev);
2723
2724 sky2->rx_csum = data;
793b883e 2725
cd28ab6a
SH		 2726 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2727 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2728
2729 return 0;
2730}
2731
2732static u32 sky2_get_msglevel(struct net_device *netdev)
2733{
2734 struct sky2_port *sky2 = netdev_priv(netdev);
2735 return sky2->msg_enable;
2736}
2737
9a7ae0a9
SH		 2738static int sky2_nway_reset(struct net_device *dev)
2739{
2740 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2741
16ad91e1 2742 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2743 return -EINVAL;
2744
1b537565 2745 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2746
2747 return 0;
2748}
2749
793b883e 2750static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2751{
2752 struct sky2_hw *hw = sky2->hw;
2753 unsigned port = sky2->port;
2754 int i;
2755
2756 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2757 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2758 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2759 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2760
793b883e 2761 for (i = 2; i < count; i++)
cd28ab6a
SH		 2762 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2763}
2764
cd28ab6a
SH		 2765static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2766{
2767 struct sky2_port *sky2 = netdev_priv(netdev);
2768 sky2->msg_enable = value;
2769}
2770
2771static int sky2_get_stats_count(struct net_device *dev)
2772{
2773 return ARRAY_SIZE(sky2_stats);
2774}
2775
2776static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2777 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2778{
2779 struct sky2_port *sky2 = netdev_priv(dev);
2780
793b883e 2781 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2782}
2783
793b883e 2784static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2785{
2786 int i;
2787
2788 switch (stringset) {
2789 case ETH_SS_STATS:
2790 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2791 memcpy(data + i * ETH_GSTRING_LEN,
2792 sky2_stats[i].name, ETH_GSTRING_LEN);
2793 break;
2794 }
2795}
2796
2797/* Use hardware MIB variables for critical path statistics and
2798 * transmit feedback not reported at interrupt.
2799 * Other errors are accounted for in interrupt handler.
2800 */
2801static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2802{
2803 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2804 u64 data[13];
cd28ab6a 2805
793b883e 2806 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2807
2808 sky2->net_stats.tx_bytes = data[0];
2809 sky2->net_stats.rx_bytes = data[1];
2810 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2811 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2812 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2813 sky2->net_stats.collisions = data[10];
2814 sky2->net_stats.tx_aborted_errors = data[12];
2815
2816 return &sky2->net_stats;
2817}
2818
2819static int sky2_set_mac_address(struct net_device *dev, void *p)
2820{
2821 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2822 struct sky2_hw *hw = sky2->hw;
2823 unsigned port = sky2->port;
2824 const struct sockaddr *addr = p;
cd28ab6a
SH		 2825
2826 if (!is_valid_ether_addr(addr->sa_data))
2827 return -EADDRNOTAVAIL;
2828
cd28ab6a 2829 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2830 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2831 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2832 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2833 dev->dev_addr, ETH_ALEN);
1b537565 2834
a8ab1ec0
SH		 2835 /* virtual address for data */
2836 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2837
2838 /* physical address: used for pause frames */
2839 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2840
2841 return 0;
cd28ab6a
SH		 2842}
2843
a052b52f
SH		 2844static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2845{
2846 u32 bit;
2847
2848 bit = ether_crc(ETH_ALEN, addr) & 63;
2849 filter[bit >> 3] |= 1 << (bit & 7);
2850}
2851
cd28ab6a
SH		 2852static void sky2_set_multicast(struct net_device *dev)
2853{
2854 struct sky2_port *sky2 = netdev_priv(dev);
2855 struct sky2_hw *hw = sky2->hw;
2856 unsigned port = sky2->port;
2857 struct dev_mc_list *list = dev->mc_list;
2858 u16 reg;
2859 u8 filter[8];
a052b52f
SH		 2860 int rx_pause;
2861 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 2862
a052b52f 2863 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 2864 memset(filter, 0, sizeof(filter));
2865
2866 reg = gma_read16(hw, port, GM_RX_CTRL);
2867 reg |= GM_RXCR_UCF_ENA;
2868
d571b694 2869 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2870 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 2871 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 2872 memset(filter, 0xff, sizeof(filter));
a052b52f 2873 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 2874 reg &= ~GM_RXCR_MCF_ENA;
2875 else {
2876 int i;
2877 reg |= GM_RXCR_MCF_ENA;
2878
a052b52f
SH		 2879 if (rx_pause)
2880 sky2_add_filter(filter, pause_mc_addr);
2881
2882 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2883 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 2884 }
2885
cd28ab6a 2886 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2887 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2888 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2889 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2890 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2891 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2892 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2893 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2894
2895 gma_write16(hw, port, GM_RX_CTRL, reg);
2896}
2897
2898/* Can have one global because blinking is controlled by
2899 * ethtool and that is always under RTNL mutex
2900 */
91c86df5 2901static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2902{
793b883e
SH		 2903 u16 pg;
2904
793b883e
SH		 2905 switch (hw->chip_id) {
2906 case CHIP_ID_YUKON_XL:
2907 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2908 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2909 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2910 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2911 PHY_M_LEDC_INIT_CTRL(7) |
2912 PHY_M_LEDC_STA1_CTRL(7) |
2913 PHY_M_LEDC_STA0_CTRL(7))
2914 : 0);
2915
2916 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2917 break;
2918
2919 default:
2920 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2921 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2922 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2923 PHY_M_LED_MO_10(MO_LED_ON) |
2924 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2925 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2926 PHY_M_LED_MO_RX(MO_LED_ON)
2927 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2928 PHY_M_LED_MO_10(MO_LED_OFF) |
2929 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2930 PHY_M_LED_MO_1000(MO_LED_OFF) |
2931 PHY_M_LED_MO_RX(MO_LED_OFF));
2932
793b883e 2933 }
cd28ab6a
SH		 2934}
2935
2936/* blink LED's for finding board */
2937static int sky2_phys_id(struct net_device *dev, u32 data)
2938{
2939 struct sky2_port *sky2 = netdev_priv(dev);
2940 struct sky2_hw *hw = sky2->hw;
2941 unsigned port = sky2->port;
793b883e 2942 u16 ledctrl, ledover = 0;
cd28ab6a 2943 long ms;
91c86df5 2944 int interrupted;
cd28ab6a
SH		 2945 int onoff = 1;
2946
793b883e 2947 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2948 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2949 else
2950 ms = data * 1000;
2951
2952 /* save initial values */
e07b1aa8 2953 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2954 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2955 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2956 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2957 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2958 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2959 } else {
2960 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2961 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2962 }
cd28ab6a 2963
91c86df5
SH		 2964 interrupted = 0;
2965 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2966 sky2_led(hw, port, onoff);
2967 onoff = !onoff;
2968
e07b1aa8 2969 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2970 interrupted = msleep_interruptible(250);
e07b1aa8 2971 spin_lock_bh(&sky2->phy_lock);
91c86df5 2972
cd28ab6a
SH		 2973 ms -= 250;
2974 }
2975
2976 /* resume regularly scheduled programming */
793b883e
SH		 2977 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2978 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2979 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2980 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2981 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2982 } else {
2983 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2984 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2985 }
e07b1aa8 2986 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2987
2988 return 0;
2989}
2990
2991static void sky2_get_pauseparam(struct net_device *dev,
2992 struct ethtool_pauseparam *ecmd)
2993{
2994 struct sky2_port *sky2 = netdev_priv(dev);
2995
16ad91e1
SH		 2996 switch (sky2->flow_mode) {
2997 case FC_NONE:
2998 ecmd->tx_pause = ecmd->rx_pause = 0;
2999 break;
3000 case FC_TX:
3001 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3002 break;
3003 case FC_RX:
3004 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3005 break;
3006 case FC_BOTH:
3007 ecmd->tx_pause = ecmd->rx_pause = 1;
3008 }
3009
cd28ab6a
SH		 3010 ecmd->autoneg = sky2->autoneg;
3011}
3012
3013static int sky2_set_pauseparam(struct net_device *dev,
3014 struct ethtool_pauseparam *ecmd)
3015{
3016 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3017
3018 sky2->autoneg = ecmd->autoneg;
16ad91e1 3019 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3020
16ad91e1
SH		 3021 if (netif_running(dev))
3022 sky2_phy_reinit(sky2);
cd28ab6a 3023
2eaba1a2 3024 return 0;
cd28ab6a
SH		 3025}
3026
fb17358f
SH		 3027static int sky2_get_coalesce(struct net_device *dev,
3028 struct ethtool_coalesce *ecmd)
3029{
3030 struct sky2_port *sky2 = netdev_priv(dev);
3031 struct sky2_hw *hw = sky2->hw;
3032
3033 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3034 ecmd->tx_coalesce_usecs = 0;
3035 else {
3036 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3037 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3038 }
3039 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3040
3041 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3042 ecmd->rx_coalesce_usecs = 0;
3043 else {
3044 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3045 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3046 }
3047 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3048
3049 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3050 ecmd->rx_coalesce_usecs_irq = 0;
3051 else {
3052 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3053 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3054 }
3055
3056 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3057
3058 return 0;
3059}
3060
3061/* Note: this affect both ports */
3062static int sky2_set_coalesce(struct net_device *dev,
3063 struct ethtool_coalesce *ecmd)
3064{
3065 struct sky2_port *sky2 = netdev_priv(dev);
3066 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3067 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3068
77b3d6a2
SH		 3069 if (ecmd->tx_coalesce_usecs > tmax ||
3070 ecmd->rx_coalesce_usecs > tmax ||
3071 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3072 return -EINVAL;
3073
ff81fbbe 3074 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3075 return -EINVAL;
ff81fbbe 3076 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3077 return -EINVAL;
ff81fbbe 3078 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3079 return -EINVAL;
3080
3081 if (ecmd->tx_coalesce_usecs == 0)
3082 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3083 else {
3084 sky2_write32(hw, STAT_TX_TIMER_INI,
3085 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3086 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3087 }
3088 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3089
3090 if (ecmd->rx_coalesce_usecs == 0)
3091 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3092 else {
3093 sky2_write32(hw, STAT_LEV_TIMER_INI,
3094 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3095 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3096 }
3097 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3098
3099 if (ecmd->rx_coalesce_usecs_irq == 0)
3100 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3101 else {
d28d4870 3102 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3103 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3104 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3105 }
3106 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3107 return 0;
3108}
3109
793b883e
SH		 3110static void sky2_get_ringparam(struct net_device *dev,
3111 struct ethtool_ringparam *ering)
3112{
3113 struct sky2_port *sky2 = netdev_priv(dev);
3114
3115 ering->rx_max_pending = RX_MAX_PENDING;
3116 ering->rx_mini_max_pending = 0;
3117 ering->rx_jumbo_max_pending = 0;
3118 ering->tx_max_pending = TX_RING_SIZE - 1;
3119
3120 ering->rx_pending = sky2->rx_pending;
3121 ering->rx_mini_pending = 0;
3122 ering->rx_jumbo_pending = 0;
3123 ering->tx_pending = sky2->tx_pending;
3124}
3125
3126static int sky2_set_ringparam(struct net_device *dev,
3127 struct ethtool_ringparam *ering)
3128{
3129 struct sky2_port *sky2 = netdev_priv(dev);
3130 int err = 0;
3131
3132 if (ering->rx_pending > RX_MAX_PENDING ||
3133 ering->rx_pending < 8 ||
3134 ering->tx_pending < MAX_SKB_TX_LE ||
3135 ering->tx_pending > TX_RING_SIZE - 1)
3136 return -EINVAL;
3137
3138 if (netif_running(dev))
3139 sky2_down(dev);
3140
3141 sky2->rx_pending = ering->rx_pending;
3142 sky2->tx_pending = ering->tx_pending;
3143
1b537565 3144 if (netif_running(dev)) {
793b883e 3145 err = sky2_up(dev);
1b537565
SH		 3146 if (err)
3147 dev_close(dev);
6ed995bb
SH		 3148 else
3149 sky2_set_multicast(dev);
1b537565 3150 }
793b883e
SH		 3151
3152 return err;
3153}
3154
793b883e
SH		 3155static int sky2_get_regs_len(struct net_device *dev)
3156{
6e4cbb34 3157 return 0x4000;
793b883e
SH		 3158}
3159
3160/*
3161 * Returns copy of control register region
6e4cbb34 3162 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3163 */
3164static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3165 void *p)
3166{
3167 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3168 const void __iomem *io = sky2->hw->regs;
793b883e 3169
6e4cbb34 3170 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3171 regs->version = 1;
6e4cbb34 3172 memset(p, 0, regs->len);
793b883e 3173
6e4cbb34
SH		 3174 memcpy_fromio(p, io, B3_RAM_ADDR);
3175
3176 memcpy_fromio(p + B3_RI_WTO_R1,
3177 io + B3_RI_WTO_R1,
3178 regs->len - B3_RI_WTO_R1);
793b883e 3179}
cd28ab6a 3180
7282d491 3181static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3182 .get_settings = sky2_get_settings,
3183 .set_settings = sky2_set_settings,
3184 .get_drvinfo = sky2_get_drvinfo,
3185 .get_msglevel = sky2_get_msglevel,
3186 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3187 .nway_reset = sky2_nway_reset,
793b883e
SH		 3188 .get_regs_len = sky2_get_regs_len,
3189 .get_regs = sky2_get_regs,
3190 .get_link = ethtool_op_get_link,
3191 .get_sg = ethtool_op_get_sg,
3192 .set_sg = ethtool_op_set_sg,
3193 .get_tx_csum = ethtool_op_get_tx_csum,
3194 .set_tx_csum = ethtool_op_set_tx_csum,
3195 .get_tso = ethtool_op_get_tso,
3196 .set_tso = ethtool_op_set_tso,
3197 .get_rx_csum = sky2_get_rx_csum,
3198 .set_rx_csum = sky2_set_rx_csum,
3199 .get_strings = sky2_get_strings,
fb17358f
SH		 3200 .get_coalesce = sky2_get_coalesce,
3201 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3202 .get_ringparam = sky2_get_ringparam,
3203 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3204 .get_pauseparam = sky2_get_pauseparam,
3205 .set_pauseparam = sky2_set_pauseparam,
793b883e 3206 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3207 .get_stats_count = sky2_get_stats_count,
3208 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3209 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3210};
3211
3212/* Initialize network device */
3213static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3214 unsigned port, int highmem)
3215{
3216 struct sky2_port *sky2;
3217 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3218
3219 if (!dev) {
3220 printk(KERN_ERR "sky2 etherdev alloc failed");
3221 return NULL;
3222 }
3223
3224 SET_MODULE_OWNER(dev);
3225 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3226 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3227 dev->open = sky2_up;
3228 dev->stop = sky2_down;
ef743d33 3229 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3230 dev->hard_start_xmit = sky2_xmit_frame;
3231 dev->get_stats = sky2_get_stats;
3232 dev->set_multicast_list = sky2_set_multicast;
3233 dev->set_mac_address = sky2_set_mac_address;
3234 dev->change_mtu = sky2_change_mtu;
3235 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3236 dev->tx_timeout = sky2_tx_timeout;
3237 dev->watchdog_timeo = TX_WATCHDOG;
3238 if (port == 0)
3239 dev->poll = sky2_poll;
3240 dev->weight = NAPI_WEIGHT;
3241#ifdef CONFIG_NET_POLL_CONTROLLER
3242 dev->poll_controller = sky2_netpoll;
3243#endif
cd28ab6a
SH		 3244
3245 sky2 = netdev_priv(dev);
3246 sky2->netdev = dev;
3247 sky2->hw = hw;
3248 sky2->msg_enable = netif_msg_init(debug, default_msg);
3249
cd28ab6a
SH		 3250 /* Auto speed and flow control */
3251 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3252 sky2->flow_mode = FC_BOTH;
3253
cd28ab6a
SH		 3254 sky2->duplex = -1;
3255 sky2->speed = -1;
3256 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3257 sky2->rx_csum = 1;
75d070c5 3258
e07b1aa8 3259 spin_lock_init(&sky2->phy_lock);
793b883e 3260 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3261 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3262
3263 hw->dev[port] = dev;
3264
3265 sky2->port = port;
3266
5a5b1ea0
SH		 3267 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3268 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3269 if (highmem)
3270 dev->features |= NETIF_F_HIGHDMA;
793b883e 3271 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3272
d1f13708
SH		 3273#ifdef SKY2_VLAN_TAG_USED
3274 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3275 dev->vlan_rx_register = sky2_vlan_rx_register;
3276 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3277#endif
3278
cd28ab6a 3279 /* read the mac address */
793b883e 3280 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3281 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3282
3283 /* device is off until link detection */
3284 netif_carrier_off(dev);
3285 netif_stop_queue(dev);
3286
3287 return dev;
3288}
3289
28bd181a 3290static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3291{
3292 const struct sky2_port *sky2 = netdev_priv(dev);
3293
3294 if (netif_msg_probe(sky2))
3295 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3296 dev->name,
3297 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3298 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3299}
3300
fb2690a9 3301/* Handle software interrupt used during MSI test */
7d12e780 3302static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3303{
3304 struct sky2_hw *hw = dev_id;
3305 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3306
3307 if (status == 0)
3308 return IRQ_NONE;
3309
3310 if (status & Y2_IS_IRQ_SW) {
3311 hw->msi_detected = 1;
3312 wake_up(&hw->msi_wait);
3313 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3314 }
3315 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3316
3317 return IRQ_HANDLED;
3318}
3319
3320/* Test interrupt path by forcing a a software IRQ */
3321static int __devinit sky2_test_msi(struct sky2_hw *hw)
3322{
3323 struct pci_dev *pdev = hw->pdev;
3324 int err;
3325
bb507fe1
SH		 3326 init_waitqueue_head (&hw->msi_wait);
3327
fb2690a9
SH		 3328 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3329
1fb9df5d 3330 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
fb2690a9
SH		 3331 if (err) {
3332 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3333 pci_name(pdev), pdev->irq);
3334 return err;
3335 }
3336
fb2690a9 3337 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3338 sky2_read8(hw, B0_CTST);
fb2690a9
SH		 3339
3340 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3341
3342 if (!hw->msi_detected) {
3343 /* MSI test failed, go back to INTx mode */
2bffc23a
SH		 3344 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3345 "switching to INTx mode.\n",
fb2690a9
SH		 3346 pci_name(pdev));
3347
3348 err = -EOPNOTSUPP;
3349 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3350 }
3351
3352 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3353 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3354
3355 free_irq(pdev->irq, hw);
3356
3357 return err;
3358}
3359
cd28ab6a
SH		 3360static int __devinit sky2_probe(struct pci_dev *pdev,
3361 const struct pci_device_id *ent)
3362{
793b883e 3363 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3364 struct sky2_hw *hw;
5afa0a9c 3365 int err, pm_cap, using_dac = 0;
cd28ab6a 3366
793b883e
SH		 3367 err = pci_enable_device(pdev);
3368 if (err) {
cd28ab6a
SH		 3369 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3370 pci_name(pdev));
3371 goto err_out;
3372 }
3373
793b883e
SH		 3374 err = pci_request_regions(pdev, DRV_NAME);
3375 if (err) {
cd28ab6a
SH		 3376 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3377 pci_name(pdev));
793b883e 3378 goto err_out;
cd28ab6a
SH		 3379 }
3380
3381 pci_set_master(pdev);
3382
5afa0a9c
SH		 3383 /* Find power-management capability. */
3384 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3385 if (pm_cap == 0) {
3386 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3387 "aborting.\n");
3388 err = -EIO;
3389 goto err_out_free_regions;
3390 }
3391
d1f3d4dd
SH		 3392 if (sizeof(dma_addr_t) > sizeof(u32) &&
3393 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3394 using_dac = 1;
3395 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3396 if (err < 0) {
3397 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3398 "for consistent allocations\n", pci_name(pdev));
3399 goto err_out_free_regions;
3400 }
cd28ab6a 3401
d1f3d4dd 3402 } else {
cd28ab6a
SH		 3403 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3404 if (err) {
3405 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3406 pci_name(pdev));
3407 goto err_out_free_regions;
3408 }
3409 }
d1f3d4dd 3410
cd28ab6a 3411 err = -ENOMEM;
6aad85d6 3412 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3413 if (!hw) {
3414 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3415 pci_name(pdev));
3416 goto err_out_free_regions;
3417 }
3418
cd28ab6a 3419 hw->pdev = pdev;
cd28ab6a
SH		 3420
3421 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3422 if (!hw->regs) {
3423 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3424 pci_name(pdev));
3425 goto err_out_free_hw;
3426 }
5afa0a9c 3427 hw->pm_cap = pm_cap;
cd28ab6a 3428
56a645cc 3429#ifdef __BIG_ENDIAN
f65b138c
SH		 3430 /* The sk98lin vendor driver uses hardware byte swapping but
3431 * this driver uses software swapping.
3432 */
56a645cc
SH		 3433 {
3434 u32 reg;
56a645cc 3435 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3436 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3437 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3438 }
3439#endif
3440
08c06d8a
SH		 3441 /* ring for status responses */
3442 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3443 &hw->st_dma);
3444 if (!hw->st_le)
3445 goto err_out_iounmap;
3446
cd28ab6a
SH		 3447 err = sky2_reset(hw);
3448 if (err)
793b883e 3449 goto err_out_iounmap;
cd28ab6a 3450
7c7459d1
GKH		 3451 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3452 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3453 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3454 hw->chip_id, hw->chip_rev);
cd28ab6a 3455
793b883e
SH		 3456 dev = sky2_init_netdev(hw, 0, using_dac);
3457 if (!dev)
cd28ab6a
SH		 3458 goto err_out_free_pci;
3459
9fa1b1f3
SH		 3460 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3461 err = sky2_test_msi(hw);
3462 if (err == -EOPNOTSUPP)
3463 pci_disable_msi(pdev);
3464 else if (err)
3465 goto err_out_free_netdev;
3466 }
3467
793b883e
SH		 3468 err = register_netdev(dev);
3469 if (err) {
cd28ab6a
SH		 3470 printk(KERN_ERR PFX "%s: cannot register net device\n",
3471 pci_name(pdev));
3472 goto err_out_free_netdev;
3473 }
3474
9fa1b1f3
SH		 3475 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, dev->name, hw);
3476 if (err) {
3477 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3478 pci_name(pdev), pdev->irq);
3479 goto err_out_unregister;
3480 }
3481 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3482
cd28ab6a
SH		 3483 sky2_show_addr(dev);
3484
3485 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3486 if (register_netdev(dev1) == 0)
3487 sky2_show_addr(dev1);
3488 else {
3489 /* Failure to register second port need not be fatal */
793b883e
SH		 3490 printk(KERN_WARNING PFX
3491 "register of second port failed\n");
cd28ab6a
SH		 3492 hw->dev[1] = NULL;
3493 free_netdev(dev1);
3494 }
3495 }
3496
01bd7564 3497 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3498 sky2_idle_start(hw);
d27ed387 3499
793b883e
SH		 3500 pci_set_drvdata(pdev, hw);
3501
cd28ab6a
SH		 3502 return 0;
3503
793b883e 3504err_out_unregister:
fb2690a9 3505 pci_disable_msi(pdev);
793b883e 3506 unregister_netdev(dev);
cd28ab6a
SH		 3507err_out_free_netdev:
3508 free_netdev(dev);
cd28ab6a 3509err_out_free_pci:
793b883e 3510 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3511 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3512err_out_iounmap:
3513 iounmap(hw->regs);
3514err_out_free_hw:
3515 kfree(hw);
3516err_out_free_regions:
3517 pci_release_regions(pdev);
cd28ab6a 3518 pci_disable_device(pdev);
cd28ab6a
SH		 3519err_out:
3520 return err;
3521}
3522
3523static void __devexit sky2_remove(struct pci_dev *pdev)
3524{
793b883e 3525 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3526 struct net_device *dev0, *dev1;
3527
793b883e 3528 if (!hw)
cd28ab6a
SH		 3529 return;
3530
d27ed387
SH		 3531 del_timer_sync(&hw->idle_timer);
3532
3533 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3534 synchronize_irq(hw->pdev->irq);
3535
cd28ab6a 3536 dev0 = hw->dev[0];
793b883e
SH		 3537 dev1 = hw->dev[1];
3538 if (dev1)
3539 unregister_netdev(dev1);
cd28ab6a
SH		 3540 unregister_netdev(dev0);
3541
5afa0a9c 3542 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3543 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3544 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3545 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3546
3547 free_irq(pdev->irq, hw);
fb2690a9 3548 pci_disable_msi(pdev);
793b883e 3549 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3550 pci_release_regions(pdev);
3551 pci_disable_device(pdev);
793b883e 3552
cd28ab6a
SH		 3553 if (dev1)
3554 free_netdev(dev1);
3555 free_netdev(dev0);
3556 iounmap(hw->regs);
3557 kfree(hw);
5afa0a9c 3558
cd28ab6a
SH		 3559 pci_set_drvdata(pdev, NULL);
3560}
3561
3562#ifdef CONFIG_PM
3563static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3564{
793b883e 3565 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3566 int i;
2ccc99b7
SH		 3567 pci_power_t pstate = pci_choose_state(pdev, state);
3568
3569 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3570 return -EINVAL;
cd28ab6a 3571
eb35cf60 3572 del_timer_sync(&hw->idle_timer);
6a5706b9 3573 netif_poll_disable(hw->dev[0]);
eb35cf60 3574
f05267e7 3575 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3576 struct net_device *dev = hw->dev[i];
3577
6a5706b9 3578 if (netif_running(dev)) {
5afa0a9c 3579 sky2_down(dev);
cd28ab6a 3580 netif_device_detach(dev);
cd28ab6a
SH		 3581 }
3582 }
3583
8ab8fca2 3584 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3585 pci_save_state(pdev);
2ccc99b7
SH		 3586 sky2_set_power_state(hw, pstate);
3587 return 0;
cd28ab6a
SH		 3588}
3589
3590static int sky2_resume(struct pci_dev *pdev)
3591{
793b883e 3592 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3593 int i, err;
cd28ab6a 3594
cd28ab6a
SH		 3595 pci_restore_state(pdev);
3596 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3597 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3598
08c06d8a
SH		 3599 err = sky2_reset(hw);
3600 if (err)
3601 goto out;
cd28ab6a 3602
8ab8fca2
SH		 3603 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3604
f05267e7 3605 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3606 struct net_device *dev = hw->dev[i];
6a5706b9 3607 if (netif_running(dev)) {
08c06d8a 3608 netif_device_attach(dev);
88d11360 3609
08c06d8a
SH		 3610 err = sky2_up(dev);
3611 if (err) {
3612 printk(KERN_ERR PFX "%s: could not up: %d\n",
3613 dev->name, err);
3614 dev_close(dev);
eb35cf60 3615 goto out;
5afa0a9c 3616 }
cd28ab6a
SH		 3617 }
3618 }
eb35cf60 3619
6a5706b9 3620 netif_poll_enable(hw->dev[0]);
eb35cf60 3621 sky2_idle_start(hw);
08c06d8a
SH		 3622out:
3623 return err;
cd28ab6a
SH		 3624}
3625#endif
3626
3627static struct pci_driver sky2_driver = {
793b883e
SH		 3628 .name = DRV_NAME,
3629 .id_table = sky2_id_table,
3630 .probe = sky2_probe,
3631 .remove = __devexit_p(sky2_remove),
cd28ab6a 3632#ifdef CONFIG_PM
793b883e
SH		 3633 .suspend = sky2_suspend,
3634 .resume = sky2_resume,
cd28ab6a
SH		 3635#endif
3636};
3637
3638static int __init sky2_init_module(void)
3639{
50241c4c 3640 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3641}
3642
3643static void __exit sky2_cleanup_module(void)
3644{
3645 pci_unregister_driver(&sky2_driver);
3646}
3647
3648module_init(sky2_init_module);
3649module_exit(sky2_cleanup_module);
3650
3651MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3652MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3653MODULE_LICENSE("GPL");
5f4f9dc1 3654MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree