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[NETXEN]: Fix ->poll() done logic.
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
1e354787 54#define DRV_VERSION "1.20"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
cd28ab6a
SH		 138 { 0 }
139};
793b883e 140
cd28ab6a
SH		 141MODULE_DEVICE_TABLE(pci, sky2_id_table);
142
143/* Avoid conditionals by using array */
144static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
145static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 146static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 147
92f965e8
SH		 148/* This driver supports yukon2 chipset only */
149static const char *yukon2_name[] = {
150 "XL", /* 0xb3 */
151 "EC Ultra", /* 0xb4 */
93745494 152 "Extreme", /* 0xb5 */
92f965e8
SH		 153 "EC", /* 0xb6 */
154 "FE", /* 0xb7 */
05745c4a 155 "FE+", /* 0xb8 */
793b883e
SH		 156};
157
d1b139c0
SH		 158static void sky2_set_multicast(struct net_device *dev);
159
af043aa5 160/* Access to PHY via serial interconnect */
ef743d33 161static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 162{
163 int i;
164
165 gma_write16(hw, port, GM_SMI_DATA, val);
166 gma_write16(hw, port, GM_SMI_CTRL,
167 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
168
169 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 170 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
171 if (ctrl == 0xffff)
172 goto io_error;
173
174 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 175 return 0;
af043aa5
SH		 176
177 udelay(10);
cd28ab6a 178 }
ef743d33 179
af043aa5 180 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 181 return -ETIMEDOUT;
af043aa5
SH		 182
183io_error:
184 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
185 return -EIO;
cd28ab6a
SH		 186}
187
ef743d33 188static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 189{
190 int i;
191
793b883e 192 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 193 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
194
195 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 196 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
197 if (ctrl == 0xffff)
198 goto io_error;
199
200 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 201 *val = gma_read16(hw, port, GM_SMI_DATA);
202 return 0;
203 }
204
af043aa5 205 udelay(10);
cd28ab6a
SH		 206 }
207
af043aa5 208 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 209 return -ETIMEDOUT;
af043aa5
SH		 210io_error:
211 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
212 return -EIO;
ef743d33
SH		 213}
214
af043aa5 215static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 216{
217 u16 v;
af043aa5 218 __gm_phy_read(hw, port, reg, &v);
ef743d33 219 return v;
cd28ab6a
SH		 220}
221
5afa0a9c 222
ae306cca
SH		 223static void sky2_power_on(struct sky2_hw *hw)
224{
225 /* switch power to VCC (WA for VAUX problem) */
226 sky2_write8(hw, B0_POWER_CTRL,
227 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 228
ae306cca
SH		 229 /* disable Core Clock Division, */
230 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 231
ae306cca
SH		 232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
233 /* enable bits are inverted */
234 sky2_write8(hw, B2_Y2_CLK_GATE,
235 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
236 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
237 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
238 else
239 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 240
ea76e635 241 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 242 u32 reg;
5afa0a9c 243
b32f40c4 244 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 245
b32f40c4 246 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 247 /* set all bits to 0 except bits 15..12 and 8 */
248 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 249 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 250
b32f40c4 251 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 252 /* set all bits to 0 except bits 28 & 27 */
253 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 254 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 255
b32f40c4 256 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 257
258 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
259 reg = sky2_read32(hw, B2_GP_IO);
260 reg |= GLB_GPIO_STAT_RACE_DIS;
261 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 262
263 sky2_read32(hw, B2_GP_IO);
5afa0a9c 264 }
ae306cca 265}
5afa0a9c 266
ae306cca
SH		 267static void sky2_power_aux(struct sky2_hw *hw)
268{
269 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
270 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
271 else
272 /* enable bits are inverted */
273 sky2_write8(hw, B2_Y2_CLK_GATE,
274 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
275 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
276 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
277
278 /* switch power to VAUX */
279 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
280 sky2_write8(hw, B0_POWER_CTRL,
281 (PC_VAUX_ENA | PC_VCC_ENA |
282 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 283}
284
d3bcfbeb 285static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 286{
287 u16 reg;
288
289 /* disable all GMAC IRQ's */
290 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 291
cd28ab6a
SH		 292 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
293 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
296
297 reg = gma_read16(hw, port, GM_RX_CTRL);
298 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
299 gma_write16(hw, port, GM_RX_CTRL, reg);
300}
301
16ad91e1
SH		 302/* flow control to advertise bits */
303static const u16 copper_fc_adv[] = {
304 [FC_NONE] = 0,
305 [FC_TX] = PHY_M_AN_ASP,
306 [FC_RX] = PHY_M_AN_PC,
307 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
308};
309
310/* flow control to advertise bits when using 1000BaseX */
311static const u16 fiber_fc_adv[] = {
df3fe1f3 312 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 313 [FC_TX] = PHY_M_P_ASYM_MD_X,
314 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 315 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 316};
317
318/* flow control to GMA disable bits */
319static const u16 gm_fc_disable[] = {
320 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
321 [FC_TX] = GM_GPCR_FC_RX_DIS,
322 [FC_RX] = GM_GPCR_FC_TX_DIS,
323 [FC_BOTH] = 0,
324};
325
326
cd28ab6a
SH		 327static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
328{
329 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 330 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 331
ea76e635
SH		 332 if (sky2->autoneg == AUTONEG_ENABLE &&
333 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 334 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
335
336 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 337 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 338 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
339
53419c68 340 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 341 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 342 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 343 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
344 else
53419c68
SH		 345 /* set master & slave downshift counter to 1x */
346 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 347
348 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
349 }
350
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 352 if (sky2_is_copper(hw)) {
05745c4a 353 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 354 /* enable automatic crossover */
355 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 356
357 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
358 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
359 u16 spec;
360
361 /* Enable Class A driver for FE+ A0 */
362 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
363 spec |= PHY_M_FESC_SEL_CL_A;
364 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
365 }
cd28ab6a
SH		 366 } else {
367 /* disable energy detect */
368 ctrl &= ~PHY_M_PC_EN_DET_MSK;
369
370 /* enable automatic crossover */
371 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
372
53419c68 373 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 374 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 375 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 376 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 377 ctrl &= ~PHY_M_PC_DSC_MSK;
378 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
379 }
380 }
cd28ab6a
SH		 381 } else {
382 /* workaround for deviation #4.88 (CRC errors) */
383 /* disable Automatic Crossover */
384
385 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 386 }
cd28ab6a 387
b89165f2
SH		 388 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
389
390 /* special setup for PHY 88E1112 Fiber */
ea76e635 391 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 392 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 393
b89165f2
SH		 394 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
396 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
397 ctrl &= ~PHY_M_MAC_MD_MSK;
398 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
399 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
400
401 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 402 /* select page 1 to access Fiber registers */
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 404
405 /* for SFP-module set SIGDET polarity to low */
406 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
407 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 408 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 409 }
b89165f2
SH		 410
411 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 412 }
413
7800fddc 414 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 415 ct1000 = 0;
416 adv = PHY_AN_CSMA;
2eaba1a2 417 reg = 0;
cd28ab6a
SH		 418
419 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 420 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 421 if (sky2->advertising & ADVERTISED_1000baseT_Full)
422 ct1000 |= PHY_M_1000C_AFD;
423 if (sky2->advertising & ADVERTISED_1000baseT_Half)
424 ct1000 |= PHY_M_1000C_AHD;
425 if (sky2->advertising & ADVERTISED_100baseT_Full)
426 adv |= PHY_M_AN_100_FD;
427 if (sky2->advertising & ADVERTISED_100baseT_Half)
428 adv |= PHY_M_AN_100_HD;
429 if (sky2->advertising & ADVERTISED_10baseT_Full)
430 adv |= PHY_M_AN_10_FD;
431 if (sky2->advertising & ADVERTISED_10baseT_Half)
432 adv |= PHY_M_AN_10_HD;
709c6e7b 433
16ad91e1 434 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 435 } else { /* special defines for FIBER (88E1040S only) */
436 if (sky2->advertising & ADVERTISED_1000baseT_Full)
437 adv |= PHY_M_AN_1000X_AFD;
438 if (sky2->advertising & ADVERTISED_1000baseT_Half)
439 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 440
16ad91e1 441 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 442 }
cd28ab6a
SH		 443
444 /* Restart Auto-negotiation */
445 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
446 } else {
447 /* forced speed/duplex settings */
448 ct1000 = PHY_M_1000C_MSE;
449
2eaba1a2
SH		 450 /* Disable auto update for duplex flow control and speed */
451 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 452
453 switch (sky2->speed) {
454 case SPEED_1000:
455 ctrl |= PHY_CT_SP1000;
2eaba1a2 456 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 457 break;
458 case SPEED_100:
459 ctrl |= PHY_CT_SP100;
2eaba1a2 460 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 461 break;
462 }
463
2eaba1a2
SH		 464 if (sky2->duplex == DUPLEX_FULL) {
465 reg |= GM_GPCR_DUP_FULL;
466 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 467 } else if (sky2->speed < SPEED_1000)
468 sky2->flow_mode = FC_NONE;
2eaba1a2 469
2eaba1a2 470
16ad91e1 471 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 472
473 /* Forward pause packets to GMAC? */
16ad91e1 474 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 475 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
476 else
477 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 478 }
479
2eaba1a2
SH		 480 gma_write16(hw, port, GM_GP_CTRL, reg);
481
05745c4a 482 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 483 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
484
485 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
486 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
487
488 /* Setup Phy LED's */
489 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
490 ledover = 0;
491
492 switch (hw->chip_id) {
493 case CHIP_ID_YUKON_FE:
494 /* on 88E3082 these bits are at 11..9 (shifted left) */
495 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
496
497 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
498
499 /* delete ACT LED control bits */
500 ctrl &= ~PHY_M_FELP_LED1_MSK;
501 /* change ACT LED control to blink mode */
502 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
503 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
504 break;
505
05745c4a
SH		 506 case CHIP_ID_YUKON_FE_P:
507 /* Enable Link Partner Next Page */
508 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
509 ctrl |= PHY_M_PC_ENA_LIP_NP;
510
511 /* disable Energy Detect and enable scrambler */
512 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
513 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
514
515 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
516 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
517 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
518 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
519
520 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
521 break;
522
cd28ab6a 523 case CHIP_ID_YUKON_XL:
793b883e 524 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 525
526 /* select page 3 to access LED control register */
527 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
528
529 /* set LED Function Control register */
ed6d32c7
SH		 530 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
531 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
532 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
533 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
534 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 535
536 /* set Polarity Control register */
537 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 538 (PHY_M_POLC_LS1_P_MIX(4) |
539 PHY_M_POLC_IS0_P_MIX(4) |
540 PHY_M_POLC_LOS_CTRL(2) |
541 PHY_M_POLC_INIT_CTRL(2) |
542 PHY_M_POLC_STA1_CTRL(2) |
543 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 544
545 /* restore page register */
793b883e 546 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 547 break;
93745494 548
ed6d32c7 549 case CHIP_ID_YUKON_EC_U:
93745494 550 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 551 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
552
553 /* select page 3 to access LED control register */
554 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
555
556 /* set LED Function Control register */
557 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
558 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
559 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
560 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
561 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
562
563 /* set Blink Rate in LED Timer Control Register */
564 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
565 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
566 /* restore page register */
567 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
568 break;
cd28ab6a
SH		 569
570 default:
571 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
572 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
573 /* turn off the Rx LED (LED_RX) */
0efdf262 574 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 575 }
576
9467a8fc
SH		 577 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
578 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 579 /* apply fixes in PHY AFE */
ed6d32c7
SH		 580 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
581
977bdf06 582 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 583 gm_phy_write(hw, port, 0x18, 0xaa99);
584 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 585
977bdf06 586 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 587 gm_phy_write(hw, port, 0x18, 0xa204);
588 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 589
590 /* set page register to 0 */
9467a8fc 591 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 592 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
593 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
594 /* apply workaround for integrated resistors calibration */
595 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
596 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 597 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 598 /* no effect on Yukon-XL */
977bdf06 599 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 600
977bdf06
SH		 601 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
602 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 603 ledover |= PHY_M_LED_MO_100;
977bdf06 604 }
cd28ab6a 605
977bdf06
SH		 606 if (ledover)
607 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
608
609 }
2eaba1a2 610
d571b694 611 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 612 if (sky2->autoneg == AUTONEG_ENABLE)
613 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
614 else
615 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
616}
617
d3bcfbeb
SH		 618static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
619{
620 u32 reg1;
ff35164e
SH		 621 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
622 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
d3bcfbeb 623
b32f40c4 624 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
ff35164e 625 /* Turn on/off phy power saving */
d3bcfbeb 626 if (onoff)
d3bcfbeb
SH		 627 reg1 &= ~phy_power[port];
628 else
629 reg1 |= phy_power[port];
630
ff35164e
SH		 631 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
632 reg1 |= coma_mode[port];
633
b32f40c4
SH		 634 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
635 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
167f53d0 636
d3bcfbeb
SH		 637 udelay(100);
638}
639
1b537565
SH		 640/* Force a renegotiation */
641static void sky2_phy_reinit(struct sky2_port *sky2)
642{
e07b1aa8 643 spin_lock_bh(&sky2->phy_lock);
1b537565 644 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 645 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 646}
647
e3173832
SH		 648/* Put device in state to listen for Wake On Lan */
649static void sky2_wol_init(struct sky2_port *sky2)
650{
651 struct sky2_hw *hw = sky2->hw;
652 unsigned port = sky2->port;
653 enum flow_control save_mode;
654 u16 ctrl;
655 u32 reg1;
656
657 /* Bring hardware out of reset */
658 sky2_write16(hw, B0_CTST, CS_RST_CLR);
659 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
660
661 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
662 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
663
664 /* Force to 10/100
665 * sky2_reset will re-enable on resume
666 */
667 save_mode = sky2->flow_mode;
668 ctrl = sky2->advertising;
669
670 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
671 sky2->flow_mode = FC_NONE;
672 sky2_phy_power(hw, port, 1);
673 sky2_phy_reinit(sky2);
674
675 sky2->flow_mode = save_mode;
676 sky2->advertising = ctrl;
677
678 /* Set GMAC to no flow control and auto update for speed/duplex */
679 gma_write16(hw, port, GM_GP_CTRL,
680 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
681 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
682
683 /* Set WOL address */
684 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
685 sky2->netdev->dev_addr, ETH_ALEN);
686
687 /* Turn on appropriate WOL control bits */
688 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
689 ctrl = 0;
690 if (sky2->wol & WAKE_PHY)
691 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
692 else
693 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
694
695 if (sky2->wol & WAKE_MAGIC)
696 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
697 else
698 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
699
700 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
701 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
702
703 /* Turn on legacy PCI-Express PME mode */
b32f40c4 704 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 705 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 706 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 707
708 /* block receiver */
709 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
710
711}
712
69161611
SH		 713static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
714{
05745c4a
SH		 715 struct net_device *dev = hw->dev[port];
716
717 if (dev->mtu <= ETH_DATA_LEN)
69161611 718 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
05745c4a
SH		 719 TX_JUMBO_DIS | TX_STFW_ENA);
720
721 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
722 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
723 TX_STFW_ENA | TX_JUMBO_ENA);
724 else {
725 /* set Tx GMAC FIFO Almost Empty Threshold */
726 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
727 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 728
05745c4a
SH		 729 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
730 TX_JUMBO_ENA | TX_STFW_DIS);
69161611 731
05745c4a
SH		 732 /* Can't do offload because of lack of store/forward */
733 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
69161611
SH		 734 }
735}
736
cd28ab6a
SH		 737static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
738{
739 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
740 u16 reg;
25cccecc 741 u32 rx_reg;
cd28ab6a
SH		 742 int i;
743 const u8 *addr = hw->dev[port]->dev_addr;
744
f350339c
SH		 745 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
746 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 747
748 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
749
793b883e 750 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 751 /* WA DEV_472 -- looks like crossed wires on port 2 */
752 /* clear GMAC 1 Control reset */
753 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
754 do {
755 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
756 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
757 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
758 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
759 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
760 }
761
793b883e 762 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 763
2eaba1a2
SH		 764 /* Enable Transmit FIFO Underrun */
765 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
766
e07b1aa8 767 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 768 sky2_phy_init(hw, port);
e07b1aa8 769 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 770
771 /* MIB clear */
772 reg = gma_read16(hw, port, GM_PHY_ADDR);
773 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
774
43f2f104
SH		 775 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
776 gma_read16(hw, port, i);
cd28ab6a
SH		 777 gma_write16(hw, port, GM_PHY_ADDR, reg);
778
779 /* transmit control */
780 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
781
782 /* receive control reg: unicast + multicast + no FCS */
783 gma_write16(hw, port, GM_RX_CTRL,
793b883e 784 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 785
786 /* transmit flow control */
787 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
788
789 /* transmit parameter */
790 gma_write16(hw, port, GM_TX_PARAM,
791 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
792 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
793 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
794 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
795
796 /* serial mode register */
797 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 798 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 799
6b1a3aef 800 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 801 reg |= GM_SMOD_JUMBO_ENA;
802
803 gma_write16(hw, port, GM_SERIAL_MODE, reg);
804
cd28ab6a
SH		 805 /* virtual address for data */
806 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
807
793b883e
SH		 808 /* physical address: used for pause frames */
809 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
810
811 /* ignore counter overflows */
cd28ab6a
SH		 812 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
813 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
814 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
815
816 /* Configure Rx MAC FIFO */
817 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 818 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 819 if (hw->chip_id == CHIP_ID_YUKON_EX ||
820 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 821 rx_reg |= GMF_RX_OVER_ON;
69161611 822
25cccecc 823 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 824
798fdd07
SH		 825 if (hw->chip_id == CHIP_ID_YUKON_XL) {
826 /* Hardware errata - clear flush mask */
827 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
828 } else {
829 /* Flush Rx MAC FIFO on any flow control or error */
830 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
831 }
cd28ab6a 832
8df9a876 833 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 834 reg = RX_GMF_FL_THR_DEF + 1;
835 /* Another magic mystery workaround from sk98lin */
836 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
837 hw->chip_rev == CHIP_REV_YU_FE2_A0)
838 reg = 0x178;
839 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 840
841 /* Configure Tx MAC FIFO */
842 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
843 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 844
e0c28116
SH		 845 /* On chips without ram buffer, pause is controled by MAC level */
846 if (sky2_read8(hw, B2_E_0) == 0) {
8df9a876 847 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 848 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 849
69161611 850 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 851 }
852
e970d1f8
SH		 853 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
854 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
855 /* disable dynamic watermark */
856 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
857 reg &= ~TX_DYN_WM_ENA;
858 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
859 }
cd28ab6a
SH		 860}
861
67712901
SH		 862/* Assign Ram Buffer allocation to queue */
863static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 864{
67712901
SH		 865 u32 end;
866
867 /* convert from K bytes to qwords used for hw register */
868 start *= 1024/8;
869 space *= 1024/8;
870 end = start + space - 1;
793b883e 871
cd28ab6a
SH		 872 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
873 sky2_write32(hw, RB_ADDR(q, RB_START), start);
874 sky2_write32(hw, RB_ADDR(q, RB_END), end);
875 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
876 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
877
878 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 879 u32 tp = space - space/4;
793b883e 880
1c28f6ba
SH		 881 /* On receive queue's set the thresholds
882 * give receiver priority when > 3/4 full
883 * send pause when down to 2K
884 */
885 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
886 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 887
1c28f6ba
SH		 888 tp = space - 2048/8;
889 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
890 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 891 } else {
892 /* Enable store & forward on Tx queue's because
893 * Tx FIFO is only 1K on Yukon
894 */
895 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
896 }
897
898 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 899 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 900}
901
cd28ab6a 902/* Setup Bus Memory Interface */
af4ed7e6 903static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 904{
905 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
906 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
907 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 908 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 909}
910
cd28ab6a
SH		 911/* Setup prefetch unit registers. This is the interface between
912 * hardware and driver list elements
913 */
8cc048e3 914static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 915 u64 addr, u32 last)
916{
cd28ab6a
SH		 917 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
918 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
919 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
920 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
921 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
922 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 923
924 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 925}
926
793b883e
SH		 927static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
928{
929 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
930
cb5d9547 931 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 932 le->ctrl = 0;
793b883e
SH		 933 return le;
934}
cd28ab6a 935
88f5f0ca
SH		 936static void tx_init(struct sky2_port *sky2)
937{
938 struct sky2_tx_le *le;
939
940 sky2->tx_prod = sky2->tx_cons = 0;
941 sky2->tx_tcpsum = 0;
942 sky2->tx_last_mss = 0;
943
944 le = get_tx_le(sky2);
945 le->addr = 0;
946 le->opcode = OP_ADDR64 | HW_OWNER;
947 sky2->tx_addr64 = 0;
948}
949
291ea614
SH		 950static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
951 struct sky2_tx_le *le)
952{
953 return sky2->tx_ring + (le - sky2->tx_le);
954}
955
290d4de5
SH		 956/* Update chip's next pointer */
957static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 958{
50432cb5 959 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 960 wmb();
50432cb5
SH		 961 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
962
963 /* Synchronize I/O on since next processor may write to tail */
964 mmiowb();
cd28ab6a
SH		 965}
966
793b883e 967
cd28ab6a
SH		 968static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
969{
970 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 971 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 972 le->ctrl = 0;
cd28ab6a
SH		 973 return le;
974}
975
14d0263f
SH		 976/* Build description to hardware for one receive segment */
977static void sky2_rx_add(struct sky2_port *sky2, u8 op,
978 dma_addr_t map, unsigned len)
cd28ab6a
SH		 979{
980 struct sky2_rx_le *le;
36eb0c71 981 u32 hi = upper_32_bits(map);
cd28ab6a 982
793b883e 983 if (sky2->rx_addr64 != hi) {
cd28ab6a 984 le = sky2_next_rx(sky2);
793b883e 985 le->addr = cpu_to_le32(hi);
cd28ab6a 986 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 987 sky2->rx_addr64 = upper_32_bits(map + len);
cd28ab6a 988 }
793b883e 989
cd28ab6a 990 le = sky2_next_rx(sky2);
734d1868
SH		 991 le->addr = cpu_to_le32((u32) map);
992 le->length = cpu_to_le16(len);
14d0263f 993 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 994}
995
14d0263f
SH		 996/* Build description to hardware for one possibly fragmented skb */
997static void sky2_rx_submit(struct sky2_port *sky2,
998 const struct rx_ring_info *re)
999{
1000 int i;
1001
1002 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1003
1004 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1005 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1006}
1007
1008
1009static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1010 unsigned size)
1011{
1012 struct sk_buff *skb = re->skb;
1013 int i;
1014
1015 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1016 pci_unmap_len_set(re, data_size, size);
1017
1018 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1019 re->frag_addr[i] = pci_map_page(pdev,
1020 skb_shinfo(skb)->frags[i].page,
1021 skb_shinfo(skb)->frags[i].page_offset,
1022 skb_shinfo(skb)->frags[i].size,
1023 PCI_DMA_FROMDEVICE);
1024}
1025
1026static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1027{
1028 struct sk_buff *skb = re->skb;
1029 int i;
1030
1031 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1032 PCI_DMA_FROMDEVICE);
1033
1034 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1035 pci_unmap_page(pdev, re->frag_addr[i],
1036 skb_shinfo(skb)->frags[i].size,
1037 PCI_DMA_FROMDEVICE);
1038}
793b883e 1039
cd28ab6a
SH		 1040/* Tell chip where to start receive checksum.
1041 * Actually has two checksums, but set both same to avoid possible byte
1042 * order problems.
1043 */
793b883e 1044static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1045{
ea76e635 1046 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1047
ea76e635
SH		 1048 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1049 le->ctrl = 0;
1050 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1051
ea76e635
SH		 1052 sky2_write32(sky2->hw,
1053 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1054 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1055}
1056
6b1a3aef
SH		 1057/*
1058 * The RX Stop command will not work for Yukon-2 if the BMU does not
1059 * reach the end of packet and since we can't make sure that we have
1060 * incoming data, we must reset the BMU while it is not doing a DMA
1061 * transfer. Since it is possible that the RX path is still active,
1062 * the RX RAM buffer will be stopped first, so any possible incoming
1063 * data will not trigger a DMA. After the RAM buffer is stopped, the
1064 * BMU is polled until any DMA in progress is ended and only then it
1065 * will be reset.
1066 */
1067static void sky2_rx_stop(struct sky2_port *sky2)
1068{
1069 struct sky2_hw *hw = sky2->hw;
1070 unsigned rxq = rxqaddr[sky2->port];
1071 int i;
1072
1073 /* disable the RAM Buffer receive queue */
1074 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1075
1076 for (i = 0; i < 0xffff; i++)
1077 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1078 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1079 goto stopped;
1080
1081 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1082 sky2->netdev->name);
1083stopped:
1084 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1085
1086 /* reset the Rx prefetch unit */
1087 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1088 mmiowb();
6b1a3aef 1089}
793b883e 1090
d571b694 1091/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1092static void sky2_rx_clean(struct sky2_port *sky2)
1093{
1094 unsigned i;
1095
1096 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1097 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1098 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1099
1100 if (re->skb) {
14d0263f 1101 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1102 kfree_skb(re->skb);
1103 re->skb = NULL;
1104 }
1105 }
1106}
1107
ef743d33
SH		 1108/* Basic MII support */
1109static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1110{
1111 struct mii_ioctl_data *data = if_mii(ifr);
1112 struct sky2_port *sky2 = netdev_priv(dev);
1113 struct sky2_hw *hw = sky2->hw;
1114 int err = -EOPNOTSUPP;
1115
1116 if (!netif_running(dev))
1117 return -ENODEV; /* Phy still in reset */
1118
d89e1343 1119 switch (cmd) {
ef743d33
SH		 1120 case SIOCGMIIPHY:
1121 data->phy_id = PHY_ADDR_MARV;
1122
1123 /* fallthru */
1124 case SIOCGMIIREG: {
1125 u16 val = 0;
91c86df5 1126
e07b1aa8 1127 spin_lock_bh(&sky2->phy_lock);
ef743d33 1128 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1129 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1130
ef743d33
SH		 1131 data->val_out = val;
1132 break;
1133 }
1134
1135 case SIOCSMIIREG:
1136 if (!capable(CAP_NET_ADMIN))
1137 return -EPERM;
1138
e07b1aa8 1139 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1140 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1141 data->val_in);
e07b1aa8 1142 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1143 break;
1144 }
1145 return err;
1146}
1147
d1f13708
SH		 1148#ifdef SKY2_VLAN_TAG_USED
1149static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1150{
1151 struct sky2_port *sky2 = netdev_priv(dev);
1152 struct sky2_hw *hw = sky2->hw;
1153 u16 port = sky2->port;
d1f13708 1154
2bb8c262 1155 netif_tx_lock_bh(dev);
bea3348e 1156 napi_disable(&hw->napi);
d1f13708 1157
d1f13708 1158 sky2->vlgrp = grp;
3d4e66f5
SH		 1159 if (grp) {
1160 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1161 RX_VLAN_STRIP_ON);
1162 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1163 TX_VLAN_TAG_ON);
1164 } else {
1165 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1166 RX_VLAN_STRIP_OFF);
1167 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1168 TX_VLAN_TAG_OFF);
1169 }
d1f13708 1170
bea3348e 1171 napi_enable(&hw->napi);
2bb8c262 1172 netif_tx_unlock_bh(dev);
d1f13708
SH		 1173}
1174#endif
1175
82788c7a 1176/*
14d0263f
SH		 1177 * Allocate an skb for receiving. If the MTU is large enough
1178 * make the skb non-linear with a fragment list of pages.
1179 *
82788c7a
SH		 1180 * It appears the hardware has a bug in the FIFO logic that
1181 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1182 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1183 * aligned except if slab debugging is enabled.
82788c7a 1184 */
14d0263f 1185static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1186{
1187 struct sk_buff *skb;
14d0263f
SH		 1188 unsigned long p;
1189 int i;
82788c7a 1190
14d0263f
SH		 1191 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1192 if (!skb)
1193 goto nomem;
1194
1195 p = (unsigned long) skb->data;
1196 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1197
1198 for (i = 0; i < sky2->rx_nfrags; i++) {
1199 struct page *page = alloc_page(GFP_ATOMIC);
1200
1201 if (!page)
1202 goto free_partial;
1203 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1204 }
1205
1206 return skb;
14d0263f
SH		 1207free_partial:
1208 kfree_skb(skb);
1209nomem:
1210 return NULL;
82788c7a
SH		 1211}
1212
55c9dd35
SH		 1213static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1214{
1215 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1216}
1217
cd28ab6a
SH		 1218/*
1219 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1220 * Normal case this ends up creating one list element for skb
1221 * in the receive ring. Worst case if using large MTU and each
1222 * allocation falls on a different 64 bit region, that results
1223 * in 6 list elements per ring entry.
1224 * One element is used for checksum enable/disable, and one
1225 * extra to avoid wrap.
cd28ab6a 1226 */
6b1a3aef 1227static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1228{
6b1a3aef 1229 struct sky2_hw *hw = sky2->hw;
14d0263f 1230 struct rx_ring_info *re;
6b1a3aef 1231 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1232 unsigned i, size, space, thresh;
cd28ab6a 1233
6b1a3aef 1234 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1235 sky2_qset(hw, rxq);
977bdf06 1236
c3905bc4
SH		 1237 /* On PCI express lowering the watermark gives better performance */
1238 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1239 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1240
1241 /* These chips have no ram buffer?
1242 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1243 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1244 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1245 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1246 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1247
6b1a3aef
SH		 1248 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1249
ea76e635
SH		 1250 if (!(hw->flags & SKY2_HW_NEW_LE))
1251 rx_set_checksum(sky2);
14d0263f
SH		 1252
1253 /* Space needed for frame data + headers rounded up */
f957da2a 1254 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1255
1256 /* Stopping point for hardware truncation */
1257 thresh = (size - 8) / sizeof(u32);
1258
1259 /* Account for overhead of skb - to avoid order > 0 allocation */
1260 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1261 + sizeof(struct skb_shared_info);
1262
1263 sky2->rx_nfrags = space >> PAGE_SHIFT;
1264 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1265
1266 if (sky2->rx_nfrags != 0) {
1267 /* Compute residue after pages */
1268 space = sky2->rx_nfrags << PAGE_SHIFT;
1269
1270 if (space < size)
1271 size -= space;
1272 else
1273 size = 0;
1274
1275 /* Optimize to handle small packets and headers */
1276 if (size < copybreak)
1277 size = copybreak;
1278 if (size < ETH_HLEN)
1279 size = ETH_HLEN;
1280 }
1281 sky2->rx_data_size = size;
1282
1283 /* Fill Rx ring */
793b883e 1284 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1285 re = sky2->rx_ring + i;
cd28ab6a 1286
14d0263f 1287 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1288 if (!re->skb)
1289 goto nomem;
1290
14d0263f
SH		 1291 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1292 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1293 }
1294
a1433ac4
SH		 1295 /*
1296 * The receiver hangs if it receives frames larger than the
1297 * packet buffer. As a workaround, truncate oversize frames, but
1298 * the register is limited to 9 bits, so if you do frames > 2052
1299 * you better get the MTU right!
1300 */
a1433ac4
SH		 1301 if (thresh > 0x1ff)
1302 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1303 else {
1304 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1305 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1306 }
1307
6b1a3aef 1308 /* Tell chip about available buffers */
55c9dd35 1309 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1310 return 0;
1311nomem:
1312 sky2_rx_clean(sky2);
1313 return -ENOMEM;
1314}
1315
1316/* Bring up network interface. */
1317static int sky2_up(struct net_device *dev)
1318{
1319 struct sky2_port *sky2 = netdev_priv(dev);
1320 struct sky2_hw *hw = sky2->hw;
1321 unsigned port = sky2->port;
e0c28116 1322 u32 imask, ramsize;
ee7abb04 1323 int cap, err = -ENOMEM;
843a46f4 1324 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1325
ee7abb04
SH		 1326 /*
1327 * On dual port PCI-X card, there is an problem where status
1328 * can be received out of order due to split transactions
843a46f4 1329 */
ee7abb04
SH		 1330 if (otherdev && netif_running(otherdev) &&
1331 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1332 u16 cmd;
1333
b32f40c4 1334 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1335 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1336 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1337
ee7abb04 1338 }
843a46f4 1339
cd28ab6a
SH		 1340 if (netif_msg_ifup(sky2))
1341 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1342
55d7b4e6
SH		 1343 netif_carrier_off(dev);
1344
cd28ab6a
SH		 1345 /* must be power of 2 */
1346 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1347 TX_RING_SIZE *
1348 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1349 &sky2->tx_le_map);
1350 if (!sky2->tx_le)
1351 goto err_out;
1352
6cdbbdf3 1353 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1354 GFP_KERNEL);
1355 if (!sky2->tx_ring)
1356 goto err_out;
88f5f0ca
SH		 1357
1358 tx_init(sky2);
cd28ab6a
SH		 1359
1360 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1361 &sky2->rx_le_map);
1362 if (!sky2->rx_le)
1363 goto err_out;
1364 memset(sky2->rx_le, 0, RX_LE_BYTES);
1365
291ea614 1366 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1367 GFP_KERNEL);
1368 if (!sky2->rx_ring)
1369 goto err_out;
1370
d3bcfbeb
SH		 1371 sky2_phy_power(hw, port, 1);
1372
cd28ab6a
SH		 1373 sky2_mac_init(hw, port);
1374
e0c28116
SH		 1375 /* Register is number of 4K blocks on internal RAM buffer. */
1376 ramsize = sky2_read8(hw, B2_E_0) * 4;
1377 if (ramsize > 0) {
67712901 1378 u32 rxspace;
cd28ab6a 1379
e0c28116 1380 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1381 if (ramsize < 16)
1382 rxspace = ramsize / 2;
1383 else
1384 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1385
67712901
SH		 1386 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1387 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1388
1389 /* Make sure SyncQ is disabled */
1390 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1391 RB_RST_SET);
1392 }
793b883e 1393
af4ed7e6 1394 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1395
69161611
SH		 1396 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1397 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1398 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1399
977bdf06 1400 /* Set almost empty threshold */
c2716fb4
SH		 1401 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1402 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1403 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1404
6b1a3aef
SH		 1405 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1406 TX_RING_SIZE - 1);
cd28ab6a 1407
6b1a3aef 1408 err = sky2_rx_start(sky2);
6de16237 1409 if (err)
cd28ab6a
SH		 1410 goto err_out;
1411
cd28ab6a 1412 /* Enable interrupts from phy/mac for port */
e07b1aa8 1413 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1414 imask |= portirq_msk[port];
e07b1aa8
SH		 1415 sky2_write32(hw, B0_IMSK, imask);
1416
cd28ab6a
SH		 1417 return 0;
1418
1419err_out:
1b537565 1420 if (sky2->rx_le) {
cd28ab6a
SH		 1421 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1422 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1423 sky2->rx_le = NULL;
1424 }
1425 if (sky2->tx_le) {
cd28ab6a
SH		 1426 pci_free_consistent(hw->pdev,
1427 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1428 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1429 sky2->tx_le = NULL;
1430 }
1431 kfree(sky2->tx_ring);
1432 kfree(sky2->rx_ring);
cd28ab6a 1433
1b537565
SH		 1434 sky2->tx_ring = NULL;
1435 sky2->rx_ring = NULL;
cd28ab6a
SH		 1436 return err;
1437}
1438
793b883e
SH		 1439/* Modular subtraction in ring */
1440static inline int tx_dist(unsigned tail, unsigned head)
1441{
cb5d9547 1442 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1443}
cd28ab6a 1444
793b883e
SH		 1445/* Number of list elements available for next tx */
1446static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1447{
793b883e 1448 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1449}
1450
793b883e 1451/* Estimate of number of transmit list elements required */
28bd181a 1452static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1453{
793b883e
SH		 1454 unsigned count;
1455
1456 count = sizeof(dma_addr_t) / sizeof(u32);
1457 count += skb_shinfo(skb)->nr_frags * count;
1458
89114afd 1459 if (skb_is_gso(skb))
793b883e
SH		 1460 ++count;
1461
84fa7933 1462 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1463 ++count;
1464
1465 return count;
cd28ab6a
SH		 1466}
1467
793b883e
SH		 1468/*
1469 * Put one packet in ring for transmit.
1470 * A single packet can generate multiple list elements, and
1471 * the number of ring elements will probably be less than the number
1472 * of list elements used.
1473 */
cd28ab6a
SH		 1474static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1475{
1476 struct sky2_port *sky2 = netdev_priv(dev);
1477 struct sky2_hw *hw = sky2->hw;
d1f13708 1478 struct sky2_tx_le *le = NULL;
6cdbbdf3 1479 struct tx_ring_info *re;
cd28ab6a
SH		 1480 unsigned i, len;
1481 dma_addr_t mapping;
1482 u32 addr64;
1483 u16 mss;
1484 u8 ctrl;
1485
2bb8c262
SH		 1486 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1487 return NETDEV_TX_BUSY;
cd28ab6a 1488
793b883e 1489 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1490 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1491 dev->name, sky2->tx_prod, skb->len);
1492
cd28ab6a
SH		 1493 len = skb_headlen(skb);
1494 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
36eb0c71 1495 addr64 = upper_32_bits(mapping);
793b883e 1496
a018e330 1497 /* Send high bits if changed or crosses boundary */
36eb0c71
SH		 1498 if (addr64 != sky2->tx_addr64 ||
1499 upper_32_bits(mapping + len) != sky2->tx_addr64) {
793b883e 1500 le = get_tx_le(sky2);
f65b138c 1501 le->addr = cpu_to_le32(addr64);
793b883e 1502 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 1503 sky2->tx_addr64 = upper_32_bits(mapping + len);
793b883e 1504 }
cd28ab6a
SH		 1505
1506 /* Check for TCP Segmentation Offload */
7967168c 1507 mss = skb_shinfo(skb)->gso_size;
793b883e 1508 if (mss != 0) {
ea76e635
SH		 1509
1510 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1511 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1512
1513 if (mss != sky2->tx_last_mss) {
1514 le = get_tx_le(sky2);
1515 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1516
1517 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1518 le->opcode = OP_MSS | HW_OWNER;
1519 else
1520 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1521 sky2->tx_last_mss = mss;
1522 }
cd28ab6a
SH		 1523 }
1524
cd28ab6a 1525 ctrl = 0;
d1f13708
SH		 1526#ifdef SKY2_VLAN_TAG_USED
1527 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1528 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1529 if (!le) {
1530 le = get_tx_le(sky2);
f65b138c 1531 le->addr = 0;
d1f13708 1532 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1533 } else
1534 le->opcode |= OP_VLAN;
1535 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1536 ctrl |= INS_VLAN;
1537 }
1538#endif
1539
1540 /* Handle TCP checksum offload */
84fa7933 1541 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1542 /* On Yukon EX (some versions) encoding change. */
ea76e635 1543 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1544 ctrl |= CALSUM; /* auto checksum */
1545 else {
1546 const unsigned offset = skb_transport_offset(skb);
1547 u32 tcpsum;
1548
1549 tcpsum = offset << 16; /* sum start */
1550 tcpsum |= offset + skb->csum_offset; /* sum write */
1551
1552 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1553 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1554 ctrl |= UDPTCP;
1555
1556 if (tcpsum != sky2->tx_tcpsum) {
1557 sky2->tx_tcpsum = tcpsum;
1558
1559 le = get_tx_le(sky2);
1560 le->addr = cpu_to_le32(tcpsum);
1561 le->length = 0; /* initial checksum value */
1562 le->ctrl = 1; /* one packet */
1563 le->opcode = OP_TCPLISW | HW_OWNER;
1564 }
1d179332 1565 }
cd28ab6a
SH		 1566 }
1567
1568 le = get_tx_le(sky2);
f65b138c 1569 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1570 le->length = cpu_to_le16(len);
1571 le->ctrl = ctrl;
793b883e 1572 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1573
291ea614 1574 re = tx_le_re(sky2, le);
cd28ab6a 1575 re->skb = skb;
6cdbbdf3 1576 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1577 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1578
1579 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1580 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1581
1582 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1583 frag->size, PCI_DMA_TODEVICE);
36eb0c71 1584 addr64 = upper_32_bits(mapping);
793b883e
SH		 1585 if (addr64 != sky2->tx_addr64) {
1586 le = get_tx_le(sky2);
f65b138c 1587 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1588 le->ctrl = 0;
1589 le->opcode = OP_ADDR64 | HW_OWNER;
1590 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1591 }
1592
1593 le = get_tx_le(sky2);
f65b138c 1594 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1595 le->length = cpu_to_le16(frag->size);
1596 le->ctrl = ctrl;
793b883e 1597 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1598
291ea614
SH		 1599 re = tx_le_re(sky2, le);
1600 re->skb = skb;
1601 pci_unmap_addr_set(re, mapaddr, mapping);
1602 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1603 }
6cdbbdf3 1604
cd28ab6a
SH		 1605 le->ctrl |= EOP;
1606
97bda706
SH		 1607 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1608 netif_stop_queue(dev);
b19666d9 1609
290d4de5 1610 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1611
cd28ab6a
SH		 1612 dev->trans_start = jiffies;
1613 return NETDEV_TX_OK;
1614}
1615
cd28ab6a 1616/*
793b883e
SH		 1617 * Free ring elements from starting at tx_cons until "done"
1618 *
1619 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1620 * buffers so make sure not to free skb to early.
cd28ab6a 1621 */
d11c13e7 1622static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1623{
d11c13e7 1624 struct net_device *dev = sky2->netdev;
af2a58ac 1625 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1626 unsigned idx;
cd28ab6a 1627
0e3ff6aa 1628 BUG_ON(done >= TX_RING_SIZE);
2224795d 1629
291ea614
SH		 1630 for (idx = sky2->tx_cons; idx != done;
1631 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1632 struct sky2_tx_le *le = sky2->tx_le + idx;
1633 struct tx_ring_info *re = sky2->tx_ring + idx;
1634
1635 switch(le->opcode & ~HW_OWNER) {
1636 case OP_LARGESEND:
1637 case OP_PACKET:
1638 pci_unmap_single(pdev,
1639 pci_unmap_addr(re, mapaddr),
1640 pci_unmap_len(re, maplen),
1641 PCI_DMA_TODEVICE);
af2a58ac 1642 break;
291ea614
SH		 1643 case OP_BUFFER:
1644 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1645 pci_unmap_len(re, maplen),
734d1868 1646 PCI_DMA_TODEVICE);
291ea614
SH		 1647 break;
1648 }
1649
1650 if (le->ctrl & EOP) {
1651 if (unlikely(netif_msg_tx_done(sky2)))
1652 printk(KERN_DEBUG "%s: tx done %u\n",
1653 dev->name, idx);
3cf26753 1654
7138a0f5
SH		 1655 dev->stats.tx_packets++;
1656 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1657
794b2bd2 1658 dev_kfree_skb_any(re->skb);
3cf26753 1659 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1660 }
793b883e 1661 }
793b883e 1662
291ea614 1663 sky2->tx_cons = idx;
50432cb5
SH		 1664 smp_mb();
1665
22e11703 1666 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1667 netif_wake_queue(dev);
cd28ab6a
SH		 1668}
1669
1670/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1671static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1672{
2bb8c262
SH		 1673 struct sky2_port *sky2 = netdev_priv(dev);
1674
1675 netif_tx_lock_bh(dev);
d11c13e7 1676 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1677 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1678}
1679
1680/* Network shutdown */
1681static int sky2_down(struct net_device *dev)
1682{
1683 struct sky2_port *sky2 = netdev_priv(dev);
1684 struct sky2_hw *hw = sky2->hw;
1685 unsigned port = sky2->port;
1686 u16 ctrl;
e07b1aa8 1687 u32 imask;
cd28ab6a 1688
1b537565
SH		 1689 /* Never really got started! */
1690 if (!sky2->tx_le)
1691 return 0;
1692
cd28ab6a
SH		 1693 if (netif_msg_ifdown(sky2))
1694 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1695
018d1c66 1696 /* Stop more packets from being queued */
cd28ab6a
SH		 1697 netif_stop_queue(dev);
1698
ebc646f6
SH		 1699 /* Disable port IRQ */
1700 imask = sky2_read32(hw, B0_IMSK);
1701 imask &= ~portirq_msk[port];
1702 sky2_write32(hw, B0_IMSK, imask);
1703
6de16237
SH		 1704 synchronize_irq(hw->pdev->irq);
1705
d3bcfbeb 1706 sky2_gmac_reset(hw, port);
793b883e 1707
cd28ab6a
SH		 1708 /* Stop transmitter */
1709 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1710 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1711
1712 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1713 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1714
1715 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1716 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1717 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1718
6de16237
SH		 1719 /* Make sure no packets are pending */
1720 napi_synchronize(&hw->napi);
1721
cd28ab6a
SH		 1722 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1723
1724 /* Workaround shared GMAC reset */
793b883e
SH		 1725 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1726 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1727 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1728
1729 /* Disable Force Sync bit and Enable Alloc bit */
1730 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1731 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1732
1733 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1734 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1735 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1736
1737 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1738 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1739 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1740
1741 /* Reset the Tx prefetch units */
1742 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1743 PREF_UNIT_RST_SET);
1744
1745 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1746
6b1a3aef 1747 sky2_rx_stop(sky2);
cd28ab6a
SH		 1748
1749 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1750 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1751
d3bcfbeb
SH		 1752 sky2_phy_power(hw, port, 0);
1753
55d7b4e6
SH		 1754 netif_carrier_off(dev);
1755
d571b694 1756 /* turn off LED's */
cd28ab6a
SH		 1757 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1758
2bb8c262 1759 sky2_tx_clean(dev);
cd28ab6a
SH		 1760 sky2_rx_clean(sky2);
1761
1762 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1763 sky2->rx_le, sky2->rx_le_map);
1764 kfree(sky2->rx_ring);
1765
1766 pci_free_consistent(hw->pdev,
1767 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1768 sky2->tx_le, sky2->tx_le_map);
1769 kfree(sky2->tx_ring);
1770
1b537565
SH		 1771 sky2->tx_le = NULL;
1772 sky2->rx_le = NULL;
1773
1774 sky2->rx_ring = NULL;
1775 sky2->tx_ring = NULL;
1776
cd28ab6a
SH		 1777 return 0;
1778}
1779
1780static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1781{
ea76e635 1782 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1783 return SPEED_1000;
1784
05745c4a
SH		 1785 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1786 if (aux & PHY_M_PS_SPEED_100)
1787 return SPEED_100;
1788 else
1789 return SPEED_10;
1790 }
cd28ab6a
SH		 1791
1792 switch (aux & PHY_M_PS_SPEED_MSK) {
1793 case PHY_M_PS_SPEED_1000:
1794 return SPEED_1000;
1795 case PHY_M_PS_SPEED_100:
1796 return SPEED_100;
1797 default:
1798 return SPEED_10;
1799 }
1800}
1801
1802static void sky2_link_up(struct sky2_port *sky2)
1803{
1804 struct sky2_hw *hw = sky2->hw;
1805 unsigned port = sky2->port;
1806 u16 reg;
16ad91e1
SH		 1807 static const char *fc_name[] = {
1808 [FC_NONE] = "none",
1809 [FC_TX] = "tx",
1810 [FC_RX] = "rx",
1811 [FC_BOTH] = "both",
1812 };
cd28ab6a 1813
cd28ab6a 1814 /* enable Rx/Tx */
2eaba1a2 1815 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1816 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1817 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1818
1819 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1820
1821 netif_carrier_on(sky2->netdev);
cd28ab6a 1822
75e80683 1823 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1824
cd28ab6a 1825 /* Turn on link LED */
793b883e 1826 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1827 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1828
1829 if (netif_msg_link(sky2))
1830 printk(KERN_INFO PFX
d571b694 1831 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1832 sky2->netdev->name, sky2->speed,
1833 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1834 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1835}
1836
1837static void sky2_link_down(struct sky2_port *sky2)
1838{
1839 struct sky2_hw *hw = sky2->hw;
1840 unsigned port = sky2->port;
1841 u16 reg;
1842
1843 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1844
1845 reg = gma_read16(hw, port, GM_GP_CTRL);
1846 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1847 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1848
cd28ab6a 1849 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1850
1851 /* Turn on link LED */
1852 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1853
1854 if (netif_msg_link(sky2))
1855 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1856
cd28ab6a
SH		 1857 sky2_phy_init(hw, port);
1858}
1859
16ad91e1
SH		 1860static enum flow_control sky2_flow(int rx, int tx)
1861{
1862 if (rx)
1863 return tx ? FC_BOTH : FC_RX;
1864 else
1865 return tx ? FC_TX : FC_NONE;
1866}
1867
793b883e
SH		 1868static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1869{
1870 struct sky2_hw *hw = sky2->hw;
1871 unsigned port = sky2->port;
da4c1ff4 1872 u16 advert, lpa;
793b883e 1873
da4c1ff4 1874 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1875 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1876 if (lpa & PHY_M_AN_RF) {
1877 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1878 return -1;
1879 }
1880
793b883e
SH		 1881 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1882 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1883 sky2->netdev->name);
1884 return -1;
1885 }
1886
793b883e 1887 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1888 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1889
da4c1ff4
SH		 1890 /* Since the pause result bits seem to in different positions on
1891 * different chips. look at registers.
1892 */
ea76e635 1893 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1894 /* Shift for bits in fiber PHY */
1895 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1896 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1897
1898 if (advert & ADVERTISE_1000XPAUSE)
1899 advert |= ADVERTISE_PAUSE_CAP;
1900 if (advert & ADVERTISE_1000XPSE_ASYM)
1901 advert |= ADVERTISE_PAUSE_ASYM;
1902 if (lpa & LPA_1000XPAUSE)
1903 lpa |= LPA_PAUSE_CAP;
1904 if (lpa & LPA_1000XPAUSE_ASYM)
1905 lpa |= LPA_PAUSE_ASYM;
1906 }
793b883e 1907
da4c1ff4
SH		 1908 sky2->flow_status = FC_NONE;
1909 if (advert & ADVERTISE_PAUSE_CAP) {
1910 if (lpa & LPA_PAUSE_CAP)
1911 sky2->flow_status = FC_BOTH;
1912 else if (advert & ADVERTISE_PAUSE_ASYM)
1913 sky2->flow_status = FC_RX;
1914 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1915 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1916 sky2->flow_status = FC_TX;
1917 }
793b883e 1918
16ad91e1 1919 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1920 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1921 sky2->flow_status = FC_NONE;
2eaba1a2 1922
da4c1ff4 1923 if (sky2->flow_status & FC_TX)
793b883e
SH		 1924 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1925 else
1926 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1927
1928 return 0;
1929}
cd28ab6a 1930
e07b1aa8
SH		 1931/* Interrupt from PHY */
1932static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1933{
e07b1aa8
SH		 1934 struct net_device *dev = hw->dev[port];
1935 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1936 u16 istatus, phystat;
1937
ebc646f6
SH		 1938 if (!netif_running(dev))
1939 return;
1940
e07b1aa8
SH		 1941 spin_lock(&sky2->phy_lock);
1942 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1943 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1944
cd28ab6a
SH		 1945 if (netif_msg_intr(sky2))
1946 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1947 sky2->netdev->name, istatus, phystat);
1948
2eaba1a2 1949 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1950 if (sky2_autoneg_done(sky2, phystat) == 0)
1951 sky2_link_up(sky2);
1952 goto out;
1953 }
cd28ab6a 1954
793b883e
SH		 1955 if (istatus & PHY_M_IS_LSP_CHANGE)
1956 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1957
793b883e
SH		 1958 if (istatus & PHY_M_IS_DUP_CHANGE)
1959 sky2->duplex =
1960 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1961
793b883e
SH		 1962 if (istatus & PHY_M_IS_LST_CHANGE) {
1963 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1964 sky2_link_up(sky2);
793b883e
SH		 1965 else
1966 sky2_link_down(sky2);
cd28ab6a 1967 }
793b883e 1968out:
e07b1aa8 1969 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1970}
1971
62335ab0 1972/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1973 * and tx queue is full (stopped).
1974 */
cd28ab6a
SH		 1975static void sky2_tx_timeout(struct net_device *dev)
1976{
1977 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1978 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1979
1980 if (netif_msg_timer(sky2))
1981 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1982
8f24664d 1983 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1984 dev->name, sky2->tx_cons, sky2->tx_prod,
1985 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1986 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1987
81906791
SH		 1988 /* can't restart safely under softirq */
1989 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1990}
1991
1992static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1993{
6b1a3aef
SH		 1994 struct sky2_port *sky2 = netdev_priv(dev);
1995 struct sky2_hw *hw = sky2->hw;
b628ed98 1996 unsigned port = sky2->port;
6b1a3aef
SH		 1997 int err;
1998 u16 ctl, mode;
e07b1aa8 1999 u32 imask;
cd28ab6a
SH		 2000
2001 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2002 return -EINVAL;
2003
05745c4a
SH		 2004 if (new_mtu > ETH_DATA_LEN &&
2005 (hw->chip_id == CHIP_ID_YUKON_FE ||
2006 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2007 return -EINVAL;
2008
6b1a3aef
SH		 2009 if (!netif_running(dev)) {
2010 dev->mtu = new_mtu;
2011 return 0;
2012 }
2013
e07b1aa8 2014 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2015 sky2_write32(hw, B0_IMSK, 0);
2016
018d1c66
SH		 2017 dev->trans_start = jiffies; /* prevent tx timeout */
2018 netif_stop_queue(dev);
bea3348e 2019 napi_disable(&hw->napi);
018d1c66 2020
e07b1aa8
SH		 2021 synchronize_irq(hw->pdev->irq);
2022
e0c28116 2023 if (sky2_read8(hw, B2_E_0) == 0)
69161611 2024 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2025
2026 ctl = gma_read16(hw, port, GM_GP_CTRL);
2027 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2028 sky2_rx_stop(sky2);
2029 sky2_rx_clean(sky2);
cd28ab6a
SH		 2030
2031 dev->mtu = new_mtu;
14d0263f 2032
6b1a3aef
SH		 2033 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2034 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2035
2036 if (dev->mtu > ETH_DATA_LEN)
2037 mode |= GM_SMOD_JUMBO_ENA;
2038
b628ed98 2039 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2040
b628ed98 2041 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2042
6b1a3aef 2043 err = sky2_rx_start(sky2);
e07b1aa8 2044 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2045
bea3348e
SH		 2046 napi_enable(&hw->napi);
2047
1b537565
SH		 2048 if (err)
2049 dev_close(dev);
2050 else {
b628ed98 2051 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2052
1b537565
SH		 2053 netif_wake_queue(dev);
2054 }
2055
cd28ab6a
SH		 2056 return err;
2057}
2058
14d0263f
SH		 2059/* For small just reuse existing skb for next receive */
2060static struct sk_buff *receive_copy(struct sky2_port *sky2,
2061 const struct rx_ring_info *re,
2062 unsigned length)
2063{
2064 struct sk_buff *skb;
2065
2066 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2067 if (likely(skb)) {
2068 skb_reserve(skb, 2);
2069 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2070 length, PCI_DMA_FROMDEVICE);
d626f62b 2071 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2072 skb->ip_summed = re->skb->ip_summed;
2073 skb->csum = re->skb->csum;
2074 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2075 length, PCI_DMA_FROMDEVICE);
2076 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2077 skb_put(skb, length);
14d0263f
SH		 2078 }
2079 return skb;
2080}
2081
2082/* Adjust length of skb with fragments to match received data */
2083static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2084 unsigned int length)
2085{
2086 int i, num_frags;
2087 unsigned int size;
2088
2089 /* put header into skb */
2090 size = min(length, hdr_space);
2091 skb->tail += size;
2092 skb->len += size;
2093 length -= size;
2094
2095 num_frags = skb_shinfo(skb)->nr_frags;
2096 for (i = 0; i < num_frags; i++) {
2097 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2098
2099 if (length == 0) {
2100 /* don't need this page */
2101 __free_page(frag->page);
2102 --skb_shinfo(skb)->nr_frags;
2103 } else {
2104 size = min(length, (unsigned) PAGE_SIZE);
2105
2106 frag->size = size;
2107 skb->data_len += size;
2108 skb->truesize += size;
2109 skb->len += size;
2110 length -= size;
2111 }
2112 }
2113}
2114
2115/* Normal packet - take skb from ring element and put in a new one */
2116static struct sk_buff *receive_new(struct sky2_port *sky2,
2117 struct rx_ring_info *re,
2118 unsigned int length)
2119{
2120 struct sk_buff *skb, *nskb;
2121 unsigned hdr_space = sky2->rx_data_size;
2122
14d0263f
SH		 2123 /* Don't be tricky about reusing pages (yet) */
2124 nskb = sky2_rx_alloc(sky2);
2125 if (unlikely(!nskb))
2126 return NULL;
2127
2128 skb = re->skb;
2129 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2130
2131 prefetch(skb->data);
2132 re->skb = nskb;
2133 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2134
2135 if (skb_shinfo(skb)->nr_frags)
2136 skb_put_frags(skb, hdr_space, length);
2137 else
489b10c1 2138 skb_put(skb, length);
14d0263f
SH		 2139 return skb;
2140}
2141
cd28ab6a
SH		 2142/*
2143 * Receive one packet.
d571b694 2144 * For larger packets, get new buffer.
cd28ab6a 2145 */
497d7c86 2146static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2147 u16 length, u32 status)
2148{
497d7c86 2149 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2150 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2151 struct sk_buff *skb = NULL;
d6532232
SH		 2152 u16 count = (status & GMR_FS_LEN) >> 16;
2153
2154#ifdef SKY2_VLAN_TAG_USED
2155 /* Account for vlan tag */
2156 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2157 count -= VLAN_HLEN;
2158#endif
cd28ab6a
SH		 2159
2160 if (unlikely(netif_msg_rx_status(sky2)))
2161 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2162 dev->name, sky2->rx_next, status, length);
cd28ab6a 2163
793b883e 2164 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2165 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2166
3b12e014
SH		 2167 /* This chip has hardware problems that generates bogus status.
2168 * So do only marginal checking and expect higher level protocols
2169 * to handle crap frames.
2170 */
2171 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2172 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2173 length != count)
2174 goto okay;
2175
42eeea01 2176 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2177 goto error;
2178
42eeea01
SH		 2179 if (!(status & GMR_FS_RX_OK))
2180 goto resubmit;
2181
d6532232
SH		 2182 /* if length reported by DMA does not match PHY, packet was truncated */
2183 if (length != count)
3b12e014 2184 goto len_error;
71749531 2185
3b12e014 2186okay:
14d0263f
SH		 2187 if (length < copybreak)
2188 skb = receive_copy(sky2, re, length);
2189 else
2190 skb = receive_new(sky2, re, length);
793b883e 2191resubmit:
14d0263f 2192 sky2_rx_submit(sky2, re);
79e57d32 2193
cd28ab6a
SH		 2194 return skb;
2195
3b12e014 2196len_error:
71749531
SH		 2197 /* Truncation of overlength packets
2198 causes PHY length to not match MAC length */
7138a0f5 2199 ++dev->stats.rx_length_errors;
d6532232 2200 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2201 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2202 dev->name, status, length);
d6532232 2203 goto resubmit;
71749531 2204
cd28ab6a 2205error:
7138a0f5 2206 ++dev->stats.rx_errors;
b6d77734 2207 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2208 dev->stats.rx_over_errors++;
b6d77734
SH		 2209 goto resubmit;
2210 }
6e15b712 2211
3be92a70 2212 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2213 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2214 dev->name, status, length);
793b883e
SH		 2215
2216 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2217 dev->stats.rx_length_errors++;
cd28ab6a 2218 if (status & GMR_FS_FRAGMENT)
7138a0f5 2219 dev->stats.rx_frame_errors++;
cd28ab6a 2220 if (status & GMR_FS_CRC_ERR)
7138a0f5 2221 dev->stats.rx_crc_errors++;
79e57d32 2222
793b883e 2223 goto resubmit;
cd28ab6a
SH		 2224}
2225
e07b1aa8
SH		 2226/* Transmit complete */
2227static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2228{
e07b1aa8 2229 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2230
e07b1aa8 2231 if (netif_running(dev)) {
2bb8c262 2232 netif_tx_lock(dev);
e07b1aa8 2233 sky2_tx_complete(sky2, last);
2bb8c262 2234 netif_tx_unlock(dev);
2224795d 2235 }
cd28ab6a
SH		 2236}
2237
e07b1aa8 2238/* Process status response ring */
26691830 2239static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2240{
e07b1aa8 2241 int work_done = 0;
55c9dd35 2242 unsigned rx[2] = { 0, 0 };
a8fd6266 2243
af2a58ac 2244 rmb();
26691830 2245 do {
55c9dd35 2246 struct sky2_port *sky2;
13210ce5 2247 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2248 unsigned port;
13210ce5 2249 struct net_device *dev;
cd28ab6a 2250 struct sk_buff *skb;
cd28ab6a
SH		 2251 u32 status;
2252 u16 length;
ab5adecb
SH		 2253 u8 opcode = le->opcode;
2254
2255 if (!(opcode & HW_OWNER))
2256 break;
cd28ab6a 2257
cb5d9547 2258 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2259
ab5adecb 2260 port = le->css & CSS_LINK_BIT;
69161611 2261 dev = hw->dev[port];
13210ce5 2262 sky2 = netdev_priv(dev);
f65b138c
SH		 2263 length = le16_to_cpu(le->length);
2264 status = le32_to_cpu(le->status);
cd28ab6a 2265
ab5adecb
SH		 2266 le->opcode = 0;
2267 switch (opcode & ~HW_OWNER) {
cd28ab6a 2268 case OP_RXSTAT:
55c9dd35 2269 ++rx[port];
497d7c86 2270 skb = sky2_receive(dev, length, status);
3225b919 2271 if (unlikely(!skb)) {
7138a0f5 2272 dev->stats.rx_dropped++;
55c9dd35 2273 break;
3225b919 2274 }
13210ce5 2275
69161611 2276 /* This chip reports checksum status differently */
05745c4a 2277 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2278 if (sky2->rx_csum &&
2279 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2280 (le->css & CSS_TCPUDPCSOK))
2281 skb->ip_summed = CHECKSUM_UNNECESSARY;
2282 else
2283 skb->ip_summed = CHECKSUM_NONE;
2284 }
2285
13210ce5 2286 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2287 dev->stats.rx_packets++;
2288 dev->stats.rx_bytes += skb->len;
13210ce5
SH		 2289 dev->last_rx = jiffies;
2290
d1f13708
SH		 2291#ifdef SKY2_VLAN_TAG_USED
2292 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2293 vlan_hwaccel_receive_skb(skb,
2294 sky2->vlgrp,
2295 be16_to_cpu(sky2->rx_tag));
2296 } else
2297#endif
cd28ab6a 2298 netif_receive_skb(skb);
13210ce5 2299
22e11703 2300 /* Stop after net poll weight */
13210ce5
SH		 2301 if (++work_done >= to_do)
2302 goto exit_loop;
cd28ab6a
SH		 2303 break;
2304
d1f13708
SH		 2305#ifdef SKY2_VLAN_TAG_USED
2306 case OP_RXVLAN:
2307 sky2->rx_tag = length;
2308 break;
2309
2310 case OP_RXCHKSVLAN:
2311 sky2->rx_tag = length;
2312 /* fall through */
2313#endif
cd28ab6a 2314 case OP_RXCHKS:
87418307
SH		 2315 if (!sky2->rx_csum)
2316 break;
2317
05745c4a
SH		 2318 /* If this happens then driver assuming wrong format */
2319 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2320 if (net_ratelimit())
2321 printk(KERN_NOTICE "%s: unexpected"
2322 " checksum status\n",
2323 dev->name);
69161611 2324 break;
05745c4a 2325 }
69161611 2326
87418307
SH		 2327 /* Both checksum counters are programmed to start at
2328 * the same offset, so unless there is a problem they
2329 * should match. This failure is an early indication that
2330 * hardware receive checksumming won't work.
2331 */
2332 if (likely(status >> 16 == (status & 0xffff))) {
2333 skb = sky2->rx_ring[sky2->rx_next].skb;
2334 skb->ip_summed = CHECKSUM_COMPLETE;
2335 skb->csum = status & 0xffff;
2336 } else {
2337 printk(KERN_NOTICE PFX "%s: hardware receive "
2338 "checksum problem (status = %#x)\n",
2339 dev->name, status);
2340 sky2->rx_csum = 0;
2341 sky2_write32(sky2->hw,
69161611 2342 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2343 BMU_DIS_RX_CHKSUM);
2344 }
cd28ab6a
SH		 2345 break;
2346
2347 case OP_TXINDEXLE:
13b97b74 2348 /* TX index reports status for both ports */
f55925d7
SH		 2349 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2350 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2351 if (hw->dev[1])
2352 sky2_tx_done(hw->dev[1],
2353 ((status >> 24) & 0xff)
2354 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2355 break;
2356
cd28ab6a
SH		 2357 default:
2358 if (net_ratelimit())
793b883e 2359 printk(KERN_WARNING PFX
ab5adecb 2360 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2361 }
26691830 2362 } while (hw->st_idx != idx);
cd28ab6a 2363
fe2a24df
SH		 2364 /* Fully processed status ring so clear irq */
2365 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2366
13210ce5 2367exit_loop:
55c9dd35
SH		 2368 if (rx[0])
2369 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2370
55c9dd35
SH		 2371 if (rx[1])
2372 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2373
e07b1aa8 2374 return work_done;
cd28ab6a
SH		 2375}
2376
2377static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2378{
2379 struct net_device *dev = hw->dev[port];
2380
3be92a70
SH		 2381 if (net_ratelimit())
2382 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2383 dev->name, status);
cd28ab6a
SH		 2384
2385 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2386 if (net_ratelimit())
2387 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2388 dev->name);
cd28ab6a
SH		 2389 /* Clear IRQ */
2390 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2391 }
2392
2393 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2394 if (net_ratelimit())
2395 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2396 dev->name);
cd28ab6a
SH		 2397
2398 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2399 }
2400
2401 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2402 if (net_ratelimit())
2403 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2404 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2405 }
2406
2407 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2408 if (net_ratelimit())
2409 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2410 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2411 }
2412
2413 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2414 if (net_ratelimit())
2415 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2416 dev->name);
cd28ab6a
SH		 2417 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2418 }
2419}
2420
2421static void sky2_hw_intr(struct sky2_hw *hw)
2422{
555382cb 2423 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2424 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2425 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2426
2427 status &= hwmsk;
cd28ab6a 2428
793b883e 2429 if (status & Y2_IS_TIST_OV)
cd28ab6a 2430 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2431
2432 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2433 u16 pci_err;
2434
b32f40c4 2435 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2436 if (net_ratelimit())
555382cb 2437 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2438 pci_err);
cd28ab6a 2439
b32f40c4 2440 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2441 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2442 }
2443
2444 if (status & Y2_IS_PCI_EXP) {
d571b694 2445 /* PCI-Express uncorrectable Error occurred */
555382cb 2446 u32 err;
cd28ab6a 2447
7782c8c4
SH		 2448 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2449 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2450 0xfffffffful);
3be92a70 2451 if (net_ratelimit())
555382cb 2452 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2453
7782c8c4 2454 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
cd28ab6a
SH		 2455 }
2456
2457 if (status & Y2_HWE_L1_MASK)
2458 sky2_hw_error(hw, 0, status);
2459 status >>= 8;
2460 if (status & Y2_HWE_L1_MASK)
2461 sky2_hw_error(hw, 1, status);
2462}
2463
2464static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2465{
2466 struct net_device *dev = hw->dev[port];
2467 struct sky2_port *sky2 = netdev_priv(dev);
2468 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2469
2470 if (netif_msg_intr(sky2))
2471 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2472 dev->name, status);
2473
a3caeada
SH		 2474 if (status & GM_IS_RX_CO_OV)
2475 gma_read16(hw, port, GM_RX_IRQ_SRC);
2476
2477 if (status & GM_IS_TX_CO_OV)
2478 gma_read16(hw, port, GM_TX_IRQ_SRC);
2479
cd28ab6a 2480 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2481 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2482 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2483 }
2484
2485 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2486 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2487 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2488 }
cd28ab6a
SH		 2489}
2490
40b01727
SH		 2491/* This should never happen it is a bug. */
2492static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2493 u16 q, unsigned ring_size)
d257924e
SH		 2494{
2495 struct net_device *dev = hw->dev[port];
2496 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2497 unsigned idx;
2498 const u64 *le = (q == Q_R1 || q == Q_R2)
2499 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2500
40b01727
SH		 2501 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2502 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2503 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2504 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2505
40b01727 2506 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2507}
cd28ab6a 2508
75e80683
SH		 2509static int sky2_rx_hung(struct net_device *dev)
2510{
2511 struct sky2_port *sky2 = netdev_priv(dev);
2512 struct sky2_hw *hw = sky2->hw;
2513 unsigned port = sky2->port;
2514 unsigned rxq = rxqaddr[port];
2515 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2516 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2517 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2518 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2519
2520 /* If idle and MAC or PCI is stuck */
2521 if (sky2->check.last == dev->last_rx &&
2522 ((mac_rp == sky2->check.mac_rp &&
2523 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2524 /* Check if the PCI RX hang */
2525 (fifo_rp == sky2->check.fifo_rp &&
2526 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2527 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2528 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2529 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2530 return 1;
2531 } else {
2532 sky2->check.last = dev->last_rx;
2533 sky2->check.mac_rp = mac_rp;
2534 sky2->check.mac_lev = mac_lev;
2535 sky2->check.fifo_rp = fifo_rp;
2536 sky2->check.fifo_lev = fifo_lev;
2537 return 0;
2538 }
2539}
2540
32c2c300 2541static void sky2_watchdog(unsigned long arg)
d27ed387 2542{
01bd7564 2543 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2544
75e80683 2545 /* Check for lost IRQ once a second */
32c2c300 2546 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2547 napi_schedule(&hw->napi);
75e80683
SH		 2548 } else {
2549 int i, active = 0;
2550
2551 for (i = 0; i < hw->ports; i++) {
bea3348e 2552 struct net_device *dev = hw->dev[i];
75e80683
SH		 2553 if (!netif_running(dev))
2554 continue;
2555 ++active;
2556
2557 /* For chips with Rx FIFO, check if stuck */
e0c28116 2558 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
75e80683
SH		 2559 sky2_rx_hung(dev)) {
2560 pr_info(PFX "%s: receiver hang detected\n",
2561 dev->name);
2562 schedule_work(&hw->restart_work);
2563 return;
2564 }
2565 }
2566
2567 if (active == 0)
2568 return;
32c2c300 2569 }
01bd7564 2570
75e80683 2571 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2572}
2573
40b01727
SH		 2574/* Hardware/software error handling */
2575static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2576{
40b01727
SH		 2577 if (net_ratelimit())
2578 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2579
1e5f1283
SH		 2580 if (status & Y2_IS_HW_ERR)
2581 sky2_hw_intr(hw);
d257924e 2582
1e5f1283
SH		 2583 if (status & Y2_IS_IRQ_MAC1)
2584 sky2_mac_intr(hw, 0);
cd28ab6a 2585
1e5f1283
SH		 2586 if (status & Y2_IS_IRQ_MAC2)
2587 sky2_mac_intr(hw, 1);
cd28ab6a 2588
1e5f1283 2589 if (status & Y2_IS_CHK_RX1)
40b01727 2590 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2591
1e5f1283 2592 if (status & Y2_IS_CHK_RX2)
40b01727 2593 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2594
1e5f1283 2595 if (status & Y2_IS_CHK_TXA1)
40b01727 2596 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2597
1e5f1283 2598 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2599 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2600}
2601
bea3348e 2602static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2603{
bea3348e 2604 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2605 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2606 int work_done = 0;
26691830 2607 u16 idx;
40b01727
SH		 2608
2609 if (unlikely(status & Y2_IS_ERROR))
2610 sky2_err_intr(hw, status);
2611
2612 if (status & Y2_IS_IRQ_PHY1)
2613 sky2_phy_intr(hw, 0);
2614
2615 if (status & Y2_IS_IRQ_PHY2)
2616 sky2_phy_intr(hw, 1);
cd28ab6a 2617
26691830
SH		 2618 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2619 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2620
2621 if (work_done >= work_limit)
26691830
SH		 2622 goto done;
2623 }
6f535763 2624
26691830
SH		 2625 /* Bug/Errata workaround?
2626 * Need to kick the TX irq moderation timer.
2627 */
2628 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2629 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2630 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2631 }
26691830
SH		 2632 napi_complete(napi);
2633 sky2_read32(hw, B0_Y2_SP_LISR);
2634done:
6f535763 2635
bea3348e 2636 return work_done;
e07b1aa8
SH		 2637}
2638
7d12e780 2639static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2640{
2641 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2642 u32 status;
2643
2644 /* Reading this mask interrupts as side effect */
2645 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2646 if (status == 0 || status == ~0)
2647 return IRQ_NONE;
793b883e 2648
e07b1aa8 2649 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2650
2651 napi_schedule(&hw->napi);
793b883e 2652
cd28ab6a
SH		 2653 return IRQ_HANDLED;
2654}
2655
2656#ifdef CONFIG_NET_POLL_CONTROLLER
2657static void sky2_netpoll(struct net_device *dev)
2658{
2659 struct sky2_port *sky2 = netdev_priv(dev);
2660
bea3348e 2661 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2662}
2663#endif
2664
2665/* Chip internal frequency for clock calculations */
05745c4a 2666static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2667{
793b883e 2668 switch (hw->chip_id) {
cd28ab6a 2669 case CHIP_ID_YUKON_EC:
5a5b1ea0 2670 case CHIP_ID_YUKON_EC_U:
93745494 2671 case CHIP_ID_YUKON_EX:
05745c4a
SH		 2672 return 125;
2673
cd28ab6a 2674 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2675 return 100;
2676
2677 case CHIP_ID_YUKON_FE_P:
2678 return 50;
2679
2680 case CHIP_ID_YUKON_XL:
2681 return 156;
2682
2683 default:
2684 BUG();
cd28ab6a
SH		 2685 }
2686}
2687
fb17358f 2688static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2689{
fb17358f 2690 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2691}
2692
fb17358f 2693static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2694{
fb17358f 2695 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2696}
2697
fb17358f 2698
e3173832 2699static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2700{
b89165f2 2701 u8 t8;
cd28ab6a 2702
167f53d0 2703 /* Enable all clocks and check for bad PCI access */
b32f40c4 2704 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2705
cd28ab6a 2706 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2707
cd28ab6a 2708 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2709 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2710
2711 switch(hw->chip_id) {
2712 case CHIP_ID_YUKON_XL:
2713 hw->flags = SKY2_HW_GIGABIT
e0c28116
SH		 2714 | SKY2_HW_NEWER_PHY;
2715 if (hw->chip_rev < 3)
2716 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2717
ea76e635
SH		 2718 break;
2719
2720 case CHIP_ID_YUKON_EC_U:
2721 hw->flags = SKY2_HW_GIGABIT
2722 | SKY2_HW_NEWER_PHY
2723 | SKY2_HW_ADV_POWER_CTL;
2724 break;
2725
2726 case CHIP_ID_YUKON_EX:
2727 hw->flags = SKY2_HW_GIGABIT
2728 | SKY2_HW_NEWER_PHY
2729 | SKY2_HW_NEW_LE
2730 | SKY2_HW_ADV_POWER_CTL;
2731
2732 /* New transmit checksum */
2733 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2734 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2735 break;
2736
2737 case CHIP_ID_YUKON_EC:
2738 /* This rev is really old, and requires untested workarounds */
2739 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2740 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2741 return -EOPNOTSUPP;
2742 }
e0c28116 2743 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
ea76e635
SH		 2744 break;
2745
2746 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2747 break;
2748
05745c4a
SH		 2749 case CHIP_ID_YUKON_FE_P:
2750 hw->flags = SKY2_HW_NEWER_PHY
2751 | SKY2_HW_NEW_LE
2752 | SKY2_HW_AUTO_TX_SUM
2753 | SKY2_HW_ADV_POWER_CTL;
2754 break;
ea76e635 2755 default:
b02a9258
SH		 2756 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2757 hw->chip_id);
cd28ab6a
SH		 2758 return -EOPNOTSUPP;
2759 }
2760
ea76e635
SH		 2761 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2762 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2763 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2764
290d4de5 2765
e3173832
SH		 2766 hw->ports = 1;
2767 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2768 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2769 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2770 ++hw->ports;
2771 }
2772
2773 return 0;
2774}
2775
2776static void sky2_reset(struct sky2_hw *hw)
2777{
555382cb 2778 struct pci_dev *pdev = hw->pdev;
e3173832 2779 u16 status;
555382cb
SH		 2780 int i, cap;
2781 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2782
cd28ab6a 2783 /* disable ASF */
4f44d8ba
SH		 2784 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2785 status = sky2_read16(hw, HCU_CCSR);
2786 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2787 HCU_CCSR_UC_STATE_MSK);
2788 sky2_write16(hw, HCU_CCSR, status);
2789 } else
2790 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2791 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2792
2793 /* do a SW reset */
2794 sky2_write8(hw, B0_CTST, CS_RST_SET);
2795 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2796
ac93a394
SH		 2797 /* allow writes to PCI config */
2798 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2799
cd28ab6a 2800 /* clear PCI errors, if any */
b32f40c4 2801 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2802 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2803 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2804
2805 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2806
555382cb
SH		 2807 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2808 if (cap) {
7782c8c4
SH		 2809 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2810 0xfffffffful);
555382cb
SH		 2811
2812 /* If error bit is stuck on ignore it */
2813 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2814 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2815 else
555382cb
SH		 2816 hwe_mask |= Y2_IS_PCI_EXP;
2817 }
cd28ab6a 2818
ae306cca 2819 sky2_power_on(hw);
cd28ab6a
SH		 2820
2821 for (i = 0; i < hw->ports; i++) {
2822 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2823 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2824
2825 if (hw->chip_id == CHIP_ID_YUKON_EX)
2826 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2827 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2828 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2829 }
2830
793b883e
SH		 2831 /* Clear I2C IRQ noise */
2832 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2833
2834 /* turn off hardware timer (unused) */
2835 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2836 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2837
cd28ab6a
SH		 2838 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2839
69634ee7
SH		 2840 /* Turn off descriptor polling */
2841 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2842
2843 /* Turn off receive timestamp */
2844 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2845 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2846
2847 /* enable the Tx Arbiters */
2848 for (i = 0; i < hw->ports; i++)
2849 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2850
2851 /* Initialize ram interface */
2852 for (i = 0; i < hw->ports; i++) {
793b883e 2853 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2854
2855 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2856 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2857 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2858 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2859 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2860 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2861 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2862 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2863 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2864 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2865 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2866 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2867 }
2868
555382cb 2869 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2870
cd28ab6a 2871 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2872 sky2_gmac_reset(hw, i);
cd28ab6a 2873
cd28ab6a
SH		 2874 memset(hw->st_le, 0, STATUS_LE_BYTES);
2875 hw->st_idx = 0;
2876
2877 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2878 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2879
2880 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2881 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2882
2883 /* Set the list last index */
793b883e 2884 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2885
290d4de5
SH		 2886 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2887 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2888
290d4de5
SH		 2889 /* set Status-FIFO ISR watermark */
2890 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2891 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2892 else
2893 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2894
290d4de5 2895 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2896 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2897 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2898
793b883e 2899 /* enable status unit */
cd28ab6a
SH		 2900 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2901
2902 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2903 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2904 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2905}
2906
81906791
SH		 2907static void sky2_restart(struct work_struct *work)
2908{
2909 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2910 struct net_device *dev;
2911 int i, err;
2912
81906791 2913 rtnl_lock();
81906791
SH		 2914 for (i = 0; i < hw->ports; i++) {
2915 dev = hw->dev[i];
2916 if (netif_running(dev))
2917 sky2_down(dev);
2918 }
2919
8cfcbe99
SH		 2920 napi_disable(&hw->napi);
2921 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 2922 sky2_reset(hw);
2923 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 2924 napi_enable(&hw->napi);
81906791
SH		 2925
2926 for (i = 0; i < hw->ports; i++) {
2927 dev = hw->dev[i];
2928 if (netif_running(dev)) {
2929 err = sky2_up(dev);
2930 if (err) {
2931 printk(KERN_INFO PFX "%s: could not restart %d\n",
2932 dev->name, err);
2933 dev_close(dev);
2934 }
2935 }
2936 }
2937
81906791
SH		 2938 rtnl_unlock();
2939}
2940
e3173832
SH		 2941static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2942{
2943 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2944}
2945
2946static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2947{
2948 const struct sky2_port *sky2 = netdev_priv(dev);
2949
2950 wol->supported = sky2_wol_supported(sky2->hw);
2951 wol->wolopts = sky2->wol;
2952}
2953
2954static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2955{
2956 struct sky2_port *sky2 = netdev_priv(dev);
2957 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2958
e3173832
SH		 2959 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2960 return -EOPNOTSUPP;
2961
2962 sky2->wol = wol->wolopts;
2963
05745c4a
SH		 2964 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2965 hw->chip_id == CHIP_ID_YUKON_EX ||
2966 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 2967 sky2_write32(hw, B0_CTST, sky2->wol
2968 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2969
2970 if (!netif_running(dev))
2971 sky2_wol_init(sky2);
cd28ab6a
SH		 2972 return 0;
2973}
2974
28bd181a 2975static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2976{
b89165f2
SH		 2977 if (sky2_is_copper(hw)) {
2978 u32 modes = SUPPORTED_10baseT_Half
2979 | SUPPORTED_10baseT_Full
2980 | SUPPORTED_100baseT_Half
2981 | SUPPORTED_100baseT_Full
2982 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2983
ea76e635 2984 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 2985 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2986 | SUPPORTED_1000baseT_Full;
2987 return modes;
cd28ab6a 2988 } else
b89165f2
SH		 2989 return SUPPORTED_1000baseT_Half
2990 | SUPPORTED_1000baseT_Full
2991 | SUPPORTED_Autoneg
2992 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2993}
2994
793b883e 2995static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2996{
2997 struct sky2_port *sky2 = netdev_priv(dev);
2998 struct sky2_hw *hw = sky2->hw;
2999
3000 ecmd->transceiver = XCVR_INTERNAL;
3001 ecmd->supported = sky2_supported_modes(hw);
3002 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3003 if (sky2_is_copper(hw)) {
cd28ab6a 3004 ecmd->port = PORT_TP;
b89165f2
SH		 3005 ecmd->speed = sky2->speed;
3006 } else {
3007 ecmd->speed = SPEED_1000;
cd28ab6a 3008 ecmd->port = PORT_FIBRE;
b89165f2 3009 }
cd28ab6a
SH		 3010
3011 ecmd->advertising = sky2->advertising;
3012 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3013 ecmd->duplex = sky2->duplex;
3014 return 0;
3015}
3016
3017static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3018{
3019 struct sky2_port *sky2 = netdev_priv(dev);
3020 const struct sky2_hw *hw = sky2->hw;
3021 u32 supported = sky2_supported_modes(hw);
3022
3023 if (ecmd->autoneg == AUTONEG_ENABLE) {
3024 ecmd->advertising = supported;
3025 sky2->duplex = -1;
3026 sky2->speed = -1;
3027 } else {
3028 u32 setting;
3029
793b883e 3030 switch (ecmd->speed) {
cd28ab6a
SH		 3031 case SPEED_1000:
3032 if (ecmd->duplex == DUPLEX_FULL)
3033 setting = SUPPORTED_1000baseT_Full;
3034 else if (ecmd->duplex == DUPLEX_HALF)
3035 setting = SUPPORTED_1000baseT_Half;
3036 else
3037 return -EINVAL;
3038 break;
3039 case SPEED_100:
3040 if (ecmd->duplex == DUPLEX_FULL)
3041 setting = SUPPORTED_100baseT_Full;
3042 else if (ecmd->duplex == DUPLEX_HALF)
3043 setting = SUPPORTED_100baseT_Half;
3044 else
3045 return -EINVAL;
3046 break;
3047
3048 case SPEED_10:
3049 if (ecmd->duplex == DUPLEX_FULL)
3050 setting = SUPPORTED_10baseT_Full;
3051 else if (ecmd->duplex == DUPLEX_HALF)
3052 setting = SUPPORTED_10baseT_Half;
3053 else
3054 return -EINVAL;
3055 break;
3056 default:
3057 return -EINVAL;
3058 }
3059
3060 if ((setting & supported) == 0)
3061 return -EINVAL;
3062
3063 sky2->speed = ecmd->speed;
3064 sky2->duplex = ecmd->duplex;
3065 }
3066
3067 sky2->autoneg = ecmd->autoneg;
3068 sky2->advertising = ecmd->advertising;
3069
d1b139c0 3070 if (netif_running(dev)) {
1b537565 3071 sky2_phy_reinit(sky2);
d1b139c0
SH		 3072 sky2_set_multicast(dev);
3073 }
cd28ab6a
SH		 3074
3075 return 0;
3076}
3077
3078static void sky2_get_drvinfo(struct net_device *dev,
3079 struct ethtool_drvinfo *info)
3080{
3081 struct sky2_port *sky2 = netdev_priv(dev);
3082
3083 strcpy(info->driver, DRV_NAME);
3084 strcpy(info->version, DRV_VERSION);
3085 strcpy(info->fw_version, "N/A");
3086 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3087}
3088
3089static const struct sky2_stat {
793b883e
SH		 3090 char name[ETH_GSTRING_LEN];
3091 u16 offset;
cd28ab6a
SH		 3092} sky2_stats[] = {
3093 { "tx_bytes", GM_TXO_OK_HI },
3094 { "rx_bytes", GM_RXO_OK_HI },
3095 { "tx_broadcast", GM_TXF_BC_OK },
3096 { "rx_broadcast", GM_RXF_BC_OK },
3097 { "tx_multicast", GM_TXF_MC_OK },
3098 { "rx_multicast", GM_RXF_MC_OK },
3099 { "tx_unicast", GM_TXF_UC_OK },
3100 { "rx_unicast", GM_RXF_UC_OK },
3101 { "tx_mac_pause", GM_TXF_MPAUSE },
3102 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3103 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3104 { "late_collision",GM_TXF_LAT_COL },
3105 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3106 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3107 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3108
d2604540 3109 { "rx_short", GM_RXF_SHT },
cd28ab6a 3110 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3111 { "rx_64_byte_packets", GM_RXF_64B },
3112 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3113 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3114 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3115 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3116 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3117 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3118 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3119 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3120 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3121 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3122
3123 { "tx_64_byte_packets", GM_TXF_64B },
3124 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3125 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3126 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3127 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3128 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3129 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3130 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3131};
3132
cd28ab6a
SH		 3133static u32 sky2_get_rx_csum(struct net_device *dev)
3134{
3135 struct sky2_port *sky2 = netdev_priv(dev);
3136
3137 return sky2->rx_csum;
3138}
3139
3140static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3141{
3142 struct sky2_port *sky2 = netdev_priv(dev);
3143
3144 sky2->rx_csum = data;
793b883e 3145
cd28ab6a
SH		 3146 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3147 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3148
3149 return 0;
3150}
3151
3152static u32 sky2_get_msglevel(struct net_device *netdev)
3153{
3154 struct sky2_port *sky2 = netdev_priv(netdev);
3155 return sky2->msg_enable;
3156}
3157
9a7ae0a9
SH		 3158static int sky2_nway_reset(struct net_device *dev)
3159{
3160 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3161
16ad91e1 3162 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3163 return -EINVAL;
3164
1b537565 3165 sky2_phy_reinit(sky2);
d1b139c0 3166 sky2_set_multicast(dev);
9a7ae0a9
SH		 3167
3168 return 0;
3169}
3170
793b883e 3171static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3172{
3173 struct sky2_hw *hw = sky2->hw;
3174 unsigned port = sky2->port;
3175 int i;
3176
3177 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3178 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3179 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3180 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3181
793b883e 3182 for (i = 2; i < count; i++)
cd28ab6a
SH		 3183 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3184}
3185
cd28ab6a
SH		 3186static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3187{
3188 struct sky2_port *sky2 = netdev_priv(netdev);
3189 sky2->msg_enable = value;
3190}
3191
b9f2c044 3192static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3193{
b9f2c044
JG		 3194 switch (sset) {
3195 case ETH_SS_STATS:
3196 return ARRAY_SIZE(sky2_stats);
3197 default:
3198 return -EOPNOTSUPP;
3199 }
cd28ab6a
SH		 3200}
3201
3202static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3203 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3204{
3205 struct sky2_port *sky2 = netdev_priv(dev);
3206
793b883e 3207 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3208}
3209
793b883e 3210static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3211{
3212 int i;
3213
3214 switch (stringset) {
3215 case ETH_SS_STATS:
3216 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3217 memcpy(data + i * ETH_GSTRING_LEN,
3218 sky2_stats[i].name, ETH_GSTRING_LEN);
3219 break;
3220 }
3221}
3222
cd28ab6a
SH		 3223static int sky2_set_mac_address(struct net_device *dev, void *p)
3224{
3225 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3226 struct sky2_hw *hw = sky2->hw;
3227 unsigned port = sky2->port;
3228 const struct sockaddr *addr = p;
cd28ab6a
SH		 3229
3230 if (!is_valid_ether_addr(addr->sa_data))
3231 return -EADDRNOTAVAIL;
3232
cd28ab6a 3233 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3234 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3235 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3236 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3237 dev->dev_addr, ETH_ALEN);
1b537565 3238
a8ab1ec0
SH		 3239 /* virtual address for data */
3240 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3241
3242 /* physical address: used for pause frames */
3243 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3244
3245 return 0;
cd28ab6a
SH		 3246}
3247
a052b52f
SH		 3248static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3249{
3250 u32 bit;
3251
3252 bit = ether_crc(ETH_ALEN, addr) & 63;
3253 filter[bit >> 3] |= 1 << (bit & 7);
3254}
3255
cd28ab6a
SH		 3256static void sky2_set_multicast(struct net_device *dev)
3257{
3258 struct sky2_port *sky2 = netdev_priv(dev);
3259 struct sky2_hw *hw = sky2->hw;
3260 unsigned port = sky2->port;
3261 struct dev_mc_list *list = dev->mc_list;
3262 u16 reg;
3263 u8 filter[8];
a052b52f
SH		 3264 int rx_pause;
3265 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3266
a052b52f 3267 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3268 memset(filter, 0, sizeof(filter));
3269
3270 reg = gma_read16(hw, port, GM_RX_CTRL);
3271 reg |= GM_RXCR_UCF_ENA;
3272
d571b694 3273 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3274 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3275 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3276 memset(filter, 0xff, sizeof(filter));
a052b52f 3277 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3278 reg &= ~GM_RXCR_MCF_ENA;
3279 else {
3280 int i;
3281 reg |= GM_RXCR_MCF_ENA;
3282
a052b52f
SH		 3283 if (rx_pause)
3284 sky2_add_filter(filter, pause_mc_addr);
3285
3286 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3287 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3288 }
3289
cd28ab6a 3290 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3291 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3292 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3293 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3294 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3295 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3296 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3297 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3298
3299 gma_write16(hw, port, GM_RX_CTRL, reg);
3300}
3301
3302/* Can have one global because blinking is controlled by
3303 * ethtool and that is always under RTNL mutex
3304 */
91c86df5 3305static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3306{
793b883e
SH		 3307 u16 pg;
3308
793b883e
SH		 3309 switch (hw->chip_id) {
3310 case CHIP_ID_YUKON_XL:
3311 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3312 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3313 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3314 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3315 PHY_M_LEDC_INIT_CTRL(7) |
3316 PHY_M_LEDC_STA1_CTRL(7) |
3317 PHY_M_LEDC_STA0_CTRL(7))
3318 : 0);
3319
3320 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3321 break;
3322
3323 default:
3324 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3325 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3326 on ? PHY_M_LED_ALL : 0);
793b883e 3327 }
cd28ab6a
SH		 3328}
3329
3330/* blink LED's for finding board */
3331static int sky2_phys_id(struct net_device *dev, u32 data)
3332{
3333 struct sky2_port *sky2 = netdev_priv(dev);
3334 struct sky2_hw *hw = sky2->hw;
3335 unsigned port = sky2->port;
793b883e 3336 u16 ledctrl, ledover = 0;
cd28ab6a 3337 long ms;
91c86df5 3338 int interrupted;
cd28ab6a
SH		 3339 int onoff = 1;
3340
793b883e 3341 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3342 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3343 else
3344 ms = data * 1000;
3345
3346 /* save initial values */
e07b1aa8 3347 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3348 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3349 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3350 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3351 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3352 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3353 } else {
3354 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3355 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3356 }
cd28ab6a 3357
91c86df5
SH		 3358 interrupted = 0;
3359 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3360 sky2_led(hw, port, onoff);
3361 onoff = !onoff;
3362
e07b1aa8 3363 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3364 interrupted = msleep_interruptible(250);
e07b1aa8 3365 spin_lock_bh(&sky2->phy_lock);
91c86df5 3366
cd28ab6a
SH		 3367 ms -= 250;
3368 }
3369
3370 /* resume regularly scheduled programming */
793b883e
SH		 3371 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3372 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3373 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3374 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3375 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3376 } else {
3377 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3378 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3379 }
e07b1aa8 3380 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3381
3382 return 0;
3383}
3384
3385static void sky2_get_pauseparam(struct net_device *dev,
3386 struct ethtool_pauseparam *ecmd)
3387{
3388 struct sky2_port *sky2 = netdev_priv(dev);
3389
16ad91e1
SH		 3390 switch (sky2->flow_mode) {
3391 case FC_NONE:
3392 ecmd->tx_pause = ecmd->rx_pause = 0;
3393 break;
3394 case FC_TX:
3395 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3396 break;
3397 case FC_RX:
3398 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3399 break;
3400 case FC_BOTH:
3401 ecmd->tx_pause = ecmd->rx_pause = 1;
3402 }
3403
cd28ab6a
SH		 3404 ecmd->autoneg = sky2->autoneg;
3405}
3406
3407static int sky2_set_pauseparam(struct net_device *dev,
3408 struct ethtool_pauseparam *ecmd)
3409{
3410 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3411
3412 sky2->autoneg = ecmd->autoneg;
16ad91e1 3413 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3414
16ad91e1
SH		 3415 if (netif_running(dev))
3416 sky2_phy_reinit(sky2);
cd28ab6a 3417
2eaba1a2 3418 return 0;
cd28ab6a
SH		 3419}
3420
fb17358f
SH		 3421static int sky2_get_coalesce(struct net_device *dev,
3422 struct ethtool_coalesce *ecmd)
3423{
3424 struct sky2_port *sky2 = netdev_priv(dev);
3425 struct sky2_hw *hw = sky2->hw;
3426
3427 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3428 ecmd->tx_coalesce_usecs = 0;
3429 else {
3430 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3431 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3432 }
3433 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3434
3435 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3436 ecmd->rx_coalesce_usecs = 0;
3437 else {
3438 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3439 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3440 }
3441 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3442
3443 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3444 ecmd->rx_coalesce_usecs_irq = 0;
3445 else {
3446 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3447 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3448 }
3449
3450 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3451
3452 return 0;
3453}
3454
3455/* Note: this affect both ports */
3456static int sky2_set_coalesce(struct net_device *dev,
3457 struct ethtool_coalesce *ecmd)
3458{
3459 struct sky2_port *sky2 = netdev_priv(dev);
3460 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3461 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3462
77b3d6a2
SH		 3463 if (ecmd->tx_coalesce_usecs > tmax ||
3464 ecmd->rx_coalesce_usecs > tmax ||
3465 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3466 return -EINVAL;
3467
ff81fbbe 3468 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3469 return -EINVAL;
ff81fbbe 3470 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3471 return -EINVAL;
ff81fbbe 3472 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3473 return -EINVAL;
3474
3475 if (ecmd->tx_coalesce_usecs == 0)
3476 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3477 else {
3478 sky2_write32(hw, STAT_TX_TIMER_INI,
3479 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3480 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3481 }
3482 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3483
3484 if (ecmd->rx_coalesce_usecs == 0)
3485 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3486 else {
3487 sky2_write32(hw, STAT_LEV_TIMER_INI,
3488 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3489 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3490 }
3491 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3492
3493 if (ecmd->rx_coalesce_usecs_irq == 0)
3494 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3495 else {
d28d4870 3496 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3497 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3498 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3499 }
3500 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3501 return 0;
3502}
3503
793b883e
SH		 3504static void sky2_get_ringparam(struct net_device *dev,
3505 struct ethtool_ringparam *ering)
3506{
3507 struct sky2_port *sky2 = netdev_priv(dev);
3508
3509 ering->rx_max_pending = RX_MAX_PENDING;
3510 ering->rx_mini_max_pending = 0;
3511 ering->rx_jumbo_max_pending = 0;
3512 ering->tx_max_pending = TX_RING_SIZE - 1;
3513
3514 ering->rx_pending = sky2->rx_pending;
3515 ering->rx_mini_pending = 0;
3516 ering->rx_jumbo_pending = 0;
3517 ering->tx_pending = sky2->tx_pending;
3518}
3519
3520static int sky2_set_ringparam(struct net_device *dev,
3521 struct ethtool_ringparam *ering)
3522{
3523 struct sky2_port *sky2 = netdev_priv(dev);
3524 int err = 0;
3525
3526 if (ering->rx_pending > RX_MAX_PENDING ||
3527 ering->rx_pending < 8 ||
3528 ering->tx_pending < MAX_SKB_TX_LE ||
3529 ering->tx_pending > TX_RING_SIZE - 1)
3530 return -EINVAL;
3531
3532 if (netif_running(dev))
3533 sky2_down(dev);
3534
3535 sky2->rx_pending = ering->rx_pending;
3536 sky2->tx_pending = ering->tx_pending;
3537
1b537565 3538 if (netif_running(dev)) {
793b883e 3539 err = sky2_up(dev);
1b537565
SH		 3540 if (err)
3541 dev_close(dev);
6ed995bb
SH		 3542 else
3543 sky2_set_multicast(dev);
1b537565 3544 }
793b883e
SH		 3545
3546 return err;
3547}
3548
793b883e
SH		 3549static int sky2_get_regs_len(struct net_device *dev)
3550{
6e4cbb34 3551 return 0x4000;
793b883e
SH		 3552}
3553
3554/*
3555 * Returns copy of control register region
3ead5db7 3556 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3557 */
3558static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3559 void *p)
3560{
3561 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3562 const void __iomem *io = sky2->hw->regs;
295b54c4 3563 unsigned int b;
793b883e
SH		 3564
3565 regs->version = 1;
793b883e 3566
295b54c4
SH		 3567 for (b = 0; b < 128; b++) {
3568 /* This complicated switch statement is to make sure and
3569 * only access regions that are unreserved.
3570 * Some blocks are only valid on dual port cards.
3571 * and block 3 has some special diagnostic registers that
3572 * are poison.
3573 */
3574 switch (b) {
3575 case 3:
3576 /* skip diagnostic ram region */
3577 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3578 break;
3ead5db7 3579
295b54c4
SH		 3580 /* dual port cards only */
3581 case 5: /* Tx Arbiter 2 */
3582 case 9: /* RX2 */
3583 case 14 ... 15: /* TX2 */
3584 case 17: case 19: /* Ram Buffer 2 */
3585 case 22 ... 23: /* Tx Ram Buffer 2 */
3586 case 25: /* Rx MAC Fifo 1 */
3587 case 27: /* Tx MAC Fifo 2 */
3588 case 31: /* GPHY 2 */
3589 case 40 ... 47: /* Pattern Ram 2 */
3590 case 52: case 54: /* TCP Segmentation 2 */
3591 case 112 ... 116: /* GMAC 2 */
3592 if (sky2->hw->ports == 1)
3593 goto reserved;
3594 /* fall through */
3595 case 0: /* Control */
3596 case 2: /* Mac address */
3597 case 4: /* Tx Arbiter 1 */
3598 case 7: /* PCI express reg */
3599 case 8: /* RX1 */
3600 case 12 ... 13: /* TX1 */
3601 case 16: case 18:/* Rx Ram Buffer 1 */
3602 case 20 ... 21: /* Tx Ram Buffer 1 */
3603 case 24: /* Rx MAC Fifo 1 */
3604 case 26: /* Tx MAC Fifo 1 */
3605 case 28 ... 29: /* Descriptor and status unit */
3606 case 30: /* GPHY 1*/
3607 case 32 ... 39: /* Pattern Ram 1 */
3608 case 48: case 50: /* TCP Segmentation 1 */
3609 case 56 ... 60: /* PCI space */
3610 case 80 ... 84: /* GMAC 1 */
3611 memcpy_fromio(p, io, 128);
3612 break;
3613 default:
3614reserved:
3615 memset(p, 0, 128);
3616 }
3ead5db7 3617
295b54c4
SH		 3618 p += 128;
3619 io += 128;
3620 }
793b883e 3621}
cd28ab6a 3622
b628ed98
SH		 3623/* In order to do Jumbo packets on these chips, need to turn off the
3624 * transmit store/forward. Therefore checksum offload won't work.
3625 */
3626static int no_tx_offload(struct net_device *dev)
3627{
3628 const struct sky2_port *sky2 = netdev_priv(dev);
3629 const struct sky2_hw *hw = sky2->hw;
3630
69161611 3631 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3632}
3633
3634static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3635{
3636 if (data && no_tx_offload(dev))
3637 return -EINVAL;
3638
3639 return ethtool_op_set_tx_csum(dev, data);
3640}
3641
3642
3643static int sky2_set_tso(struct net_device *dev, u32 data)
3644{
3645 if (data && no_tx_offload(dev))
3646 return -EINVAL;
3647
3648 return ethtool_op_set_tso(dev, data);
3649}
3650
f4331a6d
SH		 3651static int sky2_get_eeprom_len(struct net_device *dev)
3652{
3653 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3654 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3655 u16 reg2;
3656
b32f40c4 3657 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3658 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3659}
3660
b32f40c4 3661static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
f4331a6d 3662{
167f53d0 3663 u32 val;
f4331a6d 3664
b32f40c4 3665 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
167f53d0
SH		 3666
3667 do {
b32f40c4 3668 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0
SH		 3669 } while (!(offset & PCI_VPD_ADDR_F));
3670
b32f40c4 3671 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
167f53d0 3672 return val;
f4331a6d
SH		 3673}
3674
b32f40c4 3675static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
f4331a6d 3676{
b32f40c4
SH		 3677 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3678 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
f4331a6d 3679 do {
b32f40c4 3680 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0 3681 } while (offset & PCI_VPD_ADDR_F);
f4331a6d
SH		 3682}
3683
3684static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3685 u8 *data)
3686{
3687 struct sky2_port *sky2 = netdev_priv(dev);
3688 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3689 int length = eeprom->len;
3690 u16 offset = eeprom->offset;
3691
3692 if (!cap)
3693 return -EINVAL;
3694
3695 eeprom->magic = SKY2_EEPROM_MAGIC;
3696
3697 while (length > 0) {
b32f40c4 3698 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3699 int n = min_t(int, length, sizeof(val));
3700
3701 memcpy(data, &val, n);
3702 length -= n;
3703 data += n;
3704 offset += n;
3705 }
3706 return 0;
3707}
3708
3709static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3710 u8 *data)
3711{
3712 struct sky2_port *sky2 = netdev_priv(dev);
3713 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3714 int length = eeprom->len;
3715 u16 offset = eeprom->offset;
3716
3717 if (!cap)
3718 return -EINVAL;
3719
3720 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3721 return -EINVAL;
3722
3723 while (length > 0) {
3724 u32 val;
3725 int n = min_t(int, length, sizeof(val));
3726
3727 if (n < sizeof(val))
b32f40c4 3728 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3729 memcpy(&val, data, n);
3730
b32f40c4 3731 sky2_vpd_write(sky2->hw, cap, offset, val);
f4331a6d
SH		 3732
3733 length -= n;
3734 data += n;
3735 offset += n;
3736 }
3737 return 0;
3738}
3739
3740
7282d491 3741static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3742 .get_settings = sky2_get_settings,
3743 .set_settings = sky2_set_settings,
3744 .get_drvinfo = sky2_get_drvinfo,
3745 .get_wol = sky2_get_wol,
3746 .set_wol = sky2_set_wol,
3747 .get_msglevel = sky2_get_msglevel,
3748 .set_msglevel = sky2_set_msglevel,
3749 .nway_reset = sky2_nway_reset,
3750 .get_regs_len = sky2_get_regs_len,
3751 .get_regs = sky2_get_regs,
3752 .get_link = ethtool_op_get_link,
3753 .get_eeprom_len = sky2_get_eeprom_len,
3754 .get_eeprom = sky2_get_eeprom,
3755 .set_eeprom = sky2_set_eeprom,
f4331a6d 3756 .set_sg = ethtool_op_set_sg,
f4331a6d 3757 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3758 .set_tso = sky2_set_tso,
3759 .get_rx_csum = sky2_get_rx_csum,
3760 .set_rx_csum = sky2_set_rx_csum,
3761 .get_strings = sky2_get_strings,
3762 .get_coalesce = sky2_get_coalesce,
3763 .set_coalesce = sky2_set_coalesce,
3764 .get_ringparam = sky2_get_ringparam,
3765 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3766 .get_pauseparam = sky2_get_pauseparam,
3767 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3768 .phys_id = sky2_phys_id,
b9f2c044 3769 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3770 .get_ethtool_stats = sky2_get_ethtool_stats,
3771};
3772
3cf26753
SH		 3773#ifdef CONFIG_SKY2_DEBUG
3774
3775static struct dentry *sky2_debug;
3776
3777static int sky2_debug_show(struct seq_file *seq, void *v)
3778{
3779 struct net_device *dev = seq->private;
3780 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3781 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3782 unsigned port = sky2->port;
3783 unsigned idx, last;
3784 int sop;
3785
3786 if (!netif_running(dev))
3787 return -ENETDOWN;
3788
3789 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3790 sky2_read32(hw, B0_ISRC),
3791 sky2_read32(hw, B0_IMSK),
3792 sky2_read32(hw, B0_Y2_SP_ICR));
3793
bea3348e 3794 napi_disable(&hw->napi);
3cf26753
SH		 3795 last = sky2_read16(hw, STAT_PUT_IDX);
3796
3797 if (hw->st_idx == last)
3798 seq_puts(seq, "Status ring (empty)\n");
3799 else {
3800 seq_puts(seq, "Status ring\n");
3801 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3802 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3803 const struct sky2_status_le *le = hw->st_le + idx;
3804 seq_printf(seq, "[%d] %#x %d %#x\n",
3805 idx, le->opcode, le->length, le->status);
3806 }
3807 seq_puts(seq, "\n");
3808 }
3809
3810 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3811 sky2->tx_cons, sky2->tx_prod,
3812 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3813 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3814
3815 /* Dump contents of tx ring */
3816 sop = 1;
3817 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3818 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3819 const struct sky2_tx_le *le = sky2->tx_le + idx;
3820 u32 a = le32_to_cpu(le->addr);
3821
3822 if (sop)
3823 seq_printf(seq, "%u:", idx);
3824 sop = 0;
3825
3826 switch(le->opcode & ~HW_OWNER) {
3827 case OP_ADDR64:
3828 seq_printf(seq, " %#x:", a);
3829 break;
3830 case OP_LRGLEN:
3831 seq_printf(seq, " mtu=%d", a);
3832 break;
3833 case OP_VLAN:
3834 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3835 break;
3836 case OP_TCPLISW:
3837 seq_printf(seq, " csum=%#x", a);
3838 break;
3839 case OP_LARGESEND:
3840 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3841 break;
3842 case OP_PACKET:
3843 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3844 break;
3845 case OP_BUFFER:
3846 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3847 break;
3848 default:
3849 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3850 a, le16_to_cpu(le->length));
3851 }
3852
3853 if (le->ctrl & EOP) {
3854 seq_putc(seq, '\n');
3855 sop = 1;
3856 }
3857 }
3858
3859 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3860 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3861 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3862 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3863
bea3348e 3864 napi_enable(&hw->napi);
3cf26753
SH		 3865 return 0;
3866}
3867
3868static int sky2_debug_open(struct inode *inode, struct file *file)
3869{
3870 return single_open(file, sky2_debug_show, inode->i_private);
3871}
3872
3873static const struct file_operations sky2_debug_fops = {
3874 .owner = THIS_MODULE,
3875 .open = sky2_debug_open,
3876 .read = seq_read,
3877 .llseek = seq_lseek,
3878 .release = single_release,
3879};
3880
3881/*
3882 * Use network device events to create/remove/rename
3883 * debugfs file entries
3884 */
3885static int sky2_device_event(struct notifier_block *unused,
3886 unsigned long event, void *ptr)
3887{
3888 struct net_device *dev = ptr;
5b296bc9 3889 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 3890
5b296bc9
SH		 3891 if (dev->open != sky2_up || !sky2_debug)
3892 return NOTIFY_DONE;
3cf26753 3893
5b296bc9
SH		 3894 switch(event) {
3895 case NETDEV_CHANGENAME:
3896 if (sky2->debugfs) {
3897 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3898 sky2_debug, dev->name);
3899 }
3900 break;
3cf26753 3901
5b296bc9
SH		 3902 case NETDEV_GOING_DOWN:
3903 if (sky2->debugfs) {
3904 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3905 dev->name);
3906 debugfs_remove(sky2->debugfs);
3907 sky2->debugfs = NULL;
3cf26753 3908 }
5b296bc9
SH		 3909 break;
3910
3911 case NETDEV_UP:
3912 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3913 sky2_debug, dev,
3914 &sky2_debug_fops);
3915 if (IS_ERR(sky2->debugfs))
3916 sky2->debugfs = NULL;
3cf26753
SH		 3917 }
3918
3919 return NOTIFY_DONE;
3920}
3921
3922static struct notifier_block sky2_notifier = {
3923 .notifier_call = sky2_device_event,
3924};
3925
3926
3927static __init void sky2_debug_init(void)
3928{
3929 struct dentry *ent;
3930
3931 ent = debugfs_create_dir("sky2", NULL);
3932 if (!ent || IS_ERR(ent))
3933 return;
3934
3935 sky2_debug = ent;
3936 register_netdevice_notifier(&sky2_notifier);
3937}
3938
3939static __exit void sky2_debug_cleanup(void)
3940{
3941 if (sky2_debug) {
3942 unregister_netdevice_notifier(&sky2_notifier);
3943 debugfs_remove(sky2_debug);
3944 sky2_debug = NULL;
3945 }
3946}
3947
3948#else
3949#define sky2_debug_init()
3950#define sky2_debug_cleanup()
3951#endif
3952
3953
cd28ab6a
SH		 3954/* Initialize network device */
3955static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3956 unsigned port,
3957 int highmem, int wol)
cd28ab6a
SH		 3958{
3959 struct sky2_port *sky2;
3960 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3961
3962 if (!dev) {
898eb71c 3963 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 3964 return NULL;
3965 }
3966
cd28ab6a 3967 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3968 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3969 dev->open = sky2_up;
3970 dev->stop = sky2_down;
ef743d33 3971 dev->do_ioctl = sky2_ioctl;
cd28ab6a 3972 dev->hard_start_xmit = sky2_xmit_frame;
cd28ab6a
SH		 3973 dev->set_multicast_list = sky2_set_multicast;
3974 dev->set_mac_address = sky2_set_mac_address;
3975 dev->change_mtu = sky2_change_mtu;
3976 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3977 dev->tx_timeout = sky2_tx_timeout;
3978 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 3979#ifdef CONFIG_NET_POLL_CONTROLLER
a5e68c02
SH		 3980 if (port == 0)
3981 dev->poll_controller = sky2_netpoll;
cd28ab6a 3982#endif
cd28ab6a
SH		 3983
3984 sky2 = netdev_priv(dev);
3985 sky2->netdev = dev;
3986 sky2->hw = hw;
3987 sky2->msg_enable = netif_msg_init(debug, default_msg);
3988
cd28ab6a
SH		 3989 /* Auto speed and flow control */
3990 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3991 sky2->flow_mode = FC_BOTH;
3992
cd28ab6a
SH		 3993 sky2->duplex = -1;
3994 sky2->speed = -1;
3995 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 3996 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
e3173832 3997 sky2->wol = wol;
75d070c5 3998
e07b1aa8 3999 spin_lock_init(&sky2->phy_lock);
793b883e 4000 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4001 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4002
4003 hw->dev[port] = dev;
4004
4005 sky2->port = port;
4006
4a50a876 4007 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4008 if (highmem)
4009 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4010
d1f13708 4011#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4012 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4013 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4014 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4015 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4016 dev->vlan_rx_register = sky2_vlan_rx_register;
4017 }
d1f13708
SH		 4018#endif
4019
cd28ab6a 4020 /* read the mac address */
793b883e 4021 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4022 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4023
cd28ab6a
SH		 4024 return dev;
4025}
4026
28bd181a 4027static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4028{
4029 const struct sky2_port *sky2 = netdev_priv(dev);
0795af57 4030 DECLARE_MAC_BUF(mac);
cd28ab6a
SH		 4031
4032 if (netif_msg_probe(sky2))
0795af57
JP		 4033 printk(KERN_INFO PFX "%s: addr %s\n",
4034 dev->name, print_mac(mac, dev->dev_addr));
cd28ab6a
SH		 4035}
4036
fb2690a9 4037/* Handle software interrupt used during MSI test */
7d12e780 4038static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4039{
4040 struct sky2_hw *hw = dev_id;
4041 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4042
4043 if (status == 0)
4044 return IRQ_NONE;
4045
4046 if (status & Y2_IS_IRQ_SW) {
ea76e635 4047 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4048 wake_up(&hw->msi_wait);
4049 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4050 }
4051 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4052
4053 return IRQ_HANDLED;
4054}
4055
4056/* Test interrupt path by forcing a a software IRQ */
4057static int __devinit sky2_test_msi(struct sky2_hw *hw)
4058{
4059 struct pci_dev *pdev = hw->pdev;
4060 int err;
4061
bb507fe1
SH		 4062 init_waitqueue_head (&hw->msi_wait);
4063
fb2690a9
SH		 4064 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4065
b0a20ded 4066 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4067 if (err) {
b02a9258 4068 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4069 return err;
4070 }
4071
fb2690a9 4072 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4073 sky2_read8(hw, B0_CTST);
fb2690a9 4074
ea76e635 4075 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4076
ea76e635 4077 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4078 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4079 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4080 "switching to INTx mode.\n");
fb2690a9
SH		 4081
4082 err = -EOPNOTSUPP;
4083 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4084 }
4085
4086 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4087 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4088
4089 free_irq(pdev->irq, hw);
4090
4091 return err;
4092}
4093
e3173832
SH		 4094static int __devinit pci_wake_enabled(struct pci_dev *dev)
4095{
4096 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4097 u16 value;
4098
4099 if (!pm)
4100 return 0;
4101 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4102 return 0;
4103 return value & PCI_PM_CTRL_PME_ENABLE;
4104}
4105
cd28ab6a
SH		 4106static int __devinit sky2_probe(struct pci_dev *pdev,
4107 const struct pci_device_id *ent)
4108{
7f60c64b 4109 struct net_device *dev;
cd28ab6a 4110 struct sky2_hw *hw;
e3173832 4111 int err, using_dac = 0, wol_default;
cd28ab6a 4112
793b883e
SH		 4113 err = pci_enable_device(pdev);
4114 if (err) {
b02a9258 4115 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4116 goto err_out;
4117 }
4118
793b883e
SH		 4119 err = pci_request_regions(pdev, DRV_NAME);
4120 if (err) {
b02a9258 4121 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4122 goto err_out_disable;
cd28ab6a
SH		 4123 }
4124
4125 pci_set_master(pdev);
4126
d1f3d4dd
SH		 4127 if (sizeof(dma_addr_t) > sizeof(u32) &&
4128 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4129 using_dac = 1;
4130 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4131 if (err < 0) {
b02a9258
SH		 4132 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4133 "for consistent allocations\n");
d1f3d4dd
SH		 4134 goto err_out_free_regions;
4135 }
d1f3d4dd 4136 } else {
cd28ab6a
SH		 4137 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4138 if (err) {
b02a9258 4139 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4140 goto err_out_free_regions;
4141 }
4142 }
d1f3d4dd 4143
e3173832
SH		 4144 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4145
cd28ab6a 4146 err = -ENOMEM;
6aad85d6 4147 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4148 if (!hw) {
b02a9258 4149 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4150 goto err_out_free_regions;
4151 }
4152
cd28ab6a 4153 hw->pdev = pdev;
cd28ab6a
SH		 4154
4155 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4156 if (!hw->regs) {
b02a9258 4157 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4158 goto err_out_free_hw;
4159 }
4160
56a645cc 4161#ifdef __BIG_ENDIAN
f65b138c
SH		 4162 /* The sk98lin vendor driver uses hardware byte swapping but
4163 * this driver uses software swapping.
4164 */
56a645cc
SH		 4165 {
4166 u32 reg;
b32f40c4 4167 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4168 reg &= ~PCI_REV_DESC;
b32f40c4 4169 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
56a645cc
SH		 4170 }
4171#endif
4172
08c06d8a 4173 /* ring for status responses */
167f53d0 4174 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4175 if (!hw->st_le)
4176 goto err_out_iounmap;
4177
e3173832 4178 err = sky2_init(hw);
cd28ab6a 4179 if (err)
793b883e 4180 goto err_out_iounmap;
cd28ab6a 4181
b02a9258 4182 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4183 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4184 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4185 hw->chip_id, hw->chip_rev);
cd28ab6a 4186
e3173832
SH		 4187 sky2_reset(hw);
4188
4189 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4190 if (!dev) {
4191 err = -ENOMEM;
cd28ab6a 4192 goto err_out_free_pci;
7f60c64b 4193 }
cd28ab6a 4194
9fa1b1f3
SH		 4195 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4196 err = sky2_test_msi(hw);
4197 if (err == -EOPNOTSUPP)
4198 pci_disable_msi(pdev);
4199 else if (err)
4200 goto err_out_free_netdev;
4201 }
4202
793b883e
SH		 4203 err = register_netdev(dev);
4204 if (err) {
b02a9258 4205 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4206 goto err_out_free_netdev;
4207 }
4208
6de16237
SH		 4209 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4210
ea76e635
SH		 4211 err = request_irq(pdev->irq, sky2_intr,
4212 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4213 dev->name, hw);
9fa1b1f3 4214 if (err) {
b02a9258 4215 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4216 goto err_out_unregister;
4217 }
4218 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4219 napi_enable(&hw->napi);
9fa1b1f3 4220
cd28ab6a
SH		 4221 sky2_show_addr(dev);
4222
7f60c64b 4223 if (hw->ports > 1) {
4224 struct net_device *dev1;
4225
e3173832 4226 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4227 if (!dev1)
4228 dev_warn(&pdev->dev, "allocation for second device failed\n");
4229 else if ((err = register_netdev(dev1))) {
4230 dev_warn(&pdev->dev,
4231 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4232 hw->dev[1] = NULL;
4233 free_netdev(dev1);
b02a9258
SH		 4234 } else
4235 sky2_show_addr(dev1);
cd28ab6a
SH		 4236 }
4237
32c2c300 4238 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4239 INIT_WORK(&hw->restart_work, sky2_restart);
4240
793b883e
SH		 4241 pci_set_drvdata(pdev, hw);
4242
cd28ab6a
SH		 4243 return 0;
4244
793b883e 4245err_out_unregister:
ea76e635 4246 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4247 pci_disable_msi(pdev);
793b883e 4248 unregister_netdev(dev);
cd28ab6a
SH		 4249err_out_free_netdev:
4250 free_netdev(dev);
cd28ab6a 4251err_out_free_pci:
793b883e 4252 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4253 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4254err_out_iounmap:
4255 iounmap(hw->regs);
4256err_out_free_hw:
4257 kfree(hw);
4258err_out_free_regions:
4259 pci_release_regions(pdev);
44a1d2e5 4260err_out_disable:
cd28ab6a 4261 pci_disable_device(pdev);
cd28ab6a 4262err_out:
549a68c3 4263 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4264 return err;
4265}
4266
4267static void __devexit sky2_remove(struct pci_dev *pdev)
4268{
793b883e 4269 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4270 int i;
cd28ab6a 4271
793b883e 4272 if (!hw)
cd28ab6a
SH		 4273 return;
4274
32c2c300 4275 del_timer_sync(&hw->watchdog_timer);
6de16237 4276 cancel_work_sync(&hw->restart_work);
d27ed387 4277
b877fe28 4278 for (i = hw->ports-1; i >= 0; --i)
6de16237 4279 unregister_netdev(hw->dev[i]);
81906791 4280
d27ed387 4281 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4282
ae306cca
SH		 4283 sky2_power_aux(hw);
4284
cd28ab6a 4285 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4286 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4287 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4288
4289 free_irq(pdev->irq, hw);
ea76e635 4290 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4291 pci_disable_msi(pdev);
793b883e 4292 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4293 pci_release_regions(pdev);
4294 pci_disable_device(pdev);
793b883e 4295
b877fe28 4296 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4297 free_netdev(hw->dev[i]);
4298
cd28ab6a
SH		 4299 iounmap(hw->regs);
4300 kfree(hw);
5afa0a9c 4301
cd28ab6a
SH		 4302 pci_set_drvdata(pdev, NULL);
4303}
4304
4305#ifdef CONFIG_PM
4306static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4307{
793b883e 4308 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4309 int i, wol = 0;
cd28ab6a 4310
549a68c3
SH		 4311 if (!hw)
4312 return 0;
4313
f05267e7 4314 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4315 struct net_device *dev = hw->dev[i];
e3173832 4316 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4317
e3173832 4318 if (netif_running(dev))
5afa0a9c 4319 sky2_down(dev);
e3173832
SH		 4320
4321 if (sky2->wol)
4322 sky2_wol_init(sky2);
4323
4324 wol |= sky2->wol;
cd28ab6a
SH		 4325 }
4326
8ab8fca2 4327 sky2_write32(hw, B0_IMSK, 0);
6de16237 4328 napi_disable(&hw->napi);
ae306cca 4329 sky2_power_aux(hw);
e3173832 4330
d374c1c1 4331 pci_save_state(pdev);
e3173832 4332 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4333 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4334
2ccc99b7 4335 return 0;
cd28ab6a
SH		 4336}
4337
4338static int sky2_resume(struct pci_dev *pdev)
4339{
793b883e 4340 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4341 int i, err;
cd28ab6a 4342
549a68c3
SH		 4343 if (!hw)
4344 return 0;
4345
ae306cca
SH		 4346 err = pci_set_power_state(pdev, PCI_D0);
4347 if (err)
4348 goto out;
4349
4350 err = pci_restore_state(pdev);
4351 if (err)
4352 goto out;
4353
cd28ab6a 4354 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4355
4356 /* Re-enable all clocks */
05745c4a
SH		 4357 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4358 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4359 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4360 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4361
e3173832 4362 sky2_reset(hw);
8ab8fca2 4363 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4364 napi_enable(&hw->napi);
8ab8fca2 4365
f05267e7 4366 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4367 struct net_device *dev = hw->dev[i];
6a5706b9 4368 if (netif_running(dev)) {
08c06d8a
SH		 4369 err = sky2_up(dev);
4370 if (err) {
4371 printk(KERN_ERR PFX "%s: could not up: %d\n",
4372 dev->name, err);
4373 dev_close(dev);
eb35cf60 4374 goto out;
5afa0a9c 4375 }
d1b139c0
SH		 4376
4377 sky2_set_multicast(dev);
cd28ab6a
SH		 4378 }
4379 }
eb35cf60 4380
ae306cca 4381 return 0;
08c06d8a 4382out:
b02a9258 4383 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4384 pci_disable_device(pdev);
08c06d8a 4385 return err;
cd28ab6a
SH		 4386}
4387#endif
4388
e3173832
SH		 4389static void sky2_shutdown(struct pci_dev *pdev)
4390{
4391 struct sky2_hw *hw = pci_get_drvdata(pdev);
4392 int i, wol = 0;
4393
549a68c3
SH		 4394 if (!hw)
4395 return;
4396
5c0d6b34 4397 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4398
4399 for (i = 0; i < hw->ports; i++) {
4400 struct net_device *dev = hw->dev[i];
4401 struct sky2_port *sky2 = netdev_priv(dev);
4402
4403 if (sky2->wol) {
4404 wol = 1;
4405 sky2_wol_init(sky2);
4406 }
4407 }
4408
4409 if (wol)
4410 sky2_power_aux(hw);
4411
4412 pci_enable_wake(pdev, PCI_D3hot, wol);
4413 pci_enable_wake(pdev, PCI_D3cold, wol);
4414
4415 pci_disable_device(pdev);
4416 pci_set_power_state(pdev, PCI_D3hot);
4417
4418}
4419
cd28ab6a 4420static struct pci_driver sky2_driver = {
793b883e
SH		 4421 .name = DRV_NAME,
4422 .id_table = sky2_id_table,
4423 .probe = sky2_probe,
4424 .remove = __devexit_p(sky2_remove),
cd28ab6a 4425#ifdef CONFIG_PM
793b883e
SH		 4426 .suspend = sky2_suspend,
4427 .resume = sky2_resume,
cd28ab6a 4428#endif
e3173832 4429 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4430};
4431
4432static int __init sky2_init_module(void)
4433{
3cf26753 4434 sky2_debug_init();
50241c4c 4435 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4436}
4437
4438static void __exit sky2_cleanup_module(void)
4439{
4440 pci_unregister_driver(&sky2_driver);
3cf26753 4441 sky2_debug_cleanup();
cd28ab6a
SH		 4442}
4443
4444module_init(sky2_init_module);
4445module_exit(sky2_cleanup_module);
4446
4447MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4448MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4449MODULE_LICENSE("GPL");
5f4f9dc1 4450MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree