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[PATCH] sky2: allow dual port usage
[net-next-2.6.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/config.h>
14c85021 28#include <linux/in.h>
baef58b1
SH		 29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/if_vlan.h>
37#include <linux/ip.h>
38#include <linux/delay.h>
39#include <linux/crc32.h>
4075400b 40#include <linux/dma-mapping.h>
2cd8e5d3 41#include <linux/mii.h>
baef58b1
SH		 42#include <asm/irq.h>
43
44#include "skge.h"
45
46#define DRV_NAME "skge"
eff4b1fe 47#define DRV_VERSION "1.5"
baef58b1
SH		 48#define PFX DRV_NAME " "
49
50#define DEFAULT_TX_RING_SIZE 128
51#define DEFAULT_RX_RING_SIZE 512
52#define MAX_TX_RING_SIZE 1024
53#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 54#define RX_COPY_THRESHOLD 128
55#define RX_BUF_SIZE 1536
baef58b1
SH		 56#define PHY_RETRIES 1000
57#define ETH_JUMBO_MTU 9000
58#define TX_WATCHDOG (5 * HZ)
59#define NAPI_WEIGHT 64
6abebb53 60#define BLINK_MS 250
baef58b1
SH		 61
62MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
64MODULE_LICENSE("GPL");
65MODULE_VERSION(DRV_VERSION);
66
67static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71static int debug = -1; /* defaults above */
72module_param(debug, int, 0);
73MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
275834d1 80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
5636f727
SH		 81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
82 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
275834d1
SH		 83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
84 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
85 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 86 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86f0cd50 87 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
baef58b1
SH		 88 { 0 }
89};
90MODULE_DEVICE_TABLE(pci, skge_id_table);
91
92static int skge_up(struct net_device *dev);
93static int skge_down(struct net_device *dev);
ee294dcd 94static void skge_phy_reset(struct skge_port *skge);
baef58b1 95static void skge_tx_clean(struct skge_port *skge);
2cd8e5d3
SH		 96static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 98static void genesis_get_stats(struct skge_port *skge, u64 *data);
99static void yukon_get_stats(struct skge_port *skge, u64 *data);
100static void yukon_init(struct skge_hw *hw, int port);
baef58b1 101static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 102static void genesis_link_up(struct skge_port *skge);
baef58b1 103
7e676d91 104/* Avoid conditionals by using array */
baef58b1
SH		 105static const int txqaddr[] = { Q_XA1, Q_XA2 };
106static const int rxqaddr[] = { Q_R1, Q_R2 };
107static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
108static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
109
baef58b1
SH		 110static int skge_get_regs_len(struct net_device *dev)
111{
c3f8be96 112 return 0x4000;
baef58b1
SH		 113}
114
115/*
c3f8be96
SH		 116 * Returns copy of whole control register region
117 * Note: skip RAM address register because accessing it will
118 * cause bus hangs!
baef58b1
SH		 119 */
120static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
121 void *p)
122{
123 const struct skge_port *skge = netdev_priv(dev);
baef58b1 124 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 125
126 regs->version = 1;
c3f8be96
SH		 127 memset(p, 0, regs->len);
128 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 129
c3f8be96
SH		 130 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
131 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 132}
133
8f3f8193 134/* Wake on Lan only supported on Yukon chips with rev 1 or above */
baef58b1
SH		 135static int wol_supported(const struct skge_hw *hw)
136{
137 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 138 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 139}
140
141static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
142{
143 struct skge_port *skge = netdev_priv(dev);
144
145 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
146 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
147}
148
149static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
150{
151 struct skge_port *skge = netdev_priv(dev);
152 struct skge_hw *hw = skge->hw;
153
95566065 154 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 155 return -EOPNOTSUPP;
156
157 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
158 return -EOPNOTSUPP;
159
160 skge->wol = wol->wolopts == WAKE_MAGIC;
161
162 if (skge->wol) {
163 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
164
165 skge_write16(hw, WOL_CTRL_STAT,
166 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
167 WOL_CTL_ENA_MAGIC_PKT_UNIT);
168 } else
169 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
170
171 return 0;
172}
173
8f3f8193
SH		 174/* Determine supported/advertised modes based on hardware.
175 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 176 */
177static u32 skge_supported_modes(const struct skge_hw *hw)
178{
179 u32 supported;
180
5e1705dd 181 if (hw->copper) {
31b619c5
SH		 182 supported = SUPPORTED_10baseT_Half
183 | SUPPORTED_10baseT_Full
184 | SUPPORTED_100baseT_Half
185 | SUPPORTED_100baseT_Full
186 | SUPPORTED_1000baseT_Half
187 | SUPPORTED_1000baseT_Full
188 | SUPPORTED_Autoneg| SUPPORTED_TP;
189
190 if (hw->chip_id == CHIP_ID_GENESIS)
191 supported &= ~(SUPPORTED_10baseT_Half
192 | SUPPORTED_10baseT_Full
193 | SUPPORTED_100baseT_Half
194 | SUPPORTED_100baseT_Full);
195
196 else if (hw->chip_id == CHIP_ID_YUKON)
197 supported &= ~SUPPORTED_1000baseT_Half;
198 } else
199 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
200 | SUPPORTED_Autoneg;
201
202 return supported;
203}
baef58b1
SH		 204
205static int skge_get_settings(struct net_device *dev,
206 struct ethtool_cmd *ecmd)
207{
208 struct skge_port *skge = netdev_priv(dev);
209 struct skge_hw *hw = skge->hw;
210
211 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 212 ecmd->supported = skge_supported_modes(hw);
baef58b1 213
5e1705dd 214 if (hw->copper) {
baef58b1
SH		 215 ecmd->port = PORT_TP;
216 ecmd->phy_address = hw->phy_addr;
31b619c5 217 } else
baef58b1 218 ecmd->port = PORT_FIBRE;
baef58b1
SH		 219
220 ecmd->advertising = skge->advertising;
221 ecmd->autoneg = skge->autoneg;
222 ecmd->speed = skge->speed;
223 ecmd->duplex = skge->duplex;
224 return 0;
225}
226
baef58b1
SH		 227static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
228{
229 struct skge_port *skge = netdev_priv(dev);
230 const struct skge_hw *hw = skge->hw;
31b619c5 231 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 232
233 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 234 ecmd->advertising = supported;
235 skge->duplex = -1;
236 skge->speed = -1;
baef58b1 237 } else {
31b619c5
SH		 238 u32 setting;
239
2c668514 240 switch (ecmd->speed) {
baef58b1 241 case SPEED_1000:
31b619c5
SH		 242 if (ecmd->duplex == DUPLEX_FULL)
243 setting = SUPPORTED_1000baseT_Full;
244 else if (ecmd->duplex == DUPLEX_HALF)
245 setting = SUPPORTED_1000baseT_Half;
246 else
247 return -EINVAL;
baef58b1
SH		 248 break;
249 case SPEED_100:
31b619c5
SH		 250 if (ecmd->duplex == DUPLEX_FULL)
251 setting = SUPPORTED_100baseT_Full;
252 else if (ecmd->duplex == DUPLEX_HALF)
253 setting = SUPPORTED_100baseT_Half;
254 else
255 return -EINVAL;
256 break;
257
baef58b1 258 case SPEED_10:
31b619c5
SH		 259 if (ecmd->duplex == DUPLEX_FULL)
260 setting = SUPPORTED_10baseT_Full;
261 else if (ecmd->duplex == DUPLEX_HALF)
262 setting = SUPPORTED_10baseT_Half;
263 else
baef58b1
SH		 264 return -EINVAL;
265 break;
266 default:
267 return -EINVAL;
268 }
31b619c5
SH		 269
270 if ((setting & supported) == 0)
271 return -EINVAL;
272
273 skge->speed = ecmd->speed;
274 skge->duplex = ecmd->duplex;
baef58b1
SH		 275 }
276
277 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 278 skge->advertising = ecmd->advertising;
279
ee294dcd
SH		 280 if (netif_running(dev))
281 skge_phy_reset(skge);
282
baef58b1
SH		 283 return (0);
284}
285
286static void skge_get_drvinfo(struct net_device *dev,
287 struct ethtool_drvinfo *info)
288{
289 struct skge_port *skge = netdev_priv(dev);
290
291 strcpy(info->driver, DRV_NAME);
292 strcpy(info->version, DRV_VERSION);
293 strcpy(info->fw_version, "N/A");
294 strcpy(info->bus_info, pci_name(skge->hw->pdev));
295}
296
297static const struct skge_stat {
298 char name[ETH_GSTRING_LEN];
299 u16 xmac_offset;
300 u16 gma_offset;
301} skge_stats[] = {
302 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
303 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
304
305 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
306 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
307 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
308 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
309 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
310 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
311 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
312 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
313
314 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
315 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
316 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
317 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
318 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
319 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
320
321 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
322 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
323 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
324 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
325 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
326};
327
328static int skge_get_stats_count(struct net_device *dev)
329{
330 return ARRAY_SIZE(skge_stats);
331}
332
333static void skge_get_ethtool_stats(struct net_device *dev,
334 struct ethtool_stats *stats, u64 *data)
335{
336 struct skge_port *skge = netdev_priv(dev);
337
338 if (skge->hw->chip_id == CHIP_ID_GENESIS)
339 genesis_get_stats(skge, data);
340 else
341 yukon_get_stats(skge, data);
342}
343
344/* Use hardware MIB variables for critical path statistics and
345 * transmit feedback not reported at interrupt.
346 * Other errors are accounted for in interrupt handler.
347 */
348static struct net_device_stats *skge_get_stats(struct net_device *dev)
349{
350 struct skge_port *skge = netdev_priv(dev);
351 u64 data[ARRAY_SIZE(skge_stats)];
352
353 if (skge->hw->chip_id == CHIP_ID_GENESIS)
354 genesis_get_stats(skge, data);
355 else
356 yukon_get_stats(skge, data);
357
358 skge->net_stats.tx_bytes = data[0];
359 skge->net_stats.rx_bytes = data[1];
360 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
361 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
4c180fc4 362 skge->net_stats.multicast = data[3] + data[5];
baef58b1
SH		 363 skge->net_stats.collisions = data[10];
364 skge->net_stats.tx_aborted_errors = data[12];
365
366 return &skge->net_stats;
367}
368
369static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
370{
371 int i;
372
95566065 373 switch (stringset) {
baef58b1
SH		 374 case ETH_SS_STATS:
375 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
376 memcpy(data + i * ETH_GSTRING_LEN,
377 skge_stats[i].name, ETH_GSTRING_LEN);
378 break;
379 }
380}
381
382static void skge_get_ring_param(struct net_device *dev,
383 struct ethtool_ringparam *p)
384{
385 struct skge_port *skge = netdev_priv(dev);
386
387 p->rx_max_pending = MAX_RX_RING_SIZE;
388 p->tx_max_pending = MAX_TX_RING_SIZE;
389 p->rx_mini_max_pending = 0;
390 p->rx_jumbo_max_pending = 0;
391
392 p->rx_pending = skge->rx_ring.count;
393 p->tx_pending = skge->tx_ring.count;
394 p->rx_mini_pending = 0;
395 p->rx_jumbo_pending = 0;
396}
397
398static int skge_set_ring_param(struct net_device *dev,
399 struct ethtool_ringparam *p)
400{
401 struct skge_port *skge = netdev_priv(dev);
3b8bb472 402 int err;
baef58b1
SH		 403
404 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
405 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
406 return -EINVAL;
407
408 skge->rx_ring.count = p->rx_pending;
409 skge->tx_ring.count = p->tx_pending;
410
411 if (netif_running(dev)) {
412 skge_down(dev);
3b8bb472
SH		 413 err = skge_up(dev);
414 if (err)
415 dev_close(dev);
baef58b1
SH		 416 }
417
418 return 0;
419}
420
421static u32 skge_get_msglevel(struct net_device *netdev)
422{
423 struct skge_port *skge = netdev_priv(netdev);
424 return skge->msg_enable;
425}
426
427static void skge_set_msglevel(struct net_device *netdev, u32 value)
428{
429 struct skge_port *skge = netdev_priv(netdev);
430 skge->msg_enable = value;
431}
432
433static int skge_nway_reset(struct net_device *dev)
434{
435 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 436
437 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
438 return -EINVAL;
439
ee294dcd 440 skge_phy_reset(skge);
baef58b1
SH		 441 return 0;
442}
443
444static int skge_set_sg(struct net_device *dev, u32 data)
445{
446 struct skge_port *skge = netdev_priv(dev);
447 struct skge_hw *hw = skge->hw;
448
449 if (hw->chip_id == CHIP_ID_GENESIS && data)
450 return -EOPNOTSUPP;
451 return ethtool_op_set_sg(dev, data);
452}
453
454static int skge_set_tx_csum(struct net_device *dev, u32 data)
455{
456 struct skge_port *skge = netdev_priv(dev);
457 struct skge_hw *hw = skge->hw;
458
459 if (hw->chip_id == CHIP_ID_GENESIS && data)
460 return -EOPNOTSUPP;
461
462 return ethtool_op_set_tx_csum(dev, data);
463}
464
465static u32 skge_get_rx_csum(struct net_device *dev)
466{
467 struct skge_port *skge = netdev_priv(dev);
468
469 return skge->rx_csum;
470}
471
472/* Only Yukon supports checksum offload. */
473static int skge_set_rx_csum(struct net_device *dev, u32 data)
474{
475 struct skge_port *skge = netdev_priv(dev);
476
477 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
478 return -EOPNOTSUPP;
479
480 skge->rx_csum = data;
481 return 0;
482}
483
baef58b1
SH		 484static void skge_get_pauseparam(struct net_device *dev,
485 struct ethtool_pauseparam *ecmd)
486{
487 struct skge_port *skge = netdev_priv(dev);
488
489 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
490 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
491 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
492 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
493
494 ecmd->autoneg = skge->autoneg;
495}
496
497static int skge_set_pauseparam(struct net_device *dev,
498 struct ethtool_pauseparam *ecmd)
499{
500 struct skge_port *skge = netdev_priv(dev);
501
502 skge->autoneg = ecmd->autoneg;
503 if (ecmd->rx_pause && ecmd->tx_pause)
504 skge->flow_control = FLOW_MODE_SYMMETRIC;
95566065 505 else if (ecmd->rx_pause && !ecmd->tx_pause)
baef58b1 506 skge->flow_control = FLOW_MODE_REM_SEND;
95566065 507 else if (!ecmd->rx_pause && ecmd->tx_pause)
baef58b1
SH		 508 skge->flow_control = FLOW_MODE_LOC_SEND;
509 else
510 skge->flow_control = FLOW_MODE_NONE;
511
e8df8554
SH		 512 if (netif_running(dev))
513 skge_phy_reset(skge);
baef58b1
SH		 514 return 0;
515}
516
517/* Chip internal frequency for clock calculations */
518static inline u32 hwkhz(const struct skge_hw *hw)
519{
520 if (hw->chip_id == CHIP_ID_GENESIS)
521 return 53215; /* or: 53.125 MHz */
baef58b1
SH		 522 else
523 return 78215; /* or: 78.125 MHz */
524}
525
8f3f8193 526/* Chip HZ to microseconds */
baef58b1
SH		 527static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
528{
529 return (ticks * 1000) / hwkhz(hw);
530}
531
8f3f8193 532/* Microseconds to chip HZ */
baef58b1
SH		 533static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
534{
535 return hwkhz(hw) * usec / 1000;
536}
537
538static int skge_get_coalesce(struct net_device *dev,
539 struct ethtool_coalesce *ecmd)
540{
541 struct skge_port *skge = netdev_priv(dev);
542 struct skge_hw *hw = skge->hw;
543 int port = skge->port;
544
545 ecmd->rx_coalesce_usecs = 0;
546 ecmd->tx_coalesce_usecs = 0;
547
548 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
549 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
550 u32 msk = skge_read32(hw, B2_IRQM_MSK);
551
552 if (msk & rxirqmask[port])
553 ecmd->rx_coalesce_usecs = delay;
554 if (msk & txirqmask[port])
555 ecmd->tx_coalesce_usecs = delay;
556 }
557
558 return 0;
559}
560
561/* Note: interrupt timer is per board, but can turn on/off per port */
562static int skge_set_coalesce(struct net_device *dev,
563 struct ethtool_coalesce *ecmd)
564{
565 struct skge_port *skge = netdev_priv(dev);
566 struct skge_hw *hw = skge->hw;
567 int port = skge->port;
568 u32 msk = skge_read32(hw, B2_IRQM_MSK);
569 u32 delay = 25;
570
571 if (ecmd->rx_coalesce_usecs == 0)
572 msk &= ~rxirqmask[port];
573 else if (ecmd->rx_coalesce_usecs < 25 ||
574 ecmd->rx_coalesce_usecs > 33333)
575 return -EINVAL;
576 else {
577 msk |= rxirqmask[port];
578 delay = ecmd->rx_coalesce_usecs;
579 }
580
581 if (ecmd->tx_coalesce_usecs == 0)
582 msk &= ~txirqmask[port];
583 else if (ecmd->tx_coalesce_usecs < 25 ||
584 ecmd->tx_coalesce_usecs > 33333)
585 return -EINVAL;
586 else {
587 msk |= txirqmask[port];
588 delay = min(delay, ecmd->rx_coalesce_usecs);
589 }
590
591 skge_write32(hw, B2_IRQM_MSK, msk);
592 if (msk == 0)
593 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
594 else {
595 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
596 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
597 }
598 return 0;
599}
600
6abebb53
SH		 601enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
602static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 603{
6abebb53
SH		 604 struct skge_hw *hw = skge->hw;
605 int port = skge->port;
606
607 spin_lock_bh(&hw->phy_lock);
baef58b1 608 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 609 switch (mode) {
610 case LED_MODE_OFF:
611 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
612 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
613 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
614 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
615 break;
baef58b1 616
6abebb53
SH		 617 case LED_MODE_ON:
618 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
619 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 620
6abebb53
SH		 621 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
622 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 623
6abebb53 624 break;
baef58b1 625
6abebb53
SH		 626 case LED_MODE_TST:
627 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
628 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
629 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 630
6abebb53
SH		 631 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
632 break;
633 }
baef58b1 634 } else {
6abebb53
SH		 635 switch (mode) {
636 case LED_MODE_OFF:
637 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
638 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
639 PHY_M_LED_MO_DUP(MO_LED_OFF) |
640 PHY_M_LED_MO_10(MO_LED_OFF) |
641 PHY_M_LED_MO_100(MO_LED_OFF) |
642 PHY_M_LED_MO_1000(MO_LED_OFF) |
643 PHY_M_LED_MO_RX(MO_LED_OFF));
644 break;
645 case LED_MODE_ON:
646 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
647 PHY_M_LED_PULS_DUR(PULS_170MS) |
648 PHY_M_LED_BLINK_RT(BLINK_84MS) |
649 PHY_M_LEDC_TX_CTRL |
650 PHY_M_LEDC_DP_CTRL);
46a60f2d 651
6abebb53
SH		 652 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
653 PHY_M_LED_MO_RX(MO_LED_OFF) |
654 (skge->speed == SPEED_100 ?
655 PHY_M_LED_MO_100(MO_LED_ON) : 0));
656 break;
657 case LED_MODE_TST:
658 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
659 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
660 PHY_M_LED_MO_DUP(MO_LED_ON) |
661 PHY_M_LED_MO_10(MO_LED_ON) |
662 PHY_M_LED_MO_100(MO_LED_ON) |
663 PHY_M_LED_MO_1000(MO_LED_ON) |
664 PHY_M_LED_MO_RX(MO_LED_ON));
665 }
baef58b1 666 }
4ff6ac05 667 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 668}
669
670/* blink LED's for finding board */
671static int skge_phys_id(struct net_device *dev, u32 data)
672{
673 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 674 unsigned long ms;
675 enum led_mode mode = LED_MODE_TST;
baef58b1 676
95566065 677 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 678 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
679 else
680 ms = data * 1000;
baef58b1 681
6abebb53
SH		 682 while (ms > 0) {
683 skge_led(skge, mode);
684 mode ^= LED_MODE_TST;
baef58b1 685
6abebb53
SH		 686 if (msleep_interruptible(BLINK_MS))
687 break;
688 ms -= BLINK_MS;
689 }
baef58b1 690
6abebb53
SH		 691 /* back to regular LED state */
692 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 693
694 return 0;
695}
696
697static struct ethtool_ops skge_ethtool_ops = {
698 .get_settings = skge_get_settings,
699 .set_settings = skge_set_settings,
700 .get_drvinfo = skge_get_drvinfo,
701 .get_regs_len = skge_get_regs_len,
702 .get_regs = skge_get_regs,
703 .get_wol = skge_get_wol,
704 .set_wol = skge_set_wol,
705 .get_msglevel = skge_get_msglevel,
706 .set_msglevel = skge_set_msglevel,
707 .nway_reset = skge_nway_reset,
708 .get_link = ethtool_op_get_link,
709 .get_ringparam = skge_get_ring_param,
710 .set_ringparam = skge_set_ring_param,
711 .get_pauseparam = skge_get_pauseparam,
712 .set_pauseparam = skge_set_pauseparam,
713 .get_coalesce = skge_get_coalesce,
714 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 715 .get_sg = ethtool_op_get_sg,
716 .set_sg = skge_set_sg,
717 .get_tx_csum = ethtool_op_get_tx_csum,
718 .set_tx_csum = skge_set_tx_csum,
719 .get_rx_csum = skge_get_rx_csum,
720 .set_rx_csum = skge_set_rx_csum,
721 .get_strings = skge_get_strings,
722 .phys_id = skge_phys_id,
723 .get_stats_count = skge_get_stats_count,
724 .get_ethtool_stats = skge_get_ethtool_stats,
56230d53 725 .get_perm_addr = ethtool_op_get_perm_addr,
baef58b1
SH		 726};
727
728/*
729 * Allocate ring elements and chain them together
730 * One-to-one association of board descriptors with ring elements
731 */
c3da1447 732static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 733{
734 struct skge_tx_desc *d;
735 struct skge_element *e;
736 int i;
737
ff7907ae 738 ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);
baef58b1
SH		 739 if (!ring->start)
740 return -ENOMEM;
741
742 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
743 e->desc = d;
744 if (i == ring->count - 1) {
745 e->next = ring->start;
746 d->next_offset = base;
747 } else {
748 e->next = e + 1;
749 d->next_offset = base + (i+1) * sizeof(*d);
750 }
751 }
752 ring->to_use = ring->to_clean = ring->start;
753
754 return 0;
755}
756
19a33d4e
SH		 757/* Allocate and setup a new buffer for receiving */
758static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
759 struct sk_buff *skb, unsigned int bufsize)
760{
761 struct skge_rx_desc *rd = e->desc;
762 u64 map;
baef58b1
SH		 763
764 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
765 PCI_DMA_FROMDEVICE);
766
767 rd->dma_lo = map;
768 rd->dma_hi = map >> 32;
769 e->skb = skb;
770 rd->csum1_start = ETH_HLEN;
771 rd->csum2_start = ETH_HLEN;
772 rd->csum1 = 0;
773 rd->csum2 = 0;
774
775 wmb();
776
777 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
778 pci_unmap_addr_set(e, mapaddr, map);
779 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 780}
781
19a33d4e
SH		 782/* Resume receiving using existing skb,
783 * Note: DMA address is not changed by chip.
784 * MTU not changed while receiver active.
785 */
5a011447 786static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 787{
788 struct skge_rx_desc *rd = e->desc;
789
790 rd->csum2 = 0;
791 rd->csum2_start = ETH_HLEN;
792
793 wmb();
794
795 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
796}
797
798
799/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 800static void skge_rx_clean(struct skge_port *skge)
801{
802 struct skge_hw *hw = skge->hw;
803 struct skge_ring *ring = &skge->rx_ring;
804 struct skge_element *e;
805
19a33d4e
SH		 806 e = ring->start;
807 do {
baef58b1
SH		 808 struct skge_rx_desc *rd = e->desc;
809 rd->control = 0;
19a33d4e
SH		 810 if (e->skb) {
811 pci_unmap_single(hw->pdev,
812 pci_unmap_addr(e, mapaddr),
813 pci_unmap_len(e, maplen),
814 PCI_DMA_FROMDEVICE);
815 dev_kfree_skb(e->skb);
816 e->skb = NULL;
817 }
818 } while ((e = e->next) != ring->start);
baef58b1
SH		 819}
820
19a33d4e 821
baef58b1 822/* Allocate buffers for receive ring
19a33d4e 823 * For receive: to_clean is next received frame.
baef58b1
SH		 824 */
825static int skge_rx_fill(struct skge_port *skge)
826{
827 struct skge_ring *ring = &skge->rx_ring;
828 struct skge_element *e;
baef58b1 829
19a33d4e
SH		 830 e = ring->start;
831 do {
383181ac 832 struct sk_buff *skb;
baef58b1 833
b5d56ddc 834 skb = alloc_skb(skge->rx_buf_size + NET_IP_ALIGN, GFP_KERNEL);
19a33d4e
SH		 835 if (!skb)
836 return -ENOMEM;
837
383181ac
SH		 838 skb_reserve(skb, NET_IP_ALIGN);
839 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
19a33d4e 840 } while ( (e = e->next) != ring->start);
baef58b1 841
19a33d4e
SH		 842 ring->to_clean = ring->start;
843 return 0;
baef58b1
SH		 844}
845
846static void skge_link_up(struct skge_port *skge)
847{
46a60f2d 848 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 849 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
850
baef58b1 851 netif_carrier_on(skge->netdev);
29b4e886 852 netif_wake_queue(skge->netdev);
baef58b1
SH		 853
854 if (netif_msg_link(skge))
855 printk(KERN_INFO PFX
856 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
857 skge->netdev->name, skge->speed,
858 skge->duplex == DUPLEX_FULL ? "full" : "half",
859 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
860 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
861 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
862 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
863 "unknown");
864}
865
866static void skge_link_down(struct skge_port *skge)
867{
54cfb5aa 868 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 869 netif_carrier_off(skge->netdev);
870 netif_stop_queue(skge->netdev);
871
872 if (netif_msg_link(skge))
873 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
874}
875
2cd8e5d3 876static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 877{
878 int i;
baef58b1 879
6b0c1480 880 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 881 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 882
89bf5f23 883 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 884 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 885 goto ready;
0781191c 886 udelay(1);
baef58b1
SH		 887 }
888
2cd8e5d3 889 return -ETIMEDOUT;
89bf5f23 890 ready:
2cd8e5d3 891 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 892
2cd8e5d3
SH		 893 return 0;
894}
895
896static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
897{
898 u16 v = 0;
899 if (__xm_phy_read(hw, port, reg, &v))
900 printk(KERN_WARNING PFX "%s: phy read timed out\n",
901 hw->dev[port]->name);
baef58b1
SH		 902 return v;
903}
904
2cd8e5d3 905static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 906{
907 int i;
908
6b0c1480 909 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 910 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 911 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 912 goto ready;
89bf5f23 913 udelay(1);
baef58b1 914 }
2cd8e5d3 915 return -EIO;
baef58b1
SH		 916
917 ready:
6b0c1480 918 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 919 for (i = 0; i < PHY_RETRIES; i++) {
920 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
921 return 0;
922 udelay(1);
923 }
924 return -ETIMEDOUT;
baef58b1
SH		 925}
926
927static void genesis_init(struct skge_hw *hw)
928{
929 /* set blink source counter */
930 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
931 skge_write8(hw, B2_BSC_CTRL, BSC_START);
932
933 /* configure mac arbiter */
934 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
935
936 /* configure mac arbiter timeout values */
937 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
938 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
939 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
940 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
941
942 skge_write8(hw, B3_MA_RCINI_RX1, 0);
943 skge_write8(hw, B3_MA_RCINI_RX2, 0);
944 skge_write8(hw, B3_MA_RCINI_TX1, 0);
945 skge_write8(hw, B3_MA_RCINI_TX2, 0);
946
947 /* configure packet arbiter timeout */
948 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
949 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
950 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
951 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
952 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
953}
954
955static void genesis_reset(struct skge_hw *hw, int port)
956{
45bada65 957 const u8 zero[8] = { 0 };
baef58b1 958
46a60f2d
SH		 959 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
960
baef58b1 961 /* reset the statistics module */
6b0c1480
SH		 962 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
963 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
964 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
965 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
966 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 967
89bf5f23
SH		 968 /* disable Broadcom PHY IRQ */
969 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 970
45bada65 971 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 972}
973
974
45bada65
SH		 975/* Convert mode to MII values */
976static const u16 phy_pause_map[] = {
977 [FLOW_MODE_NONE] = 0,
978 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
979 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
980 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
981};
982
983
984/* Check status of Broadcom phy link */
985static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 986{
45bada65
SH		 987 struct net_device *dev = hw->dev[port];
988 struct skge_port *skge = netdev_priv(dev);
989 u16 status;
990
991 /* read twice because of latch */
992 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
993 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
994
45bada65
SH		 995 if ((status & PHY_ST_LSYNC) == 0) {
996 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
997 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
998 xm_write16(hw, port, XM_MMU_CMD, cmd);
999 /* dummy read to ensure writing */
1000 (void) xm_read16(hw, port, XM_MMU_CMD);
1001
1002 if (netif_carrier_ok(dev))
1003 skge_link_down(skge);
1004 } else {
1005 if (skge->autoneg == AUTONEG_ENABLE &&
1006 (status & PHY_ST_AN_OVER)) {
1007 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1008 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1009
1010 if (lpa & PHY_B_AN_RF) {
1011 printk(KERN_NOTICE PFX "%s: remote fault\n",
1012 dev->name);
1013 return;
1014 }
1015
1016 /* Check Duplex mismatch */
2c668514 1017 switch (aux & PHY_B_AS_AN_RES_MSK) {
45bada65
SH		 1018 case PHY_B_RES_1000FD:
1019 skge->duplex = DUPLEX_FULL;
1020 break;
1021 case PHY_B_RES_1000HD:
1022 skge->duplex = DUPLEX_HALF;
1023 break;
1024 default:
1025 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1026 dev->name);
1027 return;
1028 }
1029
1030
1031 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1032 switch (aux & PHY_B_AS_PAUSE_MSK) {
1033 case PHY_B_AS_PAUSE_MSK:
1034 skge->flow_control = FLOW_MODE_SYMMETRIC;
1035 break;
1036 case PHY_B_AS_PRR:
1037 skge->flow_control = FLOW_MODE_REM_SEND;
1038 break;
1039 case PHY_B_AS_PRT:
1040 skge->flow_control = FLOW_MODE_LOC_SEND;
1041 break;
1042 default:
1043 skge->flow_control = FLOW_MODE_NONE;
1044 }
1045
1046 skge->speed = SPEED_1000;
1047 }
1048
1049 if (!netif_carrier_ok(dev))
1050 genesis_link_up(skge);
1051 }
1052}
1053
1054/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1055 * Phy on for 100 or 10Mbit operation
1056 */
1057static void bcom_phy_init(struct skge_port *skge, int jumbo)
1058{
1059 struct skge_hw *hw = skge->hw;
1060 int port = skge->port;
baef58b1 1061 int i;
45bada65 1062 u16 id1, r, ext, ctl;
baef58b1
SH		 1063
1064 /* magic workaround patterns for Broadcom */
1065 static const struct {
1066 u16 reg;
1067 u16 val;
1068 } A1hack[] = {
1069 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1070 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1071 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1072 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1073 }, C0hack[] = {
1074 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1075 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1076 };
1077
45bada65
SH		 1078 /* read Id from external PHY (all have the same address) */
1079 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1080
1081 /* Optimize MDIO transfer by suppressing preamble. */
1082 r = xm_read16(hw, port, XM_MMU_CMD);
1083 r |= XM_MMU_NO_PRE;
1084 xm_write16(hw, port, XM_MMU_CMD,r);
1085
2c668514 1086 switch (id1) {
45bada65
SH		 1087 case PHY_BCOM_ID1_C0:
1088 /*
1089 * Workaround BCOM Errata for the C0 type.
1090 * Write magic patterns to reserved registers.
1091 */
1092 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1093 xm_phy_write(hw, port,
1094 C0hack[i].reg, C0hack[i].val);
1095
1096 break;
1097 case PHY_BCOM_ID1_A1:
1098 /*
1099 * Workaround BCOM Errata for the A1 type.
1100 * Write magic patterns to reserved registers.
1101 */
1102 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1103 xm_phy_write(hw, port,
1104 A1hack[i].reg, A1hack[i].val);
1105 break;
1106 }
1107
1108 /*
1109 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1110 * Disable Power Management after reset.
1111 */
1112 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1113 r |= PHY_B_AC_DIS_PM;
1114 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1115
1116 /* Dummy read */
1117 xm_read16(hw, port, XM_ISRC);
1118
1119 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1120 ctl = PHY_CT_SP1000; /* always 1000mbit */
1121
1122 if (skge->autoneg == AUTONEG_ENABLE) {
1123 /*
1124 * Workaround BCOM Errata #1 for the C5 type.
1125 * 1000Base-T Link Acquisition Failure in Slave Mode
1126 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1127 */
1128 u16 adv = PHY_B_1000C_RD;
1129 if (skge->advertising & ADVERTISED_1000baseT_Half)
1130 adv |= PHY_B_1000C_AHD;
1131 if (skge->advertising & ADVERTISED_1000baseT_Full)
1132 adv |= PHY_B_1000C_AFD;
1133 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1134
1135 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1136 } else {
1137 if (skge->duplex == DUPLEX_FULL)
1138 ctl |= PHY_CT_DUP_MD;
1139 /* Force to slave */
1140 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1141 }
1142
1143 /* Set autonegotiation pause parameters */
1144 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1145 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1146
1147 /* Handle Jumbo frames */
1148 if (jumbo) {
1149 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1150 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1151
1152 ext |= PHY_B_PEC_HIGH_LA;
1153
1154 }
1155
1156 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1157 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1158
8f3f8193 1159 /* Use link status change interrupt */
45bada65
SH		 1160 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1161
1162 bcom_check_link(hw, port);
1163}
1164
1165static void genesis_mac_init(struct skge_hw *hw, int port)
1166{
1167 struct net_device *dev = hw->dev[port];
1168 struct skge_port *skge = netdev_priv(dev);
1169 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1170 int i;
1171 u32 r;
1172 const u8 zero[6] = { 0 };
1173
0781191c
SH		 1174 for (i = 0; i < 10; i++) {
1175 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1176 MFF_SET_MAC_RST);
1177 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1178 goto reset_ok;
1179 udelay(1);
1180 }
baef58b1 1181
0781191c
SH		 1182 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1183
1184 reset_ok:
baef58b1 1185 /* Unreset the XMAC. */
6b0c1480 1186 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1187
1188 /*
1189 * Perform additional initialization for external PHYs,
1190 * namely for the 1000baseTX cards that use the XMAC's
1191 * GMII mode.
1192 */
45bada65 1193 /* Take external Phy out of reset */
89bf5f23
SH		 1194 r = skge_read32(hw, B2_GP_IO);
1195 if (port == 0)
1196 r |= GP_DIR_0|GP_IO_0;
1197 else
1198 r |= GP_DIR_2|GP_IO_2;
1199
1200 skge_write32(hw, B2_GP_IO, r);
0781191c 1201
89bf5f23 1202
8f3f8193 1203 /* Enable GMII interface */
89bf5f23
SH		 1204 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1205
45bada65 1206 bcom_phy_init(skge, jumbo);
89bf5f23 1207
45bada65
SH		 1208 /* Set Station Address */
1209 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1210
45bada65
SH		 1211 /* We don't use match addresses so clear */
1212 for (i = 1; i < 16; i++)
1213 xm_outaddr(hw, port, XM_EXM(i), zero);
1214
0781191c
SH		 1215 /* Clear MIB counters */
1216 xm_write16(hw, port, XM_STAT_CMD,
1217 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1218 /* Clear two times according to Errata #3 */
1219 xm_write16(hw, port, XM_STAT_CMD,
1220 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1221
45bada65
SH		 1222 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1223 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1224
1225 /* We don't need the FCS appended to the packet. */
1226 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1227 if (jumbo)
1228 r |= XM_RX_BIG_PK_OK;
89bf5f23 1229
45bada65 1230 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1231 /*
45bada65
SH		 1232 * If in manual half duplex mode the other side might be in
1233 * full duplex mode, so ignore if a carrier extension is not seen
1234 * on frames received
89bf5f23 1235 */
45bada65 1236 r |= XM_RX_DIS_CEXT;
baef58b1 1237 }
45bada65 1238 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1239
baef58b1
SH		 1240
1241 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1242 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1243
1244 /*
1245 * Bump up the transmit threshold. This helps hold off transmit
1246 * underruns when we're blasting traffic from both ports at once.
1247 */
1248 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1249
1250 /*
1251 * Enable the reception of all error frames. This is is
1252 * a necessary evil due to the design of the XMAC. The
1253 * XMAC's receive FIFO is only 8K in size, however jumbo
1254 * frames can be up to 9000 bytes in length. When bad
1255 * frame filtering is enabled, the XMAC's RX FIFO operates
1256 * in 'store and forward' mode. For this to work, the
1257 * entire frame has to fit into the FIFO, but that means
1258 * that jumbo frames larger than 8192 bytes will be
1259 * truncated. Disabling all bad frame filtering causes
1260 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1261 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1262 * RX FIFO as soon as the FIFO threshold is reached.
1263 */
45bada65 1264 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1265
baef58b1
SH		 1266
1267 /*
45bada65
SH		 1268 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1269 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1270 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1271 */
45bada65
SH		 1272 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1273
1274 /*
1275 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1276 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1277 * and 'Octets Tx OK Hi Cnt Ov'.
1278 */
1279 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1280
1281 /* Configure MAC arbiter */
1282 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1283
1284 /* configure timeout values */
1285 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1286 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1287 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1288 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1289
1290 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1291 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1292 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1293 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1294
1295 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1296 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1297 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1298 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1299
1300 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1301 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1302 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1303 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1304
45bada65 1305 if (jumbo) {
baef58b1 1306 /* Enable frame flushing if jumbo frames used */
6b0c1480 1307 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1308 } else {
1309 /* enable timeout timers if normal frames */
1310 skge_write16(hw, B3_PA_CTRL,
45bada65 1311 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1312 }
baef58b1
SH		 1313}
1314
1315static void genesis_stop(struct skge_port *skge)
1316{
1317 struct skge_hw *hw = skge->hw;
1318 int port = skge->port;
89bf5f23 1319 u32 reg;
baef58b1 1320
46a60f2d
SH		 1321 genesis_reset(hw, port);
1322
baef58b1
SH		 1323 /* Clear Tx packet arbiter timeout IRQ */
1324 skge_write16(hw, B3_PA_CTRL,
1325 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1326
1327 /*
8f3f8193 1328 * If the transfer sticks at the MAC the STOP command will not
baef58b1
SH		 1329 * terminate if we don't flush the XMAC's transmit FIFO !
1330 */
6b0c1480
SH		 1331 xm_write32(hw, port, XM_MODE,
1332 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1333
1334
1335 /* Reset the MAC */
6b0c1480 1336 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1337
1338 /* For external PHYs there must be special handling */
89bf5f23
SH		 1339 reg = skge_read32(hw, B2_GP_IO);
1340 if (port == 0) {
1341 reg |= GP_DIR_0;
1342 reg &= ~GP_IO_0;
1343 } else {
1344 reg |= GP_DIR_2;
1345 reg &= ~GP_IO_2;
baef58b1 1346 }
89bf5f23
SH		 1347 skge_write32(hw, B2_GP_IO, reg);
1348 skge_read32(hw, B2_GP_IO);
baef58b1 1349
6b0c1480
SH		 1350 xm_write16(hw, port, XM_MMU_CMD,
1351 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1352 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1353
6b0c1480 1354 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1355}
1356
1357
1358static void genesis_get_stats(struct skge_port *skge, u64 *data)
1359{
1360 struct skge_hw *hw = skge->hw;
1361 int port = skge->port;
1362 int i;
1363 unsigned long timeout = jiffies + HZ;
1364
6b0c1480 1365 xm_write16(hw, port,
baef58b1
SH		 1366 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1367
1368 /* wait for update to complete */
6b0c1480 1369 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1370 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1371 if (time_after(jiffies, timeout))
1372 break;
1373 udelay(10);
1374 }
1375
1376 /* special case for 64 bit octet counter */
6b0c1480
SH		 1377 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1378 | xm_read32(hw, port, XM_TXO_OK_LO);
1379 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1380 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1381
1382 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1383 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1384}
1385
1386static void genesis_mac_intr(struct skge_hw *hw, int port)
1387{
1388 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1389 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1390
7e676d91
SH		 1391 if (netif_msg_intr(skge))
1392 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1393 skge->netdev->name, status);
baef58b1
SH		 1394
1395 if (status & XM_IS_TXF_UR) {
6b0c1480 1396 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1397 ++skge->net_stats.tx_fifo_errors;
1398 }
1399 if (status & XM_IS_RXF_OV) {
6b0c1480 1400 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1401 ++skge->net_stats.rx_fifo_errors;
1402 }
1403}
1404
baef58b1
SH		 1405static void genesis_link_up(struct skge_port *skge)
1406{
1407 struct skge_hw *hw = skge->hw;
1408 int port = skge->port;
1409 u16 cmd;
1410 u32 mode, msk;
1411
6b0c1480 1412 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1413
1414 /*
1415 * enabling pause frame reception is required for 1000BT
1416 * because the XMAC is not reset if the link is going down
1417 */
1418 if (skge->flow_control == FLOW_MODE_NONE ||
1419 skge->flow_control == FLOW_MODE_LOC_SEND)
7e676d91 1420 /* Disable Pause Frame Reception */
baef58b1
SH		 1421 cmd |= XM_MMU_IGN_PF;
1422 else
1423 /* Enable Pause Frame Reception */
1424 cmd &= ~XM_MMU_IGN_PF;
1425
6b0c1480 1426 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1427
6b0c1480 1428 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 1429 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1430 skge->flow_control == FLOW_MODE_LOC_SEND) {
1431 /*
1432 * Configure Pause Frame Generation
1433 * Use internal and external Pause Frame Generation.
1434 * Sending pause frames is edge triggered.
1435 * Send a Pause frame with the maximum pause time if
1436 * internal oder external FIFO full condition occurs.
1437 * Send a zero pause time frame to re-start transmission.
1438 */
1439 /* XM_PAUSE_DA = '010000C28001' (default) */
1440 /* XM_MAC_PTIME = 0xffff (maximum) */
1441 /* remember this value is defined in big endian (!) */
6b0c1480 1442 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1443
1444 mode |= XM_PAUSE_MODE;
6b0c1480 1445 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1446 } else {
1447 /*
1448 * disable pause frame generation is required for 1000BT
1449 * because the XMAC is not reset if the link is going down
1450 */
1451 /* Disable Pause Mode in Mode Register */
1452 mode &= ~XM_PAUSE_MODE;
1453
6b0c1480 1454 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1455 }
1456
6b0c1480 1457 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 1458
1459 msk = XM_DEF_MSK;
89bf5f23
SH		 1460 /* disable GP0 interrupt bit for external Phy */
1461 msk |= XM_IS_INP_ASS;
baef58b1 1462
6b0c1480
SH		 1463 xm_write16(hw, port, XM_IMSK, msk);
1464 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1465
1466 /* get MMU Command Reg. */
6b0c1480 1467 cmd = xm_read16(hw, port, XM_MMU_CMD);
89bf5f23 1468 if (skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1469 cmd |= XM_MMU_GMII_FD;
1470
89bf5f23
SH		 1471 /*
1472 * Workaround BCOM Errata (#10523) for all BCom Phys
1473 * Enable Power Management after link up
1474 */
1475 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1476 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1477 & ~PHY_B_AC_DIS_PM);
1478 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
baef58b1
SH		 1479
1480 /* enable Rx/Tx */
6b0c1480 1481 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1482 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1483 skge_link_up(skge);
1484}
1485
1486
45bada65 1487static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1488{
1489 struct skge_hw *hw = skge->hw;
1490 int port = skge->port;
45bada65
SH		 1491 u16 isrc;
1492
1493 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1494 if (netif_msg_intr(skge))
1495 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1496 skge->netdev->name, isrc);
baef58b1 1497
45bada65
SH		 1498 if (isrc & PHY_B_IS_PSE)
1499 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1500 hw->dev[port]->name);
baef58b1
SH		 1501
1502 /* Workaround BCom Errata:
1503 * enable and disable loopback mode if "NO HCD" occurs.
1504 */
45bada65 1505 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1506 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1507 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1508 ctrl | PHY_CT_LOOP);
6b0c1480 1509 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1510 ctrl & ~PHY_CT_LOOP);
1511 }
1512
45bada65
SH		 1513 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1514 bcom_check_link(hw, port);
baef58b1 1515
baef58b1
SH		 1516}
1517
2cd8e5d3
SH		 1518static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1519{
1520 int i;
1521
1522 gma_write16(hw, port, GM_SMI_DATA, val);
1523 gma_write16(hw, port, GM_SMI_CTRL,
1524 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1525 for (i = 0; i < PHY_RETRIES; i++) {
1526 udelay(1);
1527
1528 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1529 return 0;
1530 }
1531
1532 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1533 hw->dev[port]->name);
1534 return -EIO;
1535}
1536
1537static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1538{
1539 int i;
1540
1541 gma_write16(hw, port, GM_SMI_CTRL,
1542 GM_SMI_CT_PHY_AD(hw->phy_addr)
1543 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1544
1545 for (i = 0; i < PHY_RETRIES; i++) {
1546 udelay(1);
1547 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1548 goto ready;
1549 }
1550
1551 return -ETIMEDOUT;
1552 ready:
1553 *val = gma_read16(hw, port, GM_SMI_DATA);
1554 return 0;
1555}
1556
1557static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1558{
1559 u16 v = 0;
1560 if (__gm_phy_read(hw, port, reg, &v))
1561 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1562 hw->dev[port]->name);
1563 return v;
1564}
1565
8f3f8193 1566/* Marvell Phy Initialization */
baef58b1
SH		 1567static void yukon_init(struct skge_hw *hw, int port)
1568{
1569 struct skge_port *skge = netdev_priv(hw->dev[port]);
1570 u16 ctrl, ct1000, adv;
baef58b1 1571
baef58b1 1572 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1573 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1574
1575 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1576 PHY_M_EC_MAC_S_MSK);
1577 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1578
c506a509 1579 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1580
6b0c1480 1581 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1582 }
1583
6b0c1480 1584 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1585 if (skge->autoneg == AUTONEG_DISABLE)
1586 ctrl &= ~PHY_CT_ANE;
1587
1588 ctrl |= PHY_CT_RESET;
6b0c1480 1589 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1590
1591 ctrl = 0;
1592 ct1000 = 0;
b18f2091 1593 adv = PHY_AN_CSMA;
baef58b1
SH		 1594
1595 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1596 if (hw->copper) {
baef58b1
SH		 1597 if (skge->advertising & ADVERTISED_1000baseT_Full)
1598 ct1000 |= PHY_M_1000C_AFD;
1599 if (skge->advertising & ADVERTISED_1000baseT_Half)
1600 ct1000 |= PHY_M_1000C_AHD;
1601 if (skge->advertising & ADVERTISED_100baseT_Full)
1602 adv |= PHY_M_AN_100_FD;
1603 if (skge->advertising & ADVERTISED_100baseT_Half)
1604 adv |= PHY_M_AN_100_HD;
1605 if (skge->advertising & ADVERTISED_10baseT_Full)
1606 adv |= PHY_M_AN_10_FD;
1607 if (skge->advertising & ADVERTISED_10baseT_Half)
1608 adv |= PHY_M_AN_10_HD;
45bada65 1609 } else /* special defines for FIBER (88E1011S only) */
baef58b1
SH		 1610 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1611
45bada65
SH		 1612 /* Set Flow-control capabilities */
1613 adv |= phy_pause_map[skge->flow_control];
1614
baef58b1
SH		 1615 /* Restart Auto-negotiation */
1616 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1617 } else {
1618 /* forced speed/duplex settings */
1619 ct1000 = PHY_M_1000C_MSE;
1620
1621 if (skge->duplex == DUPLEX_FULL)
1622 ctrl |= PHY_CT_DUP_MD;
1623
1624 switch (skge->speed) {
1625 case SPEED_1000:
1626 ctrl |= PHY_CT_SP1000;
1627 break;
1628 case SPEED_100:
1629 ctrl |= PHY_CT_SP100;
1630 break;
1631 }
1632
1633 ctrl |= PHY_CT_RESET;
1634 }
1635
c506a509 1636 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1637
6b0c1480
SH		 1638 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1639 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 1640
baef58b1
SH		 1641 /* Enable phy interrupt on autonegotiation complete (or link up) */
1642 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 1643 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 1644 else
4cde06ed 1645 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1646}
1647
1648static void yukon_reset(struct skge_hw *hw, int port)
1649{
6b0c1480
SH		 1650 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1651 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1652 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1653 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1654 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1655
6b0c1480
SH		 1656 gma_write16(hw, port, GM_RX_CTRL,
1657 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1658 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1659}
1660
c8868611
SH		 1661/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1662static int is_yukon_lite_a0(struct skge_hw *hw)
1663{
1664 u32 reg;
1665 int ret;
1666
1667 if (hw->chip_id != CHIP_ID_YUKON)
1668 return 0;
1669
1670 reg = skge_read32(hw, B2_FAR);
1671 skge_write8(hw, B2_FAR + 3, 0xff);
1672 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1673 skge_write32(hw, B2_FAR, reg);
1674 return ret;
1675}
1676
baef58b1
SH		 1677static void yukon_mac_init(struct skge_hw *hw, int port)
1678{
1679 struct skge_port *skge = netdev_priv(hw->dev[port]);
1680 int i;
1681 u32 reg;
1682 const u8 *addr = hw->dev[port]->dev_addr;
1683
1684 /* WA code for COMA mode -- set PHY reset */
1685 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1686 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1687 reg = skge_read32(hw, B2_GP_IO);
1688 reg |= GP_DIR_9 | GP_IO_9;
1689 skge_write32(hw, B2_GP_IO, reg);
1690 }
baef58b1
SH		 1691
1692 /* hard reset */
6b0c1480
SH		 1693 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1694 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1695
1696 /* WA code for COMA mode -- clear PHY reset */
1697 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1698 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1699 reg = skge_read32(hw, B2_GP_IO);
1700 reg |= GP_DIR_9;
1701 reg &= ~GP_IO_9;
1702 skge_write32(hw, B2_GP_IO, reg);
1703 }
baef58b1
SH		 1704
1705 /* Set hardware config mode */
1706 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1707 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 1708 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 1709
1710 /* Clear GMC reset */
6b0c1480
SH		 1711 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1712 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1713 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 1714
baef58b1
SH		 1715 if (skge->autoneg == AUTONEG_DISABLE) {
1716 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1717 gma_write16(hw, port, GM_GP_CTRL,
1718 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1719
1720 switch (skge->speed) {
1721 case SPEED_1000:
564f9abb 1722 reg &= ~GM_GPCR_SPEED_100;
baef58b1 1723 reg |= GM_GPCR_SPEED_1000;
564f9abb 1724 break;
baef58b1 1725 case SPEED_100:
564f9abb 1726 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 1727 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 1728 break;
1729 case SPEED_10:
1730 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1731 break;
baef58b1
SH		 1732 }
1733
1734 if (skge->duplex == DUPLEX_FULL)
1735 reg |= GM_GPCR_DUP_FULL;
1736 } else
1737 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 1738
baef58b1
SH		 1739 switch (skge->flow_control) {
1740 case FLOW_MODE_NONE:
6b0c1480 1741 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1742 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1743 break;
1744 case FLOW_MODE_LOC_SEND:
1745 /* disable Rx flow-control */
1746 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1747 }
1748
6b0c1480 1749 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 1750 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1751
baef58b1 1752 yukon_init(hw, port);
baef58b1
SH		 1753
1754 /* MIB clear */
6b0c1480
SH		 1755 reg = gma_read16(hw, port, GM_PHY_ADDR);
1756 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1757
1758 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1759 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1760 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1761
1762 /* transmit control */
6b0c1480 1763 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1764
1765 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1766 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1767 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1768
1769 /* transmit flow control */
6b0c1480 1770 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1771
1772 /* transmit parameter */
6b0c1480 1773 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1774 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1775 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1776 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1777
1778 /* serial mode register */
1779 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1780 if (hw->dev[port]->mtu > 1500)
1781 reg |= GM_SMOD_JUMBO_ENA;
1782
6b0c1480 1783 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 1784
1785 /* physical address: used for pause frames */
6b0c1480 1786 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 1787 /* virtual address for data */
6b0c1480 1788 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 1789
1790 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 1791 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1792 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1793 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 1794
1795 /* Initialize Mac Fifo */
1796
1797 /* Configure Rx MAC FIFO */
6b0c1480 1798 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 1799 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 1800
1801 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1802 if (is_yukon_lite_a0(hw))
baef58b1 1803 reg &= ~GMF_RX_F_FL_ON;
c8868611 1804
6b0c1480
SH		 1805 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1806 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 1807 /*
1808 * because Pause Packet Truncation in GMAC is not working
1809 * we have to increase the Flush Threshold to 64 bytes
1810 * in order to flush pause packets in Rx FIFO on Yukon-1
1811 */
1812 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 1813
1814 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1815 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1816 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 1817}
1818
355ec572
SH		 1819/* Go into power down mode */
1820static void yukon_suspend(struct skge_hw *hw, int port)
1821{
1822 u16 ctrl;
1823
1824 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1825 ctrl |= PHY_M_PC_POL_R_DIS;
1826 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1827
1828 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1829 ctrl |= PHY_CT_RESET;
1830 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1831
1832 /* switch IEEE compatible power down mode on */
1833 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1834 ctrl |= PHY_CT_PDOWN;
1835 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1836}
1837
baef58b1
SH		 1838static void yukon_stop(struct skge_port *skge)
1839{
1840 struct skge_hw *hw = skge->hw;
1841 int port = skge->port;
1842
46a60f2d
SH		 1843 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1844 yukon_reset(hw, port);
baef58b1 1845
6b0c1480
SH		 1846 gma_write16(hw, port, GM_GP_CTRL,
1847 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 1848 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 1849 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 1850
355ec572 1851 yukon_suspend(hw, port);
46a60f2d 1852
baef58b1 1853 /* set GPHY Control reset */
46a60f2d
SH		 1854 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1855 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1856}
1857
1858static void yukon_get_stats(struct skge_port *skge, u64 *data)
1859{
1860 struct skge_hw *hw = skge->hw;
1861 int port = skge->port;
1862 int i;
1863
6b0c1480
SH		 1864 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1865 | gma_read32(hw, port, GM_TXO_OK_LO);
1866 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1867 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 1868
1869 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1870 data[i] = gma_read32(hw, port,
baef58b1
SH		 1871 skge_stats[i].gma_offset);
1872}
1873
1874static void yukon_mac_intr(struct skge_hw *hw, int port)
1875{
7e676d91
SH		 1876 struct net_device *dev = hw->dev[port];
1877 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1878 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1879
7e676d91
SH		 1880 if (netif_msg_intr(skge))
1881 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1882 dev->name, status);
1883
baef58b1
SH		 1884 if (status & GM_IS_RX_FF_OR) {
1885 ++skge->net_stats.rx_fifo_errors;
d8a09943 1886 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 1887 }
d8a09943 1888
baef58b1
SH		 1889 if (status & GM_IS_TX_FF_UR) {
1890 ++skge->net_stats.tx_fifo_errors;
d8a09943 1891 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 1892 }
1893
1894}
1895
1896static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1897{
95566065 1898 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 1899 case PHY_M_PS_SPEED_1000:
1900 return SPEED_1000;
1901 case PHY_M_PS_SPEED_100:
1902 return SPEED_100;
1903 default:
1904 return SPEED_10;
1905 }
1906}
1907
1908static void yukon_link_up(struct skge_port *skge)
1909{
1910 struct skge_hw *hw = skge->hw;
1911 int port = skge->port;
1912 u16 reg;
1913
baef58b1 1914 /* Enable Transmit FIFO Underrun */
46a60f2d 1915 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 1916
6b0c1480 1917 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1918 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1919 reg |= GM_GPCR_DUP_FULL;
1920
1921 /* enable Rx/Tx */
1922 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 1923 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 1924
4cde06ed 1925 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1926 skge_link_up(skge);
1927}
1928
1929static void yukon_link_down(struct skge_port *skge)
1930{
1931 struct skge_hw *hw = skge->hw;
1932 int port = skge->port;
d8a09943 1933 u16 ctrl;
baef58b1 1934
6b0c1480 1935 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
d8a09943
SH		 1936
1937 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1938 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1939 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 1940
c506a509 1941 if (skge->flow_control == FLOW_MODE_REM_SEND) {
baef58b1 1942 /* restore Asymmetric Pause bit */
6b0c1480
SH		 1943 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1944 gm_phy_read(hw, port,
baef58b1
SH		 1945 PHY_MARV_AUNE_ADV)
1946 | PHY_M_AN_ASP);
1947
1948 }
1949
1950 yukon_reset(hw, port);
1951 skge_link_down(skge);
1952
1953 yukon_init(hw, port);
1954}
1955
1956static void yukon_phy_intr(struct skge_port *skge)
1957{
1958 struct skge_hw *hw = skge->hw;
1959 int port = skge->port;
1960 const char *reason = NULL;
1961 u16 istatus, phystat;
1962
6b0c1480
SH		 1963 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1964 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 1965
1966 if (netif_msg_intr(skge))
1967 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1968 skge->netdev->name, istatus, phystat);
baef58b1
SH		 1969
1970 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 1971 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 1972 & PHY_M_AN_RF) {
1973 reason = "remote fault";
1974 goto failed;
1975 }
1976
c506a509 1977 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 1978 reason = "master/slave fault";
1979 goto failed;
1980 }
1981
1982 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1983 reason = "speed/duplex";
1984 goto failed;
1985 }
1986
1987 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1988 ? DUPLEX_FULL : DUPLEX_HALF;
1989 skge->speed = yukon_speed(hw, phystat);
1990
baef58b1
SH		 1991 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1992 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1993 case PHY_M_PS_PAUSE_MSK:
1994 skge->flow_control = FLOW_MODE_SYMMETRIC;
1995 break;
1996 case PHY_M_PS_RX_P_EN:
1997 skge->flow_control = FLOW_MODE_REM_SEND;
1998 break;
1999 case PHY_M_PS_TX_P_EN:
2000 skge->flow_control = FLOW_MODE_LOC_SEND;
2001 break;
2002 default:
2003 skge->flow_control = FLOW_MODE_NONE;
2004 }
2005
2006 if (skge->flow_control == FLOW_MODE_NONE ||
2007 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2008 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2009 else
6b0c1480 2010 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2011 yukon_link_up(skge);
2012 return;
2013 }
2014
2015 if (istatus & PHY_M_IS_LSP_CHANGE)
2016 skge->speed = yukon_speed(hw, phystat);
2017
2018 if (istatus & PHY_M_IS_DUP_CHANGE)
2019 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2020 if (istatus & PHY_M_IS_LST_CHANGE) {
2021 if (phystat & PHY_M_PS_LINK_UP)
2022 yukon_link_up(skge);
2023 else
2024 yukon_link_down(skge);
2025 }
2026 return;
2027 failed:
2028 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2029 skge->netdev->name, reason);
2030
2031 /* XXX restart autonegotiation? */
2032}
2033
ee294dcd
SH		 2034static void skge_phy_reset(struct skge_port *skge)
2035{
2036 struct skge_hw *hw = skge->hw;
2037 int port = skge->port;
2038
2039 netif_stop_queue(skge->netdev);
2040 netif_carrier_off(skge->netdev);
2041
2042 spin_lock_bh(&hw->phy_lock);
2043 if (hw->chip_id == CHIP_ID_GENESIS) {
2044 genesis_reset(hw, port);
2045 genesis_mac_init(hw, port);
2046 } else {
2047 yukon_reset(hw, port);
2048 yukon_init(hw, port);
2049 }
2050 spin_unlock_bh(&hw->phy_lock);
2051}
2052
2cd8e5d3
SH		 2053/* Basic MII support */
2054static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2055{
2056 struct mii_ioctl_data *data = if_mii(ifr);
2057 struct skge_port *skge = netdev_priv(dev);
2058 struct skge_hw *hw = skge->hw;
2059 int err = -EOPNOTSUPP;
2060
2061 if (!netif_running(dev))
2062 return -ENODEV; /* Phy still in reset */
2063
2064 switch(cmd) {
2065 case SIOCGMIIPHY:
2066 data->phy_id = hw->phy_addr;
2067
2068 /* fallthru */
2069 case SIOCGMIIREG: {
2070 u16 val = 0;
2071 spin_lock_bh(&hw->phy_lock);
2072 if (hw->chip_id == CHIP_ID_GENESIS)
2073 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2074 else
2075 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2076 spin_unlock_bh(&hw->phy_lock);
2077 data->val_out = val;
2078 break;
2079 }
2080
2081 case SIOCSMIIREG:
2082 if (!capable(CAP_NET_ADMIN))
2083 return -EPERM;
2084
2085 spin_lock_bh(&hw->phy_lock);
2086 if (hw->chip_id == CHIP_ID_GENESIS)
2087 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2088 data->val_in);
2089 else
2090 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2091 data->val_in);
2092 spin_unlock_bh(&hw->phy_lock);
2093 break;
2094 }
2095 return err;
2096}
2097
baef58b1
SH		 2098static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2099{
2100 u32 end;
2101
2102 start /= 8;
2103 len /= 8;
2104 end = start + len - 1;
2105
2106 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2107 skge_write32(hw, RB_ADDR(q, RB_START), start);
2108 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2109 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2110 skge_write32(hw, RB_ADDR(q, RB_END), end);
2111
2112 if (q == Q_R1 || q == Q_R2) {
2113 /* Set thresholds on receive queue's */
2114 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2115 start + (2*len)/3);
2116 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2117 start + (len/3));
2118 } else {
2119 /* Enable store & forward on Tx queue's because
2120 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2121 */
2122 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2123 }
2124
2125 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2126}
2127
2128/* Setup Bus Memory Interface */
2129static void skge_qset(struct skge_port *skge, u16 q,
2130 const struct skge_element *e)
2131{
2132 struct skge_hw *hw = skge->hw;
2133 u32 watermark = 0x600;
2134 u64 base = skge->dma + (e->desc - skge->mem);
2135
2136 /* optimization to reduce window on 32bit/33mhz */
2137 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2138 watermark /= 2;
2139
2140 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2141 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2142 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2143 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2144}
2145
2146static int skge_up(struct net_device *dev)
2147{
2148 struct skge_port *skge = netdev_priv(dev);
2149 struct skge_hw *hw = skge->hw;
2150 int port = skge->port;
2151 u32 chunk, ram_addr;
2152 size_t rx_size, tx_size;
2153 int err;
2154
2155 if (netif_msg_ifup(skge))
2156 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2157
19a33d4e 2158 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2159 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2160 else
2161 skge->rx_buf_size = RX_BUF_SIZE;
2162
2163
baef58b1
SH		 2164 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2165 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2166 skge->mem_size = tx_size + rx_size;
2167 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2168 if (!skge->mem)
2169 return -ENOMEM;
2170
c3da1447
SH		 2171 BUG_ON(skge->dma & 7);
2172
2173 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2174 printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
2175 err = -EINVAL;
2176 goto free_pci_mem;
2177 }
2178
baef58b1
SH		 2179 memset(skge->mem, 0, skge->mem_size);
2180
203babb6
SH		 2181 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2182 if (err)
baef58b1
SH		 2183 goto free_pci_mem;
2184
19a33d4e
SH		 2185 err = skge_rx_fill(skge);
2186 if (err)
baef58b1
SH		 2187 goto free_rx_ring;
2188
203babb6
SH		 2189 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2190 skge->dma + rx_size);
2191 if (err)
baef58b1
SH		 2192 goto free_rx_ring;
2193
8f3f8193 2194 /* Initialize MAC */
4ff6ac05 2195 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2196 if (hw->chip_id == CHIP_ID_GENESIS)
2197 genesis_mac_init(hw, port);
2198 else
2199 yukon_mac_init(hw, port);
4ff6ac05 2200 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 2201
2202 /* Configure RAMbuffers */
981d0377 2203 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2204 ram_addr = hw->ram_offset + 2 * chunk * port;
2205
2206 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2207 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2208
2209 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2210 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2211 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2212
2213 /* Start receiver BMU */
2214 wmb();
2215 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2216 skge_led(skge, LED_MODE_ON);
baef58b1 2217
baef58b1
SH		 2218 return 0;
2219
2220 free_rx_ring:
2221 skge_rx_clean(skge);
2222 kfree(skge->rx_ring.start);
2223 free_pci_mem:
2224 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2225 skge->mem = NULL;
baef58b1
SH		 2226
2227 return err;
2228}
2229
2230static int skge_down(struct net_device *dev)
2231{
2232 struct skge_port *skge = netdev_priv(dev);
2233 struct skge_hw *hw = skge->hw;
2234 int port = skge->port;
2235
7731a4ea
SH		 2236 if (skge->mem == NULL)
2237 return 0;
2238
baef58b1
SH		 2239 if (netif_msg_ifdown(skge))
2240 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2241
2242 netif_stop_queue(dev);
2243
46a60f2d
SH		 2244 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2245 if (hw->chip_id == CHIP_ID_GENESIS)
2246 genesis_stop(skge);
2247 else
2248 yukon_stop(skge);
2249
baef58b1
SH		 2250 /* Stop transmitter */
2251 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2252 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2253 RB_RST_SET|RB_DIS_OP_MD);
2254
baef58b1
SH		 2255
2256 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2257 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2258 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2259
2260 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2261 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2262 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2263
2264 /* Reset PCI FIFO */
2265 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2266 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2267
2268 /* Reset the RAM Buffer async Tx queue */
2269 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2270 /* stop receiver */
2271 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2272 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2273 RB_RST_SET|RB_DIS_OP_MD);
2274 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2275
2276 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2277 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2278 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2279 } else {
6b0c1480
SH		 2280 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2281 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2282 }
2283
6abebb53 2284 skge_led(skge, LED_MODE_OFF);
baef58b1
SH		 2285
2286 skge_tx_clean(skge);
2287 skge_rx_clean(skge);
2288
2289 kfree(skge->rx_ring.start);
2290 kfree(skge->tx_ring.start);
2291 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2292 skge->mem = NULL;
baef58b1
SH		 2293 return 0;
2294}
2295
29b4e886
SH		 2296static inline int skge_avail(const struct skge_ring *ring)
2297{
2298 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2299 + (ring->to_clean - ring->to_use) - 1;
2300}
2301
baef58b1
SH		 2302static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2303{
2304 struct skge_port *skge = netdev_priv(dev);
2305 struct skge_hw *hw = skge->hw;
2306 struct skge_ring *ring = &skge->tx_ring;
2307 struct skge_element *e;
2308 struct skge_tx_desc *td;
2309 int i;
2310 u32 control, len;
2311 u64 map;
baef58b1
SH		 2312
2313 skb = skb_padto(skb, ETH_ZLEN);
2314 if (!skb)
2315 return NETDEV_TX_OK;
2316
baef58b1 2317 if (!spin_trylock(&skge->tx_lock)) {
203babb6
SH		 2318 /* Collision - tell upper layer to requeue */
2319 return NETDEV_TX_LOCKED;
2320 }
baef58b1 2321
29b4e886 2322 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1)) {
98684a9d 2323 if (!netif_queue_stopped(dev)) {
ee1c8191 2324 netif_stop_queue(dev);
baef58b1 2325
ee1c8191
SH		 2326 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2327 dev->name);
2328 }
00a6cae2 2329 spin_unlock(&skge->tx_lock);
baef58b1
SH		 2330 return NETDEV_TX_BUSY;
2331 }
2332
2333 e = ring->to_use;
2334 td = e->desc;
2335 e->skb = skb;
2336 len = skb_headlen(skb);
2337 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2338 pci_unmap_addr_set(e, mapaddr, map);
2339 pci_unmap_len_set(e, maplen, len);
2340
2341 td->dma_lo = map;
2342 td->dma_hi = map >> 32;
2343
2344 if (skb->ip_summed == CHECKSUM_HW) {
baef58b1
SH		 2345 int offset = skb->h.raw - skb->data;
2346
2347 /* This seems backwards, but it is what the sk98lin
2348 * does. Looks like hardware is wrong?
2349 */
ea182d4a 2350 if (skb->h.ipiph->protocol == IPPROTO_UDP
981d0377 2351 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2352 control = BMU_TCP_CHECK;
2353 else
2354 control = BMU_UDP_CHECK;
2355
2356 td->csum_offs = 0;
2357 td->csum_start = offset;
2358 td->csum_write = offset + skb->csum;
2359 } else
2360 control = BMU_CHECK;
2361
2362 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2363 control |= BMU_EOF| BMU_IRQ_EOF;
2364 else {
2365 struct skge_tx_desc *tf = td;
2366
2367 control |= BMU_STFWD;
2368 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2369 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2370
2371 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2372 frag->size, PCI_DMA_TODEVICE);
2373
2374 e = e->next;
2375 e->skb = NULL;
2376 tf = e->desc;
2377 tf->dma_lo = map;
2378 tf->dma_hi = (u64) map >> 32;
2379 pci_unmap_addr_set(e, mapaddr, map);
2380 pci_unmap_len_set(e, maplen, frag->size);
2381
2382 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2383 }
2384 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2385 }
2386 /* Make sure all the descriptors written */
2387 wmb();
2388 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2389 wmb();
2390
2391 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2392
2393 if (netif_msg_tx_queued(skge))
0b2d7fea 2394 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
baef58b1
SH		 2395 dev->name, e - ring->start, skb->len);
2396
2397 ring->to_use = e->next;
29b4e886 2398 if (skge_avail(&skge->tx_ring) <= MAX_SKB_FRAGS + 1) {
baef58b1
SH		 2399 pr_debug("%s: transmit queue full\n", dev->name);
2400 netif_stop_queue(dev);
2401 }
2402
c68ce71a 2403 mmiowb();
00a6cae2 2404 spin_unlock(&skge->tx_lock);
baef58b1 2405
c68ce71a
SH		 2406 dev->trans_start = jiffies;
2407
baef58b1
SH		 2408 return NETDEV_TX_OK;
2409}
2410
866b4f3e
SH		 2411static void skge_tx_complete(struct skge_port *skge, struct skge_element *last)
2412{
2413 struct pci_dev *pdev = skge->hw->pdev;
2414 struct skge_element *e;
2415
2416 for (e = skge->tx_ring.to_clean; e != last; e = e->next) {
2417 struct sk_buff *skb = e->skb;
2418 int i;
2419
baef58b1 2420 e->skb = NULL;
866b4f3e
SH		 2421 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2422 skb_headlen(skb), PCI_DMA_TODEVICE);
866b4f3e
SH		 2423
2424 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2425 e = e->next;
2426 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2427 skb_shinfo(skb)->frags[i].size,
2428 PCI_DMA_TODEVICE);
866b4f3e
SH		 2429 }
2430
2431 dev_kfree_skb(skb);
baef58b1 2432 }
866b4f3e 2433 skge->tx_ring.to_clean = e;
baef58b1
SH		 2434}
2435
2436static void skge_tx_clean(struct skge_port *skge)
2437{
baef58b1 2438
00a6cae2 2439 spin_lock_bh(&skge->tx_lock);
866b4f3e
SH		 2440 skge_tx_complete(skge, skge->tx_ring.to_use);
2441 netif_wake_queue(skge->netdev);
00a6cae2 2442 spin_unlock_bh(&skge->tx_lock);
baef58b1
SH		 2443}
2444
2445static void skge_tx_timeout(struct net_device *dev)
2446{
2447 struct skge_port *skge = netdev_priv(dev);
2448
2449 if (netif_msg_timer(skge))
2450 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2451
2452 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2453 skge_tx_clean(skge);
2454}
2455
2456static int skge_change_mtu(struct net_device *dev, int new_mtu)
2457{
7731a4ea 2458 int err;
baef58b1 2459
95566065 2460 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2461 return -EINVAL;
2462
7731a4ea
SH		 2463 if (!netif_running(dev)) {
2464 dev->mtu = new_mtu;
2465 return 0;
2466 }
2467
2468 skge_down(dev);
baef58b1 2469
19a33d4e 2470 dev->mtu = new_mtu;
7731a4ea
SH		 2471
2472 err = skge_up(dev);
2473 if (err)
2474 dev_close(dev);
baef58b1
SH		 2475
2476 return err;
2477}
2478
2479static void genesis_set_multicast(struct net_device *dev)
2480{
2481 struct skge_port *skge = netdev_priv(dev);
2482 struct skge_hw *hw = skge->hw;
2483 int port = skge->port;
2484 int i, count = dev->mc_count;
2485 struct dev_mc_list *list = dev->mc_list;
2486 u32 mode;
2487 u8 filter[8];
2488
6b0c1480 2489 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2490 mode |= XM_MD_ENA_HASH;
2491 if (dev->flags & IFF_PROMISC)
2492 mode |= XM_MD_ENA_PROM;
2493 else
2494 mode &= ~XM_MD_ENA_PROM;
2495
2496 if (dev->flags & IFF_ALLMULTI)
2497 memset(filter, 0xff, sizeof(filter));
2498 else {
2499 memset(filter, 0, sizeof(filter));
95566065 2500 for (i = 0; list && i < count; i++, list = list->next) {
45bada65
SH		 2501 u32 crc, bit;
2502 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2503 bit = ~crc & 0x3f;
baef58b1
SH		 2504 filter[bit/8] |= 1 << (bit%8);
2505 }
2506 }
2507
6b0c1480 2508 xm_write32(hw, port, XM_MODE, mode);
45bada65 2509 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2510}
2511
2512static void yukon_set_multicast(struct net_device *dev)
2513{
2514 struct skge_port *skge = netdev_priv(dev);
2515 struct skge_hw *hw = skge->hw;
2516 int port = skge->port;
2517 struct dev_mc_list *list = dev->mc_list;
2518 u16 reg;
2519 u8 filter[8];
2520
2521 memset(filter, 0, sizeof(filter));
2522
6b0c1480 2523 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2524 reg |= GM_RXCR_UCF_ENA;
2525
8f3f8193 2526 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2527 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2528 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2529 memset(filter, 0xff, sizeof(filter));
2530 else if (dev->mc_count == 0) /* no multicast */
2531 reg &= ~GM_RXCR_MCF_ENA;
2532 else {
2533 int i;
2534 reg |= GM_RXCR_MCF_ENA;
2535
95566065 2536 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2537 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2538 filter[bit/8] |= 1 << (bit%8);
2539 }
2540 }
2541
2542
6b0c1480 2543 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2544 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2545 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2546 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2547 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2548 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2549 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2550 (u16)filter[6] | ((u16)filter[7] << 8));
2551
6b0c1480 2552 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2553}
2554
383181ac
SH		 2555static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2556{
2557 if (hw->chip_id == CHIP_ID_GENESIS)
2558 return status >> XMR_FS_LEN_SHIFT;
2559 else
2560 return status >> GMR_FS_LEN_SHIFT;
2561}
2562
baef58b1
SH		 2563static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2564{
2565 if (hw->chip_id == CHIP_ID_GENESIS)
2566 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2567 else
2568 return (status & GMR_FS_ANY_ERR) ||
2569 (status & GMR_FS_RX_OK) == 0;
2570}
2571
19a33d4e
SH		 2572
2573/* Get receive buffer from descriptor.
2574 * Handles copy of small buffers and reallocation failures
2575 */
2576static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2577 struct skge_element *e,
383181ac 2578 u32 control, u32 status, u16 csum)
19a33d4e 2579{
383181ac
SH		 2580 struct sk_buff *skb;
2581 u16 len = control & BMU_BBC;
2582
2583 if (unlikely(netif_msg_rx_status(skge)))
2584 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2585 skge->netdev->name, e - skge->rx_ring.start,
2586 status, len);
2587
2588 if (len > skge->rx_buf_size)
2589 goto error;
2590
2591 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2592 goto error;
2593
2594 if (bad_phy_status(skge->hw, status))
2595 goto error;
2596
2597 if (phy_length(skge->hw, status) != len)
2598 goto error;
19a33d4e
SH		 2599
2600 if (len < RX_COPY_THRESHOLD) {
b5d56ddc 2601 skb = alloc_skb(len + 2, GFP_ATOMIC);
383181ac
SH		 2602 if (!skb)
2603 goto resubmit;
19a33d4e 2604
383181ac 2605 skb_reserve(skb, 2);
19a33d4e
SH		 2606 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2607 pci_unmap_addr(e, mapaddr),
2608 len, PCI_DMA_FROMDEVICE);
383181ac 2609 memcpy(skb->data, e->skb->data, len);
19a33d4e
SH		 2610 pci_dma_sync_single_for_device(skge->hw->pdev,
2611 pci_unmap_addr(e, mapaddr),
2612 len, PCI_DMA_FROMDEVICE);
19a33d4e 2613 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 2614 } else {
383181ac 2615 struct sk_buff *nskb;
b5d56ddc 2616 nskb = alloc_skb(skge->rx_buf_size + NET_IP_ALIGN, GFP_ATOMIC);
383181ac
SH		 2617 if (!nskb)
2618 goto resubmit;
19a33d4e 2619
901ccefb 2620 skb_reserve(nskb, NET_IP_ALIGN);
19a33d4e
SH		 2621 pci_unmap_single(skge->hw->pdev,
2622 pci_unmap_addr(e, mapaddr),
2623 pci_unmap_len(e, maplen),
2624 PCI_DMA_FROMDEVICE);
2625 skb = e->skb;
383181ac 2626 prefetch(skb->data);
19a33d4e 2627 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 2628 }
383181ac
SH		 2629
2630 skb_put(skb, len);
2631 skb->dev = skge->netdev;
2632 if (skge->rx_csum) {
2633 skb->csum = csum;
2634 skb->ip_summed = CHECKSUM_HW;
2635 }
2636
2637 skb->protocol = eth_type_trans(skb, skge->netdev);
2638
2639 return skb;
2640error:
2641
2642 if (netif_msg_rx_err(skge))
2643 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2644 skge->netdev->name, e - skge->rx_ring.start,
2645 control, status);
2646
2647 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2648 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2649 skge->net_stats.rx_length_errors++;
2650 if (status & XMR_FS_FRA_ERR)
2651 skge->net_stats.rx_frame_errors++;
2652 if (status & XMR_FS_FCS_ERR)
2653 skge->net_stats.rx_crc_errors++;
2654 } else {
2655 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2656 skge->net_stats.rx_length_errors++;
2657 if (status & GMR_FS_FRAGMENT)
2658 skge->net_stats.rx_frame_errors++;
2659 if (status & GMR_FS_CRC_ERR)
2660 skge->net_stats.rx_crc_errors++;
2661 }
2662
2663resubmit:
2664 skge_rx_reuse(e, skge->rx_buf_size);
2665 return NULL;
baef58b1
SH		 2666}
2667
00a6cae2
SH		 2668static void skge_tx_done(struct skge_port *skge)
2669{
2670 struct skge_ring *ring = &skge->tx_ring;
866b4f3e 2671 struct skge_element *e, *last;
00a6cae2
SH		 2672
2673 spin_lock(&skge->tx_lock);
866b4f3e
SH		 2674 last = ring->to_clean;
2675 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
00a6cae2 2676 struct skge_tx_desc *td = e->desc;
00a6cae2 2677
866b4f3e 2678 if (td->control & BMU_OWN)
00a6cae2
SH		 2679 break;
2680
866b4f3e
SH		 2681 if (td->control & BMU_EOF) {
2682 last = e->next;
2683 if (unlikely(netif_msg_tx_done(skge)))
2684 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2685 skge->netdev->name, e - ring->start);
2686 }
00a6cae2 2687 }
866b4f3e
SH		 2688
2689 skge_tx_complete(skge, last);
2690
00a6cae2
SH		 2691 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2692
29b4e886 2693 if (skge_avail(&skge->tx_ring) > MAX_SKB_FRAGS + 1)
00a6cae2
SH		 2694 netif_wake_queue(skge->netdev);
2695
2696 spin_unlock(&skge->tx_lock);
2697}
19a33d4e 2698
baef58b1
SH		 2699static int skge_poll(struct net_device *dev, int *budget)
2700{
2701 struct skge_port *skge = netdev_priv(dev);
2702 struct skge_hw *hw = skge->hw;
2703 struct skge_ring *ring = &skge->rx_ring;
2704 struct skge_element *e;
00a6cae2
SH		 2705 int to_do = min(dev->quota, *budget);
2706 int work_done = 0;
2707
2708 skge_tx_done(skge);
7e676d91 2709
1631aef1 2710 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 2711 struct skge_rx_desc *rd = e->desc;
19a33d4e 2712 struct sk_buff *skb;
383181ac 2713 u32 control;
baef58b1
SH		 2714
2715 rmb();
2716 control = rd->control;
2717 if (control & BMU_OWN)
2718 break;
2719
203babb6
SH		 2720 skb = skge_rx_get(skge, e, control, rd->status,
2721 le16_to_cpu(rd->csum2));
19a33d4e 2722 if (likely(skb)) {
19a33d4e
SH		 2723 dev->last_rx = jiffies;
2724 netif_receive_skb(skb);
baef58b1 2725
19a33d4e 2726 ++work_done;
5a011447 2727 }
baef58b1
SH		 2728 }
2729 ring->to_clean = e;
2730
baef58b1
SH		 2731 /* restart receiver */
2732 wmb();
a9cdab86 2733 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 2734
19a33d4e
SH		 2735 *budget -= work_done;
2736 dev->quota -= work_done;
2737
2738 if (work_done >= to_do)
2739 return 1; /* not done */
baef58b1 2740
cfc3ed79 2741 netif_rx_complete(dev);
c68ce71a
SH		 2742 mmiowb();
2743
cfc3ed79 2744 hw->intr_mask |= skge->port == 0 ? (IS_R1_F|IS_XA1_F) : (IS_R2_F|IS_XA2_F);
80dd857d 2745 skge_write32(hw, B0_IMSK, hw->intr_mask);
1631aef1 2746
19a33d4e 2747 return 0;
baef58b1
SH		 2748}
2749
f6620cab
SH		 2750/* Parity errors seem to happen when Genesis is connected to a switch
2751 * with no other ports present. Heartbeat error??
2752 */
baef58b1
SH		 2753static void skge_mac_parity(struct skge_hw *hw, int port)
2754{
f6620cab
SH		 2755 struct net_device *dev = hw->dev[port];
2756
2757 if (dev) {
2758 struct skge_port *skge = netdev_priv(dev);
2759 ++skge->net_stats.tx_heartbeat_errors;
2760 }
baef58b1
SH		 2761
2762 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2763 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2764 MFF_CLR_PERR);
2765 else
2766 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2767 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2768 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2769 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2770}
2771
baef58b1
SH		 2772static void skge_mac_intr(struct skge_hw *hw, int port)
2773{
95566065 2774 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2775 genesis_mac_intr(hw, port);
2776 else
2777 yukon_mac_intr(hw, port);
2778}
2779
2780/* Handle device specific framing and timeout interrupts */
2781static void skge_error_irq(struct skge_hw *hw)
2782{
2783 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2784
2785 if (hw->chip_id == CHIP_ID_GENESIS) {
2786 /* clear xmac errors */
2787 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 2788 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 2789 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 2790 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 2791 } else {
2792 /* Timestamp (unused) overflow */
2793 if (hwstatus & IS_IRQ_TIST_OV)
2794 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 2795 }
2796
2797 if (hwstatus & IS_RAM_RD_PAR) {
2798 printk(KERN_ERR PFX "Ram read data parity error\n");
2799 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2800 }
2801
2802 if (hwstatus & IS_RAM_WR_PAR) {
2803 printk(KERN_ERR PFX "Ram write data parity error\n");
2804 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2805 }
2806
2807 if (hwstatus & IS_M1_PAR_ERR)
2808 skge_mac_parity(hw, 0);
2809
2810 if (hwstatus & IS_M2_PAR_ERR)
2811 skge_mac_parity(hw, 1);
2812
b9d64acc
SH		 2813 if (hwstatus & IS_R1_PAR_ERR) {
2814 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2815 hw->dev[0]->name);
baef58b1 2816 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 2817 }
baef58b1 2818
b9d64acc
SH		 2819 if (hwstatus & IS_R2_PAR_ERR) {
2820 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2821 hw->dev[1]->name);
baef58b1 2822 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 2823 }
baef58b1
SH		 2824
2825 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 2826 u16 pci_status, pci_cmd;
2827
2828 pci_read_config_word(hw->pdev, PCI_COMMAND, &pci_cmd);
2829 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
baef58b1 2830
b9d64acc
SH		 2831 printk(KERN_ERR PFX "%s: PCI error cmd=%#x status=%#x\n",
2832 pci_name(hw->pdev), pci_cmd, pci_status);
2833
2834 /* Write the error bits back to clear them. */
2835 pci_status &= PCI_STATUS_ERROR_BITS;
2836 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2837 pci_write_config_word(hw->pdev, PCI_COMMAND,
2838 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2839 pci_write_config_word(hw->pdev, PCI_STATUS, pci_status);
2840 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 2841
050ec18a 2842 /* if error still set then just ignore it */
baef58b1
SH		 2843 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2844 if (hwstatus & IS_IRQ_STAT) {
b9d64acc 2845 printk(KERN_INFO PFX "unable to clear error (so ignoring them)\n");
baef58b1
SH		 2846 hw->intr_mask &= ~IS_HW_ERR;
2847 }
2848 }
2849}
2850
2851/*
8f3f8193 2852 * Interrupt from PHY are handled in tasklet (soft irq)
baef58b1
SH		 2853 * because accessing phy registers requires spin wait which might
2854 * cause excess interrupt latency.
2855 */
2856static void skge_extirq(unsigned long data)
2857{
2858 struct skge_hw *hw = (struct skge_hw *) data;
2859 int port;
2860
2861 spin_lock(&hw->phy_lock);
cfc3ed79 2862 for (port = 0; port < hw->ports; port++) {
baef58b1 2863 struct net_device *dev = hw->dev[port];
cfc3ed79 2864 struct skge_port *skge = netdev_priv(dev);
baef58b1 2865
cfc3ed79 2866 if (netif_running(dev)) {
baef58b1
SH		 2867 if (hw->chip_id != CHIP_ID_GENESIS)
2868 yukon_phy_intr(skge);
89bf5f23 2869 else
45bada65 2870 bcom_phy_intr(skge);
baef58b1
SH		 2871 }
2872 }
2873 spin_unlock(&hw->phy_lock);
2874
baef58b1
SH		 2875 hw->intr_mask |= IS_EXT_REG;
2876 skge_write32(hw, B0_IMSK, hw->intr_mask);
baef58b1
SH		 2877}
2878
2879static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2880{
2881 struct skge_hw *hw = dev_id;
cfc3ed79 2882 u32 status;
baef58b1 2883
cfc3ed79
SH		 2884 /* Reading this register masks IRQ */
2885 status = skge_read32(hw, B0_SP_ISRC);
2886 if (status == 0)
baef58b1
SH		 2887 return IRQ_NONE;
2888
cfc3ed79
SH		 2889 if (status & IS_EXT_REG) {
2890 hw->intr_mask &= ~IS_EXT_REG;
2891 tasklet_schedule(&hw->ext_tasklet);
2892 }
2893
00a6cae2 2894 if (status & (IS_R1_F|IS_XA1_F)) {
a9cdab86 2895 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
00a6cae2 2896 hw->intr_mask &= ~(IS_R1_F|IS_XA1_F);
a9cdab86 2897 netif_rx_schedule(hw->dev[0]);
baef58b1
SH		 2898 }
2899
00a6cae2 2900 if (status & (IS_R2_F|IS_XA2_F)) {
a9cdab86 2901 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
00a6cae2 2902 hw->intr_mask &= ~(IS_R2_F|IS_XA2_F);
a9cdab86 2903 netif_rx_schedule(hw->dev[1]);
baef58b1
SH		 2904 }
2905
cfc3ed79
SH		 2906 if (likely((status & hw->intr_mask) == 0))
2907 return IRQ_HANDLED;
2908
d25f5a67
SH		 2909 if (status & IS_PA_TO_RX1) {
2910 struct skge_port *skge = netdev_priv(hw->dev[0]);
2911 ++skge->net_stats.rx_over_errors;
2912 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2913 }
2914
2915 if (status & IS_PA_TO_RX2) {
2916 struct skge_port *skge = netdev_priv(hw->dev[1]);
2917 ++skge->net_stats.rx_over_errors;
2918 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2919 }
2920
2921 if (status & IS_PA_TO_TX1)
2922 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2923
2924 if (status & IS_PA_TO_TX2)
2925 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2926
baef58b1
SH		 2927 if (status & IS_MAC1)
2928 skge_mac_intr(hw, 0);
95566065 2929
baef58b1
SH		 2930 if (status & IS_MAC2)
2931 skge_mac_intr(hw, 1);
2932
2933 if (status & IS_HW_ERR)
2934 skge_error_irq(hw);
2935
7e676d91 2936 skge_write32(hw, B0_IMSK, hw->intr_mask);
baef58b1
SH		 2937
2938 return IRQ_HANDLED;
2939}
2940
2941#ifdef CONFIG_NET_POLL_CONTROLLER
2942static void skge_netpoll(struct net_device *dev)
2943{
2944 struct skge_port *skge = netdev_priv(dev);
2945
2946 disable_irq(dev->irq);
2947 skge_intr(dev->irq, skge->hw, NULL);
2948 enable_irq(dev->irq);
2949}
2950#endif
2951
2952static int skge_set_mac_address(struct net_device *dev, void *p)
2953{
2954 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 2955 struct skge_hw *hw = skge->hw;
2956 unsigned port = skge->port;
2957 const struct sockaddr *addr = p;
baef58b1
SH		 2958
2959 if (!is_valid_ether_addr(addr->sa_data))
2960 return -EADDRNOTAVAIL;
2961
c2681dd8 2962 spin_lock_bh(&hw->phy_lock);
baef58b1 2963 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 2964 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
baef58b1 2965 dev->dev_addr, ETH_ALEN);
c2681dd8 2966 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
baef58b1 2967 dev->dev_addr, ETH_ALEN);
c2681dd8
SH		 2968
2969 if (hw->chip_id == CHIP_ID_GENESIS)
2970 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2971 else {
2972 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2973 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2974 }
2975 spin_unlock_bh(&hw->phy_lock);
2976
2977 return 0;
baef58b1
SH		 2978}
2979
2980static const struct {
2981 u8 id;
2982 const char *name;
2983} skge_chips[] = {
2984 { CHIP_ID_GENESIS, "Genesis" },
2985 { CHIP_ID_YUKON, "Yukon" },
2986 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2987 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 2988};
2989
2990static const char *skge_board_name(const struct skge_hw *hw)
2991{
2992 int i;
2993 static char buf[16];
2994
2995 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2996 if (skge_chips[i].id == hw->chip_id)
2997 return skge_chips[i].name;
2998
2999 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3000 return buf;
3001}
3002
3003
3004/*
3005 * Setup the board data structure, but don't bring up
3006 * the port(s)
3007 */
3008static int skge_reset(struct skge_hw *hw)
3009{
adba9e23 3010 u32 reg;
b9d64acc 3011 u16 ctst, pci_status;
5e1705dd 3012 u8 t8, mac_cfg, pmd_type, phy_type;
981d0377 3013 int i;
baef58b1
SH		 3014
3015 ctst = skge_read16(hw, B0_CTST);
3016
3017 /* do a SW reset */
3018 skge_write8(hw, B0_CTST, CS_RST_SET);
3019 skge_write8(hw, B0_CTST, CS_RST_CLR);
3020
3021 /* clear PCI errors, if any */
b9d64acc
SH		 3022 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3023 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3024
b9d64acc
SH		 3025 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3026 pci_write_config_word(hw->pdev, PCI_STATUS,
3027 pci_status | PCI_STATUS_ERROR_BITS);
3028 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3029 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3030
3031 /* restore CLK_RUN bits (for Yukon-Lite) */
3032 skge_write16(hw, B0_CTST,
3033 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3034
3035 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
5e1705dd
SH		 3036 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3037 pmd_type = skge_read8(hw, B2_PMD_TYP);
3038 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3039
95566065 3040 switch (hw->chip_id) {
baef58b1 3041 case CHIP_ID_GENESIS:
5e1705dd 3042 switch (phy_type) {
baef58b1
SH		 3043 case SK_PHY_BCOM:
3044 hw->phy_addr = PHY_ADDR_BCOM;
3045 break;
3046 default:
3047 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
5e1705dd 3048 pci_name(hw->pdev), phy_type);
baef58b1
SH		 3049 return -EOPNOTSUPP;
3050 }
3051 break;
3052
3053 case CHIP_ID_YUKON:
3054 case CHIP_ID_YUKON_LITE:
3055 case CHIP_ID_YUKON_LP:
5e1705dd
SH		 3056 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3057 hw->copper = 1;
baef58b1
SH		 3058
3059 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3060 break;
3061
3062 default:
3063 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3064 pci_name(hw->pdev), hw->chip_id);
3065 return -EOPNOTSUPP;
3066 }
3067
981d0377
SH		 3068 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3069 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3070 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3071
3072 /* read the adapters RAM size */
3073 t8 = skge_read8(hw, B2_E_0);
3074 if (hw->chip_id == CHIP_ID_GENESIS) {
3075 if (t8 == 3) {
3076 /* special case: 4 x 64k x 36, offset = 0x80000 */
3077 hw->ram_size = 0x100000;
3078 hw->ram_offset = 0x80000;
3079 } else
3080 hw->ram_size = t8 * 512;
3081 }
3082 else if (t8 == 0)
3083 hw->ram_size = 0x20000;
3084 else
3085 hw->ram_size = t8 * 4096;
3086
cfc3ed79
SH		 3087 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
3088 if (hw->ports > 1)
3089 hw->intr_mask |= IS_PORT_2;
3090
baef58b1
SH		 3091 if (hw->chip_id == CHIP_ID_GENESIS)
3092 genesis_init(hw);
3093 else {
3094 /* switch power to VCC (WA for VAUX problem) */
3095 skge_write8(hw, B0_POWER_CTRL,
3096 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3097
050ec18a
SH		 3098 /* avoid boards with stuck Hardware error bits */
3099 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3100 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3101 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3102 hw->intr_mask &= ~IS_HW_ERR;
3103 }
3104
adba9e23
SH		 3105 /* Clear PHY COMA */
3106 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3107 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3108 reg &= ~PCI_PHY_COMA;
3109 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3110 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3111
3112
981d0377 3113 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3114 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3115 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3116 }
3117 }
3118
3119 /* turn off hardware timer (unused) */
3120 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3121 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3122 skge_write8(hw, B0_LED, LED_STAT_ON);
3123
3124 /* enable the Tx Arbiters */
981d0377 3125 for (i = 0; i < hw->ports; i++)
6b0c1480 3126 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3127
3128 /* Initialize ram interface */
3129 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3130
3131 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3132 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3133 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3134 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3135 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3136 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3137 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3138 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3139 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3140 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3141 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3142 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3143
3144 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3145
3146 /* Set interrupt moderation for Transmit only
3147 * Receive interrupts avoided by NAPI
3148 */
3149 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3150 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3151 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3152
baef58b1
SH		 3153 skge_write32(hw, B0_IMSK, hw->intr_mask);
3154
baef58b1 3155 spin_lock_bh(&hw->phy_lock);
981d0377 3156 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3157 if (hw->chip_id == CHIP_ID_GENESIS)
3158 genesis_reset(hw, i);
3159 else
3160 yukon_reset(hw, i);
3161 }
3162 spin_unlock_bh(&hw->phy_lock);
3163
3164 return 0;
3165}
3166
3167/* Initialize network device */
981d0377
SH		 3168static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3169 int highmem)
baef58b1
SH		 3170{
3171 struct skge_port *skge;
3172 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3173
3174 if (!dev) {
3175 printk(KERN_ERR "skge etherdev alloc failed");
3176 return NULL;
3177 }
3178
3179 SET_MODULE_OWNER(dev);
3180 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3181 dev->open = skge_up;
3182 dev->stop = skge_down;
2cd8e5d3 3183 dev->do_ioctl = skge_ioctl;
baef58b1
SH		 3184 dev->hard_start_xmit = skge_xmit_frame;
3185 dev->get_stats = skge_get_stats;
3186 if (hw->chip_id == CHIP_ID_GENESIS)
3187 dev->set_multicast_list = genesis_set_multicast;
3188 else
3189 dev->set_multicast_list = yukon_set_multicast;
3190
3191 dev->set_mac_address = skge_set_mac_address;
3192 dev->change_mtu = skge_change_mtu;
3193 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3194 dev->tx_timeout = skge_tx_timeout;
3195 dev->watchdog_timeo = TX_WATCHDOG;
3196 dev->poll = skge_poll;
3197 dev->weight = NAPI_WEIGHT;
3198#ifdef CONFIG_NET_POLL_CONTROLLER
3199 dev->poll_controller = skge_netpoll;
3200#endif
3201 dev->irq = hw->pdev->irq;
3202 dev->features = NETIF_F_LLTX;
981d0377
SH		 3203 if (highmem)
3204 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3205
3206 skge = netdev_priv(dev);
3207 skge->netdev = dev;
3208 skge->hw = hw;
3209 skge->msg_enable = netif_msg_init(debug, default_msg);
3210 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3211 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3212
3213 /* Auto speed and flow control */
3214 skge->autoneg = AUTONEG_ENABLE;
3215 skge->flow_control = FLOW_MODE_SYMMETRIC;
3216 skge->duplex = -1;
3217 skge->speed = -1;
31b619c5 3218 skge->advertising = skge_supported_modes(hw);
baef58b1
SH		 3219
3220 hw->dev[port] = dev;
3221
3222 skge->port = port;
3223
3224 spin_lock_init(&skge->tx_lock);
3225
baef58b1
SH		 3226 if (hw->chip_id != CHIP_ID_GENESIS) {
3227 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3228 skge->rx_csum = 1;
3229 }
3230
3231 /* read the mac address */
3232 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3233 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3234
3235 /* device is off until link detection */
3236 netif_carrier_off(dev);
3237 netif_stop_queue(dev);
3238
3239 return dev;
3240}
3241
3242static void __devinit skge_show_addr(struct net_device *dev)
3243{
3244 const struct skge_port *skge = netdev_priv(dev);
3245
3246 if (netif_msg_probe(skge))
3247 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3248 dev->name,
3249 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3250 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3251}
3252
3253static int __devinit skge_probe(struct pci_dev *pdev,
3254 const struct pci_device_id *ent)
3255{
3256 struct net_device *dev, *dev1;
3257 struct skge_hw *hw;
3258 int err, using_dac = 0;
3259
203babb6
SH		 3260 err = pci_enable_device(pdev);
3261 if (err) {
baef58b1
SH		 3262 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3263 pci_name(pdev));
3264 goto err_out;
3265 }
3266
203babb6
SH		 3267 err = pci_request_regions(pdev, DRV_NAME);
3268 if (err) {
baef58b1
SH		 3269 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3270 pci_name(pdev));
3271 goto err_out_disable_pdev;
3272 }
3273
3274 pci_set_master(pdev);
3275
93aea718 3276 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
baef58b1 3277 using_dac = 1;
77783a78 3278 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
93aea718
SH		 3279 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3280 using_dac = 0;
3281 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3282 }
3283
3284 if (err) {
3285 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3286 pci_name(pdev));
3287 goto err_out_free_regions;
baef58b1
SH		 3288 }
3289
3290#ifdef __BIG_ENDIAN
8f3f8193 3291 /* byte swap descriptors in hardware */
baef58b1
SH		 3292 {
3293 u32 reg;
3294
3295 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3296 reg |= PCI_REV_DESC;
3297 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3298 }
3299#endif
3300
3301 err = -ENOMEM;
7e863061 3302 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
baef58b1
SH		 3303 if (!hw) {
3304 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3305 pci_name(pdev));
3306 goto err_out_free_regions;
3307 }
3308
baef58b1
SH		 3309 hw->pdev = pdev;
3310 spin_lock_init(&hw->phy_lock);
3311 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3312
3313 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3314 if (!hw->regs) {
3315 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3316 pci_name(pdev));
3317 goto err_out_free_hw;
3318 }
3319
203babb6
SH		 3320 err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw);
3321 if (err) {
baef58b1
SH		 3322 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3323 pci_name(pdev), pdev->irq);
3324 goto err_out_iounmap;
3325 }
3326 pci_set_drvdata(pdev, hw);
3327
3328 err = skge_reset(hw);
3329 if (err)
3330 goto err_out_free_irq;
3331
d7eaee08 3332 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
baef58b1 3333 pci_resource_start(pdev, 0), pdev->irq,
981d0377 3334 skge_board_name(hw), hw->chip_rev);
baef58b1 3335
981d0377 3336 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
baef58b1
SH		 3337 goto err_out_led_off;
3338
203babb6
SH		 3339 err = register_netdev(dev);
3340 if (err) {
baef58b1
SH		 3341 printk(KERN_ERR PFX "%s: cannot register net device\n",
3342 pci_name(pdev));
3343 goto err_out_free_netdev;
3344 }
3345
3346 skge_show_addr(dev);
3347
981d0377 3348 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3349 if (register_netdev(dev1) == 0)
3350 skge_show_addr(dev1);
3351 else {
3352 /* Failure to register second port need not be fatal */
3353 printk(KERN_WARNING PFX "register of second port failed\n");
3354 hw->dev[1] = NULL;
3355 free_netdev(dev1);
3356 }
3357 }
3358
3359 return 0;
3360
3361err_out_free_netdev:
3362 free_netdev(dev);
3363err_out_led_off:
3364 skge_write16(hw, B0_LED, LED_STAT_OFF);
3365err_out_free_irq:
3366 free_irq(pdev->irq, hw);
3367err_out_iounmap:
3368 iounmap(hw->regs);
3369err_out_free_hw:
3370 kfree(hw);
3371err_out_free_regions:
3372 pci_release_regions(pdev);
3373err_out_disable_pdev:
3374 pci_disable_device(pdev);
3375 pci_set_drvdata(pdev, NULL);
3376err_out:
3377 return err;
3378}
3379
3380static void __devexit skge_remove(struct pci_dev *pdev)
3381{
3382 struct skge_hw *hw = pci_get_drvdata(pdev);
3383 struct net_device *dev0, *dev1;
3384
95566065 3385 if (!hw)
baef58b1
SH		 3386 return;
3387
3388 if ((dev1 = hw->dev[1]))
3389 unregister_netdev(dev1);
3390 dev0 = hw->dev[0];
3391 unregister_netdev(dev0);
3392
46a60f2d
SH		 3393 skge_write32(hw, B0_IMSK, 0);
3394 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 3395 skge_write8(hw, B0_CTST, CS_RST_SET);
3396
baef58b1
SH		 3397 tasklet_kill(&hw->ext_tasklet);
3398
3399 free_irq(pdev->irq, hw);
3400 pci_release_regions(pdev);
3401 pci_disable_device(pdev);
3402 if (dev1)
3403 free_netdev(dev1);
3404 free_netdev(dev0);
46a60f2d 3405
baef58b1
SH		 3406 iounmap(hw->regs);
3407 kfree(hw);
3408 pci_set_drvdata(pdev, NULL);
3409}
3410
3411#ifdef CONFIG_PM
2a569579 3412static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3413{
3414 struct skge_hw *hw = pci_get_drvdata(pdev);
3415 int i, wol = 0;
3416
95566065 3417 for (i = 0; i < 2; i++) {
baef58b1
SH		 3418 struct net_device *dev = hw->dev[i];
3419
3420 if (dev) {
3421 struct skge_port *skge = netdev_priv(dev);
3422 if (netif_running(dev)) {
3423 netif_carrier_off(dev);
46a60f2d
SH		 3424 if (skge->wol)
3425 netif_stop_queue(dev);
3426 else
3427 skge_down(dev);
baef58b1
SH		 3428 }
3429 netif_device_detach(dev);
3430 wol |= skge->wol;
3431 }
3432 }
3433
3434 pci_save_state(pdev);
2a569579 3435 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3436 pci_disable_device(pdev);
3437 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3438
3439 return 0;
3440}
3441
3442static int skge_resume(struct pci_dev *pdev)
3443{
3444 struct skge_hw *hw = pci_get_drvdata(pdev);
3445 int i;
3446
3447 pci_set_power_state(pdev, PCI_D0);
3448 pci_restore_state(pdev);
3449 pci_enable_wake(pdev, PCI_D0, 0);
3450
3451 skge_reset(hw);
3452
95566065 3453 for (i = 0; i < 2; i++) {
baef58b1
SH		 3454 struct net_device *dev = hw->dev[i];
3455 if (dev) {
3456 netif_device_attach(dev);
edd702e8
SH		 3457 if (netif_running(dev) && skge_up(dev))
3458 dev_close(dev);
baef58b1
SH		 3459 }
3460 }
3461 return 0;
3462}
3463#endif
3464
3465static struct pci_driver skge_driver = {
3466 .name = DRV_NAME,
3467 .id_table = skge_id_table,
3468 .probe = skge_probe,
3469 .remove = __devexit_p(skge_remove),
3470#ifdef CONFIG_PM
3471 .suspend = skge_suspend,
3472 .resume = skge_resume,
3473#endif
3474};
3475
3476static int __init skge_init_module(void)
3477{
3478 return pci_module_init(&skge_driver);
3479}
3480
3481static void __exit skge_cleanup_module(void)
3482{
3483 pci_unregister_driver(&skge_driver);
3484}
3485
3486module_init(skge_init_module);
3487module_exit(skge_cleanup_module);
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