]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/skge.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge master.kernel.org:/pub/scm/linux/kernel/git/herbert/crypto-2.6
[net-next-2.6.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/config.h>
14c85021 28#include <linux/in.h>
baef58b1
SH		 29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/if_vlan.h>
37#include <linux/ip.h>
38#include <linux/delay.h>
39#include <linux/crc32.h>
4075400b 40#include <linux/dma-mapping.h>
2cd8e5d3 41#include <linux/mii.h>
baef58b1
SH		 42#include <asm/irq.h>
43
44#include "skge.h"
45
46#define DRV_NAME "skge"
f15943f5 47#define DRV_VERSION "1.3"
baef58b1
SH		 48#define PFX DRV_NAME " "
49
50#define DEFAULT_TX_RING_SIZE 128
51#define DEFAULT_RX_RING_SIZE 512
52#define MAX_TX_RING_SIZE 1024
53#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 54#define RX_COPY_THRESHOLD 128
55#define RX_BUF_SIZE 1536
baef58b1
SH		 56#define PHY_RETRIES 1000
57#define ETH_JUMBO_MTU 9000
58#define TX_WATCHDOG (5 * HZ)
59#define NAPI_WEIGHT 64
6abebb53 60#define BLINK_MS 250
baef58b1
SH		 61
62MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
64MODULE_LICENSE("GPL");
65MODULE_VERSION(DRV_VERSION);
66
67static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71static int debug = -1; /* defaults above */
72module_param(debug, int, 0);
73MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
275834d1
SH		 80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
81 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
83 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 84 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86f0cd50 85 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
baef58b1
SH		 86 { 0 }
87};
88MODULE_DEVICE_TABLE(pci, skge_id_table);
89
90static int skge_up(struct net_device *dev);
91static int skge_down(struct net_device *dev);
ee294dcd 92static void skge_phy_reset(struct skge_port *skge);
baef58b1 93static void skge_tx_clean(struct skge_port *skge);
2cd8e5d3
SH		 94static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
95static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 96static void genesis_get_stats(struct skge_port *skge, u64 *data);
97static void yukon_get_stats(struct skge_port *skge, u64 *data);
98static void yukon_init(struct skge_hw *hw, int port);
baef58b1 99static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 100static void genesis_link_up(struct skge_port *skge);
baef58b1 101
7e676d91 102/* Avoid conditionals by using array */
baef58b1
SH		 103static const int txqaddr[] = { Q_XA1, Q_XA2 };
104static const int rxqaddr[] = { Q_R1, Q_R2 };
105static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
106static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
7e676d91 107static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1 108
baef58b1
SH		 109static int skge_get_regs_len(struct net_device *dev)
110{
c3f8be96 111 return 0x4000;
baef58b1
SH		 112}
113
114/*
c3f8be96
SH		 115 * Returns copy of whole control register region
116 * Note: skip RAM address register because accessing it will
117 * cause bus hangs!
baef58b1
SH		 118 */
119static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
120 void *p)
121{
122 const struct skge_port *skge = netdev_priv(dev);
baef58b1 123 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 124
125 regs->version = 1;
c3f8be96
SH		 126 memset(p, 0, regs->len);
127 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 128
c3f8be96
SH		 129 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
130 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 131}
132
8f3f8193 133/* Wake on Lan only supported on Yukon chips with rev 1 or above */
baef58b1
SH		 134static int wol_supported(const struct skge_hw *hw)
135{
136 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 137 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 138}
139
140static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
141{
142 struct skge_port *skge = netdev_priv(dev);
143
144 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
145 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
146}
147
148static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
149{
150 struct skge_port *skge = netdev_priv(dev);
151 struct skge_hw *hw = skge->hw;
152
95566065 153 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 154 return -EOPNOTSUPP;
155
156 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
157 return -EOPNOTSUPP;
158
159 skge->wol = wol->wolopts == WAKE_MAGIC;
160
161 if (skge->wol) {
162 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
163
164 skge_write16(hw, WOL_CTRL_STAT,
165 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
166 WOL_CTL_ENA_MAGIC_PKT_UNIT);
167 } else
168 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
169
170 return 0;
171}
172
8f3f8193
SH		 173/* Determine supported/advertised modes based on hardware.
174 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 175 */
176static u32 skge_supported_modes(const struct skge_hw *hw)
177{
178 u32 supported;
179
5e1705dd 180 if (hw->copper) {
31b619c5
SH		 181 supported = SUPPORTED_10baseT_Half
182 | SUPPORTED_10baseT_Full
183 | SUPPORTED_100baseT_Half
184 | SUPPORTED_100baseT_Full
185 | SUPPORTED_1000baseT_Half
186 | SUPPORTED_1000baseT_Full
187 | SUPPORTED_Autoneg| SUPPORTED_TP;
188
189 if (hw->chip_id == CHIP_ID_GENESIS)
190 supported &= ~(SUPPORTED_10baseT_Half
191 | SUPPORTED_10baseT_Full
192 | SUPPORTED_100baseT_Half
193 | SUPPORTED_100baseT_Full);
194
195 else if (hw->chip_id == CHIP_ID_YUKON)
196 supported &= ~SUPPORTED_1000baseT_Half;
197 } else
198 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
199 | SUPPORTED_Autoneg;
200
201 return supported;
202}
baef58b1
SH		 203
204static int skge_get_settings(struct net_device *dev,
205 struct ethtool_cmd *ecmd)
206{
207 struct skge_port *skge = netdev_priv(dev);
208 struct skge_hw *hw = skge->hw;
209
210 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 211 ecmd->supported = skge_supported_modes(hw);
baef58b1 212
5e1705dd 213 if (hw->copper) {
baef58b1
SH		 214 ecmd->port = PORT_TP;
215 ecmd->phy_address = hw->phy_addr;
31b619c5 216 } else
baef58b1 217 ecmd->port = PORT_FIBRE;
baef58b1
SH		 218
219 ecmd->advertising = skge->advertising;
220 ecmd->autoneg = skge->autoneg;
221 ecmd->speed = skge->speed;
222 ecmd->duplex = skge->duplex;
223 return 0;
224}
225
baef58b1
SH		 226static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
227{
228 struct skge_port *skge = netdev_priv(dev);
229 const struct skge_hw *hw = skge->hw;
31b619c5 230 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 231
232 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 233 ecmd->advertising = supported;
234 skge->duplex = -1;
235 skge->speed = -1;
baef58b1 236 } else {
31b619c5
SH		 237 u32 setting;
238
2c668514 239 switch (ecmd->speed) {
baef58b1 240 case SPEED_1000:
31b619c5
SH		 241 if (ecmd->duplex == DUPLEX_FULL)
242 setting = SUPPORTED_1000baseT_Full;
243 else if (ecmd->duplex == DUPLEX_HALF)
244 setting = SUPPORTED_1000baseT_Half;
245 else
246 return -EINVAL;
baef58b1
SH		 247 break;
248 case SPEED_100:
31b619c5
SH		 249 if (ecmd->duplex == DUPLEX_FULL)
250 setting = SUPPORTED_100baseT_Full;
251 else if (ecmd->duplex == DUPLEX_HALF)
252 setting = SUPPORTED_100baseT_Half;
253 else
254 return -EINVAL;
255 break;
256
baef58b1 257 case SPEED_10:
31b619c5
SH		 258 if (ecmd->duplex == DUPLEX_FULL)
259 setting = SUPPORTED_10baseT_Full;
260 else if (ecmd->duplex == DUPLEX_HALF)
261 setting = SUPPORTED_10baseT_Half;
262 else
baef58b1
SH		 263 return -EINVAL;
264 break;
265 default:
266 return -EINVAL;
267 }
31b619c5
SH		 268
269 if ((setting & supported) == 0)
270 return -EINVAL;
271
272 skge->speed = ecmd->speed;
273 skge->duplex = ecmd->duplex;
baef58b1
SH		 274 }
275
276 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 277 skge->advertising = ecmd->advertising;
278
ee294dcd
SH		 279 if (netif_running(dev))
280 skge_phy_reset(skge);
281
baef58b1
SH		 282 return (0);
283}
284
285static void skge_get_drvinfo(struct net_device *dev,
286 struct ethtool_drvinfo *info)
287{
288 struct skge_port *skge = netdev_priv(dev);
289
290 strcpy(info->driver, DRV_NAME);
291 strcpy(info->version, DRV_VERSION);
292 strcpy(info->fw_version, "N/A");
293 strcpy(info->bus_info, pci_name(skge->hw->pdev));
294}
295
296static const struct skge_stat {
297 char name[ETH_GSTRING_LEN];
298 u16 xmac_offset;
299 u16 gma_offset;
300} skge_stats[] = {
301 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
302 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
303
304 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
305 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
306 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
307 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
308 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
309 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
310 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
311 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
312
313 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
314 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
315 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
316 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
317 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
318 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
319
320 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
321 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
322 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
323 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
324 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
325};
326
327static int skge_get_stats_count(struct net_device *dev)
328{
329 return ARRAY_SIZE(skge_stats);
330}
331
332static void skge_get_ethtool_stats(struct net_device *dev,
333 struct ethtool_stats *stats, u64 *data)
334{
335 struct skge_port *skge = netdev_priv(dev);
336
337 if (skge->hw->chip_id == CHIP_ID_GENESIS)
338 genesis_get_stats(skge, data);
339 else
340 yukon_get_stats(skge, data);
341}
342
343/* Use hardware MIB variables for critical path statistics and
344 * transmit feedback not reported at interrupt.
345 * Other errors are accounted for in interrupt handler.
346 */
347static struct net_device_stats *skge_get_stats(struct net_device *dev)
348{
349 struct skge_port *skge = netdev_priv(dev);
350 u64 data[ARRAY_SIZE(skge_stats)];
351
352 if (skge->hw->chip_id == CHIP_ID_GENESIS)
353 genesis_get_stats(skge, data);
354 else
355 yukon_get_stats(skge, data);
356
357 skge->net_stats.tx_bytes = data[0];
358 skge->net_stats.rx_bytes = data[1];
359 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
360 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
361 skge->net_stats.multicast = data[5] + data[7];
362 skge->net_stats.collisions = data[10];
363 skge->net_stats.tx_aborted_errors = data[12];
364
365 return &skge->net_stats;
366}
367
368static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
369{
370 int i;
371
95566065 372 switch (stringset) {
baef58b1
SH		 373 case ETH_SS_STATS:
374 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
375 memcpy(data + i * ETH_GSTRING_LEN,
376 skge_stats[i].name, ETH_GSTRING_LEN);
377 break;
378 }
379}
380
381static void skge_get_ring_param(struct net_device *dev,
382 struct ethtool_ringparam *p)
383{
384 struct skge_port *skge = netdev_priv(dev);
385
386 p->rx_max_pending = MAX_RX_RING_SIZE;
387 p->tx_max_pending = MAX_TX_RING_SIZE;
388 p->rx_mini_max_pending = 0;
389 p->rx_jumbo_max_pending = 0;
390
391 p->rx_pending = skge->rx_ring.count;
392 p->tx_pending = skge->tx_ring.count;
393 p->rx_mini_pending = 0;
394 p->rx_jumbo_pending = 0;
395}
396
397static int skge_set_ring_param(struct net_device *dev,
398 struct ethtool_ringparam *p)
399{
400 struct skge_port *skge = netdev_priv(dev);
3b8bb472 401 int err;
baef58b1
SH		 402
403 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
404 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
405 return -EINVAL;
406
407 skge->rx_ring.count = p->rx_pending;
408 skge->tx_ring.count = p->tx_pending;
409
410 if (netif_running(dev)) {
411 skge_down(dev);
3b8bb472
SH		 412 err = skge_up(dev);
413 if (err)
414 dev_close(dev);
baef58b1
SH		 415 }
416
417 return 0;
418}
419
420static u32 skge_get_msglevel(struct net_device *netdev)
421{
422 struct skge_port *skge = netdev_priv(netdev);
423 return skge->msg_enable;
424}
425
426static void skge_set_msglevel(struct net_device *netdev, u32 value)
427{
428 struct skge_port *skge = netdev_priv(netdev);
429 skge->msg_enable = value;
430}
431
432static int skge_nway_reset(struct net_device *dev)
433{
434 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 435
436 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
437 return -EINVAL;
438
ee294dcd 439 skge_phy_reset(skge);
baef58b1
SH		 440 return 0;
441}
442
443static int skge_set_sg(struct net_device *dev, u32 data)
444{
445 struct skge_port *skge = netdev_priv(dev);
446 struct skge_hw *hw = skge->hw;
447
448 if (hw->chip_id == CHIP_ID_GENESIS && data)
449 return -EOPNOTSUPP;
450 return ethtool_op_set_sg(dev, data);
451}
452
453static int skge_set_tx_csum(struct net_device *dev, u32 data)
454{
455 struct skge_port *skge = netdev_priv(dev);
456 struct skge_hw *hw = skge->hw;
457
458 if (hw->chip_id == CHIP_ID_GENESIS && data)
459 return -EOPNOTSUPP;
460
461 return ethtool_op_set_tx_csum(dev, data);
462}
463
464static u32 skge_get_rx_csum(struct net_device *dev)
465{
466 struct skge_port *skge = netdev_priv(dev);
467
468 return skge->rx_csum;
469}
470
471/* Only Yukon supports checksum offload. */
472static int skge_set_rx_csum(struct net_device *dev, u32 data)
473{
474 struct skge_port *skge = netdev_priv(dev);
475
476 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
477 return -EOPNOTSUPP;
478
479 skge->rx_csum = data;
480 return 0;
481}
482
baef58b1
SH		 483static void skge_get_pauseparam(struct net_device *dev,
484 struct ethtool_pauseparam *ecmd)
485{
486 struct skge_port *skge = netdev_priv(dev);
487
488 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
489 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
490 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
491 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
492
493 ecmd->autoneg = skge->autoneg;
494}
495
496static int skge_set_pauseparam(struct net_device *dev,
497 struct ethtool_pauseparam *ecmd)
498{
499 struct skge_port *skge = netdev_priv(dev);
500
501 skge->autoneg = ecmd->autoneg;
502 if (ecmd->rx_pause && ecmd->tx_pause)
503 skge->flow_control = FLOW_MODE_SYMMETRIC;
95566065 504 else if (ecmd->rx_pause && !ecmd->tx_pause)
baef58b1 505 skge->flow_control = FLOW_MODE_REM_SEND;
95566065 506 else if (!ecmd->rx_pause && ecmd->tx_pause)
baef58b1
SH		 507 skge->flow_control = FLOW_MODE_LOC_SEND;
508 else
509 skge->flow_control = FLOW_MODE_NONE;
510
e8df8554
SH		 511 if (netif_running(dev))
512 skge_phy_reset(skge);
baef58b1
SH		 513 return 0;
514}
515
516/* Chip internal frequency for clock calculations */
517static inline u32 hwkhz(const struct skge_hw *hw)
518{
519 if (hw->chip_id == CHIP_ID_GENESIS)
520 return 53215; /* or: 53.125 MHz */
baef58b1
SH		 521 else
522 return 78215; /* or: 78.125 MHz */
523}
524
8f3f8193 525/* Chip HZ to microseconds */
baef58b1
SH		 526static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
527{
528 return (ticks * 1000) / hwkhz(hw);
529}
530
8f3f8193 531/* Microseconds to chip HZ */
baef58b1
SH		 532static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
533{
534 return hwkhz(hw) * usec / 1000;
535}
536
537static int skge_get_coalesce(struct net_device *dev,
538 struct ethtool_coalesce *ecmd)
539{
540 struct skge_port *skge = netdev_priv(dev);
541 struct skge_hw *hw = skge->hw;
542 int port = skge->port;
543
544 ecmd->rx_coalesce_usecs = 0;
545 ecmd->tx_coalesce_usecs = 0;
546
547 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
548 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
549 u32 msk = skge_read32(hw, B2_IRQM_MSK);
550
551 if (msk & rxirqmask[port])
552 ecmd->rx_coalesce_usecs = delay;
553 if (msk & txirqmask[port])
554 ecmd->tx_coalesce_usecs = delay;
555 }
556
557 return 0;
558}
559
560/* Note: interrupt timer is per board, but can turn on/off per port */
561static int skge_set_coalesce(struct net_device *dev,
562 struct ethtool_coalesce *ecmd)
563{
564 struct skge_port *skge = netdev_priv(dev);
565 struct skge_hw *hw = skge->hw;
566 int port = skge->port;
567 u32 msk = skge_read32(hw, B2_IRQM_MSK);
568 u32 delay = 25;
569
570 if (ecmd->rx_coalesce_usecs == 0)
571 msk &= ~rxirqmask[port];
572 else if (ecmd->rx_coalesce_usecs < 25 ||
573 ecmd->rx_coalesce_usecs > 33333)
574 return -EINVAL;
575 else {
576 msk |= rxirqmask[port];
577 delay = ecmd->rx_coalesce_usecs;
578 }
579
580 if (ecmd->tx_coalesce_usecs == 0)
581 msk &= ~txirqmask[port];
582 else if (ecmd->tx_coalesce_usecs < 25 ||
583 ecmd->tx_coalesce_usecs > 33333)
584 return -EINVAL;
585 else {
586 msk |= txirqmask[port];
587 delay = min(delay, ecmd->rx_coalesce_usecs);
588 }
589
590 skge_write32(hw, B2_IRQM_MSK, msk);
591 if (msk == 0)
592 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
593 else {
594 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
595 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
596 }
597 return 0;
598}
599
6abebb53
SH		 600enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
601static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 602{
6abebb53
SH		 603 struct skge_hw *hw = skge->hw;
604 int port = skge->port;
605
606 spin_lock_bh(&hw->phy_lock);
baef58b1 607 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 608 switch (mode) {
609 case LED_MODE_OFF:
610 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
611 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
612 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
613 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
614 break;
baef58b1 615
6abebb53
SH		 616 case LED_MODE_ON:
617 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
618 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 619
6abebb53
SH		 620 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
621 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 622
6abebb53 623 break;
baef58b1 624
6abebb53
SH		 625 case LED_MODE_TST:
626 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
627 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
628 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 629
6abebb53
SH		 630 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
631 break;
632 }
baef58b1 633 } else {
6abebb53
SH		 634 switch (mode) {
635 case LED_MODE_OFF:
636 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
637 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
638 PHY_M_LED_MO_DUP(MO_LED_OFF) |
639 PHY_M_LED_MO_10(MO_LED_OFF) |
640 PHY_M_LED_MO_100(MO_LED_OFF) |
641 PHY_M_LED_MO_1000(MO_LED_OFF) |
642 PHY_M_LED_MO_RX(MO_LED_OFF));
643 break;
644 case LED_MODE_ON:
645 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
646 PHY_M_LED_PULS_DUR(PULS_170MS) |
647 PHY_M_LED_BLINK_RT(BLINK_84MS) |
648 PHY_M_LEDC_TX_CTRL |
649 PHY_M_LEDC_DP_CTRL);
46a60f2d 650
6abebb53
SH		 651 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
652 PHY_M_LED_MO_RX(MO_LED_OFF) |
653 (skge->speed == SPEED_100 ?
654 PHY_M_LED_MO_100(MO_LED_ON) : 0));
655 break;
656 case LED_MODE_TST:
657 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
658 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
659 PHY_M_LED_MO_DUP(MO_LED_ON) |
660 PHY_M_LED_MO_10(MO_LED_ON) |
661 PHY_M_LED_MO_100(MO_LED_ON) |
662 PHY_M_LED_MO_1000(MO_LED_ON) |
663 PHY_M_LED_MO_RX(MO_LED_ON));
664 }
baef58b1 665 }
4ff6ac05 666 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 667}
668
669/* blink LED's for finding board */
670static int skge_phys_id(struct net_device *dev, u32 data)
671{
672 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 673 unsigned long ms;
674 enum led_mode mode = LED_MODE_TST;
baef58b1 675
95566065 676 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 677 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
678 else
679 ms = data * 1000;
baef58b1 680
6abebb53
SH		 681 while (ms > 0) {
682 skge_led(skge, mode);
683 mode ^= LED_MODE_TST;
baef58b1 684
6abebb53
SH		 685 if (msleep_interruptible(BLINK_MS))
686 break;
687 ms -= BLINK_MS;
688 }
baef58b1 689
6abebb53
SH		 690 /* back to regular LED state */
691 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 692
693 return 0;
694}
695
696static struct ethtool_ops skge_ethtool_ops = {
697 .get_settings = skge_get_settings,
698 .set_settings = skge_set_settings,
699 .get_drvinfo = skge_get_drvinfo,
700 .get_regs_len = skge_get_regs_len,
701 .get_regs = skge_get_regs,
702 .get_wol = skge_get_wol,
703 .set_wol = skge_set_wol,
704 .get_msglevel = skge_get_msglevel,
705 .set_msglevel = skge_set_msglevel,
706 .nway_reset = skge_nway_reset,
707 .get_link = ethtool_op_get_link,
708 .get_ringparam = skge_get_ring_param,
709 .set_ringparam = skge_set_ring_param,
710 .get_pauseparam = skge_get_pauseparam,
711 .set_pauseparam = skge_set_pauseparam,
712 .get_coalesce = skge_get_coalesce,
713 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 714 .get_sg = ethtool_op_get_sg,
715 .set_sg = skge_set_sg,
716 .get_tx_csum = ethtool_op_get_tx_csum,
717 .set_tx_csum = skge_set_tx_csum,
718 .get_rx_csum = skge_get_rx_csum,
719 .set_rx_csum = skge_set_rx_csum,
720 .get_strings = skge_get_strings,
721 .phys_id = skge_phys_id,
722 .get_stats_count = skge_get_stats_count,
723 .get_ethtool_stats = skge_get_ethtool_stats,
56230d53 724 .get_perm_addr = ethtool_op_get_perm_addr,
baef58b1
SH		 725};
726
727/*
728 * Allocate ring elements and chain them together
729 * One-to-one association of board descriptors with ring elements
730 */
731static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
732{
733 struct skge_tx_desc *d;
734 struct skge_element *e;
735 int i;
736
737 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
738 if (!ring->start)
739 return -ENOMEM;
740
741 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
742 e->desc = d;
19a33d4e 743 e->skb = NULL;
baef58b1
SH		 744 if (i == ring->count - 1) {
745 e->next = ring->start;
746 d->next_offset = base;
747 } else {
748 e->next = e + 1;
749 d->next_offset = base + (i+1) * sizeof(*d);
750 }
751 }
752 ring->to_use = ring->to_clean = ring->start;
753
754 return 0;
755}
756
19a33d4e
SH		 757/* Allocate and setup a new buffer for receiving */
758static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
759 struct sk_buff *skb, unsigned int bufsize)
760{
761 struct skge_rx_desc *rd = e->desc;
762 u64 map;
baef58b1
SH		 763
764 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
765 PCI_DMA_FROMDEVICE);
766
767 rd->dma_lo = map;
768 rd->dma_hi = map >> 32;
769 e->skb = skb;
770 rd->csum1_start = ETH_HLEN;
771 rd->csum2_start = ETH_HLEN;
772 rd->csum1 = 0;
773 rd->csum2 = 0;
774
775 wmb();
776
777 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
778 pci_unmap_addr_set(e, mapaddr, map);
779 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 780}
781
19a33d4e
SH		 782/* Resume receiving using existing skb,
783 * Note: DMA address is not changed by chip.
784 * MTU not changed while receiver active.
785 */
786static void skge_rx_reuse(struct skge_element *e, unsigned int size)
787{
788 struct skge_rx_desc *rd = e->desc;
789
790 rd->csum2 = 0;
791 rd->csum2_start = ETH_HLEN;
792
793 wmb();
794
795 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
796}
797
798
799/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 800static void skge_rx_clean(struct skge_port *skge)
801{
802 struct skge_hw *hw = skge->hw;
803 struct skge_ring *ring = &skge->rx_ring;
804 struct skge_element *e;
805
19a33d4e
SH		 806 e = ring->start;
807 do {
baef58b1
SH		 808 struct skge_rx_desc *rd = e->desc;
809 rd->control = 0;
19a33d4e
SH		 810 if (e->skb) {
811 pci_unmap_single(hw->pdev,
812 pci_unmap_addr(e, mapaddr),
813 pci_unmap_len(e, maplen),
814 PCI_DMA_FROMDEVICE);
815 dev_kfree_skb(e->skb);
816 e->skb = NULL;
817 }
818 } while ((e = e->next) != ring->start);
baef58b1
SH		 819}
820
19a33d4e 821
baef58b1 822/* Allocate buffers for receive ring
19a33d4e 823 * For receive: to_clean is next received frame.
baef58b1
SH		 824 */
825static int skge_rx_fill(struct skge_port *skge)
826{
827 struct skge_ring *ring = &skge->rx_ring;
828 struct skge_element *e;
baef58b1 829
19a33d4e
SH		 830 e = ring->start;
831 do {
383181ac 832 struct sk_buff *skb;
baef58b1 833
383181ac 834 skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
19a33d4e
SH		 835 if (!skb)
836 return -ENOMEM;
837
383181ac
SH		 838 skb_reserve(skb, NET_IP_ALIGN);
839 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
19a33d4e 840 } while ( (e = e->next) != ring->start);
baef58b1 841
19a33d4e
SH		 842 ring->to_clean = ring->start;
843 return 0;
baef58b1
SH		 844}
845
846static void skge_link_up(struct skge_port *skge)
847{
46a60f2d 848 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 849 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
850
baef58b1
SH		 851 netif_carrier_on(skge->netdev);
852 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
853 netif_wake_queue(skge->netdev);
854
855 if (netif_msg_link(skge))
856 printk(KERN_INFO PFX
857 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
858 skge->netdev->name, skge->speed,
859 skge->duplex == DUPLEX_FULL ? "full" : "half",
860 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
861 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
862 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
863 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
864 "unknown");
865}
866
867static void skge_link_down(struct skge_port *skge)
868{
54cfb5aa 869 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 870 netif_carrier_off(skge->netdev);
871 netif_stop_queue(skge->netdev);
872
873 if (netif_msg_link(skge))
874 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
875}
876
2cd8e5d3 877static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 878{
879 int i;
baef58b1 880
6b0c1480 881 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 882 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 883
89bf5f23 884 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 885 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 886 goto ready;
0781191c 887 udelay(1);
baef58b1
SH		 888 }
889
2cd8e5d3 890 return -ETIMEDOUT;
89bf5f23 891 ready:
2cd8e5d3 892 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 893
2cd8e5d3
SH		 894 return 0;
895}
896
897static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
898{
899 u16 v = 0;
900 if (__xm_phy_read(hw, port, reg, &v))
901 printk(KERN_WARNING PFX "%s: phy read timed out\n",
902 hw->dev[port]->name);
baef58b1
SH		 903 return v;
904}
905
2cd8e5d3 906static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 907{
908 int i;
909
6b0c1480 910 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 911 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 912 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 913 goto ready;
89bf5f23 914 udelay(1);
baef58b1 915 }
2cd8e5d3 916 return -EIO;
baef58b1
SH		 917
918 ready:
6b0c1480 919 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 920 for (i = 0; i < PHY_RETRIES; i++) {
921 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
922 return 0;
923 udelay(1);
924 }
925 return -ETIMEDOUT;
baef58b1
SH		 926}
927
928static void genesis_init(struct skge_hw *hw)
929{
930 /* set blink source counter */
931 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
932 skge_write8(hw, B2_BSC_CTRL, BSC_START);
933
934 /* configure mac arbiter */
935 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
936
937 /* configure mac arbiter timeout values */
938 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
939 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
940 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
941 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
942
943 skge_write8(hw, B3_MA_RCINI_RX1, 0);
944 skge_write8(hw, B3_MA_RCINI_RX2, 0);
945 skge_write8(hw, B3_MA_RCINI_TX1, 0);
946 skge_write8(hw, B3_MA_RCINI_TX2, 0);
947
948 /* configure packet arbiter timeout */
949 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
950 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
951 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
952 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
953 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
954}
955
956static void genesis_reset(struct skge_hw *hw, int port)
957{
45bada65 958 const u8 zero[8] = { 0 };
baef58b1 959
46a60f2d
SH		 960 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
961
baef58b1 962 /* reset the statistics module */
6b0c1480
SH		 963 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
964 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
965 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
966 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
967 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 968
89bf5f23
SH		 969 /* disable Broadcom PHY IRQ */
970 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 971
45bada65 972 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 973}
974
975
45bada65
SH		 976/* Convert mode to MII values */
977static const u16 phy_pause_map[] = {
978 [FLOW_MODE_NONE] = 0,
979 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
980 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
981 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
982};
983
984
985/* Check status of Broadcom phy link */
986static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 987{
45bada65
SH		 988 struct net_device *dev = hw->dev[port];
989 struct skge_port *skge = netdev_priv(dev);
990 u16 status;
991
992 /* read twice because of latch */
993 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
994 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
995
45bada65
SH		 996 if ((status & PHY_ST_LSYNC) == 0) {
997 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
998 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
999 xm_write16(hw, port, XM_MMU_CMD, cmd);
1000 /* dummy read to ensure writing */
1001 (void) xm_read16(hw, port, XM_MMU_CMD);
1002
1003 if (netif_carrier_ok(dev))
1004 skge_link_down(skge);
1005 } else {
1006 if (skge->autoneg == AUTONEG_ENABLE &&
1007 (status & PHY_ST_AN_OVER)) {
1008 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1009 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1010
1011 if (lpa & PHY_B_AN_RF) {
1012 printk(KERN_NOTICE PFX "%s: remote fault\n",
1013 dev->name);
1014 return;
1015 }
1016
1017 /* Check Duplex mismatch */
2c668514 1018 switch (aux & PHY_B_AS_AN_RES_MSK) {
45bada65
SH		 1019 case PHY_B_RES_1000FD:
1020 skge->duplex = DUPLEX_FULL;
1021 break;
1022 case PHY_B_RES_1000HD:
1023 skge->duplex = DUPLEX_HALF;
1024 break;
1025 default:
1026 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1027 dev->name);
1028 return;
1029 }
1030
1031
1032 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1033 switch (aux & PHY_B_AS_PAUSE_MSK) {
1034 case PHY_B_AS_PAUSE_MSK:
1035 skge->flow_control = FLOW_MODE_SYMMETRIC;
1036 break;
1037 case PHY_B_AS_PRR:
1038 skge->flow_control = FLOW_MODE_REM_SEND;
1039 break;
1040 case PHY_B_AS_PRT:
1041 skge->flow_control = FLOW_MODE_LOC_SEND;
1042 break;
1043 default:
1044 skge->flow_control = FLOW_MODE_NONE;
1045 }
1046
1047 skge->speed = SPEED_1000;
1048 }
1049
1050 if (!netif_carrier_ok(dev))
1051 genesis_link_up(skge);
1052 }
1053}
1054
1055/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1056 * Phy on for 100 or 10Mbit operation
1057 */
1058static void bcom_phy_init(struct skge_port *skge, int jumbo)
1059{
1060 struct skge_hw *hw = skge->hw;
1061 int port = skge->port;
baef58b1 1062 int i;
45bada65 1063 u16 id1, r, ext, ctl;
baef58b1
SH		 1064
1065 /* magic workaround patterns for Broadcom */
1066 static const struct {
1067 u16 reg;
1068 u16 val;
1069 } A1hack[] = {
1070 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1071 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1072 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1073 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1074 }, C0hack[] = {
1075 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1076 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1077 };
1078
45bada65
SH		 1079 /* read Id from external PHY (all have the same address) */
1080 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1081
1082 /* Optimize MDIO transfer by suppressing preamble. */
1083 r = xm_read16(hw, port, XM_MMU_CMD);
1084 r |= XM_MMU_NO_PRE;
1085 xm_write16(hw, port, XM_MMU_CMD,r);
1086
2c668514 1087 switch (id1) {
45bada65
SH		 1088 case PHY_BCOM_ID1_C0:
1089 /*
1090 * Workaround BCOM Errata for the C0 type.
1091 * Write magic patterns to reserved registers.
1092 */
1093 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1094 xm_phy_write(hw, port,
1095 C0hack[i].reg, C0hack[i].val);
1096
1097 break;
1098 case PHY_BCOM_ID1_A1:
1099 /*
1100 * Workaround BCOM Errata for the A1 type.
1101 * Write magic patterns to reserved registers.
1102 */
1103 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1104 xm_phy_write(hw, port,
1105 A1hack[i].reg, A1hack[i].val);
1106 break;
1107 }
1108
1109 /*
1110 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1111 * Disable Power Management after reset.
1112 */
1113 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1114 r |= PHY_B_AC_DIS_PM;
1115 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1116
1117 /* Dummy read */
1118 xm_read16(hw, port, XM_ISRC);
1119
1120 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1121 ctl = PHY_CT_SP1000; /* always 1000mbit */
1122
1123 if (skge->autoneg == AUTONEG_ENABLE) {
1124 /*
1125 * Workaround BCOM Errata #1 for the C5 type.
1126 * 1000Base-T Link Acquisition Failure in Slave Mode
1127 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1128 */
1129 u16 adv = PHY_B_1000C_RD;
1130 if (skge->advertising & ADVERTISED_1000baseT_Half)
1131 adv |= PHY_B_1000C_AHD;
1132 if (skge->advertising & ADVERTISED_1000baseT_Full)
1133 adv |= PHY_B_1000C_AFD;
1134 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1135
1136 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1137 } else {
1138 if (skge->duplex == DUPLEX_FULL)
1139 ctl |= PHY_CT_DUP_MD;
1140 /* Force to slave */
1141 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1142 }
1143
1144 /* Set autonegotiation pause parameters */
1145 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1146 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1147
1148 /* Handle Jumbo frames */
1149 if (jumbo) {
1150 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1151 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1152
1153 ext |= PHY_B_PEC_HIGH_LA;
1154
1155 }
1156
1157 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1158 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1159
8f3f8193 1160 /* Use link status change interrupt */
45bada65
SH		 1161 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1162
1163 bcom_check_link(hw, port);
1164}
1165
1166static void genesis_mac_init(struct skge_hw *hw, int port)
1167{
1168 struct net_device *dev = hw->dev[port];
1169 struct skge_port *skge = netdev_priv(dev);
1170 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1171 int i;
1172 u32 r;
1173 const u8 zero[6] = { 0 };
1174
0781191c
SH		 1175 for (i = 0; i < 10; i++) {
1176 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1177 MFF_SET_MAC_RST);
1178 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1179 goto reset_ok;
1180 udelay(1);
1181 }
baef58b1 1182
0781191c
SH		 1183 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1184
1185 reset_ok:
baef58b1 1186 /* Unreset the XMAC. */
6b0c1480 1187 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1188
1189 /*
1190 * Perform additional initialization for external PHYs,
1191 * namely for the 1000baseTX cards that use the XMAC's
1192 * GMII mode.
1193 */
45bada65 1194 /* Take external Phy out of reset */
89bf5f23
SH		 1195 r = skge_read32(hw, B2_GP_IO);
1196 if (port == 0)
1197 r |= GP_DIR_0|GP_IO_0;
1198 else
1199 r |= GP_DIR_2|GP_IO_2;
1200
1201 skge_write32(hw, B2_GP_IO, r);
0781191c 1202
89bf5f23 1203
8f3f8193 1204 /* Enable GMII interface */
89bf5f23
SH		 1205 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1206
45bada65 1207 bcom_phy_init(skge, jumbo);
89bf5f23 1208
45bada65
SH		 1209 /* Set Station Address */
1210 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1211
45bada65
SH		 1212 /* We don't use match addresses so clear */
1213 for (i = 1; i < 16; i++)
1214 xm_outaddr(hw, port, XM_EXM(i), zero);
1215
0781191c
SH		 1216 /* Clear MIB counters */
1217 xm_write16(hw, port, XM_STAT_CMD,
1218 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1219 /* Clear two times according to Errata #3 */
1220 xm_write16(hw, port, XM_STAT_CMD,
1221 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1222
45bada65
SH		 1223 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1224 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1225
1226 /* We don't need the FCS appended to the packet. */
1227 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1228 if (jumbo)
1229 r |= XM_RX_BIG_PK_OK;
89bf5f23 1230
45bada65 1231 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1232 /*
45bada65
SH		 1233 * If in manual half duplex mode the other side might be in
1234 * full duplex mode, so ignore if a carrier extension is not seen
1235 * on frames received
89bf5f23 1236 */
45bada65 1237 r |= XM_RX_DIS_CEXT;
baef58b1 1238 }
45bada65 1239 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1240
baef58b1
SH		 1241
1242 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1243 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1244
1245 /*
1246 * Bump up the transmit threshold. This helps hold off transmit
1247 * underruns when we're blasting traffic from both ports at once.
1248 */
1249 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1250
1251 /*
1252 * Enable the reception of all error frames. This is is
1253 * a necessary evil due to the design of the XMAC. The
1254 * XMAC's receive FIFO is only 8K in size, however jumbo
1255 * frames can be up to 9000 bytes in length. When bad
1256 * frame filtering is enabled, the XMAC's RX FIFO operates
1257 * in 'store and forward' mode. For this to work, the
1258 * entire frame has to fit into the FIFO, but that means
1259 * that jumbo frames larger than 8192 bytes will be
1260 * truncated. Disabling all bad frame filtering causes
1261 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1262 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1263 * RX FIFO as soon as the FIFO threshold is reached.
1264 */
45bada65 1265 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1266
baef58b1
SH		 1267
1268 /*
45bada65
SH		 1269 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1270 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1271 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1272 */
45bada65
SH		 1273 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1274
1275 /*
1276 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1277 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1278 * and 'Octets Tx OK Hi Cnt Ov'.
1279 */
1280 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1281
1282 /* Configure MAC arbiter */
1283 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1284
1285 /* configure timeout values */
1286 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1287 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1288 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1289 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1290
1291 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1292 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1293 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1294 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1295
1296 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1297 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1298 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1299 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1300
1301 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1302 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1303 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1304 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1305
45bada65 1306 if (jumbo) {
baef58b1 1307 /* Enable frame flushing if jumbo frames used */
6b0c1480 1308 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1309 } else {
1310 /* enable timeout timers if normal frames */
1311 skge_write16(hw, B3_PA_CTRL,
45bada65 1312 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1313 }
baef58b1
SH		 1314}
1315
1316static void genesis_stop(struct skge_port *skge)
1317{
1318 struct skge_hw *hw = skge->hw;
1319 int port = skge->port;
89bf5f23 1320 u32 reg;
baef58b1 1321
46a60f2d
SH		 1322 genesis_reset(hw, port);
1323
baef58b1
SH		 1324 /* Clear Tx packet arbiter timeout IRQ */
1325 skge_write16(hw, B3_PA_CTRL,
1326 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1327
1328 /*
8f3f8193 1329 * If the transfer sticks at the MAC the STOP command will not
baef58b1
SH		 1330 * terminate if we don't flush the XMAC's transmit FIFO !
1331 */
6b0c1480
SH		 1332 xm_write32(hw, port, XM_MODE,
1333 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1334
1335
1336 /* Reset the MAC */
6b0c1480 1337 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1338
1339 /* For external PHYs there must be special handling */
89bf5f23
SH		 1340 reg = skge_read32(hw, B2_GP_IO);
1341 if (port == 0) {
1342 reg |= GP_DIR_0;
1343 reg &= ~GP_IO_0;
1344 } else {
1345 reg |= GP_DIR_2;
1346 reg &= ~GP_IO_2;
baef58b1 1347 }
89bf5f23
SH		 1348 skge_write32(hw, B2_GP_IO, reg);
1349 skge_read32(hw, B2_GP_IO);
baef58b1 1350
6b0c1480
SH		 1351 xm_write16(hw, port, XM_MMU_CMD,
1352 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1353 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1354
6b0c1480 1355 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1356}
1357
1358
1359static void genesis_get_stats(struct skge_port *skge, u64 *data)
1360{
1361 struct skge_hw *hw = skge->hw;
1362 int port = skge->port;
1363 int i;
1364 unsigned long timeout = jiffies + HZ;
1365
6b0c1480 1366 xm_write16(hw, port,
baef58b1
SH		 1367 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1368
1369 /* wait for update to complete */
6b0c1480 1370 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1371 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1372 if (time_after(jiffies, timeout))
1373 break;
1374 udelay(10);
1375 }
1376
1377 /* special case for 64 bit octet counter */
6b0c1480
SH		 1378 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1379 | xm_read32(hw, port, XM_TXO_OK_LO);
1380 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1381 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1382
1383 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1384 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1385}
1386
1387static void genesis_mac_intr(struct skge_hw *hw, int port)
1388{
1389 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1390 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1391
7e676d91
SH		 1392 if (netif_msg_intr(skge))
1393 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1394 skge->netdev->name, status);
baef58b1
SH		 1395
1396 if (status & XM_IS_TXF_UR) {
6b0c1480 1397 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1398 ++skge->net_stats.tx_fifo_errors;
1399 }
1400 if (status & XM_IS_RXF_OV) {
6b0c1480 1401 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1402 ++skge->net_stats.rx_fifo_errors;
1403 }
1404}
1405
baef58b1
SH		 1406static void genesis_link_up(struct skge_port *skge)
1407{
1408 struct skge_hw *hw = skge->hw;
1409 int port = skge->port;
1410 u16 cmd;
1411 u32 mode, msk;
1412
6b0c1480 1413 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1414
1415 /*
1416 * enabling pause frame reception is required for 1000BT
1417 * because the XMAC is not reset if the link is going down
1418 */
1419 if (skge->flow_control == FLOW_MODE_NONE ||
1420 skge->flow_control == FLOW_MODE_LOC_SEND)
7e676d91 1421 /* Disable Pause Frame Reception */
baef58b1
SH		 1422 cmd |= XM_MMU_IGN_PF;
1423 else
1424 /* Enable Pause Frame Reception */
1425 cmd &= ~XM_MMU_IGN_PF;
1426
6b0c1480 1427 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1428
6b0c1480 1429 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 1430 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1431 skge->flow_control == FLOW_MODE_LOC_SEND) {
1432 /*
1433 * Configure Pause Frame Generation
1434 * Use internal and external Pause Frame Generation.
1435 * Sending pause frames is edge triggered.
1436 * Send a Pause frame with the maximum pause time if
1437 * internal oder external FIFO full condition occurs.
1438 * Send a zero pause time frame to re-start transmission.
1439 */
1440 /* XM_PAUSE_DA = '010000C28001' (default) */
1441 /* XM_MAC_PTIME = 0xffff (maximum) */
1442 /* remember this value is defined in big endian (!) */
6b0c1480 1443 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1444
1445 mode |= XM_PAUSE_MODE;
6b0c1480 1446 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1447 } else {
1448 /*
1449 * disable pause frame generation is required for 1000BT
1450 * because the XMAC is not reset if the link is going down
1451 */
1452 /* Disable Pause Mode in Mode Register */
1453 mode &= ~XM_PAUSE_MODE;
1454
6b0c1480 1455 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1456 }
1457
6b0c1480 1458 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 1459
1460 msk = XM_DEF_MSK;
89bf5f23
SH		 1461 /* disable GP0 interrupt bit for external Phy */
1462 msk |= XM_IS_INP_ASS;
baef58b1 1463
6b0c1480
SH		 1464 xm_write16(hw, port, XM_IMSK, msk);
1465 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1466
1467 /* get MMU Command Reg. */
6b0c1480 1468 cmd = xm_read16(hw, port, XM_MMU_CMD);
89bf5f23 1469 if (skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1470 cmd |= XM_MMU_GMII_FD;
1471
89bf5f23
SH		 1472 /*
1473 * Workaround BCOM Errata (#10523) for all BCom Phys
1474 * Enable Power Management after link up
1475 */
1476 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1477 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1478 & ~PHY_B_AC_DIS_PM);
1479 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
baef58b1
SH		 1480
1481 /* enable Rx/Tx */
6b0c1480 1482 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1483 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1484 skge_link_up(skge);
1485}
1486
1487
45bada65 1488static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1489{
1490 struct skge_hw *hw = skge->hw;
1491 int port = skge->port;
45bada65
SH		 1492 u16 isrc;
1493
1494 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1495 if (netif_msg_intr(skge))
1496 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1497 skge->netdev->name, isrc);
baef58b1 1498
45bada65
SH		 1499 if (isrc & PHY_B_IS_PSE)
1500 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1501 hw->dev[port]->name);
baef58b1
SH		 1502
1503 /* Workaround BCom Errata:
1504 * enable and disable loopback mode if "NO HCD" occurs.
1505 */
45bada65 1506 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1507 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1508 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1509 ctrl | PHY_CT_LOOP);
6b0c1480 1510 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1511 ctrl & ~PHY_CT_LOOP);
1512 }
1513
45bada65
SH		 1514 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1515 bcom_check_link(hw, port);
baef58b1 1516
baef58b1
SH		 1517}
1518
2cd8e5d3
SH		 1519static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1520{
1521 int i;
1522
1523 gma_write16(hw, port, GM_SMI_DATA, val);
1524 gma_write16(hw, port, GM_SMI_CTRL,
1525 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1526 for (i = 0; i < PHY_RETRIES; i++) {
1527 udelay(1);
1528
1529 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1530 return 0;
1531 }
1532
1533 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1534 hw->dev[port]->name);
1535 return -EIO;
1536}
1537
1538static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1539{
1540 int i;
1541
1542 gma_write16(hw, port, GM_SMI_CTRL,
1543 GM_SMI_CT_PHY_AD(hw->phy_addr)
1544 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1545
1546 for (i = 0; i < PHY_RETRIES; i++) {
1547 udelay(1);
1548 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1549 goto ready;
1550 }
1551
1552 return -ETIMEDOUT;
1553 ready:
1554 *val = gma_read16(hw, port, GM_SMI_DATA);
1555 return 0;
1556}
1557
1558static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1559{
1560 u16 v = 0;
1561 if (__gm_phy_read(hw, port, reg, &v))
1562 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1563 hw->dev[port]->name);
1564 return v;
1565}
1566
8f3f8193 1567/* Marvell Phy Initialization */
baef58b1
SH		 1568static void yukon_init(struct skge_hw *hw, int port)
1569{
1570 struct skge_port *skge = netdev_priv(hw->dev[port]);
1571 u16 ctrl, ct1000, adv;
baef58b1 1572
baef58b1 1573 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1574 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1575
1576 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1577 PHY_M_EC_MAC_S_MSK);
1578 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1579
c506a509 1580 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1581
6b0c1480 1582 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1583 }
1584
6b0c1480 1585 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1586 if (skge->autoneg == AUTONEG_DISABLE)
1587 ctrl &= ~PHY_CT_ANE;
1588
1589 ctrl |= PHY_CT_RESET;
6b0c1480 1590 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1591
1592 ctrl = 0;
1593 ct1000 = 0;
b18f2091 1594 adv = PHY_AN_CSMA;
baef58b1
SH		 1595
1596 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1597 if (hw->copper) {
baef58b1
SH		 1598 if (skge->advertising & ADVERTISED_1000baseT_Full)
1599 ct1000 |= PHY_M_1000C_AFD;
1600 if (skge->advertising & ADVERTISED_1000baseT_Half)
1601 ct1000 |= PHY_M_1000C_AHD;
1602 if (skge->advertising & ADVERTISED_100baseT_Full)
1603 adv |= PHY_M_AN_100_FD;
1604 if (skge->advertising & ADVERTISED_100baseT_Half)
1605 adv |= PHY_M_AN_100_HD;
1606 if (skge->advertising & ADVERTISED_10baseT_Full)
1607 adv |= PHY_M_AN_10_FD;
1608 if (skge->advertising & ADVERTISED_10baseT_Half)
1609 adv |= PHY_M_AN_10_HD;
45bada65 1610 } else /* special defines for FIBER (88E1011S only) */
baef58b1
SH		 1611 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1612
45bada65
SH		 1613 /* Set Flow-control capabilities */
1614 adv |= phy_pause_map[skge->flow_control];
1615
baef58b1
SH		 1616 /* Restart Auto-negotiation */
1617 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1618 } else {
1619 /* forced speed/duplex settings */
1620 ct1000 = PHY_M_1000C_MSE;
1621
1622 if (skge->duplex == DUPLEX_FULL)
1623 ctrl |= PHY_CT_DUP_MD;
1624
1625 switch (skge->speed) {
1626 case SPEED_1000:
1627 ctrl |= PHY_CT_SP1000;
1628 break;
1629 case SPEED_100:
1630 ctrl |= PHY_CT_SP100;
1631 break;
1632 }
1633
1634 ctrl |= PHY_CT_RESET;
1635 }
1636
c506a509 1637 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1638
6b0c1480
SH		 1639 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1640 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 1641
baef58b1
SH		 1642 /* Enable phy interrupt on autonegotiation complete (or link up) */
1643 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 1644 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 1645 else
4cde06ed 1646 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1647}
1648
1649static void yukon_reset(struct skge_hw *hw, int port)
1650{
6b0c1480
SH		 1651 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1652 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1653 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1654 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1655 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1656
6b0c1480
SH		 1657 gma_write16(hw, port, GM_RX_CTRL,
1658 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1659 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1660}
1661
c8868611
SH		 1662/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1663static int is_yukon_lite_a0(struct skge_hw *hw)
1664{
1665 u32 reg;
1666 int ret;
1667
1668 if (hw->chip_id != CHIP_ID_YUKON)
1669 return 0;
1670
1671 reg = skge_read32(hw, B2_FAR);
1672 skge_write8(hw, B2_FAR + 3, 0xff);
1673 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1674 skge_write32(hw, B2_FAR, reg);
1675 return ret;
1676}
1677
baef58b1
SH		 1678static void yukon_mac_init(struct skge_hw *hw, int port)
1679{
1680 struct skge_port *skge = netdev_priv(hw->dev[port]);
1681 int i;
1682 u32 reg;
1683 const u8 *addr = hw->dev[port]->dev_addr;
1684
1685 /* WA code for COMA mode -- set PHY reset */
1686 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1687 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1688 reg = skge_read32(hw, B2_GP_IO);
1689 reg |= GP_DIR_9 | GP_IO_9;
1690 skge_write32(hw, B2_GP_IO, reg);
1691 }
baef58b1
SH		 1692
1693 /* hard reset */
6b0c1480
SH		 1694 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1695 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1696
1697 /* WA code for COMA mode -- clear PHY reset */
1698 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1699 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1700 reg = skge_read32(hw, B2_GP_IO);
1701 reg |= GP_DIR_9;
1702 reg &= ~GP_IO_9;
1703 skge_write32(hw, B2_GP_IO, reg);
1704 }
baef58b1
SH		 1705
1706 /* Set hardware config mode */
1707 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1708 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 1709 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 1710
1711 /* Clear GMC reset */
6b0c1480
SH		 1712 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1713 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1714 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 1715
baef58b1
SH		 1716 if (skge->autoneg == AUTONEG_DISABLE) {
1717 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1718 gma_write16(hw, port, GM_GP_CTRL,
1719 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1720
1721 switch (skge->speed) {
1722 case SPEED_1000:
564f9abb 1723 reg &= ~GM_GPCR_SPEED_100;
baef58b1 1724 reg |= GM_GPCR_SPEED_1000;
564f9abb 1725 break;
baef58b1 1726 case SPEED_100:
564f9abb 1727 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 1728 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 1729 break;
1730 case SPEED_10:
1731 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1732 break;
baef58b1
SH		 1733 }
1734
1735 if (skge->duplex == DUPLEX_FULL)
1736 reg |= GM_GPCR_DUP_FULL;
1737 } else
1738 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 1739
baef58b1
SH		 1740 switch (skge->flow_control) {
1741 case FLOW_MODE_NONE:
6b0c1480 1742 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1743 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1744 break;
1745 case FLOW_MODE_LOC_SEND:
1746 /* disable Rx flow-control */
1747 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1748 }
1749
6b0c1480 1750 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 1751 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1752
baef58b1 1753 yukon_init(hw, port);
baef58b1
SH		 1754
1755 /* MIB clear */
6b0c1480
SH		 1756 reg = gma_read16(hw, port, GM_PHY_ADDR);
1757 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1758
1759 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1760 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1761 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1762
1763 /* transmit control */
6b0c1480 1764 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1765
1766 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1767 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1768 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1769
1770 /* transmit flow control */
6b0c1480 1771 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1772
1773 /* transmit parameter */
6b0c1480 1774 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1775 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1776 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1777 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1778
1779 /* serial mode register */
1780 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1781 if (hw->dev[port]->mtu > 1500)
1782 reg |= GM_SMOD_JUMBO_ENA;
1783
6b0c1480 1784 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 1785
1786 /* physical address: used for pause frames */
6b0c1480 1787 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 1788 /* virtual address for data */
6b0c1480 1789 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 1790
1791 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 1792 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1793 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1794 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 1795
1796 /* Initialize Mac Fifo */
1797
1798 /* Configure Rx MAC FIFO */
6b0c1480 1799 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 1800 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 1801
1802 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1803 if (is_yukon_lite_a0(hw))
baef58b1 1804 reg &= ~GMF_RX_F_FL_ON;
c8868611 1805
6b0c1480
SH		 1806 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1807 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 1808 /*
1809 * because Pause Packet Truncation in GMAC is not working
1810 * we have to increase the Flush Threshold to 64 bytes
1811 * in order to flush pause packets in Rx FIFO on Yukon-1
1812 */
1813 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 1814
1815 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1816 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1817 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 1818}
1819
355ec572
SH		 1820/* Go into power down mode */
1821static void yukon_suspend(struct skge_hw *hw, int port)
1822{
1823 u16 ctrl;
1824
1825 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1826 ctrl |= PHY_M_PC_POL_R_DIS;
1827 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1828
1829 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1830 ctrl |= PHY_CT_RESET;
1831 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1832
1833 /* switch IEEE compatible power down mode on */
1834 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1835 ctrl |= PHY_CT_PDOWN;
1836 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1837}
1838
baef58b1
SH		 1839static void yukon_stop(struct skge_port *skge)
1840{
1841 struct skge_hw *hw = skge->hw;
1842 int port = skge->port;
1843
46a60f2d
SH		 1844 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1845 yukon_reset(hw, port);
baef58b1 1846
6b0c1480
SH		 1847 gma_write16(hw, port, GM_GP_CTRL,
1848 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 1849 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 1850 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 1851
355ec572 1852 yukon_suspend(hw, port);
46a60f2d 1853
baef58b1 1854 /* set GPHY Control reset */
46a60f2d
SH		 1855 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1856 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1857}
1858
1859static void yukon_get_stats(struct skge_port *skge, u64 *data)
1860{
1861 struct skge_hw *hw = skge->hw;
1862 int port = skge->port;
1863 int i;
1864
6b0c1480
SH		 1865 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1866 | gma_read32(hw, port, GM_TXO_OK_LO);
1867 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1868 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 1869
1870 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1871 data[i] = gma_read32(hw, port,
baef58b1
SH		 1872 skge_stats[i].gma_offset);
1873}
1874
1875static void yukon_mac_intr(struct skge_hw *hw, int port)
1876{
7e676d91
SH		 1877 struct net_device *dev = hw->dev[port];
1878 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1879 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1880
7e676d91
SH		 1881 if (netif_msg_intr(skge))
1882 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1883 dev->name, status);
1884
baef58b1
SH		 1885 if (status & GM_IS_RX_FF_OR) {
1886 ++skge->net_stats.rx_fifo_errors;
d8a09943 1887 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 1888 }
d8a09943 1889
baef58b1
SH		 1890 if (status & GM_IS_TX_FF_UR) {
1891 ++skge->net_stats.tx_fifo_errors;
d8a09943 1892 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 1893 }
1894
1895}
1896
1897static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1898{
95566065 1899 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 1900 case PHY_M_PS_SPEED_1000:
1901 return SPEED_1000;
1902 case PHY_M_PS_SPEED_100:
1903 return SPEED_100;
1904 default:
1905 return SPEED_10;
1906 }
1907}
1908
1909static void yukon_link_up(struct skge_port *skge)
1910{
1911 struct skge_hw *hw = skge->hw;
1912 int port = skge->port;
1913 u16 reg;
1914
baef58b1 1915 /* Enable Transmit FIFO Underrun */
46a60f2d 1916 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 1917
6b0c1480 1918 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1919 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1920 reg |= GM_GPCR_DUP_FULL;
1921
1922 /* enable Rx/Tx */
1923 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 1924 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 1925
4cde06ed 1926 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1927 skge_link_up(skge);
1928}
1929
1930static void yukon_link_down(struct skge_port *skge)
1931{
1932 struct skge_hw *hw = skge->hw;
1933 int port = skge->port;
d8a09943 1934 u16 ctrl;
baef58b1 1935
6b0c1480 1936 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
d8a09943
SH		 1937
1938 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1939 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1940 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 1941
c506a509 1942 if (skge->flow_control == FLOW_MODE_REM_SEND) {
baef58b1 1943 /* restore Asymmetric Pause bit */
6b0c1480
SH		 1944 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1945 gm_phy_read(hw, port,
baef58b1
SH		 1946 PHY_MARV_AUNE_ADV)
1947 | PHY_M_AN_ASP);
1948
1949 }
1950
1951 yukon_reset(hw, port);
1952 skge_link_down(skge);
1953
1954 yukon_init(hw, port);
1955}
1956
1957static void yukon_phy_intr(struct skge_port *skge)
1958{
1959 struct skge_hw *hw = skge->hw;
1960 int port = skge->port;
1961 const char *reason = NULL;
1962 u16 istatus, phystat;
1963
6b0c1480
SH		 1964 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1965 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 1966
1967 if (netif_msg_intr(skge))
1968 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1969 skge->netdev->name, istatus, phystat);
baef58b1
SH		 1970
1971 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 1972 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 1973 & PHY_M_AN_RF) {
1974 reason = "remote fault";
1975 goto failed;
1976 }
1977
c506a509 1978 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 1979 reason = "master/slave fault";
1980 goto failed;
1981 }
1982
1983 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1984 reason = "speed/duplex";
1985 goto failed;
1986 }
1987
1988 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1989 ? DUPLEX_FULL : DUPLEX_HALF;
1990 skge->speed = yukon_speed(hw, phystat);
1991
baef58b1
SH		 1992 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1993 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1994 case PHY_M_PS_PAUSE_MSK:
1995 skge->flow_control = FLOW_MODE_SYMMETRIC;
1996 break;
1997 case PHY_M_PS_RX_P_EN:
1998 skge->flow_control = FLOW_MODE_REM_SEND;
1999 break;
2000 case PHY_M_PS_TX_P_EN:
2001 skge->flow_control = FLOW_MODE_LOC_SEND;
2002 break;
2003 default:
2004 skge->flow_control = FLOW_MODE_NONE;
2005 }
2006
2007 if (skge->flow_control == FLOW_MODE_NONE ||
2008 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2009 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2010 else
6b0c1480 2011 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2012 yukon_link_up(skge);
2013 return;
2014 }
2015
2016 if (istatus & PHY_M_IS_LSP_CHANGE)
2017 skge->speed = yukon_speed(hw, phystat);
2018
2019 if (istatus & PHY_M_IS_DUP_CHANGE)
2020 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2021 if (istatus & PHY_M_IS_LST_CHANGE) {
2022 if (phystat & PHY_M_PS_LINK_UP)
2023 yukon_link_up(skge);
2024 else
2025 yukon_link_down(skge);
2026 }
2027 return;
2028 failed:
2029 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2030 skge->netdev->name, reason);
2031
2032 /* XXX restart autonegotiation? */
2033}
2034
ee294dcd
SH		 2035static void skge_phy_reset(struct skge_port *skge)
2036{
2037 struct skge_hw *hw = skge->hw;
2038 int port = skge->port;
2039
2040 netif_stop_queue(skge->netdev);
2041 netif_carrier_off(skge->netdev);
2042
2043 spin_lock_bh(&hw->phy_lock);
2044 if (hw->chip_id == CHIP_ID_GENESIS) {
2045 genesis_reset(hw, port);
2046 genesis_mac_init(hw, port);
2047 } else {
2048 yukon_reset(hw, port);
2049 yukon_init(hw, port);
2050 }
2051 spin_unlock_bh(&hw->phy_lock);
2052}
2053
2cd8e5d3
SH		 2054/* Basic MII support */
2055static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2056{
2057 struct mii_ioctl_data *data = if_mii(ifr);
2058 struct skge_port *skge = netdev_priv(dev);
2059 struct skge_hw *hw = skge->hw;
2060 int err = -EOPNOTSUPP;
2061
2062 if (!netif_running(dev))
2063 return -ENODEV; /* Phy still in reset */
2064
2065 switch(cmd) {
2066 case SIOCGMIIPHY:
2067 data->phy_id = hw->phy_addr;
2068
2069 /* fallthru */
2070 case SIOCGMIIREG: {
2071 u16 val = 0;
2072 spin_lock_bh(&hw->phy_lock);
2073 if (hw->chip_id == CHIP_ID_GENESIS)
2074 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2075 else
2076 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2077 spin_unlock_bh(&hw->phy_lock);
2078 data->val_out = val;
2079 break;
2080 }
2081
2082 case SIOCSMIIREG:
2083 if (!capable(CAP_NET_ADMIN))
2084 return -EPERM;
2085
2086 spin_lock_bh(&hw->phy_lock);
2087 if (hw->chip_id == CHIP_ID_GENESIS)
2088 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2089 data->val_in);
2090 else
2091 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2092 data->val_in);
2093 spin_unlock_bh(&hw->phy_lock);
2094 break;
2095 }
2096 return err;
2097}
2098
baef58b1
SH		 2099static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2100{
2101 u32 end;
2102
2103 start /= 8;
2104 len /= 8;
2105 end = start + len - 1;
2106
2107 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2108 skge_write32(hw, RB_ADDR(q, RB_START), start);
2109 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2110 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2111 skge_write32(hw, RB_ADDR(q, RB_END), end);
2112
2113 if (q == Q_R1 || q == Q_R2) {
2114 /* Set thresholds on receive queue's */
2115 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2116 start + (2*len)/3);
2117 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2118 start + (len/3));
2119 } else {
2120 /* Enable store & forward on Tx queue's because
2121 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2122 */
2123 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2124 }
2125
2126 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2127}
2128
2129/* Setup Bus Memory Interface */
2130static void skge_qset(struct skge_port *skge, u16 q,
2131 const struct skge_element *e)
2132{
2133 struct skge_hw *hw = skge->hw;
2134 u32 watermark = 0x600;
2135 u64 base = skge->dma + (e->desc - skge->mem);
2136
2137 /* optimization to reduce window on 32bit/33mhz */
2138 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2139 watermark /= 2;
2140
2141 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2142 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2143 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2144 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2145}
2146
2147static int skge_up(struct net_device *dev)
2148{
2149 struct skge_port *skge = netdev_priv(dev);
2150 struct skge_hw *hw = skge->hw;
2151 int port = skge->port;
2152 u32 chunk, ram_addr;
2153 size_t rx_size, tx_size;
2154 int err;
2155
2156 if (netif_msg_ifup(skge))
2157 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2158
19a33d4e
SH		 2159 if (dev->mtu > RX_BUF_SIZE)
2160 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2161 else
2162 skge->rx_buf_size = RX_BUF_SIZE;
2163
2164
baef58b1
SH		 2165 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2166 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2167 skge->mem_size = tx_size + rx_size;
2168 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2169 if (!skge->mem)
2170 return -ENOMEM;
2171
2172 memset(skge->mem, 0, skge->mem_size);
2173
2174 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2175 goto free_pci_mem;
2176
19a33d4e
SH		 2177 err = skge_rx_fill(skge);
2178 if (err)
baef58b1
SH		 2179 goto free_rx_ring;
2180
2181 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2182 skge->dma + rx_size)))
2183 goto free_rx_ring;
2184
2185 skge->tx_avail = skge->tx_ring.count - 1;
2186
7e676d91 2187 /* Enable IRQ from port */
80dd857d 2188 spin_lock_irq(&hw->hw_lock);
7e676d91
SH		 2189 hw->intr_mask |= portirqmask[port];
2190 skge_write32(hw, B0_IMSK, hw->intr_mask);
80dd857d 2191 spin_unlock_irq(&hw->hw_lock);
7e676d91 2192
8f3f8193 2193 /* Initialize MAC */
4ff6ac05 2194 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2195 if (hw->chip_id == CHIP_ID_GENESIS)
2196 genesis_mac_init(hw, port);
2197 else
2198 yukon_mac_init(hw, port);
4ff6ac05 2199 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 2200
2201 /* Configure RAMbuffers */
981d0377 2202 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2203 ram_addr = hw->ram_offset + 2 * chunk * port;
2204
2205 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2206 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2207
2208 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2209 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2210 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2211
2212 /* Start receiver BMU */
2213 wmb();
2214 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2215 skge_led(skge, LED_MODE_ON);
baef58b1 2216
baef58b1
SH		 2217 return 0;
2218
2219 free_rx_ring:
2220 skge_rx_clean(skge);
2221 kfree(skge->rx_ring.start);
2222 free_pci_mem:
2223 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2224 skge->mem = NULL;
baef58b1
SH		 2225
2226 return err;
2227}
2228
2229static int skge_down(struct net_device *dev)
2230{
2231 struct skge_port *skge = netdev_priv(dev);
2232 struct skge_hw *hw = skge->hw;
2233 int port = skge->port;
2234
7731a4ea
SH		 2235 if (skge->mem == NULL)
2236 return 0;
2237
baef58b1
SH		 2238 if (netif_msg_ifdown(skge))
2239 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2240
2241 netif_stop_queue(dev);
2242
46a60f2d
SH		 2243 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2244 if (hw->chip_id == CHIP_ID_GENESIS)
2245 genesis_stop(skge);
2246 else
2247 yukon_stop(skge);
2248
80dd857d 2249 spin_lock_irq(&hw->hw_lock);
46a60f2d
SH		 2250 hw->intr_mask &= ~portirqmask[skge->port];
2251 skge_write32(hw, B0_IMSK, hw->intr_mask);
80dd857d 2252 spin_unlock_irq(&hw->hw_lock);
46a60f2d 2253
baef58b1
SH		 2254 /* Stop transmitter */
2255 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2256 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2257 RB_RST_SET|RB_DIS_OP_MD);
2258
baef58b1
SH		 2259
2260 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2261 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2262 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2263
2264 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2265 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2266 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2267
2268 /* Reset PCI FIFO */
2269 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2270 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2271
2272 /* Reset the RAM Buffer async Tx queue */
2273 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2274 /* stop receiver */
2275 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2276 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2277 RB_RST_SET|RB_DIS_OP_MD);
2278 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2279
2280 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2281 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2282 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2283 } else {
6b0c1480
SH		 2284 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2285 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2286 }
2287
6abebb53 2288 skge_led(skge, LED_MODE_OFF);
baef58b1
SH		 2289
2290 skge_tx_clean(skge);
2291 skge_rx_clean(skge);
2292
2293 kfree(skge->rx_ring.start);
2294 kfree(skge->tx_ring.start);
2295 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2296 skge->mem = NULL;
baef58b1
SH		 2297 return 0;
2298}
2299
2300static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2301{
2302 struct skge_port *skge = netdev_priv(dev);
2303 struct skge_hw *hw = skge->hw;
2304 struct skge_ring *ring = &skge->tx_ring;
2305 struct skge_element *e;
2306 struct skge_tx_desc *td;
2307 int i;
2308 u32 control, len;
2309 u64 map;
2310 unsigned long flags;
2311
2312 skb = skb_padto(skb, ETH_ZLEN);
2313 if (!skb)
2314 return NETDEV_TX_OK;
2315
2316 local_irq_save(flags);
2317 if (!spin_trylock(&skge->tx_lock)) {
95566065
SH		 2318 /* Collision - tell upper layer to requeue */
2319 local_irq_restore(flags);
2320 return NETDEV_TX_LOCKED;
2321 }
baef58b1
SH		 2322
2323 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
98684a9d 2324 if (!netif_queue_stopped(dev)) {
ee1c8191 2325 netif_stop_queue(dev);
baef58b1 2326
ee1c8191
SH		 2327 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2328 dev->name);
2329 }
2330 spin_unlock_irqrestore(&skge->tx_lock, flags);
baef58b1
SH		 2331 return NETDEV_TX_BUSY;
2332 }
2333
2334 e = ring->to_use;
2335 td = e->desc;
2336 e->skb = skb;
2337 len = skb_headlen(skb);
2338 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2339 pci_unmap_addr_set(e, mapaddr, map);
2340 pci_unmap_len_set(e, maplen, len);
2341
2342 td->dma_lo = map;
2343 td->dma_hi = map >> 32;
2344
2345 if (skb->ip_summed == CHECKSUM_HW) {
baef58b1
SH		 2346 int offset = skb->h.raw - skb->data;
2347
2348 /* This seems backwards, but it is what the sk98lin
2349 * does. Looks like hardware is wrong?
2350 */
ea182d4a 2351 if (skb->h.ipiph->protocol == IPPROTO_UDP
981d0377 2352 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2353 control = BMU_TCP_CHECK;
2354 else
2355 control = BMU_UDP_CHECK;
2356
2357 td->csum_offs = 0;
2358 td->csum_start = offset;
2359 td->csum_write = offset + skb->csum;
2360 } else
2361 control = BMU_CHECK;
2362
2363 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2364 control |= BMU_EOF| BMU_IRQ_EOF;
2365 else {
2366 struct skge_tx_desc *tf = td;
2367
2368 control |= BMU_STFWD;
2369 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2370 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2371
2372 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2373 frag->size, PCI_DMA_TODEVICE);
2374
2375 e = e->next;
2376 e->skb = NULL;
2377 tf = e->desc;
2378 tf->dma_lo = map;
2379 tf->dma_hi = (u64) map >> 32;
2380 pci_unmap_addr_set(e, mapaddr, map);
2381 pci_unmap_len_set(e, maplen, frag->size);
2382
2383 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2384 }
2385 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2386 }
2387 /* Make sure all the descriptors written */
2388 wmb();
2389 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2390 wmb();
2391
2392 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2393
2394 if (netif_msg_tx_queued(skge))
0b2d7fea 2395 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
baef58b1
SH		 2396 dev->name, e - ring->start, skb->len);
2397
2398 ring->to_use = e->next;
2399 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2400 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2401 pr_debug("%s: transmit queue full\n", dev->name);
2402 netif_stop_queue(dev);
2403 }
2404
2405 dev->trans_start = jiffies;
2406 spin_unlock_irqrestore(&skge->tx_lock, flags);
2407
2408 return NETDEV_TX_OK;
2409}
2410
2411static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2412{
19a33d4e 2413 /* This ring element can be skb or fragment */
baef58b1
SH		 2414 if (e->skb) {
2415 pci_unmap_single(hw->pdev,
2416 pci_unmap_addr(e, mapaddr),
2417 pci_unmap_len(e, maplen),
2418 PCI_DMA_TODEVICE);
2419 dev_kfree_skb_any(e->skb);
2420 e->skb = NULL;
2421 } else {
2422 pci_unmap_page(hw->pdev,
2423 pci_unmap_addr(e, mapaddr),
2424 pci_unmap_len(e, maplen),
2425 PCI_DMA_TODEVICE);
2426 }
2427}
2428
2429static void skge_tx_clean(struct skge_port *skge)
2430{
2431 struct skge_ring *ring = &skge->tx_ring;
2432 struct skge_element *e;
2433 unsigned long flags;
2434
2435 spin_lock_irqsave(&skge->tx_lock, flags);
2436 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2437 ++skge->tx_avail;
2438 skge_tx_free(skge->hw, e);
2439 }
2440 ring->to_clean = e;
2441 spin_unlock_irqrestore(&skge->tx_lock, flags);
2442}
2443
2444static void skge_tx_timeout(struct net_device *dev)
2445{
2446 struct skge_port *skge = netdev_priv(dev);
2447
2448 if (netif_msg_timer(skge))
2449 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2450
2451 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2452 skge_tx_clean(skge);
2453}
2454
2455static int skge_change_mtu(struct net_device *dev, int new_mtu)
2456{
7731a4ea 2457 int err;
baef58b1 2458
95566065 2459 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2460 return -EINVAL;
2461
7731a4ea
SH		 2462 if (!netif_running(dev)) {
2463 dev->mtu = new_mtu;
2464 return 0;
2465 }
2466
2467 skge_down(dev);
baef58b1 2468
19a33d4e 2469 dev->mtu = new_mtu;
7731a4ea
SH		 2470
2471 err = skge_up(dev);
2472 if (err)
2473 dev_close(dev);
baef58b1
SH		 2474
2475 return err;
2476}
2477
2478static void genesis_set_multicast(struct net_device *dev)
2479{
2480 struct skge_port *skge = netdev_priv(dev);
2481 struct skge_hw *hw = skge->hw;
2482 int port = skge->port;
2483 int i, count = dev->mc_count;
2484 struct dev_mc_list *list = dev->mc_list;
2485 u32 mode;
2486 u8 filter[8];
2487
6b0c1480 2488 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2489 mode |= XM_MD_ENA_HASH;
2490 if (dev->flags & IFF_PROMISC)
2491 mode |= XM_MD_ENA_PROM;
2492 else
2493 mode &= ~XM_MD_ENA_PROM;
2494
2495 if (dev->flags & IFF_ALLMULTI)
2496 memset(filter, 0xff, sizeof(filter));
2497 else {
2498 memset(filter, 0, sizeof(filter));
95566065 2499 for (i = 0; list && i < count; i++, list = list->next) {
45bada65
SH		 2500 u32 crc, bit;
2501 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2502 bit = ~crc & 0x3f;
baef58b1
SH		 2503 filter[bit/8] |= 1 << (bit%8);
2504 }
2505 }
2506
6b0c1480 2507 xm_write32(hw, port, XM_MODE, mode);
45bada65 2508 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2509}
2510
2511static void yukon_set_multicast(struct net_device *dev)
2512{
2513 struct skge_port *skge = netdev_priv(dev);
2514 struct skge_hw *hw = skge->hw;
2515 int port = skge->port;
2516 struct dev_mc_list *list = dev->mc_list;
2517 u16 reg;
2518 u8 filter[8];
2519
2520 memset(filter, 0, sizeof(filter));
2521
6b0c1480 2522 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2523 reg |= GM_RXCR_UCF_ENA;
2524
8f3f8193 2525 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2526 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2527 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2528 memset(filter, 0xff, sizeof(filter));
2529 else if (dev->mc_count == 0) /* no multicast */
2530 reg &= ~GM_RXCR_MCF_ENA;
2531 else {
2532 int i;
2533 reg |= GM_RXCR_MCF_ENA;
2534
95566065 2535 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2536 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2537 filter[bit/8] |= 1 << (bit%8);
2538 }
2539 }
2540
2541
6b0c1480 2542 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2543 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2544 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2545 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2546 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2547 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2548 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2549 (u16)filter[6] | ((u16)filter[7] << 8));
2550
6b0c1480 2551 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2552}
2553
383181ac
SH		 2554static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2555{
2556 if (hw->chip_id == CHIP_ID_GENESIS)
2557 return status >> XMR_FS_LEN_SHIFT;
2558 else
2559 return status >> GMR_FS_LEN_SHIFT;
2560}
2561
baef58b1
SH		 2562static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2563{
2564 if (hw->chip_id == CHIP_ID_GENESIS)
2565 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2566 else
2567 return (status & GMR_FS_ANY_ERR) ||
2568 (status & GMR_FS_RX_OK) == 0;
2569}
2570
19a33d4e
SH		 2571
2572/* Get receive buffer from descriptor.
2573 * Handles copy of small buffers and reallocation failures
2574 */
2575static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2576 struct skge_element *e,
383181ac 2577 u32 control, u32 status, u16 csum)
19a33d4e 2578{
383181ac
SH		 2579 struct sk_buff *skb;
2580 u16 len = control & BMU_BBC;
2581
2582 if (unlikely(netif_msg_rx_status(skge)))
2583 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2584 skge->netdev->name, e - skge->rx_ring.start,
2585 status, len);
2586
2587 if (len > skge->rx_buf_size)
2588 goto error;
2589
2590 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2591 goto error;
2592
2593 if (bad_phy_status(skge->hw, status))
2594 goto error;
2595
2596 if (phy_length(skge->hw, status) != len)
2597 goto error;
19a33d4e
SH		 2598
2599 if (len < RX_COPY_THRESHOLD) {
383181ac
SH		 2600 skb = dev_alloc_skb(len + 2);
2601 if (!skb)
2602 goto resubmit;
19a33d4e 2603
383181ac 2604 skb_reserve(skb, 2);
19a33d4e
SH		 2605 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2606 pci_unmap_addr(e, mapaddr),
2607 len, PCI_DMA_FROMDEVICE);
383181ac 2608 memcpy(skb->data, e->skb->data, len);
19a33d4e
SH		 2609 pci_dma_sync_single_for_device(skge->hw->pdev,
2610 pci_unmap_addr(e, mapaddr),
2611 len, PCI_DMA_FROMDEVICE);
19a33d4e 2612 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 2613 } else {
383181ac
SH		 2614 struct sk_buff *nskb;
2615 nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
2616 if (!nskb)
2617 goto resubmit;
19a33d4e
SH		 2618
2619 pci_unmap_single(skge->hw->pdev,
2620 pci_unmap_addr(e, mapaddr),
2621 pci_unmap_len(e, maplen),
2622 PCI_DMA_FROMDEVICE);
2623 skb = e->skb;
383181ac 2624 prefetch(skb->data);
19a33d4e 2625 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 2626 }
383181ac
SH		 2627
2628 skb_put(skb, len);
2629 skb->dev = skge->netdev;
2630 if (skge->rx_csum) {
2631 skb->csum = csum;
2632 skb->ip_summed = CHECKSUM_HW;
2633 }
2634
2635 skb->protocol = eth_type_trans(skb, skge->netdev);
2636
2637 return skb;
2638error:
2639
2640 if (netif_msg_rx_err(skge))
2641 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2642 skge->netdev->name, e - skge->rx_ring.start,
2643 control, status);
2644
2645 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2646 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2647 skge->net_stats.rx_length_errors++;
2648 if (status & XMR_FS_FRA_ERR)
2649 skge->net_stats.rx_frame_errors++;
2650 if (status & XMR_FS_FCS_ERR)
2651 skge->net_stats.rx_crc_errors++;
2652 } else {
2653 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2654 skge->net_stats.rx_length_errors++;
2655 if (status & GMR_FS_FRAGMENT)
2656 skge->net_stats.rx_frame_errors++;
2657 if (status & GMR_FS_CRC_ERR)
2658 skge->net_stats.rx_crc_errors++;
2659 }
2660
2661resubmit:
2662 skge_rx_reuse(e, skge->rx_buf_size);
2663 return NULL;
baef58b1
SH		 2664}
2665
19a33d4e 2666
baef58b1
SH		 2667static int skge_poll(struct net_device *dev, int *budget)
2668{
2669 struct skge_port *skge = netdev_priv(dev);
2670 struct skge_hw *hw = skge->hw;
2671 struct skge_ring *ring = &skge->rx_ring;
2672 struct skge_element *e;
2673 unsigned int to_do = min(dev->quota, *budget);
2674 unsigned int work_done = 0;
7e676d91 2675
1631aef1 2676 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 2677 struct skge_rx_desc *rd = e->desc;
19a33d4e 2678 struct sk_buff *skb;
383181ac 2679 u32 control;
baef58b1
SH		 2680
2681 rmb();
2682 control = rd->control;
2683 if (control & BMU_OWN)
2684 break;
2685
383181ac
SH		 2686 skb = skge_rx_get(skge, e, control, rd->status,
2687 le16_to_cpu(rd->csum2));
19a33d4e 2688 if (likely(skb)) {
19a33d4e
SH		 2689 dev->last_rx = jiffies;
2690 netif_receive_skb(skb);
baef58b1 2691
19a33d4e
SH		 2692 ++work_done;
2693 } else
2694 skge_rx_reuse(e, skge->rx_buf_size);
baef58b1
SH		 2695 }
2696 ring->to_clean = e;
2697
baef58b1
SH		 2698 /* restart receiver */
2699 wmb();
a9cdab86 2700 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 2701
19a33d4e
SH		 2702 *budget -= work_done;
2703 dev->quota -= work_done;
2704
2705 if (work_done >= to_do)
2706 return 1; /* not done */
baef58b1 2707
80dd857d
SH		 2708 spin_lock_irq(&hw->hw_lock);
2709 __netif_rx_complete(dev);
2710 hw->intr_mask |= portirqmask[skge->port];
2711 skge_write32(hw, B0_IMSK, hw->intr_mask);
2712 spin_unlock_irq(&hw->hw_lock);
1631aef1 2713
19a33d4e 2714 return 0;
baef58b1
SH		 2715}
2716
2717static inline void skge_tx_intr(struct net_device *dev)
2718{
2719 struct skge_port *skge = netdev_priv(dev);
2720 struct skge_hw *hw = skge->hw;
2721 struct skge_ring *ring = &skge->tx_ring;
2722 struct skge_element *e;
2723
2724 spin_lock(&skge->tx_lock);
1631aef1 2725 for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
baef58b1
SH		 2726 struct skge_tx_desc *td = e->desc;
2727 u32 control;
2728
2729 rmb();
2730 control = td->control;
2731 if (control & BMU_OWN)
2732 break;
2733
2734 if (unlikely(netif_msg_tx_done(skge)))
0b2d7fea 2735 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
baef58b1
SH		 2736 dev->name, e - ring->start, td->status);
2737
2738 skge_tx_free(hw, e);
2739 e->skb = NULL;
2740 ++skge->tx_avail;
2741 }
2742 ring->to_clean = e;
2743 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2744
2745 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2746 netif_wake_queue(dev);
2747
2748 spin_unlock(&skge->tx_lock);
2749}
2750
f6620cab
SH		 2751/* Parity errors seem to happen when Genesis is connected to a switch
2752 * with no other ports present. Heartbeat error??
2753 */
baef58b1
SH		 2754static void skge_mac_parity(struct skge_hw *hw, int port)
2755{
f6620cab
SH		 2756 struct net_device *dev = hw->dev[port];
2757
2758 if (dev) {
2759 struct skge_port *skge = netdev_priv(dev);
2760 ++skge->net_stats.tx_heartbeat_errors;
2761 }
baef58b1
SH		 2762
2763 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2764 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2765 MFF_CLR_PERR);
2766 else
2767 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2768 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2769 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2770 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2771}
2772
2773static void skge_pci_clear(struct skge_hw *hw)
2774{
2775 u16 status;
2776
467b3417 2777 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
baef58b1 2778 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
467b3417
SH		 2779 pci_write_config_word(hw->pdev, PCI_STATUS,
2780 status | PCI_STATUS_ERROR_BITS);
baef58b1
SH		 2781 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2782}
2783
2784static void skge_mac_intr(struct skge_hw *hw, int port)
2785{
95566065 2786 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2787 genesis_mac_intr(hw, port);
2788 else
2789 yukon_mac_intr(hw, port);
2790}
2791
2792/* Handle device specific framing and timeout interrupts */
2793static void skge_error_irq(struct skge_hw *hw)
2794{
2795 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2796
2797 if (hw->chip_id == CHIP_ID_GENESIS) {
2798 /* clear xmac errors */
2799 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 2800 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 2801 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 2802 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 2803 } else {
2804 /* Timestamp (unused) overflow */
2805 if (hwstatus & IS_IRQ_TIST_OV)
2806 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 2807 }
2808
2809 if (hwstatus & IS_RAM_RD_PAR) {
2810 printk(KERN_ERR PFX "Ram read data parity error\n");
2811 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2812 }
2813
2814 if (hwstatus & IS_RAM_WR_PAR) {
2815 printk(KERN_ERR PFX "Ram write data parity error\n");
2816 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2817 }
2818
2819 if (hwstatus & IS_M1_PAR_ERR)
2820 skge_mac_parity(hw, 0);
2821
2822 if (hwstatus & IS_M2_PAR_ERR)
2823 skge_mac_parity(hw, 1);
2824
2825 if (hwstatus & IS_R1_PAR_ERR)
2826 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2827
2828 if (hwstatus & IS_R2_PAR_ERR)
2829 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2830
2831 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2832 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2833 hwstatus);
2834
2835 skge_pci_clear(hw);
2836
050ec18a 2837 /* if error still set then just ignore it */
baef58b1
SH		 2838 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2839 if (hwstatus & IS_IRQ_STAT) {
050ec18a 2840 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
baef58b1
SH		 2841 hwstatus);
2842 hw->intr_mask &= ~IS_HW_ERR;
2843 }
2844 }
2845}
2846
2847/*
8f3f8193 2848 * Interrupt from PHY are handled in tasklet (soft irq)
baef58b1
SH		 2849 * because accessing phy registers requires spin wait which might
2850 * cause excess interrupt latency.
2851 */
2852static void skge_extirq(unsigned long data)
2853{
2854 struct skge_hw *hw = (struct skge_hw *) data;
2855 int port;
2856
2857 spin_lock(&hw->phy_lock);
2858 for (port = 0; port < 2; port++) {
2859 struct net_device *dev = hw->dev[port];
2860
2861 if (dev && netif_running(dev)) {
2862 struct skge_port *skge = netdev_priv(dev);
2863
2864 if (hw->chip_id != CHIP_ID_GENESIS)
2865 yukon_phy_intr(skge);
89bf5f23 2866 else
45bada65 2867 bcom_phy_intr(skge);
baef58b1
SH		 2868 }
2869 }
2870 spin_unlock(&hw->phy_lock);
2871
80dd857d 2872 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 2873 hw->intr_mask |= IS_EXT_REG;
2874 skge_write32(hw, B0_IMSK, hw->intr_mask);
80dd857d 2875 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 2876}
2877
2878static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2879{
2880 struct skge_hw *hw = dev_id;
2881 u32 status = skge_read32(hw, B0_SP_ISRC);
2882
2883 if (status == 0 || status == ~0) /* hotplug or shared irq */
2884 return IRQ_NONE;
2885
80dd857d 2886 spin_lock(&hw->hw_lock);
7e676d91 2887 if (status & IS_R1_F) {
a9cdab86 2888 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
baef58b1 2889 hw->intr_mask &= ~IS_R1_F;
a9cdab86 2890 netif_rx_schedule(hw->dev[0]);
baef58b1
SH		 2891 }
2892
7e676d91 2893 if (status & IS_R2_F) {
a9cdab86 2894 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
baef58b1 2895 hw->intr_mask &= ~IS_R2_F;
a9cdab86 2896 netif_rx_schedule(hw->dev[1]);
baef58b1
SH		 2897 }
2898
2899 if (status & IS_XA1_F)
2900 skge_tx_intr(hw->dev[0]);
2901
2902 if (status & IS_XA2_F)
2903 skge_tx_intr(hw->dev[1]);
2904
d25f5a67
SH		 2905 if (status & IS_PA_TO_RX1) {
2906 struct skge_port *skge = netdev_priv(hw->dev[0]);
2907 ++skge->net_stats.rx_over_errors;
2908 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2909 }
2910
2911 if (status & IS_PA_TO_RX2) {
2912 struct skge_port *skge = netdev_priv(hw->dev[1]);
2913 ++skge->net_stats.rx_over_errors;
2914 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2915 }
2916
2917 if (status & IS_PA_TO_TX1)
2918 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2919
2920 if (status & IS_PA_TO_TX2)
2921 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2922
baef58b1
SH		 2923 if (status & IS_MAC1)
2924 skge_mac_intr(hw, 0);
95566065 2925
baef58b1
SH		 2926 if (status & IS_MAC2)
2927 skge_mac_intr(hw, 1);
2928
2929 if (status & IS_HW_ERR)
2930 skge_error_irq(hw);
2931
2932 if (status & IS_EXT_REG) {
2933 hw->intr_mask &= ~IS_EXT_REG;
2934 tasklet_schedule(&hw->ext_tasklet);
2935 }
2936
7e676d91 2937 skge_write32(hw, B0_IMSK, hw->intr_mask);
80dd857d 2938 spin_unlock(&hw->hw_lock);
baef58b1
SH		 2939
2940 return IRQ_HANDLED;
2941}
2942
2943#ifdef CONFIG_NET_POLL_CONTROLLER
2944static void skge_netpoll(struct net_device *dev)
2945{
2946 struct skge_port *skge = netdev_priv(dev);
2947
2948 disable_irq(dev->irq);
2949 skge_intr(dev->irq, skge->hw, NULL);
2950 enable_irq(dev->irq);
2951}
2952#endif
2953
2954static int skge_set_mac_address(struct net_device *dev, void *p)
2955{
2956 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 2957 struct skge_hw *hw = skge->hw;
2958 unsigned port = skge->port;
2959 const struct sockaddr *addr = p;
baef58b1
SH		 2960
2961 if (!is_valid_ether_addr(addr->sa_data))
2962 return -EADDRNOTAVAIL;
2963
c2681dd8 2964 spin_lock_bh(&hw->phy_lock);
baef58b1 2965 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 2966 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
baef58b1 2967 dev->dev_addr, ETH_ALEN);
c2681dd8 2968 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
baef58b1 2969 dev->dev_addr, ETH_ALEN);
c2681dd8
SH		 2970
2971 if (hw->chip_id == CHIP_ID_GENESIS)
2972 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2973 else {
2974 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2975 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2976 }
2977 spin_unlock_bh(&hw->phy_lock);
2978
2979 return 0;
baef58b1
SH		 2980}
2981
2982static const struct {
2983 u8 id;
2984 const char *name;
2985} skge_chips[] = {
2986 { CHIP_ID_GENESIS, "Genesis" },
2987 { CHIP_ID_YUKON, "Yukon" },
2988 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2989 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 2990};
2991
2992static const char *skge_board_name(const struct skge_hw *hw)
2993{
2994 int i;
2995 static char buf[16];
2996
2997 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2998 if (skge_chips[i].id == hw->chip_id)
2999 return skge_chips[i].name;
3000
3001 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3002 return buf;
3003}
3004
3005
3006/*
3007 * Setup the board data structure, but don't bring up
3008 * the port(s)
3009 */
3010static int skge_reset(struct skge_hw *hw)
3011{
adba9e23 3012 u32 reg;
baef58b1 3013 u16 ctst;
5e1705dd 3014 u8 t8, mac_cfg, pmd_type, phy_type;
981d0377 3015 int i;
baef58b1
SH		 3016
3017 ctst = skge_read16(hw, B0_CTST);
3018
3019 /* do a SW reset */
3020 skge_write8(hw, B0_CTST, CS_RST_SET);
3021 skge_write8(hw, B0_CTST, CS_RST_CLR);
3022
3023 /* clear PCI errors, if any */
3024 skge_pci_clear(hw);
3025
3026 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3027
3028 /* restore CLK_RUN bits (for Yukon-Lite) */
3029 skge_write16(hw, B0_CTST,
3030 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3031
3032 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
5e1705dd
SH		 3033 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3034 pmd_type = skge_read8(hw, B2_PMD_TYP);
3035 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3036
95566065 3037 switch (hw->chip_id) {
baef58b1 3038 case CHIP_ID_GENESIS:
5e1705dd 3039 switch (phy_type) {
baef58b1
SH		 3040 case SK_PHY_BCOM:
3041 hw->phy_addr = PHY_ADDR_BCOM;
3042 break;
3043 default:
3044 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
5e1705dd 3045 pci_name(hw->pdev), phy_type);
baef58b1
SH		 3046 return -EOPNOTSUPP;
3047 }
3048 break;
3049
3050 case CHIP_ID_YUKON:
3051 case CHIP_ID_YUKON_LITE:
3052 case CHIP_ID_YUKON_LP:
5e1705dd
SH		 3053 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3054 hw->copper = 1;
baef58b1
SH		 3055
3056 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3057 break;
3058
3059 default:
3060 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3061 pci_name(hw->pdev), hw->chip_id);
3062 return -EOPNOTSUPP;
3063 }
3064
981d0377
SH		 3065 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3066 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3067 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3068
3069 /* read the adapters RAM size */
3070 t8 = skge_read8(hw, B2_E_0);
3071 if (hw->chip_id == CHIP_ID_GENESIS) {
3072 if (t8 == 3) {
3073 /* special case: 4 x 64k x 36, offset = 0x80000 */
3074 hw->ram_size = 0x100000;
3075 hw->ram_offset = 0x80000;
3076 } else
3077 hw->ram_size = t8 * 512;
3078 }
3079 else if (t8 == 0)
3080 hw->ram_size = 0x20000;
3081 else
3082 hw->ram_size = t8 * 4096;
3083
050ec18a 3084 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
baef58b1
SH		 3085 if (hw->chip_id == CHIP_ID_GENESIS)
3086 genesis_init(hw);
3087 else {
3088 /* switch power to VCC (WA for VAUX problem) */
3089 skge_write8(hw, B0_POWER_CTRL,
3090 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3091
050ec18a
SH		 3092 /* avoid boards with stuck Hardware error bits */
3093 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3094 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3095 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3096 hw->intr_mask &= ~IS_HW_ERR;
3097 }
3098
adba9e23
SH		 3099 /* Clear PHY COMA */
3100 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3101 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3102 reg &= ~PCI_PHY_COMA;
3103 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3104 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3105
3106
981d0377 3107 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3108 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3109 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3110 }
3111 }
3112
3113 /* turn off hardware timer (unused) */
3114 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3115 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3116 skge_write8(hw, B0_LED, LED_STAT_ON);
3117
3118 /* enable the Tx Arbiters */
981d0377 3119 for (i = 0; i < hw->ports; i++)
6b0c1480 3120 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3121
3122 /* Initialize ram interface */
3123 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3124
3125 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3126 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3127 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3128 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3129 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3130 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3131 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3132 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3133 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3134 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3135 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3136 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3137
3138 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3139
3140 /* Set interrupt moderation for Transmit only
3141 * Receive interrupts avoided by NAPI
3142 */
3143 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3144 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3145 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3146
baef58b1
SH		 3147 skge_write32(hw, B0_IMSK, hw->intr_mask);
3148
baef58b1 3149 spin_lock_bh(&hw->phy_lock);
981d0377 3150 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3151 if (hw->chip_id == CHIP_ID_GENESIS)
3152 genesis_reset(hw, i);
3153 else
3154 yukon_reset(hw, i);
3155 }
3156 spin_unlock_bh(&hw->phy_lock);
3157
3158 return 0;
3159}
3160
3161/* Initialize network device */
981d0377
SH		 3162static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3163 int highmem)
baef58b1
SH		 3164{
3165 struct skge_port *skge;
3166 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3167
3168 if (!dev) {
3169 printk(KERN_ERR "skge etherdev alloc failed");
3170 return NULL;
3171 }
3172
3173 SET_MODULE_OWNER(dev);
3174 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3175 dev->open = skge_up;
3176 dev->stop = skge_down;
2cd8e5d3 3177 dev->do_ioctl = skge_ioctl;
baef58b1
SH		 3178 dev->hard_start_xmit = skge_xmit_frame;
3179 dev->get_stats = skge_get_stats;
3180 if (hw->chip_id == CHIP_ID_GENESIS)
3181 dev->set_multicast_list = genesis_set_multicast;
3182 else
3183 dev->set_multicast_list = yukon_set_multicast;
3184
3185 dev->set_mac_address = skge_set_mac_address;
3186 dev->change_mtu = skge_change_mtu;
3187 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3188 dev->tx_timeout = skge_tx_timeout;
3189 dev->watchdog_timeo = TX_WATCHDOG;
3190 dev->poll = skge_poll;
3191 dev->weight = NAPI_WEIGHT;
3192#ifdef CONFIG_NET_POLL_CONTROLLER
3193 dev->poll_controller = skge_netpoll;
3194#endif
3195 dev->irq = hw->pdev->irq;
3196 dev->features = NETIF_F_LLTX;
981d0377
SH		 3197 if (highmem)
3198 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3199
3200 skge = netdev_priv(dev);
3201 skge->netdev = dev;
3202 skge->hw = hw;
3203 skge->msg_enable = netif_msg_init(debug, default_msg);
3204 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3205 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3206
3207 /* Auto speed and flow control */
3208 skge->autoneg = AUTONEG_ENABLE;
3209 skge->flow_control = FLOW_MODE_SYMMETRIC;
3210 skge->duplex = -1;
3211 skge->speed = -1;
31b619c5 3212 skge->advertising = skge_supported_modes(hw);
baef58b1
SH		 3213
3214 hw->dev[port] = dev;
3215
3216 skge->port = port;
3217
3218 spin_lock_init(&skge->tx_lock);
3219
baef58b1
SH		 3220 if (hw->chip_id != CHIP_ID_GENESIS) {
3221 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3222 skge->rx_csum = 1;
3223 }
3224
3225 /* read the mac address */
3226 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3227 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3228
3229 /* device is off until link detection */
3230 netif_carrier_off(dev);
3231 netif_stop_queue(dev);
3232
3233 return dev;
3234}
3235
3236static void __devinit skge_show_addr(struct net_device *dev)
3237{
3238 const struct skge_port *skge = netdev_priv(dev);
3239
3240 if (netif_msg_probe(skge))
3241 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3242 dev->name,
3243 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3244 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3245}
3246
3247static int __devinit skge_probe(struct pci_dev *pdev,
3248 const struct pci_device_id *ent)
3249{
3250 struct net_device *dev, *dev1;
3251 struct skge_hw *hw;
3252 int err, using_dac = 0;
3253
3254 if ((err = pci_enable_device(pdev))) {
3255 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3256 pci_name(pdev));
3257 goto err_out;
3258 }
3259
3260 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3261 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3262 pci_name(pdev));
3263 goto err_out_disable_pdev;
3264 }
3265
3266 pci_set_master(pdev);
3267
77783a78
SH		 3268 if (sizeof(dma_addr_t) > sizeof(u32) &&
3269 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
baef58b1 3270 using_dac = 1;
77783a78
SH		 3271 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3272 if (err < 0) {
3273 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3274 "for consistent allocations\n", pci_name(pdev));
3275 goto err_out_free_regions;
3276 }
3277 } else {
3278 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3279 if (err) {
3280 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3281 pci_name(pdev));
3282 goto err_out_free_regions;
3283 }
baef58b1
SH		 3284 }
3285
3286#ifdef __BIG_ENDIAN
8f3f8193 3287 /* byte swap descriptors in hardware */
baef58b1
SH		 3288 {
3289 u32 reg;
3290
3291 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3292 reg |= PCI_REV_DESC;
3293 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3294 }
3295#endif
3296
3297 err = -ENOMEM;
7e863061 3298 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
baef58b1
SH		 3299 if (!hw) {
3300 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3301 pci_name(pdev));
3302 goto err_out_free_regions;
3303 }
3304
baef58b1
SH		 3305 hw->pdev = pdev;
3306 spin_lock_init(&hw->phy_lock);
80dd857d 3307 spin_lock_init(&hw->hw_lock);
baef58b1
SH		 3308 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3309
3310 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3311 if (!hw->regs) {
3312 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3313 pci_name(pdev));
3314 goto err_out_free_hw;
3315 }
3316
3317 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3318 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3319 pci_name(pdev), pdev->irq);
3320 goto err_out_iounmap;
3321 }
3322 pci_set_drvdata(pdev, hw);
3323
3324 err = skge_reset(hw);
3325 if (err)
3326 goto err_out_free_irq;
3327
d7eaee08 3328 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
baef58b1 3329 pci_resource_start(pdev, 0), pdev->irq,
981d0377 3330 skge_board_name(hw), hw->chip_rev);
baef58b1 3331
981d0377 3332 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
baef58b1
SH		 3333 goto err_out_led_off;
3334
baef58b1
SH		 3335 if ((err = register_netdev(dev))) {
3336 printk(KERN_ERR PFX "%s: cannot register net device\n",
3337 pci_name(pdev));
3338 goto err_out_free_netdev;
3339 }
3340
3341 skge_show_addr(dev);
3342
981d0377 3343 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3344 if (register_netdev(dev1) == 0)
3345 skge_show_addr(dev1);
3346 else {
3347 /* Failure to register second port need not be fatal */
3348 printk(KERN_WARNING PFX "register of second port failed\n");
3349 hw->dev[1] = NULL;
3350 free_netdev(dev1);
3351 }
3352 }
3353
3354 return 0;
3355
3356err_out_free_netdev:
3357 free_netdev(dev);
3358err_out_led_off:
3359 skge_write16(hw, B0_LED, LED_STAT_OFF);
3360err_out_free_irq:
3361 free_irq(pdev->irq, hw);
3362err_out_iounmap:
3363 iounmap(hw->regs);
3364err_out_free_hw:
3365 kfree(hw);
3366err_out_free_regions:
3367 pci_release_regions(pdev);
3368err_out_disable_pdev:
3369 pci_disable_device(pdev);
3370 pci_set_drvdata(pdev, NULL);
3371err_out:
3372 return err;
3373}
3374
3375static void __devexit skge_remove(struct pci_dev *pdev)
3376{
3377 struct skge_hw *hw = pci_get_drvdata(pdev);
3378 struct net_device *dev0, *dev1;
3379
95566065 3380 if (!hw)
baef58b1
SH		 3381 return;
3382
3383 if ((dev1 = hw->dev[1]))
3384 unregister_netdev(dev1);
3385 dev0 = hw->dev[0];
3386 unregister_netdev(dev0);
3387
46a60f2d
SH		 3388 skge_write32(hw, B0_IMSK, 0);
3389 skge_write16(hw, B0_LED, LED_STAT_OFF);
3390 skge_pci_clear(hw);
3391 skge_write8(hw, B0_CTST, CS_RST_SET);
3392
baef58b1
SH		 3393 tasklet_kill(&hw->ext_tasklet);
3394
3395 free_irq(pdev->irq, hw);
3396 pci_release_regions(pdev);
3397 pci_disable_device(pdev);
3398 if (dev1)
3399 free_netdev(dev1);
3400 free_netdev(dev0);
46a60f2d 3401
baef58b1
SH		 3402 iounmap(hw->regs);
3403 kfree(hw);
3404 pci_set_drvdata(pdev, NULL);
3405}
3406
3407#ifdef CONFIG_PM
2a569579 3408static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3409{
3410 struct skge_hw *hw = pci_get_drvdata(pdev);
3411 int i, wol = 0;
3412
95566065 3413 for (i = 0; i < 2; i++) {
baef58b1
SH		 3414 struct net_device *dev = hw->dev[i];
3415
3416 if (dev) {
3417 struct skge_port *skge = netdev_priv(dev);
3418 if (netif_running(dev)) {
3419 netif_carrier_off(dev);
46a60f2d
SH		 3420 if (skge->wol)
3421 netif_stop_queue(dev);
3422 else
3423 skge_down(dev);
baef58b1
SH		 3424 }
3425 netif_device_detach(dev);
3426 wol |= skge->wol;
3427 }
3428 }
3429
3430 pci_save_state(pdev);
2a569579 3431 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3432 pci_disable_device(pdev);
3433 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3434
3435 return 0;
3436}
3437
3438static int skge_resume(struct pci_dev *pdev)
3439{
3440 struct skge_hw *hw = pci_get_drvdata(pdev);
3441 int i;
3442
3443 pci_set_power_state(pdev, PCI_D0);
3444 pci_restore_state(pdev);
3445 pci_enable_wake(pdev, PCI_D0, 0);
3446
3447 skge_reset(hw);
3448
95566065 3449 for (i = 0; i < 2; i++) {
baef58b1
SH		 3450 struct net_device *dev = hw->dev[i];
3451 if (dev) {
3452 netif_device_attach(dev);
edd702e8
SH		 3453 if (netif_running(dev) && skge_up(dev))
3454 dev_close(dev);
baef58b1
SH		 3455 }
3456 }
3457 return 0;
3458}
3459#endif
3460
3461static struct pci_driver skge_driver = {
3462 .name = DRV_NAME,
3463 .id_table = skge_id_table,
3464 .probe = skge_probe,
3465 .remove = __devexit_p(skge_remove),
3466#ifdef CONFIG_PM
3467 .suspend = skge_suspend,
3468 .resume = skge_resume,
3469#endif
3470};
3471
3472static int __init skge_init_module(void)
3473{
3474 return pci_module_init(&skge_driver);
3475}
3476
3477static void __exit skge_cleanup_module(void)
3478{
3479 pci_unregister_driver(&skge_driver);
3480}
3481
3482module_init(skge_init_module);
3483module_exit(skge_cleanup_module);
Clone of davem's net-next-2.6 tree