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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
[net-next-2.6.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
798b6b19 14 * the Free Software Foundation; either version 2 of the License.
baef58b1
SH		 15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
f15063cd
JP		 26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
14c85021 28#include <linux/in.h>
baef58b1
SH		 29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/if_vlan.h>
37#include <linux/ip.h>
38#include <linux/delay.h>
39#include <linux/crc32.h>
4075400b 40#include <linux/dma-mapping.h>
678aa1f6 41#include <linux/debugfs.h>
d43c36dc 42#include <linux/sched.h>
678aa1f6 43#include <linux/seq_file.h>
2cd8e5d3 44#include <linux/mii.h>
5a0e3ad6 45#include <linux/slab.h>
392bd0cb 46#include <linux/dmi.h>
baef58b1
SH		 47#include <asm/irq.h>
48
49#include "skge.h"
50
51#define DRV_NAME "skge"
bf9f56d5 52#define DRV_VERSION "1.13"
baef58b1
SH		 53
54#define DEFAULT_TX_RING_SIZE 128
55#define DEFAULT_RX_RING_SIZE 512
56#define MAX_TX_RING_SIZE 1024
9db96479 57#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
baef58b1 58#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 59#define RX_COPY_THRESHOLD 128
60#define RX_BUF_SIZE 1536
baef58b1
SH		 61#define PHY_RETRIES 1000
62#define ETH_JUMBO_MTU 9000
63#define TX_WATCHDOG (5 * HZ)
64#define NAPI_WEIGHT 64
6abebb53 65#define BLINK_MS 250
501fb72d 66#define LINK_HZ HZ
baef58b1 67
afa151b9
SH		 68#define SKGE_EEPROM_MAGIC 0x9933aabb
69
70
baef58b1 71MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
65ebe634 72MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
baef58b1
SH		 73MODULE_LICENSE("GPL");
74MODULE_VERSION(DRV_VERSION);
75
67777f9b
JP		 76static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
77 NETIF_MSG_LINK | NETIF_MSG_IFUP |
78 NETIF_MSG_IFDOWN);
baef58b1
SH		 79
80static int debug = -1; /* defaults above */
81module_param(debug, int, 0);
82MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
83
a3aa1884 84static DEFINE_PCI_DEVICE_TABLE(skge_id_table) = {
275834d1
SH		 85 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
86 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
87 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
88 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
f19841f5 89 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
2d2a3871 90 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
275834d1
SH		 91 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
92 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
93 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 94 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
f19841f5 95 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
baef58b1
SH		 96 { 0 }
97};
98MODULE_DEVICE_TABLE(pci, skge_id_table);
99
100static int skge_up(struct net_device *dev);
101static int skge_down(struct net_device *dev);
ee294dcd 102static void skge_phy_reset(struct skge_port *skge);
513f533e 103static void skge_tx_clean(struct net_device *dev);
2cd8e5d3
SH		 104static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
105static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 106static void genesis_get_stats(struct skge_port *skge, u64 *data);
107static void yukon_get_stats(struct skge_port *skge, u64 *data);
108static void yukon_init(struct skge_hw *hw, int port);
baef58b1 109static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 110static void genesis_link_up(struct skge_port *skge);
f80d032b 111static void skge_set_multicast(struct net_device *dev);
baef58b1 112
7e676d91 113/* Avoid conditionals by using array */
baef58b1
SH		 114static const int txqaddr[] = { Q_XA1, Q_XA2 };
115static const int rxqaddr[] = { Q_R1, Q_R2 };
116static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
117static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
4ebabfcb
SH		 118static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
119static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1 120
baef58b1
SH		 121static int skge_get_regs_len(struct net_device *dev)
122{
c3f8be96 123 return 0x4000;
baef58b1
SH		 124}
125
126/*
c3f8be96
SH		 127 * Returns copy of whole control register region
128 * Note: skip RAM address register because accessing it will
129 * cause bus hangs!
baef58b1
SH		 130 */
131static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
132 void *p)
133{
134 const struct skge_port *skge = netdev_priv(dev);
baef58b1 135 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 136
137 regs->version = 1;
c3f8be96
SH		 138 memset(p, 0, regs->len);
139 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 140
c3f8be96
SH		 141 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
142 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 143}
144
8f3f8193 145/* Wake on Lan only supported on Yukon chips with rev 1 or above */
a504e64a 146static u32 wol_supported(const struct skge_hw *hw)
baef58b1 147{
d17ecb23 148 if (hw->chip_id == CHIP_ID_GENESIS)
a504e64a 149 return 0;
d17ecb23
SH		 150
151 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
152 return 0;
153
154 return WAKE_MAGIC | WAKE_PHY;
a504e64a
SH		 155}
156
a504e64a
SH		 157static void skge_wol_init(struct skge_port *skge)
158{
159 struct skge_hw *hw = skge->hw;
160 int port = skge->port;
692412b3 161 u16 ctrl;
a504e64a 162
a504e64a
SH		 163 skge_write16(hw, B0_CTST, CS_RST_CLR);
164 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
165
692412b3
SH		 166 /* Turn on Vaux */
167 skge_write8(hw, B0_POWER_CTRL,
168 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
a504e64a 169
692412b3
SH		 170 /* WA code for COMA mode -- clear PHY reset */
171 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
172 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
173 u32 reg = skge_read32(hw, B2_GP_IO);
174 reg |= GP_DIR_9;
175 reg &= ~GP_IO_9;
176 skge_write32(hw, B2_GP_IO, reg);
177 }
a504e64a 178
692412b3
SH		 179 skge_write32(hw, SK_REG(port, GPHY_CTRL),
180 GPC_DIS_SLEEP |
181 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
182 GPC_ANEG_1 | GPC_RST_SET);
a504e64a 183
692412b3
SH		 184 skge_write32(hw, SK_REG(port, GPHY_CTRL),
185 GPC_DIS_SLEEP |
186 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
187 GPC_ANEG_1 | GPC_RST_CLR);
188
189 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
190
191 /* Force to 10/100 skge_reset will re-enable on resume */
192 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
67777f9b
JP		 193 (PHY_AN_100FULL | PHY_AN_100HALF |
194 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
692412b3
SH		 195 /* no 1000 HD/FD */
196 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
197 gm_phy_write(hw, port, PHY_MARV_CTRL,
198 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
199 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
a504e64a 200
a504e64a
SH		 201
202 /* Set GMAC to no flow control and auto update for speed/duplex */
203 gma_write16(hw, port, GM_GP_CTRL,
204 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
205 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
206
207 /* Set WOL address */
208 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
209 skge->netdev->dev_addr, ETH_ALEN);
210
211 /* Turn on appropriate WOL control bits */
212 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
213 ctrl = 0;
214 if (skge->wol & WAKE_PHY)
215 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
216 else
217 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
218
219 if (skge->wol & WAKE_MAGIC)
220 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
221 else
a419aef8 222 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
a504e64a
SH		 223
224 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
225 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
226
227 /* block receiver */
228 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 229}
230
231static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
232{
233 struct skge_port *skge = netdev_priv(dev);
234
a504e64a
SH		 235 wol->supported = wol_supported(skge->hw);
236 wol->wolopts = skge->wol;
baef58b1
SH		 237}
238
239static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
240{
241 struct skge_port *skge = netdev_priv(dev);
242 struct skge_hw *hw = skge->hw;
243
8e95a202
JP		 244 if ((wol->wolopts & ~wol_supported(hw)) ||
245 !device_can_wakeup(&hw->pdev->dev))
baef58b1
SH		 246 return -EOPNOTSUPP;
247
a504e64a 248 skge->wol = wol->wolopts;
5177b324
RW		 249
250 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
251
baef58b1
SH		 252 return 0;
253}
254
8f3f8193
SH		 255/* Determine supported/advertised modes based on hardware.
256 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 257 */
258static u32 skge_supported_modes(const struct skge_hw *hw)
259{
260 u32 supported;
261
5e1705dd 262 if (hw->copper) {
67777f9b
JP		 263 supported = (SUPPORTED_10baseT_Half |
264 SUPPORTED_10baseT_Full |
265 SUPPORTED_100baseT_Half |
266 SUPPORTED_100baseT_Full |
267 SUPPORTED_1000baseT_Half |
268 SUPPORTED_1000baseT_Full |
269 SUPPORTED_Autoneg |
270 SUPPORTED_TP);
31b619c5
SH		 271
272 if (hw->chip_id == CHIP_ID_GENESIS)
67777f9b
JP		 273 supported &= ~(SUPPORTED_10baseT_Half |
274 SUPPORTED_10baseT_Full |
275 SUPPORTED_100baseT_Half |
276 SUPPORTED_100baseT_Full);
31b619c5
SH		 277
278 else if (hw->chip_id == CHIP_ID_YUKON)
279 supported &= ~SUPPORTED_1000baseT_Half;
280 } else
67777f9b
JP		 281 supported = (SUPPORTED_1000baseT_Full |
282 SUPPORTED_1000baseT_Half |
283 SUPPORTED_FIBRE |
284 SUPPORTED_Autoneg);
31b619c5
SH		 285
286 return supported;
287}
baef58b1
SH		 288
289static int skge_get_settings(struct net_device *dev,
290 struct ethtool_cmd *ecmd)
291{
292 struct skge_port *skge = netdev_priv(dev);
293 struct skge_hw *hw = skge->hw;
294
295 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 296 ecmd->supported = skge_supported_modes(hw);
baef58b1 297
5e1705dd 298 if (hw->copper) {
baef58b1
SH		 299 ecmd->port = PORT_TP;
300 ecmd->phy_address = hw->phy_addr;
31b619c5 301 } else
baef58b1 302 ecmd->port = PORT_FIBRE;
baef58b1
SH		 303
304 ecmd->advertising = skge->advertising;
305 ecmd->autoneg = skge->autoneg;
306 ecmd->speed = skge->speed;
307 ecmd->duplex = skge->duplex;
308 return 0;
309}
310
baef58b1
SH		 311static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
312{
313 struct skge_port *skge = netdev_priv(dev);
314 const struct skge_hw *hw = skge->hw;
31b619c5 315 u32 supported = skge_supported_modes(hw);
9ac1353f 316 int err = 0;
baef58b1
SH		 317
318 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 319 ecmd->advertising = supported;
320 skge->duplex = -1;
321 skge->speed = -1;
baef58b1 322 } else {
31b619c5
SH		 323 u32 setting;
324
2c668514 325 switch (ecmd->speed) {
baef58b1 326 case SPEED_1000:
31b619c5
SH		 327 if (ecmd->duplex == DUPLEX_FULL)
328 setting = SUPPORTED_1000baseT_Full;
329 else if (ecmd->duplex == DUPLEX_HALF)
330 setting = SUPPORTED_1000baseT_Half;
331 else
332 return -EINVAL;
baef58b1
SH		 333 break;
334 case SPEED_100:
31b619c5
SH		 335 if (ecmd->duplex == DUPLEX_FULL)
336 setting = SUPPORTED_100baseT_Full;
337 else if (ecmd->duplex == DUPLEX_HALF)
338 setting = SUPPORTED_100baseT_Half;
339 else
340 return -EINVAL;
341 break;
342
baef58b1 343 case SPEED_10:
31b619c5
SH		 344 if (ecmd->duplex == DUPLEX_FULL)
345 setting = SUPPORTED_10baseT_Full;
346 else if (ecmd->duplex == DUPLEX_HALF)
347 setting = SUPPORTED_10baseT_Half;
348 else
baef58b1
SH		 349 return -EINVAL;
350 break;
351 default:
352 return -EINVAL;
353 }
31b619c5
SH		 354
355 if ((setting & supported) == 0)
356 return -EINVAL;
357
358 skge->speed = ecmd->speed;
359 skge->duplex = ecmd->duplex;
baef58b1
SH		 360 }
361
362 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 363 skge->advertising = ecmd->advertising;
364
9ac1353f
XZ		 365 if (netif_running(dev)) {
366 skge_down(dev);
367 err = skge_up(dev);
368 if (err) {
369 dev_close(dev);
370 return err;
371 }
372 }
ee294dcd 373
67777f9b 374 return 0;
baef58b1
SH		 375}
376
377static void skge_get_drvinfo(struct net_device *dev,
378 struct ethtool_drvinfo *info)
379{
380 struct skge_port *skge = netdev_priv(dev);
381
382 strcpy(info->driver, DRV_NAME);
383 strcpy(info->version, DRV_VERSION);
384 strcpy(info->fw_version, "N/A");
385 strcpy(info->bus_info, pci_name(skge->hw->pdev));
386}
387
388static const struct skge_stat {
389 char name[ETH_GSTRING_LEN];
390 u16 xmac_offset;
391 u16 gma_offset;
392} skge_stats[] = {
393 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
394 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
395
396 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
397 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
398 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
399 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
400 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
401 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
402 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
403 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
404
405 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
406 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
407 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
408 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
409 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
410 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
411
412 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
413 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
414 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
415 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
416 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
417};
418
b9f2c044 419static int skge_get_sset_count(struct net_device *dev, int sset)
baef58b1 420{
b9f2c044
JG		 421 switch (sset) {
422 case ETH_SS_STATS:
423 return ARRAY_SIZE(skge_stats);
424 default:
425 return -EOPNOTSUPP;
426 }
baef58b1
SH		 427}
428
429static void skge_get_ethtool_stats(struct net_device *dev,
430 struct ethtool_stats *stats, u64 *data)
431{
432 struct skge_port *skge = netdev_priv(dev);
433
434 if (skge->hw->chip_id == CHIP_ID_GENESIS)
435 genesis_get_stats(skge, data);
436 else
437 yukon_get_stats(skge, data);
438}
439
440/* Use hardware MIB variables for critical path statistics and
441 * transmit feedback not reported at interrupt.
442 * Other errors are accounted for in interrupt handler.
443 */
444static struct net_device_stats *skge_get_stats(struct net_device *dev)
445{
446 struct skge_port *skge = netdev_priv(dev);
447 u64 data[ARRAY_SIZE(skge_stats)];
448
449 if (skge->hw->chip_id == CHIP_ID_GENESIS)
450 genesis_get_stats(skge, data);
451 else
452 yukon_get_stats(skge, data);
453
da00772f
SH		 454 dev->stats.tx_bytes = data[0];
455 dev->stats.rx_bytes = data[1];
456 dev->stats.tx_packets = data[2] + data[4] + data[6];
457 dev->stats.rx_packets = data[3] + data[5] + data[7];
458 dev->stats.multicast = data[3] + data[5];
459 dev->stats.collisions = data[10];
460 dev->stats.tx_aborted_errors = data[12];
baef58b1 461
da00772f 462 return &dev->stats;
baef58b1
SH		 463}
464
465static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
466{
467 int i;
468
95566065 469 switch (stringset) {
baef58b1
SH		 470 case ETH_SS_STATS:
471 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
472 memcpy(data + i * ETH_GSTRING_LEN,
473 skge_stats[i].name, ETH_GSTRING_LEN);
474 break;
475 }
476}
477
478static void skge_get_ring_param(struct net_device *dev,
479 struct ethtool_ringparam *p)
480{
481 struct skge_port *skge = netdev_priv(dev);
482
483 p->rx_max_pending = MAX_RX_RING_SIZE;
484 p->tx_max_pending = MAX_TX_RING_SIZE;
485 p->rx_mini_max_pending = 0;
486 p->rx_jumbo_max_pending = 0;
487
488 p->rx_pending = skge->rx_ring.count;
489 p->tx_pending = skge->tx_ring.count;
490 p->rx_mini_pending = 0;
491 p->rx_jumbo_pending = 0;
492}
493
494static int skge_set_ring_param(struct net_device *dev,
495 struct ethtool_ringparam *p)
496{
497 struct skge_port *skge = netdev_priv(dev);
e824b3eb 498 int err = 0;
baef58b1
SH		 499
500 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
9db96479 501 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
baef58b1
SH		 502 return -EINVAL;
503
504 skge->rx_ring.count = p->rx_pending;
505 skge->tx_ring.count = p->tx_pending;
506
507 if (netif_running(dev)) {
508 skge_down(dev);
3b8bb472
SH		 509 err = skge_up(dev);
510 if (err)
511 dev_close(dev);
baef58b1
SH		 512 }
513
e824b3eb 514 return err;
baef58b1
SH		 515}
516
517static u32 skge_get_msglevel(struct net_device *netdev)
518{
519 struct skge_port *skge = netdev_priv(netdev);
520 return skge->msg_enable;
521}
522
523static void skge_set_msglevel(struct net_device *netdev, u32 value)
524{
525 struct skge_port *skge = netdev_priv(netdev);
526 skge->msg_enable = value;
527}
528
529static int skge_nway_reset(struct net_device *dev)
530{
531 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 532
533 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
534 return -EINVAL;
535
ee294dcd 536 skge_phy_reset(skge);
baef58b1
SH		 537 return 0;
538}
539
540static int skge_set_sg(struct net_device *dev, u32 data)
541{
542 struct skge_port *skge = netdev_priv(dev);
543 struct skge_hw *hw = skge->hw;
544
545 if (hw->chip_id == CHIP_ID_GENESIS && data)
546 return -EOPNOTSUPP;
547 return ethtool_op_set_sg(dev, data);
548}
549
550static int skge_set_tx_csum(struct net_device *dev, u32 data)
551{
552 struct skge_port *skge = netdev_priv(dev);
553 struct skge_hw *hw = skge->hw;
554
555 if (hw->chip_id == CHIP_ID_GENESIS && data)
556 return -EOPNOTSUPP;
557
558 return ethtool_op_set_tx_csum(dev, data);
559}
560
561static u32 skge_get_rx_csum(struct net_device *dev)
562{
563 struct skge_port *skge = netdev_priv(dev);
564
565 return skge->rx_csum;
566}
567
568/* Only Yukon supports checksum offload. */
569static int skge_set_rx_csum(struct net_device *dev, u32 data)
570{
571 struct skge_port *skge = netdev_priv(dev);
572
573 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
574 return -EOPNOTSUPP;
575
576 skge->rx_csum = data;
577 return 0;
578}
579
baef58b1
SH		 580static void skge_get_pauseparam(struct net_device *dev,
581 struct ethtool_pauseparam *ecmd)
582{
583 struct skge_port *skge = netdev_priv(dev);
584
8e95a202
JP		 585 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
586 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
587 ecmd->tx_pause = (ecmd->rx_pause ||
588 (skge->flow_control == FLOW_MODE_LOC_SEND));
baef58b1 589
5d5c8e03 590 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
baef58b1
SH		 591}
592
593static int skge_set_pauseparam(struct net_device *dev,
594 struct ethtool_pauseparam *ecmd)
595{
596 struct skge_port *skge = netdev_priv(dev);
5d5c8e03 597 struct ethtool_pauseparam old;
9ac1353f 598 int err = 0;
baef58b1 599
5d5c8e03
SH		 600 skge_get_pauseparam(dev, &old);
601
602 if (ecmd->autoneg != old.autoneg)
603 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
604 else {
605 if (ecmd->rx_pause && ecmd->tx_pause)
606 skge->flow_control = FLOW_MODE_SYMMETRIC;
607 else if (ecmd->rx_pause && !ecmd->tx_pause)
608 skge->flow_control = FLOW_MODE_SYM_OR_REM;
609 else if (!ecmd->rx_pause && ecmd->tx_pause)
610 skge->flow_control = FLOW_MODE_LOC_SEND;
611 else
612 skge->flow_control = FLOW_MODE_NONE;
613 }
baef58b1 614
9ac1353f
XZ		 615 if (netif_running(dev)) {
616 skge_down(dev);
617 err = skge_up(dev);
618 if (err) {
619 dev_close(dev);
620 return err;
621 }
622 }
5d5c8e03 623
baef58b1
SH		 624 return 0;
625}
626
627/* Chip internal frequency for clock calculations */
628static inline u32 hwkhz(const struct skge_hw *hw)
629{
187ff3b8 630 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
baef58b1
SH		 631}
632
8f3f8193 633/* Chip HZ to microseconds */
baef58b1
SH		 634static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
635{
636 return (ticks * 1000) / hwkhz(hw);
637}
638
8f3f8193 639/* Microseconds to chip HZ */
baef58b1
SH		 640static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
641{
642 return hwkhz(hw) * usec / 1000;
643}
644
645static int skge_get_coalesce(struct net_device *dev,
646 struct ethtool_coalesce *ecmd)
647{
648 struct skge_port *skge = netdev_priv(dev);
649 struct skge_hw *hw = skge->hw;
650 int port = skge->port;
651
652 ecmd->rx_coalesce_usecs = 0;
653 ecmd->tx_coalesce_usecs = 0;
654
655 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
656 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
657 u32 msk = skge_read32(hw, B2_IRQM_MSK);
658
659 if (msk & rxirqmask[port])
660 ecmd->rx_coalesce_usecs = delay;
661 if (msk & txirqmask[port])
662 ecmd->tx_coalesce_usecs = delay;
663 }
664
665 return 0;
666}
667
668/* Note: interrupt timer is per board, but can turn on/off per port */
669static int skge_set_coalesce(struct net_device *dev,
670 struct ethtool_coalesce *ecmd)
671{
672 struct skge_port *skge = netdev_priv(dev);
673 struct skge_hw *hw = skge->hw;
674 int port = skge->port;
675 u32 msk = skge_read32(hw, B2_IRQM_MSK);
676 u32 delay = 25;
677
678 if (ecmd->rx_coalesce_usecs == 0)
679 msk &= ~rxirqmask[port];
680 else if (ecmd->rx_coalesce_usecs < 25 ||
681 ecmd->rx_coalesce_usecs > 33333)
682 return -EINVAL;
683 else {
684 msk |= rxirqmask[port];
685 delay = ecmd->rx_coalesce_usecs;
686 }
687
688 if (ecmd->tx_coalesce_usecs == 0)
689 msk &= ~txirqmask[port];
690 else if (ecmd->tx_coalesce_usecs < 25 ||
691 ecmd->tx_coalesce_usecs > 33333)
692 return -EINVAL;
693 else {
694 msk |= txirqmask[port];
695 delay = min(delay, ecmd->rx_coalesce_usecs);
696 }
697
698 skge_write32(hw, B2_IRQM_MSK, msk);
699 if (msk == 0)
700 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
701 else {
702 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
703 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
704 }
705 return 0;
706}
707
6abebb53
SH		 708enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
709static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 710{
6abebb53
SH		 711 struct skge_hw *hw = skge->hw;
712 int port = skge->port;
713
9cbe330f 714 spin_lock_bh(&hw->phy_lock);
baef58b1 715 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 716 switch (mode) {
717 case LED_MODE_OFF:
64f6b64d
SH		 718 if (hw->phy_type == SK_PHY_BCOM)
719 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
720 else {
721 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
722 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
723 }
6abebb53
SH		 724 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
725 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
726 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
727 break;
baef58b1 728
6abebb53
SH		 729 case LED_MODE_ON:
730 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
731 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 732
6abebb53
SH		 733 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
734 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 735
6abebb53 736 break;
baef58b1 737
6abebb53
SH		 738 case LED_MODE_TST:
739 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
740 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
741 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 742
64f6b64d
SH		 743 if (hw->phy_type == SK_PHY_BCOM)
744 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
745 else {
746 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
747 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
748 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
749 }
750
6abebb53 751 }
baef58b1 752 } else {
6abebb53
SH		 753 switch (mode) {
754 case LED_MODE_OFF:
755 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
756 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
757 PHY_M_LED_MO_DUP(MO_LED_OFF) |
758 PHY_M_LED_MO_10(MO_LED_OFF) |
759 PHY_M_LED_MO_100(MO_LED_OFF) |
760 PHY_M_LED_MO_1000(MO_LED_OFF) |
761 PHY_M_LED_MO_RX(MO_LED_OFF));
762 break;
763 case LED_MODE_ON:
764 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
765 PHY_M_LED_PULS_DUR(PULS_170MS) |
766 PHY_M_LED_BLINK_RT(BLINK_84MS) |
767 PHY_M_LEDC_TX_CTRL |
768 PHY_M_LEDC_DP_CTRL);
46a60f2d 769
6abebb53
SH		 770 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
771 PHY_M_LED_MO_RX(MO_LED_OFF) |
772 (skge->speed == SPEED_100 ?
773 PHY_M_LED_MO_100(MO_LED_ON) : 0));
774 break;
775 case LED_MODE_TST:
776 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
777 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
778 PHY_M_LED_MO_DUP(MO_LED_ON) |
779 PHY_M_LED_MO_10(MO_LED_ON) |
780 PHY_M_LED_MO_100(MO_LED_ON) |
781 PHY_M_LED_MO_1000(MO_LED_ON) |
782 PHY_M_LED_MO_RX(MO_LED_ON));
783 }
baef58b1 784 }
9cbe330f 785 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 786}
787
788/* blink LED's for finding board */
789static int skge_phys_id(struct net_device *dev, u32 data)
790{
791 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 792 unsigned long ms;
793 enum led_mode mode = LED_MODE_TST;
baef58b1 794
95566065 795 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 796 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
797 else
798 ms = data * 1000;
baef58b1 799
6abebb53
SH		 800 while (ms > 0) {
801 skge_led(skge, mode);
802 mode ^= LED_MODE_TST;
baef58b1 803
6abebb53
SH		 804 if (msleep_interruptible(BLINK_MS))
805 break;
806 ms -= BLINK_MS;
807 }
baef58b1 808
6abebb53
SH		 809 /* back to regular LED state */
810 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 811
812 return 0;
813}
814
afa151b9
SH		 815static int skge_get_eeprom_len(struct net_device *dev)
816{
817 struct skge_port *skge = netdev_priv(dev);
818 u32 reg2;
819
820 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
67777f9b 821 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
afa151b9
SH		 822}
823
824static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
825{
826 u32 val;
827
828 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
829
830 do {
831 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
832 } while (!(offset & PCI_VPD_ADDR_F));
833
834 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
835 return val;
836}
837
838static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
839{
840 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
841 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
842 offset | PCI_VPD_ADDR_F);
843
844 do {
845 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
846 } while (offset & PCI_VPD_ADDR_F);
847}
848
849static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
850 u8 *data)
851{
852 struct skge_port *skge = netdev_priv(dev);
853 struct pci_dev *pdev = skge->hw->pdev;
854 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
855 int length = eeprom->len;
856 u16 offset = eeprom->offset;
857
858 if (!cap)
859 return -EINVAL;
860
861 eeprom->magic = SKGE_EEPROM_MAGIC;
862
863 while (length > 0) {
864 u32 val = skge_vpd_read(pdev, cap, offset);
865 int n = min_t(int, length, sizeof(val));
866
867 memcpy(data, &val, n);
868 length -= n;
869 data += n;
870 offset += n;
871 }
872 return 0;
873}
874
875static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
876 u8 *data)
877{
878 struct skge_port *skge = netdev_priv(dev);
879 struct pci_dev *pdev = skge->hw->pdev;
880 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
881 int length = eeprom->len;
882 u16 offset = eeprom->offset;
883
884 if (!cap)
885 return -EINVAL;
886
887 if (eeprom->magic != SKGE_EEPROM_MAGIC)
888 return -EINVAL;
889
890 while (length > 0) {
891 u32 val;
892 int n = min_t(int, length, sizeof(val));
893
894 if (n < sizeof(val))
895 val = skge_vpd_read(pdev, cap, offset);
896 memcpy(&val, data, n);
897
898 skge_vpd_write(pdev, cap, offset, val);
899
900 length -= n;
901 data += n;
902 offset += n;
903 }
904 return 0;
905}
906
7282d491 907static const struct ethtool_ops skge_ethtool_ops = {
baef58b1
SH		 908 .get_settings = skge_get_settings,
909 .set_settings = skge_set_settings,
910 .get_drvinfo = skge_get_drvinfo,
911 .get_regs_len = skge_get_regs_len,
912 .get_regs = skge_get_regs,
913 .get_wol = skge_get_wol,
914 .set_wol = skge_set_wol,
915 .get_msglevel = skge_get_msglevel,
916 .set_msglevel = skge_set_msglevel,
917 .nway_reset = skge_nway_reset,
918 .get_link = ethtool_op_get_link,
afa151b9
SH		 919 .get_eeprom_len = skge_get_eeprom_len,
920 .get_eeprom = skge_get_eeprom,
921 .set_eeprom = skge_set_eeprom,
baef58b1
SH		 922 .get_ringparam = skge_get_ring_param,
923 .set_ringparam = skge_set_ring_param,
924 .get_pauseparam = skge_get_pauseparam,
925 .set_pauseparam = skge_set_pauseparam,
926 .get_coalesce = skge_get_coalesce,
927 .set_coalesce = skge_set_coalesce,
baef58b1 928 .set_sg = skge_set_sg,
baef58b1
SH		 929 .set_tx_csum = skge_set_tx_csum,
930 .get_rx_csum = skge_get_rx_csum,
931 .set_rx_csum = skge_set_rx_csum,
932 .get_strings = skge_get_strings,
933 .phys_id = skge_phys_id,
b9f2c044 934 .get_sset_count = skge_get_sset_count,
baef58b1
SH		 935 .get_ethtool_stats = skge_get_ethtool_stats,
936};
937
938/*
939 * Allocate ring elements and chain them together
940 * One-to-one association of board descriptors with ring elements
941 */
c3da1447 942static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 943{
944 struct skge_tx_desc *d;
945 struct skge_element *e;
946 int i;
947
cd861280 948 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
baef58b1
SH		 949 if (!ring->start)
950 return -ENOMEM;
951
952 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
953 e->desc = d;
954 if (i == ring->count - 1) {
955 e->next = ring->start;
956 d->next_offset = base;
957 } else {
958 e->next = e + 1;
959 d->next_offset = base + (i+1) * sizeof(*d);
960 }
961 }
962 ring->to_use = ring->to_clean = ring->start;
963
964 return 0;
965}
966
19a33d4e
SH		 967/* Allocate and setup a new buffer for receiving */
968static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
969 struct sk_buff *skb, unsigned int bufsize)
970{
971 struct skge_rx_desc *rd = e->desc;
972 u64 map;
baef58b1
SH		 973
974 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
975 PCI_DMA_FROMDEVICE);
976
977 rd->dma_lo = map;
978 rd->dma_hi = map >> 32;
979 e->skb = skb;
980 rd->csum1_start = ETH_HLEN;
981 rd->csum2_start = ETH_HLEN;
982 rd->csum1 = 0;
983 rd->csum2 = 0;
984
985 wmb();
986
987 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
10fc51b9
FT		 988 dma_unmap_addr_set(e, mapaddr, map);
989 dma_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 990}
991
19a33d4e
SH		 992/* Resume receiving using existing skb,
993 * Note: DMA address is not changed by chip.
994 * MTU not changed while receiver active.
995 */
5a011447 996static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 997{
998 struct skge_rx_desc *rd = e->desc;
999
1000 rd->csum2 = 0;
1001 rd->csum2_start = ETH_HLEN;
1002
1003 wmb();
1004
1005 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
1006}
1007
1008
1009/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 1010static void skge_rx_clean(struct skge_port *skge)
1011{
1012 struct skge_hw *hw = skge->hw;
1013 struct skge_ring *ring = &skge->rx_ring;
1014 struct skge_element *e;
1015
19a33d4e
SH		 1016 e = ring->start;
1017 do {
baef58b1
SH		 1018 struct skge_rx_desc *rd = e->desc;
1019 rd->control = 0;
19a33d4e
SH		 1020 if (e->skb) {
1021 pci_unmap_single(hw->pdev,
10fc51b9
FT		 1022 dma_unmap_addr(e, mapaddr),
1023 dma_unmap_len(e, maplen),
19a33d4e
SH		 1024 PCI_DMA_FROMDEVICE);
1025 dev_kfree_skb(e->skb);
1026 e->skb = NULL;
1027 }
1028 } while ((e = e->next) != ring->start);
baef58b1
SH		 1029}
1030
19a33d4e 1031
baef58b1 1032/* Allocate buffers for receive ring
19a33d4e 1033 * For receive: to_clean is next received frame.
baef58b1 1034 */
c54f9765 1035static int skge_rx_fill(struct net_device *dev)
baef58b1 1036{
c54f9765 1037 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 1038 struct skge_ring *ring = &skge->rx_ring;
1039 struct skge_element *e;
baef58b1 1040
19a33d4e
SH		 1041 e = ring->start;
1042 do {
383181ac 1043 struct sk_buff *skb;
baef58b1 1044
c54f9765
SH		 1045 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1046 GFP_KERNEL);
19a33d4e
SH		 1047 if (!skb)
1048 return -ENOMEM;
1049
383181ac
SH		 1050 skb_reserve(skb, NET_IP_ALIGN);
1051 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
67777f9b 1052 } while ((e = e->next) != ring->start);
baef58b1 1053
19a33d4e
SH		 1054 ring->to_clean = ring->start;
1055 return 0;
baef58b1
SH		 1056}
1057
5d5c8e03
SH		 1058static const char *skge_pause(enum pause_status status)
1059{
67777f9b 1060 switch (status) {
5d5c8e03
SH		 1061 case FLOW_STAT_NONE:
1062 return "none";
1063 case FLOW_STAT_REM_SEND:
1064 return "rx only";
1065 case FLOW_STAT_LOC_SEND:
1066 return "tx_only";
1067 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1068 return "both";
1069 default:
1070 return "indeterminated";
1071 }
1072}
1073
1074
baef58b1
SH		 1075static void skge_link_up(struct skge_port *skge)
1076{
46a60f2d 1077 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 1078 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1079
baef58b1 1080 netif_carrier_on(skge->netdev);
29b4e886 1081 netif_wake_queue(skge->netdev);
baef58b1 1082
d707204c
JP		 1083 netif_info(skge, link, skge->netdev,
1084 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1085 skge->speed,
1086 skge->duplex == DUPLEX_FULL ? "full" : "half",
1087 skge_pause(skge->flow_status));
baef58b1
SH		 1088}
1089
1090static void skge_link_down(struct skge_port *skge)
1091{
54cfb5aa 1092 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 1093 netif_carrier_off(skge->netdev);
1094 netif_stop_queue(skge->netdev);
1095
d707204c 1096 netif_info(skge, link, skge->netdev, "Link is down\n");
baef58b1
SH		 1097}
1098
a1bc9b87
SH		 1099
1100static void xm_link_down(struct skge_hw *hw, int port)
1101{
1102 struct net_device *dev = hw->dev[port];
1103 struct skge_port *skge = netdev_priv(dev);
a1bc9b87 1104
501fb72d 1105 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
a1bc9b87 1106
a1bc9b87
SH		 1107 if (netif_carrier_ok(dev))
1108 skge_link_down(skge);
1109}
1110
2cd8e5d3 1111static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 1112{
1113 int i;
baef58b1 1114
6b0c1480 1115 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 1116 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 1117
64f6b64d
SH		 1118 if (hw->phy_type == SK_PHY_XMAC)
1119 goto ready;
1120
89bf5f23 1121 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 1122 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 1123 goto ready;
0781191c 1124 udelay(1);
baef58b1
SH		 1125 }
1126
2cd8e5d3 1127 return -ETIMEDOUT;
89bf5f23 1128 ready:
2cd8e5d3 1129 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 1130
2cd8e5d3
SH		 1131 return 0;
1132}
1133
1134static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1135{
1136 u16 v = 0;
1137 if (__xm_phy_read(hw, port, reg, &v))
f15063cd 1138 pr_warning("%s: phy read timed out\n", hw->dev[port]->name);
baef58b1
SH		 1139 return v;
1140}
1141
2cd8e5d3 1142static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1143{
1144 int i;
1145
6b0c1480 1146 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 1147 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 1148 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 1149 goto ready;
89bf5f23 1150 udelay(1);
baef58b1 1151 }
2cd8e5d3 1152 return -EIO;
baef58b1
SH		 1153
1154 ready:
6b0c1480 1155 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 1156 for (i = 0; i < PHY_RETRIES; i++) {
1157 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1158 return 0;
1159 udelay(1);
1160 }
1161 return -ETIMEDOUT;
baef58b1
SH		 1162}
1163
1164static void genesis_init(struct skge_hw *hw)
1165{
1166 /* set blink source counter */
1167 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1168 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1169
1170 /* configure mac arbiter */
1171 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1172
1173 /* configure mac arbiter timeout values */
1174 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1175 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1176 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1177 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1178
1179 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1180 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1181 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1182 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1183
1184 /* configure packet arbiter timeout */
1185 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1186 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1187 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1188 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1189 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1190}
1191
1192static void genesis_reset(struct skge_hw *hw, int port)
1193{
45bada65 1194 const u8 zero[8] = { 0 };
21d7f677 1195 u32 reg;
baef58b1 1196
46a60f2d
SH		 1197 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1198
baef58b1 1199 /* reset the statistics module */
6b0c1480 1200 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
501fb72d 1201 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
6b0c1480
SH		 1202 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1203 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1204 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 1205
89bf5f23 1206 /* disable Broadcom PHY IRQ */
64f6b64d
SH		 1207 if (hw->phy_type == SK_PHY_BCOM)
1208 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 1209
45bada65 1210 xm_outhash(hw, port, XM_HSM, zero);
21d7f677
SH		 1211
1212 /* Flush TX and RX fifo */
1213 reg = xm_read32(hw, port, XM_MODE);
1214 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1215 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
baef58b1
SH		 1216}
1217
1218
45bada65
SH		 1219/* Convert mode to MII values */
1220static const u16 phy_pause_map[] = {
1221 [FLOW_MODE_NONE] = 0,
1222 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1223 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
5d5c8e03 1224 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
45bada65
SH		 1225};
1226
4b67be99
SH		 1227/* special defines for FIBER (88E1011S only) */
1228static const u16 fiber_pause_map[] = {
1229 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1230 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1231 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
5d5c8e03 1232 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
4b67be99
SH		 1233};
1234
45bada65
SH		 1235
1236/* Check status of Broadcom phy link */
1237static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 1238{
45bada65
SH		 1239 struct net_device *dev = hw->dev[port];
1240 struct skge_port *skge = netdev_priv(dev);
1241 u16 status;
1242
1243 /* read twice because of latch */
501fb72d 1244 xm_phy_read(hw, port, PHY_BCOM_STAT);
45bada65
SH		 1245 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1246
45bada65 1247 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1248 xm_link_down(hw, port);
64f6b64d
SH		 1249 return;
1250 }
45bada65 1251
64f6b64d
SH		 1252 if (skge->autoneg == AUTONEG_ENABLE) {
1253 u16 lpa, aux;
45bada65 1254
64f6b64d
SH		 1255 if (!(status & PHY_ST_AN_OVER))
1256 return;
45bada65 1257
64f6b64d
SH		 1258 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1259 if (lpa & PHY_B_AN_RF) {
f15063cd 1260 netdev_notice(dev, "remote fault\n");
64f6b64d
SH		 1261 return;
1262 }
45bada65 1263
64f6b64d
SH		 1264 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1265
1266 /* Check Duplex mismatch */
1267 switch (aux & PHY_B_AS_AN_RES_MSK) {
1268 case PHY_B_RES_1000FD:
1269 skge->duplex = DUPLEX_FULL;
1270 break;
1271 case PHY_B_RES_1000HD:
1272 skge->duplex = DUPLEX_HALF;
1273 break;
1274 default:
f15063cd 1275 netdev_notice(dev, "duplex mismatch\n");
64f6b64d 1276 return;
45bada65
SH		 1277 }
1278
64f6b64d
SH		 1279 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1280 switch (aux & PHY_B_AS_PAUSE_MSK) {
1281 case PHY_B_AS_PAUSE_MSK:
5d5c8e03 1282 skge->flow_status = FLOW_STAT_SYMMETRIC;
64f6b64d
SH		 1283 break;
1284 case PHY_B_AS_PRR:
5d5c8e03 1285 skge->flow_status = FLOW_STAT_REM_SEND;
64f6b64d
SH		 1286 break;
1287 case PHY_B_AS_PRT:
5d5c8e03 1288 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d
SH		 1289 break;
1290 default:
5d5c8e03 1291 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1292 }
1293 skge->speed = SPEED_1000;
45bada65 1294 }
64f6b64d
SH		 1295
1296 if (!netif_carrier_ok(dev))
1297 genesis_link_up(skge);
45bada65
SH		 1298}
1299
1300/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1301 * Phy on for 100 or 10Mbit operation
1302 */
64f6b64d 1303static void bcom_phy_init(struct skge_port *skge)
45bada65
SH		 1304{
1305 struct skge_hw *hw = skge->hw;
1306 int port = skge->port;
baef58b1 1307 int i;
45bada65 1308 u16 id1, r, ext, ctl;
baef58b1
SH		 1309
1310 /* magic workaround patterns for Broadcom */
1311 static const struct {
1312 u16 reg;
1313 u16 val;
1314 } A1hack[] = {
1315 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1316 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1317 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1318 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1319 }, C0hack[] = {
1320 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1321 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1322 };
1323
45bada65
SH		 1324 /* read Id from external PHY (all have the same address) */
1325 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1326
1327 /* Optimize MDIO transfer by suppressing preamble. */
1328 r = xm_read16(hw, port, XM_MMU_CMD);
1329 r |= XM_MMU_NO_PRE;
67777f9b 1330 xm_write16(hw, port, XM_MMU_CMD, r);
45bada65 1331
2c668514 1332 switch (id1) {
45bada65
SH		 1333 case PHY_BCOM_ID1_C0:
1334 /*
1335 * Workaround BCOM Errata for the C0 type.
1336 * Write magic patterns to reserved registers.
1337 */
1338 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1339 xm_phy_write(hw, port,
1340 C0hack[i].reg, C0hack[i].val);
1341
1342 break;
1343 case PHY_BCOM_ID1_A1:
1344 /*
1345 * Workaround BCOM Errata for the A1 type.
1346 * Write magic patterns to reserved registers.
1347 */
1348 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1349 xm_phy_write(hw, port,
1350 A1hack[i].reg, A1hack[i].val);
1351 break;
1352 }
1353
1354 /*
1355 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1356 * Disable Power Management after reset.
1357 */
1358 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1359 r |= PHY_B_AC_DIS_PM;
1360 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1361
1362 /* Dummy read */
1363 xm_read16(hw, port, XM_ISRC);
1364
1365 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1366 ctl = PHY_CT_SP1000; /* always 1000mbit */
1367
1368 if (skge->autoneg == AUTONEG_ENABLE) {
1369 /*
1370 * Workaround BCOM Errata #1 for the C5 type.
1371 * 1000Base-T Link Acquisition Failure in Slave Mode
1372 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1373 */
1374 u16 adv = PHY_B_1000C_RD;
1375 if (skge->advertising & ADVERTISED_1000baseT_Half)
1376 adv |= PHY_B_1000C_AHD;
1377 if (skge->advertising & ADVERTISED_1000baseT_Full)
1378 adv |= PHY_B_1000C_AFD;
1379 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1380
1381 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1382 } else {
1383 if (skge->duplex == DUPLEX_FULL)
1384 ctl |= PHY_CT_DUP_MD;
1385 /* Force to slave */
1386 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1387 }
1388
1389 /* Set autonegotiation pause parameters */
1390 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1391 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1392
1393 /* Handle Jumbo frames */
64f6b64d 1394 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
45bada65
SH		 1395 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1396 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1397
1398 ext |= PHY_B_PEC_HIGH_LA;
1399
1400 }
1401
1402 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1403 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1404
8f3f8193 1405 /* Use link status change interrupt */
45bada65 1406 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
64f6b64d 1407}
45bada65 1408
64f6b64d
SH		 1409static void xm_phy_init(struct skge_port *skge)
1410{
1411 struct skge_hw *hw = skge->hw;
1412 int port = skge->port;
1413 u16 ctrl = 0;
1414
1415 if (skge->autoneg == AUTONEG_ENABLE) {
1416 if (skge->advertising & ADVERTISED_1000baseT_Half)
1417 ctrl |= PHY_X_AN_HD;
1418 if (skge->advertising & ADVERTISED_1000baseT_Full)
1419 ctrl |= PHY_X_AN_FD;
1420
4b67be99 1421 ctrl |= fiber_pause_map[skge->flow_control];
64f6b64d
SH		 1422
1423 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1424
1425 /* Restart Auto-negotiation */
1426 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1427 } else {
1428 /* Set DuplexMode in Config register */
1429 if (skge->duplex == DUPLEX_FULL)
1430 ctrl |= PHY_CT_DUP_MD;
1431 /*
1432 * Do NOT enable Auto-negotiation here. This would hold
1433 * the link down because no IDLEs are transmitted
1434 */
1435 }
1436
1437 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1438
1439 /* Poll PHY for status changes */
9cbe330f 1440 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
64f6b64d
SH		 1441}
1442
501fb72d 1443static int xm_check_link(struct net_device *dev)
64f6b64d
SH		 1444{
1445 struct skge_port *skge = netdev_priv(dev);
1446 struct skge_hw *hw = skge->hw;
1447 int port = skge->port;
1448 u16 status;
1449
1450 /* read twice because of latch */
501fb72d 1451 xm_phy_read(hw, port, PHY_XMAC_STAT);
64f6b64d
SH		 1452 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1453
1454 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1455 xm_link_down(hw, port);
501fb72d 1456 return 0;
64f6b64d
SH		 1457 }
1458
1459 if (skge->autoneg == AUTONEG_ENABLE) {
1460 u16 lpa, res;
1461
1462 if (!(status & PHY_ST_AN_OVER))
501fb72d 1463 return 0;
64f6b64d
SH		 1464
1465 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1466 if (lpa & PHY_B_AN_RF) {
f15063cd 1467 netdev_notice(dev, "remote fault\n");
501fb72d 1468 return 0;
64f6b64d
SH		 1469 }
1470
1471 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1472
1473 /* Check Duplex mismatch */
1474 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1475 case PHY_X_RS_FD:
1476 skge->duplex = DUPLEX_FULL;
1477 break;
1478 case PHY_X_RS_HD:
1479 skge->duplex = DUPLEX_HALF;
1480 break;
1481 default:
f15063cd 1482 netdev_notice(dev, "duplex mismatch\n");
501fb72d 1483 return 0;
64f6b64d
SH		 1484 }
1485
1486 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
5d5c8e03
SH		 1487 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1488 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1489 (lpa & PHY_X_P_SYM_MD))
1490 skge->flow_status = FLOW_STAT_SYMMETRIC;
1491 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1492 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1493 /* Enable PAUSE receive, disable PAUSE transmit */
1494 skge->flow_status = FLOW_STAT_REM_SEND;
1495 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1496 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1497 /* Disable PAUSE receive, enable PAUSE transmit */
1498 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d 1499 else
5d5c8e03 1500 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1501
1502 skge->speed = SPEED_1000;
1503 }
1504
1505 if (!netif_carrier_ok(dev))
1506 genesis_link_up(skge);
501fb72d 1507 return 1;
64f6b64d
SH		 1508}
1509
1510/* Poll to check for link coming up.
501fb72d 1511 *
64f6b64d 1512 * Since internal PHY is wired to a level triggered pin, can't
501fb72d
SH		 1513 * get an interrupt when carrier is detected, need to poll for
1514 * link coming up.
64f6b64d 1515 */
9cbe330f 1516static void xm_link_timer(unsigned long arg)
64f6b64d 1517{
9cbe330f 1518 struct skge_port *skge = (struct skge_port *) arg;
c4028958 1519 struct net_device *dev = skge->netdev;
67777f9b 1520 struct skge_hw *hw = skge->hw;
64f6b64d 1521 int port = skge->port;
501fb72d
SH		 1522 int i;
1523 unsigned long flags;
64f6b64d
SH		 1524
1525 if (!netif_running(dev))
1526 return;
1527
501fb72d
SH		 1528 spin_lock_irqsave(&hw->phy_lock, flags);
1529
1530 /*
1531 * Verify that the link by checking GPIO register three times.
1532 * This pin has the signal from the link_sync pin connected to it.
1533 */
1534 for (i = 0; i < 3; i++) {
1535 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1536 goto link_down;
1537 }
1538
67777f9b 1539 /* Re-enable interrupt to detect link down */
501fb72d
SH		 1540 if (xm_check_link(dev)) {
1541 u16 msk = xm_read16(hw, port, XM_IMSK);
1542 msk &= ~XM_IS_INP_ASS;
1543 xm_write16(hw, port, XM_IMSK, msk);
64f6b64d 1544 xm_read16(hw, port, XM_ISRC);
64f6b64d 1545 } else {
501fb72d
SH		 1546link_down:
1547 mod_timer(&skge->link_timer,
1548 round_jiffies(jiffies + LINK_HZ));
64f6b64d 1549 }
501fb72d 1550 spin_unlock_irqrestore(&hw->phy_lock, flags);
45bada65
SH		 1551}
1552
1553static void genesis_mac_init(struct skge_hw *hw, int port)
1554{
1555 struct net_device *dev = hw->dev[port];
1556 struct skge_port *skge = netdev_priv(dev);
1557 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1558 int i;
1559 u32 r;
1560 const u8 zero[6] = { 0 };
1561
0781191c
SH		 1562 for (i = 0; i < 10; i++) {
1563 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1564 MFF_SET_MAC_RST);
1565 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1566 goto reset_ok;
1567 udelay(1);
1568 }
baef58b1 1569
f15063cd 1570 netdev_warn(dev, "genesis reset failed\n");
0781191c
SH		 1571
1572 reset_ok:
baef58b1 1573 /* Unreset the XMAC. */
6b0c1480 1574 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1575
1576 /*
1577 * Perform additional initialization for external PHYs,
1578 * namely for the 1000baseTX cards that use the XMAC's
1579 * GMII mode.
1580 */
64f6b64d
SH		 1581 if (hw->phy_type != SK_PHY_XMAC) {
1582 /* Take external Phy out of reset */
1583 r = skge_read32(hw, B2_GP_IO);
1584 if (port == 0)
1585 r |= GP_DIR_0|GP_IO_0;
1586 else
1587 r |= GP_DIR_2|GP_IO_2;
89bf5f23 1588
64f6b64d 1589 skge_write32(hw, B2_GP_IO, r);
0781191c 1590
64f6b64d
SH		 1591 /* Enable GMII interface */
1592 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1593 }
89bf5f23 1594
89bf5f23 1595
67777f9b 1596 switch (hw->phy_type) {
64f6b64d
SH		 1597 case SK_PHY_XMAC:
1598 xm_phy_init(skge);
1599 break;
1600 case SK_PHY_BCOM:
1601 bcom_phy_init(skge);
1602 bcom_check_link(hw, port);
1603 }
89bf5f23 1604
45bada65
SH		 1605 /* Set Station Address */
1606 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1607
45bada65
SH		 1608 /* We don't use match addresses so clear */
1609 for (i = 1; i < 16; i++)
1610 xm_outaddr(hw, port, XM_EXM(i), zero);
1611
0781191c
SH		 1612 /* Clear MIB counters */
1613 xm_write16(hw, port, XM_STAT_CMD,
1614 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1615 /* Clear two times according to Errata #3 */
1616 xm_write16(hw, port, XM_STAT_CMD,
1617 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1618
45bada65
SH		 1619 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1620 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1621
1622 /* We don't need the FCS appended to the packet. */
1623 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1624 if (jumbo)
1625 r |= XM_RX_BIG_PK_OK;
89bf5f23 1626
45bada65 1627 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1628 /*
45bada65
SH		 1629 * If in manual half duplex mode the other side might be in
1630 * full duplex mode, so ignore if a carrier extension is not seen
1631 * on frames received
89bf5f23 1632 */
45bada65 1633 r |= XM_RX_DIS_CEXT;
baef58b1 1634 }
45bada65 1635 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1636
baef58b1 1637 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1638 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1639
485982a9
SH		 1640 /* Increase threshold for jumbo frames on dual port */
1641 if (hw->ports > 1 && jumbo)
1642 xm_write16(hw, port, XM_TX_THR, 1020);
1643 else
1644 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1645
1646 /*
1647 * Enable the reception of all error frames. This is is
1648 * a necessary evil due to the design of the XMAC. The
1649 * XMAC's receive FIFO is only 8K in size, however jumbo
1650 * frames can be up to 9000 bytes in length. When bad
1651 * frame filtering is enabled, the XMAC's RX FIFO operates
1652 * in 'store and forward' mode. For this to work, the
1653 * entire frame has to fit into the FIFO, but that means
1654 * that jumbo frames larger than 8192 bytes will be
1655 * truncated. Disabling all bad frame filtering causes
1656 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1657 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1658 * RX FIFO as soon as the FIFO threshold is reached.
1659 */
45bada65 1660 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1661
baef58b1
SH		 1662
1663 /*
45bada65
SH		 1664 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1665 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1666 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1667 */
45bada65
SH		 1668 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1669
1670 /*
1671 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1672 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1673 * and 'Octets Tx OK Hi Cnt Ov'.
1674 */
1675 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1676
1677 /* Configure MAC arbiter */
1678 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1679
1680 /* configure timeout values */
1681 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1682 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1683 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1684 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1685
1686 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1687 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1688 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1689 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1690
1691 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1692 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1693 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1694 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1695
1696 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1697 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1698 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1699 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1700
45bada65 1701 if (jumbo) {
baef58b1 1702 /* Enable frame flushing if jumbo frames used */
67777f9b 1703 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1704 } else {
1705 /* enable timeout timers if normal frames */
1706 skge_write16(hw, B3_PA_CTRL,
45bada65 1707 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1708 }
baef58b1
SH		 1709}
1710
1711static void genesis_stop(struct skge_port *skge)
1712{
1713 struct skge_hw *hw = skge->hw;
1714 int port = skge->port;
799b21d2 1715 unsigned retries = 1000;
21d7f677
SH		 1716 u16 cmd;
1717
67777f9b 1718 /* Disable Tx and Rx */
21d7f677
SH		 1719 cmd = xm_read16(hw, port, XM_MMU_CMD);
1720 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1721 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1722
46a60f2d
SH		 1723 genesis_reset(hw, port);
1724
baef58b1
SH		 1725 /* Clear Tx packet arbiter timeout IRQ */
1726 skge_write16(hw, B3_PA_CTRL,
1727 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1728
baef58b1 1729 /* Reset the MAC */
799b21d2
SH		 1730 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1731 do {
1732 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1733 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1734 break;
1735 } while (--retries > 0);
baef58b1
SH		 1736
1737 /* For external PHYs there must be special handling */
64f6b64d 1738 if (hw->phy_type != SK_PHY_XMAC) {
799b21d2 1739 u32 reg = skge_read32(hw, B2_GP_IO);
64f6b64d
SH		 1740 if (port == 0) {
1741 reg |= GP_DIR_0;
1742 reg &= ~GP_IO_0;
1743 } else {
1744 reg |= GP_DIR_2;
1745 reg &= ~GP_IO_2;
1746 }
1747 skge_write32(hw, B2_GP_IO, reg);
1748 skge_read32(hw, B2_GP_IO);
baef58b1
SH		 1749 }
1750
6b0c1480
SH		 1751 xm_write16(hw, port, XM_MMU_CMD,
1752 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1753 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1754
6b0c1480 1755 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1756}
1757
1758
1759static void genesis_get_stats(struct skge_port *skge, u64 *data)
1760{
1761 struct skge_hw *hw = skge->hw;
1762 int port = skge->port;
1763 int i;
1764 unsigned long timeout = jiffies + HZ;
1765
6b0c1480 1766 xm_write16(hw, port,
baef58b1
SH		 1767 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1768
1769 /* wait for update to complete */
6b0c1480 1770 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1771 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1772 if (time_after(jiffies, timeout))
1773 break;
1774 udelay(10);
1775 }
1776
1777 /* special case for 64 bit octet counter */
6b0c1480
SH		 1778 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1779 | xm_read32(hw, port, XM_TXO_OK_LO);
1780 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1781 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1782
1783 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1784 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1785}
1786
1787static void genesis_mac_intr(struct skge_hw *hw, int port)
1788{
da00772f
SH		 1789 struct net_device *dev = hw->dev[port];
1790 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1791 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1792
d707204c
JP		 1793 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1794 "mac interrupt status 0x%x\n", status);
baef58b1 1795
501fb72d 1796 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
67777f9b 1797 xm_link_down(hw, port);
501fb72d
SH		 1798 mod_timer(&skge->link_timer, jiffies + 1);
1799 }
a1bc9b87 1800
baef58b1 1801 if (status & XM_IS_TXF_UR) {
6b0c1480 1802 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
da00772f 1803 ++dev->stats.tx_fifo_errors;
baef58b1 1804 }
baef58b1
SH		 1805}
1806
baef58b1
SH		 1807static void genesis_link_up(struct skge_port *skge)
1808{
1809 struct skge_hw *hw = skge->hw;
1810 int port = skge->port;
a1bc9b87 1811 u16 cmd, msk;
64f6b64d 1812 u32 mode;
baef58b1 1813
6b0c1480 1814 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1815
1816 /*
1817 * enabling pause frame reception is required for 1000BT
1818 * because the XMAC is not reset if the link is going down
1819 */
5d5c8e03
SH		 1820 if (skge->flow_status == FLOW_STAT_NONE ||
1821 skge->flow_status == FLOW_STAT_LOC_SEND)
7e676d91 1822 /* Disable Pause Frame Reception */
baef58b1
SH		 1823 cmd |= XM_MMU_IGN_PF;
1824 else
1825 /* Enable Pause Frame Reception */
1826 cmd &= ~XM_MMU_IGN_PF;
1827
6b0c1480 1828 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1829
6b0c1480 1830 mode = xm_read32(hw, port, XM_MODE);
67777f9b 1831 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
5d5c8e03 1832 skge->flow_status == FLOW_STAT_LOC_SEND) {
baef58b1
SH		 1833 /*
1834 * Configure Pause Frame Generation
1835 * Use internal and external Pause Frame Generation.
1836 * Sending pause frames is edge triggered.
1837 * Send a Pause frame with the maximum pause time if
1838 * internal oder external FIFO full condition occurs.
1839 * Send a zero pause time frame to re-start transmission.
1840 */
1841 /* XM_PAUSE_DA = '010000C28001' (default) */
1842 /* XM_MAC_PTIME = 0xffff (maximum) */
1843 /* remember this value is defined in big endian (!) */
6b0c1480 1844 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1845
1846 mode |= XM_PAUSE_MODE;
6b0c1480 1847 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1848 } else {
1849 /*
1850 * disable pause frame generation is required for 1000BT
1851 * because the XMAC is not reset if the link is going down
1852 */
1853 /* Disable Pause Mode in Mode Register */
1854 mode &= ~XM_PAUSE_MODE;
1855
6b0c1480 1856 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1857 }
1858
6b0c1480 1859 xm_write32(hw, port, XM_MODE, mode);
a1bc9b87 1860
d08b9bdf 1861 /* Turn on detection of Tx underrun */
501fb72d 1862 msk = xm_read16(hw, port, XM_IMSK);
d08b9bdf 1863 msk &= ~XM_IS_TXF_UR;
a1bc9b87 1864 xm_write16(hw, port, XM_IMSK, msk);
501fb72d 1865
6b0c1480 1866 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1867
1868 /* get MMU Command Reg. */
6b0c1480 1869 cmd = xm_read16(hw, port, XM_MMU_CMD);
64f6b64d 1870 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1871 cmd |= XM_MMU_GMII_FD;
1872
89bf5f23
SH		 1873 /*
1874 * Workaround BCOM Errata (#10523) for all BCom Phys
1875 * Enable Power Management after link up
1876 */
64f6b64d
SH		 1877 if (hw->phy_type == SK_PHY_BCOM) {
1878 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1879 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1880 & ~PHY_B_AC_DIS_PM);
1881 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1882 }
baef58b1
SH		 1883
1884 /* enable Rx/Tx */
6b0c1480 1885 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1886 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1887 skge_link_up(skge);
1888}
1889
1890
45bada65 1891static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1892{
1893 struct skge_hw *hw = skge->hw;
1894 int port = skge->port;
45bada65
SH		 1895 u16 isrc;
1896
1897 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
d707204c
JP		 1898 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1899 "phy interrupt status 0x%x\n", isrc);
baef58b1 1900
45bada65 1901 if (isrc & PHY_B_IS_PSE)
f15063cd 1902 pr_err("%s: uncorrectable pair swap error\n",
45bada65 1903 hw->dev[port]->name);
baef58b1
SH		 1904
1905 /* Workaround BCom Errata:
1906 * enable and disable loopback mode if "NO HCD" occurs.
1907 */
45bada65 1908 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1909 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1910 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1911 ctrl | PHY_CT_LOOP);
6b0c1480 1912 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1913 ctrl & ~PHY_CT_LOOP);
1914 }
1915
45bada65
SH		 1916 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1917 bcom_check_link(hw, port);
baef58b1 1918
baef58b1
SH		 1919}
1920
2cd8e5d3
SH		 1921static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1922{
1923 int i;
1924
1925 gma_write16(hw, port, GM_SMI_DATA, val);
1926 gma_write16(hw, port, GM_SMI_CTRL,
1927 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1928 for (i = 0; i < PHY_RETRIES; i++) {
1929 udelay(1);
1930
1931 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1932 return 0;
1933 }
1934
f15063cd 1935 pr_warning("%s: phy write timeout\n", hw->dev[port]->name);
2cd8e5d3
SH		 1936 return -EIO;
1937}
1938
1939static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1940{
1941 int i;
1942
1943 gma_write16(hw, port, GM_SMI_CTRL,
1944 GM_SMI_CT_PHY_AD(hw->phy_addr)
1945 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1946
1947 for (i = 0; i < PHY_RETRIES; i++) {
1948 udelay(1);
1949 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1950 goto ready;
1951 }
1952
1953 return -ETIMEDOUT;
1954 ready:
1955 *val = gma_read16(hw, port, GM_SMI_DATA);
1956 return 0;
1957}
1958
1959static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1960{
1961 u16 v = 0;
1962 if (__gm_phy_read(hw, port, reg, &v))
f15063cd 1963 pr_warning("%s: phy read timeout\n", hw->dev[port]->name);
2cd8e5d3
SH		 1964 return v;
1965}
1966
8f3f8193 1967/* Marvell Phy Initialization */
baef58b1
SH		 1968static void yukon_init(struct skge_hw *hw, int port)
1969{
1970 struct skge_port *skge = netdev_priv(hw->dev[port]);
1971 u16 ctrl, ct1000, adv;
baef58b1 1972
baef58b1 1973 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1974 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1975
1976 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1977 PHY_M_EC_MAC_S_MSK);
1978 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1979
c506a509 1980 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1981
6b0c1480 1982 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1983 }
1984
6b0c1480 1985 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1986 if (skge->autoneg == AUTONEG_DISABLE)
1987 ctrl &= ~PHY_CT_ANE;
1988
1989 ctrl |= PHY_CT_RESET;
6b0c1480 1990 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1991
1992 ctrl = 0;
1993 ct1000 = 0;
b18f2091 1994 adv = PHY_AN_CSMA;
baef58b1
SH		 1995
1996 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1997 if (hw->copper) {
baef58b1
SH		 1998 if (skge->advertising & ADVERTISED_1000baseT_Full)
1999 ct1000 |= PHY_M_1000C_AFD;
2000 if (skge->advertising & ADVERTISED_1000baseT_Half)
2001 ct1000 |= PHY_M_1000C_AHD;
2002 if (skge->advertising & ADVERTISED_100baseT_Full)
2003 adv |= PHY_M_AN_100_FD;
2004 if (skge->advertising & ADVERTISED_100baseT_Half)
2005 adv |= PHY_M_AN_100_HD;
2006 if (skge->advertising & ADVERTISED_10baseT_Full)
2007 adv |= PHY_M_AN_10_FD;
2008 if (skge->advertising & ADVERTISED_10baseT_Half)
2009 adv |= PHY_M_AN_10_HD;
baef58b1 2010
4b67be99
SH		 2011 /* Set Flow-control capabilities */
2012 adv |= phy_pause_map[skge->flow_control];
2013 } else {
2014 if (skge->advertising & ADVERTISED_1000baseT_Full)
2015 adv |= PHY_M_AN_1000X_AFD;
2016 if (skge->advertising & ADVERTISED_1000baseT_Half)
2017 adv |= PHY_M_AN_1000X_AHD;
2018
2019 adv |= fiber_pause_map[skge->flow_control];
2020 }
45bada65 2021
baef58b1
SH		 2022 /* Restart Auto-negotiation */
2023 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2024 } else {
2025 /* forced speed/duplex settings */
2026 ct1000 = PHY_M_1000C_MSE;
2027
2028 if (skge->duplex == DUPLEX_FULL)
2029 ctrl |= PHY_CT_DUP_MD;
2030
2031 switch (skge->speed) {
2032 case SPEED_1000:
2033 ctrl |= PHY_CT_SP1000;
2034 break;
2035 case SPEED_100:
2036 ctrl |= PHY_CT_SP100;
2037 break;
2038 }
2039
2040 ctrl |= PHY_CT_RESET;
2041 }
2042
c506a509 2043 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 2044
6b0c1480
SH		 2045 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2046 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 2047
baef58b1
SH		 2048 /* Enable phy interrupt on autonegotiation complete (or link up) */
2049 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 2050 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 2051 else
4cde06ed 2052 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2053}
2054
2055static void yukon_reset(struct skge_hw *hw, int port)
2056{
6b0c1480
SH		 2057 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2058 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2059 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2060 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2061 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 2062
6b0c1480
SH		 2063 gma_write16(hw, port, GM_RX_CTRL,
2064 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 2065 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2066}
2067
c8868611
SH		 2068/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2069static int is_yukon_lite_a0(struct skge_hw *hw)
2070{
2071 u32 reg;
2072 int ret;
2073
2074 if (hw->chip_id != CHIP_ID_YUKON)
2075 return 0;
2076
2077 reg = skge_read32(hw, B2_FAR);
2078 skge_write8(hw, B2_FAR + 3, 0xff);
2079 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2080 skge_write32(hw, B2_FAR, reg);
2081 return ret;
2082}
2083
baef58b1
SH		 2084static void yukon_mac_init(struct skge_hw *hw, int port)
2085{
2086 struct skge_port *skge = netdev_priv(hw->dev[port]);
2087 int i;
2088 u32 reg;
2089 const u8 *addr = hw->dev[port]->dev_addr;
2090
2091 /* WA code for COMA mode -- set PHY reset */
2092 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2093 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2094 reg = skge_read32(hw, B2_GP_IO);
2095 reg |= GP_DIR_9 | GP_IO_9;
2096 skge_write32(hw, B2_GP_IO, reg);
2097 }
baef58b1
SH		 2098
2099 /* hard reset */
6b0c1480
SH		 2100 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2101 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2102
2103 /* WA code for COMA mode -- clear PHY reset */
2104 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2105 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2106 reg = skge_read32(hw, B2_GP_IO);
2107 reg |= GP_DIR_9;
2108 reg &= ~GP_IO_9;
2109 skge_write32(hw, B2_GP_IO, reg);
2110 }
baef58b1
SH		 2111
2112 /* Set hardware config mode */
2113 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2114 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 2115 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 2116
2117 /* Clear GMC reset */
6b0c1480
SH		 2118 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2119 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2120 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 2121
baef58b1
SH		 2122 if (skge->autoneg == AUTONEG_DISABLE) {
2123 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 2124 gma_write16(hw, port, GM_GP_CTRL,
2125 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 2126
2127 switch (skge->speed) {
2128 case SPEED_1000:
564f9abb 2129 reg &= ~GM_GPCR_SPEED_100;
baef58b1 2130 reg |= GM_GPCR_SPEED_1000;
564f9abb 2131 break;
baef58b1 2132 case SPEED_100:
564f9abb 2133 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 2134 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 2135 break;
2136 case SPEED_10:
2137 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2138 break;
baef58b1
SH		 2139 }
2140
2141 if (skge->duplex == DUPLEX_FULL)
2142 reg |= GM_GPCR_DUP_FULL;
2143 } else
2144 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 2145
baef58b1
SH		 2146 switch (skge->flow_control) {
2147 case FLOW_MODE_NONE:
6b0c1480 2148 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 2149 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2150 break;
2151 case FLOW_MODE_LOC_SEND:
2152 /* disable Rx flow-control */
2153 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
5d5c8e03
SH		 2154 break;
2155 case FLOW_MODE_SYMMETRIC:
2156 case FLOW_MODE_SYM_OR_REM:
2157 /* enable Tx & Rx flow-control */
2158 break;
baef58b1
SH		 2159 }
2160
6b0c1480 2161 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 2162 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2163
baef58b1 2164 yukon_init(hw, port);
baef58b1
SH		 2165
2166 /* MIB clear */
6b0c1480
SH		 2167 reg = gma_read16(hw, port, GM_PHY_ADDR);
2168 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 2169
2170 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 2171 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2172 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 2173
2174 /* transmit control */
6b0c1480 2175 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 2176
2177 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 2178 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 2179 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2180
2181 /* transmit flow control */
6b0c1480 2182 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 2183
2184 /* transmit parameter */
6b0c1480 2185 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 2186 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2187 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2188 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2189
44c7fcce
SH		 2190 /* configure the Serial Mode Register */
2191 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2192 | GM_SMOD_VLAN_ENA
2193 | IPG_DATA_VAL(IPG_DATA_DEF);
2194
2195 if (hw->dev[port]->mtu > ETH_DATA_LEN)
baef58b1
SH		 2196 reg |= GM_SMOD_JUMBO_ENA;
2197
6b0c1480 2198 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 2199
2200 /* physical address: used for pause frames */
6b0c1480 2201 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 2202 /* virtual address for data */
6b0c1480 2203 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 2204
2205 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 2206 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2207 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2208 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 2209
2210 /* Initialize Mac Fifo */
2211
2212 /* Configure Rx MAC FIFO */
6b0c1480 2213 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 2214 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 2215
2216 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2217 if (is_yukon_lite_a0(hw))
baef58b1 2218 reg &= ~GMF_RX_F_FL_ON;
c8868611 2219
6b0c1480
SH		 2220 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2221 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 2222 /*
2223 * because Pause Packet Truncation in GMAC is not working
2224 * we have to increase the Flush Threshold to 64 bytes
2225 * in order to flush pause packets in Rx FIFO on Yukon-1
2226 */
2227 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 2228
2229 /* Configure Tx MAC FIFO */
6b0c1480
SH		 2230 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2231 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 2232}
2233
355ec572
SH		 2234/* Go into power down mode */
2235static void yukon_suspend(struct skge_hw *hw, int port)
2236{
2237 u16 ctrl;
2238
2239 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2240 ctrl |= PHY_M_PC_POL_R_DIS;
2241 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2242
2243 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2244 ctrl |= PHY_CT_RESET;
2245 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2246
2247 /* switch IEEE compatible power down mode on */
2248 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2249 ctrl |= PHY_CT_PDOWN;
2250 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2251}
2252
baef58b1
SH		 2253static void yukon_stop(struct skge_port *skge)
2254{
2255 struct skge_hw *hw = skge->hw;
2256 int port = skge->port;
2257
46a60f2d
SH		 2258 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2259 yukon_reset(hw, port);
baef58b1 2260
6b0c1480
SH		 2261 gma_write16(hw, port, GM_GP_CTRL,
2262 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 2263 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 2264 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 2265
355ec572 2266 yukon_suspend(hw, port);
46a60f2d 2267
baef58b1 2268 /* set GPHY Control reset */
46a60f2d
SH		 2269 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2270 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2271}
2272
2273static void yukon_get_stats(struct skge_port *skge, u64 *data)
2274{
2275 struct skge_hw *hw = skge->hw;
2276 int port = skge->port;
2277 int i;
2278
6b0c1480
SH		 2279 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2280 | gma_read32(hw, port, GM_TXO_OK_LO);
2281 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2282 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 2283
2284 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 2285 data[i] = gma_read32(hw, port,
baef58b1
SH		 2286 skge_stats[i].gma_offset);
2287}
2288
2289static void yukon_mac_intr(struct skge_hw *hw, int port)
2290{
7e676d91
SH		 2291 struct net_device *dev = hw->dev[port];
2292 struct skge_port *skge = netdev_priv(dev);
6b0c1480 2293 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2294
d707204c
JP		 2295 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2296 "mac interrupt status 0x%x\n", status);
7e676d91 2297
baef58b1 2298 if (status & GM_IS_RX_FF_OR) {
da00772f 2299 ++dev->stats.rx_fifo_errors;
d8a09943 2300 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 2301 }
d8a09943 2302
baef58b1 2303 if (status & GM_IS_TX_FF_UR) {
da00772f 2304 ++dev->stats.tx_fifo_errors;
d8a09943 2305 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 2306 }
2307
2308}
2309
2310static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2311{
95566065 2312 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 2313 case PHY_M_PS_SPEED_1000:
2314 return SPEED_1000;
2315 case PHY_M_PS_SPEED_100:
2316 return SPEED_100;
2317 default:
2318 return SPEED_10;
2319 }
2320}
2321
2322static void yukon_link_up(struct skge_port *skge)
2323{
2324 struct skge_hw *hw = skge->hw;
2325 int port = skge->port;
2326 u16 reg;
2327
baef58b1 2328 /* Enable Transmit FIFO Underrun */
46a60f2d 2329 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 2330
6b0c1480 2331 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 2332 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2333 reg |= GM_GPCR_DUP_FULL;
2334
2335 /* enable Rx/Tx */
2336 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 2337 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 2338
4cde06ed 2339 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2340 skge_link_up(skge);
2341}
2342
2343static void yukon_link_down(struct skge_port *skge)
2344{
2345 struct skge_hw *hw = skge->hw;
2346 int port = skge->port;
d8a09943 2347 u16 ctrl;
baef58b1 2348
d8a09943
SH		 2349 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2350 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2351 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 2352
5d5c8e03
SH		 2353 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2354 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2355 ctrl |= PHY_M_AN_ASP;
baef58b1 2356 /* restore Asymmetric Pause bit */
5d5c8e03 2357 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
baef58b1
SH		 2358 }
2359
baef58b1
SH		 2360 skge_link_down(skge);
2361
2362 yukon_init(hw, port);
2363}
2364
2365static void yukon_phy_intr(struct skge_port *skge)
2366{
2367 struct skge_hw *hw = skge->hw;
2368 int port = skge->port;
2369 const char *reason = NULL;
2370 u16 istatus, phystat;
2371
6b0c1480
SH		 2372 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2373 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91 2374
d707204c
JP		 2375 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2376 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
baef58b1
SH		 2377
2378 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2379 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2380 & PHY_M_AN_RF) {
2381 reason = "remote fault";
2382 goto failed;
2383 }
2384
c506a509 2385 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 2386 reason = "master/slave fault";
2387 goto failed;
2388 }
2389
2390 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2391 reason = "speed/duplex";
2392 goto failed;
2393 }
2394
2395 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2396 ? DUPLEX_FULL : DUPLEX_HALF;
2397 skge->speed = yukon_speed(hw, phystat);
2398
baef58b1
SH		 2399 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2400 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2401 case PHY_M_PS_PAUSE_MSK:
5d5c8e03 2402 skge->flow_status = FLOW_STAT_SYMMETRIC;
baef58b1
SH		 2403 break;
2404 case PHY_M_PS_RX_P_EN:
5d5c8e03 2405 skge->flow_status = FLOW_STAT_REM_SEND;
baef58b1
SH		 2406 break;
2407 case PHY_M_PS_TX_P_EN:
5d5c8e03 2408 skge->flow_status = FLOW_STAT_LOC_SEND;
baef58b1
SH		 2409 break;
2410 default:
5d5c8e03 2411 skge->flow_status = FLOW_STAT_NONE;
baef58b1
SH		 2412 }
2413
5d5c8e03 2414 if (skge->flow_status == FLOW_STAT_NONE ||
baef58b1 2415 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2416 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2417 else
6b0c1480 2418 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2419 yukon_link_up(skge);
2420 return;
2421 }
2422
2423 if (istatus & PHY_M_IS_LSP_CHANGE)
2424 skge->speed = yukon_speed(hw, phystat);
2425
2426 if (istatus & PHY_M_IS_DUP_CHANGE)
2427 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2428 if (istatus & PHY_M_IS_LST_CHANGE) {
2429 if (phystat & PHY_M_PS_LINK_UP)
2430 yukon_link_up(skge);
2431 else
2432 yukon_link_down(skge);
2433 }
2434 return;
2435 failed:
f15063cd 2436 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
baef58b1
SH		 2437
2438 /* XXX restart autonegotiation? */
2439}
2440
ee294dcd
SH		 2441static void skge_phy_reset(struct skge_port *skge)
2442{
2443 struct skge_hw *hw = skge->hw;
2444 int port = skge->port;
aae343d4 2445 struct net_device *dev = hw->dev[port];
ee294dcd
SH		 2446
2447 netif_stop_queue(skge->netdev);
2448 netif_carrier_off(skge->netdev);
2449
9cbe330f 2450 spin_lock_bh(&hw->phy_lock);
ee294dcd
SH		 2451 if (hw->chip_id == CHIP_ID_GENESIS) {
2452 genesis_reset(hw, port);
2453 genesis_mac_init(hw, port);
2454 } else {
2455 yukon_reset(hw, port);
2456 yukon_init(hw, port);
2457 }
9cbe330f 2458 spin_unlock_bh(&hw->phy_lock);
75814090 2459
f80d032b 2460 skge_set_multicast(dev);
ee294dcd
SH		 2461}
2462
2cd8e5d3
SH		 2463/* Basic MII support */
2464static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2465{
2466 struct mii_ioctl_data *data = if_mii(ifr);
2467 struct skge_port *skge = netdev_priv(dev);
2468 struct skge_hw *hw = skge->hw;
2469 int err = -EOPNOTSUPP;
2470
2471 if (!netif_running(dev))
2472 return -ENODEV; /* Phy still in reset */
2473
67777f9b 2474 switch (cmd) {
2cd8e5d3
SH		 2475 case SIOCGMIIPHY:
2476 data->phy_id = hw->phy_addr;
2477
2478 /* fallthru */
2479 case SIOCGMIIREG: {
2480 u16 val = 0;
9cbe330f 2481 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2482 if (hw->chip_id == CHIP_ID_GENESIS)
2483 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2484 else
2485 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
9cbe330f 2486 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2487 data->val_out = val;
2488 break;
2489 }
2490
2491 case SIOCSMIIREG:
9cbe330f 2492 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2493 if (hw->chip_id == CHIP_ID_GENESIS)
2494 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2495 data->val_in);
2496 else
2497 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2498 data->val_in);
9cbe330f 2499 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2500 break;
2501 }
2502 return err;
2503}
2504
279e1dab 2505static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
baef58b1
SH		 2506{
2507 u32 end;
2508
279e1dab
LT		 2509 start /= 8;
2510 len /= 8;
2511 end = start + len - 1;
baef58b1
SH		 2512
2513 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2514 skge_write32(hw, RB_ADDR(q, RB_START), start);
2515 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2516 skge_write32(hw, RB_ADDR(q, RB_RP), start);
279e1dab 2517 skge_write32(hw, RB_ADDR(q, RB_END), end);
baef58b1
SH		 2518
2519 if (q == Q_R1 || q == Q_R2) {
2520 /* Set thresholds on receive queue's */
279e1dab
LT		 2521 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2522 start + (2*len)/3);
2523 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2524 start + (len/3));
2525 } else {
2526 /* Enable store & forward on Tx queue's because
2527 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2528 */
baef58b1 2529 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
279e1dab 2530 }
baef58b1
SH		 2531
2532 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2533}
2534
2535/* Setup Bus Memory Interface */
2536static void skge_qset(struct skge_port *skge, u16 q,
2537 const struct skge_element *e)
2538{
2539 struct skge_hw *hw = skge->hw;
2540 u32 watermark = 0x600;
2541 u64 base = skge->dma + (e->desc - skge->mem);
2542
2543 /* optimization to reduce window on 32bit/33mhz */
2544 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2545 watermark /= 2;
2546
2547 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2548 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2549 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2550 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2551}
2552
2553static int skge_up(struct net_device *dev)
2554{
2555 struct skge_port *skge = netdev_priv(dev);
2556 struct skge_hw *hw = skge->hw;
2557 int port = skge->port;
279e1dab 2558 u32 chunk, ram_addr;
baef58b1
SH		 2559 size_t rx_size, tx_size;
2560 int err;
2561
fae87592
SH		 2562 if (!is_valid_ether_addr(dev->dev_addr))
2563 return -EINVAL;
2564
d707204c 2565 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
baef58b1 2566
19a33d4e 2567 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2568 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2569 else
2570 skge->rx_buf_size = RX_BUF_SIZE;
2571
2572
baef58b1
SH		 2573 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2574 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2575 skge->mem_size = tx_size + rx_size;
2576 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2577 if (!skge->mem)
2578 return -ENOMEM;
2579
c3da1447
SH		 2580 BUG_ON(skge->dma & 7);
2581
2582 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
1479d13c 2583 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
c3da1447
SH		 2584 err = -EINVAL;
2585 goto free_pci_mem;
2586 }
2587
baef58b1
SH		 2588 memset(skge->mem, 0, skge->mem_size);
2589
203babb6
SH		 2590 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2591 if (err)
baef58b1
SH		 2592 goto free_pci_mem;
2593
c54f9765 2594 err = skge_rx_fill(dev);
19a33d4e 2595 if (err)
baef58b1
SH		 2596 goto free_rx_ring;
2597
203babb6
SH		 2598 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2599 skge->dma + rx_size);
2600 if (err)
baef58b1
SH		 2601 goto free_rx_ring;
2602
8f3f8193 2603 /* Initialize MAC */
9cbe330f 2604 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2605 if (hw->chip_id == CHIP_ID_GENESIS)
2606 genesis_mac_init(hw, port);
2607 else
2608 yukon_mac_init(hw, port);
9cbe330f 2609 spin_unlock_bh(&hw->phy_lock);
baef58b1 2610
29816d9a
SH		 2611 /* Configure RAMbuffers - equally between ports and tx/rx */
2612 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
279e1dab 2613 ram_addr = hw->ram_offset + 2 * chunk * port;
baef58b1 2614
279e1dab 2615 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
7fb7ac24 2616 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
279e1dab 2617
baef58b1 2618 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
279e1dab 2619 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
baef58b1
SH		 2620 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2621
2622 /* Start receiver BMU */
2623 wmb();
2624 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2625 skge_led(skge, LED_MODE_ON);
baef58b1 2626
4ebabfcb
SH		 2627 spin_lock_irq(&hw->hw_lock);
2628 hw->intr_mask |= portmask[port];
2629 skge_write32(hw, B0_IMSK, hw->intr_mask);
2630 spin_unlock_irq(&hw->hw_lock);
2631
bea3348e 2632 napi_enable(&skge->napi);
baef58b1
SH		 2633 return 0;
2634
2635 free_rx_ring:
2636 skge_rx_clean(skge);
2637 kfree(skge->rx_ring.start);
2638 free_pci_mem:
2639 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2640 skge->mem = NULL;
baef58b1
SH		 2641
2642 return err;
2643}
2644
60b24b51
SH		 2645/* stop receiver */
2646static void skge_rx_stop(struct skge_hw *hw, int port)
2647{
2648 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2649 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2650 RB_RST_SET|RB_DIS_OP_MD);
2651 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2652}
2653
baef58b1
SH		 2654static int skge_down(struct net_device *dev)
2655{
2656 struct skge_port *skge = netdev_priv(dev);
2657 struct skge_hw *hw = skge->hw;
2658 int port = skge->port;
2659
7731a4ea
SH		 2660 if (skge->mem == NULL)
2661 return 0;
2662
d707204c 2663 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
baef58b1 2664
d119b392 2665 netif_tx_disable(dev);
692412b3 2666
64f6b64d 2667 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
9cbe330f 2668 del_timer_sync(&skge->link_timer);
baef58b1 2669
bea3348e 2670 napi_disable(&skge->napi);
692412b3 2671 netif_carrier_off(dev);
4ebabfcb
SH		 2672
2673 spin_lock_irq(&hw->hw_lock);
2674 hw->intr_mask &= ~portmask[port];
2675 skge_write32(hw, B0_IMSK, hw->intr_mask);
2676 spin_unlock_irq(&hw->hw_lock);
2677
46a60f2d
SH		 2678 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2679 if (hw->chip_id == CHIP_ID_GENESIS)
2680 genesis_stop(skge);
2681 else
2682 yukon_stop(skge);
2683
baef58b1
SH		 2684 /* Stop transmitter */
2685 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2686 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2687 RB_RST_SET|RB_DIS_OP_MD);
2688
baef58b1
SH		 2689
2690 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2691 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2692 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2693
2694 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2695 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2696 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2697
2698 /* Reset PCI FIFO */
2699 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2700 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2701
2702 /* Reset the RAM Buffer async Tx queue */
2703 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
60b24b51
SH		 2704
2705 skge_rx_stop(hw, port);
baef58b1
SH		 2706
2707 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2708 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2709 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2710 } else {
6b0c1480
SH		 2711 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2712 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2713 }
2714
6abebb53 2715 skge_led(skge, LED_MODE_OFF);
baef58b1 2716
e3a1b99f 2717 netif_tx_lock_bh(dev);
513f533e 2718 skge_tx_clean(dev);
e3a1b99f
SH		 2719 netif_tx_unlock_bh(dev);
2720
baef58b1
SH		 2721 skge_rx_clean(skge);
2722
2723 kfree(skge->rx_ring.start);
2724 kfree(skge->tx_ring.start);
2725 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2726 skge->mem = NULL;
baef58b1
SH		 2727 return 0;
2728}
2729
29b4e886
SH		 2730static inline int skge_avail(const struct skge_ring *ring)
2731{
992c9623 2732 smp_mb();
29b4e886
SH		 2733 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2734 + (ring->to_clean - ring->to_use) - 1;
2735}
2736
61357325
SH		 2737static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2738 struct net_device *dev)
baef58b1
SH		 2739{
2740 struct skge_port *skge = netdev_priv(dev);
2741 struct skge_hw *hw = skge->hw;
baef58b1
SH		 2742 struct skge_element *e;
2743 struct skge_tx_desc *td;
2744 int i;
2745 u32 control, len;
2746 u64 map;
baef58b1 2747
5b057c6b 2748 if (skb_padto(skb, ETH_ZLEN))
baef58b1
SH		 2749 return NETDEV_TX_OK;
2750
513f533e 2751 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
baef58b1 2752 return NETDEV_TX_BUSY;
baef58b1 2753
7c442fa1 2754 e = skge->tx_ring.to_use;
baef58b1 2755 td = e->desc;
7c442fa1 2756 BUG_ON(td->control & BMU_OWN);
baef58b1
SH		 2757 e->skb = skb;
2758 len = skb_headlen(skb);
2759 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
10fc51b9
FT		 2760 dma_unmap_addr_set(e, mapaddr, map);
2761 dma_unmap_len_set(e, maplen, len);
baef58b1
SH		 2762
2763 td->dma_lo = map;
2764 td->dma_hi = map >> 32;
2765
84fa7933 2766 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d 2767 const int offset = skb_transport_offset(skb);
baef58b1
SH		 2768
2769 /* This seems backwards, but it is what the sk98lin
2770 * does. Looks like hardware is wrong?
2771 */
8e95a202 2772 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
67777f9b 2773 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2774 control = BMU_TCP_CHECK;
2775 else
2776 control = BMU_UDP_CHECK;
2777
2778 td->csum_offs = 0;
2779 td->csum_start = offset;
ff1dcadb 2780 td->csum_write = offset + skb->csum_offset;
baef58b1
SH		 2781 } else
2782 control = BMU_CHECK;
2783
2784 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
67777f9b 2785 control |= BMU_EOF | BMU_IRQ_EOF;
baef58b1
SH		 2786 else {
2787 struct skge_tx_desc *tf = td;
2788
2789 control |= BMU_STFWD;
2790 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2791 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2792
2793 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2794 frag->size, PCI_DMA_TODEVICE);
2795
2796 e = e->next;
7c442fa1 2797 e->skb = skb;
baef58b1 2798 tf = e->desc;
7c442fa1
SH		 2799 BUG_ON(tf->control & BMU_OWN);
2800
baef58b1
SH		 2801 tf->dma_lo = map;
2802 tf->dma_hi = (u64) map >> 32;
10fc51b9
FT		 2803 dma_unmap_addr_set(e, mapaddr, map);
2804 dma_unmap_len_set(e, maplen, frag->size);
baef58b1
SH		 2805
2806 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2807 }
2808 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2809 }
2810 /* Make sure all the descriptors written */
2811 wmb();
2812 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2813 wmb();
2814
2815 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2816
d707204c
JP		 2817 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2818 "tx queued, slot %td, len %d\n",
2819 e - skge->tx_ring.start, skb->len);
baef58b1 2820
7c442fa1 2821 skge->tx_ring.to_use = e->next;
992c9623
SH		 2822 smp_wmb();
2823
9db96479 2824 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
f15063cd 2825 netdev_dbg(dev, "transmit queue full\n");
baef58b1
SH		 2826 netif_stop_queue(dev);
2827 }
2828
baef58b1
SH		 2829 return NETDEV_TX_OK;
2830}
2831
7c442fa1
SH		 2832
2833/* Free resources associated with this reing element */
2834static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2835 u32 control)
866b4f3e
SH		 2836{
2837 struct pci_dev *pdev = skge->hw->pdev;
866b4f3e 2838
7c442fa1
SH		 2839 /* skb header vs. fragment */
2840 if (control & BMU_STF)
10fc51b9
FT		 2841 pci_unmap_single(pdev, dma_unmap_addr(e, mapaddr),
2842 dma_unmap_len(e, maplen),
7c442fa1
SH		 2843 PCI_DMA_TODEVICE);
2844 else
10fc51b9
FT		 2845 pci_unmap_page(pdev, dma_unmap_addr(e, mapaddr),
2846 dma_unmap_len(e, maplen),
7c442fa1 2847 PCI_DMA_TODEVICE);
866b4f3e 2848
7c442fa1 2849 if (control & BMU_EOF) {
d707204c
JP		 2850 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
2851 "tx done slot %td\n", e - skge->tx_ring.start);
866b4f3e 2852
513f533e 2853 dev_kfree_skb(e->skb);
baef58b1
SH		 2854 }
2855}
2856
7c442fa1 2857/* Free all buffers in transmit ring */
513f533e 2858static void skge_tx_clean(struct net_device *dev)
baef58b1 2859{
513f533e 2860 struct skge_port *skge = netdev_priv(dev);
7c442fa1 2861 struct skge_element *e;
baef58b1 2862
7c442fa1
SH		 2863 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2864 struct skge_tx_desc *td = e->desc;
2865 skge_tx_free(skge, e, td->control);
2866 td->control = 0;
2867 }
2868
2869 skge->tx_ring.to_clean = e;
baef58b1
SH		 2870}
2871
2872static void skge_tx_timeout(struct net_device *dev)
2873{
2874 struct skge_port *skge = netdev_priv(dev);
2875
d707204c 2876 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
baef58b1
SH		 2877
2878 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
513f533e 2879 skge_tx_clean(dev);
d119b392 2880 netif_wake_queue(dev);
baef58b1
SH		 2881}
2882
2883static int skge_change_mtu(struct net_device *dev, int new_mtu)
2884{
7731a4ea 2885 int err;
baef58b1 2886
95566065 2887 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2888 return -EINVAL;
2889
7731a4ea
SH		 2890 if (!netif_running(dev)) {
2891 dev->mtu = new_mtu;
2892 return 0;
2893 }
2894
1a8098be 2895 skge_down(dev);
baef58b1 2896
19a33d4e 2897 dev->mtu = new_mtu;
7731a4ea 2898
1a8098be 2899 err = skge_up(dev);
7731a4ea
SH		 2900 if (err)
2901 dev_close(dev);
baef58b1
SH		 2902
2903 return err;
2904}
2905
c4cd29d2
SH		 2906static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2907
2908static void genesis_add_filter(u8 filter[8], const u8 *addr)
2909{
2910 u32 crc, bit;
2911
2912 crc = ether_crc_le(ETH_ALEN, addr);
2913 bit = ~crc & 0x3f;
2914 filter[bit/8] |= 1 << (bit%8);
2915}
2916
baef58b1
SH		 2917static void genesis_set_multicast(struct net_device *dev)
2918{
2919 struct skge_port *skge = netdev_priv(dev);
2920 struct skge_hw *hw = skge->hw;
2921 int port = skge->port;
22bedad3 2922 struct netdev_hw_addr *ha;
baef58b1
SH		 2923 u32 mode;
2924 u8 filter[8];
2925
6b0c1480 2926 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2927 mode |= XM_MD_ENA_HASH;
2928 if (dev->flags & IFF_PROMISC)
2929 mode |= XM_MD_ENA_PROM;
2930 else
2931 mode &= ~XM_MD_ENA_PROM;
2932
2933 if (dev->flags & IFF_ALLMULTI)
2934 memset(filter, 0xff, sizeof(filter));
2935 else {
2936 memset(filter, 0, sizeof(filter));
c4cd29d2 2937
8e95a202
JP		 2938 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2939 skge->flow_status == FLOW_STAT_SYMMETRIC)
c4cd29d2
SH		 2940 genesis_add_filter(filter, pause_mc_addr);
2941
22bedad3
JP		 2942 netdev_for_each_mc_addr(ha, dev)
2943 genesis_add_filter(filter, ha->addr);
baef58b1
SH		 2944 }
2945
6b0c1480 2946 xm_write32(hw, port, XM_MODE, mode);
45bada65 2947 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2948}
2949
c4cd29d2
SH		 2950static void yukon_add_filter(u8 filter[8], const u8 *addr)
2951{
2952 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2953 filter[bit/8] |= 1 << (bit%8);
2954}
2955
baef58b1
SH		 2956static void yukon_set_multicast(struct net_device *dev)
2957{
2958 struct skge_port *skge = netdev_priv(dev);
2959 struct skge_hw *hw = skge->hw;
2960 int port = skge->port;
22bedad3 2961 struct netdev_hw_addr *ha;
8e95a202
JP		 2962 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2963 skge->flow_status == FLOW_STAT_SYMMETRIC);
baef58b1
SH		 2964 u16 reg;
2965 u8 filter[8];
2966
2967 memset(filter, 0, sizeof(filter));
2968
6b0c1480 2969 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2970 reg |= GM_RXCR_UCF_ENA;
2971
8f3f8193 2972 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2973 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2974 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2975 memset(filter, 0xff, sizeof(filter));
4cd24eaf 2976 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
baef58b1
SH		 2977 reg &= ~GM_RXCR_MCF_ENA;
2978 else {
baef58b1
SH		 2979 reg |= GM_RXCR_MCF_ENA;
2980
c4cd29d2
SH		 2981 if (rx_pause)
2982 yukon_add_filter(filter, pause_mc_addr);
2983
22bedad3
JP		 2984 netdev_for_each_mc_addr(ha, dev)
2985 yukon_add_filter(filter, ha->addr);
baef58b1
SH		 2986 }
2987
2988
6b0c1480 2989 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2990 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2991 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2992 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2993 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2994 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2995 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2996 (u16)filter[6] | ((u16)filter[7] << 8));
2997
6b0c1480 2998 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2999}
3000
383181ac
SH		 3001static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3002{
3003 if (hw->chip_id == CHIP_ID_GENESIS)
3004 return status >> XMR_FS_LEN_SHIFT;
3005 else
3006 return status >> GMR_FS_LEN_SHIFT;
3007}
3008
baef58b1
SH		 3009static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3010{
3011 if (hw->chip_id == CHIP_ID_GENESIS)
3012 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3013 else
3014 return (status & GMR_FS_ANY_ERR) ||
3015 (status & GMR_FS_RX_OK) == 0;
3016}
3017
f80d032b
SH		 3018static void skge_set_multicast(struct net_device *dev)
3019{
3020 struct skge_port *skge = netdev_priv(dev);
3021 struct skge_hw *hw = skge->hw;
3022
3023 if (hw->chip_id == CHIP_ID_GENESIS)
3024 genesis_set_multicast(dev);
3025 else
3026 yukon_set_multicast(dev);
3027
3028}
3029
19a33d4e
SH		 3030
3031/* Get receive buffer from descriptor.
3032 * Handles copy of small buffers and reallocation failures
3033 */
c54f9765
SH		 3034static struct sk_buff *skge_rx_get(struct net_device *dev,
3035 struct skge_element *e,
3036 u32 control, u32 status, u16 csum)
19a33d4e 3037{
c54f9765 3038 struct skge_port *skge = netdev_priv(dev);
383181ac
SH		 3039 struct sk_buff *skb;
3040 u16 len = control & BMU_BBC;
3041
d707204c
JP		 3042 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3043 "rx slot %td status 0x%x len %d\n",
3044 e - skge->rx_ring.start, status, len);
383181ac
SH		 3045
3046 if (len > skge->rx_buf_size)
3047 goto error;
3048
3049 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3050 goto error;
3051
3052 if (bad_phy_status(skge->hw, status))
3053 goto error;
3054
3055 if (phy_length(skge->hw, status) != len)
3056 goto error;
19a33d4e
SH		 3057
3058 if (len < RX_COPY_THRESHOLD) {
89d71a66 3059 skb = netdev_alloc_skb_ip_align(dev, len);
383181ac
SH		 3060 if (!skb)
3061 goto resubmit;
19a33d4e
SH		 3062
3063 pci_dma_sync_single_for_cpu(skge->hw->pdev,
10fc51b9 3064 dma_unmap_addr(e, mapaddr),
19a33d4e 3065 len, PCI_DMA_FROMDEVICE);
d626f62b 3066 skb_copy_from_linear_data(e->skb, skb->data, len);
19a33d4e 3067 pci_dma_sync_single_for_device(skge->hw->pdev,
10fc51b9 3068 dma_unmap_addr(e, mapaddr),
19a33d4e 3069 len, PCI_DMA_FROMDEVICE);
19a33d4e 3070 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 3071 } else {
383181ac 3072 struct sk_buff *nskb;
89d71a66
ED		 3073
3074 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
383181ac
SH		 3075 if (!nskb)
3076 goto resubmit;
19a33d4e
SH		 3077
3078 pci_unmap_single(skge->hw->pdev,
10fc51b9
FT		 3079 dma_unmap_addr(e, mapaddr),
3080 dma_unmap_len(e, maplen),
19a33d4e
SH		 3081 PCI_DMA_FROMDEVICE);
3082 skb = e->skb;
67777f9b 3083 prefetch(skb->data);
19a33d4e 3084 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 3085 }
383181ac
SH		 3086
3087 skb_put(skb, len);
383181ac
SH		 3088 if (skge->rx_csum) {
3089 skb->csum = csum;
84fa7933 3090 skb->ip_summed = CHECKSUM_COMPLETE;
383181ac
SH		 3091 }
3092
c54f9765 3093 skb->protocol = eth_type_trans(skb, dev);
383181ac
SH		 3094
3095 return skb;
3096error:
3097
d707204c
JP		 3098 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3099 "rx err, slot %td control 0x%x status 0x%x\n",
3100 e - skge->rx_ring.start, control, status);
383181ac
SH		 3101
3102 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3103 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
da00772f 3104 dev->stats.rx_length_errors++;
383181ac 3105 if (status & XMR_FS_FRA_ERR)
da00772f 3106 dev->stats.rx_frame_errors++;
383181ac 3107 if (status & XMR_FS_FCS_ERR)
da00772f 3108 dev->stats.rx_crc_errors++;
383181ac
SH		 3109 } else {
3110 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
da00772f 3111 dev->stats.rx_length_errors++;
383181ac 3112 if (status & GMR_FS_FRAGMENT)
da00772f 3113 dev->stats.rx_frame_errors++;
383181ac 3114 if (status & GMR_FS_CRC_ERR)
da00772f 3115 dev->stats.rx_crc_errors++;
383181ac
SH		 3116 }
3117
3118resubmit:
3119 skge_rx_reuse(e, skge->rx_buf_size);
3120 return NULL;
baef58b1
SH		 3121}
3122
7c442fa1 3123/* Free all buffers in Tx ring which are no longer owned by device */
513f533e 3124static void skge_tx_done(struct net_device *dev)
00a6cae2 3125{
7c442fa1 3126 struct skge_port *skge = netdev_priv(dev);
00a6cae2 3127 struct skge_ring *ring = &skge->tx_ring;
7c442fa1
SH		 3128 struct skge_element *e;
3129
513f533e 3130 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
00a6cae2 3131
866b4f3e 3132 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
992c9623 3133 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
00a6cae2 3134
992c9623 3135 if (control & BMU_OWN)
00a6cae2
SH		 3136 break;
3137
992c9623 3138 skge_tx_free(skge, e, control);
00a6cae2 3139 }
7c442fa1 3140 skge->tx_ring.to_clean = e;
866b4f3e 3141
992c9623
SH		 3142 /* Can run lockless until we need to synchronize to restart queue. */
3143 smp_mb();
3144
3145 if (unlikely(netif_queue_stopped(dev) &&
3146 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3147 netif_tx_lock(dev);
3148 if (unlikely(netif_queue_stopped(dev) &&
3149 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3150 netif_wake_queue(dev);
00a6cae2 3151
992c9623
SH		 3152 }
3153 netif_tx_unlock(dev);
3154 }
00a6cae2 3155}
19a33d4e 3156
bea3348e 3157static int skge_poll(struct napi_struct *napi, int to_do)
baef58b1 3158{
bea3348e
SH		 3159 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3160 struct net_device *dev = skge->netdev;
baef58b1
SH		 3161 struct skge_hw *hw = skge->hw;
3162 struct skge_ring *ring = &skge->rx_ring;
3163 struct skge_element *e;
00a6cae2
SH		 3164 int work_done = 0;
3165
513f533e
SH		 3166 skge_tx_done(dev);
3167
3168 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3169
1631aef1 3170 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 3171 struct skge_rx_desc *rd = e->desc;
19a33d4e 3172 struct sk_buff *skb;
383181ac 3173 u32 control;
baef58b1
SH		 3174
3175 rmb();
3176 control = rd->control;
3177 if (control & BMU_OWN)
3178 break;
3179
c54f9765 3180 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
19a33d4e 3181 if (likely(skb)) {
86cac58b 3182 napi_gro_receive(napi, skb);
19a33d4e 3183 ++work_done;
5a011447 3184 }
baef58b1
SH		 3185 }
3186 ring->to_clean = e;
3187
baef58b1
SH		 3188 /* restart receiver */
3189 wmb();
a9cdab86 3190 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 3191
bea3348e 3192 if (work_done < to_do) {
6ef2977d 3193 unsigned long flags;
f0c88f9c 3194
86cac58b 3195 napi_gro_flush(napi);
6ef2977d 3196 spin_lock_irqsave(&hw->hw_lock, flags);
288379f0 3197 __napi_complete(napi);
bea3348e
SH		 3198 hw->intr_mask |= napimask[skge->port];
3199 skge_write32(hw, B0_IMSK, hw->intr_mask);
3200 skge_read32(hw, B0_IMSK);
6ef2977d 3201 spin_unlock_irqrestore(&hw->hw_lock, flags);
bea3348e 3202 }
1631aef1 3203
bea3348e 3204 return work_done;
baef58b1
SH		 3205}
3206
f6620cab
SH		 3207/* Parity errors seem to happen when Genesis is connected to a switch
3208 * with no other ports present. Heartbeat error??
3209 */
baef58b1
SH		 3210static void skge_mac_parity(struct skge_hw *hw, int port)
3211{
f6620cab
SH		 3212 struct net_device *dev = hw->dev[port];
3213
da00772f 3214 ++dev->stats.tx_heartbeat_errors;
baef58b1
SH		 3215
3216 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 3217 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 3218 MFF_CLR_PERR);
3219 else
3220 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 3221 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 3222 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 3223 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3224}
3225
baef58b1
SH		 3226static void skge_mac_intr(struct skge_hw *hw, int port)
3227{
95566065 3228 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 3229 genesis_mac_intr(hw, port);
3230 else
3231 yukon_mac_intr(hw, port);
3232}
3233
3234/* Handle device specific framing and timeout interrupts */
3235static void skge_error_irq(struct skge_hw *hw)
3236{
1479d13c 3237 struct pci_dev *pdev = hw->pdev;
baef58b1
SH		 3238 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3239
3240 if (hw->chip_id == CHIP_ID_GENESIS) {
3241 /* clear xmac errors */
3242 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 3243 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 3244 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 3245 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 3246 } else {
3247 /* Timestamp (unused) overflow */
3248 if (hwstatus & IS_IRQ_TIST_OV)
3249 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 3250 }
3251
3252 if (hwstatus & IS_RAM_RD_PAR) {
1479d13c 3253 dev_err(&pdev->dev, "Ram read data parity error\n");
baef58b1
SH		 3254 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3255 }
3256
3257 if (hwstatus & IS_RAM_WR_PAR) {
1479d13c 3258 dev_err(&pdev->dev, "Ram write data parity error\n");
baef58b1
SH		 3259 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3260 }
3261
3262 if (hwstatus & IS_M1_PAR_ERR)
3263 skge_mac_parity(hw, 0);
3264
3265 if (hwstatus & IS_M2_PAR_ERR)
3266 skge_mac_parity(hw, 1);
3267
b9d64acc 3268 if (hwstatus & IS_R1_PAR_ERR) {
1479d13c
SH		 3269 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3270 hw->dev[0]->name);
baef58b1 3271 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 3272 }
baef58b1 3273
b9d64acc 3274 if (hwstatus & IS_R2_PAR_ERR) {
1479d13c
SH		 3275 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3276 hw->dev[1]->name);
baef58b1 3277 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 3278 }
baef58b1
SH		 3279
3280 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 3281 u16 pci_status, pci_cmd;
3282
1479d13c
SH		 3283 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3284 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
baef58b1 3285
1479d13c
SH		 3286 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3287 pci_cmd, pci_status);
b9d64acc
SH		 3288
3289 /* Write the error bits back to clear them. */
3290 pci_status &= PCI_STATUS_ERROR_BITS;
3291 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1479d13c 3292 pci_write_config_word(pdev, PCI_COMMAND,
b9d64acc 3293 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
1479d13c 3294 pci_write_config_word(pdev, PCI_STATUS, pci_status);
b9d64acc 3295 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 3296
050ec18a 3297 /* if error still set then just ignore it */
baef58b1
SH		 3298 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3299 if (hwstatus & IS_IRQ_STAT) {
1479d13c 3300 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
baef58b1
SH		 3301 hw->intr_mask &= ~IS_HW_ERR;
3302 }
3303 }
3304}
3305
3306/*
9cbe330f 3307 * Interrupt from PHY are handled in tasklet (softirq)
baef58b1
SH		 3308 * because accessing phy registers requires spin wait which might
3309 * cause excess interrupt latency.
3310 */
9cbe330f 3311static void skge_extirq(unsigned long arg)
baef58b1 3312{
9cbe330f 3313 struct skge_hw *hw = (struct skge_hw *) arg;
baef58b1
SH		 3314 int port;
3315
cfc3ed79 3316 for (port = 0; port < hw->ports; port++) {
baef58b1
SH		 3317 struct net_device *dev = hw->dev[port];
3318
cfc3ed79 3319 if (netif_running(dev)) {
9cbe330f
SH		 3320 struct skge_port *skge = netdev_priv(dev);
3321
3322 spin_lock(&hw->phy_lock);
baef58b1
SH		 3323 if (hw->chip_id != CHIP_ID_GENESIS)
3324 yukon_phy_intr(skge);
64f6b64d 3325 else if (hw->phy_type == SK_PHY_BCOM)
45bada65 3326 bcom_phy_intr(skge);
9cbe330f 3327 spin_unlock(&hw->phy_lock);
baef58b1
SH		 3328 }
3329 }
baef58b1 3330
7c442fa1 3331 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 3332 hw->intr_mask |= IS_EXT_REG;
3333 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3334 skge_read32(hw, B0_IMSK);
7c442fa1 3335 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 3336}
3337
7d12e780 3338static irqreturn_t skge_intr(int irq, void *dev_id)
baef58b1
SH		 3339{
3340 struct skge_hw *hw = dev_id;
cfc3ed79 3341 u32 status;
29365c90 3342 int handled = 0;
baef58b1 3343
29365c90 3344 spin_lock(&hw->hw_lock);
cfc3ed79
SH		 3345 /* Reading this register masks IRQ */
3346 status = skge_read32(hw, B0_SP_ISRC);
0486a8c8 3347 if (status == 0 || status == ~0)
29365c90 3348 goto out;
baef58b1 3349
29365c90 3350 handled = 1;
7c442fa1 3351 status &= hw->intr_mask;
cfc3ed79
SH		 3352 if (status & IS_EXT_REG) {
3353 hw->intr_mask &= ~IS_EXT_REG;
9cbe330f 3354 tasklet_schedule(&hw->phy_task);
cfc3ed79
SH		 3355 }
3356
513f533e 3357 if (status & (IS_XA1_F|IS_R1_F)) {
bea3348e 3358 struct skge_port *skge = netdev_priv(hw->dev[0]);
513f533e 3359 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
288379f0 3360 napi_schedule(&skge->napi);
baef58b1
SH		 3361 }
3362
7c442fa1
SH		 3363 if (status & IS_PA_TO_TX1)
3364 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
cfc3ed79 3365
d25f5a67 3366 if (status & IS_PA_TO_RX1) {
da00772f 3367 ++hw->dev[0]->stats.rx_over_errors;
7c442fa1 3368 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
d25f5a67
SH		 3369 }
3370
d25f5a67 3371
baef58b1
SH		 3372 if (status & IS_MAC1)
3373 skge_mac_intr(hw, 0);
95566065 3374
7c442fa1 3375 if (hw->dev[1]) {
bea3348e
SH		 3376 struct skge_port *skge = netdev_priv(hw->dev[1]);
3377
513f533e
SH		 3378 if (status & (IS_XA2_F|IS_R2_F)) {
3379 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
288379f0 3380 napi_schedule(&skge->napi);
7c442fa1
SH		 3381 }
3382
3383 if (status & IS_PA_TO_RX2) {
da00772f 3384 ++hw->dev[1]->stats.rx_over_errors;
7c442fa1
SH		 3385 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3386 }
3387
3388 if (status & IS_PA_TO_TX2)
3389 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3390
3391 if (status & IS_MAC2)
3392 skge_mac_intr(hw, 1);
3393 }
baef58b1
SH		 3394
3395 if (status & IS_HW_ERR)
3396 skge_error_irq(hw);
3397
7e676d91 3398 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3399 skge_read32(hw, B0_IMSK);
29365c90 3400out:
7c442fa1 3401 spin_unlock(&hw->hw_lock);
baef58b1 3402
29365c90 3403 return IRQ_RETVAL(handled);
baef58b1
SH		 3404}
3405
3406#ifdef CONFIG_NET_POLL_CONTROLLER
3407static void skge_netpoll(struct net_device *dev)
3408{
3409 struct skge_port *skge = netdev_priv(dev);
3410
3411 disable_irq(dev->irq);
7d12e780 3412 skge_intr(dev->irq, skge->hw);
baef58b1
SH		 3413 enable_irq(dev->irq);
3414}
3415#endif
3416
3417static int skge_set_mac_address(struct net_device *dev, void *p)
3418{
3419 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 3420 struct skge_hw *hw = skge->hw;
3421 unsigned port = skge->port;
3422 const struct sockaddr *addr = p;
2eb3e621 3423 u16 ctrl;
baef58b1
SH		 3424
3425 if (!is_valid_ether_addr(addr->sa_data))
3426 return -EADDRNOTAVAIL;
3427
baef58b1 3428 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 3429
9cbe330f
SH		 3430 if (!netif_running(dev)) {
3431 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3432 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3433 } else {
3434 /* disable Rx */
3435 spin_lock_bh(&hw->phy_lock);
3436 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3437 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
2eb3e621 3438
9cbe330f
SH		 3439 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3440 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
2eb3e621 3441
2eb3e621
SH		 3442 if (hw->chip_id == CHIP_ID_GENESIS)
3443 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3444 else {
3445 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3446 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3447 }
2eb3e621 3448
9cbe330f
SH		 3449 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3450 spin_unlock_bh(&hw->phy_lock);
3451 }
c2681dd8
SH		 3452
3453 return 0;
baef58b1
SH		 3454}
3455
3456static const struct {
3457 u8 id;
3458 const char *name;
3459} skge_chips[] = {
3460 { CHIP_ID_GENESIS, "Genesis" },
3461 { CHIP_ID_YUKON, "Yukon" },
3462 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3463 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 3464};
3465
3466static const char *skge_board_name(const struct skge_hw *hw)
3467{
3468 int i;
3469 static char buf[16];
3470
3471 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3472 if (skge_chips[i].id == hw->chip_id)
3473 return skge_chips[i].name;
3474
3475 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3476 return buf;
3477}
3478
3479
3480/*
3481 * Setup the board data structure, but don't bring up
3482 * the port(s)
3483 */
3484static int skge_reset(struct skge_hw *hw)
3485{
adba9e23 3486 u32 reg;
b9d64acc 3487 u16 ctst, pci_status;
64f6b64d 3488 u8 t8, mac_cfg, pmd_type;
981d0377 3489 int i;
baef58b1
SH		 3490
3491 ctst = skge_read16(hw, B0_CTST);
3492
3493 /* do a SW reset */
3494 skge_write8(hw, B0_CTST, CS_RST_SET);
3495 skge_write8(hw, B0_CTST, CS_RST_CLR);
3496
3497 /* clear PCI errors, if any */
b9d64acc
SH		 3498 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3499 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3500
b9d64acc
SH		 3501 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3502 pci_write_config_word(hw->pdev, PCI_STATUS,
3503 pci_status | PCI_STATUS_ERROR_BITS);
3504 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3505 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3506
3507 /* restore CLK_RUN bits (for Yukon-Lite) */
3508 skge_write16(hw, B0_CTST,
3509 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3510
3511 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
64f6b64d 3512 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
5e1705dd
SH		 3513 pmd_type = skge_read8(hw, B2_PMD_TYP);
3514 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3515
95566065 3516 switch (hw->chip_id) {
baef58b1 3517 case CHIP_ID_GENESIS:
64f6b64d
SH		 3518 switch (hw->phy_type) {
3519 case SK_PHY_XMAC:
3520 hw->phy_addr = PHY_ADDR_XMAC;
3521 break;
baef58b1
SH		 3522 case SK_PHY_BCOM:
3523 hw->phy_addr = PHY_ADDR_BCOM;
3524 break;
3525 default:
1479d13c
SH		 3526 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3527 hw->phy_type);
baef58b1
SH		 3528 return -EOPNOTSUPP;
3529 }
3530 break;
3531
3532 case CHIP_ID_YUKON:
3533 case CHIP_ID_YUKON_LITE:
3534 case CHIP_ID_YUKON_LP:
64f6b64d 3535 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
5e1705dd 3536 hw->copper = 1;
baef58b1
SH		 3537
3538 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3539 break;
3540
3541 default:
1479d13c
SH		 3542 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3543 hw->chip_id);
baef58b1
SH		 3544 return -EOPNOTSUPP;
3545 }
3546
981d0377
SH		 3547 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3548 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3549 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3550
3551 /* read the adapters RAM size */
3552 t8 = skge_read8(hw, B2_E_0);
3553 if (hw->chip_id == CHIP_ID_GENESIS) {
3554 if (t8 == 3) {
3555 /* special case: 4 x 64k x 36, offset = 0x80000 */
279e1dab
LT		 3556 hw->ram_size = 0x100000;
3557 hw->ram_offset = 0x80000;
baef58b1
SH		 3558 } else
3559 hw->ram_size = t8 * 512;
67777f9b 3560 } else if (t8 == 0)
279e1dab
LT		 3561 hw->ram_size = 0x20000;
3562 else
3563 hw->ram_size = t8 * 4096;
baef58b1 3564
4ebabfcb 3565 hw->intr_mask = IS_HW_ERR;
cfc3ed79 3566
4ebabfcb 3567 /* Use PHY IRQ for all but fiber based Genesis board */
64f6b64d
SH		 3568 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3569 hw->intr_mask |= IS_EXT_REG;
3570
baef58b1
SH		 3571 if (hw->chip_id == CHIP_ID_GENESIS)
3572 genesis_init(hw);
3573 else {
3574 /* switch power to VCC (WA for VAUX problem) */
3575 skge_write8(hw, B0_POWER_CTRL,
3576 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3577
050ec18a
SH		 3578 /* avoid boards with stuck Hardware error bits */
3579 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3580 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
1479d13c 3581 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
050ec18a
SH		 3582 hw->intr_mask &= ~IS_HW_ERR;
3583 }
3584
adba9e23
SH		 3585 /* Clear PHY COMA */
3586 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3587 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3588 reg &= ~PCI_PHY_COMA;
3589 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3590 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3591
3592
981d0377 3593 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3594 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3595 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3596 }
3597 }
3598
3599 /* turn off hardware timer (unused) */
3600 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3601 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3602 skge_write8(hw, B0_LED, LED_STAT_ON);
3603
3604 /* enable the Tx Arbiters */
981d0377 3605 for (i = 0; i < hw->ports; i++)
6b0c1480 3606 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3607
3608 /* Initialize ram interface */
3609 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3610
3611 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3612 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3613 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3614 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3615 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3616 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3617 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3618 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3619 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3620 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3621 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3622 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3623
3624 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3625
3626 /* Set interrupt moderation for Transmit only
3627 * Receive interrupts avoided by NAPI
3628 */
3629 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3630 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3631 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3632
baef58b1
SH		 3633 skge_write32(hw, B0_IMSK, hw->intr_mask);
3634
981d0377 3635 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3636 if (hw->chip_id == CHIP_ID_GENESIS)
3637 genesis_reset(hw, i);
3638 else
3639 yukon_reset(hw, i);
3640 }
baef58b1
SH		 3641
3642 return 0;
3643}
3644
678aa1f6
SH		 3645
3646#ifdef CONFIG_SKGE_DEBUG
3647
3648static struct dentry *skge_debug;
3649
3650static int skge_debug_show(struct seq_file *seq, void *v)
3651{
3652 struct net_device *dev = seq->private;
3653 const struct skge_port *skge = netdev_priv(dev);
3654 const struct skge_hw *hw = skge->hw;
3655 const struct skge_element *e;
3656
3657 if (!netif_running(dev))
3658 return -ENETDOWN;
3659
3660 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3661 skge_read32(hw, B0_IMSK));
3662
3663 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3664 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3665 const struct skge_tx_desc *t = e->desc;
3666 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3667 t->control, t->dma_hi, t->dma_lo, t->status,
3668 t->csum_offs, t->csum_write, t->csum_start);
3669 }
3670
2381a55c 3671 seq_printf(seq, "\nRx Ring:\n");
678aa1f6
SH		 3672 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3673 const struct skge_rx_desc *r = e->desc;
3674
3675 if (r->control & BMU_OWN)
3676 break;
3677
3678 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3679 r->control, r->dma_hi, r->dma_lo, r->status,
3680 r->timestamp, r->csum1, r->csum1_start);
3681 }
3682
3683 return 0;
3684}
3685
3686static int skge_debug_open(struct inode *inode, struct file *file)
3687{
3688 return single_open(file, skge_debug_show, inode->i_private);
3689}
3690
3691static const struct file_operations skge_debug_fops = {
3692 .owner = THIS_MODULE,
3693 .open = skge_debug_open,
3694 .read = seq_read,
3695 .llseek = seq_lseek,
3696 .release = single_release,
3697};
3698
3699/*
3700 * Use network device events to create/remove/rename
3701 * debugfs file entries
3702 */
3703static int skge_device_event(struct notifier_block *unused,
3704 unsigned long event, void *ptr)
3705{
3706 struct net_device *dev = ptr;
3707 struct skge_port *skge;
3708 struct dentry *d;
3709
f80d032b 3710 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
678aa1f6
SH		 3711 goto done;
3712
3713 skge = netdev_priv(dev);
67777f9b 3714 switch (event) {
678aa1f6
SH		 3715 case NETDEV_CHANGENAME:
3716 if (skge->debugfs) {
3717 d = debugfs_rename(skge_debug, skge->debugfs,
3718 skge_debug, dev->name);
3719 if (d)
3720 skge->debugfs = d;
3721 else {
f15063cd 3722 netdev_info(dev, "rename failed\n");
678aa1f6
SH		 3723 debugfs_remove(skge->debugfs);
3724 }
3725 }
3726 break;
3727
3728 case NETDEV_GOING_DOWN:
3729 if (skge->debugfs) {
3730 debugfs_remove(skge->debugfs);
3731 skge->debugfs = NULL;
3732 }
3733 break;
3734
3735 case NETDEV_UP:
3736 d = debugfs_create_file(dev->name, S_IRUGO,
3737 skge_debug, dev,
3738 &skge_debug_fops);
3739 if (!d || IS_ERR(d))
f15063cd 3740 netdev_info(dev, "debugfs create failed\n");
678aa1f6
SH		 3741 else
3742 skge->debugfs = d;
3743 break;
3744 }
3745
3746done:
3747 return NOTIFY_DONE;
3748}
3749
3750static struct notifier_block skge_notifier = {
3751 .notifier_call = skge_device_event,
3752};
3753
3754
3755static __init void skge_debug_init(void)
3756{
3757 struct dentry *ent;
3758
3759 ent = debugfs_create_dir("skge", NULL);
3760 if (!ent || IS_ERR(ent)) {
f15063cd 3761 pr_info("debugfs create directory failed\n");
678aa1f6
SH		 3762 return;
3763 }
3764
3765 skge_debug = ent;
3766 register_netdevice_notifier(&skge_notifier);
3767}
3768
3769static __exit void skge_debug_cleanup(void)
3770{
3771 if (skge_debug) {
3772 unregister_netdevice_notifier(&skge_notifier);
3773 debugfs_remove(skge_debug);
3774 skge_debug = NULL;
3775 }
3776}
3777
3778#else
3779#define skge_debug_init()
3780#define skge_debug_cleanup()
3781#endif
3782
f80d032b
SH		 3783static const struct net_device_ops skge_netdev_ops = {
3784 .ndo_open = skge_up,
3785 .ndo_stop = skge_down,
00829823 3786 .ndo_start_xmit = skge_xmit_frame,
f80d032b
SH		 3787 .ndo_do_ioctl = skge_ioctl,
3788 .ndo_get_stats = skge_get_stats,
3789 .ndo_tx_timeout = skge_tx_timeout,
3790 .ndo_change_mtu = skge_change_mtu,
3791 .ndo_validate_addr = eth_validate_addr,
3792 .ndo_set_multicast_list = skge_set_multicast,
3793 .ndo_set_mac_address = skge_set_mac_address,
3794#ifdef CONFIG_NET_POLL_CONTROLLER
3795 .ndo_poll_controller = skge_netpoll,
3796#endif
3797};
3798
3799
baef58b1 3800/* Initialize network device */
981d0377
SH		 3801static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3802 int highmem)
baef58b1
SH		 3803{
3804 struct skge_port *skge;
3805 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3806
3807 if (!dev) {
1479d13c 3808 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
baef58b1
SH		 3809 return NULL;
3810 }
3811
baef58b1 3812 SET_NETDEV_DEV(dev, &hw->pdev->dev);
f80d032b
SH		 3813 dev->netdev_ops = &skge_netdev_ops;
3814 dev->ethtool_ops = &skge_ethtool_ops;
baef58b1 3815 dev->watchdog_timeo = TX_WATCHDOG;
baef58b1 3816 dev->irq = hw->pdev->irq;
513f533e 3817
981d0377
SH		 3818 if (highmem)
3819 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3820
3821 skge = netdev_priv(dev);
bea3348e 3822 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
baef58b1
SH		 3823 skge->netdev = dev;
3824 skge->hw = hw;
3825 skge->msg_enable = netif_msg_init(debug, default_msg);
9cbe330f 3826
baef58b1
SH		 3827 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3828 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3829
3830 /* Auto speed and flow control */
3831 skge->autoneg = AUTONEG_ENABLE;
5d5c8e03 3832 skge->flow_control = FLOW_MODE_SYM_OR_REM;
baef58b1
SH		 3833 skge->duplex = -1;
3834 skge->speed = -1;
31b619c5 3835 skge->advertising = skge_supported_modes(hw);
5b982c5b 3836
7b55a4a3 3837 if (device_can_wakeup(&hw->pdev->dev)) {
5b982c5b 3838 skge->wol = wol_supported(hw) & WAKE_MAGIC;
7b55a4a3
RW		 3839 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3840 }
baef58b1
SH		 3841
3842 hw->dev[port] = dev;
3843
3844 skge->port = port;
3845
64f6b64d 3846 /* Only used for Genesis XMAC */
9cbe330f 3847 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
64f6b64d 3848
baef58b1
SH		 3849 if (hw->chip_id != CHIP_ID_GENESIS) {
3850 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3851 skge->rx_csum = 1;
3852 }
86cac58b 3853 dev->features |= NETIF_F_GRO;
baef58b1
SH		 3854
3855 /* read the mac address */
3856 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3857 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3858
3859 /* device is off until link detection */
3860 netif_carrier_off(dev);
baef58b1
SH		 3861
3862 return dev;
3863}
3864
3865static void __devinit skge_show_addr(struct net_device *dev)
3866{
3867 const struct skge_port *skge = netdev_priv(dev);
3868
d707204c 3869 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
baef58b1
SH		 3870}
3871
392bd0cb
SG		 3872static int only_32bit_dma;
3873
baef58b1
SH		 3874static int __devinit skge_probe(struct pci_dev *pdev,
3875 const struct pci_device_id *ent)
3876{
3877 struct net_device *dev, *dev1;
3878 struct skge_hw *hw;
3879 int err, using_dac = 0;
3880
203babb6
SH		 3881 err = pci_enable_device(pdev);
3882 if (err) {
1479d13c 3883 dev_err(&pdev->dev, "cannot enable PCI device\n");
baef58b1
SH		 3884 goto err_out;
3885 }
3886
203babb6
SH		 3887 err = pci_request_regions(pdev, DRV_NAME);
3888 if (err) {
1479d13c 3889 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
baef58b1
SH		 3890 goto err_out_disable_pdev;
3891 }
3892
3893 pci_set_master(pdev);
3894
392bd0cb 3895 if (!only_32bit_dma && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
baef58b1 3896 using_dac = 1;
6a35528a 3897 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
284901a9 3898 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
93aea718 3899 using_dac = 0;
284901a9 3900 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
93aea718
SH		 3901 }
3902
3903 if (err) {
1479d13c 3904 dev_err(&pdev->dev, "no usable DMA configuration\n");
93aea718 3905 goto err_out_free_regions;
baef58b1
SH		 3906 }
3907
3908#ifdef __BIG_ENDIAN
8f3f8193 3909 /* byte swap descriptors in hardware */
baef58b1
SH		 3910 {
3911 u32 reg;
3912
3913 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3914 reg |= PCI_REV_DESC;
3915 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3916 }
3917#endif
3918
3919 err = -ENOMEM;
415e69e6 3920 /* space for skge@pci:0000:04:00.0 */
67777f9b 3921 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
415e69e6 3922 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
baef58b1 3923 if (!hw) {
1479d13c 3924 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
baef58b1
SH		 3925 goto err_out_free_regions;
3926 }
415e69e6 3927 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
baef58b1 3928
baef58b1 3929 hw->pdev = pdev;
d38efdd6 3930 spin_lock_init(&hw->hw_lock);
9cbe330f 3931 spin_lock_init(&hw->phy_lock);
164165da 3932 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
baef58b1
SH		 3933
3934 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3935 if (!hw->regs) {
1479d13c 3936 dev_err(&pdev->dev, "cannot map device registers\n");
baef58b1
SH		 3937 goto err_out_free_hw;
3938 }
3939
baef58b1
SH		 3940 err = skge_reset(hw);
3941 if (err)
ccdaa2a9 3942 goto err_out_iounmap;
baef58b1 3943
f15063cd
JP		 3944 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3945 DRV_VERSION,
3946 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3947 skge_board_name(hw), hw->chip_rev);
baef58b1 3948
ccdaa2a9
SH		 3949 dev = skge_devinit(hw, 0, using_dac);
3950 if (!dev)
baef58b1
SH		 3951 goto err_out_led_off;
3952
fae87592 3953 /* Some motherboards are broken and has zero in ROM. */
1479d13c
SH		 3954 if (!is_valid_ether_addr(dev->dev_addr))
3955 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
631ae320 3956
203babb6
SH		 3957 err = register_netdev(dev);
3958 if (err) {
1479d13c 3959 dev_err(&pdev->dev, "cannot register net device\n");
baef58b1
SH		 3960 goto err_out_free_netdev;
3961 }
3962
415e69e6 3963 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw);
ccdaa2a9 3964 if (err) {
1479d13c 3965 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
ccdaa2a9
SH		 3966 dev->name, pdev->irq);
3967 goto err_out_unregister;
3968 }
baef58b1
SH		 3969 skge_show_addr(dev);
3970
f1914226
MM		 3971 if (hw->ports > 1) {
3972 dev1 = skge_devinit(hw, 1, using_dac);
3973 if (dev1 && register_netdev(dev1) == 0)
baef58b1
SH		 3974 skge_show_addr(dev1);
3975 else {
3976 /* Failure to register second port need not be fatal */
1479d13c 3977 dev_warn(&pdev->dev, "register of second port failed\n");
baef58b1 3978 hw->dev[1] = NULL;
f1914226
MM		 3979 hw->ports = 1;
3980 if (dev1)
3981 free_netdev(dev1);
baef58b1
SH		 3982 }
3983 }
ccdaa2a9 3984 pci_set_drvdata(pdev, hw);
baef58b1
SH		 3985
3986 return 0;
3987
ccdaa2a9
SH		 3988err_out_unregister:
3989 unregister_netdev(dev);
baef58b1
SH		 3990err_out_free_netdev:
3991 free_netdev(dev);
3992err_out_led_off:
3993 skge_write16(hw, B0_LED, LED_STAT_OFF);
baef58b1
SH		 3994err_out_iounmap:
3995 iounmap(hw->regs);
3996err_out_free_hw:
3997 kfree(hw);
3998err_out_free_regions:
3999 pci_release_regions(pdev);
4000err_out_disable_pdev:
4001 pci_disable_device(pdev);
4002 pci_set_drvdata(pdev, NULL);
4003err_out:
4004 return err;
4005}
4006
4007static void __devexit skge_remove(struct pci_dev *pdev)
4008{
4009 struct skge_hw *hw = pci_get_drvdata(pdev);
4010 struct net_device *dev0, *dev1;
4011
95566065 4012 if (!hw)
baef58b1
SH		 4013 return;
4014
208491d8
SH		 4015 flush_scheduled_work();
4016
67777f9b
JP		 4017 dev1 = hw->dev[1];
4018 if (dev1)
baef58b1
SH		 4019 unregister_netdev(dev1);
4020 dev0 = hw->dev[0];
4021 unregister_netdev(dev0);
4022
9cbe330f
SH		 4023 tasklet_disable(&hw->phy_task);
4024
7c442fa1
SH		 4025 spin_lock_irq(&hw->hw_lock);
4026 hw->intr_mask = 0;
46a60f2d 4027 skge_write32(hw, B0_IMSK, 0);
78bc2186 4028 skge_read32(hw, B0_IMSK);
7c442fa1
SH		 4029 spin_unlock_irq(&hw->hw_lock);
4030
46a60f2d 4031 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 4032 skge_write8(hw, B0_CTST, CS_RST_SET);
4033
baef58b1
SH		 4034 free_irq(pdev->irq, hw);
4035 pci_release_regions(pdev);
4036 pci_disable_device(pdev);
4037 if (dev1)
4038 free_netdev(dev1);
4039 free_netdev(dev0);
46a60f2d 4040
baef58b1
SH		 4041 iounmap(hw->regs);
4042 kfree(hw);
4043 pci_set_drvdata(pdev, NULL);
4044}
4045
4046#ifdef CONFIG_PM
2a569579 4047static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 4048{
4049 struct skge_hw *hw = pci_get_drvdata(pdev);
a504e64a
SH		 4050 int i, err, wol = 0;
4051
e3b7df17
SH		 4052 if (!hw)
4053 return 0;
4054
a504e64a
SH		 4055 err = pci_save_state(pdev);
4056 if (err)
4057 return err;
baef58b1 4058
d38efdd6 4059 for (i = 0; i < hw->ports; i++) {
baef58b1 4060 struct net_device *dev = hw->dev[i];
a504e64a 4061 struct skge_port *skge = netdev_priv(dev);
baef58b1 4062
a504e64a
SH		 4063 if (netif_running(dev))
4064 skge_down(dev);
4065 if (skge->wol)
4066 skge_wol_init(skge);
d38efdd6 4067
a504e64a 4068 wol |= skge->wol;
baef58b1
SH		 4069 }
4070
d38efdd6 4071 skge_write32(hw, B0_IMSK, 0);
5177b324
RW		 4072
4073 pci_prepare_to_sleep(pdev);
baef58b1
SH		 4074
4075 return 0;
4076}
4077
4078static int skge_resume(struct pci_dev *pdev)
4079{
4080 struct skge_hw *hw = pci_get_drvdata(pdev);
d38efdd6 4081 int i, err;
baef58b1 4082
e3b7df17
SH		 4083 if (!hw)
4084 return 0;
4085
5177b324 4086 err = pci_back_from_sleep(pdev);
a504e64a
SH		 4087 if (err)
4088 goto out;
4089
4090 err = pci_restore_state(pdev);
4091 if (err)
4092 goto out;
4093
d38efdd6
SH		 4094 err = skge_reset(hw);
4095 if (err)
4096 goto out;
baef58b1 4097
d38efdd6 4098 for (i = 0; i < hw->ports; i++) {
baef58b1 4099 struct net_device *dev = hw->dev[i];
d38efdd6 4100
d38efdd6
SH		 4101 if (netif_running(dev)) {
4102 err = skge_up(dev);
4103
4104 if (err) {
f15063cd 4105 netdev_err(dev, "could not up: %d\n", err);
edd702e8 4106 dev_close(dev);
d38efdd6
SH		 4107 goto out;
4108 }
baef58b1
SH		 4109 }
4110 }
d38efdd6
SH		 4111out:
4112 return err;
baef58b1
SH		 4113}
4114#endif
4115
692412b3
SH		 4116static void skge_shutdown(struct pci_dev *pdev)
4117{
4118 struct skge_hw *hw = pci_get_drvdata(pdev);
4119 int i, wol = 0;
4120
e3b7df17
SH		 4121 if (!hw)
4122 return;
4123
692412b3
SH		 4124 for (i = 0; i < hw->ports; i++) {
4125 struct net_device *dev = hw->dev[i];
4126 struct skge_port *skge = netdev_priv(dev);
4127
4128 if (skge->wol)
4129 skge_wol_init(skge);
4130 wol |= skge->wol;
4131 }
4132
5177b324
RW		 4133 if (pci_enable_wake(pdev, PCI_D3cold, wol))
4134 pci_enable_wake(pdev, PCI_D3hot, wol);
692412b3
SH		 4135
4136 pci_disable_device(pdev);
4137 pci_set_power_state(pdev, PCI_D3hot);
4138
4139}
4140
baef58b1
SH		 4141static struct pci_driver skge_driver = {
4142 .name = DRV_NAME,
4143 .id_table = skge_id_table,
4144 .probe = skge_probe,
4145 .remove = __devexit_p(skge_remove),
4146#ifdef CONFIG_PM
4147 .suspend = skge_suspend,
4148 .resume = skge_resume,
4149#endif
692412b3 4150 .shutdown = skge_shutdown,
baef58b1
SH		 4151};
4152
392bd0cb
SG		 4153static struct dmi_system_id skge_32bit_dma_boards[] = {
4154 {
4155 .ident = "Gigabyte nForce boards",
4156 .matches = {
4157 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4158 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4159 },
4160 },
4161 {}
4162};
4163
baef58b1
SH		 4164static int __init skge_init_module(void)
4165{
392bd0cb
SG		 4166 if (dmi_check_system(skge_32bit_dma_boards))
4167 only_32bit_dma = 1;
678aa1f6 4168 skge_debug_init();
29917620 4169 return pci_register_driver(&skge_driver);
baef58b1
SH		 4170}
4171
4172static void __exit skge_cleanup_module(void)
4173{
4174 pci_unregister_driver(&skge_driver);
678aa1f6 4175 skge_debug_cleanup();
baef58b1
SH		 4176}
4177
4178module_init(skge_init_module);
4179module_exit(skge_cleanup_module);
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