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Commit | Line | Data |
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baef58b1 SH |
1 | /* |
2 | * New driver for Marvell Yukon chipset and SysKonnect Gigabit | |
3 | * Ethernet adapters. Based on earlier sk98lin, e100 and | |
4 | * FreeBSD if_sk drivers. | |
5 | * | |
6 | * This driver intentionally does not support all the features | |
7 | * of the original driver such as link fail-over and link management because | |
8 | * those should be done at higher levels. | |
9 | * | |
747802ab | 10 | * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org> |
baef58b1 SH |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
798b6b19 | 14 | * the Free Software Foundation; either version 2 of the License. |
baef58b1 SH |
15 | * |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
14c85021 | 26 | #include <linux/in.h> |
baef58b1 SH |
27 | #include <linux/kernel.h> |
28 | #include <linux/module.h> | |
29 | #include <linux/moduleparam.h> | |
30 | #include <linux/netdevice.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/ethtool.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/if_vlan.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/crc32.h> | |
4075400b | 38 | #include <linux/dma-mapping.h> |
2cd8e5d3 | 39 | #include <linux/mii.h> |
baef58b1 SH |
40 | #include <asm/irq.h> |
41 | ||
42 | #include "skge.h" | |
43 | ||
44 | #define DRV_NAME "skge" | |
a407a6a0 | 45 | #define DRV_VERSION "1.10" |
baef58b1 SH |
46 | #define PFX DRV_NAME " " |
47 | ||
48 | #define DEFAULT_TX_RING_SIZE 128 | |
49 | #define DEFAULT_RX_RING_SIZE 512 | |
50 | #define MAX_TX_RING_SIZE 1024 | |
9db96479 | 51 | #define TX_LOW_WATER (MAX_SKB_FRAGS + 1) |
baef58b1 | 52 | #define MAX_RX_RING_SIZE 4096 |
19a33d4e SH |
53 | #define RX_COPY_THRESHOLD 128 |
54 | #define RX_BUF_SIZE 1536 | |
baef58b1 SH |
55 | #define PHY_RETRIES 1000 |
56 | #define ETH_JUMBO_MTU 9000 | |
57 | #define TX_WATCHDOG (5 * HZ) | |
58 | #define NAPI_WEIGHT 64 | |
6abebb53 | 59 | #define BLINK_MS 250 |
64f6b64d | 60 | #define LINK_HZ (HZ/2) |
baef58b1 SH |
61 | |
62 | MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver"); | |
65ebe634 | 63 | MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); |
baef58b1 SH |
64 | MODULE_LICENSE("GPL"); |
65 | MODULE_VERSION(DRV_VERSION); | |
66 | ||
67 | static const u32 default_msg | |
68 | = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK | |
69 | | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN; | |
70 | ||
71 | static int debug = -1; /* defaults above */ | |
72 | module_param(debug, int, 0); | |
73 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
74 | ||
75 | static const struct pci_device_id skge_id_table[] = { | |
275834d1 SH |
76 | { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) }, |
77 | { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) }, | |
78 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) }, | |
79 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) }, | |
275834d1 | 80 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), }, |
2d2a3871 | 81 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */ |
275834d1 SH |
82 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, |
83 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */ | |
84 | { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) }, | |
275834d1 | 85 | { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) }, |
86f0cd50 | 86 | { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, }, |
baef58b1 SH |
87 | { 0 } |
88 | }; | |
89 | MODULE_DEVICE_TABLE(pci, skge_id_table); | |
90 | ||
91 | static int skge_up(struct net_device *dev); | |
92 | static int skge_down(struct net_device *dev); | |
ee294dcd | 93 | static void skge_phy_reset(struct skge_port *skge); |
513f533e | 94 | static void skge_tx_clean(struct net_device *dev); |
2cd8e5d3 SH |
95 | static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); |
96 | static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); | |
baef58b1 SH |
97 | static void genesis_get_stats(struct skge_port *skge, u64 *data); |
98 | static void yukon_get_stats(struct skge_port *skge, u64 *data); | |
99 | static void yukon_init(struct skge_hw *hw, int port); | |
baef58b1 | 100 | static void genesis_mac_init(struct skge_hw *hw, int port); |
45bada65 | 101 | static void genesis_link_up(struct skge_port *skge); |
baef58b1 | 102 | |
7e676d91 | 103 | /* Avoid conditionals by using array */ |
baef58b1 SH |
104 | static const int txqaddr[] = { Q_XA1, Q_XA2 }; |
105 | static const int rxqaddr[] = { Q_R1, Q_R2 }; | |
106 | static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F }; | |
107 | static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F }; | |
513f533e | 108 | static const u32 irqmask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F }; |
baef58b1 | 109 | |
baef58b1 SH |
110 | static int skge_get_regs_len(struct net_device *dev) |
111 | { | |
c3f8be96 | 112 | return 0x4000; |
baef58b1 SH |
113 | } |
114 | ||
115 | /* | |
c3f8be96 SH |
116 | * Returns copy of whole control register region |
117 | * Note: skip RAM address register because accessing it will | |
118 | * cause bus hangs! | |
baef58b1 SH |
119 | */ |
120 | static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
121 | void *p) | |
122 | { | |
123 | const struct skge_port *skge = netdev_priv(dev); | |
baef58b1 | 124 | const void __iomem *io = skge->hw->regs; |
baef58b1 SH |
125 | |
126 | regs->version = 1; | |
c3f8be96 SH |
127 | memset(p, 0, regs->len); |
128 | memcpy_fromio(p, io, B3_RAM_ADDR); | |
baef58b1 | 129 | |
c3f8be96 SH |
130 | memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, |
131 | regs->len - B3_RI_WTO_R1); | |
baef58b1 SH |
132 | } |
133 | ||
8f3f8193 | 134 | /* Wake on Lan only supported on Yukon chips with rev 1 or above */ |
a504e64a | 135 | static u32 wol_supported(const struct skge_hw *hw) |
baef58b1 | 136 | { |
a504e64a SH |
137 | if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev != 0) |
138 | return WAKE_MAGIC | WAKE_PHY; | |
139 | else | |
140 | return 0; | |
141 | } | |
142 | ||
143 | static u32 pci_wake_enabled(struct pci_dev *dev) | |
144 | { | |
145 | int pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
146 | u16 value; | |
147 | ||
148 | /* If device doesn't support PM Capabilities, but request is to disable | |
149 | * wake events, it's a nop; otherwise fail */ | |
150 | if (!pm) | |
151 | return 0; | |
152 | ||
153 | pci_read_config_word(dev, pm + PCI_PM_PMC, &value); | |
154 | ||
155 | value &= PCI_PM_CAP_PME_MASK; | |
156 | value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ | |
157 | ||
158 | return value != 0; | |
159 | } | |
160 | ||
161 | static void skge_wol_init(struct skge_port *skge) | |
162 | { | |
163 | struct skge_hw *hw = skge->hw; | |
164 | int port = skge->port; | |
165 | enum pause_control save_mode; | |
166 | u32 ctrl; | |
167 | ||
168 | /* Bring hardware out of reset */ | |
169 | skge_write16(hw, B0_CTST, CS_RST_CLR); | |
170 | skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
171 | ||
172 | skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
173 | skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
174 | ||
175 | /* Force to 10/100 skge_reset will re-enable on resume */ | |
176 | save_mode = skge->flow_control; | |
177 | skge->flow_control = FLOW_MODE_SYMMETRIC; | |
178 | ||
179 | ctrl = skge->advertising; | |
180 | skge->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); | |
181 | ||
182 | skge_phy_reset(skge); | |
183 | ||
184 | skge->flow_control = save_mode; | |
185 | skge->advertising = ctrl; | |
186 | ||
187 | /* Set GMAC to no flow control and auto update for speed/duplex */ | |
188 | gma_write16(hw, port, GM_GP_CTRL, | |
189 | GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| | |
190 | GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); | |
191 | ||
192 | /* Set WOL address */ | |
193 | memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), | |
194 | skge->netdev->dev_addr, ETH_ALEN); | |
195 | ||
196 | /* Turn on appropriate WOL control bits */ | |
197 | skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); | |
198 | ctrl = 0; | |
199 | if (skge->wol & WAKE_PHY) | |
200 | ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; | |
201 | else | |
202 | ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; | |
203 | ||
204 | if (skge->wol & WAKE_MAGIC) | |
205 | ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; | |
206 | else | |
207 | ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;; | |
208 | ||
209 | ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; | |
210 | skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); | |
211 | ||
212 | /* block receiver */ | |
213 | skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
baef58b1 SH |
214 | } |
215 | ||
216 | static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
217 | { | |
218 | struct skge_port *skge = netdev_priv(dev); | |
219 | ||
a504e64a SH |
220 | wol->supported = wol_supported(skge->hw); |
221 | wol->wolopts = skge->wol; | |
baef58b1 SH |
222 | } |
223 | ||
224 | static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
225 | { | |
226 | struct skge_port *skge = netdev_priv(dev); | |
227 | struct skge_hw *hw = skge->hw; | |
228 | ||
a504e64a | 229 | if (wol->wolopts & wol_supported(hw)) |
baef58b1 SH |
230 | return -EOPNOTSUPP; |
231 | ||
a504e64a SH |
232 | skge->wol = wol->wolopts; |
233 | if (!netif_running(dev)) | |
234 | skge_wol_init(skge); | |
baef58b1 SH |
235 | return 0; |
236 | } | |
237 | ||
8f3f8193 SH |
238 | /* Determine supported/advertised modes based on hardware. |
239 | * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx | |
31b619c5 SH |
240 | */ |
241 | static u32 skge_supported_modes(const struct skge_hw *hw) | |
242 | { | |
243 | u32 supported; | |
244 | ||
5e1705dd | 245 | if (hw->copper) { |
31b619c5 SH |
246 | supported = SUPPORTED_10baseT_Half |
247 | | SUPPORTED_10baseT_Full | |
248 | | SUPPORTED_100baseT_Half | |
249 | | SUPPORTED_100baseT_Full | |
250 | | SUPPORTED_1000baseT_Half | |
251 | | SUPPORTED_1000baseT_Full | |
252 | | SUPPORTED_Autoneg| SUPPORTED_TP; | |
253 | ||
254 | if (hw->chip_id == CHIP_ID_GENESIS) | |
255 | supported &= ~(SUPPORTED_10baseT_Half | |
256 | | SUPPORTED_10baseT_Full | |
257 | | SUPPORTED_100baseT_Half | |
258 | | SUPPORTED_100baseT_Full); | |
259 | ||
260 | else if (hw->chip_id == CHIP_ID_YUKON) | |
261 | supported &= ~SUPPORTED_1000baseT_Half; | |
262 | } else | |
4b67be99 SH |
263 | supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half |
264 | | SUPPORTED_FIBRE | SUPPORTED_Autoneg; | |
31b619c5 SH |
265 | |
266 | return supported; | |
267 | } | |
baef58b1 SH |
268 | |
269 | static int skge_get_settings(struct net_device *dev, | |
270 | struct ethtool_cmd *ecmd) | |
271 | { | |
272 | struct skge_port *skge = netdev_priv(dev); | |
273 | struct skge_hw *hw = skge->hw; | |
274 | ||
275 | ecmd->transceiver = XCVR_INTERNAL; | |
31b619c5 | 276 | ecmd->supported = skge_supported_modes(hw); |
baef58b1 | 277 | |
5e1705dd | 278 | if (hw->copper) { |
baef58b1 SH |
279 | ecmd->port = PORT_TP; |
280 | ecmd->phy_address = hw->phy_addr; | |
31b619c5 | 281 | } else |
baef58b1 | 282 | ecmd->port = PORT_FIBRE; |
baef58b1 SH |
283 | |
284 | ecmd->advertising = skge->advertising; | |
285 | ecmd->autoneg = skge->autoneg; | |
286 | ecmd->speed = skge->speed; | |
287 | ecmd->duplex = skge->duplex; | |
288 | return 0; | |
289 | } | |
290 | ||
baef58b1 SH |
291 | static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
292 | { | |
293 | struct skge_port *skge = netdev_priv(dev); | |
294 | const struct skge_hw *hw = skge->hw; | |
31b619c5 | 295 | u32 supported = skge_supported_modes(hw); |
baef58b1 SH |
296 | |
297 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
31b619c5 SH |
298 | ecmd->advertising = supported; |
299 | skge->duplex = -1; | |
300 | skge->speed = -1; | |
baef58b1 | 301 | } else { |
31b619c5 SH |
302 | u32 setting; |
303 | ||
2c668514 | 304 | switch (ecmd->speed) { |
baef58b1 | 305 | case SPEED_1000: |
31b619c5 SH |
306 | if (ecmd->duplex == DUPLEX_FULL) |
307 | setting = SUPPORTED_1000baseT_Full; | |
308 | else if (ecmd->duplex == DUPLEX_HALF) | |
309 | setting = SUPPORTED_1000baseT_Half; | |
310 | else | |
311 | return -EINVAL; | |
baef58b1 SH |
312 | break; |
313 | case SPEED_100: | |
31b619c5 SH |
314 | if (ecmd->duplex == DUPLEX_FULL) |
315 | setting = SUPPORTED_100baseT_Full; | |
316 | else if (ecmd->duplex == DUPLEX_HALF) | |
317 | setting = SUPPORTED_100baseT_Half; | |
318 | else | |
319 | return -EINVAL; | |
320 | break; | |
321 | ||
baef58b1 | 322 | case SPEED_10: |
31b619c5 SH |
323 | if (ecmd->duplex == DUPLEX_FULL) |
324 | setting = SUPPORTED_10baseT_Full; | |
325 | else if (ecmd->duplex == DUPLEX_HALF) | |
326 | setting = SUPPORTED_10baseT_Half; | |
327 | else | |
baef58b1 SH |
328 | return -EINVAL; |
329 | break; | |
330 | default: | |
331 | return -EINVAL; | |
332 | } | |
31b619c5 SH |
333 | |
334 | if ((setting & supported) == 0) | |
335 | return -EINVAL; | |
336 | ||
337 | skge->speed = ecmd->speed; | |
338 | skge->duplex = ecmd->duplex; | |
baef58b1 SH |
339 | } |
340 | ||
341 | skge->autoneg = ecmd->autoneg; | |
baef58b1 SH |
342 | skge->advertising = ecmd->advertising; |
343 | ||
ee294dcd SH |
344 | if (netif_running(dev)) |
345 | skge_phy_reset(skge); | |
346 | ||
baef58b1 SH |
347 | return (0); |
348 | } | |
349 | ||
350 | static void skge_get_drvinfo(struct net_device *dev, | |
351 | struct ethtool_drvinfo *info) | |
352 | { | |
353 | struct skge_port *skge = netdev_priv(dev); | |
354 | ||
355 | strcpy(info->driver, DRV_NAME); | |
356 | strcpy(info->version, DRV_VERSION); | |
357 | strcpy(info->fw_version, "N/A"); | |
358 | strcpy(info->bus_info, pci_name(skge->hw->pdev)); | |
359 | } | |
360 | ||
361 | static const struct skge_stat { | |
362 | char name[ETH_GSTRING_LEN]; | |
363 | u16 xmac_offset; | |
364 | u16 gma_offset; | |
365 | } skge_stats[] = { | |
366 | { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI }, | |
367 | { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI }, | |
368 | ||
369 | { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK }, | |
370 | { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK }, | |
371 | { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK }, | |
372 | { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK }, | |
373 | { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK }, | |
374 | { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK }, | |
375 | { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE }, | |
376 | { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE }, | |
377 | ||
378 | { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL }, | |
379 | { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL }, | |
380 | { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL }, | |
381 | { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL }, | |
382 | { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR }, | |
383 | { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV }, | |
384 | ||
385 | { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, | |
386 | { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT }, | |
387 | { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG }, | |
388 | { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, | |
389 | { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR }, | |
390 | }; | |
391 | ||
392 | static int skge_get_stats_count(struct net_device *dev) | |
393 | { | |
394 | return ARRAY_SIZE(skge_stats); | |
395 | } | |
396 | ||
397 | static void skge_get_ethtool_stats(struct net_device *dev, | |
398 | struct ethtool_stats *stats, u64 *data) | |
399 | { | |
400 | struct skge_port *skge = netdev_priv(dev); | |
401 | ||
402 | if (skge->hw->chip_id == CHIP_ID_GENESIS) | |
403 | genesis_get_stats(skge, data); | |
404 | else | |
405 | yukon_get_stats(skge, data); | |
406 | } | |
407 | ||
408 | /* Use hardware MIB variables for critical path statistics and | |
409 | * transmit feedback not reported at interrupt. | |
410 | * Other errors are accounted for in interrupt handler. | |
411 | */ | |
412 | static struct net_device_stats *skge_get_stats(struct net_device *dev) | |
413 | { | |
414 | struct skge_port *skge = netdev_priv(dev); | |
415 | u64 data[ARRAY_SIZE(skge_stats)]; | |
416 | ||
417 | if (skge->hw->chip_id == CHIP_ID_GENESIS) | |
418 | genesis_get_stats(skge, data); | |
419 | else | |
420 | yukon_get_stats(skge, data); | |
421 | ||
422 | skge->net_stats.tx_bytes = data[0]; | |
423 | skge->net_stats.rx_bytes = data[1]; | |
424 | skge->net_stats.tx_packets = data[2] + data[4] + data[6]; | |
425 | skge->net_stats.rx_packets = data[3] + data[5] + data[7]; | |
4c180fc4 | 426 | skge->net_stats.multicast = data[3] + data[5]; |
baef58b1 SH |
427 | skge->net_stats.collisions = data[10]; |
428 | skge->net_stats.tx_aborted_errors = data[12]; | |
429 | ||
430 | return &skge->net_stats; | |
431 | } | |
432 | ||
433 | static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
434 | { | |
435 | int i; | |
436 | ||
95566065 | 437 | switch (stringset) { |
baef58b1 SH |
438 | case ETH_SS_STATS: |
439 | for (i = 0; i < ARRAY_SIZE(skge_stats); i++) | |
440 | memcpy(data + i * ETH_GSTRING_LEN, | |
441 | skge_stats[i].name, ETH_GSTRING_LEN); | |
442 | break; | |
443 | } | |
444 | } | |
445 | ||
446 | static void skge_get_ring_param(struct net_device *dev, | |
447 | struct ethtool_ringparam *p) | |
448 | { | |
449 | struct skge_port *skge = netdev_priv(dev); | |
450 | ||
451 | p->rx_max_pending = MAX_RX_RING_SIZE; | |
452 | p->tx_max_pending = MAX_TX_RING_SIZE; | |
453 | p->rx_mini_max_pending = 0; | |
454 | p->rx_jumbo_max_pending = 0; | |
455 | ||
456 | p->rx_pending = skge->rx_ring.count; | |
457 | p->tx_pending = skge->tx_ring.count; | |
458 | p->rx_mini_pending = 0; | |
459 | p->rx_jumbo_pending = 0; | |
460 | } | |
461 | ||
462 | static int skge_set_ring_param(struct net_device *dev, | |
463 | struct ethtool_ringparam *p) | |
464 | { | |
465 | struct skge_port *skge = netdev_priv(dev); | |
3b8bb472 | 466 | int err; |
baef58b1 SH |
467 | |
468 | if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE || | |
9db96479 | 469 | p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE) |
baef58b1 SH |
470 | return -EINVAL; |
471 | ||
472 | skge->rx_ring.count = p->rx_pending; | |
473 | skge->tx_ring.count = p->tx_pending; | |
474 | ||
475 | if (netif_running(dev)) { | |
476 | skge_down(dev); | |
3b8bb472 SH |
477 | err = skge_up(dev); |
478 | if (err) | |
479 | dev_close(dev); | |
baef58b1 SH |
480 | } |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | static u32 skge_get_msglevel(struct net_device *netdev) | |
486 | { | |
487 | struct skge_port *skge = netdev_priv(netdev); | |
488 | return skge->msg_enable; | |
489 | } | |
490 | ||
491 | static void skge_set_msglevel(struct net_device *netdev, u32 value) | |
492 | { | |
493 | struct skge_port *skge = netdev_priv(netdev); | |
494 | skge->msg_enable = value; | |
495 | } | |
496 | ||
497 | static int skge_nway_reset(struct net_device *dev) | |
498 | { | |
499 | struct skge_port *skge = netdev_priv(dev); | |
baef58b1 SH |
500 | |
501 | if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev)) | |
502 | return -EINVAL; | |
503 | ||
ee294dcd | 504 | skge_phy_reset(skge); |
baef58b1 SH |
505 | return 0; |
506 | } | |
507 | ||
508 | static int skge_set_sg(struct net_device *dev, u32 data) | |
509 | { | |
510 | struct skge_port *skge = netdev_priv(dev); | |
511 | struct skge_hw *hw = skge->hw; | |
512 | ||
513 | if (hw->chip_id == CHIP_ID_GENESIS && data) | |
514 | return -EOPNOTSUPP; | |
515 | return ethtool_op_set_sg(dev, data); | |
516 | } | |
517 | ||
518 | static int skge_set_tx_csum(struct net_device *dev, u32 data) | |
519 | { | |
520 | struct skge_port *skge = netdev_priv(dev); | |
521 | struct skge_hw *hw = skge->hw; | |
522 | ||
523 | if (hw->chip_id == CHIP_ID_GENESIS && data) | |
524 | return -EOPNOTSUPP; | |
525 | ||
526 | return ethtool_op_set_tx_csum(dev, data); | |
527 | } | |
528 | ||
529 | static u32 skge_get_rx_csum(struct net_device *dev) | |
530 | { | |
531 | struct skge_port *skge = netdev_priv(dev); | |
532 | ||
533 | return skge->rx_csum; | |
534 | } | |
535 | ||
536 | /* Only Yukon supports checksum offload. */ | |
537 | static int skge_set_rx_csum(struct net_device *dev, u32 data) | |
538 | { | |
539 | struct skge_port *skge = netdev_priv(dev); | |
540 | ||
541 | if (skge->hw->chip_id == CHIP_ID_GENESIS && data) | |
542 | return -EOPNOTSUPP; | |
543 | ||
544 | skge->rx_csum = data; | |
545 | return 0; | |
546 | } | |
547 | ||
baef58b1 SH |
548 | static void skge_get_pauseparam(struct net_device *dev, |
549 | struct ethtool_pauseparam *ecmd) | |
550 | { | |
551 | struct skge_port *skge = netdev_priv(dev); | |
552 | ||
5d5c8e03 SH |
553 | ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC) |
554 | || (skge->flow_control == FLOW_MODE_SYM_OR_REM); | |
555 | ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND); | |
baef58b1 | 556 | |
5d5c8e03 | 557 | ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause; |
baef58b1 SH |
558 | } |
559 | ||
560 | static int skge_set_pauseparam(struct net_device *dev, | |
561 | struct ethtool_pauseparam *ecmd) | |
562 | { | |
563 | struct skge_port *skge = netdev_priv(dev); | |
5d5c8e03 | 564 | struct ethtool_pauseparam old; |
baef58b1 | 565 | |
5d5c8e03 SH |
566 | skge_get_pauseparam(dev, &old); |
567 | ||
568 | if (ecmd->autoneg != old.autoneg) | |
569 | skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC; | |
570 | else { | |
571 | if (ecmd->rx_pause && ecmd->tx_pause) | |
572 | skge->flow_control = FLOW_MODE_SYMMETRIC; | |
573 | else if (ecmd->rx_pause && !ecmd->tx_pause) | |
574 | skge->flow_control = FLOW_MODE_SYM_OR_REM; | |
575 | else if (!ecmd->rx_pause && ecmd->tx_pause) | |
576 | skge->flow_control = FLOW_MODE_LOC_SEND; | |
577 | else | |
578 | skge->flow_control = FLOW_MODE_NONE; | |
579 | } | |
baef58b1 | 580 | |
e8df8554 SH |
581 | if (netif_running(dev)) |
582 | skge_phy_reset(skge); | |
5d5c8e03 | 583 | |
baef58b1 SH |
584 | return 0; |
585 | } | |
586 | ||
587 | /* Chip internal frequency for clock calculations */ | |
588 | static inline u32 hwkhz(const struct skge_hw *hw) | |
589 | { | |
187ff3b8 | 590 | return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125; |
baef58b1 SH |
591 | } |
592 | ||
8f3f8193 | 593 | /* Chip HZ to microseconds */ |
baef58b1 SH |
594 | static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks) |
595 | { | |
596 | return (ticks * 1000) / hwkhz(hw); | |
597 | } | |
598 | ||
8f3f8193 | 599 | /* Microseconds to chip HZ */ |
baef58b1 SH |
600 | static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec) |
601 | { | |
602 | return hwkhz(hw) * usec / 1000; | |
603 | } | |
604 | ||
605 | static int skge_get_coalesce(struct net_device *dev, | |
606 | struct ethtool_coalesce *ecmd) | |
607 | { | |
608 | struct skge_port *skge = netdev_priv(dev); | |
609 | struct skge_hw *hw = skge->hw; | |
610 | int port = skge->port; | |
611 | ||
612 | ecmd->rx_coalesce_usecs = 0; | |
613 | ecmd->tx_coalesce_usecs = 0; | |
614 | ||
615 | if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) { | |
616 | u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI)); | |
617 | u32 msk = skge_read32(hw, B2_IRQM_MSK); | |
618 | ||
619 | if (msk & rxirqmask[port]) | |
620 | ecmd->rx_coalesce_usecs = delay; | |
621 | if (msk & txirqmask[port]) | |
622 | ecmd->tx_coalesce_usecs = delay; | |
623 | } | |
624 | ||
625 | return 0; | |
626 | } | |
627 | ||
628 | /* Note: interrupt timer is per board, but can turn on/off per port */ | |
629 | static int skge_set_coalesce(struct net_device *dev, | |
630 | struct ethtool_coalesce *ecmd) | |
631 | { | |
632 | struct skge_port *skge = netdev_priv(dev); | |
633 | struct skge_hw *hw = skge->hw; | |
634 | int port = skge->port; | |
635 | u32 msk = skge_read32(hw, B2_IRQM_MSK); | |
636 | u32 delay = 25; | |
637 | ||
638 | if (ecmd->rx_coalesce_usecs == 0) | |
639 | msk &= ~rxirqmask[port]; | |
640 | else if (ecmd->rx_coalesce_usecs < 25 || | |
641 | ecmd->rx_coalesce_usecs > 33333) | |
642 | return -EINVAL; | |
643 | else { | |
644 | msk |= rxirqmask[port]; | |
645 | delay = ecmd->rx_coalesce_usecs; | |
646 | } | |
647 | ||
648 | if (ecmd->tx_coalesce_usecs == 0) | |
649 | msk &= ~txirqmask[port]; | |
650 | else if (ecmd->tx_coalesce_usecs < 25 || | |
651 | ecmd->tx_coalesce_usecs > 33333) | |
652 | return -EINVAL; | |
653 | else { | |
654 | msk |= txirqmask[port]; | |
655 | delay = min(delay, ecmd->rx_coalesce_usecs); | |
656 | } | |
657 | ||
658 | skge_write32(hw, B2_IRQM_MSK, msk); | |
659 | if (msk == 0) | |
660 | skge_write32(hw, B2_IRQM_CTRL, TIM_STOP); | |
661 | else { | |
662 | skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay)); | |
663 | skge_write32(hw, B2_IRQM_CTRL, TIM_START); | |
664 | } | |
665 | return 0; | |
666 | } | |
667 | ||
6abebb53 SH |
668 | enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST }; |
669 | static void skge_led(struct skge_port *skge, enum led_mode mode) | |
baef58b1 | 670 | { |
6abebb53 SH |
671 | struct skge_hw *hw = skge->hw; |
672 | int port = skge->port; | |
673 | ||
d85b514f | 674 | mutex_lock(&hw->phy_mutex); |
baef58b1 | 675 | if (hw->chip_id == CHIP_ID_GENESIS) { |
6abebb53 SH |
676 | switch (mode) { |
677 | case LED_MODE_OFF: | |
64f6b64d SH |
678 | if (hw->phy_type == SK_PHY_BCOM) |
679 | xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF); | |
680 | else { | |
681 | skge_write32(hw, SK_REG(port, TX_LED_VAL), 0); | |
682 | skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF); | |
683 | } | |
6abebb53 SH |
684 | skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); |
685 | skge_write32(hw, SK_REG(port, RX_LED_VAL), 0); | |
686 | skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF); | |
687 | break; | |
baef58b1 | 688 | |
6abebb53 SH |
689 | case LED_MODE_ON: |
690 | skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON); | |
691 | skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); | |
baef58b1 | 692 | |
6abebb53 SH |
693 | skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); |
694 | skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); | |
baef58b1 | 695 | |
6abebb53 | 696 | break; |
baef58b1 | 697 | |
6abebb53 SH |
698 | case LED_MODE_TST: |
699 | skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON); | |
700 | skge_write32(hw, SK_REG(port, RX_LED_VAL), 100); | |
701 | skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); | |
baef58b1 | 702 | |
64f6b64d SH |
703 | if (hw->phy_type == SK_PHY_BCOM) |
704 | xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON); | |
705 | else { | |
706 | skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON); | |
707 | skge_write32(hw, SK_REG(port, TX_LED_VAL), 100); | |
708 | skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); | |
709 | } | |
710 | ||
6abebb53 | 711 | } |
baef58b1 | 712 | } else { |
6abebb53 SH |
713 | switch (mode) { |
714 | case LED_MODE_OFF: | |
715 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
716 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, | |
717 | PHY_M_LED_MO_DUP(MO_LED_OFF) | | |
718 | PHY_M_LED_MO_10(MO_LED_OFF) | | |
719 | PHY_M_LED_MO_100(MO_LED_OFF) | | |
720 | PHY_M_LED_MO_1000(MO_LED_OFF) | | |
721 | PHY_M_LED_MO_RX(MO_LED_OFF)); | |
722 | break; | |
723 | case LED_MODE_ON: | |
724 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, | |
725 | PHY_M_LED_PULS_DUR(PULS_170MS) | | |
726 | PHY_M_LED_BLINK_RT(BLINK_84MS) | | |
727 | PHY_M_LEDC_TX_CTRL | | |
728 | PHY_M_LEDC_DP_CTRL); | |
46a60f2d | 729 | |
6abebb53 SH |
730 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
731 | PHY_M_LED_MO_RX(MO_LED_OFF) | | |
732 | (skge->speed == SPEED_100 ? | |
733 | PHY_M_LED_MO_100(MO_LED_ON) : 0)); | |
734 | break; | |
735 | case LED_MODE_TST: | |
736 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
737 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, | |
738 | PHY_M_LED_MO_DUP(MO_LED_ON) | | |
739 | PHY_M_LED_MO_10(MO_LED_ON) | | |
740 | PHY_M_LED_MO_100(MO_LED_ON) | | |
741 | PHY_M_LED_MO_1000(MO_LED_ON) | | |
742 | PHY_M_LED_MO_RX(MO_LED_ON)); | |
743 | } | |
baef58b1 | 744 | } |
d85b514f | 745 | mutex_unlock(&hw->phy_mutex); |
baef58b1 SH |
746 | } |
747 | ||
748 | /* blink LED's for finding board */ | |
749 | static int skge_phys_id(struct net_device *dev, u32 data) | |
750 | { | |
751 | struct skge_port *skge = netdev_priv(dev); | |
6abebb53 SH |
752 | unsigned long ms; |
753 | enum led_mode mode = LED_MODE_TST; | |
baef58b1 | 754 | |
95566065 | 755 | if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)) |
6abebb53 SH |
756 | ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000; |
757 | else | |
758 | ms = data * 1000; | |
baef58b1 | 759 | |
6abebb53 SH |
760 | while (ms > 0) { |
761 | skge_led(skge, mode); | |
762 | mode ^= LED_MODE_TST; | |
baef58b1 | 763 | |
6abebb53 SH |
764 | if (msleep_interruptible(BLINK_MS)) |
765 | break; | |
766 | ms -= BLINK_MS; | |
767 | } | |
baef58b1 | 768 | |
6abebb53 SH |
769 | /* back to regular LED state */ |
770 | skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF); | |
baef58b1 SH |
771 | |
772 | return 0; | |
773 | } | |
774 | ||
7282d491 | 775 | static const struct ethtool_ops skge_ethtool_ops = { |
baef58b1 SH |
776 | .get_settings = skge_get_settings, |
777 | .set_settings = skge_set_settings, | |
778 | .get_drvinfo = skge_get_drvinfo, | |
779 | .get_regs_len = skge_get_regs_len, | |
780 | .get_regs = skge_get_regs, | |
781 | .get_wol = skge_get_wol, | |
782 | .set_wol = skge_set_wol, | |
783 | .get_msglevel = skge_get_msglevel, | |
784 | .set_msglevel = skge_set_msglevel, | |
785 | .nway_reset = skge_nway_reset, | |
786 | .get_link = ethtool_op_get_link, | |
787 | .get_ringparam = skge_get_ring_param, | |
788 | .set_ringparam = skge_set_ring_param, | |
789 | .get_pauseparam = skge_get_pauseparam, | |
790 | .set_pauseparam = skge_set_pauseparam, | |
791 | .get_coalesce = skge_get_coalesce, | |
792 | .set_coalesce = skge_set_coalesce, | |
baef58b1 SH |
793 | .get_sg = ethtool_op_get_sg, |
794 | .set_sg = skge_set_sg, | |
795 | .get_tx_csum = ethtool_op_get_tx_csum, | |
796 | .set_tx_csum = skge_set_tx_csum, | |
797 | .get_rx_csum = skge_get_rx_csum, | |
798 | .set_rx_csum = skge_set_rx_csum, | |
799 | .get_strings = skge_get_strings, | |
800 | .phys_id = skge_phys_id, | |
801 | .get_stats_count = skge_get_stats_count, | |
802 | .get_ethtool_stats = skge_get_ethtool_stats, | |
56230d53 | 803 | .get_perm_addr = ethtool_op_get_perm_addr, |
baef58b1 SH |
804 | }; |
805 | ||
806 | /* | |
807 | * Allocate ring elements and chain them together | |
808 | * One-to-one association of board descriptors with ring elements | |
809 | */ | |
c3da1447 | 810 | static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base) |
baef58b1 SH |
811 | { |
812 | struct skge_tx_desc *d; | |
813 | struct skge_element *e; | |
814 | int i; | |
815 | ||
cd861280 | 816 | ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL); |
baef58b1 SH |
817 | if (!ring->start) |
818 | return -ENOMEM; | |
819 | ||
820 | for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) { | |
821 | e->desc = d; | |
822 | if (i == ring->count - 1) { | |
823 | e->next = ring->start; | |
824 | d->next_offset = base; | |
825 | } else { | |
826 | e->next = e + 1; | |
827 | d->next_offset = base + (i+1) * sizeof(*d); | |
828 | } | |
829 | } | |
830 | ring->to_use = ring->to_clean = ring->start; | |
831 | ||
832 | return 0; | |
833 | } | |
834 | ||
19a33d4e SH |
835 | /* Allocate and setup a new buffer for receiving */ |
836 | static void skge_rx_setup(struct skge_port *skge, struct skge_element *e, | |
837 | struct sk_buff *skb, unsigned int bufsize) | |
838 | { | |
839 | struct skge_rx_desc *rd = e->desc; | |
840 | u64 map; | |
baef58b1 SH |
841 | |
842 | map = pci_map_single(skge->hw->pdev, skb->data, bufsize, | |
843 | PCI_DMA_FROMDEVICE); | |
844 | ||
845 | rd->dma_lo = map; | |
846 | rd->dma_hi = map >> 32; | |
847 | e->skb = skb; | |
848 | rd->csum1_start = ETH_HLEN; | |
849 | rd->csum2_start = ETH_HLEN; | |
850 | rd->csum1 = 0; | |
851 | rd->csum2 = 0; | |
852 | ||
853 | wmb(); | |
854 | ||
855 | rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize; | |
856 | pci_unmap_addr_set(e, mapaddr, map); | |
857 | pci_unmap_len_set(e, maplen, bufsize); | |
baef58b1 SH |
858 | } |
859 | ||
19a33d4e SH |
860 | /* Resume receiving using existing skb, |
861 | * Note: DMA address is not changed by chip. | |
862 | * MTU not changed while receiver active. | |
863 | */ | |
5a011447 | 864 | static inline void skge_rx_reuse(struct skge_element *e, unsigned int size) |
19a33d4e SH |
865 | { |
866 | struct skge_rx_desc *rd = e->desc; | |
867 | ||
868 | rd->csum2 = 0; | |
869 | rd->csum2_start = ETH_HLEN; | |
870 | ||
871 | wmb(); | |
872 | ||
873 | rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size; | |
874 | } | |
875 | ||
876 | ||
877 | /* Free all buffers in receive ring, assumes receiver stopped */ | |
baef58b1 SH |
878 | static void skge_rx_clean(struct skge_port *skge) |
879 | { | |
880 | struct skge_hw *hw = skge->hw; | |
881 | struct skge_ring *ring = &skge->rx_ring; | |
882 | struct skge_element *e; | |
883 | ||
19a33d4e SH |
884 | e = ring->start; |
885 | do { | |
baef58b1 SH |
886 | struct skge_rx_desc *rd = e->desc; |
887 | rd->control = 0; | |
19a33d4e SH |
888 | if (e->skb) { |
889 | pci_unmap_single(hw->pdev, | |
890 | pci_unmap_addr(e, mapaddr), | |
891 | pci_unmap_len(e, maplen), | |
892 | PCI_DMA_FROMDEVICE); | |
893 | dev_kfree_skb(e->skb); | |
894 | e->skb = NULL; | |
895 | } | |
896 | } while ((e = e->next) != ring->start); | |
baef58b1 SH |
897 | } |
898 | ||
19a33d4e | 899 | |
baef58b1 | 900 | /* Allocate buffers for receive ring |
19a33d4e | 901 | * For receive: to_clean is next received frame. |
baef58b1 | 902 | */ |
c54f9765 | 903 | static int skge_rx_fill(struct net_device *dev) |
baef58b1 | 904 | { |
c54f9765 | 905 | struct skge_port *skge = netdev_priv(dev); |
baef58b1 SH |
906 | struct skge_ring *ring = &skge->rx_ring; |
907 | struct skge_element *e; | |
baef58b1 | 908 | |
19a33d4e SH |
909 | e = ring->start; |
910 | do { | |
383181ac | 911 | struct sk_buff *skb; |
baef58b1 | 912 | |
c54f9765 SH |
913 | skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN, |
914 | GFP_KERNEL); | |
19a33d4e SH |
915 | if (!skb) |
916 | return -ENOMEM; | |
917 | ||
383181ac SH |
918 | skb_reserve(skb, NET_IP_ALIGN); |
919 | skge_rx_setup(skge, e, skb, skge->rx_buf_size); | |
19a33d4e | 920 | } while ( (e = e->next) != ring->start); |
baef58b1 | 921 | |
19a33d4e SH |
922 | ring->to_clean = ring->start; |
923 | return 0; | |
baef58b1 SH |
924 | } |
925 | ||
5d5c8e03 SH |
926 | static const char *skge_pause(enum pause_status status) |
927 | { | |
928 | switch(status) { | |
929 | case FLOW_STAT_NONE: | |
930 | return "none"; | |
931 | case FLOW_STAT_REM_SEND: | |
932 | return "rx only"; | |
933 | case FLOW_STAT_LOC_SEND: | |
934 | return "tx_only"; | |
935 | case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */ | |
936 | return "both"; | |
937 | default: | |
938 | return "indeterminated"; | |
939 | } | |
940 | } | |
941 | ||
942 | ||
baef58b1 SH |
943 | static void skge_link_up(struct skge_port *skge) |
944 | { | |
46a60f2d | 945 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), |
54cfb5aa SH |
946 | LED_BLK_OFF|LED_SYNC_OFF|LED_ON); |
947 | ||
baef58b1 | 948 | netif_carrier_on(skge->netdev); |
29b4e886 | 949 | netif_wake_queue(skge->netdev); |
baef58b1 | 950 | |
5d5c8e03 | 951 | if (netif_msg_link(skge)) { |
baef58b1 SH |
952 | printk(KERN_INFO PFX |
953 | "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", | |
954 | skge->netdev->name, skge->speed, | |
955 | skge->duplex == DUPLEX_FULL ? "full" : "half", | |
5d5c8e03 SH |
956 | skge_pause(skge->flow_status)); |
957 | } | |
baef58b1 SH |
958 | } |
959 | ||
960 | static void skge_link_down(struct skge_port *skge) | |
961 | { | |
54cfb5aa | 962 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); |
baef58b1 SH |
963 | netif_carrier_off(skge->netdev); |
964 | netif_stop_queue(skge->netdev); | |
965 | ||
966 | if (netif_msg_link(skge)) | |
967 | printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name); | |
968 | } | |
969 | ||
a1bc9b87 SH |
970 | |
971 | static void xm_link_down(struct skge_hw *hw, int port) | |
972 | { | |
973 | struct net_device *dev = hw->dev[port]; | |
974 | struct skge_port *skge = netdev_priv(dev); | |
975 | u16 cmd, msk; | |
976 | ||
977 | if (hw->phy_type == SK_PHY_XMAC) { | |
978 | msk = xm_read16(hw, port, XM_IMSK); | |
979 | msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND; | |
980 | xm_write16(hw, port, XM_IMSK, msk); | |
981 | } | |
982 | ||
983 | cmd = xm_read16(hw, port, XM_MMU_CMD); | |
984 | cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX); | |
985 | xm_write16(hw, port, XM_MMU_CMD, cmd); | |
986 | /* dummy read to ensure writing */ | |
987 | (void) xm_read16(hw, port, XM_MMU_CMD); | |
988 | ||
989 | if (netif_carrier_ok(dev)) | |
990 | skge_link_down(skge); | |
991 | } | |
992 | ||
2cd8e5d3 | 993 | static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) |
baef58b1 SH |
994 | { |
995 | int i; | |
baef58b1 | 996 | |
6b0c1480 | 997 | xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); |
0781191c | 998 | *val = xm_read16(hw, port, XM_PHY_DATA); |
baef58b1 | 999 | |
64f6b64d SH |
1000 | if (hw->phy_type == SK_PHY_XMAC) |
1001 | goto ready; | |
1002 | ||
89bf5f23 | 1003 | for (i = 0; i < PHY_RETRIES; i++) { |
2cd8e5d3 | 1004 | if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY) |
89bf5f23 | 1005 | goto ready; |
0781191c | 1006 | udelay(1); |
baef58b1 SH |
1007 | } |
1008 | ||
2cd8e5d3 | 1009 | return -ETIMEDOUT; |
89bf5f23 | 1010 | ready: |
2cd8e5d3 | 1011 | *val = xm_read16(hw, port, XM_PHY_DATA); |
89bf5f23 | 1012 | |
2cd8e5d3 SH |
1013 | return 0; |
1014 | } | |
1015 | ||
1016 | static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg) | |
1017 | { | |
1018 | u16 v = 0; | |
1019 | if (__xm_phy_read(hw, port, reg, &v)) | |
1020 | printk(KERN_WARNING PFX "%s: phy read timed out\n", | |
1021 | hw->dev[port]->name); | |
baef58b1 SH |
1022 | return v; |
1023 | } | |
1024 | ||
2cd8e5d3 | 1025 | static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) |
baef58b1 SH |
1026 | { |
1027 | int i; | |
1028 | ||
6b0c1480 | 1029 | xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); |
baef58b1 | 1030 | for (i = 0; i < PHY_RETRIES; i++) { |
6b0c1480 | 1031 | if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) |
baef58b1 | 1032 | goto ready; |
89bf5f23 | 1033 | udelay(1); |
baef58b1 | 1034 | } |
2cd8e5d3 | 1035 | return -EIO; |
baef58b1 SH |
1036 | |
1037 | ready: | |
6b0c1480 | 1038 | xm_write16(hw, port, XM_PHY_DATA, val); |
0781191c SH |
1039 | for (i = 0; i < PHY_RETRIES; i++) { |
1040 | if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) | |
1041 | return 0; | |
1042 | udelay(1); | |
1043 | } | |
1044 | return -ETIMEDOUT; | |
baef58b1 SH |
1045 | } |
1046 | ||
1047 | static void genesis_init(struct skge_hw *hw) | |
1048 | { | |
1049 | /* set blink source counter */ | |
1050 | skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100); | |
1051 | skge_write8(hw, B2_BSC_CTRL, BSC_START); | |
1052 | ||
1053 | /* configure mac arbiter */ | |
1054 | skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); | |
1055 | ||
1056 | /* configure mac arbiter timeout values */ | |
1057 | skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53); | |
1058 | skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53); | |
1059 | skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53); | |
1060 | skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53); | |
1061 | ||
1062 | skge_write8(hw, B3_MA_RCINI_RX1, 0); | |
1063 | skge_write8(hw, B3_MA_RCINI_RX2, 0); | |
1064 | skge_write8(hw, B3_MA_RCINI_TX1, 0); | |
1065 | skge_write8(hw, B3_MA_RCINI_TX2, 0); | |
1066 | ||
1067 | /* configure packet arbiter timeout */ | |
1068 | skge_write16(hw, B3_PA_CTRL, PA_RST_CLR); | |
1069 | skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); | |
1070 | skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); | |
1071 | skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); | |
1072 | skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); | |
1073 | } | |
1074 | ||
1075 | static void genesis_reset(struct skge_hw *hw, int port) | |
1076 | { | |
45bada65 | 1077 | const u8 zero[8] = { 0 }; |
baef58b1 | 1078 | |
46a60f2d SH |
1079 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); |
1080 | ||
baef58b1 | 1081 | /* reset the statistics module */ |
6b0c1480 SH |
1082 | xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); |
1083 | xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */ | |
1084 | xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ | |
1085 | xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ | |
1086 | xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ | |
baef58b1 | 1087 | |
89bf5f23 | 1088 | /* disable Broadcom PHY IRQ */ |
64f6b64d SH |
1089 | if (hw->phy_type == SK_PHY_BCOM) |
1090 | xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); | |
baef58b1 | 1091 | |
45bada65 | 1092 | xm_outhash(hw, port, XM_HSM, zero); |
baef58b1 SH |
1093 | } |
1094 | ||
1095 | ||
45bada65 SH |
1096 | /* Convert mode to MII values */ |
1097 | static const u16 phy_pause_map[] = { | |
1098 | [FLOW_MODE_NONE] = 0, | |
1099 | [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM, | |
1100 | [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP, | |
5d5c8e03 | 1101 | [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM, |
45bada65 SH |
1102 | }; |
1103 | ||
4b67be99 SH |
1104 | /* special defines for FIBER (88E1011S only) */ |
1105 | static const u16 fiber_pause_map[] = { | |
1106 | [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE, | |
1107 | [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD, | |
1108 | [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD, | |
5d5c8e03 | 1109 | [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD, |
4b67be99 SH |
1110 | }; |
1111 | ||
45bada65 SH |
1112 | |
1113 | /* Check status of Broadcom phy link */ | |
1114 | static void bcom_check_link(struct skge_hw *hw, int port) | |
baef58b1 | 1115 | { |
45bada65 SH |
1116 | struct net_device *dev = hw->dev[port]; |
1117 | struct skge_port *skge = netdev_priv(dev); | |
1118 | u16 status; | |
1119 | ||
1120 | /* read twice because of latch */ | |
1121 | (void) xm_phy_read(hw, port, PHY_BCOM_STAT); | |
1122 | status = xm_phy_read(hw, port, PHY_BCOM_STAT); | |
1123 | ||
45bada65 | 1124 | if ((status & PHY_ST_LSYNC) == 0) { |
a1bc9b87 | 1125 | xm_link_down(hw, port); |
64f6b64d SH |
1126 | return; |
1127 | } | |
45bada65 | 1128 | |
64f6b64d SH |
1129 | if (skge->autoneg == AUTONEG_ENABLE) { |
1130 | u16 lpa, aux; | |
45bada65 | 1131 | |
64f6b64d SH |
1132 | if (!(status & PHY_ST_AN_OVER)) |
1133 | return; | |
45bada65 | 1134 | |
64f6b64d SH |
1135 | lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); |
1136 | if (lpa & PHY_B_AN_RF) { | |
1137 | printk(KERN_NOTICE PFX "%s: remote fault\n", | |
1138 | dev->name); | |
1139 | return; | |
1140 | } | |
45bada65 | 1141 | |
64f6b64d SH |
1142 | aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT); |
1143 | ||
1144 | /* Check Duplex mismatch */ | |
1145 | switch (aux & PHY_B_AS_AN_RES_MSK) { | |
1146 | case PHY_B_RES_1000FD: | |
1147 | skge->duplex = DUPLEX_FULL; | |
1148 | break; | |
1149 | case PHY_B_RES_1000HD: | |
1150 | skge->duplex = DUPLEX_HALF; | |
1151 | break; | |
1152 | default: | |
1153 | printk(KERN_NOTICE PFX "%s: duplex mismatch\n", | |
1154 | dev->name); | |
1155 | return; | |
45bada65 SH |
1156 | } |
1157 | ||
64f6b64d SH |
1158 | /* We are using IEEE 802.3z/D5.0 Table 37-4 */ |
1159 | switch (aux & PHY_B_AS_PAUSE_MSK) { | |
1160 | case PHY_B_AS_PAUSE_MSK: | |
5d5c8e03 | 1161 | skge->flow_status = FLOW_STAT_SYMMETRIC; |
64f6b64d SH |
1162 | break; |
1163 | case PHY_B_AS_PRR: | |
5d5c8e03 | 1164 | skge->flow_status = FLOW_STAT_REM_SEND; |
64f6b64d SH |
1165 | break; |
1166 | case PHY_B_AS_PRT: | |
5d5c8e03 | 1167 | skge->flow_status = FLOW_STAT_LOC_SEND; |
64f6b64d SH |
1168 | break; |
1169 | default: | |
5d5c8e03 | 1170 | skge->flow_status = FLOW_STAT_NONE; |
64f6b64d SH |
1171 | } |
1172 | skge->speed = SPEED_1000; | |
45bada65 | 1173 | } |
64f6b64d SH |
1174 | |
1175 | if (!netif_carrier_ok(dev)) | |
1176 | genesis_link_up(skge); | |
45bada65 SH |
1177 | } |
1178 | ||
1179 | /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional | |
1180 | * Phy on for 100 or 10Mbit operation | |
1181 | */ | |
64f6b64d | 1182 | static void bcom_phy_init(struct skge_port *skge) |
45bada65 SH |
1183 | { |
1184 | struct skge_hw *hw = skge->hw; | |
1185 | int port = skge->port; | |
baef58b1 | 1186 | int i; |
45bada65 | 1187 | u16 id1, r, ext, ctl; |
baef58b1 SH |
1188 | |
1189 | /* magic workaround patterns for Broadcom */ | |
1190 | static const struct { | |
1191 | u16 reg; | |
1192 | u16 val; | |
1193 | } A1hack[] = { | |
1194 | { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, | |
1195 | { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 }, | |
1196 | { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 }, | |
1197 | { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, | |
1198 | }, C0hack[] = { | |
1199 | { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, | |
1200 | { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 }, | |
1201 | }; | |
1202 | ||
45bada65 SH |
1203 | /* read Id from external PHY (all have the same address) */ |
1204 | id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); | |
1205 | ||
1206 | /* Optimize MDIO transfer by suppressing preamble. */ | |
1207 | r = xm_read16(hw, port, XM_MMU_CMD); | |
1208 | r |= XM_MMU_NO_PRE; | |
1209 | xm_write16(hw, port, XM_MMU_CMD,r); | |
1210 | ||
2c668514 | 1211 | switch (id1) { |
45bada65 SH |
1212 | case PHY_BCOM_ID1_C0: |
1213 | /* | |
1214 | * Workaround BCOM Errata for the C0 type. | |
1215 | * Write magic patterns to reserved registers. | |
1216 | */ | |
1217 | for (i = 0; i < ARRAY_SIZE(C0hack); i++) | |
1218 | xm_phy_write(hw, port, | |
1219 | C0hack[i].reg, C0hack[i].val); | |
1220 | ||
1221 | break; | |
1222 | case PHY_BCOM_ID1_A1: | |
1223 | /* | |
1224 | * Workaround BCOM Errata for the A1 type. | |
1225 | * Write magic patterns to reserved registers. | |
1226 | */ | |
1227 | for (i = 0; i < ARRAY_SIZE(A1hack); i++) | |
1228 | xm_phy_write(hw, port, | |
1229 | A1hack[i].reg, A1hack[i].val); | |
1230 | break; | |
1231 | } | |
1232 | ||
1233 | /* | |
1234 | * Workaround BCOM Errata (#10523) for all BCom PHYs. | |
1235 | * Disable Power Management after reset. | |
1236 | */ | |
1237 | r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL); | |
1238 | r |= PHY_B_AC_DIS_PM; | |
1239 | xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r); | |
1240 | ||
1241 | /* Dummy read */ | |
1242 | xm_read16(hw, port, XM_ISRC); | |
1243 | ||
1244 | ext = PHY_B_PEC_EN_LTR; /* enable tx led */ | |
1245 | ctl = PHY_CT_SP1000; /* always 1000mbit */ | |
1246 | ||
1247 | if (skge->autoneg == AUTONEG_ENABLE) { | |
1248 | /* | |
1249 | * Workaround BCOM Errata #1 for the C5 type. | |
1250 | * 1000Base-T Link Acquisition Failure in Slave Mode | |
1251 | * Set Repeater/DTE bit 10 of the 1000Base-T Control Register | |
1252 | */ | |
1253 | u16 adv = PHY_B_1000C_RD; | |
1254 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1255 | adv |= PHY_B_1000C_AHD; | |
1256 | if (skge->advertising & ADVERTISED_1000baseT_Full) | |
1257 | adv |= PHY_B_1000C_AFD; | |
1258 | xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv); | |
1259 | ||
1260 | ctl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
1261 | } else { | |
1262 | if (skge->duplex == DUPLEX_FULL) | |
1263 | ctl |= PHY_CT_DUP_MD; | |
1264 | /* Force to slave */ | |
1265 | xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE); | |
1266 | } | |
1267 | ||
1268 | /* Set autonegotiation pause parameters */ | |
1269 | xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, | |
1270 | phy_pause_map[skge->flow_control] | PHY_AN_CSMA); | |
1271 | ||
1272 | /* Handle Jumbo frames */ | |
64f6b64d | 1273 | if (hw->dev[port]->mtu > ETH_DATA_LEN) { |
45bada65 SH |
1274 | xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, |
1275 | PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK); | |
1276 | ||
1277 | ext |= PHY_B_PEC_HIGH_LA; | |
1278 | ||
1279 | } | |
1280 | ||
1281 | xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext); | |
1282 | xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl); | |
1283 | ||
8f3f8193 | 1284 | /* Use link status change interrupt */ |
45bada65 | 1285 | xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); |
64f6b64d | 1286 | } |
45bada65 | 1287 | |
64f6b64d SH |
1288 | static void xm_phy_init(struct skge_port *skge) |
1289 | { | |
1290 | struct skge_hw *hw = skge->hw; | |
1291 | int port = skge->port; | |
1292 | u16 ctrl = 0; | |
1293 | ||
1294 | if (skge->autoneg == AUTONEG_ENABLE) { | |
1295 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1296 | ctrl |= PHY_X_AN_HD; | |
1297 | if (skge->advertising & ADVERTISED_1000baseT_Full) | |
1298 | ctrl |= PHY_X_AN_FD; | |
1299 | ||
4b67be99 | 1300 | ctrl |= fiber_pause_map[skge->flow_control]; |
64f6b64d SH |
1301 | |
1302 | xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl); | |
1303 | ||
1304 | /* Restart Auto-negotiation */ | |
1305 | ctrl = PHY_CT_ANE | PHY_CT_RE_CFG; | |
1306 | } else { | |
1307 | /* Set DuplexMode in Config register */ | |
1308 | if (skge->duplex == DUPLEX_FULL) | |
1309 | ctrl |= PHY_CT_DUP_MD; | |
1310 | /* | |
1311 | * Do NOT enable Auto-negotiation here. This would hold | |
1312 | * the link down because no IDLEs are transmitted | |
1313 | */ | |
1314 | } | |
1315 | ||
1316 | xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl); | |
1317 | ||
1318 | /* Poll PHY for status changes */ | |
1319 | schedule_delayed_work(&skge->link_thread, LINK_HZ); | |
1320 | } | |
1321 | ||
1322 | static void xm_check_link(struct net_device *dev) | |
1323 | { | |
1324 | struct skge_port *skge = netdev_priv(dev); | |
1325 | struct skge_hw *hw = skge->hw; | |
1326 | int port = skge->port; | |
1327 | u16 status; | |
1328 | ||
1329 | /* read twice because of latch */ | |
1330 | (void) xm_phy_read(hw, port, PHY_XMAC_STAT); | |
1331 | status = xm_phy_read(hw, port, PHY_XMAC_STAT); | |
1332 | ||
1333 | if ((status & PHY_ST_LSYNC) == 0) { | |
a1bc9b87 | 1334 | xm_link_down(hw, port); |
64f6b64d SH |
1335 | return; |
1336 | } | |
1337 | ||
1338 | if (skge->autoneg == AUTONEG_ENABLE) { | |
1339 | u16 lpa, res; | |
1340 | ||
1341 | if (!(status & PHY_ST_AN_OVER)) | |
1342 | return; | |
1343 | ||
1344 | lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); | |
1345 | if (lpa & PHY_B_AN_RF) { | |
1346 | printk(KERN_NOTICE PFX "%s: remote fault\n", | |
1347 | dev->name); | |
1348 | return; | |
1349 | } | |
1350 | ||
1351 | res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI); | |
1352 | ||
1353 | /* Check Duplex mismatch */ | |
1354 | switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) { | |
1355 | case PHY_X_RS_FD: | |
1356 | skge->duplex = DUPLEX_FULL; | |
1357 | break; | |
1358 | case PHY_X_RS_HD: | |
1359 | skge->duplex = DUPLEX_HALF; | |
1360 | break; | |
1361 | default: | |
1362 | printk(KERN_NOTICE PFX "%s: duplex mismatch\n", | |
1363 | dev->name); | |
1364 | return; | |
1365 | } | |
1366 | ||
1367 | /* We are using IEEE 802.3z/D5.0 Table 37-4 */ | |
5d5c8e03 SH |
1368 | if ((skge->flow_control == FLOW_MODE_SYMMETRIC || |
1369 | skge->flow_control == FLOW_MODE_SYM_OR_REM) && | |
1370 | (lpa & PHY_X_P_SYM_MD)) | |
1371 | skge->flow_status = FLOW_STAT_SYMMETRIC; | |
1372 | else if (skge->flow_control == FLOW_MODE_SYM_OR_REM && | |
1373 | (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) | |
1374 | /* Enable PAUSE receive, disable PAUSE transmit */ | |
1375 | skge->flow_status = FLOW_STAT_REM_SEND; | |
1376 | else if (skge->flow_control == FLOW_MODE_LOC_SEND && | |
1377 | (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) | |
1378 | /* Disable PAUSE receive, enable PAUSE transmit */ | |
1379 | skge->flow_status = FLOW_STAT_LOC_SEND; | |
64f6b64d | 1380 | else |
5d5c8e03 | 1381 | skge->flow_status = FLOW_STAT_NONE; |
64f6b64d SH |
1382 | |
1383 | skge->speed = SPEED_1000; | |
1384 | } | |
1385 | ||
1386 | if (!netif_carrier_ok(dev)) | |
1387 | genesis_link_up(skge); | |
1388 | } | |
1389 | ||
1390 | /* Poll to check for link coming up. | |
1391 | * Since internal PHY is wired to a level triggered pin, can't | |
1392 | * get an interrupt when carrier is detected. | |
1393 | */ | |
c4028958 | 1394 | static void xm_link_timer(struct work_struct *work) |
64f6b64d | 1395 | { |
c4028958 DH |
1396 | struct skge_port *skge = |
1397 | container_of(work, struct skge_port, link_thread.work); | |
1398 | struct net_device *dev = skge->netdev; | |
64f6b64d SH |
1399 | struct skge_hw *hw = skge->hw; |
1400 | int port = skge->port; | |
1401 | ||
1402 | if (!netif_running(dev)) | |
1403 | return; | |
1404 | ||
1405 | if (netif_carrier_ok(dev)) { | |
1406 | xm_read16(hw, port, XM_ISRC); | |
1407 | if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)) | |
1408 | goto nochange; | |
1409 | } else { | |
1410 | if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS) | |
1411 | goto nochange; | |
1412 | xm_read16(hw, port, XM_ISRC); | |
1413 | if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS) | |
1414 | goto nochange; | |
1415 | } | |
1416 | ||
1417 | mutex_lock(&hw->phy_mutex); | |
1418 | xm_check_link(dev); | |
1419 | mutex_unlock(&hw->phy_mutex); | |
1420 | ||
1421 | nochange: | |
1422 | schedule_delayed_work(&skge->link_thread, LINK_HZ); | |
45bada65 SH |
1423 | } |
1424 | ||
1425 | static void genesis_mac_init(struct skge_hw *hw, int port) | |
1426 | { | |
1427 | struct net_device *dev = hw->dev[port]; | |
1428 | struct skge_port *skge = netdev_priv(dev); | |
1429 | int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN; | |
1430 | int i; | |
1431 | u32 r; | |
1432 | const u8 zero[6] = { 0 }; | |
1433 | ||
0781191c SH |
1434 | for (i = 0; i < 10; i++) { |
1435 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), | |
1436 | MFF_SET_MAC_RST); | |
1437 | if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST) | |
1438 | goto reset_ok; | |
1439 | udelay(1); | |
1440 | } | |
baef58b1 | 1441 | |
0781191c SH |
1442 | printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name); |
1443 | ||
1444 | reset_ok: | |
baef58b1 | 1445 | /* Unreset the XMAC. */ |
6b0c1480 | 1446 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); |
baef58b1 SH |
1447 | |
1448 | /* | |
1449 | * Perform additional initialization for external PHYs, | |
1450 | * namely for the 1000baseTX cards that use the XMAC's | |
1451 | * GMII mode. | |
1452 | */ | |
64f6b64d SH |
1453 | if (hw->phy_type != SK_PHY_XMAC) { |
1454 | /* Take external Phy out of reset */ | |
1455 | r = skge_read32(hw, B2_GP_IO); | |
1456 | if (port == 0) | |
1457 | r |= GP_DIR_0|GP_IO_0; | |
1458 | else | |
1459 | r |= GP_DIR_2|GP_IO_2; | |
89bf5f23 | 1460 | |
64f6b64d | 1461 | skge_write32(hw, B2_GP_IO, r); |
0781191c | 1462 | |
64f6b64d SH |
1463 | /* Enable GMII interface */ |
1464 | xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); | |
1465 | } | |
89bf5f23 | 1466 | |
89bf5f23 | 1467 | |
64f6b64d SH |
1468 | switch(hw->phy_type) { |
1469 | case SK_PHY_XMAC: | |
1470 | xm_phy_init(skge); | |
1471 | break; | |
1472 | case SK_PHY_BCOM: | |
1473 | bcom_phy_init(skge); | |
1474 | bcom_check_link(hw, port); | |
1475 | } | |
89bf5f23 | 1476 | |
45bada65 SH |
1477 | /* Set Station Address */ |
1478 | xm_outaddr(hw, port, XM_SA, dev->dev_addr); | |
89bf5f23 | 1479 | |
45bada65 SH |
1480 | /* We don't use match addresses so clear */ |
1481 | for (i = 1; i < 16; i++) | |
1482 | xm_outaddr(hw, port, XM_EXM(i), zero); | |
1483 | ||
0781191c SH |
1484 | /* Clear MIB counters */ |
1485 | xm_write16(hw, port, XM_STAT_CMD, | |
1486 | XM_SC_CLR_RXC | XM_SC_CLR_TXC); | |
1487 | /* Clear two times according to Errata #3 */ | |
1488 | xm_write16(hw, port, XM_STAT_CMD, | |
1489 | XM_SC_CLR_RXC | XM_SC_CLR_TXC); | |
1490 | ||
45bada65 SH |
1491 | /* configure Rx High Water Mark (XM_RX_HI_WM) */ |
1492 | xm_write16(hw, port, XM_RX_HI_WM, 1450); | |
1493 | ||
1494 | /* We don't need the FCS appended to the packet. */ | |
1495 | r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS; | |
1496 | if (jumbo) | |
1497 | r |= XM_RX_BIG_PK_OK; | |
89bf5f23 | 1498 | |
45bada65 | 1499 | if (skge->duplex == DUPLEX_HALF) { |
89bf5f23 | 1500 | /* |
45bada65 SH |
1501 | * If in manual half duplex mode the other side might be in |
1502 | * full duplex mode, so ignore if a carrier extension is not seen | |
1503 | * on frames received | |
89bf5f23 | 1504 | */ |
45bada65 | 1505 | r |= XM_RX_DIS_CEXT; |
baef58b1 | 1506 | } |
45bada65 | 1507 | xm_write16(hw, port, XM_RX_CMD, r); |
baef58b1 | 1508 | |
baef58b1 SH |
1509 | |
1510 | /* We want short frames padded to 60 bytes. */ | |
45bada65 SH |
1511 | xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD); |
1512 | ||
1513 | /* | |
1514 | * Bump up the transmit threshold. This helps hold off transmit | |
1515 | * underruns when we're blasting traffic from both ports at once. | |
1516 | */ | |
1517 | xm_write16(hw, port, XM_TX_THR, 512); | |
baef58b1 SH |
1518 | |
1519 | /* | |
1520 | * Enable the reception of all error frames. This is is | |
1521 | * a necessary evil due to the design of the XMAC. The | |
1522 | * XMAC's receive FIFO is only 8K in size, however jumbo | |
1523 | * frames can be up to 9000 bytes in length. When bad | |
1524 | * frame filtering is enabled, the XMAC's RX FIFO operates | |
1525 | * in 'store and forward' mode. For this to work, the | |
1526 | * entire frame has to fit into the FIFO, but that means | |
1527 | * that jumbo frames larger than 8192 bytes will be | |
1528 | * truncated. Disabling all bad frame filtering causes | |
1529 | * the RX FIFO to operate in streaming mode, in which | |
8f3f8193 | 1530 | * case the XMAC will start transferring frames out of the |
baef58b1 SH |
1531 | * RX FIFO as soon as the FIFO threshold is reached. |
1532 | */ | |
45bada65 | 1533 | xm_write32(hw, port, XM_MODE, XM_DEF_MODE); |
baef58b1 | 1534 | |
baef58b1 SH |
1535 | |
1536 | /* | |
45bada65 SH |
1537 | * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK) |
1538 | * - Enable all bits excepting 'Octets Rx OK Low CntOv' | |
1539 | * and 'Octets Rx OK Hi Cnt Ov'. | |
baef58b1 | 1540 | */ |
45bada65 SH |
1541 | xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK); |
1542 | ||
1543 | /* | |
1544 | * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK) | |
1545 | * - Enable all bits excepting 'Octets Tx OK Low CntOv' | |
1546 | * and 'Octets Tx OK Hi Cnt Ov'. | |
1547 | */ | |
1548 | xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK); | |
baef58b1 SH |
1549 | |
1550 | /* Configure MAC arbiter */ | |
1551 | skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); | |
1552 | ||
1553 | /* configure timeout values */ | |
1554 | skge_write8(hw, B3_MA_TOINI_RX1, 72); | |
1555 | skge_write8(hw, B3_MA_TOINI_RX2, 72); | |
1556 | skge_write8(hw, B3_MA_TOINI_TX1, 72); | |
1557 | skge_write8(hw, B3_MA_TOINI_TX2, 72); | |
1558 | ||
1559 | skge_write8(hw, B3_MA_RCINI_RX1, 0); | |
1560 | skge_write8(hw, B3_MA_RCINI_RX2, 0); | |
1561 | skge_write8(hw, B3_MA_RCINI_TX1, 0); | |
1562 | skge_write8(hw, B3_MA_RCINI_TX2, 0); | |
1563 | ||
1564 | /* Configure Rx MAC FIFO */ | |
6b0c1480 SH |
1565 | skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); |
1566 | skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); | |
1567 | skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); | |
baef58b1 SH |
1568 | |
1569 | /* Configure Tx MAC FIFO */ | |
6b0c1480 SH |
1570 | skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); |
1571 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); | |
1572 | skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); | |
baef58b1 | 1573 | |
45bada65 | 1574 | if (jumbo) { |
baef58b1 | 1575 | /* Enable frame flushing if jumbo frames used */ |
6b0c1480 | 1576 | skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH); |
baef58b1 SH |
1577 | } else { |
1578 | /* enable timeout timers if normal frames */ | |
1579 | skge_write16(hw, B3_PA_CTRL, | |
45bada65 | 1580 | (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2); |
baef58b1 | 1581 | } |
baef58b1 SH |
1582 | } |
1583 | ||
1584 | static void genesis_stop(struct skge_port *skge) | |
1585 | { | |
1586 | struct skge_hw *hw = skge->hw; | |
1587 | int port = skge->port; | |
89bf5f23 | 1588 | u32 reg; |
baef58b1 | 1589 | |
46a60f2d SH |
1590 | genesis_reset(hw, port); |
1591 | ||
baef58b1 SH |
1592 | /* Clear Tx packet arbiter timeout IRQ */ |
1593 | skge_write16(hw, B3_PA_CTRL, | |
1594 | port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); | |
1595 | ||
1596 | /* | |
8f3f8193 | 1597 | * If the transfer sticks at the MAC the STOP command will not |
baef58b1 SH |
1598 | * terminate if we don't flush the XMAC's transmit FIFO ! |
1599 | */ | |
6b0c1480 SH |
1600 | xm_write32(hw, port, XM_MODE, |
1601 | xm_read32(hw, port, XM_MODE)|XM_MD_FTF); | |
baef58b1 SH |
1602 | |
1603 | ||
1604 | /* Reset the MAC */ | |
6b0c1480 | 1605 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); |
baef58b1 SH |
1606 | |
1607 | /* For external PHYs there must be special handling */ | |
64f6b64d SH |
1608 | if (hw->phy_type != SK_PHY_XMAC) { |
1609 | reg = skge_read32(hw, B2_GP_IO); | |
1610 | if (port == 0) { | |
1611 | reg |= GP_DIR_0; | |
1612 | reg &= ~GP_IO_0; | |
1613 | } else { | |
1614 | reg |= GP_DIR_2; | |
1615 | reg &= ~GP_IO_2; | |
1616 | } | |
1617 | skge_write32(hw, B2_GP_IO, reg); | |
1618 | skge_read32(hw, B2_GP_IO); | |
baef58b1 SH |
1619 | } |
1620 | ||
6b0c1480 SH |
1621 | xm_write16(hw, port, XM_MMU_CMD, |
1622 | xm_read16(hw, port, XM_MMU_CMD) | |
baef58b1 SH |
1623 | & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); |
1624 | ||
6b0c1480 | 1625 | xm_read16(hw, port, XM_MMU_CMD); |
baef58b1 SH |
1626 | } |
1627 | ||
1628 | ||
1629 | static void genesis_get_stats(struct skge_port *skge, u64 *data) | |
1630 | { | |
1631 | struct skge_hw *hw = skge->hw; | |
1632 | int port = skge->port; | |
1633 | int i; | |
1634 | unsigned long timeout = jiffies + HZ; | |
1635 | ||
6b0c1480 | 1636 | xm_write16(hw, port, |
baef58b1 SH |
1637 | XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC); |
1638 | ||
1639 | /* wait for update to complete */ | |
6b0c1480 | 1640 | while (xm_read16(hw, port, XM_STAT_CMD) |
baef58b1 SH |
1641 | & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) { |
1642 | if (time_after(jiffies, timeout)) | |
1643 | break; | |
1644 | udelay(10); | |
1645 | } | |
1646 | ||
1647 | /* special case for 64 bit octet counter */ | |
6b0c1480 SH |
1648 | data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32 |
1649 | | xm_read32(hw, port, XM_TXO_OK_LO); | |
1650 | data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32 | |
1651 | | xm_read32(hw, port, XM_RXO_OK_LO); | |
baef58b1 SH |
1652 | |
1653 | for (i = 2; i < ARRAY_SIZE(skge_stats); i++) | |
6b0c1480 | 1654 | data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset); |
baef58b1 SH |
1655 | } |
1656 | ||
1657 | static void genesis_mac_intr(struct skge_hw *hw, int port) | |
1658 | { | |
1659 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
6b0c1480 | 1660 | u16 status = xm_read16(hw, port, XM_ISRC); |
baef58b1 | 1661 | |
7e676d91 SH |
1662 | if (netif_msg_intr(skge)) |
1663 | printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n", | |
1664 | skge->netdev->name, status); | |
baef58b1 | 1665 | |
a1bc9b87 SH |
1666 | if (hw->phy_type == SK_PHY_XMAC && |
1667 | (status & (XM_IS_INP_ASS | XM_IS_LIPA_RC))) | |
1668 | xm_link_down(hw, port); | |
1669 | ||
baef58b1 | 1670 | if (status & XM_IS_TXF_UR) { |
6b0c1480 | 1671 | xm_write32(hw, port, XM_MODE, XM_MD_FTF); |
baef58b1 SH |
1672 | ++skge->net_stats.tx_fifo_errors; |
1673 | } | |
1674 | if (status & XM_IS_RXF_OV) { | |
6b0c1480 | 1675 | xm_write32(hw, port, XM_MODE, XM_MD_FRF); |
baef58b1 SH |
1676 | ++skge->net_stats.rx_fifo_errors; |
1677 | } | |
1678 | } | |
1679 | ||
baef58b1 SH |
1680 | static void genesis_link_up(struct skge_port *skge) |
1681 | { | |
1682 | struct skge_hw *hw = skge->hw; | |
1683 | int port = skge->port; | |
a1bc9b87 | 1684 | u16 cmd, msk; |
64f6b64d | 1685 | u32 mode; |
baef58b1 | 1686 | |
6b0c1480 | 1687 | cmd = xm_read16(hw, port, XM_MMU_CMD); |
baef58b1 SH |
1688 | |
1689 | /* | |
1690 | * enabling pause frame reception is required for 1000BT | |
1691 | * because the XMAC is not reset if the link is going down | |
1692 | */ | |
5d5c8e03 SH |
1693 | if (skge->flow_status == FLOW_STAT_NONE || |
1694 | skge->flow_status == FLOW_STAT_LOC_SEND) | |
7e676d91 | 1695 | /* Disable Pause Frame Reception */ |
baef58b1 SH |
1696 | cmd |= XM_MMU_IGN_PF; |
1697 | else | |
1698 | /* Enable Pause Frame Reception */ | |
1699 | cmd &= ~XM_MMU_IGN_PF; | |
1700 | ||
6b0c1480 | 1701 | xm_write16(hw, port, XM_MMU_CMD, cmd); |
baef58b1 | 1702 | |
6b0c1480 | 1703 | mode = xm_read32(hw, port, XM_MODE); |
5d5c8e03 SH |
1704 | if (skge->flow_status== FLOW_STAT_SYMMETRIC || |
1705 | skge->flow_status == FLOW_STAT_LOC_SEND) { | |
baef58b1 SH |
1706 | /* |
1707 | * Configure Pause Frame Generation | |
1708 | * Use internal and external Pause Frame Generation. | |
1709 | * Sending pause frames is edge triggered. | |
1710 | * Send a Pause frame with the maximum pause time if | |
1711 | * internal oder external FIFO full condition occurs. | |
1712 | * Send a zero pause time frame to re-start transmission. | |
1713 | */ | |
1714 | /* XM_PAUSE_DA = '010000C28001' (default) */ | |
1715 | /* XM_MAC_PTIME = 0xffff (maximum) */ | |
1716 | /* remember this value is defined in big endian (!) */ | |
6b0c1480 | 1717 | xm_write16(hw, port, XM_MAC_PTIME, 0xffff); |
baef58b1 SH |
1718 | |
1719 | mode |= XM_PAUSE_MODE; | |
6b0c1480 | 1720 | skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); |
baef58b1 SH |
1721 | } else { |
1722 | /* | |
1723 | * disable pause frame generation is required for 1000BT | |
1724 | * because the XMAC is not reset if the link is going down | |
1725 | */ | |
1726 | /* Disable Pause Mode in Mode Register */ | |
1727 | mode &= ~XM_PAUSE_MODE; | |
1728 | ||
6b0c1480 | 1729 | skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); |
baef58b1 SH |
1730 | } |
1731 | ||
6b0c1480 | 1732 | xm_write32(hw, port, XM_MODE, mode); |
a1bc9b87 SH |
1733 | msk = XM_DEF_MSK; |
1734 | if (hw->phy_type != SK_PHY_XMAC) | |
1735 | msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */ | |
1736 | ||
1737 | xm_write16(hw, port, XM_IMSK, msk); | |
6b0c1480 | 1738 | xm_read16(hw, port, XM_ISRC); |
baef58b1 SH |
1739 | |
1740 | /* get MMU Command Reg. */ | |
6b0c1480 | 1741 | cmd = xm_read16(hw, port, XM_MMU_CMD); |
64f6b64d | 1742 | if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL) |
baef58b1 SH |
1743 | cmd |= XM_MMU_GMII_FD; |
1744 | ||
89bf5f23 SH |
1745 | /* |
1746 | * Workaround BCOM Errata (#10523) for all BCom Phys | |
1747 | * Enable Power Management after link up | |
1748 | */ | |
64f6b64d SH |
1749 | if (hw->phy_type == SK_PHY_BCOM) { |
1750 | xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, | |
1751 | xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) | |
1752 | & ~PHY_B_AC_DIS_PM); | |
1753 | xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); | |
1754 | } | |
baef58b1 SH |
1755 | |
1756 | /* enable Rx/Tx */ | |
6b0c1480 | 1757 | xm_write16(hw, port, XM_MMU_CMD, |
baef58b1 SH |
1758 | cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX); |
1759 | skge_link_up(skge); | |
1760 | } | |
1761 | ||
1762 | ||
45bada65 | 1763 | static inline void bcom_phy_intr(struct skge_port *skge) |
baef58b1 SH |
1764 | { |
1765 | struct skge_hw *hw = skge->hw; | |
1766 | int port = skge->port; | |
45bada65 SH |
1767 | u16 isrc; |
1768 | ||
1769 | isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT); | |
7e676d91 SH |
1770 | if (netif_msg_intr(skge)) |
1771 | printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n", | |
1772 | skge->netdev->name, isrc); | |
baef58b1 | 1773 | |
45bada65 SH |
1774 | if (isrc & PHY_B_IS_PSE) |
1775 | printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n", | |
1776 | hw->dev[port]->name); | |
baef58b1 SH |
1777 | |
1778 | /* Workaround BCom Errata: | |
1779 | * enable and disable loopback mode if "NO HCD" occurs. | |
1780 | */ | |
45bada65 | 1781 | if (isrc & PHY_B_IS_NO_HDCL) { |
6b0c1480 SH |
1782 | u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL); |
1783 | xm_phy_write(hw, port, PHY_BCOM_CTRL, | |
baef58b1 | 1784 | ctrl | PHY_CT_LOOP); |
6b0c1480 | 1785 | xm_phy_write(hw, port, PHY_BCOM_CTRL, |
baef58b1 SH |
1786 | ctrl & ~PHY_CT_LOOP); |
1787 | } | |
1788 | ||
45bada65 SH |
1789 | if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) |
1790 | bcom_check_link(hw, port); | |
baef58b1 | 1791 | |
baef58b1 SH |
1792 | } |
1793 | ||
2cd8e5d3 SH |
1794 | static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) |
1795 | { | |
1796 | int i; | |
1797 | ||
1798 | gma_write16(hw, port, GM_SMI_DATA, val); | |
1799 | gma_write16(hw, port, GM_SMI_CTRL, | |
1800 | GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); | |
1801 | for (i = 0; i < PHY_RETRIES; i++) { | |
1802 | udelay(1); | |
1803 | ||
1804 | if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) | |
1805 | return 0; | |
1806 | } | |
1807 | ||
1808 | printk(KERN_WARNING PFX "%s: phy write timeout\n", | |
1809 | hw->dev[port]->name); | |
1810 | return -EIO; | |
1811 | } | |
1812 | ||
1813 | static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) | |
1814 | { | |
1815 | int i; | |
1816 | ||
1817 | gma_write16(hw, port, GM_SMI_CTRL, | |
1818 | GM_SMI_CT_PHY_AD(hw->phy_addr) | |
1819 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); | |
1820 | ||
1821 | for (i = 0; i < PHY_RETRIES; i++) { | |
1822 | udelay(1); | |
1823 | if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) | |
1824 | goto ready; | |
1825 | } | |
1826 | ||
1827 | return -ETIMEDOUT; | |
1828 | ready: | |
1829 | *val = gma_read16(hw, port, GM_SMI_DATA); | |
1830 | return 0; | |
1831 | } | |
1832 | ||
1833 | static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg) | |
1834 | { | |
1835 | u16 v = 0; | |
1836 | if (__gm_phy_read(hw, port, reg, &v)) | |
1837 | printk(KERN_WARNING PFX "%s: phy read timeout\n", | |
1838 | hw->dev[port]->name); | |
1839 | return v; | |
1840 | } | |
1841 | ||
8f3f8193 | 1842 | /* Marvell Phy Initialization */ |
baef58b1 SH |
1843 | static void yukon_init(struct skge_hw *hw, int port) |
1844 | { | |
1845 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
1846 | u16 ctrl, ct1000, adv; | |
baef58b1 | 1847 | |
baef58b1 | 1848 | if (skge->autoneg == AUTONEG_ENABLE) { |
6b0c1480 | 1849 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
baef58b1 SH |
1850 | |
1851 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
1852 | PHY_M_EC_MAC_S_MSK); | |
1853 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); | |
1854 | ||
c506a509 | 1855 | ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); |
baef58b1 | 1856 | |
6b0c1480 | 1857 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); |
baef58b1 SH |
1858 | } |
1859 | ||
6b0c1480 | 1860 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); |
baef58b1 SH |
1861 | if (skge->autoneg == AUTONEG_DISABLE) |
1862 | ctrl &= ~PHY_CT_ANE; | |
1863 | ||
1864 | ctrl |= PHY_CT_RESET; | |
6b0c1480 | 1865 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); |
baef58b1 SH |
1866 | |
1867 | ctrl = 0; | |
1868 | ct1000 = 0; | |
b18f2091 | 1869 | adv = PHY_AN_CSMA; |
baef58b1 SH |
1870 | |
1871 | if (skge->autoneg == AUTONEG_ENABLE) { | |
5e1705dd | 1872 | if (hw->copper) { |
baef58b1 SH |
1873 | if (skge->advertising & ADVERTISED_1000baseT_Full) |
1874 | ct1000 |= PHY_M_1000C_AFD; | |
1875 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1876 | ct1000 |= PHY_M_1000C_AHD; | |
1877 | if (skge->advertising & ADVERTISED_100baseT_Full) | |
1878 | adv |= PHY_M_AN_100_FD; | |
1879 | if (skge->advertising & ADVERTISED_100baseT_Half) | |
1880 | adv |= PHY_M_AN_100_HD; | |
1881 | if (skge->advertising & ADVERTISED_10baseT_Full) | |
1882 | adv |= PHY_M_AN_10_FD; | |
1883 | if (skge->advertising & ADVERTISED_10baseT_Half) | |
1884 | adv |= PHY_M_AN_10_HD; | |
baef58b1 | 1885 | |
4b67be99 SH |
1886 | /* Set Flow-control capabilities */ |
1887 | adv |= phy_pause_map[skge->flow_control]; | |
1888 | } else { | |
1889 | if (skge->advertising & ADVERTISED_1000baseT_Full) | |
1890 | adv |= PHY_M_AN_1000X_AFD; | |
1891 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1892 | adv |= PHY_M_AN_1000X_AHD; | |
1893 | ||
1894 | adv |= fiber_pause_map[skge->flow_control]; | |
1895 | } | |
45bada65 | 1896 | |
baef58b1 SH |
1897 | /* Restart Auto-negotiation */ |
1898 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
1899 | } else { | |
1900 | /* forced speed/duplex settings */ | |
1901 | ct1000 = PHY_M_1000C_MSE; | |
1902 | ||
1903 | if (skge->duplex == DUPLEX_FULL) | |
1904 | ctrl |= PHY_CT_DUP_MD; | |
1905 | ||
1906 | switch (skge->speed) { | |
1907 | case SPEED_1000: | |
1908 | ctrl |= PHY_CT_SP1000; | |
1909 | break; | |
1910 | case SPEED_100: | |
1911 | ctrl |= PHY_CT_SP100; | |
1912 | break; | |
1913 | } | |
1914 | ||
1915 | ctrl |= PHY_CT_RESET; | |
1916 | } | |
1917 | ||
c506a509 | 1918 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); |
baef58b1 | 1919 | |
6b0c1480 SH |
1920 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); |
1921 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
baef58b1 | 1922 | |
baef58b1 SH |
1923 | /* Enable phy interrupt on autonegotiation complete (or link up) */ |
1924 | if (skge->autoneg == AUTONEG_ENABLE) | |
4cde06ed | 1925 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK); |
baef58b1 | 1926 | else |
4cde06ed | 1927 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); |
baef58b1 SH |
1928 | } |
1929 | ||
1930 | static void yukon_reset(struct skge_hw *hw, int port) | |
1931 | { | |
6b0c1480 SH |
1932 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ |
1933 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ | |
1934 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
1935 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
1936 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
baef58b1 | 1937 | |
6b0c1480 SH |
1938 | gma_write16(hw, port, GM_RX_CTRL, |
1939 | gma_read16(hw, port, GM_RX_CTRL) | |
baef58b1 SH |
1940 | | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
1941 | } | |
1942 | ||
c8868611 SH |
1943 | /* Apparently, early versions of Yukon-Lite had wrong chip_id? */ |
1944 | static int is_yukon_lite_a0(struct skge_hw *hw) | |
1945 | { | |
1946 | u32 reg; | |
1947 | int ret; | |
1948 | ||
1949 | if (hw->chip_id != CHIP_ID_YUKON) | |
1950 | return 0; | |
1951 | ||
1952 | reg = skge_read32(hw, B2_FAR); | |
1953 | skge_write8(hw, B2_FAR + 3, 0xff); | |
1954 | ret = (skge_read8(hw, B2_FAR + 3) != 0); | |
1955 | skge_write32(hw, B2_FAR, reg); | |
1956 | return ret; | |
1957 | } | |
1958 | ||
baef58b1 SH |
1959 | static void yukon_mac_init(struct skge_hw *hw, int port) |
1960 | { | |
1961 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
1962 | int i; | |
1963 | u32 reg; | |
1964 | const u8 *addr = hw->dev[port]->dev_addr; | |
1965 | ||
1966 | /* WA code for COMA mode -- set PHY reset */ | |
1967 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | |
46a60f2d SH |
1968 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
1969 | reg = skge_read32(hw, B2_GP_IO); | |
1970 | reg |= GP_DIR_9 | GP_IO_9; | |
1971 | skge_write32(hw, B2_GP_IO, reg); | |
1972 | } | |
baef58b1 SH |
1973 | |
1974 | /* hard reset */ | |
6b0c1480 SH |
1975 | skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
1976 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); | |
baef58b1 SH |
1977 | |
1978 | /* WA code for COMA mode -- clear PHY reset */ | |
1979 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | |
46a60f2d SH |
1980 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
1981 | reg = skge_read32(hw, B2_GP_IO); | |
1982 | reg |= GP_DIR_9; | |
1983 | reg &= ~GP_IO_9; | |
1984 | skge_write32(hw, B2_GP_IO, reg); | |
1985 | } | |
baef58b1 SH |
1986 | |
1987 | /* Set hardware config mode */ | |
1988 | reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | | |
1989 | GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE; | |
5e1705dd | 1990 | reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; |
baef58b1 SH |
1991 | |
1992 | /* Clear GMC reset */ | |
6b0c1480 SH |
1993 | skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET); |
1994 | skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); | |
1995 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); | |
564f9abb | 1996 | |
baef58b1 SH |
1997 | if (skge->autoneg == AUTONEG_DISABLE) { |
1998 | reg = GM_GPCR_AU_ALL_DIS; | |
6b0c1480 SH |
1999 | gma_write16(hw, port, GM_GP_CTRL, |
2000 | gma_read16(hw, port, GM_GP_CTRL) | reg); | |
baef58b1 SH |
2001 | |
2002 | switch (skge->speed) { | |
2003 | case SPEED_1000: | |
564f9abb | 2004 | reg &= ~GM_GPCR_SPEED_100; |
baef58b1 | 2005 | reg |= GM_GPCR_SPEED_1000; |
564f9abb | 2006 | break; |
baef58b1 | 2007 | case SPEED_100: |
564f9abb | 2008 | reg &= ~GM_GPCR_SPEED_1000; |
baef58b1 | 2009 | reg |= GM_GPCR_SPEED_100; |
564f9abb SH |
2010 | break; |
2011 | case SPEED_10: | |
2012 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | |
2013 | break; | |
baef58b1 SH |
2014 | } |
2015 | ||
2016 | if (skge->duplex == DUPLEX_FULL) | |
2017 | reg |= GM_GPCR_DUP_FULL; | |
2018 | } else | |
2019 | reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; | |
564f9abb | 2020 | |
baef58b1 SH |
2021 | switch (skge->flow_control) { |
2022 | case FLOW_MODE_NONE: | |
6b0c1480 | 2023 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); |
baef58b1 SH |
2024 | reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; |
2025 | break; | |
2026 | case FLOW_MODE_LOC_SEND: | |
2027 | /* disable Rx flow-control */ | |
2028 | reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
5d5c8e03 SH |
2029 | break; |
2030 | case FLOW_MODE_SYMMETRIC: | |
2031 | case FLOW_MODE_SYM_OR_REM: | |
2032 | /* enable Tx & Rx flow-control */ | |
2033 | break; | |
baef58b1 SH |
2034 | } |
2035 | ||
6b0c1480 | 2036 | gma_write16(hw, port, GM_GP_CTRL, reg); |
46a60f2d | 2037 | skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
baef58b1 | 2038 | |
baef58b1 | 2039 | yukon_init(hw, port); |
baef58b1 SH |
2040 | |
2041 | /* MIB clear */ | |
6b0c1480 SH |
2042 | reg = gma_read16(hw, port, GM_PHY_ADDR); |
2043 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
baef58b1 SH |
2044 | |
2045 | for (i = 0; i < GM_MIB_CNT_SIZE; i++) | |
6b0c1480 SH |
2046 | gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); |
2047 | gma_write16(hw, port, GM_PHY_ADDR, reg); | |
baef58b1 SH |
2048 | |
2049 | /* transmit control */ | |
6b0c1480 | 2050 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); |
baef58b1 SH |
2051 | |
2052 | /* receive control reg: unicast + multicast + no FCS */ | |
6b0c1480 | 2053 | gma_write16(hw, port, GM_RX_CTRL, |
baef58b1 SH |
2054 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
2055 | ||
2056 | /* transmit flow control */ | |
6b0c1480 | 2057 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); |
baef58b1 SH |
2058 | |
2059 | /* transmit parameter */ | |
6b0c1480 | 2060 | gma_write16(hw, port, GM_TX_PARAM, |
baef58b1 SH |
2061 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | |
2062 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
2063 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF)); | |
2064 | ||
2065 | /* serial mode register */ | |
2066 | reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); | |
2067 | if (hw->dev[port]->mtu > 1500) | |
2068 | reg |= GM_SMOD_JUMBO_ENA; | |
2069 | ||
6b0c1480 | 2070 | gma_write16(hw, port, GM_SERIAL_MODE, reg); |
baef58b1 SH |
2071 | |
2072 | /* physical address: used for pause frames */ | |
6b0c1480 | 2073 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); |
baef58b1 | 2074 | /* virtual address for data */ |
6b0c1480 | 2075 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); |
baef58b1 SH |
2076 | |
2077 | /* enable interrupt mask for counter overflows */ | |
6b0c1480 SH |
2078 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
2079 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
2080 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
baef58b1 SH |
2081 | |
2082 | /* Initialize Mac Fifo */ | |
2083 | ||
2084 | /* Configure Rx MAC FIFO */ | |
6b0c1480 | 2085 | skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); |
baef58b1 | 2086 | reg = GMF_OPER_ON | GMF_RX_F_FL_ON; |
c8868611 SH |
2087 | |
2088 | /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */ | |
2089 | if (is_yukon_lite_a0(hw)) | |
baef58b1 | 2090 | reg &= ~GMF_RX_F_FL_ON; |
c8868611 | 2091 | |
6b0c1480 SH |
2092 | skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); |
2093 | skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg); | |
c5923081 SH |
2094 | /* |
2095 | * because Pause Packet Truncation in GMAC is not working | |
2096 | * we have to increase the Flush Threshold to 64 bytes | |
2097 | * in order to flush pause packets in Rx FIFO on Yukon-1 | |
2098 | */ | |
2099 | skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); | |
baef58b1 SH |
2100 | |
2101 | /* Configure Tx MAC FIFO */ | |
6b0c1480 SH |
2102 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); |
2103 | skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
baef58b1 SH |
2104 | } |
2105 | ||
355ec572 SH |
2106 | /* Go into power down mode */ |
2107 | static void yukon_suspend(struct skge_hw *hw, int port) | |
2108 | { | |
2109 | u16 ctrl; | |
2110 | ||
2111 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
2112 | ctrl |= PHY_M_PC_POL_R_DIS; | |
2113 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
2114 | ||
2115 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
2116 | ctrl |= PHY_CT_RESET; | |
2117 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
2118 | ||
2119 | /* switch IEEE compatible power down mode on */ | |
2120 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
2121 | ctrl |= PHY_CT_PDOWN; | |
2122 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
2123 | } | |
2124 | ||
baef58b1 SH |
2125 | static void yukon_stop(struct skge_port *skge) |
2126 | { | |
2127 | struct skge_hw *hw = skge->hw; | |
2128 | int port = skge->port; | |
2129 | ||
46a60f2d SH |
2130 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); |
2131 | yukon_reset(hw, port); | |
baef58b1 | 2132 | |
6b0c1480 SH |
2133 | gma_write16(hw, port, GM_GP_CTRL, |
2134 | gma_read16(hw, port, GM_GP_CTRL) | |
0eedf4ac | 2135 | & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); |
6b0c1480 | 2136 | gma_read16(hw, port, GM_GP_CTRL); |
baef58b1 | 2137 | |
355ec572 | 2138 | yukon_suspend(hw, port); |
46a60f2d | 2139 | |
baef58b1 | 2140 | /* set GPHY Control reset */ |
46a60f2d SH |
2141 | skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
2142 | skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); | |
baef58b1 SH |
2143 | } |
2144 | ||
2145 | static void yukon_get_stats(struct skge_port *skge, u64 *data) | |
2146 | { | |
2147 | struct skge_hw *hw = skge->hw; | |
2148 | int port = skge->port; | |
2149 | int i; | |
2150 | ||
6b0c1480 SH |
2151 | data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 |
2152 | | gma_read32(hw, port, GM_TXO_OK_LO); | |
2153 | data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 | |
2154 | | gma_read32(hw, port, GM_RXO_OK_LO); | |
baef58b1 SH |
2155 | |
2156 | for (i = 2; i < ARRAY_SIZE(skge_stats); i++) | |
6b0c1480 | 2157 | data[i] = gma_read32(hw, port, |
baef58b1 SH |
2158 | skge_stats[i].gma_offset); |
2159 | } | |
2160 | ||
2161 | static void yukon_mac_intr(struct skge_hw *hw, int port) | |
2162 | { | |
7e676d91 SH |
2163 | struct net_device *dev = hw->dev[port]; |
2164 | struct skge_port *skge = netdev_priv(dev); | |
6b0c1480 | 2165 | u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); |
baef58b1 | 2166 | |
7e676d91 SH |
2167 | if (netif_msg_intr(skge)) |
2168 | printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n", | |
2169 | dev->name, status); | |
2170 | ||
baef58b1 SH |
2171 | if (status & GM_IS_RX_FF_OR) { |
2172 | ++skge->net_stats.rx_fifo_errors; | |
d8a09943 | 2173 | skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); |
baef58b1 | 2174 | } |
d8a09943 | 2175 | |
baef58b1 SH |
2176 | if (status & GM_IS_TX_FF_UR) { |
2177 | ++skge->net_stats.tx_fifo_errors; | |
d8a09943 | 2178 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); |
baef58b1 SH |
2179 | } |
2180 | ||
2181 | } | |
2182 | ||
2183 | static u16 yukon_speed(const struct skge_hw *hw, u16 aux) | |
2184 | { | |
95566065 | 2185 | switch (aux & PHY_M_PS_SPEED_MSK) { |
baef58b1 SH |
2186 | case PHY_M_PS_SPEED_1000: |
2187 | return SPEED_1000; | |
2188 | case PHY_M_PS_SPEED_100: | |
2189 | return SPEED_100; | |
2190 | default: | |
2191 | return SPEED_10; | |
2192 | } | |
2193 | } | |
2194 | ||
2195 | static void yukon_link_up(struct skge_port *skge) | |
2196 | { | |
2197 | struct skge_hw *hw = skge->hw; | |
2198 | int port = skge->port; | |
2199 | u16 reg; | |
2200 | ||
baef58b1 | 2201 | /* Enable Transmit FIFO Underrun */ |
46a60f2d | 2202 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
baef58b1 | 2203 | |
6b0c1480 | 2204 | reg = gma_read16(hw, port, GM_GP_CTRL); |
baef58b1 SH |
2205 | if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE) |
2206 | reg |= GM_GPCR_DUP_FULL; | |
2207 | ||
2208 | /* enable Rx/Tx */ | |
2209 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
6b0c1480 | 2210 | gma_write16(hw, port, GM_GP_CTRL, reg); |
baef58b1 | 2211 | |
4cde06ed | 2212 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); |
baef58b1 SH |
2213 | skge_link_up(skge); |
2214 | } | |
2215 | ||
2216 | static void yukon_link_down(struct skge_port *skge) | |
2217 | { | |
2218 | struct skge_hw *hw = skge->hw; | |
2219 | int port = skge->port; | |
d8a09943 | 2220 | u16 ctrl; |
baef58b1 | 2221 | |
d8a09943 SH |
2222 | ctrl = gma_read16(hw, port, GM_GP_CTRL); |
2223 | ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
2224 | gma_write16(hw, port, GM_GP_CTRL, ctrl); | |
baef58b1 | 2225 | |
5d5c8e03 SH |
2226 | if (skge->flow_status == FLOW_STAT_REM_SEND) { |
2227 | ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); | |
2228 | ctrl |= PHY_M_AN_ASP; | |
baef58b1 | 2229 | /* restore Asymmetric Pause bit */ |
5d5c8e03 | 2230 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl); |
baef58b1 SH |
2231 | } |
2232 | ||
baef58b1 SH |
2233 | skge_link_down(skge); |
2234 | ||
2235 | yukon_init(hw, port); | |
2236 | } | |
2237 | ||
2238 | static void yukon_phy_intr(struct skge_port *skge) | |
2239 | { | |
2240 | struct skge_hw *hw = skge->hw; | |
2241 | int port = skge->port; | |
2242 | const char *reason = NULL; | |
2243 | u16 istatus, phystat; | |
2244 | ||
6b0c1480 SH |
2245 | istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); |
2246 | phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); | |
7e676d91 SH |
2247 | |
2248 | if (netif_msg_intr(skge)) | |
2249 | printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n", | |
2250 | skge->netdev->name, istatus, phystat); | |
baef58b1 SH |
2251 | |
2252 | if (istatus & PHY_M_IS_AN_COMPL) { | |
6b0c1480 | 2253 | if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP) |
baef58b1 SH |
2254 | & PHY_M_AN_RF) { |
2255 | reason = "remote fault"; | |
2256 | goto failed; | |
2257 | } | |
2258 | ||
c506a509 | 2259 | if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { |
baef58b1 SH |
2260 | reason = "master/slave fault"; |
2261 | goto failed; | |
2262 | } | |
2263 | ||
2264 | if (!(phystat & PHY_M_PS_SPDUP_RES)) { | |
2265 | reason = "speed/duplex"; | |
2266 | goto failed; | |
2267 | } | |
2268 | ||
2269 | skge->duplex = (phystat & PHY_M_PS_FULL_DUP) | |
2270 | ? DUPLEX_FULL : DUPLEX_HALF; | |
2271 | skge->speed = yukon_speed(hw, phystat); | |
2272 | ||
baef58b1 SH |
2273 | /* We are using IEEE 802.3z/D5.0 Table 37-4 */ |
2274 | switch (phystat & PHY_M_PS_PAUSE_MSK) { | |
2275 | case PHY_M_PS_PAUSE_MSK: | |
5d5c8e03 | 2276 | skge->flow_status = FLOW_STAT_SYMMETRIC; |
baef58b1 SH |
2277 | break; |
2278 | case PHY_M_PS_RX_P_EN: | |
5d5c8e03 | 2279 | skge->flow_status = FLOW_STAT_REM_SEND; |
baef58b1 SH |
2280 | break; |
2281 | case PHY_M_PS_TX_P_EN: | |
5d5c8e03 | 2282 | skge->flow_status = FLOW_STAT_LOC_SEND; |
baef58b1 SH |
2283 | break; |
2284 | default: | |
5d5c8e03 | 2285 | skge->flow_status = FLOW_STAT_NONE; |
baef58b1 SH |
2286 | } |
2287 | ||
5d5c8e03 | 2288 | if (skge->flow_status == FLOW_STAT_NONE || |
baef58b1 | 2289 | (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF)) |
6b0c1480 | 2290 | skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); |
baef58b1 | 2291 | else |
6b0c1480 | 2292 | skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); |
baef58b1 SH |
2293 | yukon_link_up(skge); |
2294 | return; | |
2295 | } | |
2296 | ||
2297 | if (istatus & PHY_M_IS_LSP_CHANGE) | |
2298 | skge->speed = yukon_speed(hw, phystat); | |
2299 | ||
2300 | if (istatus & PHY_M_IS_DUP_CHANGE) | |
2301 | skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
2302 | if (istatus & PHY_M_IS_LST_CHANGE) { | |
2303 | if (phystat & PHY_M_PS_LINK_UP) | |
2304 | yukon_link_up(skge); | |
2305 | else | |
2306 | yukon_link_down(skge); | |
2307 | } | |
2308 | return; | |
2309 | failed: | |
2310 | printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n", | |
2311 | skge->netdev->name, reason); | |
2312 | ||
2313 | /* XXX restart autonegotiation? */ | |
2314 | } | |
2315 | ||
ee294dcd SH |
2316 | static void skge_phy_reset(struct skge_port *skge) |
2317 | { | |
2318 | struct skge_hw *hw = skge->hw; | |
2319 | int port = skge->port; | |
aae343d4 | 2320 | struct net_device *dev = hw->dev[port]; |
ee294dcd SH |
2321 | |
2322 | netif_stop_queue(skge->netdev); | |
2323 | netif_carrier_off(skge->netdev); | |
2324 | ||
d85b514f | 2325 | mutex_lock(&hw->phy_mutex); |
ee294dcd SH |
2326 | if (hw->chip_id == CHIP_ID_GENESIS) { |
2327 | genesis_reset(hw, port); | |
2328 | genesis_mac_init(hw, port); | |
2329 | } else { | |
2330 | yukon_reset(hw, port); | |
2331 | yukon_init(hw, port); | |
2332 | } | |
d85b514f | 2333 | mutex_unlock(&hw->phy_mutex); |
75814090 SH |
2334 | |
2335 | dev->set_multicast_list(dev); | |
ee294dcd SH |
2336 | } |
2337 | ||
2cd8e5d3 SH |
2338 | /* Basic MII support */ |
2339 | static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
2340 | { | |
2341 | struct mii_ioctl_data *data = if_mii(ifr); | |
2342 | struct skge_port *skge = netdev_priv(dev); | |
2343 | struct skge_hw *hw = skge->hw; | |
2344 | int err = -EOPNOTSUPP; | |
2345 | ||
2346 | if (!netif_running(dev)) | |
2347 | return -ENODEV; /* Phy still in reset */ | |
2348 | ||
2349 | switch(cmd) { | |
2350 | case SIOCGMIIPHY: | |
2351 | data->phy_id = hw->phy_addr; | |
2352 | ||
2353 | /* fallthru */ | |
2354 | case SIOCGMIIREG: { | |
2355 | u16 val = 0; | |
d85b514f | 2356 | mutex_lock(&hw->phy_mutex); |
2cd8e5d3 SH |
2357 | if (hw->chip_id == CHIP_ID_GENESIS) |
2358 | err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); | |
2359 | else | |
2360 | err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); | |
d85b514f | 2361 | mutex_unlock(&hw->phy_mutex); |
2cd8e5d3 SH |
2362 | data->val_out = val; |
2363 | break; | |
2364 | } | |
2365 | ||
2366 | case SIOCSMIIREG: | |
2367 | if (!capable(CAP_NET_ADMIN)) | |
2368 | return -EPERM; | |
2369 | ||
d85b514f | 2370 | mutex_lock(&hw->phy_mutex); |
2cd8e5d3 SH |
2371 | if (hw->chip_id == CHIP_ID_GENESIS) |
2372 | err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, | |
2373 | data->val_in); | |
2374 | else | |
2375 | err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f, | |
2376 | data->val_in); | |
d85b514f | 2377 | mutex_unlock(&hw->phy_mutex); |
2cd8e5d3 SH |
2378 | break; |
2379 | } | |
2380 | return err; | |
2381 | } | |
2382 | ||
baef58b1 SH |
2383 | static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len) |
2384 | { | |
2385 | u32 end; | |
2386 | ||
2387 | start /= 8; | |
2388 | len /= 8; | |
2389 | end = start + len - 1; | |
2390 | ||
2391 | skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); | |
2392 | skge_write32(hw, RB_ADDR(q, RB_START), start); | |
2393 | skge_write32(hw, RB_ADDR(q, RB_WP), start); | |
2394 | skge_write32(hw, RB_ADDR(q, RB_RP), start); | |
2395 | skge_write32(hw, RB_ADDR(q, RB_END), end); | |
2396 | ||
2397 | if (q == Q_R1 || q == Q_R2) { | |
2398 | /* Set thresholds on receive queue's */ | |
2399 | skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), | |
2400 | start + (2*len)/3); | |
2401 | skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), | |
2402 | start + (len/3)); | |
2403 | } else { | |
2404 | /* Enable store & forward on Tx queue's because | |
2405 | * Tx FIFO is only 4K on Genesis and 1K on Yukon | |
2406 | */ | |
2407 | skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
2408 | } | |
2409 | ||
2410 | skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
2411 | } | |
2412 | ||
2413 | /* Setup Bus Memory Interface */ | |
2414 | static void skge_qset(struct skge_port *skge, u16 q, | |
2415 | const struct skge_element *e) | |
2416 | { | |
2417 | struct skge_hw *hw = skge->hw; | |
2418 | u32 watermark = 0x600; | |
2419 | u64 base = skge->dma + (e->desc - skge->mem); | |
2420 | ||
2421 | /* optimization to reduce window on 32bit/33mhz */ | |
2422 | if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0) | |
2423 | watermark /= 2; | |
2424 | ||
2425 | skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); | |
2426 | skge_write32(hw, Q_ADDR(q, Q_F), watermark); | |
2427 | skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); | |
2428 | skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); | |
2429 | } | |
2430 | ||
2431 | static int skge_up(struct net_device *dev) | |
2432 | { | |
2433 | struct skge_port *skge = netdev_priv(dev); | |
2434 | struct skge_hw *hw = skge->hw; | |
2435 | int port = skge->port; | |
2436 | u32 chunk, ram_addr; | |
2437 | size_t rx_size, tx_size; | |
2438 | int err; | |
2439 | ||
fae87592 SH |
2440 | if (!is_valid_ether_addr(dev->dev_addr)) |
2441 | return -EINVAL; | |
2442 | ||
baef58b1 SH |
2443 | if (netif_msg_ifup(skge)) |
2444 | printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); | |
2445 | ||
19a33d4e | 2446 | if (dev->mtu > RX_BUF_SIZE) |
901ccefb | 2447 | skge->rx_buf_size = dev->mtu + ETH_HLEN; |
19a33d4e SH |
2448 | else |
2449 | skge->rx_buf_size = RX_BUF_SIZE; | |
2450 | ||
2451 | ||
baef58b1 SH |
2452 | rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc); |
2453 | tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc); | |
2454 | skge->mem_size = tx_size + rx_size; | |
2455 | skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma); | |
2456 | if (!skge->mem) | |
2457 | return -ENOMEM; | |
2458 | ||
c3da1447 SH |
2459 | BUG_ON(skge->dma & 7); |
2460 | ||
2461 | if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) { | |
1479d13c | 2462 | dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n"); |
c3da1447 SH |
2463 | err = -EINVAL; |
2464 | goto free_pci_mem; | |
2465 | } | |
2466 | ||
baef58b1 SH |
2467 | memset(skge->mem, 0, skge->mem_size); |
2468 | ||
203babb6 SH |
2469 | err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma); |
2470 | if (err) | |
baef58b1 SH |
2471 | goto free_pci_mem; |
2472 | ||
c54f9765 | 2473 | err = skge_rx_fill(dev); |
19a33d4e | 2474 | if (err) |
baef58b1 SH |
2475 | goto free_rx_ring; |
2476 | ||
203babb6 SH |
2477 | err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size, |
2478 | skge->dma + rx_size); | |
2479 | if (err) | |
baef58b1 SH |
2480 | goto free_rx_ring; |
2481 | ||
8f3f8193 | 2482 | /* Initialize MAC */ |
d85b514f | 2483 | mutex_lock(&hw->phy_mutex); |
baef58b1 SH |
2484 | if (hw->chip_id == CHIP_ID_GENESIS) |
2485 | genesis_mac_init(hw, port); | |
2486 | else | |
2487 | yukon_mac_init(hw, port); | |
d85b514f | 2488 | mutex_unlock(&hw->phy_mutex); |
baef58b1 SH |
2489 | |
2490 | /* Configure RAMbuffers */ | |
981d0377 | 2491 | chunk = hw->ram_size / ((hw->ports + 1)*2); |
baef58b1 SH |
2492 | ram_addr = hw->ram_offset + 2 * chunk * port; |
2493 | ||
2494 | skge_ramset(hw, rxqaddr[port], ram_addr, chunk); | |
2495 | skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean); | |
2496 | ||
2497 | BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean); | |
2498 | skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk); | |
2499 | skge_qset(skge, txqaddr[port], skge->tx_ring.to_use); | |
2500 | ||
2501 | /* Start receiver BMU */ | |
2502 | wmb(); | |
2503 | skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); | |
6abebb53 | 2504 | skge_led(skge, LED_MODE_ON); |
baef58b1 | 2505 | |
239e44e1 | 2506 | netif_poll_enable(dev); |
baef58b1 SH |
2507 | return 0; |
2508 | ||
2509 | free_rx_ring: | |
2510 | skge_rx_clean(skge); | |
2511 | kfree(skge->rx_ring.start); | |
2512 | free_pci_mem: | |
2513 | pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); | |
7731a4ea | 2514 | skge->mem = NULL; |
baef58b1 SH |
2515 | |
2516 | return err; | |
2517 | } | |
2518 | ||
2519 | static int skge_down(struct net_device *dev) | |
2520 | { | |
2521 | struct skge_port *skge = netdev_priv(dev); | |
2522 | struct skge_hw *hw = skge->hw; | |
2523 | int port = skge->port; | |
2524 | ||
7731a4ea SH |
2525 | if (skge->mem == NULL) |
2526 | return 0; | |
2527 | ||
baef58b1 SH |
2528 | if (netif_msg_ifdown(skge)) |
2529 | printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); | |
2530 | ||
2531 | netif_stop_queue(dev); | |
64f6b64d SH |
2532 | if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC) |
2533 | cancel_rearming_delayed_work(&skge->link_thread); | |
baef58b1 | 2534 | |
46a60f2d SH |
2535 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); |
2536 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2537 | genesis_stop(skge); | |
2538 | else | |
2539 | yukon_stop(skge); | |
2540 | ||
baef58b1 SH |
2541 | /* Stop transmitter */ |
2542 | skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); | |
2543 | skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
2544 | RB_RST_SET|RB_DIS_OP_MD); | |
2545 | ||
baef58b1 SH |
2546 | |
2547 | /* Disable Force Sync bit and Enable Alloc bit */ | |
6b0c1480 | 2548 | skge_write8(hw, SK_REG(port, TXA_CTRL), |
baef58b1 SH |
2549 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); |
2550 | ||
2551 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
6b0c1480 SH |
2552 | skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); |
2553 | skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
baef58b1 SH |
2554 | |
2555 | /* Reset PCI FIFO */ | |
2556 | skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); | |
2557 | skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
2558 | ||
2559 | /* Reset the RAM Buffer async Tx queue */ | |
2560 | skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); | |
2561 | /* stop receiver */ | |
2562 | skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); | |
2563 | skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), | |
2564 | RB_RST_SET|RB_DIS_OP_MD); | |
2565 | skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); | |
2566 | ||
2567 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
6b0c1480 SH |
2568 | skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET); |
2569 | skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET); | |
baef58b1 | 2570 | } else { |
6b0c1480 SH |
2571 | skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); |
2572 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
baef58b1 SH |
2573 | } |
2574 | ||
6abebb53 | 2575 | skge_led(skge, LED_MODE_OFF); |
baef58b1 | 2576 | |
239e44e1 | 2577 | netif_poll_disable(dev); |
513f533e | 2578 | skge_tx_clean(dev); |
baef58b1 SH |
2579 | skge_rx_clean(skge); |
2580 | ||
2581 | kfree(skge->rx_ring.start); | |
2582 | kfree(skge->tx_ring.start); | |
2583 | pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); | |
7731a4ea | 2584 | skge->mem = NULL; |
baef58b1 SH |
2585 | return 0; |
2586 | } | |
2587 | ||
29b4e886 SH |
2588 | static inline int skge_avail(const struct skge_ring *ring) |
2589 | { | |
2590 | return ((ring->to_clean > ring->to_use) ? 0 : ring->count) | |
2591 | + (ring->to_clean - ring->to_use) - 1; | |
2592 | } | |
2593 | ||
baef58b1 SH |
2594 | static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev) |
2595 | { | |
2596 | struct skge_port *skge = netdev_priv(dev); | |
2597 | struct skge_hw *hw = skge->hw; | |
baef58b1 SH |
2598 | struct skge_element *e; |
2599 | struct skge_tx_desc *td; | |
2600 | int i; | |
2601 | u32 control, len; | |
2602 | u64 map; | |
baef58b1 | 2603 | |
5b057c6b | 2604 | if (skb_padto(skb, ETH_ZLEN)) |
baef58b1 SH |
2605 | return NETDEV_TX_OK; |
2606 | ||
513f533e | 2607 | if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1)) |
baef58b1 | 2608 | return NETDEV_TX_BUSY; |
baef58b1 | 2609 | |
7c442fa1 | 2610 | e = skge->tx_ring.to_use; |
baef58b1 | 2611 | td = e->desc; |
7c442fa1 | 2612 | BUG_ON(td->control & BMU_OWN); |
baef58b1 SH |
2613 | e->skb = skb; |
2614 | len = skb_headlen(skb); | |
2615 | map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
2616 | pci_unmap_addr_set(e, mapaddr, map); | |
2617 | pci_unmap_len_set(e, maplen, len); | |
2618 | ||
2619 | td->dma_lo = map; | |
2620 | td->dma_hi = map >> 32; | |
2621 | ||
84fa7933 | 2622 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
baef58b1 SH |
2623 | int offset = skb->h.raw - skb->data; |
2624 | ||
2625 | /* This seems backwards, but it is what the sk98lin | |
2626 | * does. Looks like hardware is wrong? | |
2627 | */ | |
ea182d4a | 2628 | if (skb->h.ipiph->protocol == IPPROTO_UDP |
981d0377 | 2629 | && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON) |
baef58b1 SH |
2630 | control = BMU_TCP_CHECK; |
2631 | else | |
2632 | control = BMU_UDP_CHECK; | |
2633 | ||
2634 | td->csum_offs = 0; | |
2635 | td->csum_start = offset; | |
ff1dcadb | 2636 | td->csum_write = offset + skb->csum_offset; |
baef58b1 SH |
2637 | } else |
2638 | control = BMU_CHECK; | |
2639 | ||
2640 | if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */ | |
2641 | control |= BMU_EOF| BMU_IRQ_EOF; | |
2642 | else { | |
2643 | struct skge_tx_desc *tf = td; | |
2644 | ||
2645 | control |= BMU_STFWD; | |
2646 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
2647 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2648 | ||
2649 | map = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
2650 | frag->size, PCI_DMA_TODEVICE); | |
2651 | ||
2652 | e = e->next; | |
7c442fa1 | 2653 | e->skb = skb; |
baef58b1 | 2654 | tf = e->desc; |
7c442fa1 SH |
2655 | BUG_ON(tf->control & BMU_OWN); |
2656 | ||
baef58b1 SH |
2657 | tf->dma_lo = map; |
2658 | tf->dma_hi = (u64) map >> 32; | |
2659 | pci_unmap_addr_set(e, mapaddr, map); | |
2660 | pci_unmap_len_set(e, maplen, frag->size); | |
2661 | ||
2662 | tf->control = BMU_OWN | BMU_SW | control | frag->size; | |
2663 | } | |
2664 | tf->control |= BMU_EOF | BMU_IRQ_EOF; | |
2665 | } | |
2666 | /* Make sure all the descriptors written */ | |
2667 | wmb(); | |
2668 | td->control = BMU_OWN | BMU_SW | BMU_STF | control | len; | |
2669 | wmb(); | |
2670 | ||
2671 | skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); | |
2672 | ||
7c442fa1 | 2673 | if (unlikely(netif_msg_tx_queued(skge))) |
0b2d7fea | 2674 | printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n", |
7c442fa1 | 2675 | dev->name, e - skge->tx_ring.start, skb->len); |
baef58b1 | 2676 | |
7c442fa1 | 2677 | skge->tx_ring.to_use = e->next; |
9db96479 | 2678 | if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) { |
baef58b1 SH |
2679 | pr_debug("%s: transmit queue full\n", dev->name); |
2680 | netif_stop_queue(dev); | |
2681 | } | |
2682 | ||
c68ce71a SH |
2683 | dev->trans_start = jiffies; |
2684 | ||
baef58b1 SH |
2685 | return NETDEV_TX_OK; |
2686 | } | |
2687 | ||
7c442fa1 SH |
2688 | |
2689 | /* Free resources associated with this reing element */ | |
2690 | static void skge_tx_free(struct skge_port *skge, struct skge_element *e, | |
2691 | u32 control) | |
866b4f3e SH |
2692 | { |
2693 | struct pci_dev *pdev = skge->hw->pdev; | |
866b4f3e | 2694 | |
7c442fa1 | 2695 | BUG_ON(!e->skb); |
866b4f3e | 2696 | |
7c442fa1 SH |
2697 | /* skb header vs. fragment */ |
2698 | if (control & BMU_STF) | |
866b4f3e | 2699 | pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr), |
7c442fa1 SH |
2700 | pci_unmap_len(e, maplen), |
2701 | PCI_DMA_TODEVICE); | |
2702 | else | |
2703 | pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr), | |
2704 | pci_unmap_len(e, maplen), | |
2705 | PCI_DMA_TODEVICE); | |
866b4f3e | 2706 | |
7c442fa1 SH |
2707 | if (control & BMU_EOF) { |
2708 | if (unlikely(netif_msg_tx_done(skge))) | |
2709 | printk(KERN_DEBUG PFX "%s: tx done slot %td\n", | |
2710 | skge->netdev->name, e - skge->tx_ring.start); | |
866b4f3e | 2711 | |
513f533e | 2712 | dev_kfree_skb(e->skb); |
baef58b1 | 2713 | } |
7c442fa1 | 2714 | e->skb = NULL; |
baef58b1 SH |
2715 | } |
2716 | ||
7c442fa1 | 2717 | /* Free all buffers in transmit ring */ |
513f533e | 2718 | static void skge_tx_clean(struct net_device *dev) |
baef58b1 | 2719 | { |
513f533e | 2720 | struct skge_port *skge = netdev_priv(dev); |
7c442fa1 | 2721 | struct skge_element *e; |
baef58b1 | 2722 | |
513f533e | 2723 | netif_tx_lock_bh(dev); |
7c442fa1 SH |
2724 | for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { |
2725 | struct skge_tx_desc *td = e->desc; | |
2726 | skge_tx_free(skge, e, td->control); | |
2727 | td->control = 0; | |
2728 | } | |
2729 | ||
2730 | skge->tx_ring.to_clean = e; | |
513f533e SH |
2731 | netif_wake_queue(dev); |
2732 | netif_tx_unlock_bh(dev); | |
baef58b1 SH |
2733 | } |
2734 | ||
2735 | static void skge_tx_timeout(struct net_device *dev) | |
2736 | { | |
2737 | struct skge_port *skge = netdev_priv(dev); | |
2738 | ||
2739 | if (netif_msg_timer(skge)) | |
2740 | printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name); | |
2741 | ||
2742 | skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP); | |
513f533e | 2743 | skge_tx_clean(dev); |
baef58b1 SH |
2744 | } |
2745 | ||
2746 | static int skge_change_mtu(struct net_device *dev, int new_mtu) | |
2747 | { | |
7731a4ea | 2748 | int err; |
baef58b1 | 2749 | |
95566065 | 2750 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) |
baef58b1 SH |
2751 | return -EINVAL; |
2752 | ||
7731a4ea SH |
2753 | if (!netif_running(dev)) { |
2754 | dev->mtu = new_mtu; | |
2755 | return 0; | |
2756 | } | |
2757 | ||
2758 | skge_down(dev); | |
baef58b1 | 2759 | |
19a33d4e | 2760 | dev->mtu = new_mtu; |
7731a4ea SH |
2761 | |
2762 | err = skge_up(dev); | |
2763 | if (err) | |
2764 | dev_close(dev); | |
baef58b1 SH |
2765 | |
2766 | return err; | |
2767 | } | |
2768 | ||
2769 | static void genesis_set_multicast(struct net_device *dev) | |
2770 | { | |
2771 | struct skge_port *skge = netdev_priv(dev); | |
2772 | struct skge_hw *hw = skge->hw; | |
2773 | int port = skge->port; | |
2774 | int i, count = dev->mc_count; | |
2775 | struct dev_mc_list *list = dev->mc_list; | |
2776 | u32 mode; | |
2777 | u8 filter[8]; | |
2778 | ||
6b0c1480 | 2779 | mode = xm_read32(hw, port, XM_MODE); |
baef58b1 SH |
2780 | mode |= XM_MD_ENA_HASH; |
2781 | if (dev->flags & IFF_PROMISC) | |
2782 | mode |= XM_MD_ENA_PROM; | |
2783 | else | |
2784 | mode &= ~XM_MD_ENA_PROM; | |
2785 | ||
2786 | if (dev->flags & IFF_ALLMULTI) | |
2787 | memset(filter, 0xff, sizeof(filter)); | |
2788 | else { | |
2789 | memset(filter, 0, sizeof(filter)); | |
95566065 | 2790 | for (i = 0; list && i < count; i++, list = list->next) { |
45bada65 SH |
2791 | u32 crc, bit; |
2792 | crc = ether_crc_le(ETH_ALEN, list->dmi_addr); | |
2793 | bit = ~crc & 0x3f; | |
baef58b1 SH |
2794 | filter[bit/8] |= 1 << (bit%8); |
2795 | } | |
2796 | } | |
2797 | ||
6b0c1480 | 2798 | xm_write32(hw, port, XM_MODE, mode); |
45bada65 | 2799 | xm_outhash(hw, port, XM_HSM, filter); |
baef58b1 SH |
2800 | } |
2801 | ||
2802 | static void yukon_set_multicast(struct net_device *dev) | |
2803 | { | |
2804 | struct skge_port *skge = netdev_priv(dev); | |
2805 | struct skge_hw *hw = skge->hw; | |
2806 | int port = skge->port; | |
2807 | struct dev_mc_list *list = dev->mc_list; | |
2808 | u16 reg; | |
2809 | u8 filter[8]; | |
2810 | ||
2811 | memset(filter, 0, sizeof(filter)); | |
2812 | ||
6b0c1480 | 2813 | reg = gma_read16(hw, port, GM_RX_CTRL); |
baef58b1 SH |
2814 | reg |= GM_RXCR_UCF_ENA; |
2815 | ||
8f3f8193 | 2816 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
baef58b1 SH |
2817 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
2818 | else if (dev->flags & IFF_ALLMULTI) /* all multicast */ | |
2819 | memset(filter, 0xff, sizeof(filter)); | |
2820 | else if (dev->mc_count == 0) /* no multicast */ | |
2821 | reg &= ~GM_RXCR_MCF_ENA; | |
2822 | else { | |
2823 | int i; | |
2824 | reg |= GM_RXCR_MCF_ENA; | |
2825 | ||
95566065 | 2826 | for (i = 0; list && i < dev->mc_count; i++, list = list->next) { |
baef58b1 SH |
2827 | u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; |
2828 | filter[bit/8] |= 1 << (bit%8); | |
2829 | } | |
2830 | } | |
2831 | ||
2832 | ||
6b0c1480 | 2833 | gma_write16(hw, port, GM_MC_ADDR_H1, |
baef58b1 | 2834 | (u16)filter[0] | ((u16)filter[1] << 8)); |
6b0c1480 | 2835 | gma_write16(hw, port, GM_MC_ADDR_H2, |
baef58b1 | 2836 | (u16)filter[2] | ((u16)filter[3] << 8)); |
6b0c1480 | 2837 | gma_write16(hw, port, GM_MC_ADDR_H3, |
baef58b1 | 2838 | (u16)filter[4] | ((u16)filter[5] << 8)); |
6b0c1480 | 2839 | gma_write16(hw, port, GM_MC_ADDR_H4, |
baef58b1 SH |
2840 | (u16)filter[6] | ((u16)filter[7] << 8)); |
2841 | ||
6b0c1480 | 2842 | gma_write16(hw, port, GM_RX_CTRL, reg); |
baef58b1 SH |
2843 | } |
2844 | ||
383181ac SH |
2845 | static inline u16 phy_length(const struct skge_hw *hw, u32 status) |
2846 | { | |
2847 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2848 | return status >> XMR_FS_LEN_SHIFT; | |
2849 | else | |
2850 | return status >> GMR_FS_LEN_SHIFT; | |
2851 | } | |
2852 | ||
baef58b1 SH |
2853 | static inline int bad_phy_status(const struct skge_hw *hw, u32 status) |
2854 | { | |
2855 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2856 | return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0; | |
2857 | else | |
2858 | return (status & GMR_FS_ANY_ERR) || | |
2859 | (status & GMR_FS_RX_OK) == 0; | |
2860 | } | |
2861 | ||
19a33d4e SH |
2862 | |
2863 | /* Get receive buffer from descriptor. | |
2864 | * Handles copy of small buffers and reallocation failures | |
2865 | */ | |
c54f9765 SH |
2866 | static struct sk_buff *skge_rx_get(struct net_device *dev, |
2867 | struct skge_element *e, | |
2868 | u32 control, u32 status, u16 csum) | |
19a33d4e | 2869 | { |
c54f9765 | 2870 | struct skge_port *skge = netdev_priv(dev); |
383181ac SH |
2871 | struct sk_buff *skb; |
2872 | u16 len = control & BMU_BBC; | |
2873 | ||
2874 | if (unlikely(netif_msg_rx_status(skge))) | |
2875 | printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n", | |
c54f9765 | 2876 | dev->name, e - skge->rx_ring.start, |
383181ac SH |
2877 | status, len); |
2878 | ||
2879 | if (len > skge->rx_buf_size) | |
2880 | goto error; | |
2881 | ||
2882 | if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)) | |
2883 | goto error; | |
2884 | ||
2885 | if (bad_phy_status(skge->hw, status)) | |
2886 | goto error; | |
2887 | ||
2888 | if (phy_length(skge->hw, status) != len) | |
2889 | goto error; | |
19a33d4e SH |
2890 | |
2891 | if (len < RX_COPY_THRESHOLD) { | |
c54f9765 | 2892 | skb = netdev_alloc_skb(dev, len + 2); |
383181ac SH |
2893 | if (!skb) |
2894 | goto resubmit; | |
19a33d4e | 2895 | |
383181ac | 2896 | skb_reserve(skb, 2); |
19a33d4e SH |
2897 | pci_dma_sync_single_for_cpu(skge->hw->pdev, |
2898 | pci_unmap_addr(e, mapaddr), | |
2899 | len, PCI_DMA_FROMDEVICE); | |
383181ac | 2900 | memcpy(skb->data, e->skb->data, len); |
19a33d4e SH |
2901 | pci_dma_sync_single_for_device(skge->hw->pdev, |
2902 | pci_unmap_addr(e, mapaddr), | |
2903 | len, PCI_DMA_FROMDEVICE); | |
19a33d4e | 2904 | skge_rx_reuse(e, skge->rx_buf_size); |
19a33d4e | 2905 | } else { |
383181ac | 2906 | struct sk_buff *nskb; |
c54f9765 | 2907 | nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN); |
383181ac SH |
2908 | if (!nskb) |
2909 | goto resubmit; | |
19a33d4e | 2910 | |
901ccefb | 2911 | skb_reserve(nskb, NET_IP_ALIGN); |
19a33d4e SH |
2912 | pci_unmap_single(skge->hw->pdev, |
2913 | pci_unmap_addr(e, mapaddr), | |
2914 | pci_unmap_len(e, maplen), | |
2915 | PCI_DMA_FROMDEVICE); | |
2916 | skb = e->skb; | |
383181ac | 2917 | prefetch(skb->data); |
19a33d4e | 2918 | skge_rx_setup(skge, e, nskb, skge->rx_buf_size); |
baef58b1 | 2919 | } |
383181ac SH |
2920 | |
2921 | skb_put(skb, len); | |
383181ac SH |
2922 | if (skge->rx_csum) { |
2923 | skb->csum = csum; | |
84fa7933 | 2924 | skb->ip_summed = CHECKSUM_COMPLETE; |
383181ac SH |
2925 | } |
2926 | ||
c54f9765 | 2927 | skb->protocol = eth_type_trans(skb, dev); |
383181ac SH |
2928 | |
2929 | return skb; | |
2930 | error: | |
2931 | ||
2932 | if (netif_msg_rx_err(skge)) | |
2933 | printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n", | |
c54f9765 | 2934 | dev->name, e - skge->rx_ring.start, |
383181ac SH |
2935 | control, status); |
2936 | ||
2937 | if (skge->hw->chip_id == CHIP_ID_GENESIS) { | |
2938 | if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR)) | |
2939 | skge->net_stats.rx_length_errors++; | |
2940 | if (status & XMR_FS_FRA_ERR) | |
2941 | skge->net_stats.rx_frame_errors++; | |
2942 | if (status & XMR_FS_FCS_ERR) | |
2943 | skge->net_stats.rx_crc_errors++; | |
2944 | } else { | |
2945 | if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE)) | |
2946 | skge->net_stats.rx_length_errors++; | |
2947 | if (status & GMR_FS_FRAGMENT) | |
2948 | skge->net_stats.rx_frame_errors++; | |
2949 | if (status & GMR_FS_CRC_ERR) | |
2950 | skge->net_stats.rx_crc_errors++; | |
2951 | } | |
2952 | ||
2953 | resubmit: | |
2954 | skge_rx_reuse(e, skge->rx_buf_size); | |
2955 | return NULL; | |
baef58b1 SH |
2956 | } |
2957 | ||
7c442fa1 | 2958 | /* Free all buffers in Tx ring which are no longer owned by device */ |
513f533e | 2959 | static void skge_tx_done(struct net_device *dev) |
00a6cae2 | 2960 | { |
7c442fa1 | 2961 | struct skge_port *skge = netdev_priv(dev); |
00a6cae2 | 2962 | struct skge_ring *ring = &skge->tx_ring; |
7c442fa1 SH |
2963 | struct skge_element *e; |
2964 | ||
513f533e | 2965 | skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); |
00a6cae2 | 2966 | |
513f533e | 2967 | netif_tx_lock(dev); |
866b4f3e | 2968 | for (e = ring->to_clean; e != ring->to_use; e = e->next) { |
00a6cae2 | 2969 | struct skge_tx_desc *td = e->desc; |
00a6cae2 | 2970 | |
866b4f3e | 2971 | if (td->control & BMU_OWN) |
00a6cae2 SH |
2972 | break; |
2973 | ||
7c442fa1 | 2974 | skge_tx_free(skge, e, td->control); |
00a6cae2 | 2975 | } |
7c442fa1 | 2976 | skge->tx_ring.to_clean = e; |
866b4f3e | 2977 | |
513f533e SH |
2978 | if (skge_avail(&skge->tx_ring) > TX_LOW_WATER) |
2979 | netif_wake_queue(dev); | |
00a6cae2 | 2980 | |
513f533e | 2981 | netif_tx_unlock(dev); |
00a6cae2 | 2982 | } |
19a33d4e | 2983 | |
baef58b1 SH |
2984 | static int skge_poll(struct net_device *dev, int *budget) |
2985 | { | |
2986 | struct skge_port *skge = netdev_priv(dev); | |
2987 | struct skge_hw *hw = skge->hw; | |
2988 | struct skge_ring *ring = &skge->rx_ring; | |
2989 | struct skge_element *e; | |
d15e9c4d | 2990 | unsigned long flags; |
00a6cae2 SH |
2991 | int to_do = min(dev->quota, *budget); |
2992 | int work_done = 0; | |
2993 | ||
513f533e SH |
2994 | skge_tx_done(dev); |
2995 | ||
2996 | skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); | |
2997 | ||
1631aef1 | 2998 | for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) { |
baef58b1 | 2999 | struct skge_rx_desc *rd = e->desc; |
19a33d4e | 3000 | struct sk_buff *skb; |
383181ac | 3001 | u32 control; |
baef58b1 SH |
3002 | |
3003 | rmb(); | |
3004 | control = rd->control; | |
3005 | if (control & BMU_OWN) | |
3006 | break; | |
3007 | ||
c54f9765 | 3008 | skb = skge_rx_get(dev, e, control, rd->status, rd->csum2); |
19a33d4e | 3009 | if (likely(skb)) { |
19a33d4e SH |
3010 | dev->last_rx = jiffies; |
3011 | netif_receive_skb(skb); | |
baef58b1 | 3012 | |
19a33d4e | 3013 | ++work_done; |
5a011447 | 3014 | } |
baef58b1 SH |
3015 | } |
3016 | ring->to_clean = e; | |
3017 | ||
baef58b1 SH |
3018 | /* restart receiver */ |
3019 | wmb(); | |
a9cdab86 | 3020 | skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START); |
baef58b1 | 3021 | |
19a33d4e SH |
3022 | *budget -= work_done; |
3023 | dev->quota -= work_done; | |
3024 | ||
3025 | if (work_done >= to_do) | |
3026 | return 1; /* not done */ | |
baef58b1 | 3027 | |
d15e9c4d | 3028 | spin_lock_irqsave(&hw->hw_lock, flags); |
513f533e SH |
3029 | __netif_rx_complete(dev); |
3030 | hw->intr_mask |= irqmask[skge->port]; | |
80dd857d | 3031 | skge_write32(hw, B0_IMSK, hw->intr_mask); |
78bc2186 | 3032 | skge_read32(hw, B0_IMSK); |
d15e9c4d | 3033 | spin_unlock_irqrestore(&hw->hw_lock, flags); |
1631aef1 | 3034 | |
19a33d4e | 3035 | return 0; |
baef58b1 SH |
3036 | } |
3037 | ||
f6620cab SH |
3038 | /* Parity errors seem to happen when Genesis is connected to a switch |
3039 | * with no other ports present. Heartbeat error?? | |
3040 | */ | |
baef58b1 SH |
3041 | static void skge_mac_parity(struct skge_hw *hw, int port) |
3042 | { | |
f6620cab SH |
3043 | struct net_device *dev = hw->dev[port]; |
3044 | ||
3045 | if (dev) { | |
3046 | struct skge_port *skge = netdev_priv(dev); | |
3047 | ++skge->net_stats.tx_heartbeat_errors; | |
3048 | } | |
baef58b1 SH |
3049 | |
3050 | if (hw->chip_id == CHIP_ID_GENESIS) | |
6b0c1480 | 3051 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), |
baef58b1 SH |
3052 | MFF_CLR_PERR); |
3053 | else | |
3054 | /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */ | |
6b0c1480 | 3055 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), |
981d0377 | 3056 | (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) |
baef58b1 SH |
3057 | ? GMF_CLI_TX_FC : GMF_CLI_TX_PE); |
3058 | } | |
3059 | ||
baef58b1 SH |
3060 | static void skge_mac_intr(struct skge_hw *hw, int port) |
3061 | { | |
95566065 | 3062 | if (hw->chip_id == CHIP_ID_GENESIS) |
baef58b1 SH |
3063 | genesis_mac_intr(hw, port); |
3064 | else | |
3065 | yukon_mac_intr(hw, port); | |
3066 | } | |
3067 | ||
3068 | /* Handle device specific framing and timeout interrupts */ | |
3069 | static void skge_error_irq(struct skge_hw *hw) | |
3070 | { | |
1479d13c | 3071 | struct pci_dev *pdev = hw->pdev; |
baef58b1 SH |
3072 | u32 hwstatus = skge_read32(hw, B0_HWE_ISRC); |
3073 | ||
3074 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
3075 | /* clear xmac errors */ | |
3076 | if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1)) | |
46a60f2d | 3077 | skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT); |
baef58b1 | 3078 | if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2)) |
46a60f2d | 3079 | skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT); |
baef58b1 SH |
3080 | } else { |
3081 | /* Timestamp (unused) overflow */ | |
3082 | if (hwstatus & IS_IRQ_TIST_OV) | |
3083 | skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); | |
baef58b1 SH |
3084 | } |
3085 | ||
3086 | if (hwstatus & IS_RAM_RD_PAR) { | |
1479d13c | 3087 | dev_err(&pdev->dev, "Ram read data parity error\n"); |
baef58b1 SH |
3088 | skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR); |
3089 | } | |
3090 | ||
3091 | if (hwstatus & IS_RAM_WR_PAR) { | |
1479d13c | 3092 | dev_err(&pdev->dev, "Ram write data parity error\n"); |
baef58b1 SH |
3093 | skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR); |
3094 | } | |
3095 | ||
3096 | if (hwstatus & IS_M1_PAR_ERR) | |
3097 | skge_mac_parity(hw, 0); | |
3098 | ||
3099 | if (hwstatus & IS_M2_PAR_ERR) | |
3100 | skge_mac_parity(hw, 1); | |
3101 | ||
b9d64acc | 3102 | if (hwstatus & IS_R1_PAR_ERR) { |
1479d13c SH |
3103 | dev_err(&pdev->dev, "%s: receive queue parity error\n", |
3104 | hw->dev[0]->name); | |
baef58b1 | 3105 | skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P); |
b9d64acc | 3106 | } |
baef58b1 | 3107 | |
b9d64acc | 3108 | if (hwstatus & IS_R2_PAR_ERR) { |
1479d13c SH |
3109 | dev_err(&pdev->dev, "%s: receive queue parity error\n", |
3110 | hw->dev[1]->name); | |
baef58b1 | 3111 | skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); |
b9d64acc | 3112 | } |
baef58b1 SH |
3113 | |
3114 | if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) { | |
b9d64acc SH |
3115 | u16 pci_status, pci_cmd; |
3116 | ||
1479d13c SH |
3117 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); |
3118 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
baef58b1 | 3119 | |
1479d13c SH |
3120 | dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n", |
3121 | pci_cmd, pci_status); | |
b9d64acc SH |
3122 | |
3123 | /* Write the error bits back to clear them. */ | |
3124 | pci_status &= PCI_STATUS_ERROR_BITS; | |
3125 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
1479d13c | 3126 | pci_write_config_word(pdev, PCI_COMMAND, |
b9d64acc | 3127 | pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY); |
1479d13c | 3128 | pci_write_config_word(pdev, PCI_STATUS, pci_status); |
b9d64acc | 3129 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
baef58b1 | 3130 | |
050ec18a | 3131 | /* if error still set then just ignore it */ |
baef58b1 SH |
3132 | hwstatus = skge_read32(hw, B0_HWE_ISRC); |
3133 | if (hwstatus & IS_IRQ_STAT) { | |
1479d13c | 3134 | dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n"); |
baef58b1 SH |
3135 | hw->intr_mask &= ~IS_HW_ERR; |
3136 | } | |
3137 | } | |
3138 | } | |
3139 | ||
3140 | /* | |
d85b514f | 3141 | * Interrupt from PHY are handled in work queue |
baef58b1 SH |
3142 | * because accessing phy registers requires spin wait which might |
3143 | * cause excess interrupt latency. | |
3144 | */ | |
c4028958 | 3145 | static void skge_extirq(struct work_struct *work) |
baef58b1 | 3146 | { |
c4028958 | 3147 | struct skge_hw *hw = container_of(work, struct skge_hw, phy_work); |
baef58b1 SH |
3148 | int port; |
3149 | ||
d85b514f | 3150 | mutex_lock(&hw->phy_mutex); |
cfc3ed79 | 3151 | for (port = 0; port < hw->ports; port++) { |
baef58b1 | 3152 | struct net_device *dev = hw->dev[port]; |
cfc3ed79 | 3153 | struct skge_port *skge = netdev_priv(dev); |
baef58b1 | 3154 | |
cfc3ed79 | 3155 | if (netif_running(dev)) { |
baef58b1 SH |
3156 | if (hw->chip_id != CHIP_ID_GENESIS) |
3157 | yukon_phy_intr(skge); | |
64f6b64d | 3158 | else if (hw->phy_type == SK_PHY_BCOM) |
45bada65 | 3159 | bcom_phy_intr(skge); |
baef58b1 SH |
3160 | } |
3161 | } | |
d85b514f | 3162 | mutex_unlock(&hw->phy_mutex); |
baef58b1 | 3163 | |
7c442fa1 | 3164 | spin_lock_irq(&hw->hw_lock); |
baef58b1 SH |
3165 | hw->intr_mask |= IS_EXT_REG; |
3166 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
78bc2186 | 3167 | skge_read32(hw, B0_IMSK); |
7c442fa1 | 3168 | spin_unlock_irq(&hw->hw_lock); |
baef58b1 SH |
3169 | } |
3170 | ||
7d12e780 | 3171 | static irqreturn_t skge_intr(int irq, void *dev_id) |
baef58b1 SH |
3172 | { |
3173 | struct skge_hw *hw = dev_id; | |
cfc3ed79 | 3174 | u32 status; |
29365c90 | 3175 | int handled = 0; |
baef58b1 | 3176 | |
29365c90 | 3177 | spin_lock(&hw->hw_lock); |
cfc3ed79 SH |
3178 | /* Reading this register masks IRQ */ |
3179 | status = skge_read32(hw, B0_SP_ISRC); | |
0486a8c8 | 3180 | if (status == 0 || status == ~0) |
29365c90 | 3181 | goto out; |
baef58b1 | 3182 | |
29365c90 | 3183 | handled = 1; |
7c442fa1 | 3184 | status &= hw->intr_mask; |
cfc3ed79 SH |
3185 | if (status & IS_EXT_REG) { |
3186 | hw->intr_mask &= ~IS_EXT_REG; | |
d85b514f | 3187 | schedule_work(&hw->phy_work); |
cfc3ed79 SH |
3188 | } |
3189 | ||
513f533e SH |
3190 | if (status & (IS_XA1_F|IS_R1_F)) { |
3191 | hw->intr_mask &= ~(IS_XA1_F|IS_R1_F); | |
7c442fa1 | 3192 | netif_rx_schedule(hw->dev[0]); |
baef58b1 SH |
3193 | } |
3194 | ||
7c442fa1 SH |
3195 | if (status & IS_PA_TO_TX1) |
3196 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1); | |
cfc3ed79 | 3197 | |
d25f5a67 SH |
3198 | if (status & IS_PA_TO_RX1) { |
3199 | struct skge_port *skge = netdev_priv(hw->dev[0]); | |
d25f5a67 | 3200 | |
d25f5a67 | 3201 | ++skge->net_stats.rx_over_errors; |
7c442fa1 | 3202 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1); |
d25f5a67 SH |
3203 | } |
3204 | ||
d25f5a67 | 3205 | |
baef58b1 SH |
3206 | if (status & IS_MAC1) |
3207 | skge_mac_intr(hw, 0); | |
95566065 | 3208 | |
7c442fa1 | 3209 | if (hw->dev[1]) { |
513f533e SH |
3210 | if (status & (IS_XA2_F|IS_R2_F)) { |
3211 | hw->intr_mask &= ~(IS_XA2_F|IS_R2_F); | |
7c442fa1 SH |
3212 | netif_rx_schedule(hw->dev[1]); |
3213 | } | |
3214 | ||
3215 | if (status & IS_PA_TO_RX2) { | |
3216 | struct skge_port *skge = netdev_priv(hw->dev[1]); | |
3217 | ++skge->net_stats.rx_over_errors; | |
3218 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2); | |
3219 | } | |
3220 | ||
3221 | if (status & IS_PA_TO_TX2) | |
3222 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2); | |
3223 | ||
3224 | if (status & IS_MAC2) | |
3225 | skge_mac_intr(hw, 1); | |
3226 | } | |
baef58b1 SH |
3227 | |
3228 | if (status & IS_HW_ERR) | |
3229 | skge_error_irq(hw); | |
3230 | ||
7e676d91 | 3231 | skge_write32(hw, B0_IMSK, hw->intr_mask); |
78bc2186 | 3232 | skge_read32(hw, B0_IMSK); |
29365c90 | 3233 | out: |
7c442fa1 | 3234 | spin_unlock(&hw->hw_lock); |
baef58b1 | 3235 | |
29365c90 | 3236 | return IRQ_RETVAL(handled); |
baef58b1 SH |
3237 | } |
3238 | ||
3239 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3240 | static void skge_netpoll(struct net_device *dev) | |
3241 | { | |
3242 | struct skge_port *skge = netdev_priv(dev); | |
3243 | ||
3244 | disable_irq(dev->irq); | |
7d12e780 | 3245 | skge_intr(dev->irq, skge->hw); |
baef58b1 SH |
3246 | enable_irq(dev->irq); |
3247 | } | |
3248 | #endif | |
3249 | ||
3250 | static int skge_set_mac_address(struct net_device *dev, void *p) | |
3251 | { | |
3252 | struct skge_port *skge = netdev_priv(dev); | |
c2681dd8 SH |
3253 | struct skge_hw *hw = skge->hw; |
3254 | unsigned port = skge->port; | |
3255 | const struct sockaddr *addr = p; | |
baef58b1 SH |
3256 | |
3257 | if (!is_valid_ether_addr(addr->sa_data)) | |
3258 | return -EADDRNOTAVAIL; | |
3259 | ||
d85b514f | 3260 | mutex_lock(&hw->phy_mutex); |
baef58b1 | 3261 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
c2681dd8 | 3262 | memcpy_toio(hw->regs + B2_MAC_1 + port*8, |
baef58b1 | 3263 | dev->dev_addr, ETH_ALEN); |
c2681dd8 | 3264 | memcpy_toio(hw->regs + B2_MAC_2 + port*8, |
baef58b1 | 3265 | dev->dev_addr, ETH_ALEN); |
c2681dd8 SH |
3266 | |
3267 | if (hw->chip_id == CHIP_ID_GENESIS) | |
3268 | xm_outaddr(hw, port, XM_SA, dev->dev_addr); | |
3269 | else { | |
3270 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); | |
3271 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); | |
3272 | } | |
d85b514f | 3273 | mutex_unlock(&hw->phy_mutex); |
c2681dd8 SH |
3274 | |
3275 | return 0; | |
baef58b1 SH |
3276 | } |
3277 | ||
3278 | static const struct { | |
3279 | u8 id; | |
3280 | const char *name; | |
3281 | } skge_chips[] = { | |
3282 | { CHIP_ID_GENESIS, "Genesis" }, | |
3283 | { CHIP_ID_YUKON, "Yukon" }, | |
3284 | { CHIP_ID_YUKON_LITE, "Yukon-Lite"}, | |
3285 | { CHIP_ID_YUKON_LP, "Yukon-LP"}, | |
baef58b1 SH |
3286 | }; |
3287 | ||
3288 | static const char *skge_board_name(const struct skge_hw *hw) | |
3289 | { | |
3290 | int i; | |
3291 | static char buf[16]; | |
3292 | ||
3293 | for (i = 0; i < ARRAY_SIZE(skge_chips); i++) | |
3294 | if (skge_chips[i].id == hw->chip_id) | |
3295 | return skge_chips[i].name; | |
3296 | ||
3297 | snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id); | |
3298 | return buf; | |
3299 | } | |
3300 | ||
3301 | ||
3302 | /* | |
3303 | * Setup the board data structure, but don't bring up | |
3304 | * the port(s) | |
3305 | */ | |
3306 | static int skge_reset(struct skge_hw *hw) | |
3307 | { | |
adba9e23 | 3308 | u32 reg; |
b9d64acc | 3309 | u16 ctst, pci_status; |
64f6b64d | 3310 | u8 t8, mac_cfg, pmd_type; |
981d0377 | 3311 | int i; |
baef58b1 SH |
3312 | |
3313 | ctst = skge_read16(hw, B0_CTST); | |
3314 | ||
3315 | /* do a SW reset */ | |
3316 | skge_write8(hw, B0_CTST, CS_RST_SET); | |
3317 | skge_write8(hw, B0_CTST, CS_RST_CLR); | |
3318 | ||
3319 | /* clear PCI errors, if any */ | |
b9d64acc SH |
3320 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
3321 | skge_write8(hw, B2_TST_CTRL2, 0); | |
baef58b1 | 3322 | |
b9d64acc SH |
3323 | pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status); |
3324 | pci_write_config_word(hw->pdev, PCI_STATUS, | |
3325 | pci_status | PCI_STATUS_ERROR_BITS); | |
3326 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
baef58b1 SH |
3327 | skge_write8(hw, B0_CTST, CS_MRST_CLR); |
3328 | ||
3329 | /* restore CLK_RUN bits (for Yukon-Lite) */ | |
3330 | skge_write16(hw, B0_CTST, | |
3331 | ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA)); | |
3332 | ||
3333 | hw->chip_id = skge_read8(hw, B2_CHIP_ID); | |
64f6b64d | 3334 | hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; |
5e1705dd SH |
3335 | pmd_type = skge_read8(hw, B2_PMD_TYP); |
3336 | hw->copper = (pmd_type == 'T' || pmd_type == '1'); | |
baef58b1 | 3337 | |
95566065 | 3338 | switch (hw->chip_id) { |
baef58b1 | 3339 | case CHIP_ID_GENESIS: |
64f6b64d SH |
3340 | switch (hw->phy_type) { |
3341 | case SK_PHY_XMAC: | |
3342 | hw->phy_addr = PHY_ADDR_XMAC; | |
3343 | break; | |
baef58b1 SH |
3344 | case SK_PHY_BCOM: |
3345 | hw->phy_addr = PHY_ADDR_BCOM; | |
3346 | break; | |
3347 | default: | |
1479d13c SH |
3348 | dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n", |
3349 | hw->phy_type); | |
baef58b1 SH |
3350 | return -EOPNOTSUPP; |
3351 | } | |
3352 | break; | |
3353 | ||
3354 | case CHIP_ID_YUKON: | |
3355 | case CHIP_ID_YUKON_LITE: | |
3356 | case CHIP_ID_YUKON_LP: | |
64f6b64d | 3357 | if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S') |
5e1705dd | 3358 | hw->copper = 1; |
baef58b1 SH |
3359 | |
3360 | hw->phy_addr = PHY_ADDR_MARV; | |
baef58b1 SH |
3361 | break; |
3362 | ||
3363 | default: | |
1479d13c SH |
3364 | dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", |
3365 | hw->chip_id); | |
baef58b1 SH |
3366 | return -EOPNOTSUPP; |
3367 | } | |
3368 | ||
981d0377 SH |
3369 | mac_cfg = skge_read8(hw, B2_MAC_CFG); |
3370 | hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2; | |
3371 | hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4; | |
baef58b1 SH |
3372 | |
3373 | /* read the adapters RAM size */ | |
3374 | t8 = skge_read8(hw, B2_E_0); | |
3375 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
3376 | if (t8 == 3) { | |
3377 | /* special case: 4 x 64k x 36, offset = 0x80000 */ | |
3378 | hw->ram_size = 0x100000; | |
3379 | hw->ram_offset = 0x80000; | |
3380 | } else | |
3381 | hw->ram_size = t8 * 512; | |
3382 | } | |
3383 | else if (t8 == 0) | |
3384 | hw->ram_size = 0x20000; | |
3385 | else | |
3386 | hw->ram_size = t8 * 4096; | |
3387 | ||
64f6b64d | 3388 | hw->intr_mask = IS_HW_ERR | IS_PORT_1; |
cfc3ed79 SH |
3389 | if (hw->ports > 1) |
3390 | hw->intr_mask |= IS_PORT_2; | |
3391 | ||
64f6b64d SH |
3392 | if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)) |
3393 | hw->intr_mask |= IS_EXT_REG; | |
3394 | ||
baef58b1 SH |
3395 | if (hw->chip_id == CHIP_ID_GENESIS) |
3396 | genesis_init(hw); | |
3397 | else { | |
3398 | /* switch power to VCC (WA for VAUX problem) */ | |
3399 | skge_write8(hw, B0_POWER_CTRL, | |
3400 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
adba9e23 | 3401 | |
050ec18a SH |
3402 | /* avoid boards with stuck Hardware error bits */ |
3403 | if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) && | |
3404 | (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) { | |
1479d13c | 3405 | dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n"); |
050ec18a SH |
3406 | hw->intr_mask &= ~IS_HW_ERR; |
3407 | } | |
3408 | ||
adba9e23 SH |
3409 | /* Clear PHY COMA */ |
3410 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
3411 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®); | |
3412 | reg &= ~PCI_PHY_COMA; | |
3413 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); | |
3414 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
3415 | ||
3416 | ||
981d0377 | 3417 | for (i = 0; i < hw->ports; i++) { |
6b0c1480 SH |
3418 | skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); |
3419 | skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
baef58b1 SH |
3420 | } |
3421 | } | |
3422 | ||
3423 | /* turn off hardware timer (unused) */ | |
3424 | skge_write8(hw, B2_TI_CTRL, TIM_STOP); | |
3425 | skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
3426 | skge_write8(hw, B0_LED, LED_STAT_ON); | |
3427 | ||
3428 | /* enable the Tx Arbiters */ | |
981d0377 | 3429 | for (i = 0; i < hw->ports; i++) |
6b0c1480 | 3430 | skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); |
baef58b1 SH |
3431 | |
3432 | /* Initialize ram interface */ | |
3433 | skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); | |
3434 | ||
3435 | skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53); | |
3436 | skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53); | |
3437 | skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53); | |
3438 | skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53); | |
3439 | skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53); | |
3440 | skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53); | |
3441 | skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53); | |
3442 | skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53); | |
3443 | skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53); | |
3444 | skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53); | |
3445 | skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53); | |
3446 | skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53); | |
3447 | ||
3448 | skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK); | |
3449 | ||
3450 | /* Set interrupt moderation for Transmit only | |
3451 | * Receive interrupts avoided by NAPI | |
3452 | */ | |
3453 | skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F); | |
3454 | skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100)); | |
3455 | skge_write32(hw, B2_IRQM_CTRL, TIM_START); | |
3456 | ||
baef58b1 SH |
3457 | skge_write32(hw, B0_IMSK, hw->intr_mask); |
3458 | ||
d85b514f | 3459 | mutex_lock(&hw->phy_mutex); |
981d0377 | 3460 | for (i = 0; i < hw->ports; i++) { |
baef58b1 SH |
3461 | if (hw->chip_id == CHIP_ID_GENESIS) |
3462 | genesis_reset(hw, i); | |
3463 | else | |
3464 | yukon_reset(hw, i); | |
3465 | } | |
d85b514f | 3466 | mutex_unlock(&hw->phy_mutex); |
baef58b1 SH |
3467 | |
3468 | return 0; | |
3469 | } | |
3470 | ||
3471 | /* Initialize network device */ | |
981d0377 SH |
3472 | static struct net_device *skge_devinit(struct skge_hw *hw, int port, |
3473 | int highmem) | |
baef58b1 SH |
3474 | { |
3475 | struct skge_port *skge; | |
3476 | struct net_device *dev = alloc_etherdev(sizeof(*skge)); | |
3477 | ||
3478 | if (!dev) { | |
1479d13c | 3479 | dev_err(&hw->pdev->dev, "etherdev alloc failed\n"); |
baef58b1 SH |
3480 | return NULL; |
3481 | } | |
3482 | ||
3483 | SET_MODULE_OWNER(dev); | |
3484 | SET_NETDEV_DEV(dev, &hw->pdev->dev); | |
3485 | dev->open = skge_up; | |
3486 | dev->stop = skge_down; | |
2cd8e5d3 | 3487 | dev->do_ioctl = skge_ioctl; |
baef58b1 SH |
3488 | dev->hard_start_xmit = skge_xmit_frame; |
3489 | dev->get_stats = skge_get_stats; | |
3490 | if (hw->chip_id == CHIP_ID_GENESIS) | |
3491 | dev->set_multicast_list = genesis_set_multicast; | |
3492 | else | |
3493 | dev->set_multicast_list = yukon_set_multicast; | |
3494 | ||
3495 | dev->set_mac_address = skge_set_mac_address; | |
3496 | dev->change_mtu = skge_change_mtu; | |
3497 | SET_ETHTOOL_OPS(dev, &skge_ethtool_ops); | |
3498 | dev->tx_timeout = skge_tx_timeout; | |
3499 | dev->watchdog_timeo = TX_WATCHDOG; | |
3500 | dev->poll = skge_poll; | |
3501 | dev->weight = NAPI_WEIGHT; | |
3502 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3503 | dev->poll_controller = skge_netpoll; | |
3504 | #endif | |
3505 | dev->irq = hw->pdev->irq; | |
513f533e | 3506 | |
981d0377 SH |
3507 | if (highmem) |
3508 | dev->features |= NETIF_F_HIGHDMA; | |
baef58b1 SH |
3509 | |
3510 | skge = netdev_priv(dev); | |
3511 | skge->netdev = dev; | |
3512 | skge->hw = hw; | |
3513 | skge->msg_enable = netif_msg_init(debug, default_msg); | |
3514 | skge->tx_ring.count = DEFAULT_TX_RING_SIZE; | |
3515 | skge->rx_ring.count = DEFAULT_RX_RING_SIZE; | |
3516 | ||
3517 | /* Auto speed and flow control */ | |
3518 | skge->autoneg = AUTONEG_ENABLE; | |
5d5c8e03 | 3519 | skge->flow_control = FLOW_MODE_SYM_OR_REM; |
baef58b1 SH |
3520 | skge->duplex = -1; |
3521 | skge->speed = -1; | |
31b619c5 | 3522 | skge->advertising = skge_supported_modes(hw); |
a504e64a | 3523 | skge->wol = pci_wake_enabled(hw->pdev) ? wol_supported(hw) : 0; |
baef58b1 SH |
3524 | |
3525 | hw->dev[port] = dev; | |
3526 | ||
3527 | skge->port = port; | |
3528 | ||
64f6b64d | 3529 | /* Only used for Genesis XMAC */ |
c4028958 | 3530 | INIT_DELAYED_WORK(&skge->link_thread, xm_link_timer); |
64f6b64d | 3531 | |
baef58b1 SH |
3532 | if (hw->chip_id != CHIP_ID_GENESIS) { |
3533 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; | |
3534 | skge->rx_csum = 1; | |
3535 | } | |
3536 | ||
3537 | /* read the mac address */ | |
3538 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN); | |
56230d53 | 3539 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
baef58b1 SH |
3540 | |
3541 | /* device is off until link detection */ | |
3542 | netif_carrier_off(dev); | |
3543 | netif_stop_queue(dev); | |
3544 | ||
3545 | return dev; | |
3546 | } | |
3547 | ||
3548 | static void __devinit skge_show_addr(struct net_device *dev) | |
3549 | { | |
3550 | const struct skge_port *skge = netdev_priv(dev); | |
3551 | ||
3552 | if (netif_msg_probe(skge)) | |
3553 | printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n", | |
3554 | dev->name, | |
3555 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
3556 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
3557 | } | |
3558 | ||
3559 | static int __devinit skge_probe(struct pci_dev *pdev, | |
3560 | const struct pci_device_id *ent) | |
3561 | { | |
3562 | struct net_device *dev, *dev1; | |
3563 | struct skge_hw *hw; | |
3564 | int err, using_dac = 0; | |
3565 | ||
203babb6 SH |
3566 | err = pci_enable_device(pdev); |
3567 | if (err) { | |
1479d13c | 3568 | dev_err(&pdev->dev, "cannot enable PCI device\n"); |
baef58b1 SH |
3569 | goto err_out; |
3570 | } | |
3571 | ||
203babb6 SH |
3572 | err = pci_request_regions(pdev, DRV_NAME); |
3573 | if (err) { | |
1479d13c | 3574 | dev_err(&pdev->dev, "cannot obtain PCI resources\n"); |
baef58b1 SH |
3575 | goto err_out_disable_pdev; |
3576 | } | |
3577 | ||
3578 | pci_set_master(pdev); | |
3579 | ||
93aea718 | 3580 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
baef58b1 | 3581 | using_dac = 1; |
77783a78 | 3582 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
93aea718 SH |
3583 | } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) { |
3584 | using_dac = 0; | |
3585 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
3586 | } | |
3587 | ||
3588 | if (err) { | |
1479d13c | 3589 | dev_err(&pdev->dev, "no usable DMA configuration\n"); |
93aea718 | 3590 | goto err_out_free_regions; |
baef58b1 SH |
3591 | } |
3592 | ||
3593 | #ifdef __BIG_ENDIAN | |
8f3f8193 | 3594 | /* byte swap descriptors in hardware */ |
baef58b1 SH |
3595 | { |
3596 | u32 reg; | |
3597 | ||
3598 | pci_read_config_dword(pdev, PCI_DEV_REG2, ®); | |
3599 | reg |= PCI_REV_DESC; | |
3600 | pci_write_config_dword(pdev, PCI_DEV_REG2, reg); | |
3601 | } | |
3602 | #endif | |
3603 | ||
3604 | err = -ENOMEM; | |
7e863061 | 3605 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
baef58b1 | 3606 | if (!hw) { |
1479d13c | 3607 | dev_err(&pdev->dev, "cannot allocate hardware struct\n"); |
baef58b1 SH |
3608 | goto err_out_free_regions; |
3609 | } | |
3610 | ||
baef58b1 | 3611 | hw->pdev = pdev; |
d85b514f | 3612 | mutex_init(&hw->phy_mutex); |
c4028958 | 3613 | INIT_WORK(&hw->phy_work, skge_extirq); |
d38efdd6 | 3614 | spin_lock_init(&hw->hw_lock); |
baef58b1 SH |
3615 | |
3616 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
3617 | if (!hw->regs) { | |
1479d13c | 3618 | dev_err(&pdev->dev, "cannot map device registers\n"); |
baef58b1 SH |
3619 | goto err_out_free_hw; |
3620 | } | |
3621 | ||
baef58b1 SH |
3622 | err = skge_reset(hw); |
3623 | if (err) | |
ccdaa2a9 | 3624 | goto err_out_iounmap; |
baef58b1 | 3625 | |
7c7459d1 GKH |
3626 | printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n", |
3627 | (unsigned long long)pci_resource_start(pdev, 0), pdev->irq, | |
981d0377 | 3628 | skge_board_name(hw), hw->chip_rev); |
baef58b1 | 3629 | |
ccdaa2a9 SH |
3630 | dev = skge_devinit(hw, 0, using_dac); |
3631 | if (!dev) | |
baef58b1 SH |
3632 | goto err_out_led_off; |
3633 | ||
fae87592 | 3634 | /* Some motherboards are broken and has zero in ROM. */ |
1479d13c SH |
3635 | if (!is_valid_ether_addr(dev->dev_addr)) |
3636 | dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n"); | |
631ae320 | 3637 | |
203babb6 SH |
3638 | err = register_netdev(dev); |
3639 | if (err) { | |
1479d13c | 3640 | dev_err(&pdev->dev, "cannot register net device\n"); |
baef58b1 SH |
3641 | goto err_out_free_netdev; |
3642 | } | |
3643 | ||
ccdaa2a9 SH |
3644 | err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw); |
3645 | if (err) { | |
1479d13c | 3646 | dev_err(&pdev->dev, "%s: cannot assign irq %d\n", |
ccdaa2a9 SH |
3647 | dev->name, pdev->irq); |
3648 | goto err_out_unregister; | |
3649 | } | |
baef58b1 SH |
3650 | skge_show_addr(dev); |
3651 | ||
981d0377 | 3652 | if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) { |
baef58b1 SH |
3653 | if (register_netdev(dev1) == 0) |
3654 | skge_show_addr(dev1); | |
3655 | else { | |
3656 | /* Failure to register second port need not be fatal */ | |
1479d13c | 3657 | dev_warn(&pdev->dev, "register of second port failed\n"); |
baef58b1 SH |
3658 | hw->dev[1] = NULL; |
3659 | free_netdev(dev1); | |
3660 | } | |
3661 | } | |
ccdaa2a9 | 3662 | pci_set_drvdata(pdev, hw); |
baef58b1 SH |
3663 | |
3664 | return 0; | |
3665 | ||
ccdaa2a9 SH |
3666 | err_out_unregister: |
3667 | unregister_netdev(dev); | |
baef58b1 SH |
3668 | err_out_free_netdev: |
3669 | free_netdev(dev); | |
3670 | err_out_led_off: | |
3671 | skge_write16(hw, B0_LED, LED_STAT_OFF); | |
baef58b1 SH |
3672 | err_out_iounmap: |
3673 | iounmap(hw->regs); | |
3674 | err_out_free_hw: | |
3675 | kfree(hw); | |
3676 | err_out_free_regions: | |
3677 | pci_release_regions(pdev); | |
3678 | err_out_disable_pdev: | |
3679 | pci_disable_device(pdev); | |
3680 | pci_set_drvdata(pdev, NULL); | |
3681 | err_out: | |
3682 | return err; | |
3683 | } | |
3684 | ||
3685 | static void __devexit skge_remove(struct pci_dev *pdev) | |
3686 | { | |
3687 | struct skge_hw *hw = pci_get_drvdata(pdev); | |
3688 | struct net_device *dev0, *dev1; | |
3689 | ||
95566065 | 3690 | if (!hw) |
baef58b1 SH |
3691 | return; |
3692 | ||
3693 | if ((dev1 = hw->dev[1])) | |
3694 | unregister_netdev(dev1); | |
3695 | dev0 = hw->dev[0]; | |
3696 | unregister_netdev(dev0); | |
3697 | ||
7c442fa1 SH |
3698 | spin_lock_irq(&hw->hw_lock); |
3699 | hw->intr_mask = 0; | |
46a60f2d | 3700 | skge_write32(hw, B0_IMSK, 0); |
78bc2186 | 3701 | skge_read32(hw, B0_IMSK); |
7c442fa1 SH |
3702 | spin_unlock_irq(&hw->hw_lock); |
3703 | ||
46a60f2d | 3704 | skge_write16(hw, B0_LED, LED_STAT_OFF); |
46a60f2d SH |
3705 | skge_write8(hw, B0_CTST, CS_RST_SET); |
3706 | ||
d85b514f | 3707 | flush_scheduled_work(); |
baef58b1 SH |
3708 | |
3709 | free_irq(pdev->irq, hw); | |
3710 | pci_release_regions(pdev); | |
3711 | pci_disable_device(pdev); | |
3712 | if (dev1) | |
3713 | free_netdev(dev1); | |
3714 | free_netdev(dev0); | |
46a60f2d | 3715 | |
baef58b1 SH |
3716 | iounmap(hw->regs); |
3717 | kfree(hw); | |
3718 | pci_set_drvdata(pdev, NULL); | |
3719 | } | |
3720 | ||
3721 | #ifdef CONFIG_PM | |
a504e64a SH |
3722 | static int vaux_avail(struct pci_dev *pdev) |
3723 | { | |
3724 | int pm_cap; | |
3725 | ||
3726 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
3727 | if (pm_cap) { | |
3728 | u16 ctl; | |
3729 | pci_read_config_word(pdev, pm_cap + PCI_PM_PMC, &ctl); | |
3730 | if (ctl & PCI_PM_CAP_AUX_POWER) | |
3731 | return 1; | |
3732 | } | |
3733 | return 0; | |
3734 | } | |
3735 | ||
3736 | ||
2a569579 | 3737 | static int skge_suspend(struct pci_dev *pdev, pm_message_t state) |
baef58b1 SH |
3738 | { |
3739 | struct skge_hw *hw = pci_get_drvdata(pdev); | |
a504e64a SH |
3740 | int i, err, wol = 0; |
3741 | ||
3742 | err = pci_save_state(pdev); | |
3743 | if (err) | |
3744 | return err; | |
baef58b1 | 3745 | |
d38efdd6 | 3746 | for (i = 0; i < hw->ports; i++) { |
baef58b1 | 3747 | struct net_device *dev = hw->dev[i]; |
a504e64a | 3748 | struct skge_port *skge = netdev_priv(dev); |
baef58b1 | 3749 | |
a504e64a SH |
3750 | if (netif_running(dev)) |
3751 | skge_down(dev); | |
3752 | if (skge->wol) | |
3753 | skge_wol_init(skge); | |
d38efdd6 | 3754 | |
a504e64a | 3755 | wol |= skge->wol; |
baef58b1 SH |
3756 | } |
3757 | ||
a504e64a SH |
3758 | if (wol && vaux_avail(pdev)) |
3759 | skge_write8(hw, B0_POWER_CTRL, | |
3760 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); | |
3761 | ||
d38efdd6 | 3762 | skge_write32(hw, B0_IMSK, 0); |
2a569579 | 3763 | pci_enable_wake(pdev, pci_choose_state(pdev, state), wol); |
baef58b1 SH |
3764 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
3765 | ||
3766 | return 0; | |
3767 | } | |
3768 | ||
3769 | static int skge_resume(struct pci_dev *pdev) | |
3770 | { | |
3771 | struct skge_hw *hw = pci_get_drvdata(pdev); | |
d38efdd6 | 3772 | int i, err; |
baef58b1 | 3773 | |
a504e64a SH |
3774 | err = pci_set_power_state(pdev, PCI_D0); |
3775 | if (err) | |
3776 | goto out; | |
3777 | ||
3778 | err = pci_restore_state(pdev); | |
3779 | if (err) | |
3780 | goto out; | |
3781 | ||
baef58b1 SH |
3782 | pci_enable_wake(pdev, PCI_D0, 0); |
3783 | ||
d38efdd6 SH |
3784 | err = skge_reset(hw); |
3785 | if (err) | |
3786 | goto out; | |
baef58b1 | 3787 | |
d38efdd6 | 3788 | for (i = 0; i < hw->ports; i++) { |
baef58b1 | 3789 | struct net_device *dev = hw->dev[i]; |
d38efdd6 | 3790 | |
d38efdd6 SH |
3791 | if (netif_running(dev)) { |
3792 | err = skge_up(dev); | |
3793 | ||
3794 | if (err) { | |
3795 | printk(KERN_ERR PFX "%s: could not up: %d\n", | |
3796 | dev->name, err); | |
edd702e8 | 3797 | dev_close(dev); |
d38efdd6 SH |
3798 | goto out; |
3799 | } | |
baef58b1 SH |
3800 | } |
3801 | } | |
d38efdd6 SH |
3802 | out: |
3803 | return err; | |
baef58b1 SH |
3804 | } |
3805 | #endif | |
3806 | ||
3807 | static struct pci_driver skge_driver = { | |
3808 | .name = DRV_NAME, | |
3809 | .id_table = skge_id_table, | |
3810 | .probe = skge_probe, | |
3811 | .remove = __devexit_p(skge_remove), | |
3812 | #ifdef CONFIG_PM | |
3813 | .suspend = skge_suspend, | |
3814 | .resume = skge_resume, | |
3815 | #endif | |
3816 | }; | |
3817 | ||
3818 | static int __init skge_init_module(void) | |
3819 | { | |
29917620 | 3820 | return pci_register_driver(&skge_driver); |
baef58b1 SH |
3821 | } |
3822 | ||
3823 | static void __exit skge_cleanup_module(void) | |
3824 | { | |
3825 | pci_unregister_driver(&skge_driver); | |
3826 | } | |
3827 | ||
3828 | module_init(skge_init_module); | |
3829 | module_exit(skge_cleanup_module); |