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[PATCH] skge: eliminate Yukon2 hooks
[net-next-2.6.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/config.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/moduleparam.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/delay.h>
38#include <linux/crc32.h>
4075400b 39#include <linux/dma-mapping.h>
baef58b1
SH		 40#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
45#define DRV_VERSION "0.6"
46#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
51#define MAX_RX_RING_SIZE 4096
52#define PHY_RETRIES 1000
53#define ETH_JUMBO_MTU 9000
54#define TX_WATCHDOG (5 * HZ)
55#define NAPI_WEIGHT 64
56#define BLINK_HZ (HZ/4)
57#define LINK_POLL_HZ (HZ/10)
58
59MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
60MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
61MODULE_LICENSE("GPL");
62MODULE_VERSION(DRV_VERSION);
63
64static const u32 default_msg
65 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
66 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
67
68static int debug = -1; /* defaults above */
69module_param(debug, int, 0);
70MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
71
72static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 73 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
75 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
78 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
81 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032) },
83 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
baef58b1
SH		 84 { 0 }
85};
86MODULE_DEVICE_TABLE(pci, skge_id_table);
87
88static int skge_up(struct net_device *dev);
89static int skge_down(struct net_device *dev);
90static void skge_tx_clean(struct skge_port *skge);
6b0c1480
SH		 91static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
92static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 93static void genesis_get_stats(struct skge_port *skge, u64 *data);
94static void yukon_get_stats(struct skge_port *skge, u64 *data);
95static void yukon_init(struct skge_hw *hw, int port);
96static void yukon_reset(struct skge_hw *hw, int port);
97static void genesis_mac_init(struct skge_hw *hw, int port);
98static void genesis_reset(struct skge_hw *hw, int port);
99
100static const int txqaddr[] = { Q_XA1, Q_XA2 };
101static const int rxqaddr[] = { Q_R1, Q_R2 };
102static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
103static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
104
105/* Don't need to look at whole 16K.
106 * last interesting register is descriptor poll timer.
107 */
108#define SKGE_REGS_LEN (29*128)
109
110static int skge_get_regs_len(struct net_device *dev)
111{
112 return SKGE_REGS_LEN;
113}
114
115/*
116 * Returns copy of control register region
117 * I/O region is divided into banks and certain regions are unreadable
118 */
119static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
120 void *p)
121{
122 const struct skge_port *skge = netdev_priv(dev);
123 unsigned long offs;
124 const void __iomem *io = skge->hw->regs;
125 static const unsigned long bankmap
126 = (1<<0) | (1<<2) | (1<<8) | (1<<9)
127 | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
128 | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
129 | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
130
131 regs->version = 1;
132 for (offs = 0; offs < regs->len; offs += 128) {
133 u32 len = min_t(u32, 128, regs->len - offs);
134
135 if (bankmap & (1<<(offs/128)))
136 memcpy_fromio(p + offs, io + offs, len);
137 else
138 memset(p + offs, 0, len);
139 }
140}
141
142/* Wake on Lan only supported on Yukon chps with rev 1 or above */
143static int wol_supported(const struct skge_hw *hw)
144{
145 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 146 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 147}
148
149static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
150{
151 struct skge_port *skge = netdev_priv(dev);
152
153 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
154 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
155}
156
157static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
158{
159 struct skge_port *skge = netdev_priv(dev);
160 struct skge_hw *hw = skge->hw;
161
95566065 162 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 163 return -EOPNOTSUPP;
164
165 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
166 return -EOPNOTSUPP;
167
168 skge->wol = wol->wolopts == WAKE_MAGIC;
169
170 if (skge->wol) {
171 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
172
173 skge_write16(hw, WOL_CTRL_STAT,
174 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
175 WOL_CTL_ENA_MAGIC_PKT_UNIT);
176 } else
177 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
178
179 return 0;
180}
181
182
183static int skge_get_settings(struct net_device *dev,
184 struct ethtool_cmd *ecmd)
185{
186 struct skge_port *skge = netdev_priv(dev);
187 struct skge_hw *hw = skge->hw;
188
189 ecmd->transceiver = XCVR_INTERNAL;
190
191 if (iscopper(hw)) {
192 if (hw->chip_id == CHIP_ID_GENESIS)
193 ecmd->supported = SUPPORTED_1000baseT_Full
194 | SUPPORTED_1000baseT_Half
195 | SUPPORTED_Autoneg | SUPPORTED_TP;
196 else {
197 ecmd->supported = SUPPORTED_10baseT_Half
198 | SUPPORTED_10baseT_Full
199 | SUPPORTED_100baseT_Half
200 | SUPPORTED_100baseT_Full
201 | SUPPORTED_1000baseT_Half
202 | SUPPORTED_1000baseT_Full
203 | SUPPORTED_Autoneg| SUPPORTED_TP;
204
205 if (hw->chip_id == CHIP_ID_YUKON)
206 ecmd->supported &= ~SUPPORTED_1000baseT_Half;
207
208 else if (hw->chip_id == CHIP_ID_YUKON_FE)
209 ecmd->supported &= ~(SUPPORTED_1000baseT_Half
210 | SUPPORTED_1000baseT_Full);
211 }
212
213 ecmd->port = PORT_TP;
214 ecmd->phy_address = hw->phy_addr;
215 } else {
216 ecmd->supported = SUPPORTED_1000baseT_Full
217 | SUPPORTED_FIBRE
218 | SUPPORTED_Autoneg;
219
220 ecmd->port = PORT_FIBRE;
221 }
222
223 ecmd->advertising = skge->advertising;
224 ecmd->autoneg = skge->autoneg;
225 ecmd->speed = skge->speed;
226 ecmd->duplex = skge->duplex;
227 return 0;
228}
229
230static u32 skge_modes(const struct skge_hw *hw)
231{
232 u32 modes = ADVERTISED_Autoneg
233 | ADVERTISED_1000baseT_Full | ADVERTISED_1000baseT_Half
234 | ADVERTISED_100baseT_Full | ADVERTISED_100baseT_Half
235 | ADVERTISED_10baseT_Full | ADVERTISED_10baseT_Half;
236
237 if (iscopper(hw)) {
238 modes |= ADVERTISED_TP;
95566065 239 switch (hw->chip_id) {
baef58b1
SH		 240 case CHIP_ID_GENESIS:
241 modes &= ~(ADVERTISED_100baseT_Full
242 | ADVERTISED_100baseT_Half
243 | ADVERTISED_10baseT_Full
244 | ADVERTISED_10baseT_Half);
245 break;
246
247 case CHIP_ID_YUKON:
248 modes &= ~ADVERTISED_1000baseT_Half;
249 break;
250
251 case CHIP_ID_YUKON_FE:
252 modes &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
253 break;
254 }
255 } else {
256 modes |= ADVERTISED_FIBRE;
257 modes &= ~ADVERTISED_1000baseT_Half;
258 }
259 return modes;
260}
261
262static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
263{
264 struct skge_port *skge = netdev_priv(dev);
265 const struct skge_hw *hw = skge->hw;
266
267 if (ecmd->autoneg == AUTONEG_ENABLE) {
268 if (ecmd->advertising & skge_modes(hw))
269 return -EINVAL;
270 } else {
95566065 271 switch (ecmd->speed) {
baef58b1
SH		 272 case SPEED_1000:
273 if (hw->chip_id == CHIP_ID_YUKON_FE)
274 return -EINVAL;
275 break;
276 case SPEED_100:
277 case SPEED_10:
278 if (iscopper(hw) || hw->chip_id == CHIP_ID_GENESIS)
279 return -EINVAL;
280 break;
281 default:
282 return -EINVAL;
283 }
284 }
285
286 skge->autoneg = ecmd->autoneg;
287 skge->speed = ecmd->speed;
288 skge->duplex = ecmd->duplex;
289 skge->advertising = ecmd->advertising;
290
291 if (netif_running(dev)) {
292 skge_down(dev);
293 skge_up(dev);
294 }
295 return (0);
296}
297
298static void skge_get_drvinfo(struct net_device *dev,
299 struct ethtool_drvinfo *info)
300{
301 struct skge_port *skge = netdev_priv(dev);
302
303 strcpy(info->driver, DRV_NAME);
304 strcpy(info->version, DRV_VERSION);
305 strcpy(info->fw_version, "N/A");
306 strcpy(info->bus_info, pci_name(skge->hw->pdev));
307}
308
309static const struct skge_stat {
310 char name[ETH_GSTRING_LEN];
311 u16 xmac_offset;
312 u16 gma_offset;
313} skge_stats[] = {
314 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
315 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
316
317 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
318 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
319 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
320 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
321 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
322 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
323 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
324 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
325
326 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
327 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
328 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
329 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
330 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
331 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
332
333 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
334 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
335 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
336 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
337 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
338};
339
340static int skge_get_stats_count(struct net_device *dev)
341{
342 return ARRAY_SIZE(skge_stats);
343}
344
345static void skge_get_ethtool_stats(struct net_device *dev,
346 struct ethtool_stats *stats, u64 *data)
347{
348 struct skge_port *skge = netdev_priv(dev);
349
350 if (skge->hw->chip_id == CHIP_ID_GENESIS)
351 genesis_get_stats(skge, data);
352 else
353 yukon_get_stats(skge, data);
354}
355
356/* Use hardware MIB variables for critical path statistics and
357 * transmit feedback not reported at interrupt.
358 * Other errors are accounted for in interrupt handler.
359 */
360static struct net_device_stats *skge_get_stats(struct net_device *dev)
361{
362 struct skge_port *skge = netdev_priv(dev);
363 u64 data[ARRAY_SIZE(skge_stats)];
364
365 if (skge->hw->chip_id == CHIP_ID_GENESIS)
366 genesis_get_stats(skge, data);
367 else
368 yukon_get_stats(skge, data);
369
370 skge->net_stats.tx_bytes = data[0];
371 skge->net_stats.rx_bytes = data[1];
372 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
373 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
374 skge->net_stats.multicast = data[5] + data[7];
375 skge->net_stats.collisions = data[10];
376 skge->net_stats.tx_aborted_errors = data[12];
377
378 return &skge->net_stats;
379}
380
381static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
382{
383 int i;
384
95566065 385 switch (stringset) {
baef58b1
SH		 386 case ETH_SS_STATS:
387 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
388 memcpy(data + i * ETH_GSTRING_LEN,
389 skge_stats[i].name, ETH_GSTRING_LEN);
390 break;
391 }
392}
393
394static void skge_get_ring_param(struct net_device *dev,
395 struct ethtool_ringparam *p)
396{
397 struct skge_port *skge = netdev_priv(dev);
398
399 p->rx_max_pending = MAX_RX_RING_SIZE;
400 p->tx_max_pending = MAX_TX_RING_SIZE;
401 p->rx_mini_max_pending = 0;
402 p->rx_jumbo_max_pending = 0;
403
404 p->rx_pending = skge->rx_ring.count;
405 p->tx_pending = skge->tx_ring.count;
406 p->rx_mini_pending = 0;
407 p->rx_jumbo_pending = 0;
408}
409
410static int skge_set_ring_param(struct net_device *dev,
411 struct ethtool_ringparam *p)
412{
413 struct skge_port *skge = netdev_priv(dev);
414
415 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
416 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
417 return -EINVAL;
418
419 skge->rx_ring.count = p->rx_pending;
420 skge->tx_ring.count = p->tx_pending;
421
422 if (netif_running(dev)) {
423 skge_down(dev);
424 skge_up(dev);
425 }
426
427 return 0;
428}
429
430static u32 skge_get_msglevel(struct net_device *netdev)
431{
432 struct skge_port *skge = netdev_priv(netdev);
433 return skge->msg_enable;
434}
435
436static void skge_set_msglevel(struct net_device *netdev, u32 value)
437{
438 struct skge_port *skge = netdev_priv(netdev);
439 skge->msg_enable = value;
440}
441
442static int skge_nway_reset(struct net_device *dev)
443{
444 struct skge_port *skge = netdev_priv(dev);
445 struct skge_hw *hw = skge->hw;
446 int port = skge->port;
447
448 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
449 return -EINVAL;
450
451 spin_lock_bh(&hw->phy_lock);
452 if (hw->chip_id == CHIP_ID_GENESIS) {
453 genesis_reset(hw, port);
454 genesis_mac_init(hw, port);
455 } else {
456 yukon_reset(hw, port);
457 yukon_init(hw, port);
458 }
459 spin_unlock_bh(&hw->phy_lock);
460 return 0;
461}
462
463static int skge_set_sg(struct net_device *dev, u32 data)
464{
465 struct skge_port *skge = netdev_priv(dev);
466 struct skge_hw *hw = skge->hw;
467
468 if (hw->chip_id == CHIP_ID_GENESIS && data)
469 return -EOPNOTSUPP;
470 return ethtool_op_set_sg(dev, data);
471}
472
473static int skge_set_tx_csum(struct net_device *dev, u32 data)
474{
475 struct skge_port *skge = netdev_priv(dev);
476 struct skge_hw *hw = skge->hw;
477
478 if (hw->chip_id == CHIP_ID_GENESIS && data)
479 return -EOPNOTSUPP;
480
481 return ethtool_op_set_tx_csum(dev, data);
482}
483
484static u32 skge_get_rx_csum(struct net_device *dev)
485{
486 struct skge_port *skge = netdev_priv(dev);
487
488 return skge->rx_csum;
489}
490
491/* Only Yukon supports checksum offload. */
492static int skge_set_rx_csum(struct net_device *dev, u32 data)
493{
494 struct skge_port *skge = netdev_priv(dev);
495
496 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
497 return -EOPNOTSUPP;
498
499 skge->rx_csum = data;
500 return 0;
501}
502
baef58b1
SH		 503static void skge_get_pauseparam(struct net_device *dev,
504 struct ethtool_pauseparam *ecmd)
505{
506 struct skge_port *skge = netdev_priv(dev);
507
508 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
509 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
510 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
511 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
512
513 ecmd->autoneg = skge->autoneg;
514}
515
516static int skge_set_pauseparam(struct net_device *dev,
517 struct ethtool_pauseparam *ecmd)
518{
519 struct skge_port *skge = netdev_priv(dev);
520
521 skge->autoneg = ecmd->autoneg;
522 if (ecmd->rx_pause && ecmd->tx_pause)
523 skge->flow_control = FLOW_MODE_SYMMETRIC;
95566065 524 else if (ecmd->rx_pause && !ecmd->tx_pause)
baef58b1 525 skge->flow_control = FLOW_MODE_REM_SEND;
95566065 526 else if (!ecmd->rx_pause && ecmd->tx_pause)
baef58b1
SH		 527 skge->flow_control = FLOW_MODE_LOC_SEND;
528 else
529 skge->flow_control = FLOW_MODE_NONE;
530
531 if (netif_running(dev)) {
532 skge_down(dev);
533 skge_up(dev);
534 }
535 return 0;
536}
537
538/* Chip internal frequency for clock calculations */
539static inline u32 hwkhz(const struct skge_hw *hw)
540{
541 if (hw->chip_id == CHIP_ID_GENESIS)
542 return 53215; /* or: 53.125 MHz */
543 else if (hw->chip_id == CHIP_ID_YUKON_EC)
544 return 125000; /* or: 125.000 MHz */
545 else
546 return 78215; /* or: 78.125 MHz */
547}
548
549/* Chip hz to microseconds */
550static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
551{
552 return (ticks * 1000) / hwkhz(hw);
553}
554
555/* Microseconds to chip hz */
556static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
557{
558 return hwkhz(hw) * usec / 1000;
559}
560
561static int skge_get_coalesce(struct net_device *dev,
562 struct ethtool_coalesce *ecmd)
563{
564 struct skge_port *skge = netdev_priv(dev);
565 struct skge_hw *hw = skge->hw;
566 int port = skge->port;
567
568 ecmd->rx_coalesce_usecs = 0;
569 ecmd->tx_coalesce_usecs = 0;
570
571 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
572 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
573 u32 msk = skge_read32(hw, B2_IRQM_MSK);
574
575 if (msk & rxirqmask[port])
576 ecmd->rx_coalesce_usecs = delay;
577 if (msk & txirqmask[port])
578 ecmd->tx_coalesce_usecs = delay;
579 }
580
581 return 0;
582}
583
584/* Note: interrupt timer is per board, but can turn on/off per port */
585static int skge_set_coalesce(struct net_device *dev,
586 struct ethtool_coalesce *ecmd)
587{
588 struct skge_port *skge = netdev_priv(dev);
589 struct skge_hw *hw = skge->hw;
590 int port = skge->port;
591 u32 msk = skge_read32(hw, B2_IRQM_MSK);
592 u32 delay = 25;
593
594 if (ecmd->rx_coalesce_usecs == 0)
595 msk &= ~rxirqmask[port];
596 else if (ecmd->rx_coalesce_usecs < 25 ||
597 ecmd->rx_coalesce_usecs > 33333)
598 return -EINVAL;
599 else {
600 msk |= rxirqmask[port];
601 delay = ecmd->rx_coalesce_usecs;
602 }
603
604 if (ecmd->tx_coalesce_usecs == 0)
605 msk &= ~txirqmask[port];
606 else if (ecmd->tx_coalesce_usecs < 25 ||
607 ecmd->tx_coalesce_usecs > 33333)
608 return -EINVAL;
609 else {
610 msk |= txirqmask[port];
611 delay = min(delay, ecmd->rx_coalesce_usecs);
612 }
613
614 skge_write32(hw, B2_IRQM_MSK, msk);
615 if (msk == 0)
616 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
617 else {
618 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
619 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
620 }
621 return 0;
622}
623
624static void skge_led_on(struct skge_hw *hw, int port)
625{
626 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480 627 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
baef58b1
SH		 628 skge_write8(hw, B0_LED, LED_STAT_ON);
629
6b0c1480
SH		 630 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
631 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
632 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1
SH		 633
634 switch (hw->phy_type) {
635 case SK_PHY_BCOM:
6b0c1480 636 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
baef58b1
SH		 637 PHY_B_PEC_LED_ON);
638 break;
639 case SK_PHY_LONE:
6b0c1480 640 xm_phy_write(hw, port, PHY_LONE_LED_CFG,
baef58b1
SH		 641 0x0800);
642 break;
643 default:
6b0c1480
SH		 644 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
645 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
646 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1
SH		 647 }
648 } else {
6b0c1480
SH		 649 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
650 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
baef58b1
SH		 651 PHY_M_LED_MO_DUP(MO_LED_ON) |
652 PHY_M_LED_MO_10(MO_LED_ON) |
653 PHY_M_LED_MO_100(MO_LED_ON) |
654 PHY_M_LED_MO_1000(MO_LED_ON) |
655 PHY_M_LED_MO_RX(MO_LED_ON));
656 }
657}
658
659static void skge_led_off(struct skge_hw *hw, int port)
660{
661 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480 662 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
baef58b1
SH		 663 skge_write8(hw, B0_LED, LED_STAT_OFF);
664
6b0c1480
SH		 665 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
666 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
baef58b1
SH		 667
668 switch (hw->phy_type) {
669 case SK_PHY_BCOM:
6b0c1480 670 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
baef58b1
SH		 671 PHY_B_PEC_LED_OFF);
672 break;
673 case SK_PHY_LONE:
6b0c1480 674 xm_phy_write(hw, port, PHY_LONE_LED_CFG,
baef58b1
SH		 675 PHY_L_LC_LEDT);
676 break;
677 default:
6b0c1480
SH		 678 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
679 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
baef58b1
SH		 680 }
681 } else {
6b0c1480
SH		 682 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
683 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
baef58b1
SH		 684 PHY_M_LED_MO_DUP(MO_LED_OFF) |
685 PHY_M_LED_MO_10(MO_LED_OFF) |
686 PHY_M_LED_MO_100(MO_LED_OFF) |
687 PHY_M_LED_MO_1000(MO_LED_OFF) |
688 PHY_M_LED_MO_RX(MO_LED_OFF));
689 }
690}
691
692static void skge_blink_timer(unsigned long data)
693{
694 struct skge_port *skge = (struct skge_port *) data;
695 struct skge_hw *hw = skge->hw;
696 unsigned long flags;
697
698 spin_lock_irqsave(&hw->phy_lock, flags);
699 if (skge->blink_on)
700 skge_led_on(hw, skge->port);
701 else
702 skge_led_off(hw, skge->port);
703 spin_unlock_irqrestore(&hw->phy_lock, flags);
704
705 skge->blink_on = !skge->blink_on;
706 mod_timer(&skge->led_blink, jiffies + BLINK_HZ);
707}
708
709/* blink LED's for finding board */
710static int skge_phys_id(struct net_device *dev, u32 data)
711{
712 struct skge_port *skge = netdev_priv(dev);
713
95566065 714 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
baef58b1
SH		 715 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
716
717 /* start blinking */
718 skge->blink_on = 1;
719 mod_timer(&skge->led_blink, jiffies+1);
720
721 msleep_interruptible(data * 1000);
722 del_timer_sync(&skge->led_blink);
723
724 skge_led_off(skge->hw, skge->port);
725
726 return 0;
727}
728
729static struct ethtool_ops skge_ethtool_ops = {
730 .get_settings = skge_get_settings,
731 .set_settings = skge_set_settings,
732 .get_drvinfo = skge_get_drvinfo,
733 .get_regs_len = skge_get_regs_len,
734 .get_regs = skge_get_regs,
735 .get_wol = skge_get_wol,
736 .set_wol = skge_set_wol,
737 .get_msglevel = skge_get_msglevel,
738 .set_msglevel = skge_set_msglevel,
739 .nway_reset = skge_nway_reset,
740 .get_link = ethtool_op_get_link,
741 .get_ringparam = skge_get_ring_param,
742 .set_ringparam = skge_set_ring_param,
743 .get_pauseparam = skge_get_pauseparam,
744 .set_pauseparam = skge_set_pauseparam,
745 .get_coalesce = skge_get_coalesce,
746 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 747 .get_sg = ethtool_op_get_sg,
748 .set_sg = skge_set_sg,
749 .get_tx_csum = ethtool_op_get_tx_csum,
750 .set_tx_csum = skge_set_tx_csum,
751 .get_rx_csum = skge_get_rx_csum,
752 .set_rx_csum = skge_set_rx_csum,
753 .get_strings = skge_get_strings,
754 .phys_id = skge_phys_id,
755 .get_stats_count = skge_get_stats_count,
756 .get_ethtool_stats = skge_get_ethtool_stats,
757};
758
759/*
760 * Allocate ring elements and chain them together
761 * One-to-one association of board descriptors with ring elements
762 */
763static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
764{
765 struct skge_tx_desc *d;
766 struct skge_element *e;
767 int i;
768
769 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
770 if (!ring->start)
771 return -ENOMEM;
772
773 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
774 e->desc = d;
775 if (i == ring->count - 1) {
776 e->next = ring->start;
777 d->next_offset = base;
778 } else {
779 e->next = e + 1;
780 d->next_offset = base + (i+1) * sizeof(*d);
781 }
782 }
783 ring->to_use = ring->to_clean = ring->start;
784
785 return 0;
786}
787
788/* Setup buffer for receiving */
789static inline int skge_rx_alloc(struct skge_port *skge,
790 struct skge_element *e)
791{
792 unsigned long bufsize = skge->netdev->mtu + ETH_HLEN; /* VLAN? */
793 struct skge_rx_desc *rd = e->desc;
794 struct sk_buff *skb;
795 u64 map;
796
797 skb = dev_alloc_skb(bufsize + NET_IP_ALIGN);
798 if (unlikely(!skb)) {
799 printk(KERN_DEBUG PFX "%s: out of memory for receive\n",
800 skge->netdev->name);
801 return -ENOMEM;
802 }
803
804 skb->dev = skge->netdev;
805 skb_reserve(skb, NET_IP_ALIGN);
806
807 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
808 PCI_DMA_FROMDEVICE);
809
810 rd->dma_lo = map;
811 rd->dma_hi = map >> 32;
812 e->skb = skb;
813 rd->csum1_start = ETH_HLEN;
814 rd->csum2_start = ETH_HLEN;
815 rd->csum1 = 0;
816 rd->csum2 = 0;
817
818 wmb();
819
820 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
821 pci_unmap_addr_set(e, mapaddr, map);
822 pci_unmap_len_set(e, maplen, bufsize);
823 return 0;
824}
825
826/* Free all unused buffers in receive ring, assumes receiver stopped */
827static void skge_rx_clean(struct skge_port *skge)
828{
829 struct skge_hw *hw = skge->hw;
830 struct skge_ring *ring = &skge->rx_ring;
831 struct skge_element *e;
832
833 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
834 struct skge_rx_desc *rd = e->desc;
835 rd->control = 0;
836
837 pci_unmap_single(hw->pdev,
838 pci_unmap_addr(e, mapaddr),
839 pci_unmap_len(e, maplen),
840 PCI_DMA_FROMDEVICE);
841 dev_kfree_skb(e->skb);
842 e->skb = NULL;
843 }
844 ring->to_clean = e;
845}
846
847/* Allocate buffers for receive ring
848 * For receive: to_use is refill location
849 * to_clean is next received frame.
850 *
851 * if (to_use == to_clean)
852 * then ring all frames in ring need buffers
853 * if (to_use->next == to_clean)
854 * then ring all frames in ring have buffers
855 */
856static int skge_rx_fill(struct skge_port *skge)
857{
858 struct skge_ring *ring = &skge->rx_ring;
859 struct skge_element *e;
860 int ret = 0;
861
862 for (e = ring->to_use; e->next != ring->to_clean; e = e->next) {
863 if (skge_rx_alloc(skge, e)) {
864 ret = 1;
865 break;
866 }
867
868 }
869 ring->to_use = e;
870
871 return ret;
872}
873
874static void skge_link_up(struct skge_port *skge)
875{
876 netif_carrier_on(skge->netdev);
877 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
878 netif_wake_queue(skge->netdev);
879
880 if (netif_msg_link(skge))
881 printk(KERN_INFO PFX
882 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
883 skge->netdev->name, skge->speed,
884 skge->duplex == DUPLEX_FULL ? "full" : "half",
885 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
886 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
887 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
888 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
889 "unknown");
890}
891
892static void skge_link_down(struct skge_port *skge)
893{
894 netif_carrier_off(skge->netdev);
895 netif_stop_queue(skge->netdev);
896
897 if (netif_msg_link(skge))
898 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
899}
900
6b0c1480 901static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 902{
903 int i;
904 u16 v;
905
6b0c1480
SH		 906 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
907 v = xm_read16(hw, port, XM_PHY_DATA);
baef58b1
SH		 908 if (hw->phy_type != SK_PHY_XMAC) {
909 for (i = 0; i < PHY_RETRIES; i++) {
910 udelay(1);
6b0c1480 911 if (xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 912 & XM_MMU_PHY_RDY)
913 goto ready;
914 }
915
916 printk(KERN_WARNING PFX "%s: phy read timed out\n",
917 hw->dev[port]->name);
918 return 0;
919 ready:
6b0c1480 920 v = xm_read16(hw, port, XM_PHY_DATA);
baef58b1
SH		 921 }
922
923 return v;
924}
925
6b0c1480 926static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 927{
928 int i;
929
6b0c1480 930 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 931 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 932 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1
SH		 933 goto ready;
934 cpu_relax();
935 }
936 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
937 hw->dev[port]->name);
938
939
940 ready:
6b0c1480 941 xm_write16(hw, port, XM_PHY_DATA, val);
baef58b1
SH		 942 for (i = 0; i < PHY_RETRIES; i++) {
943 udelay(1);
6b0c1480 944 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1
SH		 945 return;
946 }
947 printk(KERN_WARNING PFX "%s: phy write timed out\n",
948 hw->dev[port]->name);
949}
950
951static void genesis_init(struct skge_hw *hw)
952{
953 /* set blink source counter */
954 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
955 skge_write8(hw, B2_BSC_CTRL, BSC_START);
956
957 /* configure mac arbiter */
958 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
959
960 /* configure mac arbiter timeout values */
961 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
962 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
963 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
964 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
965
966 skge_write8(hw, B3_MA_RCINI_RX1, 0);
967 skge_write8(hw, B3_MA_RCINI_RX2, 0);
968 skge_write8(hw, B3_MA_RCINI_TX1, 0);
969 skge_write8(hw, B3_MA_RCINI_TX2, 0);
970
971 /* configure packet arbiter timeout */
972 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
973 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
974 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
975 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
976 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
977}
978
979static void genesis_reset(struct skge_hw *hw, int port)
980{
981 int i;
982 u64 zero = 0;
983
984 /* reset the statistics module */
6b0c1480
SH		 985 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
986 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
987 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
988 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
989 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1
SH		 990
991 /* disable all PHY IRQs */
992 if (hw->phy_type == SK_PHY_BCOM)
6b0c1480 993 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 994
6b0c1480 995 xm_outhash(hw, port, XM_HSM, (u8 *) &zero);
baef58b1 996 for (i = 0; i < 15; i++)
6b0c1480
SH		 997 xm_outaddr(hw, port, XM_EXM(i), (u8 *) &zero);
998 xm_outhash(hw, port, XM_SRC_CHK, (u8 *) &zero);
baef58b1
SH		 999}
1000
1001
1002static void genesis_mac_init(struct skge_hw *hw, int port)
1003{
1004 struct skge_port *skge = netdev_priv(hw->dev[port]);
1005 int i;
1006 u32 r;
1007 u16 id1;
1008 u16 ctrl1, ctrl2, ctrl3, ctrl4, ctrl5;
1009
1010 /* magic workaround patterns for Broadcom */
1011 static const struct {
1012 u16 reg;
1013 u16 val;
1014 } A1hack[] = {
1015 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1016 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1017 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1018 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1019 }, C0hack[] = {
1020 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1021 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1022 };
1023
1024
1025 /* initialize Rx, Tx and Link LED */
6b0c1480
SH		 1026 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
1027 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 1028
6b0c1480
SH		 1029 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
1030 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1
SH		 1031
1032 /* Unreset the XMAC. */
6b0c1480 1033 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1034
1035 /*
1036 * Perform additional initialization for external PHYs,
1037 * namely for the 1000baseTX cards that use the XMAC's
1038 * GMII mode.
1039 */
1040 spin_lock_bh(&hw->phy_lock);
1041 if (hw->phy_type != SK_PHY_XMAC) {
1042 /* Take PHY out of reset. */
1043 r = skge_read32(hw, B2_GP_IO);
1044 if (port == 0)
1045 r |= GP_DIR_0|GP_IO_0;
1046 else
1047 r |= GP_DIR_2|GP_IO_2;
1048
1049 skge_write32(hw, B2_GP_IO, r);
1050 skge_read32(hw, B2_GP_IO);
1051
1052 /* Enable GMII mode on the XMAC. */
6b0c1480 1053 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
baef58b1 1054
6b0c1480 1055 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
baef58b1
SH		 1056
1057 /* Optimize MDIO transfer by suppressing preamble. */
6b0c1480
SH		 1058 xm_write16(hw, port, XM_MMU_CMD,
1059 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1060 | XM_MMU_NO_PRE);
1061
1062 if (id1 == PHY_BCOM_ID1_C0) {
1063 /*
1064 * Workaround BCOM Errata for the C0 type.
1065 * Write magic patterns to reserved registers.
1066 */
1067 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
6b0c1480 1068 xm_phy_write(hw, port,
baef58b1
SH		 1069 C0hack[i].reg, C0hack[i].val);
1070
1071 } else if (id1 == PHY_BCOM_ID1_A1) {
1072 /*
1073 * Workaround BCOM Errata for the A1 type.
1074 * Write magic patterns to reserved registers.
1075 */
1076 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
6b0c1480 1077 xm_phy_write(hw, port,
baef58b1
SH		 1078 A1hack[i].reg, A1hack[i].val);
1079 }
1080
1081 /*
1082 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1083 * Disable Power Management after reset.
1084 */
6b0c1480
SH		 1085 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1086 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r | PHY_B_AC_DIS_PM);
baef58b1
SH		 1087 }
1088
1089 /* Dummy read */
6b0c1480 1090 xm_read16(hw, port, XM_ISRC);
baef58b1 1091
6b0c1480
SH		 1092 r = xm_read32(hw, port, XM_MODE);
1093 xm_write32(hw, port, XM_MODE, r|XM_MD_CSA);
baef58b1
SH		 1094
1095 /* We don't need the FCS appended to the packet. */
6b0c1480
SH		 1096 r = xm_read16(hw, port, XM_RX_CMD);
1097 xm_write16(hw, port, XM_RX_CMD, r | XM_RX_STRIP_FCS);
baef58b1
SH		 1098
1099 /* We want short frames padded to 60 bytes. */
6b0c1480
SH		 1100 r = xm_read16(hw, port, XM_TX_CMD);
1101 xm_write16(hw, port, XM_TX_CMD, r | XM_TX_AUTO_PAD);
baef58b1
SH		 1102
1103 /*
1104 * Enable the reception of all error frames. This is is
1105 * a necessary evil due to the design of the XMAC. The
1106 * XMAC's receive FIFO is only 8K in size, however jumbo
1107 * frames can be up to 9000 bytes in length. When bad
1108 * frame filtering is enabled, the XMAC's RX FIFO operates
1109 * in 'store and forward' mode. For this to work, the
1110 * entire frame has to fit into the FIFO, but that means
1111 * that jumbo frames larger than 8192 bytes will be
1112 * truncated. Disabling all bad frame filtering causes
1113 * the RX FIFO to operate in streaming mode, in which
1114 * case the XMAC will start transfering frames out of the
1115 * RX FIFO as soon as the FIFO threshold is reached.
1116 */
6b0c1480
SH		 1117 r = xm_read32(hw, port, XM_MODE);
1118 xm_write32(hw, port, XM_MODE,
baef58b1
SH		 1119 XM_MD_RX_CRCE|XM_MD_RX_LONG|XM_MD_RX_RUNT|
1120 XM_MD_RX_ERR|XM_MD_RX_IRLE);
1121
6b0c1480
SH		 1122 xm_outaddr(hw, port, XM_SA, hw->dev[port]->dev_addr);
1123 xm_outaddr(hw, port, XM_EXM(0), hw->dev[port]->dev_addr);
baef58b1
SH		 1124
1125 /*
1126 * Bump up the transmit threshold. This helps hold off transmit
1127 * underruns when we're blasting traffic from both ports at once.
1128 */
6b0c1480 1129 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1130
1131 /* Configure MAC arbiter */
1132 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1133
1134 /* configure timeout values */
1135 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1136 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1137 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1138 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1139
1140 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1141 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1142 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1143 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1144
1145 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1146 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1147 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1148 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1149
1150 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1151 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1152 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1153 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1154
1155 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1156 /* Enable frame flushing if jumbo frames used */
6b0c1480 1157 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1158 } else {
1159 /* enable timeout timers if normal frames */
1160 skge_write16(hw, B3_PA_CTRL,
1161 port == 0 ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1162 }
1163
1164
6b0c1480 1165 r = xm_read16(hw, port, XM_RX_CMD);
baef58b1 1166 if (hw->dev[port]->mtu > ETH_DATA_LEN)
6b0c1480 1167 xm_write16(hw, port, XM_RX_CMD, r | XM_RX_BIG_PK_OK);
baef58b1 1168 else
6b0c1480 1169 xm_write16(hw, port, XM_RX_CMD, r & ~(XM_RX_BIG_PK_OK));
baef58b1
SH		 1170
1171 switch (hw->phy_type) {
1172 case SK_PHY_XMAC:
1173 if (skge->autoneg == AUTONEG_ENABLE) {
1174 ctrl1 = PHY_X_AN_FD | PHY_X_AN_HD;
1175
1176 switch (skge->flow_control) {
1177 case FLOW_MODE_NONE:
1178 ctrl1 |= PHY_X_P_NO_PAUSE;
1179 break;
1180 case FLOW_MODE_LOC_SEND:
1181 ctrl1 |= PHY_X_P_ASYM_MD;
1182 break;
1183 case FLOW_MODE_SYMMETRIC:
1184 ctrl1 |= PHY_X_P_SYM_MD;
1185 break;
1186 case FLOW_MODE_REM_SEND:
1187 ctrl1 |= PHY_X_P_BOTH_MD;
1188 break;
1189 }
1190
6b0c1480 1191 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl1);
baef58b1
SH		 1192 ctrl2 = PHY_CT_ANE | PHY_CT_RE_CFG;
1193 } else {
1194 ctrl2 = 0;
1195 if (skge->duplex == DUPLEX_FULL)
1196 ctrl2 |= PHY_CT_DUP_MD;
1197 }
1198
6b0c1480 1199 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl2);
baef58b1
SH		 1200 break;
1201
1202 case SK_PHY_BCOM:
1203 ctrl1 = PHY_CT_SP1000;
1204 ctrl2 = 0;
1205 ctrl3 = PHY_SEL_TYPE;
1206 ctrl4 = PHY_B_PEC_EN_LTR;
1207 ctrl5 = PHY_B_AC_TX_TST;
1208
1209 if (skge->autoneg == AUTONEG_ENABLE) {
1210 /*
1211 * Workaround BCOM Errata #1 for the C5 type.
1212 * 1000Base-T Link Acquisition Failure in Slave Mode
1213 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1214 */
1215 ctrl2 |= PHY_B_1000C_RD;
1216 if (skge->advertising & ADVERTISED_1000baseT_Half)
1217 ctrl2 |= PHY_B_1000C_AHD;
1218 if (skge->advertising & ADVERTISED_1000baseT_Full)
1219 ctrl2 |= PHY_B_1000C_AFD;
1220
1221 /* Set Flow-control capabilities */
1222 switch (skge->flow_control) {
1223 case FLOW_MODE_NONE:
1224 ctrl3 |= PHY_B_P_NO_PAUSE;
1225 break;
1226 case FLOW_MODE_LOC_SEND:
1227 ctrl3 |= PHY_B_P_ASYM_MD;
1228 break;
1229 case FLOW_MODE_SYMMETRIC:
1230 ctrl3 |= PHY_B_P_SYM_MD;
1231 break;
1232 case FLOW_MODE_REM_SEND:
1233 ctrl3 |= PHY_B_P_BOTH_MD;
1234 break;
1235 }
1236
1237 /* Restart Auto-negotiation */
1238 ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
1239 } else {
1240 if (skge->duplex == DUPLEX_FULL)
1241 ctrl1 |= PHY_CT_DUP_MD;
1242
1243 ctrl2 |= PHY_B_1000C_MSE; /* set it to Slave */
1244 }
1245
6b0c1480
SH		 1246 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, ctrl2);
1247 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, ctrl3);
baef58b1
SH		 1248
1249 if (skge->netdev->mtu > ETH_DATA_LEN) {
1250 ctrl4 |= PHY_B_PEC_HIGH_LA;
1251 ctrl5 |= PHY_B_AC_LONG_PACK;
1252
6b0c1480 1253 xm_phy_write(hw, port,PHY_BCOM_AUX_CTRL, ctrl5);
baef58b1
SH		 1254 }
1255
6b0c1480
SH		 1256 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ctrl4);
1257 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctrl1);
baef58b1
SH		 1258 break;
1259 }
1260 spin_unlock_bh(&hw->phy_lock);
1261
1262 /* Clear MIB counters */
6b0c1480 1263 xm_write16(hw, port, XM_STAT_CMD,
baef58b1
SH		 1264 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1265 /* Clear two times according to Errata #3 */
6b0c1480 1266 xm_write16(hw, port, XM_STAT_CMD,
baef58b1
SH		 1267 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1268
1269 /* Start polling for link status */
1270 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1271}
1272
1273static void genesis_stop(struct skge_port *skge)
1274{
1275 struct skge_hw *hw = skge->hw;
1276 int port = skge->port;
1277
1278 /* Clear Tx packet arbiter timeout IRQ */
1279 skge_write16(hw, B3_PA_CTRL,
1280 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1281
1282 /*
1283 * If the transfer stucks at the MAC the STOP command will not
1284 * terminate if we don't flush the XMAC's transmit FIFO !
1285 */
6b0c1480
SH		 1286 xm_write32(hw, port, XM_MODE,
1287 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1288
1289
1290 /* Reset the MAC */
6b0c1480 1291 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1292
1293 /* For external PHYs there must be special handling */
1294 if (hw->phy_type != SK_PHY_XMAC) {
1295 u32 reg = skge_read32(hw, B2_GP_IO);
1296
1297 if (port == 0) {
1298 reg |= GP_DIR_0;
1299 reg &= ~GP_IO_0;
1300 } else {
1301 reg |= GP_DIR_2;
1302 reg &= ~GP_IO_2;
1303 }
1304 skge_write32(hw, B2_GP_IO, reg);
1305 skge_read32(hw, B2_GP_IO);
1306 }
1307
6b0c1480
SH		 1308 xm_write16(hw, port, XM_MMU_CMD,
1309 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1310 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1311
6b0c1480 1312 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1313}
1314
1315
1316static void genesis_get_stats(struct skge_port *skge, u64 *data)
1317{
1318 struct skge_hw *hw = skge->hw;
1319 int port = skge->port;
1320 int i;
1321 unsigned long timeout = jiffies + HZ;
1322
6b0c1480 1323 xm_write16(hw, port,
baef58b1
SH		 1324 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1325
1326 /* wait for update to complete */
6b0c1480 1327 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1328 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1329 if (time_after(jiffies, timeout))
1330 break;
1331 udelay(10);
1332 }
1333
1334 /* special case for 64 bit octet counter */
6b0c1480
SH		 1335 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1336 | xm_read32(hw, port, XM_TXO_OK_LO);
1337 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1338 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1339
1340 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1341 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1342}
1343
1344static void genesis_mac_intr(struct skge_hw *hw, int port)
1345{
1346 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1347 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1348
1349 pr_debug("genesis_intr status %x\n", status);
1350 if (hw->phy_type == SK_PHY_XMAC) {
1351 /* LInk down, start polling for state change */
1352 if (status & XM_IS_INP_ASS) {
6b0c1480
SH		 1353 xm_write16(hw, port, XM_IMSK,
1354 xm_read16(hw, port, XM_IMSK) | XM_IS_INP_ASS);
baef58b1
SH		 1355 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1356 }
1357 else if (status & XM_IS_AND)
1358 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1359 }
1360
1361 if (status & XM_IS_TXF_UR) {
6b0c1480 1362 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1363 ++skge->net_stats.tx_fifo_errors;
1364 }
1365 if (status & XM_IS_RXF_OV) {
6b0c1480 1366 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1367 ++skge->net_stats.rx_fifo_errors;
1368 }
1369}
1370
6b0c1480 1371static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1372{
1373 int i;
1374
6b0c1480
SH		 1375 gma_write16(hw, port, GM_SMI_DATA, val);
1376 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1377 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1378 for (i = 0; i < PHY_RETRIES; i++) {
1379 udelay(1);
1380
6b0c1480 1381 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
baef58b1
SH		 1382 break;
1383 }
1384}
1385
6b0c1480 1386static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 1387{
1388 int i;
1389
6b0c1480 1390 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1391 GM_SMI_CT_PHY_AD(hw->phy_addr)
1392 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1393
1394 for (i = 0; i < PHY_RETRIES; i++) {
1395 udelay(1);
6b0c1480 1396 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
baef58b1
SH		 1397 goto ready;
1398 }
1399
1400 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1401 hw->dev[port]->name);
1402 return 0;
1403 ready:
6b0c1480 1404 return gma_read16(hw, port, GM_SMI_DATA);
baef58b1
SH		 1405}
1406
1407static void genesis_link_down(struct skge_port *skge)
1408{
1409 struct skge_hw *hw = skge->hw;
1410 int port = skge->port;
1411
1412 pr_debug("genesis_link_down\n");
1413
6b0c1480
SH		 1414 xm_write16(hw, port, XM_MMU_CMD,
1415 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1416 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1417
1418 /* dummy read to ensure writing */
6b0c1480 1419 (void) xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1420
1421 skge_link_down(skge);
1422}
1423
1424static void genesis_link_up(struct skge_port *skge)
1425{
1426 struct skge_hw *hw = skge->hw;
1427 int port = skge->port;
1428 u16 cmd;
1429 u32 mode, msk;
1430
1431 pr_debug("genesis_link_up\n");
6b0c1480 1432 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1433
1434 /*
1435 * enabling pause frame reception is required for 1000BT
1436 * because the XMAC is not reset if the link is going down
1437 */
1438 if (skge->flow_control == FLOW_MODE_NONE ||
1439 skge->flow_control == FLOW_MODE_LOC_SEND)
1440 cmd |= XM_MMU_IGN_PF;
1441 else
1442 /* Enable Pause Frame Reception */
1443 cmd &= ~XM_MMU_IGN_PF;
1444
6b0c1480 1445 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1446
6b0c1480 1447 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 1448 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1449 skge->flow_control == FLOW_MODE_LOC_SEND) {
1450 /*
1451 * Configure Pause Frame Generation
1452 * Use internal and external Pause Frame Generation.
1453 * Sending pause frames is edge triggered.
1454 * Send a Pause frame with the maximum pause time if
1455 * internal oder external FIFO full condition occurs.
1456 * Send a zero pause time frame to re-start transmission.
1457 */
1458 /* XM_PAUSE_DA = '010000C28001' (default) */
1459 /* XM_MAC_PTIME = 0xffff (maximum) */
1460 /* remember this value is defined in big endian (!) */
6b0c1480 1461 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1462
1463 mode |= XM_PAUSE_MODE;
6b0c1480 1464 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1465 } else {
1466 /*
1467 * disable pause frame generation is required for 1000BT
1468 * because the XMAC is not reset if the link is going down
1469 */
1470 /* Disable Pause Mode in Mode Register */
1471 mode &= ~XM_PAUSE_MODE;
1472
6b0c1480 1473 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1474 }
1475
6b0c1480 1476 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 1477
1478 msk = XM_DEF_MSK;
1479 if (hw->phy_type != SK_PHY_XMAC)
1480 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1481
6b0c1480
SH		 1482 xm_write16(hw, port, XM_IMSK, msk);
1483 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1484
1485 /* get MMU Command Reg. */
6b0c1480 1486 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1487 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1488 cmd |= XM_MMU_GMII_FD;
1489
1490 if (hw->phy_type == SK_PHY_BCOM) {
1491 /*
1492 * Workaround BCOM Errata (#10523) for all BCom Phys
1493 * Enable Power Management after link up
1494 */
6b0c1480
SH		 1495 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1496 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
baef58b1 1497 & ~PHY_B_AC_DIS_PM);
6b0c1480 1498 xm_phy_write(hw, port, PHY_BCOM_INT_MASK,
baef58b1
SH		 1499 PHY_B_DEF_MSK);
1500 }
1501
1502 /* enable Rx/Tx */
6b0c1480 1503 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1504 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1505 skge_link_up(skge);
1506}
1507
1508
1509static void genesis_bcom_intr(struct skge_port *skge)
1510{
1511 struct skge_hw *hw = skge->hw;
1512 int port = skge->port;
6b0c1480 1513 u16 stat = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
baef58b1
SH		 1514
1515 pr_debug("genesis_bcom intr stat=%x\n", stat);
1516
1517 /* Workaround BCom Errata:
1518 * enable and disable loopback mode if "NO HCD" occurs.
1519 */
1520 if (stat & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1521 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1522 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1523 ctrl | PHY_CT_LOOP);
6b0c1480 1524 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1525 ctrl & ~PHY_CT_LOOP);
1526 }
1527
6b0c1480 1528 stat = xm_phy_read(hw, port, PHY_BCOM_STAT);
baef58b1 1529 if (stat & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) {
6b0c1480 1530 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
baef58b1
SH		 1531 if ( !(aux & PHY_B_AS_LS) && netif_carrier_ok(skge->netdev))
1532 genesis_link_down(skge);
1533
1534 else if (stat & PHY_B_IS_LST_CHANGE) {
1535 if (aux & PHY_B_AS_AN_C) {
1536 switch (aux & PHY_B_AS_AN_RES_MSK) {
1537 case PHY_B_RES_1000FD:
1538 skge->duplex = DUPLEX_FULL;
1539 break;
1540 case PHY_B_RES_1000HD:
1541 skge->duplex = DUPLEX_HALF;
1542 break;
1543 }
1544
1545 switch (aux & PHY_B_AS_PAUSE_MSK) {
1546 case PHY_B_AS_PAUSE_MSK:
1547 skge->flow_control = FLOW_MODE_SYMMETRIC;
1548 break;
1549 case PHY_B_AS_PRR:
1550 skge->flow_control = FLOW_MODE_REM_SEND;
1551 break;
1552 case PHY_B_AS_PRT:
1553 skge->flow_control = FLOW_MODE_LOC_SEND;
1554 break;
1555 default:
1556 skge->flow_control = FLOW_MODE_NONE;
1557 }
1558 skge->speed = SPEED_1000;
1559 }
1560 genesis_link_up(skge);
1561 }
1562 else
1563 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1564 }
1565}
1566
1567/* Perodic poll of phy status to check for link transistion */
1568static void skge_link_timer(unsigned long __arg)
1569{
1570 struct skge_port *skge = (struct skge_port *) __arg;
1571 struct skge_hw *hw = skge->hw;
1572 int port = skge->port;
1573
1574 if (hw->chip_id != CHIP_ID_GENESIS || !netif_running(skge->netdev))
1575 return;
1576
1577 spin_lock_bh(&hw->phy_lock);
1578 if (hw->phy_type == SK_PHY_BCOM)
1579 genesis_bcom_intr(skge);
1580 else {
1581 int i;
1582 for (i = 0; i < 3; i++)
6b0c1480 1583 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
baef58b1
SH		 1584 break;
1585
1586 if (i == 3)
1587 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1588 else
1589 genesis_link_up(skge);
1590 }
1591 spin_unlock_bh(&hw->phy_lock);
1592}
1593
1594/* Marvell Phy Initailization */
1595static void yukon_init(struct skge_hw *hw, int port)
1596{
1597 struct skge_port *skge = netdev_priv(hw->dev[port]);
1598 u16 ctrl, ct1000, adv;
1599 u16 ledctrl, ledover;
1600
1601 pr_debug("yukon_init\n");
1602 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1603 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1604
1605 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1606 PHY_M_EC_MAC_S_MSK);
1607 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1608
1609 /* on PHY 88E1111 there is a change for downshift control */
1610 if (hw->chip_id == CHIP_ID_YUKON_EC)
1611 ectrl |= PHY_M_EC_M_DSC_2(0) | PHY_M_EC_DOWN_S_ENA;
1612 else
1613 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1614
6b0c1480 1615 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1616 }
1617
6b0c1480 1618 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1619 if (skge->autoneg == AUTONEG_DISABLE)
1620 ctrl &= ~PHY_CT_ANE;
1621
1622 ctrl |= PHY_CT_RESET;
6b0c1480 1623 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1624
1625 ctrl = 0;
1626 ct1000 = 0;
1627 adv = PHY_SEL_TYPE;
1628
1629 if (skge->autoneg == AUTONEG_ENABLE) {
1630 if (iscopper(hw)) {
1631 if (skge->advertising & ADVERTISED_1000baseT_Full)
1632 ct1000 |= PHY_M_1000C_AFD;
1633 if (skge->advertising & ADVERTISED_1000baseT_Half)
1634 ct1000 |= PHY_M_1000C_AHD;
1635 if (skge->advertising & ADVERTISED_100baseT_Full)
1636 adv |= PHY_M_AN_100_FD;
1637 if (skge->advertising & ADVERTISED_100baseT_Half)
1638 adv |= PHY_M_AN_100_HD;
1639 if (skge->advertising & ADVERTISED_10baseT_Full)
1640 adv |= PHY_M_AN_10_FD;
1641 if (skge->advertising & ADVERTISED_10baseT_Half)
1642 adv |= PHY_M_AN_10_HD;
1643
1644 /* Set Flow-control capabilities */
1645 switch (skge->flow_control) {
1646 case FLOW_MODE_NONE:
1647 adv |= PHY_B_P_NO_PAUSE;
1648 break;
1649 case FLOW_MODE_LOC_SEND:
1650 adv |= PHY_B_P_ASYM_MD;
1651 break;
1652 case FLOW_MODE_SYMMETRIC:
1653 adv |= PHY_B_P_SYM_MD;
1654 break;
1655 case FLOW_MODE_REM_SEND:
1656 adv |= PHY_B_P_BOTH_MD;
1657 break;
1658 }
1659 } else { /* special defines for FIBER (88E1011S only) */
1660 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1661
1662 /* Set Flow-control capabilities */
1663 switch (skge->flow_control) {
1664 case FLOW_MODE_NONE:
1665 adv |= PHY_M_P_NO_PAUSE_X;
1666 break;
1667 case FLOW_MODE_LOC_SEND:
1668 adv |= PHY_M_P_ASYM_MD_X;
1669 break;
1670 case FLOW_MODE_SYMMETRIC:
1671 adv |= PHY_M_P_SYM_MD_X;
1672 break;
1673 case FLOW_MODE_REM_SEND:
1674 adv |= PHY_M_P_BOTH_MD_X;
1675 break;
1676 }
1677 }
1678 /* Restart Auto-negotiation */
1679 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1680 } else {
1681 /* forced speed/duplex settings */
1682 ct1000 = PHY_M_1000C_MSE;
1683
1684 if (skge->duplex == DUPLEX_FULL)
1685 ctrl |= PHY_CT_DUP_MD;
1686
1687 switch (skge->speed) {
1688 case SPEED_1000:
1689 ctrl |= PHY_CT_SP1000;
1690 break;
1691 case SPEED_100:
1692 ctrl |= PHY_CT_SP100;
1693 break;
1694 }
1695
1696 ctrl |= PHY_CT_RESET;
1697 }
1698
1699 if (hw->chip_id != CHIP_ID_YUKON_FE)
6b0c1480 1700 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1701
6b0c1480
SH		 1702 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1703 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1704
1705 /* Setup Phy LED's */
1706 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
1707 ledover = 0;
1708
1709 if (hw->chip_id == CHIP_ID_YUKON_FE) {
1710 /* on 88E3082 these bits are at 11..9 (shifted left) */
1711 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
1712
6b0c1480
SH		 1713 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR,
1714 ((gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR)
baef58b1
SH		 1715
1716 & ~PHY_M_FELP_LED1_MSK)
1717 | PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL)));
1718 } else {
1719 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
1720 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
1721
1722 /* turn off the Rx LED (LED_RX) */
1723 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
1724 }
1725
1726 /* disable blink mode (LED_DUPLEX) on collisions */
1727 ctrl |= PHY_M_LEDC_DP_CTRL;
6b0c1480 1728 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
baef58b1
SH		 1729
1730 if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) {
1731 /* turn on 100 Mbps LED (LED_LINK100) */
1732 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
1733 }
1734
1735 if (ledover)
6b0c1480 1736 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
baef58b1
SH		 1737
1738 /* Enable phy interrupt on autonegotiation complete (or link up) */
1739 if (skge->autoneg == AUTONEG_ENABLE)
6b0c1480 1740 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
baef58b1 1741 else
6b0c1480 1742 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
baef58b1
SH		 1743}
1744
1745static void yukon_reset(struct skge_hw *hw, int port)
1746{
6b0c1480
SH		 1747 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1748 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1749 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1750 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1751 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1752
6b0c1480
SH		 1753 gma_write16(hw, port, GM_RX_CTRL,
1754 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1755 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1756}
1757
1758static void yukon_mac_init(struct skge_hw *hw, int port)
1759{
1760 struct skge_port *skge = netdev_priv(hw->dev[port]);
1761 int i;
1762 u32 reg;
1763 const u8 *addr = hw->dev[port]->dev_addr;
1764
1765 /* WA code for COMA mode -- set PHY reset */
1766 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1767 hw->chip_rev == CHIP_REV_YU_LITE_A3)
baef58b1
SH		 1768 skge_write32(hw, B2_GP_IO,
1769 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1770
1771 /* hard reset */
6b0c1480
SH		 1772 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1773 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1774
1775 /* WA code for COMA mode -- clear PHY reset */
1776 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1777 hw->chip_rev == CHIP_REV_YU_LITE_A3)
baef58b1
SH		 1778 skge_write32(hw, B2_GP_IO,
1779 (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
1780 & ~GP_IO_9);
1781
1782 /* Set hardware config mode */
1783 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1784 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1785 reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1786
1787 /* Clear GMC reset */
6b0c1480
SH		 1788 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1789 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1790 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
baef58b1
SH		 1791 if (skge->autoneg == AUTONEG_DISABLE) {
1792 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1793 gma_write16(hw, port, GM_GP_CTRL,
1794 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1795
1796 switch (skge->speed) {
1797 case SPEED_1000:
1798 reg |= GM_GPCR_SPEED_1000;
1799 /* fallthru */
1800 case SPEED_100:
1801 reg |= GM_GPCR_SPEED_100;
1802 }
1803
1804 if (skge->duplex == DUPLEX_FULL)
1805 reg |= GM_GPCR_DUP_FULL;
1806 } else
1807 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1808 switch (skge->flow_control) {
1809 case FLOW_MODE_NONE:
6b0c1480 1810 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1811 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1812 break;
1813 case FLOW_MODE_LOC_SEND:
1814 /* disable Rx flow-control */
1815 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1816 }
1817
6b0c1480 1818 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1
SH		 1819 skge_read16(hw, GMAC_IRQ_SRC);
1820
1821 spin_lock_bh(&hw->phy_lock);
1822 yukon_init(hw, port);
1823 spin_unlock_bh(&hw->phy_lock);
1824
1825 /* MIB clear */
6b0c1480
SH		 1826 reg = gma_read16(hw, port, GM_PHY_ADDR);
1827 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1828
1829 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1830 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1831 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1832
1833 /* transmit control */
6b0c1480 1834 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1835
1836 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1837 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1838 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1839
1840 /* transmit flow control */
6b0c1480 1841 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1842
1843 /* transmit parameter */
6b0c1480 1844 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1845 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1846 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1847 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1848
1849 /* serial mode register */
1850 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1851 if (hw->dev[port]->mtu > 1500)
1852 reg |= GM_SMOD_JUMBO_ENA;
1853
6b0c1480 1854 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 1855
1856 /* physical address: used for pause frames */
6b0c1480 1857 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 1858 /* virtual address for data */
6b0c1480 1859 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 1860
1861 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 1862 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1863 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1864 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 1865
1866 /* Initialize Mac Fifo */
1867
1868 /* Configure Rx MAC FIFO */
6b0c1480 1869 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1
SH		 1870 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1871 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1872 hw->chip_rev == CHIP_REV_YU_LITE_A3)
baef58b1 1873 reg &= ~GMF_RX_F_FL_ON;
6b0c1480
SH		 1874 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1875 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1876 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
baef58b1
SH		 1877
1878 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1879 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1880 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 1881}
1882
1883static void yukon_stop(struct skge_port *skge)
1884{
1885 struct skge_hw *hw = skge->hw;
1886 int port = skge->port;
1887
1888 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1889 hw->chip_rev == CHIP_REV_YU_LITE_A3) {
baef58b1
SH		 1890 skge_write32(hw, B2_GP_IO,
1891 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1892 }
1893
6b0c1480
SH		 1894 gma_write16(hw, port, GM_GP_CTRL,
1895 gma_read16(hw, port, GM_GP_CTRL)
baef58b1 1896 & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA));
6b0c1480 1897 gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1898
1899 /* set GPHY Control reset */
6b0c1480
SH		 1900 gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
1901 gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
baef58b1
SH		 1902}
1903
1904static void yukon_get_stats(struct skge_port *skge, u64 *data)
1905{
1906 struct skge_hw *hw = skge->hw;
1907 int port = skge->port;
1908 int i;
1909
6b0c1480
SH		 1910 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1911 | gma_read32(hw, port, GM_TXO_OK_LO);
1912 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1913 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 1914
1915 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1916 data[i] = gma_read32(hw, port,
baef58b1
SH		 1917 skge_stats[i].gma_offset);
1918}
1919
1920static void yukon_mac_intr(struct skge_hw *hw, int port)
1921{
1922 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1923 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1
SH		 1924
1925 pr_debug("yukon_intr status %x\n", status);
1926 if (status & GM_IS_RX_FF_OR) {
1927 ++skge->net_stats.rx_fifo_errors;
6b0c1480 1928 gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
baef58b1
SH		 1929 }
1930 if (status & GM_IS_TX_FF_UR) {
1931 ++skge->net_stats.tx_fifo_errors;
6b0c1480 1932 gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
baef58b1
SH		 1933 }
1934
1935}
1936
1937static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1938{
1939 if (hw->chip_id == CHIP_ID_YUKON_FE)
1940 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1941
95566065 1942 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 1943 case PHY_M_PS_SPEED_1000:
1944 return SPEED_1000;
1945 case PHY_M_PS_SPEED_100:
1946 return SPEED_100;
1947 default:
1948 return SPEED_10;
1949 }
1950}
1951
1952static void yukon_link_up(struct skge_port *skge)
1953{
1954 struct skge_hw *hw = skge->hw;
1955 int port = skge->port;
1956 u16 reg;
1957
1958 pr_debug("yukon_link_up\n");
1959
1960 /* Enable Transmit FIFO Underrun */
1961 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
1962
6b0c1480 1963 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1964 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1965 reg |= GM_GPCR_DUP_FULL;
1966
1967 /* enable Rx/Tx */
1968 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 1969 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 1970
6b0c1480 1971 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
baef58b1
SH		 1972 skge_link_up(skge);
1973}
1974
1975static void yukon_link_down(struct skge_port *skge)
1976{
1977 struct skge_hw *hw = skge->hw;
1978 int port = skge->port;
1979
1980 pr_debug("yukon_link_down\n");
6b0c1480
SH		 1981 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1982 gm_phy_write(hw, port, GM_GP_CTRL,
1983 gm_phy_read(hw, port, GM_GP_CTRL)
baef58b1
SH		 1984 & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
1985
1986 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1987 skge->flow_control == FLOW_MODE_REM_SEND) {
1988 /* restore Asymmetric Pause bit */
6b0c1480
SH		 1989 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1990 gm_phy_read(hw, port,
baef58b1
SH		 1991 PHY_MARV_AUNE_ADV)
1992 | PHY_M_AN_ASP);
1993
1994 }
1995
1996 yukon_reset(hw, port);
1997 skge_link_down(skge);
1998
1999 yukon_init(hw, port);
2000}
2001
2002static void yukon_phy_intr(struct skge_port *skge)
2003{
2004 struct skge_hw *hw = skge->hw;
2005 int port = skge->port;
2006 const char *reason = NULL;
2007 u16 istatus, phystat;
2008
6b0c1480
SH		 2009 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2010 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
baef58b1
SH		 2011 pr_debug("yukon phy intr istat=%x phy_stat=%x\n", istatus, phystat);
2012
2013 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2014 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2015 & PHY_M_AN_RF) {
2016 reason = "remote fault";
2017 goto failed;
2018 }
2019
2020 if (!(hw->chip_id == CHIP_ID_YUKON_FE || hw->chip_id == CHIP_ID_YUKON_EC)
6b0c1480 2021 && (gm_phy_read(hw, port, PHY_MARV_1000T_STAT)
baef58b1
SH		 2022 & PHY_B_1000S_MSF)) {
2023 reason = "master/slave fault";
2024 goto failed;
2025 }
2026
2027 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2028 reason = "speed/duplex";
2029 goto failed;
2030 }
2031
2032 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2033 ? DUPLEX_FULL : DUPLEX_HALF;
2034 skge->speed = yukon_speed(hw, phystat);
2035
2036 /* Tx & Rx Pause Enabled bits are at 9..8 */
2037 if (hw->chip_id == CHIP_ID_YUKON_XL)
2038 phystat >>= 6;
2039
2040 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2041 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2042 case PHY_M_PS_PAUSE_MSK:
2043 skge->flow_control = FLOW_MODE_SYMMETRIC;
2044 break;
2045 case PHY_M_PS_RX_P_EN:
2046 skge->flow_control = FLOW_MODE_REM_SEND;
2047 break;
2048 case PHY_M_PS_TX_P_EN:
2049 skge->flow_control = FLOW_MODE_LOC_SEND;
2050 break;
2051 default:
2052 skge->flow_control = FLOW_MODE_NONE;
2053 }
2054
2055 if (skge->flow_control == FLOW_MODE_NONE ||
2056 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2057 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2058 else
6b0c1480 2059 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2060 yukon_link_up(skge);
2061 return;
2062 }
2063
2064 if (istatus & PHY_M_IS_LSP_CHANGE)
2065 skge->speed = yukon_speed(hw, phystat);
2066
2067 if (istatus & PHY_M_IS_DUP_CHANGE)
2068 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2069 if (istatus & PHY_M_IS_LST_CHANGE) {
2070 if (phystat & PHY_M_PS_LINK_UP)
2071 yukon_link_up(skge);
2072 else
2073 yukon_link_down(skge);
2074 }
2075 return;
2076 failed:
2077 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2078 skge->netdev->name, reason);
2079
2080 /* XXX restart autonegotiation? */
2081}
2082
2083static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2084{
2085 u32 end;
2086
2087 start /= 8;
2088 len /= 8;
2089 end = start + len - 1;
2090
2091 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2092 skge_write32(hw, RB_ADDR(q, RB_START), start);
2093 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2094 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2095 skge_write32(hw, RB_ADDR(q, RB_END), end);
2096
2097 if (q == Q_R1 || q == Q_R2) {
2098 /* Set thresholds on receive queue's */
2099 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2100 start + (2*len)/3);
2101 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2102 start + (len/3));
2103 } else {
2104 /* Enable store & forward on Tx queue's because
2105 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2106 */
2107 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2108 }
2109
2110 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2111}
2112
2113/* Setup Bus Memory Interface */
2114static void skge_qset(struct skge_port *skge, u16 q,
2115 const struct skge_element *e)
2116{
2117 struct skge_hw *hw = skge->hw;
2118 u32 watermark = 0x600;
2119 u64 base = skge->dma + (e->desc - skge->mem);
2120
2121 /* optimization to reduce window on 32bit/33mhz */
2122 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2123 watermark /= 2;
2124
2125 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2126 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2127 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2128 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2129}
2130
2131static int skge_up(struct net_device *dev)
2132{
2133 struct skge_port *skge = netdev_priv(dev);
2134 struct skge_hw *hw = skge->hw;
2135 int port = skge->port;
2136 u32 chunk, ram_addr;
2137 size_t rx_size, tx_size;
2138 int err;
2139
2140 if (netif_msg_ifup(skge))
2141 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2142
2143 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2144 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2145 skge->mem_size = tx_size + rx_size;
2146 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2147 if (!skge->mem)
2148 return -ENOMEM;
2149
2150 memset(skge->mem, 0, skge->mem_size);
2151
2152 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2153 goto free_pci_mem;
2154
2155 if (skge_rx_fill(skge))
2156 goto free_rx_ring;
2157
2158 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2159 skge->dma + rx_size)))
2160 goto free_rx_ring;
2161
2162 skge->tx_avail = skge->tx_ring.count - 1;
2163
2164 /* Initialze MAC */
2165 if (hw->chip_id == CHIP_ID_GENESIS)
2166 genesis_mac_init(hw, port);
2167 else
2168 yukon_mac_init(hw, port);
2169
2170 /* Configure RAMbuffers */
981d0377 2171 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2172 ram_addr = hw->ram_offset + 2 * chunk * port;
2173
2174 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2175 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2176
2177 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2178 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2179 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2180
2181 /* Start receiver BMU */
2182 wmb();
2183 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2184
2185 pr_debug("skge_up completed\n");
2186 return 0;
2187
2188 free_rx_ring:
2189 skge_rx_clean(skge);
2190 kfree(skge->rx_ring.start);
2191 free_pci_mem:
2192 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2193
2194 return err;
2195}
2196
2197static int skge_down(struct net_device *dev)
2198{
2199 struct skge_port *skge = netdev_priv(dev);
2200 struct skge_hw *hw = skge->hw;
2201 int port = skge->port;
2202
2203 if (netif_msg_ifdown(skge))
2204 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2205
2206 netif_stop_queue(dev);
2207
2208 del_timer_sync(&skge->led_blink);
2209 del_timer_sync(&skge->link_check);
2210
2211 /* Stop transmitter */
2212 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2213 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2214 RB_RST_SET|RB_DIS_OP_MD);
2215
2216 if (hw->chip_id == CHIP_ID_GENESIS)
2217 genesis_stop(skge);
2218 else
2219 yukon_stop(skge);
2220
2221 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2222 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2223 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2224
2225 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2226 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2227 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2228
2229 /* Reset PCI FIFO */
2230 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2231 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2232
2233 /* Reset the RAM Buffer async Tx queue */
2234 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2235 /* stop receiver */
2236 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2237 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2238 RB_RST_SET|RB_DIS_OP_MD);
2239 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2240
2241 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2242 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2243 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2244 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_STOP);
2245 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_STOP);
baef58b1 2246 } else {
6b0c1480
SH		 2247 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2248 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2249 }
2250
2251 /* turn off led's */
2252 skge_write16(hw, B0_LED, LED_STAT_OFF);
2253
2254 skge_tx_clean(skge);
2255 skge_rx_clean(skge);
2256
2257 kfree(skge->rx_ring.start);
2258 kfree(skge->tx_ring.start);
2259 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2260 return 0;
2261}
2262
2263static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2264{
2265 struct skge_port *skge = netdev_priv(dev);
2266 struct skge_hw *hw = skge->hw;
2267 struct skge_ring *ring = &skge->tx_ring;
2268 struct skge_element *e;
2269 struct skge_tx_desc *td;
2270 int i;
2271 u32 control, len;
2272 u64 map;
2273 unsigned long flags;
2274
2275 skb = skb_padto(skb, ETH_ZLEN);
2276 if (!skb)
2277 return NETDEV_TX_OK;
2278
2279 local_irq_save(flags);
2280 if (!spin_trylock(&skge->tx_lock)) {
95566065
SH		 2281 /* Collision - tell upper layer to requeue */
2282 local_irq_restore(flags);
2283 return NETDEV_TX_LOCKED;
2284 }
baef58b1
SH		 2285
2286 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2287 netif_stop_queue(dev);
2288 spin_unlock_irqrestore(&skge->tx_lock, flags);
2289
2290 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2291 dev->name);
2292 return NETDEV_TX_BUSY;
2293 }
2294
2295 e = ring->to_use;
2296 td = e->desc;
2297 e->skb = skb;
2298 len = skb_headlen(skb);
2299 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2300 pci_unmap_addr_set(e, mapaddr, map);
2301 pci_unmap_len_set(e, maplen, len);
2302
2303 td->dma_lo = map;
2304 td->dma_hi = map >> 32;
2305
2306 if (skb->ip_summed == CHECKSUM_HW) {
2307 const struct iphdr *ip
2308 = (const struct iphdr *) (skb->data + ETH_HLEN);
2309 int offset = skb->h.raw - skb->data;
2310
2311 /* This seems backwards, but it is what the sk98lin
2312 * does. Looks like hardware is wrong?
2313 */
2314 if (ip->protocol == IPPROTO_UDP
981d0377 2315 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2316 control = BMU_TCP_CHECK;
2317 else
2318 control = BMU_UDP_CHECK;
2319
2320 td->csum_offs = 0;
2321 td->csum_start = offset;
2322 td->csum_write = offset + skb->csum;
2323 } else
2324 control = BMU_CHECK;
2325
2326 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2327 control |= BMU_EOF| BMU_IRQ_EOF;
2328 else {
2329 struct skge_tx_desc *tf = td;
2330
2331 control |= BMU_STFWD;
2332 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2333 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2334
2335 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2336 frag->size, PCI_DMA_TODEVICE);
2337
2338 e = e->next;
2339 e->skb = NULL;
2340 tf = e->desc;
2341 tf->dma_lo = map;
2342 tf->dma_hi = (u64) map >> 32;
2343 pci_unmap_addr_set(e, mapaddr, map);
2344 pci_unmap_len_set(e, maplen, frag->size);
2345
2346 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2347 }
2348 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2349 }
2350 /* Make sure all the descriptors written */
2351 wmb();
2352 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2353 wmb();
2354
2355 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2356
2357 if (netif_msg_tx_queued(skge))
0b2d7fea 2358 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
baef58b1
SH		 2359 dev->name, e - ring->start, skb->len);
2360
2361 ring->to_use = e->next;
2362 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2363 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2364 pr_debug("%s: transmit queue full\n", dev->name);
2365 netif_stop_queue(dev);
2366 }
2367
2368 dev->trans_start = jiffies;
2369 spin_unlock_irqrestore(&skge->tx_lock, flags);
2370
2371 return NETDEV_TX_OK;
2372}
2373
2374static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2375{
2376 if (e->skb) {
2377 pci_unmap_single(hw->pdev,
2378 pci_unmap_addr(e, mapaddr),
2379 pci_unmap_len(e, maplen),
2380 PCI_DMA_TODEVICE);
2381 dev_kfree_skb_any(e->skb);
2382 e->skb = NULL;
2383 } else {
2384 pci_unmap_page(hw->pdev,
2385 pci_unmap_addr(e, mapaddr),
2386 pci_unmap_len(e, maplen),
2387 PCI_DMA_TODEVICE);
2388 }
2389}
2390
2391static void skge_tx_clean(struct skge_port *skge)
2392{
2393 struct skge_ring *ring = &skge->tx_ring;
2394 struct skge_element *e;
2395 unsigned long flags;
2396
2397 spin_lock_irqsave(&skge->tx_lock, flags);
2398 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2399 ++skge->tx_avail;
2400 skge_tx_free(skge->hw, e);
2401 }
2402 ring->to_clean = e;
2403 spin_unlock_irqrestore(&skge->tx_lock, flags);
2404}
2405
2406static void skge_tx_timeout(struct net_device *dev)
2407{
2408 struct skge_port *skge = netdev_priv(dev);
2409
2410 if (netif_msg_timer(skge))
2411 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2412
2413 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2414 skge_tx_clean(skge);
2415}
2416
2417static int skge_change_mtu(struct net_device *dev, int new_mtu)
2418{
2419 int err = 0;
2420
95566065 2421 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2422 return -EINVAL;
2423
2424 dev->mtu = new_mtu;
2425
2426 if (netif_running(dev)) {
2427 skge_down(dev);
2428 skge_up(dev);
2429 }
2430
2431 return err;
2432}
2433
2434static void genesis_set_multicast(struct net_device *dev)
2435{
2436 struct skge_port *skge = netdev_priv(dev);
2437 struct skge_hw *hw = skge->hw;
2438 int port = skge->port;
2439 int i, count = dev->mc_count;
2440 struct dev_mc_list *list = dev->mc_list;
2441 u32 mode;
2442 u8 filter[8];
2443
6b0c1480 2444 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2445 mode |= XM_MD_ENA_HASH;
2446 if (dev->flags & IFF_PROMISC)
2447 mode |= XM_MD_ENA_PROM;
2448 else
2449 mode &= ~XM_MD_ENA_PROM;
2450
2451 if (dev->flags & IFF_ALLMULTI)
2452 memset(filter, 0xff, sizeof(filter));
2453 else {
2454 memset(filter, 0, sizeof(filter));
95566065 2455 for (i = 0; list && i < count; i++, list = list->next) {
baef58b1
SH		 2456 u32 crc = crc32_le(~0, list->dmi_addr, ETH_ALEN);
2457 u8 bit = 63 - (crc & 63);
2458
2459 filter[bit/8] |= 1 << (bit%8);
2460 }
2461 }
2462
6b0c1480 2463 xm_outhash(hw, port, XM_HSM, filter);
baef58b1 2464
6b0c1480 2465 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 2466}
2467
2468static void yukon_set_multicast(struct net_device *dev)
2469{
2470 struct skge_port *skge = netdev_priv(dev);
2471 struct skge_hw *hw = skge->hw;
2472 int port = skge->port;
2473 struct dev_mc_list *list = dev->mc_list;
2474 u16 reg;
2475 u8 filter[8];
2476
2477 memset(filter, 0, sizeof(filter));
2478
6b0c1480 2479 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2480 reg |= GM_RXCR_UCF_ENA;
2481
2482 if (dev->flags & IFF_PROMISC) /* promiscious */
2483 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2484 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2485 memset(filter, 0xff, sizeof(filter));
2486 else if (dev->mc_count == 0) /* no multicast */
2487 reg &= ~GM_RXCR_MCF_ENA;
2488 else {
2489 int i;
2490 reg |= GM_RXCR_MCF_ENA;
2491
95566065 2492 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2493 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2494 filter[bit/8] |= 1 << (bit%8);
2495 }
2496 }
2497
2498
6b0c1480 2499 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2500 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2501 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2502 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2503 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2504 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2505 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2506 (u16)filter[6] | ((u16)filter[7] << 8));
2507
6b0c1480 2508 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2509}
2510
2511static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2512{
2513 if (hw->chip_id == CHIP_ID_GENESIS)
2514 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2515 else
2516 return (status & GMR_FS_ANY_ERR) ||
2517 (status & GMR_FS_RX_OK) == 0;
2518}
2519
2520static void skge_rx_error(struct skge_port *skge, int slot,
2521 u32 control, u32 status)
2522{
2523 if (netif_msg_rx_err(skge))
2524 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2525 skge->netdev->name, slot, control, status);
2526
2527 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2528 || (control & BMU_BBC) > skge->netdev->mtu + VLAN_ETH_HLEN)
2529 skge->net_stats.rx_length_errors++;
2530 else {
2531 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2532 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2533 skge->net_stats.rx_length_errors++;
2534 if (status & XMR_FS_FRA_ERR)
2535 skge->net_stats.rx_frame_errors++;
2536 if (status & XMR_FS_FCS_ERR)
2537 skge->net_stats.rx_crc_errors++;
2538 } else {
2539 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2540 skge->net_stats.rx_length_errors++;
2541 if (status & GMR_FS_FRAGMENT)
2542 skge->net_stats.rx_frame_errors++;
2543 if (status & GMR_FS_CRC_ERR)
2544 skge->net_stats.rx_crc_errors++;
2545 }
2546 }
2547}
2548
2549static int skge_poll(struct net_device *dev, int *budget)
2550{
2551 struct skge_port *skge = netdev_priv(dev);
2552 struct skge_hw *hw = skge->hw;
2553 struct skge_ring *ring = &skge->rx_ring;
2554 struct skge_element *e;
2555 unsigned int to_do = min(dev->quota, *budget);
2556 unsigned int work_done = 0;
2557 int done;
2558 static const u32 irqmask[] = { IS_PORT_1, IS_PORT_2 };
2559
2560 for (e = ring->to_clean; e != ring->to_use && work_done < to_do;
2561 e = e->next) {
2562 struct skge_rx_desc *rd = e->desc;
2563 struct sk_buff *skb = e->skb;
2564 u32 control, len, status;
2565
2566 rmb();
2567 control = rd->control;
2568 if (control & BMU_OWN)
2569 break;
2570
2571 len = control & BMU_BBC;
2572 e->skb = NULL;
2573
2574 pci_unmap_single(hw->pdev,
2575 pci_unmap_addr(e, mapaddr),
2576 pci_unmap_len(e, maplen),
2577 PCI_DMA_FROMDEVICE);
2578
2579 status = rd->status;
2580 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2581 || len > dev->mtu + VLAN_ETH_HLEN
2582 || bad_phy_status(hw, status)) {
2583 skge_rx_error(skge, e - ring->start, control, status);
2584 dev_kfree_skb(skb);
2585 continue;
2586 }
2587
2588 if (netif_msg_rx_status(skge))
0b2d7fea 2589 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
baef58b1
SH		 2590 dev->name, e - ring->start, rd->status, len);
2591
2592 skb_put(skb, len);
2593 skb->protocol = eth_type_trans(skb, dev);
2594
2595 if (skge->rx_csum) {
2596 skb->csum = le16_to_cpu(rd->csum2);
2597 skb->ip_summed = CHECKSUM_HW;
2598 }
2599
2600 dev->last_rx = jiffies;
2601 netif_receive_skb(skb);
2602
2603 ++work_done;
2604 }
2605 ring->to_clean = e;
2606
2607 *budget -= work_done;
2608 dev->quota -= work_done;
2609 done = work_done < to_do;
2610
2611 if (skge_rx_fill(skge))
2612 done = 0;
2613
2614 /* restart receiver */
2615 wmb();
2616 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2617 CSR_START | CSR_IRQ_CL_F);
2618
2619 if (done) {
2620 local_irq_disable();
2621 hw->intr_mask |= irqmask[skge->port];
2622 /* Order is important since data can get interrupted */
2623 skge_write32(hw, B0_IMSK, hw->intr_mask);
2624 __netif_rx_complete(dev);
2625 local_irq_enable();
2626 }
2627
2628 return !done;
2629}
2630
2631static inline void skge_tx_intr(struct net_device *dev)
2632{
2633 struct skge_port *skge = netdev_priv(dev);
2634 struct skge_hw *hw = skge->hw;
2635 struct skge_ring *ring = &skge->tx_ring;
2636 struct skge_element *e;
2637
2638 spin_lock(&skge->tx_lock);
95566065 2639 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
baef58b1
SH		 2640 struct skge_tx_desc *td = e->desc;
2641 u32 control;
2642
2643 rmb();
2644 control = td->control;
2645 if (control & BMU_OWN)
2646 break;
2647
2648 if (unlikely(netif_msg_tx_done(skge)))
0b2d7fea 2649 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
baef58b1
SH		 2650 dev->name, e - ring->start, td->status);
2651
2652 skge_tx_free(hw, e);
2653 e->skb = NULL;
2654 ++skge->tx_avail;
2655 }
2656 ring->to_clean = e;
2657 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2658
2659 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2660 netif_wake_queue(dev);
2661
2662 spin_unlock(&skge->tx_lock);
2663}
2664
2665static void skge_mac_parity(struct skge_hw *hw, int port)
2666{
2667 printk(KERN_ERR PFX "%s: mac data parity error\n",
2668 hw->dev[port] ? hw->dev[port]->name
2669 : (port == 0 ? "(port A)": "(port B"));
2670
2671 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2672 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2673 MFF_CLR_PERR);
2674 else
2675 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2676 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2677 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2678 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2679}
2680
2681static void skge_pci_clear(struct skge_hw *hw)
2682{
2683 u16 status;
2684
467b3417 2685 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
baef58b1 2686 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
467b3417
SH		 2687 pci_write_config_word(hw->pdev, PCI_STATUS,
2688 status | PCI_STATUS_ERROR_BITS);
baef58b1
SH		 2689 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2690}
2691
2692static void skge_mac_intr(struct skge_hw *hw, int port)
2693{
95566065 2694 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2695 genesis_mac_intr(hw, port);
2696 else
2697 yukon_mac_intr(hw, port);
2698}
2699
2700/* Handle device specific framing and timeout interrupts */
2701static void skge_error_irq(struct skge_hw *hw)
2702{
2703 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2704
2705 if (hw->chip_id == CHIP_ID_GENESIS) {
2706 /* clear xmac errors */
2707 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
6b0c1480 2708 skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
baef58b1 2709 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
6b0c1480 2710 skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
baef58b1
SH		 2711 } else {
2712 /* Timestamp (unused) overflow */
2713 if (hwstatus & IS_IRQ_TIST_OV)
2714 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2715
2716 if (hwstatus & IS_IRQ_SENSOR) {
2717 /* no sensors on 32-bit Yukon */
2718 if (!(skge_read16(hw, B0_CTST) & CS_BUS_SLOT_SZ)) {
2719 printk(KERN_ERR PFX "ignoring bogus sensor interrups\n");
2720 skge_write32(hw, B0_HWE_IMSK,
2721 IS_ERR_MSK & ~IS_IRQ_SENSOR);
2722 } else
2723 printk(KERN_WARNING PFX "sensor interrupt\n");
2724 }
2725
2726
2727 }
2728
2729 if (hwstatus & IS_RAM_RD_PAR) {
2730 printk(KERN_ERR PFX "Ram read data parity error\n");
2731 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2732 }
2733
2734 if (hwstatus & IS_RAM_WR_PAR) {
2735 printk(KERN_ERR PFX "Ram write data parity error\n");
2736 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2737 }
2738
2739 if (hwstatus & IS_M1_PAR_ERR)
2740 skge_mac_parity(hw, 0);
2741
2742 if (hwstatus & IS_M2_PAR_ERR)
2743 skge_mac_parity(hw, 1);
2744
2745 if (hwstatus & IS_R1_PAR_ERR)
2746 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2747
2748 if (hwstatus & IS_R2_PAR_ERR)
2749 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2750
2751 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2752 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2753 hwstatus);
2754
2755 skge_pci_clear(hw);
2756
2757 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2758 if (hwstatus & IS_IRQ_STAT) {
2759 printk(KERN_WARNING PFX "IRQ status %x: still set ignoring hardware errors\n",
2760 hwstatus);
2761 hw->intr_mask &= ~IS_HW_ERR;
2762 }
2763 }
2764}
2765
2766/*
2767 * Interrrupt from PHY are handled in tasklet (soft irq)
2768 * because accessing phy registers requires spin wait which might
2769 * cause excess interrupt latency.
2770 */
2771static void skge_extirq(unsigned long data)
2772{
2773 struct skge_hw *hw = (struct skge_hw *) data;
2774 int port;
2775
2776 spin_lock(&hw->phy_lock);
2777 for (port = 0; port < 2; port++) {
2778 struct net_device *dev = hw->dev[port];
2779
2780 if (dev && netif_running(dev)) {
2781 struct skge_port *skge = netdev_priv(dev);
2782
2783 if (hw->chip_id != CHIP_ID_GENESIS)
2784 yukon_phy_intr(skge);
2785 else if (hw->phy_type == SK_PHY_BCOM)
2786 genesis_bcom_intr(skge);
2787 }
2788 }
2789 spin_unlock(&hw->phy_lock);
2790
2791 local_irq_disable();
2792 hw->intr_mask |= IS_EXT_REG;
2793 skge_write32(hw, B0_IMSK, hw->intr_mask);
2794 local_irq_enable();
2795}
2796
2797static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2798{
2799 struct skge_hw *hw = dev_id;
2800 u32 status = skge_read32(hw, B0_SP_ISRC);
2801
2802 if (status == 0 || status == ~0) /* hotplug or shared irq */
2803 return IRQ_NONE;
2804
2805 status &= hw->intr_mask;
2806
2807 if ((status & IS_R1_F) && netif_rx_schedule_prep(hw->dev[0])) {
2808 status &= ~IS_R1_F;
2809 hw->intr_mask &= ~IS_R1_F;
2810 skge_write32(hw, B0_IMSK, hw->intr_mask);
2811 __netif_rx_schedule(hw->dev[0]);
2812 }
2813
2814 if ((status & IS_R2_F) && netif_rx_schedule_prep(hw->dev[1])) {
2815 status &= ~IS_R2_F;
2816 hw->intr_mask &= ~IS_R2_F;
2817 skge_write32(hw, B0_IMSK, hw->intr_mask);
2818 __netif_rx_schedule(hw->dev[1]);
2819 }
2820
2821 if (status & IS_XA1_F)
2822 skge_tx_intr(hw->dev[0]);
2823
2824 if (status & IS_XA2_F)
2825 skge_tx_intr(hw->dev[1]);
2826
2827 if (status & IS_MAC1)
2828 skge_mac_intr(hw, 0);
95566065 2829
baef58b1
SH		 2830 if (status & IS_MAC2)
2831 skge_mac_intr(hw, 1);
2832
2833 if (status & IS_HW_ERR)
2834 skge_error_irq(hw);
2835
2836 if (status & IS_EXT_REG) {
2837 hw->intr_mask &= ~IS_EXT_REG;
2838 tasklet_schedule(&hw->ext_tasklet);
2839 }
2840
2841 if (status)
2842 skge_write32(hw, B0_IMSK, hw->intr_mask);
2843
2844 return IRQ_HANDLED;
2845}
2846
2847#ifdef CONFIG_NET_POLL_CONTROLLER
2848static void skge_netpoll(struct net_device *dev)
2849{
2850 struct skge_port *skge = netdev_priv(dev);
2851
2852 disable_irq(dev->irq);
2853 skge_intr(dev->irq, skge->hw, NULL);
2854 enable_irq(dev->irq);
2855}
2856#endif
2857
2858static int skge_set_mac_address(struct net_device *dev, void *p)
2859{
2860 struct skge_port *skge = netdev_priv(dev);
2861 struct sockaddr *addr = p;
2862 int err = 0;
2863
2864 if (!is_valid_ether_addr(addr->sa_data))
2865 return -EADDRNOTAVAIL;
2866
2867 skge_down(dev);
2868 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2869 memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2870 dev->dev_addr, ETH_ALEN);
2871 memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2872 dev->dev_addr, ETH_ALEN);
2873 if (dev->flags & IFF_UP)
2874 err = skge_up(dev);
2875 return err;
2876}
2877
2878static const struct {
2879 u8 id;
2880 const char *name;
2881} skge_chips[] = {
2882 { CHIP_ID_GENESIS, "Genesis" },
2883 { CHIP_ID_YUKON, "Yukon" },
2884 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2885 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2886 { CHIP_ID_YUKON_XL, "Yukon-2 XL"},
2887 { CHIP_ID_YUKON_EC, "YUKON-2 EC"},
2888 { CHIP_ID_YUKON_FE, "YUKON-2 FE"},
2889};
2890
2891static const char *skge_board_name(const struct skge_hw *hw)
2892{
2893 int i;
2894 static char buf[16];
2895
2896 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2897 if (skge_chips[i].id == hw->chip_id)
2898 return skge_chips[i].name;
2899
2900 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2901 return buf;
2902}
2903
2904
2905/*
2906 * Setup the board data structure, but don't bring up
2907 * the port(s)
2908 */
2909static int skge_reset(struct skge_hw *hw)
2910{
2911 u16 ctst;
981d0377
SH		 2912 u8 t8, mac_cfg;
2913 int i;
baef58b1
SH		 2914
2915 ctst = skge_read16(hw, B0_CTST);
2916
2917 /* do a SW reset */
2918 skge_write8(hw, B0_CTST, CS_RST_SET);
2919 skge_write8(hw, B0_CTST, CS_RST_CLR);
2920
2921 /* clear PCI errors, if any */
2922 skge_pci_clear(hw);
2923
2924 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2925
2926 /* restore CLK_RUN bits (for Yukon-Lite) */
2927 skge_write16(hw, B0_CTST,
2928 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2929
2930 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2931 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
2932 hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
2933
95566065 2934 switch (hw->chip_id) {
baef58b1
SH		 2935 case CHIP_ID_GENESIS:
2936 switch (hw->phy_type) {
2937 case SK_PHY_XMAC:
2938 hw->phy_addr = PHY_ADDR_XMAC;
2939 break;
2940 case SK_PHY_BCOM:
2941 hw->phy_addr = PHY_ADDR_BCOM;
2942 break;
2943 default:
2944 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2945 pci_name(hw->pdev), hw->phy_type);
2946 return -EOPNOTSUPP;
2947 }
2948 break;
2949
2950 case CHIP_ID_YUKON:
2951 case CHIP_ID_YUKON_LITE:
2952 case CHIP_ID_YUKON_LP:
2953 if (hw->phy_type < SK_PHY_MARV_COPPER && hw->pmd_type != 'S')
2954 hw->phy_type = SK_PHY_MARV_COPPER;
2955
2956 hw->phy_addr = PHY_ADDR_MARV;
2957 if (!iscopper(hw))
2958 hw->phy_type = SK_PHY_MARV_FIBER;
2959
2960 break;
2961
2962 default:
2963 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2964 pci_name(hw->pdev), hw->chip_id);
2965 return -EOPNOTSUPP;
2966 }
2967
981d0377
SH		 2968 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2969 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2970 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 2971
2972 /* read the adapters RAM size */
2973 t8 = skge_read8(hw, B2_E_0);
2974 if (hw->chip_id == CHIP_ID_GENESIS) {
2975 if (t8 == 3) {
2976 /* special case: 4 x 64k x 36, offset = 0x80000 */
2977 hw->ram_size = 0x100000;
2978 hw->ram_offset = 0x80000;
2979 } else
2980 hw->ram_size = t8 * 512;
2981 }
2982 else if (t8 == 0)
2983 hw->ram_size = 0x20000;
2984 else
2985 hw->ram_size = t8 * 4096;
2986
2987 if (hw->chip_id == CHIP_ID_GENESIS)
2988 genesis_init(hw);
2989 else {
2990 /* switch power to VCC (WA for VAUX problem) */
2991 skge_write8(hw, B0_POWER_CTRL,
2992 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
981d0377 2993 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 2994 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2995 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 2996 }
2997 }
2998
2999 /* turn off hardware timer (unused) */
3000 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3001 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3002 skge_write8(hw, B0_LED, LED_STAT_ON);
3003
3004 /* enable the Tx Arbiters */
981d0377 3005 for (i = 0; i < hw->ports; i++)
6b0c1480 3006 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3007
3008 /* Initialize ram interface */
3009 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3010
3011 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3012 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3013 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3014 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3015 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3016 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3017 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3018 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3019 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3020 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3021 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3022 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3023
3024 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3025
3026 /* Set interrupt moderation for Transmit only
3027 * Receive interrupts avoided by NAPI
3028 */
3029 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3030 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3031 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3032
3033 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
981d0377 3034 if (hw->ports > 1)
baef58b1
SH		 3035 hw->intr_mask |= IS_PORT_2;
3036 skge_write32(hw, B0_IMSK, hw->intr_mask);
3037
3038 if (hw->chip_id != CHIP_ID_GENESIS)
3039 skge_write8(hw, GMAC_IRQ_MSK, 0);
3040
3041 spin_lock_bh(&hw->phy_lock);
981d0377 3042 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3043 if (hw->chip_id == CHIP_ID_GENESIS)
3044 genesis_reset(hw, i);
3045 else
3046 yukon_reset(hw, i);
3047 }
3048 spin_unlock_bh(&hw->phy_lock);
3049
3050 return 0;
3051}
3052
3053/* Initialize network device */
981d0377
SH		 3054static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3055 int highmem)
baef58b1
SH		 3056{
3057 struct skge_port *skge;
3058 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3059
3060 if (!dev) {
3061 printk(KERN_ERR "skge etherdev alloc failed");
3062 return NULL;
3063 }
3064
3065 SET_MODULE_OWNER(dev);
3066 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3067 dev->open = skge_up;
3068 dev->stop = skge_down;
3069 dev->hard_start_xmit = skge_xmit_frame;
3070 dev->get_stats = skge_get_stats;
3071 if (hw->chip_id == CHIP_ID_GENESIS)
3072 dev->set_multicast_list = genesis_set_multicast;
3073 else
3074 dev->set_multicast_list = yukon_set_multicast;
3075
3076 dev->set_mac_address = skge_set_mac_address;
3077 dev->change_mtu = skge_change_mtu;
3078 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3079 dev->tx_timeout = skge_tx_timeout;
3080 dev->watchdog_timeo = TX_WATCHDOG;
3081 dev->poll = skge_poll;
3082 dev->weight = NAPI_WEIGHT;
3083#ifdef CONFIG_NET_POLL_CONTROLLER
3084 dev->poll_controller = skge_netpoll;
3085#endif
3086 dev->irq = hw->pdev->irq;
3087 dev->features = NETIF_F_LLTX;
981d0377
SH		 3088 if (highmem)
3089 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3090
3091 skge = netdev_priv(dev);
3092 skge->netdev = dev;
3093 skge->hw = hw;
3094 skge->msg_enable = netif_msg_init(debug, default_msg);
3095 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3096 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3097
3098 /* Auto speed and flow control */
3099 skge->autoneg = AUTONEG_ENABLE;
3100 skge->flow_control = FLOW_MODE_SYMMETRIC;
3101 skge->duplex = -1;
3102 skge->speed = -1;
3103 skge->advertising = skge_modes(hw);
3104
3105 hw->dev[port] = dev;
3106
3107 skge->port = port;
3108
3109 spin_lock_init(&skge->tx_lock);
3110
3111 init_timer(&skge->link_check);
3112 skge->link_check.function = skge_link_timer;
3113 skge->link_check.data = (unsigned long) skge;
3114
3115 init_timer(&skge->led_blink);
3116 skge->led_blink.function = skge_blink_timer;
3117 skge->led_blink.data = (unsigned long) skge;
3118
3119 if (hw->chip_id != CHIP_ID_GENESIS) {
3120 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3121 skge->rx_csum = 1;
3122 }
3123
3124 /* read the mac address */
3125 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3126
3127 /* device is off until link detection */
3128 netif_carrier_off(dev);
3129 netif_stop_queue(dev);
3130
3131 return dev;
3132}
3133
3134static void __devinit skge_show_addr(struct net_device *dev)
3135{
3136 const struct skge_port *skge = netdev_priv(dev);
3137
3138 if (netif_msg_probe(skge))
3139 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3140 dev->name,
3141 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3142 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3143}
3144
3145static int __devinit skge_probe(struct pci_dev *pdev,
3146 const struct pci_device_id *ent)
3147{
3148 struct net_device *dev, *dev1;
3149 struct skge_hw *hw;
3150 int err, using_dac = 0;
3151
3152 if ((err = pci_enable_device(pdev))) {
3153 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3154 pci_name(pdev));
3155 goto err_out;
3156 }
3157
3158 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3159 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3160 pci_name(pdev));
3161 goto err_out_disable_pdev;
3162 }
3163
3164 pci_set_master(pdev);
3165
3166 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3167 using_dac = 1;
3168 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3169 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3170 pci_name(pdev));
3171 goto err_out_free_regions;
3172 }
3173
3174#ifdef __BIG_ENDIAN
3175 /* byte swap decriptors in hardware */
3176 {
3177 u32 reg;
3178
3179 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3180 reg |= PCI_REV_DESC;
3181 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3182 }
3183#endif
3184
3185 err = -ENOMEM;
3186 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3187 if (!hw) {
3188 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3189 pci_name(pdev));
3190 goto err_out_free_regions;
3191 }
3192
3193 memset(hw, 0, sizeof(*hw));
3194 hw->pdev = pdev;
3195 spin_lock_init(&hw->phy_lock);
3196 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3197
3198 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3199 if (!hw->regs) {
3200 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3201 pci_name(pdev));
3202 goto err_out_free_hw;
3203 }
3204
3205 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3206 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3207 pci_name(pdev), pdev->irq);
3208 goto err_out_iounmap;
3209 }
3210 pci_set_drvdata(pdev, hw);
3211
3212 err = skge_reset(hw);
3213 if (err)
3214 goto err_out_free_irq;
3215
3216 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3217 pci_resource_start(pdev, 0), pdev->irq,
981d0377 3218 skge_board_name(hw), hw->chip_rev);
baef58b1 3219
981d0377 3220 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
baef58b1
SH		 3221 goto err_out_led_off;
3222
baef58b1
SH		 3223 if ((err = register_netdev(dev))) {
3224 printk(KERN_ERR PFX "%s: cannot register net device\n",
3225 pci_name(pdev));
3226 goto err_out_free_netdev;
3227 }
3228
3229 skge_show_addr(dev);
3230
981d0377 3231 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3232 if (register_netdev(dev1) == 0)
3233 skge_show_addr(dev1);
3234 else {
3235 /* Failure to register second port need not be fatal */
3236 printk(KERN_WARNING PFX "register of second port failed\n");
3237 hw->dev[1] = NULL;
3238 free_netdev(dev1);
3239 }
3240 }
3241
3242 return 0;
3243
3244err_out_free_netdev:
3245 free_netdev(dev);
3246err_out_led_off:
3247 skge_write16(hw, B0_LED, LED_STAT_OFF);
3248err_out_free_irq:
3249 free_irq(pdev->irq, hw);
3250err_out_iounmap:
3251 iounmap(hw->regs);
3252err_out_free_hw:
3253 kfree(hw);
3254err_out_free_regions:
3255 pci_release_regions(pdev);
3256err_out_disable_pdev:
3257 pci_disable_device(pdev);
3258 pci_set_drvdata(pdev, NULL);
3259err_out:
3260 return err;
3261}
3262
3263static void __devexit skge_remove(struct pci_dev *pdev)
3264{
3265 struct skge_hw *hw = pci_get_drvdata(pdev);
3266 struct net_device *dev0, *dev1;
3267
95566065 3268 if (!hw)
baef58b1
SH		 3269 return;
3270
3271 if ((dev1 = hw->dev[1]))
3272 unregister_netdev(dev1);
3273 dev0 = hw->dev[0];
3274 unregister_netdev(dev0);
3275
3276 tasklet_kill(&hw->ext_tasklet);
3277
3278 free_irq(pdev->irq, hw);
3279 pci_release_regions(pdev);
3280 pci_disable_device(pdev);
3281 if (dev1)
3282 free_netdev(dev1);
3283 free_netdev(dev0);
3284 skge_write16(hw, B0_LED, LED_STAT_OFF);
3285 iounmap(hw->regs);
3286 kfree(hw);
3287 pci_set_drvdata(pdev, NULL);
3288}
3289
3290#ifdef CONFIG_PM
3291static int skge_suspend(struct pci_dev *pdev, u32 state)
3292{
3293 struct skge_hw *hw = pci_get_drvdata(pdev);
3294 int i, wol = 0;
3295
95566065 3296 for (i = 0; i < 2; i++) {
baef58b1
SH		 3297 struct net_device *dev = hw->dev[i];
3298
3299 if (dev) {
3300 struct skge_port *skge = netdev_priv(dev);
3301 if (netif_running(dev)) {
3302 netif_carrier_off(dev);
3303 skge_down(dev);
3304 }
3305 netif_device_detach(dev);
3306 wol |= skge->wol;
3307 }
3308 }
3309
3310 pci_save_state(pdev);
3311 pci_enable_wake(pdev, state, wol);
3312 pci_disable_device(pdev);
3313 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3314
3315 return 0;
3316}
3317
3318static int skge_resume(struct pci_dev *pdev)
3319{
3320 struct skge_hw *hw = pci_get_drvdata(pdev);
3321 int i;
3322
3323 pci_set_power_state(pdev, PCI_D0);
3324 pci_restore_state(pdev);
3325 pci_enable_wake(pdev, PCI_D0, 0);
3326
3327 skge_reset(hw);
3328
95566065 3329 for (i = 0; i < 2; i++) {
baef58b1
SH		 3330 struct net_device *dev = hw->dev[i];
3331 if (dev) {
3332 netif_device_attach(dev);
95566065 3333 if (netif_running(dev))
baef58b1
SH		 3334 skge_up(dev);
3335 }
3336 }
3337 return 0;
3338}
3339#endif
3340
3341static struct pci_driver skge_driver = {
3342 .name = DRV_NAME,
3343 .id_table = skge_id_table,
3344 .probe = skge_probe,
3345 .remove = __devexit_p(skge_remove),
3346#ifdef CONFIG_PM
3347 .suspend = skge_suspend,
3348 .resume = skge_resume,
3349#endif
3350};
3351
3352static int __init skge_init_module(void)
3353{
3354 return pci_module_init(&skge_driver);
3355}
3356
3357static void __exit skge_cleanup_module(void)
3358{
3359 pci_unregister_driver(&skge_driver);
3360}
3361
3362module_init(skge_init_module);
3363module_exit(skge_cleanup_module);
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