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[net-next-2.6.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
798b6b19 14 * the Free Software Foundation; either version 2 of the License.
baef58b1
SH		 15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
14c85021 26#include <linux/in.h>
baef58b1
SH		 27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/if_vlan.h>
35#include <linux/ip.h>
36#include <linux/delay.h>
37#include <linux/crc32.h>
4075400b 38#include <linux/dma-mapping.h>
678aa1f6
SH		 39#include <linux/debugfs.h>
40#include <linux/seq_file.h>
2cd8e5d3 41#include <linux/mii.h>
baef58b1
SH		 42#include <asm/irq.h>
43
44#include "skge.h"
45
46#define DRV_NAME "skge"
d0cab896 47#define DRV_VERSION "1.12"
baef58b1
SH		 48#define PFX DRV_NAME " "
49
50#define DEFAULT_TX_RING_SIZE 128
51#define DEFAULT_RX_RING_SIZE 512
52#define MAX_TX_RING_SIZE 1024
9db96479 53#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
baef58b1 54#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 55#define RX_COPY_THRESHOLD 128
56#define RX_BUF_SIZE 1536
baef58b1
SH		 57#define PHY_RETRIES 1000
58#define ETH_JUMBO_MTU 9000
59#define TX_WATCHDOG (5 * HZ)
60#define NAPI_WEIGHT 64
6abebb53 61#define BLINK_MS 250
501fb72d 62#define LINK_HZ HZ
baef58b1 63
afa151b9
SH		 64#define SKGE_EEPROM_MAGIC 0x9933aabb
65
66
baef58b1 67MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
65ebe634 68MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
baef58b1
SH		 69MODULE_LICENSE("GPL");
70MODULE_VERSION(DRV_VERSION);
71
72static const u32 default_msg
73 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
74 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
75
76static int debug = -1; /* defaults above */
77module_param(debug, int, 0);
78MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
79
80static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 81 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
82 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
83 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
84 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
f19841f5 85 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
2d2a3871 86 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
275834d1
SH		 87 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
88 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
89 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 90 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
f19841f5 91 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
baef58b1
SH		 92 { 0 }
93};
94MODULE_DEVICE_TABLE(pci, skge_id_table);
95
96static int skge_up(struct net_device *dev);
97static int skge_down(struct net_device *dev);
ee294dcd 98static void skge_phy_reset(struct skge_port *skge);
513f533e 99static void skge_tx_clean(struct net_device *dev);
2cd8e5d3
SH		 100static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
101static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 102static void genesis_get_stats(struct skge_port *skge, u64 *data);
103static void yukon_get_stats(struct skge_port *skge, u64 *data);
104static void yukon_init(struct skge_hw *hw, int port);
baef58b1 105static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 106static void genesis_link_up(struct skge_port *skge);
baef58b1 107
7e676d91 108/* Avoid conditionals by using array */
baef58b1
SH		 109static const int txqaddr[] = { Q_XA1, Q_XA2 };
110static const int rxqaddr[] = { Q_R1, Q_R2 };
111static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
112static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
4ebabfcb
SH		 113static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
114static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1 115
baef58b1
SH		 116static int skge_get_regs_len(struct net_device *dev)
117{
c3f8be96 118 return 0x4000;
baef58b1
SH		 119}
120
121/*
c3f8be96
SH		 122 * Returns copy of whole control register region
123 * Note: skip RAM address register because accessing it will
124 * cause bus hangs!
baef58b1
SH		 125 */
126static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
127 void *p)
128{
129 const struct skge_port *skge = netdev_priv(dev);
baef58b1 130 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 131
132 regs->version = 1;
c3f8be96
SH		 133 memset(p, 0, regs->len);
134 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 135
c3f8be96
SH		 136 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
137 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 138}
139
8f3f8193 140/* Wake on Lan only supported on Yukon chips with rev 1 or above */
a504e64a 141static u32 wol_supported(const struct skge_hw *hw)
baef58b1 142{
d17ecb23 143 if (hw->chip_id == CHIP_ID_GENESIS)
a504e64a 144 return 0;
d17ecb23
SH		 145
146 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
147 return 0;
148
149 return WAKE_MAGIC | WAKE_PHY;
a504e64a
SH		 150}
151
152static u32 pci_wake_enabled(struct pci_dev *dev)
153{
154 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
155 u16 value;
156
157 /* If device doesn't support PM Capabilities, but request is to disable
158 * wake events, it's a nop; otherwise fail */
159 if (!pm)
160 return 0;
161
162 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
163
164 value &= PCI_PM_CAP_PME_MASK;
165 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
166
167 return value != 0;
168}
169
170static void skge_wol_init(struct skge_port *skge)
171{
172 struct skge_hw *hw = skge->hw;
173 int port = skge->port;
692412b3 174 u16 ctrl;
a504e64a 175
a504e64a
SH		 176 skge_write16(hw, B0_CTST, CS_RST_CLR);
177 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
178
692412b3
SH		 179 /* Turn on Vaux */
180 skge_write8(hw, B0_POWER_CTRL,
181 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
a504e64a 182
692412b3
SH		 183 /* WA code for COMA mode -- clear PHY reset */
184 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
185 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
186 u32 reg = skge_read32(hw, B2_GP_IO);
187 reg |= GP_DIR_9;
188 reg &= ~GP_IO_9;
189 skge_write32(hw, B2_GP_IO, reg);
190 }
a504e64a 191
692412b3
SH		 192 skge_write32(hw, SK_REG(port, GPHY_CTRL),
193 GPC_DIS_SLEEP |
194 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
195 GPC_ANEG_1 | GPC_RST_SET);
a504e64a 196
692412b3
SH		 197 skge_write32(hw, SK_REG(port, GPHY_CTRL),
198 GPC_DIS_SLEEP |
199 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
200 GPC_ANEG_1 | GPC_RST_CLR);
201
202 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
203
204 /* Force to 10/100 skge_reset will re-enable on resume */
205 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
206 PHY_AN_100FULL | PHY_AN_100HALF |
207 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
208 /* no 1000 HD/FD */
209 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
210 gm_phy_write(hw, port, PHY_MARV_CTRL,
211 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
212 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
a504e64a 213
a504e64a
SH		 214
215 /* Set GMAC to no flow control and auto update for speed/duplex */
216 gma_write16(hw, port, GM_GP_CTRL,
217 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
218 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
219
220 /* Set WOL address */
221 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
222 skge->netdev->dev_addr, ETH_ALEN);
223
224 /* Turn on appropriate WOL control bits */
225 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
226 ctrl = 0;
227 if (skge->wol & WAKE_PHY)
228 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
229 else
230 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
231
232 if (skge->wol & WAKE_MAGIC)
233 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
234 else
235 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
236
237 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
238 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
239
240 /* block receiver */
241 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 242}
243
244static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
245{
246 struct skge_port *skge = netdev_priv(dev);
247
a504e64a
SH		 248 wol->supported = wol_supported(skge->hw);
249 wol->wolopts = skge->wol;
baef58b1
SH		 250}
251
252static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
253{
254 struct skge_port *skge = netdev_priv(dev);
255 struct skge_hw *hw = skge->hw;
256
692412b3 257 if (wol->wolopts & ~wol_supported(hw))
baef58b1
SH		 258 return -EOPNOTSUPP;
259
a504e64a 260 skge->wol = wol->wolopts;
baef58b1
SH		 261 return 0;
262}
263
8f3f8193
SH		 264/* Determine supported/advertised modes based on hardware.
265 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 266 */
267static u32 skge_supported_modes(const struct skge_hw *hw)
268{
269 u32 supported;
270
5e1705dd 271 if (hw->copper) {
31b619c5
SH		 272 supported = SUPPORTED_10baseT_Half
273 | SUPPORTED_10baseT_Full
274 | SUPPORTED_100baseT_Half
275 | SUPPORTED_100baseT_Full
276 | SUPPORTED_1000baseT_Half
277 | SUPPORTED_1000baseT_Full
278 | SUPPORTED_Autoneg| SUPPORTED_TP;
279
280 if (hw->chip_id == CHIP_ID_GENESIS)
281 supported &= ~(SUPPORTED_10baseT_Half
282 | SUPPORTED_10baseT_Full
283 | SUPPORTED_100baseT_Half
284 | SUPPORTED_100baseT_Full);
285
286 else if (hw->chip_id == CHIP_ID_YUKON)
287 supported &= ~SUPPORTED_1000baseT_Half;
288 } else
4b67be99
SH		 289 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
290 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
31b619c5
SH		 291
292 return supported;
293}
baef58b1
SH		 294
295static int skge_get_settings(struct net_device *dev,
296 struct ethtool_cmd *ecmd)
297{
298 struct skge_port *skge = netdev_priv(dev);
299 struct skge_hw *hw = skge->hw;
300
301 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 302 ecmd->supported = skge_supported_modes(hw);
baef58b1 303
5e1705dd 304 if (hw->copper) {
baef58b1
SH		 305 ecmd->port = PORT_TP;
306 ecmd->phy_address = hw->phy_addr;
31b619c5 307 } else
baef58b1 308 ecmd->port = PORT_FIBRE;
baef58b1
SH		 309
310 ecmd->advertising = skge->advertising;
311 ecmd->autoneg = skge->autoneg;
312 ecmd->speed = skge->speed;
313 ecmd->duplex = skge->duplex;
314 return 0;
315}
316
baef58b1
SH		 317static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
318{
319 struct skge_port *skge = netdev_priv(dev);
320 const struct skge_hw *hw = skge->hw;
31b619c5 321 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 322
323 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 324 ecmd->advertising = supported;
325 skge->duplex = -1;
326 skge->speed = -1;
baef58b1 327 } else {
31b619c5
SH		 328 u32 setting;
329
2c668514 330 switch (ecmd->speed) {
baef58b1 331 case SPEED_1000:
31b619c5
SH		 332 if (ecmd->duplex == DUPLEX_FULL)
333 setting = SUPPORTED_1000baseT_Full;
334 else if (ecmd->duplex == DUPLEX_HALF)
335 setting = SUPPORTED_1000baseT_Half;
336 else
337 return -EINVAL;
baef58b1
SH		 338 break;
339 case SPEED_100:
31b619c5
SH		 340 if (ecmd->duplex == DUPLEX_FULL)
341 setting = SUPPORTED_100baseT_Full;
342 else if (ecmd->duplex == DUPLEX_HALF)
343 setting = SUPPORTED_100baseT_Half;
344 else
345 return -EINVAL;
346 break;
347
baef58b1 348 case SPEED_10:
31b619c5
SH		 349 if (ecmd->duplex == DUPLEX_FULL)
350 setting = SUPPORTED_10baseT_Full;
351 else if (ecmd->duplex == DUPLEX_HALF)
352 setting = SUPPORTED_10baseT_Half;
353 else
baef58b1
SH		 354 return -EINVAL;
355 break;
356 default:
357 return -EINVAL;
358 }
31b619c5
SH		 359
360 if ((setting & supported) == 0)
361 return -EINVAL;
362
363 skge->speed = ecmd->speed;
364 skge->duplex = ecmd->duplex;
baef58b1
SH		 365 }
366
367 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 368 skge->advertising = ecmd->advertising;
369
ee294dcd
SH		 370 if (netif_running(dev))
371 skge_phy_reset(skge);
372
baef58b1
SH		 373 return (0);
374}
375
376static void skge_get_drvinfo(struct net_device *dev,
377 struct ethtool_drvinfo *info)
378{
379 struct skge_port *skge = netdev_priv(dev);
380
381 strcpy(info->driver, DRV_NAME);
382 strcpy(info->version, DRV_VERSION);
383 strcpy(info->fw_version, "N/A");
384 strcpy(info->bus_info, pci_name(skge->hw->pdev));
385}
386
387static const struct skge_stat {
388 char name[ETH_GSTRING_LEN];
389 u16 xmac_offset;
390 u16 gma_offset;
391} skge_stats[] = {
392 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
393 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
394
395 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
396 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
397 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
398 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
399 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
400 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
401 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
402 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
403
404 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
405 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
406 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
407 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
408 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
409 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
410
411 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
412 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
413 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
414 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
415 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
416};
417
b9f2c044 418static int skge_get_sset_count(struct net_device *dev, int sset)
baef58b1 419{
b9f2c044
JG		 420 switch (sset) {
421 case ETH_SS_STATS:
422 return ARRAY_SIZE(skge_stats);
423 default:
424 return -EOPNOTSUPP;
425 }
baef58b1
SH		 426}
427
428static void skge_get_ethtool_stats(struct net_device *dev,
429 struct ethtool_stats *stats, u64 *data)
430{
431 struct skge_port *skge = netdev_priv(dev);
432
433 if (skge->hw->chip_id == CHIP_ID_GENESIS)
434 genesis_get_stats(skge, data);
435 else
436 yukon_get_stats(skge, data);
437}
438
439/* Use hardware MIB variables for critical path statistics and
440 * transmit feedback not reported at interrupt.
441 * Other errors are accounted for in interrupt handler.
442 */
443static struct net_device_stats *skge_get_stats(struct net_device *dev)
444{
445 struct skge_port *skge = netdev_priv(dev);
446 u64 data[ARRAY_SIZE(skge_stats)];
447
448 if (skge->hw->chip_id == CHIP_ID_GENESIS)
449 genesis_get_stats(skge, data);
450 else
451 yukon_get_stats(skge, data);
452
da00772f
SH		 453 dev->stats.tx_bytes = data[0];
454 dev->stats.rx_bytes = data[1];
455 dev->stats.tx_packets = data[2] + data[4] + data[6];
456 dev->stats.rx_packets = data[3] + data[5] + data[7];
457 dev->stats.multicast = data[3] + data[5];
458 dev->stats.collisions = data[10];
459 dev->stats.tx_aborted_errors = data[12];
baef58b1 460
da00772f 461 return &dev->stats;
baef58b1
SH		 462}
463
464static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
465{
466 int i;
467
95566065 468 switch (stringset) {
baef58b1
SH		 469 case ETH_SS_STATS:
470 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
471 memcpy(data + i * ETH_GSTRING_LEN,
472 skge_stats[i].name, ETH_GSTRING_LEN);
473 break;
474 }
475}
476
477static void skge_get_ring_param(struct net_device *dev,
478 struct ethtool_ringparam *p)
479{
480 struct skge_port *skge = netdev_priv(dev);
481
482 p->rx_max_pending = MAX_RX_RING_SIZE;
483 p->tx_max_pending = MAX_TX_RING_SIZE;
484 p->rx_mini_max_pending = 0;
485 p->rx_jumbo_max_pending = 0;
486
487 p->rx_pending = skge->rx_ring.count;
488 p->tx_pending = skge->tx_ring.count;
489 p->rx_mini_pending = 0;
490 p->rx_jumbo_pending = 0;
491}
492
493static int skge_set_ring_param(struct net_device *dev,
494 struct ethtool_ringparam *p)
495{
496 struct skge_port *skge = netdev_priv(dev);
3b8bb472 497 int err;
baef58b1
SH		 498
499 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
9db96479 500 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
baef58b1
SH		 501 return -EINVAL;
502
503 skge->rx_ring.count = p->rx_pending;
504 skge->tx_ring.count = p->tx_pending;
505
506 if (netif_running(dev)) {
507 skge_down(dev);
3b8bb472
SH		 508 err = skge_up(dev);
509 if (err)
510 dev_close(dev);
baef58b1
SH		 511 }
512
513 return 0;
514}
515
516static u32 skge_get_msglevel(struct net_device *netdev)
517{
518 struct skge_port *skge = netdev_priv(netdev);
519 return skge->msg_enable;
520}
521
522static void skge_set_msglevel(struct net_device *netdev, u32 value)
523{
524 struct skge_port *skge = netdev_priv(netdev);
525 skge->msg_enable = value;
526}
527
528static int skge_nway_reset(struct net_device *dev)
529{
530 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 531
532 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
533 return -EINVAL;
534
ee294dcd 535 skge_phy_reset(skge);
baef58b1
SH		 536 return 0;
537}
538
539static int skge_set_sg(struct net_device *dev, u32 data)
540{
541 struct skge_port *skge = netdev_priv(dev);
542 struct skge_hw *hw = skge->hw;
543
544 if (hw->chip_id == CHIP_ID_GENESIS && data)
545 return -EOPNOTSUPP;
546 return ethtool_op_set_sg(dev, data);
547}
548
549static int skge_set_tx_csum(struct net_device *dev, u32 data)
550{
551 struct skge_port *skge = netdev_priv(dev);
552 struct skge_hw *hw = skge->hw;
553
554 if (hw->chip_id == CHIP_ID_GENESIS && data)
555 return -EOPNOTSUPP;
556
557 return ethtool_op_set_tx_csum(dev, data);
558}
559
560static u32 skge_get_rx_csum(struct net_device *dev)
561{
562 struct skge_port *skge = netdev_priv(dev);
563
564 return skge->rx_csum;
565}
566
567/* Only Yukon supports checksum offload. */
568static int skge_set_rx_csum(struct net_device *dev, u32 data)
569{
570 struct skge_port *skge = netdev_priv(dev);
571
572 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
573 return -EOPNOTSUPP;
574
575 skge->rx_csum = data;
576 return 0;
577}
578
baef58b1
SH		 579static void skge_get_pauseparam(struct net_device *dev,
580 struct ethtool_pauseparam *ecmd)
581{
582 struct skge_port *skge = netdev_priv(dev);
583
5d5c8e03
SH		 584 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
585 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
586 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
baef58b1 587
5d5c8e03 588 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
baef58b1
SH		 589}
590
591static int skge_set_pauseparam(struct net_device *dev,
592 struct ethtool_pauseparam *ecmd)
593{
594 struct skge_port *skge = netdev_priv(dev);
5d5c8e03 595 struct ethtool_pauseparam old;
baef58b1 596
5d5c8e03
SH		 597 skge_get_pauseparam(dev, &old);
598
599 if (ecmd->autoneg != old.autoneg)
600 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
601 else {
602 if (ecmd->rx_pause && ecmd->tx_pause)
603 skge->flow_control = FLOW_MODE_SYMMETRIC;
604 else if (ecmd->rx_pause && !ecmd->tx_pause)
605 skge->flow_control = FLOW_MODE_SYM_OR_REM;
606 else if (!ecmd->rx_pause && ecmd->tx_pause)
607 skge->flow_control = FLOW_MODE_LOC_SEND;
608 else
609 skge->flow_control = FLOW_MODE_NONE;
610 }
baef58b1 611
e8df8554
SH		 612 if (netif_running(dev))
613 skge_phy_reset(skge);
5d5c8e03 614
baef58b1
SH		 615 return 0;
616}
617
618/* Chip internal frequency for clock calculations */
619static inline u32 hwkhz(const struct skge_hw *hw)
620{
187ff3b8 621 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
baef58b1
SH		 622}
623
8f3f8193 624/* Chip HZ to microseconds */
baef58b1
SH		 625static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
626{
627 return (ticks * 1000) / hwkhz(hw);
628}
629
8f3f8193 630/* Microseconds to chip HZ */
baef58b1
SH		 631static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
632{
633 return hwkhz(hw) * usec / 1000;
634}
635
636static int skge_get_coalesce(struct net_device *dev,
637 struct ethtool_coalesce *ecmd)
638{
639 struct skge_port *skge = netdev_priv(dev);
640 struct skge_hw *hw = skge->hw;
641 int port = skge->port;
642
643 ecmd->rx_coalesce_usecs = 0;
644 ecmd->tx_coalesce_usecs = 0;
645
646 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
647 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
648 u32 msk = skge_read32(hw, B2_IRQM_MSK);
649
650 if (msk & rxirqmask[port])
651 ecmd->rx_coalesce_usecs = delay;
652 if (msk & txirqmask[port])
653 ecmd->tx_coalesce_usecs = delay;
654 }
655
656 return 0;
657}
658
659/* Note: interrupt timer is per board, but can turn on/off per port */
660static int skge_set_coalesce(struct net_device *dev,
661 struct ethtool_coalesce *ecmd)
662{
663 struct skge_port *skge = netdev_priv(dev);
664 struct skge_hw *hw = skge->hw;
665 int port = skge->port;
666 u32 msk = skge_read32(hw, B2_IRQM_MSK);
667 u32 delay = 25;
668
669 if (ecmd->rx_coalesce_usecs == 0)
670 msk &= ~rxirqmask[port];
671 else if (ecmd->rx_coalesce_usecs < 25 ||
672 ecmd->rx_coalesce_usecs > 33333)
673 return -EINVAL;
674 else {
675 msk |= rxirqmask[port];
676 delay = ecmd->rx_coalesce_usecs;
677 }
678
679 if (ecmd->tx_coalesce_usecs == 0)
680 msk &= ~txirqmask[port];
681 else if (ecmd->tx_coalesce_usecs < 25 ||
682 ecmd->tx_coalesce_usecs > 33333)
683 return -EINVAL;
684 else {
685 msk |= txirqmask[port];
686 delay = min(delay, ecmd->rx_coalesce_usecs);
687 }
688
689 skge_write32(hw, B2_IRQM_MSK, msk);
690 if (msk == 0)
691 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
692 else {
693 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
694 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
695 }
696 return 0;
697}
698
6abebb53
SH		 699enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
700static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 701{
6abebb53
SH		 702 struct skge_hw *hw = skge->hw;
703 int port = skge->port;
704
9cbe330f 705 spin_lock_bh(&hw->phy_lock);
baef58b1 706 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 707 switch (mode) {
708 case LED_MODE_OFF:
64f6b64d
SH		 709 if (hw->phy_type == SK_PHY_BCOM)
710 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
711 else {
712 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
713 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
714 }
6abebb53
SH		 715 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
716 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
717 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
718 break;
baef58b1 719
6abebb53
SH		 720 case LED_MODE_ON:
721 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
722 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 723
6abebb53
SH		 724 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
725 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 726
6abebb53 727 break;
baef58b1 728
6abebb53
SH		 729 case LED_MODE_TST:
730 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
731 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
732 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 733
64f6b64d
SH		 734 if (hw->phy_type == SK_PHY_BCOM)
735 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
736 else {
737 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
738 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
739 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
740 }
741
6abebb53 742 }
baef58b1 743 } else {
6abebb53
SH		 744 switch (mode) {
745 case LED_MODE_OFF:
746 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
747 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
748 PHY_M_LED_MO_DUP(MO_LED_OFF) |
749 PHY_M_LED_MO_10(MO_LED_OFF) |
750 PHY_M_LED_MO_100(MO_LED_OFF) |
751 PHY_M_LED_MO_1000(MO_LED_OFF) |
752 PHY_M_LED_MO_RX(MO_LED_OFF));
753 break;
754 case LED_MODE_ON:
755 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
756 PHY_M_LED_PULS_DUR(PULS_170MS) |
757 PHY_M_LED_BLINK_RT(BLINK_84MS) |
758 PHY_M_LEDC_TX_CTRL |
759 PHY_M_LEDC_DP_CTRL);
46a60f2d 760
6abebb53
SH		 761 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
762 PHY_M_LED_MO_RX(MO_LED_OFF) |
763 (skge->speed == SPEED_100 ?
764 PHY_M_LED_MO_100(MO_LED_ON) : 0));
765 break;
766 case LED_MODE_TST:
767 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
768 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
769 PHY_M_LED_MO_DUP(MO_LED_ON) |
770 PHY_M_LED_MO_10(MO_LED_ON) |
771 PHY_M_LED_MO_100(MO_LED_ON) |
772 PHY_M_LED_MO_1000(MO_LED_ON) |
773 PHY_M_LED_MO_RX(MO_LED_ON));
774 }
baef58b1 775 }
9cbe330f 776 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 777}
778
779/* blink LED's for finding board */
780static int skge_phys_id(struct net_device *dev, u32 data)
781{
782 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 783 unsigned long ms;
784 enum led_mode mode = LED_MODE_TST;
baef58b1 785
95566065 786 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 787 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
788 else
789 ms = data * 1000;
baef58b1 790
6abebb53
SH		 791 while (ms > 0) {
792 skge_led(skge, mode);
793 mode ^= LED_MODE_TST;
baef58b1 794
6abebb53
SH		 795 if (msleep_interruptible(BLINK_MS))
796 break;
797 ms -= BLINK_MS;
798 }
baef58b1 799
6abebb53
SH		 800 /* back to regular LED state */
801 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 802
803 return 0;
804}
805
afa151b9
SH		 806static int skge_get_eeprom_len(struct net_device *dev)
807{
808 struct skge_port *skge = netdev_priv(dev);
809 u32 reg2;
810
811 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
812 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
813}
814
815static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
816{
817 u32 val;
818
819 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
820
821 do {
822 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
823 } while (!(offset & PCI_VPD_ADDR_F));
824
825 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
826 return val;
827}
828
829static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
830{
831 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
832 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
833 offset | PCI_VPD_ADDR_F);
834
835 do {
836 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
837 } while (offset & PCI_VPD_ADDR_F);
838}
839
840static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
841 u8 *data)
842{
843 struct skge_port *skge = netdev_priv(dev);
844 struct pci_dev *pdev = skge->hw->pdev;
845 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
846 int length = eeprom->len;
847 u16 offset = eeprom->offset;
848
849 if (!cap)
850 return -EINVAL;
851
852 eeprom->magic = SKGE_EEPROM_MAGIC;
853
854 while (length > 0) {
855 u32 val = skge_vpd_read(pdev, cap, offset);
856 int n = min_t(int, length, sizeof(val));
857
858 memcpy(data, &val, n);
859 length -= n;
860 data += n;
861 offset += n;
862 }
863 return 0;
864}
865
866static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
867 u8 *data)
868{
869 struct skge_port *skge = netdev_priv(dev);
870 struct pci_dev *pdev = skge->hw->pdev;
871 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
872 int length = eeprom->len;
873 u16 offset = eeprom->offset;
874
875 if (!cap)
876 return -EINVAL;
877
878 if (eeprom->magic != SKGE_EEPROM_MAGIC)
879 return -EINVAL;
880
881 while (length > 0) {
882 u32 val;
883 int n = min_t(int, length, sizeof(val));
884
885 if (n < sizeof(val))
886 val = skge_vpd_read(pdev, cap, offset);
887 memcpy(&val, data, n);
888
889 skge_vpd_write(pdev, cap, offset, val);
890
891 length -= n;
892 data += n;
893 offset += n;
894 }
895 return 0;
896}
897
7282d491 898static const struct ethtool_ops skge_ethtool_ops = {
baef58b1
SH		 899 .get_settings = skge_get_settings,
900 .set_settings = skge_set_settings,
901 .get_drvinfo = skge_get_drvinfo,
902 .get_regs_len = skge_get_regs_len,
903 .get_regs = skge_get_regs,
904 .get_wol = skge_get_wol,
905 .set_wol = skge_set_wol,
906 .get_msglevel = skge_get_msglevel,
907 .set_msglevel = skge_set_msglevel,
908 .nway_reset = skge_nway_reset,
909 .get_link = ethtool_op_get_link,
afa151b9
SH		 910 .get_eeprom_len = skge_get_eeprom_len,
911 .get_eeprom = skge_get_eeprom,
912 .set_eeprom = skge_set_eeprom,
baef58b1
SH		 913 .get_ringparam = skge_get_ring_param,
914 .set_ringparam = skge_set_ring_param,
915 .get_pauseparam = skge_get_pauseparam,
916 .set_pauseparam = skge_set_pauseparam,
917 .get_coalesce = skge_get_coalesce,
918 .set_coalesce = skge_set_coalesce,
baef58b1 919 .set_sg = skge_set_sg,
baef58b1
SH		 920 .set_tx_csum = skge_set_tx_csum,
921 .get_rx_csum = skge_get_rx_csum,
922 .set_rx_csum = skge_set_rx_csum,
923 .get_strings = skge_get_strings,
924 .phys_id = skge_phys_id,
b9f2c044 925 .get_sset_count = skge_get_sset_count,
baef58b1
SH		 926 .get_ethtool_stats = skge_get_ethtool_stats,
927};
928
929/*
930 * Allocate ring elements and chain them together
931 * One-to-one association of board descriptors with ring elements
932 */
c3da1447 933static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 934{
935 struct skge_tx_desc *d;
936 struct skge_element *e;
937 int i;
938
cd861280 939 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
baef58b1
SH		 940 if (!ring->start)
941 return -ENOMEM;
942
943 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
944 e->desc = d;
945 if (i == ring->count - 1) {
946 e->next = ring->start;
947 d->next_offset = base;
948 } else {
949 e->next = e + 1;
950 d->next_offset = base + (i+1) * sizeof(*d);
951 }
952 }
953 ring->to_use = ring->to_clean = ring->start;
954
955 return 0;
956}
957
19a33d4e
SH		 958/* Allocate and setup a new buffer for receiving */
959static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
960 struct sk_buff *skb, unsigned int bufsize)
961{
962 struct skge_rx_desc *rd = e->desc;
963 u64 map;
baef58b1
SH		 964
965 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
966 PCI_DMA_FROMDEVICE);
967
968 rd->dma_lo = map;
969 rd->dma_hi = map >> 32;
970 e->skb = skb;
971 rd->csum1_start = ETH_HLEN;
972 rd->csum2_start = ETH_HLEN;
973 rd->csum1 = 0;
974 rd->csum2 = 0;
975
976 wmb();
977
978 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
979 pci_unmap_addr_set(e, mapaddr, map);
980 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 981}
982
19a33d4e
SH		 983/* Resume receiving using existing skb,
984 * Note: DMA address is not changed by chip.
985 * MTU not changed while receiver active.
986 */
5a011447 987static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 988{
989 struct skge_rx_desc *rd = e->desc;
990
991 rd->csum2 = 0;
992 rd->csum2_start = ETH_HLEN;
993
994 wmb();
995
996 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
997}
998
999
1000/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 1001static void skge_rx_clean(struct skge_port *skge)
1002{
1003 struct skge_hw *hw = skge->hw;
1004 struct skge_ring *ring = &skge->rx_ring;
1005 struct skge_element *e;
1006
19a33d4e
SH		 1007 e = ring->start;
1008 do {
baef58b1
SH		 1009 struct skge_rx_desc *rd = e->desc;
1010 rd->control = 0;
19a33d4e
SH		 1011 if (e->skb) {
1012 pci_unmap_single(hw->pdev,
1013 pci_unmap_addr(e, mapaddr),
1014 pci_unmap_len(e, maplen),
1015 PCI_DMA_FROMDEVICE);
1016 dev_kfree_skb(e->skb);
1017 e->skb = NULL;
1018 }
1019 } while ((e = e->next) != ring->start);
baef58b1
SH		 1020}
1021
19a33d4e 1022
baef58b1 1023/* Allocate buffers for receive ring
19a33d4e 1024 * For receive: to_clean is next received frame.
baef58b1 1025 */
c54f9765 1026static int skge_rx_fill(struct net_device *dev)
baef58b1 1027{
c54f9765 1028 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 1029 struct skge_ring *ring = &skge->rx_ring;
1030 struct skge_element *e;
baef58b1 1031
19a33d4e
SH		 1032 e = ring->start;
1033 do {
383181ac 1034 struct sk_buff *skb;
baef58b1 1035
c54f9765
SH		 1036 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1037 GFP_KERNEL);
19a33d4e
SH		 1038 if (!skb)
1039 return -ENOMEM;
1040
383181ac
SH		 1041 skb_reserve(skb, NET_IP_ALIGN);
1042 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
19a33d4e 1043 } while ( (e = e->next) != ring->start);
baef58b1 1044
19a33d4e
SH		 1045 ring->to_clean = ring->start;
1046 return 0;
baef58b1
SH		 1047}
1048
5d5c8e03
SH		 1049static const char *skge_pause(enum pause_status status)
1050{
1051 switch(status) {
1052 case FLOW_STAT_NONE:
1053 return "none";
1054 case FLOW_STAT_REM_SEND:
1055 return "rx only";
1056 case FLOW_STAT_LOC_SEND:
1057 return "tx_only";
1058 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1059 return "both";
1060 default:
1061 return "indeterminated";
1062 }
1063}
1064
1065
baef58b1
SH		 1066static void skge_link_up(struct skge_port *skge)
1067{
46a60f2d 1068 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 1069 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1070
baef58b1 1071 netif_carrier_on(skge->netdev);
29b4e886 1072 netif_wake_queue(skge->netdev);
baef58b1 1073
5d5c8e03 1074 if (netif_msg_link(skge)) {
baef58b1
SH		 1075 printk(KERN_INFO PFX
1076 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1077 skge->netdev->name, skge->speed,
1078 skge->duplex == DUPLEX_FULL ? "full" : "half",
5d5c8e03
SH		 1079 skge_pause(skge->flow_status));
1080 }
baef58b1
SH		 1081}
1082
1083static void skge_link_down(struct skge_port *skge)
1084{
54cfb5aa 1085 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 1086 netif_carrier_off(skge->netdev);
1087 netif_stop_queue(skge->netdev);
1088
1089 if (netif_msg_link(skge))
1090 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
1091}
1092
a1bc9b87
SH		 1093
1094static void xm_link_down(struct skge_hw *hw, int port)
1095{
1096 struct net_device *dev = hw->dev[port];
1097 struct skge_port *skge = netdev_priv(dev);
501fb72d 1098 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
a1bc9b87 1099
501fb72d 1100 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
a1bc9b87 1101
a1bc9b87
SH		 1102 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1103 xm_write16(hw, port, XM_MMU_CMD, cmd);
501fb72d 1104
a1bc9b87 1105 /* dummy read to ensure writing */
501fb72d 1106 xm_read16(hw, port, XM_MMU_CMD);
a1bc9b87
SH		 1107
1108 if (netif_carrier_ok(dev))
1109 skge_link_down(skge);
1110}
1111
2cd8e5d3 1112static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 1113{
1114 int i;
baef58b1 1115
6b0c1480 1116 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 1117 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 1118
64f6b64d
SH		 1119 if (hw->phy_type == SK_PHY_XMAC)
1120 goto ready;
1121
89bf5f23 1122 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 1123 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 1124 goto ready;
0781191c 1125 udelay(1);
baef58b1
SH		 1126 }
1127
2cd8e5d3 1128 return -ETIMEDOUT;
89bf5f23 1129 ready:
2cd8e5d3 1130 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 1131
2cd8e5d3
SH		 1132 return 0;
1133}
1134
1135static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1136{
1137 u16 v = 0;
1138 if (__xm_phy_read(hw, port, reg, &v))
1139 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1140 hw->dev[port]->name);
baef58b1
SH		 1141 return v;
1142}
1143
2cd8e5d3 1144static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1145{
1146 int i;
1147
6b0c1480 1148 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 1149 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 1150 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 1151 goto ready;
89bf5f23 1152 udelay(1);
baef58b1 1153 }
2cd8e5d3 1154 return -EIO;
baef58b1
SH		 1155
1156 ready:
6b0c1480 1157 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 1158 for (i = 0; i < PHY_RETRIES; i++) {
1159 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1160 return 0;
1161 udelay(1);
1162 }
1163 return -ETIMEDOUT;
baef58b1
SH		 1164}
1165
1166static void genesis_init(struct skge_hw *hw)
1167{
1168 /* set blink source counter */
1169 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1170 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1171
1172 /* configure mac arbiter */
1173 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1174
1175 /* configure mac arbiter timeout values */
1176 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1177 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1178 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1179 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1180
1181 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1182 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1183 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1184 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1185
1186 /* configure packet arbiter timeout */
1187 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1188 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1189 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1190 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1191 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1192}
1193
1194static void genesis_reset(struct skge_hw *hw, int port)
1195{
45bada65 1196 const u8 zero[8] = { 0 };
baef58b1 1197
46a60f2d
SH		 1198 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1199
baef58b1 1200 /* reset the statistics module */
6b0c1480 1201 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
501fb72d 1202 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
6b0c1480
SH		 1203 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1204 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1205 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 1206
89bf5f23 1207 /* disable Broadcom PHY IRQ */
64f6b64d
SH		 1208 if (hw->phy_type == SK_PHY_BCOM)
1209 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 1210
45bada65 1211 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 1212}
1213
1214
45bada65
SH		 1215/* Convert mode to MII values */
1216static const u16 phy_pause_map[] = {
1217 [FLOW_MODE_NONE] = 0,
1218 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1219 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
5d5c8e03 1220 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
45bada65
SH		 1221};
1222
4b67be99
SH		 1223/* special defines for FIBER (88E1011S only) */
1224static const u16 fiber_pause_map[] = {
1225 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1226 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1227 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
5d5c8e03 1228 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
4b67be99
SH		 1229};
1230
45bada65
SH		 1231
1232/* Check status of Broadcom phy link */
1233static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 1234{
45bada65
SH		 1235 struct net_device *dev = hw->dev[port];
1236 struct skge_port *skge = netdev_priv(dev);
1237 u16 status;
1238
1239 /* read twice because of latch */
501fb72d 1240 xm_phy_read(hw, port, PHY_BCOM_STAT);
45bada65
SH		 1241 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1242
45bada65 1243 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1244 xm_link_down(hw, port);
64f6b64d
SH		 1245 return;
1246 }
45bada65 1247
64f6b64d
SH		 1248 if (skge->autoneg == AUTONEG_ENABLE) {
1249 u16 lpa, aux;
45bada65 1250
64f6b64d
SH		 1251 if (!(status & PHY_ST_AN_OVER))
1252 return;
45bada65 1253
64f6b64d
SH		 1254 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1255 if (lpa & PHY_B_AN_RF) {
1256 printk(KERN_NOTICE PFX "%s: remote fault\n",
1257 dev->name);
1258 return;
1259 }
45bada65 1260
64f6b64d
SH		 1261 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1262
1263 /* Check Duplex mismatch */
1264 switch (aux & PHY_B_AS_AN_RES_MSK) {
1265 case PHY_B_RES_1000FD:
1266 skge->duplex = DUPLEX_FULL;
1267 break;
1268 case PHY_B_RES_1000HD:
1269 skge->duplex = DUPLEX_HALF;
1270 break;
1271 default:
1272 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1273 dev->name);
1274 return;
45bada65
SH		 1275 }
1276
64f6b64d
SH		 1277 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1278 switch (aux & PHY_B_AS_PAUSE_MSK) {
1279 case PHY_B_AS_PAUSE_MSK:
5d5c8e03 1280 skge->flow_status = FLOW_STAT_SYMMETRIC;
64f6b64d
SH		 1281 break;
1282 case PHY_B_AS_PRR:
5d5c8e03 1283 skge->flow_status = FLOW_STAT_REM_SEND;
64f6b64d
SH		 1284 break;
1285 case PHY_B_AS_PRT:
5d5c8e03 1286 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d
SH		 1287 break;
1288 default:
5d5c8e03 1289 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1290 }
1291 skge->speed = SPEED_1000;
45bada65 1292 }
64f6b64d
SH		 1293
1294 if (!netif_carrier_ok(dev))
1295 genesis_link_up(skge);
45bada65
SH		 1296}
1297
1298/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1299 * Phy on for 100 or 10Mbit operation
1300 */
64f6b64d 1301static void bcom_phy_init(struct skge_port *skge)
45bada65
SH		 1302{
1303 struct skge_hw *hw = skge->hw;
1304 int port = skge->port;
baef58b1 1305 int i;
45bada65 1306 u16 id1, r, ext, ctl;
baef58b1
SH		 1307
1308 /* magic workaround patterns for Broadcom */
1309 static const struct {
1310 u16 reg;
1311 u16 val;
1312 } A1hack[] = {
1313 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1314 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1315 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1316 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1317 }, C0hack[] = {
1318 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1319 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1320 };
1321
45bada65
SH		 1322 /* read Id from external PHY (all have the same address) */
1323 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1324
1325 /* Optimize MDIO transfer by suppressing preamble. */
1326 r = xm_read16(hw, port, XM_MMU_CMD);
1327 r |= XM_MMU_NO_PRE;
1328 xm_write16(hw, port, XM_MMU_CMD,r);
1329
2c668514 1330 switch (id1) {
45bada65
SH		 1331 case PHY_BCOM_ID1_C0:
1332 /*
1333 * Workaround BCOM Errata for the C0 type.
1334 * Write magic patterns to reserved registers.
1335 */
1336 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1337 xm_phy_write(hw, port,
1338 C0hack[i].reg, C0hack[i].val);
1339
1340 break;
1341 case PHY_BCOM_ID1_A1:
1342 /*
1343 * Workaround BCOM Errata for the A1 type.
1344 * Write magic patterns to reserved registers.
1345 */
1346 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1347 xm_phy_write(hw, port,
1348 A1hack[i].reg, A1hack[i].val);
1349 break;
1350 }
1351
1352 /*
1353 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1354 * Disable Power Management after reset.
1355 */
1356 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1357 r |= PHY_B_AC_DIS_PM;
1358 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1359
1360 /* Dummy read */
1361 xm_read16(hw, port, XM_ISRC);
1362
1363 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1364 ctl = PHY_CT_SP1000; /* always 1000mbit */
1365
1366 if (skge->autoneg == AUTONEG_ENABLE) {
1367 /*
1368 * Workaround BCOM Errata #1 for the C5 type.
1369 * 1000Base-T Link Acquisition Failure in Slave Mode
1370 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1371 */
1372 u16 adv = PHY_B_1000C_RD;
1373 if (skge->advertising & ADVERTISED_1000baseT_Half)
1374 adv |= PHY_B_1000C_AHD;
1375 if (skge->advertising & ADVERTISED_1000baseT_Full)
1376 adv |= PHY_B_1000C_AFD;
1377 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1378
1379 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1380 } else {
1381 if (skge->duplex == DUPLEX_FULL)
1382 ctl |= PHY_CT_DUP_MD;
1383 /* Force to slave */
1384 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1385 }
1386
1387 /* Set autonegotiation pause parameters */
1388 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1389 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1390
1391 /* Handle Jumbo frames */
64f6b64d 1392 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
45bada65
SH		 1393 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1394 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1395
1396 ext |= PHY_B_PEC_HIGH_LA;
1397
1398 }
1399
1400 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1401 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1402
8f3f8193 1403 /* Use link status change interrupt */
45bada65 1404 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
64f6b64d 1405}
45bada65 1406
64f6b64d
SH		 1407static void xm_phy_init(struct skge_port *skge)
1408{
1409 struct skge_hw *hw = skge->hw;
1410 int port = skge->port;
1411 u16 ctrl = 0;
1412
1413 if (skge->autoneg == AUTONEG_ENABLE) {
1414 if (skge->advertising & ADVERTISED_1000baseT_Half)
1415 ctrl |= PHY_X_AN_HD;
1416 if (skge->advertising & ADVERTISED_1000baseT_Full)
1417 ctrl |= PHY_X_AN_FD;
1418
4b67be99 1419 ctrl |= fiber_pause_map[skge->flow_control];
64f6b64d
SH		 1420
1421 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1422
1423 /* Restart Auto-negotiation */
1424 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1425 } else {
1426 /* Set DuplexMode in Config register */
1427 if (skge->duplex == DUPLEX_FULL)
1428 ctrl |= PHY_CT_DUP_MD;
1429 /*
1430 * Do NOT enable Auto-negotiation here. This would hold
1431 * the link down because no IDLEs are transmitted
1432 */
1433 }
1434
1435 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1436
1437 /* Poll PHY for status changes */
9cbe330f 1438 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
64f6b64d
SH		 1439}
1440
501fb72d 1441static int xm_check_link(struct net_device *dev)
64f6b64d
SH		 1442{
1443 struct skge_port *skge = netdev_priv(dev);
1444 struct skge_hw *hw = skge->hw;
1445 int port = skge->port;
1446 u16 status;
1447
1448 /* read twice because of latch */
501fb72d 1449 xm_phy_read(hw, port, PHY_XMAC_STAT);
64f6b64d
SH		 1450 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1451
1452 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1453 xm_link_down(hw, port);
501fb72d 1454 return 0;
64f6b64d
SH		 1455 }
1456
1457 if (skge->autoneg == AUTONEG_ENABLE) {
1458 u16 lpa, res;
1459
1460 if (!(status & PHY_ST_AN_OVER))
501fb72d 1461 return 0;
64f6b64d
SH		 1462
1463 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1464 if (lpa & PHY_B_AN_RF) {
1465 printk(KERN_NOTICE PFX "%s: remote fault\n",
1466 dev->name);
501fb72d 1467 return 0;
64f6b64d
SH		 1468 }
1469
1470 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1471
1472 /* Check Duplex mismatch */
1473 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1474 case PHY_X_RS_FD:
1475 skge->duplex = DUPLEX_FULL;
1476 break;
1477 case PHY_X_RS_HD:
1478 skge->duplex = DUPLEX_HALF;
1479 break;
1480 default:
1481 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1482 dev->name);
501fb72d 1483 return 0;
64f6b64d
SH		 1484 }
1485
1486 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
5d5c8e03
SH		 1487 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1488 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1489 (lpa & PHY_X_P_SYM_MD))
1490 skge->flow_status = FLOW_STAT_SYMMETRIC;
1491 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1492 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1493 /* Enable PAUSE receive, disable PAUSE transmit */
1494 skge->flow_status = FLOW_STAT_REM_SEND;
1495 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1496 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1497 /* Disable PAUSE receive, enable PAUSE transmit */
1498 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d 1499 else
5d5c8e03 1500 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1501
1502 skge->speed = SPEED_1000;
1503 }
1504
1505 if (!netif_carrier_ok(dev))
1506 genesis_link_up(skge);
501fb72d 1507 return 1;
64f6b64d
SH		 1508}
1509
1510/* Poll to check for link coming up.
501fb72d 1511 *
64f6b64d 1512 * Since internal PHY is wired to a level triggered pin, can't
501fb72d
SH		 1513 * get an interrupt when carrier is detected, need to poll for
1514 * link coming up.
64f6b64d 1515 */
9cbe330f 1516static void xm_link_timer(unsigned long arg)
64f6b64d 1517{
9cbe330f 1518 struct skge_port *skge = (struct skge_port *) arg;
c4028958 1519 struct net_device *dev = skge->netdev;
64f6b64d
SH		 1520 struct skge_hw *hw = skge->hw;
1521 int port = skge->port;
501fb72d
SH		 1522 int i;
1523 unsigned long flags;
64f6b64d
SH		 1524
1525 if (!netif_running(dev))
1526 return;
1527
501fb72d
SH		 1528 spin_lock_irqsave(&hw->phy_lock, flags);
1529
1530 /*
1531 * Verify that the link by checking GPIO register three times.
1532 * This pin has the signal from the link_sync pin connected to it.
1533 */
1534 for (i = 0; i < 3; i++) {
1535 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1536 goto link_down;
1537 }
1538
1539 /* Re-enable interrupt to detect link down */
1540 if (xm_check_link(dev)) {
1541 u16 msk = xm_read16(hw, port, XM_IMSK);
1542 msk &= ~XM_IS_INP_ASS;
1543 xm_write16(hw, port, XM_IMSK, msk);
64f6b64d 1544 xm_read16(hw, port, XM_ISRC);
64f6b64d 1545 } else {
501fb72d
SH		 1546link_down:
1547 mod_timer(&skge->link_timer,
1548 round_jiffies(jiffies + LINK_HZ));
64f6b64d 1549 }
501fb72d 1550 spin_unlock_irqrestore(&hw->phy_lock, flags);
45bada65
SH		 1551}
1552
1553static void genesis_mac_init(struct skge_hw *hw, int port)
1554{
1555 struct net_device *dev = hw->dev[port];
1556 struct skge_port *skge = netdev_priv(dev);
1557 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1558 int i;
1559 u32 r;
1560 const u8 zero[6] = { 0 };
1561
0781191c
SH		 1562 for (i = 0; i < 10; i++) {
1563 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1564 MFF_SET_MAC_RST);
1565 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1566 goto reset_ok;
1567 udelay(1);
1568 }
baef58b1 1569
0781191c
SH		 1570 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1571
1572 reset_ok:
baef58b1 1573 /* Unreset the XMAC. */
6b0c1480 1574 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1575
1576 /*
1577 * Perform additional initialization for external PHYs,
1578 * namely for the 1000baseTX cards that use the XMAC's
1579 * GMII mode.
1580 */
64f6b64d
SH		 1581 if (hw->phy_type != SK_PHY_XMAC) {
1582 /* Take external Phy out of reset */
1583 r = skge_read32(hw, B2_GP_IO);
1584 if (port == 0)
1585 r |= GP_DIR_0|GP_IO_0;
1586 else
1587 r |= GP_DIR_2|GP_IO_2;
89bf5f23 1588
64f6b64d 1589 skge_write32(hw, B2_GP_IO, r);
0781191c 1590
64f6b64d
SH		 1591 /* Enable GMII interface */
1592 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1593 }
89bf5f23 1594
89bf5f23 1595
64f6b64d
SH		 1596 switch(hw->phy_type) {
1597 case SK_PHY_XMAC:
1598 xm_phy_init(skge);
1599 break;
1600 case SK_PHY_BCOM:
1601 bcom_phy_init(skge);
1602 bcom_check_link(hw, port);
1603 }
89bf5f23 1604
45bada65
SH		 1605 /* Set Station Address */
1606 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1607
45bada65
SH		 1608 /* We don't use match addresses so clear */
1609 for (i = 1; i < 16; i++)
1610 xm_outaddr(hw, port, XM_EXM(i), zero);
1611
0781191c
SH		 1612 /* Clear MIB counters */
1613 xm_write16(hw, port, XM_STAT_CMD,
1614 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1615 /* Clear two times according to Errata #3 */
1616 xm_write16(hw, port, XM_STAT_CMD,
1617 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1618
45bada65
SH		 1619 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1620 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1621
1622 /* We don't need the FCS appended to the packet. */
1623 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1624 if (jumbo)
1625 r |= XM_RX_BIG_PK_OK;
89bf5f23 1626
45bada65 1627 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1628 /*
45bada65
SH		 1629 * If in manual half duplex mode the other side might be in
1630 * full duplex mode, so ignore if a carrier extension is not seen
1631 * on frames received
89bf5f23 1632 */
45bada65 1633 r |= XM_RX_DIS_CEXT;
baef58b1 1634 }
45bada65 1635 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1636
baef58b1
SH		 1637
1638 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1639 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1640
1641 /*
1642 * Bump up the transmit threshold. This helps hold off transmit
1643 * underruns when we're blasting traffic from both ports at once.
1644 */
1645 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1646
1647 /*
1648 * Enable the reception of all error frames. This is is
1649 * a necessary evil due to the design of the XMAC. The
1650 * XMAC's receive FIFO is only 8K in size, however jumbo
1651 * frames can be up to 9000 bytes in length. When bad
1652 * frame filtering is enabled, the XMAC's RX FIFO operates
1653 * in 'store and forward' mode. For this to work, the
1654 * entire frame has to fit into the FIFO, but that means
1655 * that jumbo frames larger than 8192 bytes will be
1656 * truncated. Disabling all bad frame filtering causes
1657 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1658 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1659 * RX FIFO as soon as the FIFO threshold is reached.
1660 */
45bada65 1661 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1662
baef58b1
SH		 1663
1664 /*
45bada65
SH		 1665 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1666 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1667 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1668 */
45bada65
SH		 1669 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1670
1671 /*
1672 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1673 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1674 * and 'Octets Tx OK Hi Cnt Ov'.
1675 */
1676 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1677
1678 /* Configure MAC arbiter */
1679 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1680
1681 /* configure timeout values */
1682 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1683 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1684 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1685 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1686
1687 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1688 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1689 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1690 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1691
1692 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1693 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1694 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1695 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1696
1697 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1698 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1699 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1700 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1701
45bada65 1702 if (jumbo) {
baef58b1 1703 /* Enable frame flushing if jumbo frames used */
6b0c1480 1704 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1705 } else {
1706 /* enable timeout timers if normal frames */
1707 skge_write16(hw, B3_PA_CTRL,
45bada65 1708 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1709 }
baef58b1
SH		 1710}
1711
1712static void genesis_stop(struct skge_port *skge)
1713{
1714 struct skge_hw *hw = skge->hw;
1715 int port = skge->port;
89bf5f23 1716 u32 reg;
baef58b1 1717
46a60f2d
SH		 1718 genesis_reset(hw, port);
1719
baef58b1
SH		 1720 /* Clear Tx packet arbiter timeout IRQ */
1721 skge_write16(hw, B3_PA_CTRL,
1722 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1723
1724 /*
8f3f8193 1725 * If the transfer sticks at the MAC the STOP command will not
baef58b1
SH		 1726 * terminate if we don't flush the XMAC's transmit FIFO !
1727 */
6b0c1480
SH		 1728 xm_write32(hw, port, XM_MODE,
1729 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1730
1731
1732 /* Reset the MAC */
6b0c1480 1733 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1734
1735 /* For external PHYs there must be special handling */
64f6b64d
SH		 1736 if (hw->phy_type != SK_PHY_XMAC) {
1737 reg = skge_read32(hw, B2_GP_IO);
1738 if (port == 0) {
1739 reg |= GP_DIR_0;
1740 reg &= ~GP_IO_0;
1741 } else {
1742 reg |= GP_DIR_2;
1743 reg &= ~GP_IO_2;
1744 }
1745 skge_write32(hw, B2_GP_IO, reg);
1746 skge_read32(hw, B2_GP_IO);
baef58b1
SH		 1747 }
1748
6b0c1480
SH		 1749 xm_write16(hw, port, XM_MMU_CMD,
1750 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1751 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1752
6b0c1480 1753 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1754}
1755
1756
1757static void genesis_get_stats(struct skge_port *skge, u64 *data)
1758{
1759 struct skge_hw *hw = skge->hw;
1760 int port = skge->port;
1761 int i;
1762 unsigned long timeout = jiffies + HZ;
1763
6b0c1480 1764 xm_write16(hw, port,
baef58b1
SH		 1765 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1766
1767 /* wait for update to complete */
6b0c1480 1768 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1769 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1770 if (time_after(jiffies, timeout))
1771 break;
1772 udelay(10);
1773 }
1774
1775 /* special case for 64 bit octet counter */
6b0c1480
SH		 1776 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1777 | xm_read32(hw, port, XM_TXO_OK_LO);
1778 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1779 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1780
1781 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1782 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1783}
1784
1785static void genesis_mac_intr(struct skge_hw *hw, int port)
1786{
da00772f
SH		 1787 struct net_device *dev = hw->dev[port];
1788 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1789 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1790
7e676d91
SH		 1791 if (netif_msg_intr(skge))
1792 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
da00772f 1793 dev->name, status);
baef58b1 1794
501fb72d
SH		 1795 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1796 xm_link_down(hw, port);
1797 mod_timer(&skge->link_timer, jiffies + 1);
1798 }
a1bc9b87 1799
baef58b1 1800 if (status & XM_IS_TXF_UR) {
6b0c1480 1801 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
da00772f 1802 ++dev->stats.tx_fifo_errors;
baef58b1 1803 }
501fb72d 1804
baef58b1 1805 if (status & XM_IS_RXF_OV) {
6b0c1480 1806 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
da00772f 1807 ++dev->stats.rx_fifo_errors;
baef58b1
SH		 1808 }
1809}
1810
baef58b1
SH		 1811static void genesis_link_up(struct skge_port *skge)
1812{
1813 struct skge_hw *hw = skge->hw;
1814 int port = skge->port;
a1bc9b87 1815 u16 cmd, msk;
64f6b64d 1816 u32 mode;
baef58b1 1817
6b0c1480 1818 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1819
1820 /*
1821 * enabling pause frame reception is required for 1000BT
1822 * because the XMAC is not reset if the link is going down
1823 */
5d5c8e03
SH		 1824 if (skge->flow_status == FLOW_STAT_NONE ||
1825 skge->flow_status == FLOW_STAT_LOC_SEND)
7e676d91 1826 /* Disable Pause Frame Reception */
baef58b1
SH		 1827 cmd |= XM_MMU_IGN_PF;
1828 else
1829 /* Enable Pause Frame Reception */
1830 cmd &= ~XM_MMU_IGN_PF;
1831
6b0c1480 1832 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1833
6b0c1480 1834 mode = xm_read32(hw, port, XM_MODE);
5d5c8e03
SH		 1835 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1836 skge->flow_status == FLOW_STAT_LOC_SEND) {
baef58b1
SH		 1837 /*
1838 * Configure Pause Frame Generation
1839 * Use internal and external Pause Frame Generation.
1840 * Sending pause frames is edge triggered.
1841 * Send a Pause frame with the maximum pause time if
1842 * internal oder external FIFO full condition occurs.
1843 * Send a zero pause time frame to re-start transmission.
1844 */
1845 /* XM_PAUSE_DA = '010000C28001' (default) */
1846 /* XM_MAC_PTIME = 0xffff (maximum) */
1847 /* remember this value is defined in big endian (!) */
6b0c1480 1848 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1849
1850 mode |= XM_PAUSE_MODE;
6b0c1480 1851 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1852 } else {
1853 /*
1854 * disable pause frame generation is required for 1000BT
1855 * because the XMAC is not reset if the link is going down
1856 */
1857 /* Disable Pause Mode in Mode Register */
1858 mode &= ~XM_PAUSE_MODE;
1859
6b0c1480 1860 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1861 }
1862
6b0c1480 1863 xm_write32(hw, port, XM_MODE, mode);
a1bc9b87 1864
501fb72d
SH		 1865 /* Turn on detection of Tx underrun, Rx overrun */
1866 msk = xm_read16(hw, port, XM_IMSK);
1867 msk &= ~(XM_IS_RXF_OV | XM_IS_TXF_UR);
a1bc9b87 1868 xm_write16(hw, port, XM_IMSK, msk);
501fb72d 1869
6b0c1480 1870 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1871
1872 /* get MMU Command Reg. */
6b0c1480 1873 cmd = xm_read16(hw, port, XM_MMU_CMD);
64f6b64d 1874 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1875 cmd |= XM_MMU_GMII_FD;
1876
89bf5f23
SH		 1877 /*
1878 * Workaround BCOM Errata (#10523) for all BCom Phys
1879 * Enable Power Management after link up
1880 */
64f6b64d
SH		 1881 if (hw->phy_type == SK_PHY_BCOM) {
1882 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1883 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1884 & ~PHY_B_AC_DIS_PM);
1885 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1886 }
baef58b1
SH		 1887
1888 /* enable Rx/Tx */
6b0c1480 1889 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1890 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1891 skge_link_up(skge);
1892}
1893
1894
45bada65 1895static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1896{
1897 struct skge_hw *hw = skge->hw;
1898 int port = skge->port;
45bada65
SH		 1899 u16 isrc;
1900
1901 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1902 if (netif_msg_intr(skge))
1903 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1904 skge->netdev->name, isrc);
baef58b1 1905
45bada65
SH		 1906 if (isrc & PHY_B_IS_PSE)
1907 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1908 hw->dev[port]->name);
baef58b1
SH		 1909
1910 /* Workaround BCom Errata:
1911 * enable and disable loopback mode if "NO HCD" occurs.
1912 */
45bada65 1913 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1914 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1915 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1916 ctrl | PHY_CT_LOOP);
6b0c1480 1917 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1918 ctrl & ~PHY_CT_LOOP);
1919 }
1920
45bada65
SH		 1921 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1922 bcom_check_link(hw, port);
baef58b1 1923
baef58b1
SH		 1924}
1925
2cd8e5d3
SH		 1926static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1927{
1928 int i;
1929
1930 gma_write16(hw, port, GM_SMI_DATA, val);
1931 gma_write16(hw, port, GM_SMI_CTRL,
1932 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1933 for (i = 0; i < PHY_RETRIES; i++) {
1934 udelay(1);
1935
1936 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1937 return 0;
1938 }
1939
1940 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1941 hw->dev[port]->name);
1942 return -EIO;
1943}
1944
1945static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1946{
1947 int i;
1948
1949 gma_write16(hw, port, GM_SMI_CTRL,
1950 GM_SMI_CT_PHY_AD(hw->phy_addr)
1951 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1952
1953 for (i = 0; i < PHY_RETRIES; i++) {
1954 udelay(1);
1955 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1956 goto ready;
1957 }
1958
1959 return -ETIMEDOUT;
1960 ready:
1961 *val = gma_read16(hw, port, GM_SMI_DATA);
1962 return 0;
1963}
1964
1965static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1966{
1967 u16 v = 0;
1968 if (__gm_phy_read(hw, port, reg, &v))
1969 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1970 hw->dev[port]->name);
1971 return v;
1972}
1973
8f3f8193 1974/* Marvell Phy Initialization */
baef58b1
SH		 1975static void yukon_init(struct skge_hw *hw, int port)
1976{
1977 struct skge_port *skge = netdev_priv(hw->dev[port]);
1978 u16 ctrl, ct1000, adv;
baef58b1 1979
baef58b1 1980 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1981 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1982
1983 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1984 PHY_M_EC_MAC_S_MSK);
1985 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1986
c506a509 1987 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1988
6b0c1480 1989 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1990 }
1991
6b0c1480 1992 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1993 if (skge->autoneg == AUTONEG_DISABLE)
1994 ctrl &= ~PHY_CT_ANE;
1995
1996 ctrl |= PHY_CT_RESET;
6b0c1480 1997 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1998
1999 ctrl = 0;
2000 ct1000 = 0;
b18f2091 2001 adv = PHY_AN_CSMA;
baef58b1
SH		 2002
2003 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 2004 if (hw->copper) {
baef58b1
SH		 2005 if (skge->advertising & ADVERTISED_1000baseT_Full)
2006 ct1000 |= PHY_M_1000C_AFD;
2007 if (skge->advertising & ADVERTISED_1000baseT_Half)
2008 ct1000 |= PHY_M_1000C_AHD;
2009 if (skge->advertising & ADVERTISED_100baseT_Full)
2010 adv |= PHY_M_AN_100_FD;
2011 if (skge->advertising & ADVERTISED_100baseT_Half)
2012 adv |= PHY_M_AN_100_HD;
2013 if (skge->advertising & ADVERTISED_10baseT_Full)
2014 adv |= PHY_M_AN_10_FD;
2015 if (skge->advertising & ADVERTISED_10baseT_Half)
2016 adv |= PHY_M_AN_10_HD;
baef58b1 2017
4b67be99
SH		 2018 /* Set Flow-control capabilities */
2019 adv |= phy_pause_map[skge->flow_control];
2020 } else {
2021 if (skge->advertising & ADVERTISED_1000baseT_Full)
2022 adv |= PHY_M_AN_1000X_AFD;
2023 if (skge->advertising & ADVERTISED_1000baseT_Half)
2024 adv |= PHY_M_AN_1000X_AHD;
2025
2026 adv |= fiber_pause_map[skge->flow_control];
2027 }
45bada65 2028
baef58b1
SH		 2029 /* Restart Auto-negotiation */
2030 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2031 } else {
2032 /* forced speed/duplex settings */
2033 ct1000 = PHY_M_1000C_MSE;
2034
2035 if (skge->duplex == DUPLEX_FULL)
2036 ctrl |= PHY_CT_DUP_MD;
2037
2038 switch (skge->speed) {
2039 case SPEED_1000:
2040 ctrl |= PHY_CT_SP1000;
2041 break;
2042 case SPEED_100:
2043 ctrl |= PHY_CT_SP100;
2044 break;
2045 }
2046
2047 ctrl |= PHY_CT_RESET;
2048 }
2049
c506a509 2050 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 2051
6b0c1480
SH		 2052 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2053 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 2054
baef58b1
SH		 2055 /* Enable phy interrupt on autonegotiation complete (or link up) */
2056 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 2057 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 2058 else
4cde06ed 2059 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2060}
2061
2062static void yukon_reset(struct skge_hw *hw, int port)
2063{
6b0c1480
SH		 2064 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2065 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2066 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2067 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2068 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 2069
6b0c1480
SH		 2070 gma_write16(hw, port, GM_RX_CTRL,
2071 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 2072 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2073}
2074
c8868611
SH		 2075/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2076static int is_yukon_lite_a0(struct skge_hw *hw)
2077{
2078 u32 reg;
2079 int ret;
2080
2081 if (hw->chip_id != CHIP_ID_YUKON)
2082 return 0;
2083
2084 reg = skge_read32(hw, B2_FAR);
2085 skge_write8(hw, B2_FAR + 3, 0xff);
2086 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2087 skge_write32(hw, B2_FAR, reg);
2088 return ret;
2089}
2090
baef58b1
SH		 2091static void yukon_mac_init(struct skge_hw *hw, int port)
2092{
2093 struct skge_port *skge = netdev_priv(hw->dev[port]);
2094 int i;
2095 u32 reg;
2096 const u8 *addr = hw->dev[port]->dev_addr;
2097
2098 /* WA code for COMA mode -- set PHY reset */
2099 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2100 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2101 reg = skge_read32(hw, B2_GP_IO);
2102 reg |= GP_DIR_9 | GP_IO_9;
2103 skge_write32(hw, B2_GP_IO, reg);
2104 }
baef58b1
SH		 2105
2106 /* hard reset */
6b0c1480
SH		 2107 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2108 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2109
2110 /* WA code for COMA mode -- clear PHY reset */
2111 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2112 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2113 reg = skge_read32(hw, B2_GP_IO);
2114 reg |= GP_DIR_9;
2115 reg &= ~GP_IO_9;
2116 skge_write32(hw, B2_GP_IO, reg);
2117 }
baef58b1
SH		 2118
2119 /* Set hardware config mode */
2120 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2121 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 2122 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 2123
2124 /* Clear GMC reset */
6b0c1480
SH		 2125 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2126 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2127 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 2128
baef58b1
SH		 2129 if (skge->autoneg == AUTONEG_DISABLE) {
2130 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 2131 gma_write16(hw, port, GM_GP_CTRL,
2132 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 2133
2134 switch (skge->speed) {
2135 case SPEED_1000:
564f9abb 2136 reg &= ~GM_GPCR_SPEED_100;
baef58b1 2137 reg |= GM_GPCR_SPEED_1000;
564f9abb 2138 break;
baef58b1 2139 case SPEED_100:
564f9abb 2140 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 2141 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 2142 break;
2143 case SPEED_10:
2144 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2145 break;
baef58b1
SH		 2146 }
2147
2148 if (skge->duplex == DUPLEX_FULL)
2149 reg |= GM_GPCR_DUP_FULL;
2150 } else
2151 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 2152
baef58b1
SH		 2153 switch (skge->flow_control) {
2154 case FLOW_MODE_NONE:
6b0c1480 2155 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 2156 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2157 break;
2158 case FLOW_MODE_LOC_SEND:
2159 /* disable Rx flow-control */
2160 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
5d5c8e03
SH		 2161 break;
2162 case FLOW_MODE_SYMMETRIC:
2163 case FLOW_MODE_SYM_OR_REM:
2164 /* enable Tx & Rx flow-control */
2165 break;
baef58b1
SH		 2166 }
2167
6b0c1480 2168 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 2169 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2170
baef58b1 2171 yukon_init(hw, port);
baef58b1
SH		 2172
2173 /* MIB clear */
6b0c1480
SH		 2174 reg = gma_read16(hw, port, GM_PHY_ADDR);
2175 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 2176
2177 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 2178 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2179 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 2180
2181 /* transmit control */
6b0c1480 2182 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 2183
2184 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 2185 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 2186 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2187
2188 /* transmit flow control */
6b0c1480 2189 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 2190
2191 /* transmit parameter */
6b0c1480 2192 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 2193 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2194 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2195 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2196
2197 /* serial mode register */
2198 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2199 if (hw->dev[port]->mtu > 1500)
2200 reg |= GM_SMOD_JUMBO_ENA;
2201
6b0c1480 2202 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 2203
2204 /* physical address: used for pause frames */
6b0c1480 2205 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 2206 /* virtual address for data */
6b0c1480 2207 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 2208
2209 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 2210 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2211 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2212 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 2213
2214 /* Initialize Mac Fifo */
2215
2216 /* Configure Rx MAC FIFO */
6b0c1480 2217 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 2218 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 2219
2220 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2221 if (is_yukon_lite_a0(hw))
baef58b1 2222 reg &= ~GMF_RX_F_FL_ON;
c8868611 2223
6b0c1480
SH		 2224 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2225 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 2226 /*
2227 * because Pause Packet Truncation in GMAC is not working
2228 * we have to increase the Flush Threshold to 64 bytes
2229 * in order to flush pause packets in Rx FIFO on Yukon-1
2230 */
2231 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 2232
2233 /* Configure Tx MAC FIFO */
6b0c1480
SH		 2234 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2235 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 2236}
2237
355ec572
SH		 2238/* Go into power down mode */
2239static void yukon_suspend(struct skge_hw *hw, int port)
2240{
2241 u16 ctrl;
2242
2243 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2244 ctrl |= PHY_M_PC_POL_R_DIS;
2245 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2246
2247 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2248 ctrl |= PHY_CT_RESET;
2249 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2250
2251 /* switch IEEE compatible power down mode on */
2252 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2253 ctrl |= PHY_CT_PDOWN;
2254 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2255}
2256
baef58b1
SH		 2257static void yukon_stop(struct skge_port *skge)
2258{
2259 struct skge_hw *hw = skge->hw;
2260 int port = skge->port;
2261
46a60f2d
SH		 2262 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2263 yukon_reset(hw, port);
baef58b1 2264
6b0c1480
SH		 2265 gma_write16(hw, port, GM_GP_CTRL,
2266 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 2267 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 2268 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 2269
355ec572 2270 yukon_suspend(hw, port);
46a60f2d 2271
baef58b1 2272 /* set GPHY Control reset */
46a60f2d
SH		 2273 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2274 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2275}
2276
2277static void yukon_get_stats(struct skge_port *skge, u64 *data)
2278{
2279 struct skge_hw *hw = skge->hw;
2280 int port = skge->port;
2281 int i;
2282
6b0c1480
SH		 2283 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2284 | gma_read32(hw, port, GM_TXO_OK_LO);
2285 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2286 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 2287
2288 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 2289 data[i] = gma_read32(hw, port,
baef58b1
SH		 2290 skge_stats[i].gma_offset);
2291}
2292
2293static void yukon_mac_intr(struct skge_hw *hw, int port)
2294{
7e676d91
SH		 2295 struct net_device *dev = hw->dev[port];
2296 struct skge_port *skge = netdev_priv(dev);
6b0c1480 2297 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2298
7e676d91
SH		 2299 if (netif_msg_intr(skge))
2300 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2301 dev->name, status);
2302
baef58b1 2303 if (status & GM_IS_RX_FF_OR) {
da00772f 2304 ++dev->stats.rx_fifo_errors;
d8a09943 2305 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 2306 }
d8a09943 2307
baef58b1 2308 if (status & GM_IS_TX_FF_UR) {
da00772f 2309 ++dev->stats.tx_fifo_errors;
d8a09943 2310 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 2311 }
2312
2313}
2314
2315static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2316{
95566065 2317 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 2318 case PHY_M_PS_SPEED_1000:
2319 return SPEED_1000;
2320 case PHY_M_PS_SPEED_100:
2321 return SPEED_100;
2322 default:
2323 return SPEED_10;
2324 }
2325}
2326
2327static void yukon_link_up(struct skge_port *skge)
2328{
2329 struct skge_hw *hw = skge->hw;
2330 int port = skge->port;
2331 u16 reg;
2332
baef58b1 2333 /* Enable Transmit FIFO Underrun */
46a60f2d 2334 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 2335
6b0c1480 2336 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 2337 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2338 reg |= GM_GPCR_DUP_FULL;
2339
2340 /* enable Rx/Tx */
2341 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 2342 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 2343
4cde06ed 2344 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2345 skge_link_up(skge);
2346}
2347
2348static void yukon_link_down(struct skge_port *skge)
2349{
2350 struct skge_hw *hw = skge->hw;
2351 int port = skge->port;
d8a09943 2352 u16 ctrl;
baef58b1 2353
d8a09943
SH		 2354 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2355 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2356 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 2357
5d5c8e03
SH		 2358 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2359 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2360 ctrl |= PHY_M_AN_ASP;
baef58b1 2361 /* restore Asymmetric Pause bit */
5d5c8e03 2362 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
baef58b1
SH		 2363 }
2364
baef58b1
SH		 2365 skge_link_down(skge);
2366
2367 yukon_init(hw, port);
2368}
2369
2370static void yukon_phy_intr(struct skge_port *skge)
2371{
2372 struct skge_hw *hw = skge->hw;
2373 int port = skge->port;
2374 const char *reason = NULL;
2375 u16 istatus, phystat;
2376
6b0c1480
SH		 2377 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2378 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 2379
2380 if (netif_msg_intr(skge))
2381 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2382 skge->netdev->name, istatus, phystat);
baef58b1
SH		 2383
2384 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2385 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2386 & PHY_M_AN_RF) {
2387 reason = "remote fault";
2388 goto failed;
2389 }
2390
c506a509 2391 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 2392 reason = "master/slave fault";
2393 goto failed;
2394 }
2395
2396 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2397 reason = "speed/duplex";
2398 goto failed;
2399 }
2400
2401 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2402 ? DUPLEX_FULL : DUPLEX_HALF;
2403 skge->speed = yukon_speed(hw, phystat);
2404
baef58b1
SH		 2405 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2406 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2407 case PHY_M_PS_PAUSE_MSK:
5d5c8e03 2408 skge->flow_status = FLOW_STAT_SYMMETRIC;
baef58b1
SH		 2409 break;
2410 case PHY_M_PS_RX_P_EN:
5d5c8e03 2411 skge->flow_status = FLOW_STAT_REM_SEND;
baef58b1
SH		 2412 break;
2413 case PHY_M_PS_TX_P_EN:
5d5c8e03 2414 skge->flow_status = FLOW_STAT_LOC_SEND;
baef58b1
SH		 2415 break;
2416 default:
5d5c8e03 2417 skge->flow_status = FLOW_STAT_NONE;
baef58b1
SH		 2418 }
2419
5d5c8e03 2420 if (skge->flow_status == FLOW_STAT_NONE ||
baef58b1 2421 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2422 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2423 else
6b0c1480 2424 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2425 yukon_link_up(skge);
2426 return;
2427 }
2428
2429 if (istatus & PHY_M_IS_LSP_CHANGE)
2430 skge->speed = yukon_speed(hw, phystat);
2431
2432 if (istatus & PHY_M_IS_DUP_CHANGE)
2433 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2434 if (istatus & PHY_M_IS_LST_CHANGE) {
2435 if (phystat & PHY_M_PS_LINK_UP)
2436 yukon_link_up(skge);
2437 else
2438 yukon_link_down(skge);
2439 }
2440 return;
2441 failed:
2442 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2443 skge->netdev->name, reason);
2444
2445 /* XXX restart autonegotiation? */
2446}
2447
ee294dcd
SH		 2448static void skge_phy_reset(struct skge_port *skge)
2449{
2450 struct skge_hw *hw = skge->hw;
2451 int port = skge->port;
aae343d4 2452 struct net_device *dev = hw->dev[port];
ee294dcd
SH		 2453
2454 netif_stop_queue(skge->netdev);
2455 netif_carrier_off(skge->netdev);
2456
9cbe330f 2457 spin_lock_bh(&hw->phy_lock);
ee294dcd
SH		 2458 if (hw->chip_id == CHIP_ID_GENESIS) {
2459 genesis_reset(hw, port);
2460 genesis_mac_init(hw, port);
2461 } else {
2462 yukon_reset(hw, port);
2463 yukon_init(hw, port);
2464 }
9cbe330f 2465 spin_unlock_bh(&hw->phy_lock);
75814090
SH		 2466
2467 dev->set_multicast_list(dev);
ee294dcd
SH		 2468}
2469
2cd8e5d3
SH		 2470/* Basic MII support */
2471static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2472{
2473 struct mii_ioctl_data *data = if_mii(ifr);
2474 struct skge_port *skge = netdev_priv(dev);
2475 struct skge_hw *hw = skge->hw;
2476 int err = -EOPNOTSUPP;
2477
2478 if (!netif_running(dev))
2479 return -ENODEV; /* Phy still in reset */
2480
2481 switch(cmd) {
2482 case SIOCGMIIPHY:
2483 data->phy_id = hw->phy_addr;
2484
2485 /* fallthru */
2486 case SIOCGMIIREG: {
2487 u16 val = 0;
9cbe330f 2488 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2489 if (hw->chip_id == CHIP_ID_GENESIS)
2490 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2491 else
2492 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
9cbe330f 2493 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2494 data->val_out = val;
2495 break;
2496 }
2497
2498 case SIOCSMIIREG:
2499 if (!capable(CAP_NET_ADMIN))
2500 return -EPERM;
2501
9cbe330f 2502 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2503 if (hw->chip_id == CHIP_ID_GENESIS)
2504 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2505 data->val_in);
2506 else
2507 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2508 data->val_in);
9cbe330f 2509 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2510 break;
2511 }
2512 return err;
2513}
2514
279e1dab 2515static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
baef58b1
SH		 2516{
2517 u32 end;
2518
279e1dab
LT		 2519 start /= 8;
2520 len /= 8;
2521 end = start + len - 1;
baef58b1
SH		 2522
2523 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2524 skge_write32(hw, RB_ADDR(q, RB_START), start);
2525 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2526 skge_write32(hw, RB_ADDR(q, RB_RP), start);
279e1dab 2527 skge_write32(hw, RB_ADDR(q, RB_END), end);
baef58b1
SH		 2528
2529 if (q == Q_R1 || q == Q_R2) {
2530 /* Set thresholds on receive queue's */
279e1dab
LT		 2531 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2532 start + (2*len)/3);
2533 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2534 start + (len/3));
2535 } else {
2536 /* Enable store & forward on Tx queue's because
2537 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2538 */
baef58b1 2539 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
279e1dab 2540 }
baef58b1
SH		 2541
2542 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2543}
2544
2545/* Setup Bus Memory Interface */
2546static void skge_qset(struct skge_port *skge, u16 q,
2547 const struct skge_element *e)
2548{
2549 struct skge_hw *hw = skge->hw;
2550 u32 watermark = 0x600;
2551 u64 base = skge->dma + (e->desc - skge->mem);
2552
2553 /* optimization to reduce window on 32bit/33mhz */
2554 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2555 watermark /= 2;
2556
2557 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2558 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2559 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2560 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2561}
2562
2563static int skge_up(struct net_device *dev)
2564{
2565 struct skge_port *skge = netdev_priv(dev);
2566 struct skge_hw *hw = skge->hw;
2567 int port = skge->port;
279e1dab 2568 u32 chunk, ram_addr;
baef58b1
SH		 2569 size_t rx_size, tx_size;
2570 int err;
2571
fae87592
SH		 2572 if (!is_valid_ether_addr(dev->dev_addr))
2573 return -EINVAL;
2574
baef58b1
SH		 2575 if (netif_msg_ifup(skge))
2576 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2577
19a33d4e 2578 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2579 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2580 else
2581 skge->rx_buf_size = RX_BUF_SIZE;
2582
2583
baef58b1
SH		 2584 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2585 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2586 skge->mem_size = tx_size + rx_size;
2587 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2588 if (!skge->mem)
2589 return -ENOMEM;
2590
c3da1447
SH		 2591 BUG_ON(skge->dma & 7);
2592
2593 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
1479d13c 2594 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
c3da1447
SH		 2595 err = -EINVAL;
2596 goto free_pci_mem;
2597 }
2598
baef58b1
SH		 2599 memset(skge->mem, 0, skge->mem_size);
2600
203babb6
SH		 2601 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2602 if (err)
baef58b1
SH		 2603 goto free_pci_mem;
2604
c54f9765 2605 err = skge_rx_fill(dev);
19a33d4e 2606 if (err)
baef58b1
SH		 2607 goto free_rx_ring;
2608
203babb6
SH		 2609 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2610 skge->dma + rx_size);
2611 if (err)
baef58b1
SH		 2612 goto free_rx_ring;
2613
8f3f8193 2614 /* Initialize MAC */
9cbe330f 2615 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2616 if (hw->chip_id == CHIP_ID_GENESIS)
2617 genesis_mac_init(hw, port);
2618 else
2619 yukon_mac_init(hw, port);
9cbe330f 2620 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 2621
2622 /* Configure RAMbuffers */
279e1dab
LT		 2623 chunk = hw->ram_size / ((hw->ports + 1)*2);
2624 ram_addr = hw->ram_offset + 2 * chunk * port;
baef58b1 2625
279e1dab 2626 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
7fb7ac24 2627 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
279e1dab 2628
baef58b1 2629 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
279e1dab 2630 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
baef58b1
SH		 2631 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2632
2633 /* Start receiver BMU */
2634 wmb();
2635 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2636 skge_led(skge, LED_MODE_ON);
baef58b1 2637
4ebabfcb
SH		 2638 spin_lock_irq(&hw->hw_lock);
2639 hw->intr_mask |= portmask[port];
2640 skge_write32(hw, B0_IMSK, hw->intr_mask);
2641 spin_unlock_irq(&hw->hw_lock);
2642
bea3348e 2643 napi_enable(&skge->napi);
baef58b1
SH		 2644 return 0;
2645
2646 free_rx_ring:
2647 skge_rx_clean(skge);
2648 kfree(skge->rx_ring.start);
2649 free_pci_mem:
2650 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2651 skge->mem = NULL;
baef58b1
SH		 2652
2653 return err;
2654}
2655
60b24b51
SH		 2656/* stop receiver */
2657static void skge_rx_stop(struct skge_hw *hw, int port)
2658{
2659 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2660 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2661 RB_RST_SET|RB_DIS_OP_MD);
2662 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2663}
2664
baef58b1
SH		 2665static int skge_down(struct net_device *dev)
2666{
2667 struct skge_port *skge = netdev_priv(dev);
2668 struct skge_hw *hw = skge->hw;
2669 int port = skge->port;
2670
7731a4ea
SH		 2671 if (skge->mem == NULL)
2672 return 0;
2673
baef58b1
SH		 2674 if (netif_msg_ifdown(skge))
2675 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2676
2677 netif_stop_queue(dev);
692412b3 2678
64f6b64d 2679 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
9cbe330f 2680 del_timer_sync(&skge->link_timer);
baef58b1 2681
bea3348e 2682 napi_disable(&skge->napi);
692412b3 2683 netif_carrier_off(dev);
4ebabfcb
SH		 2684
2685 spin_lock_irq(&hw->hw_lock);
2686 hw->intr_mask &= ~portmask[port];
2687 skge_write32(hw, B0_IMSK, hw->intr_mask);
2688 spin_unlock_irq(&hw->hw_lock);
2689
46a60f2d
SH		 2690 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2691 if (hw->chip_id == CHIP_ID_GENESIS)
2692 genesis_stop(skge);
2693 else
2694 yukon_stop(skge);
2695
baef58b1
SH		 2696 /* Stop transmitter */
2697 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2698 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2699 RB_RST_SET|RB_DIS_OP_MD);
2700
baef58b1
SH		 2701
2702 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2703 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2704 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2705
2706 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2707 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2708 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2709
2710 /* Reset PCI FIFO */
2711 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2712 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2713
2714 /* Reset the RAM Buffer async Tx queue */
2715 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
60b24b51
SH		 2716
2717 skge_rx_stop(hw, port);
baef58b1
SH		 2718
2719 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2720 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2721 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2722 } else {
6b0c1480
SH		 2723 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2724 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2725 }
2726
6abebb53 2727 skge_led(skge, LED_MODE_OFF);
baef58b1 2728
e3a1b99f 2729 netif_tx_lock_bh(dev);
513f533e 2730 skge_tx_clean(dev);
e3a1b99f
SH		 2731 netif_tx_unlock_bh(dev);
2732
baef58b1
SH		 2733 skge_rx_clean(skge);
2734
2735 kfree(skge->rx_ring.start);
2736 kfree(skge->tx_ring.start);
2737 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2738 skge->mem = NULL;
baef58b1
SH		 2739 return 0;
2740}
2741
29b4e886
SH		 2742static inline int skge_avail(const struct skge_ring *ring)
2743{
992c9623 2744 smp_mb();
29b4e886
SH		 2745 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2746 + (ring->to_clean - ring->to_use) - 1;
2747}
2748
baef58b1
SH		 2749static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2750{
2751 struct skge_port *skge = netdev_priv(dev);
2752 struct skge_hw *hw = skge->hw;
baef58b1
SH		 2753 struct skge_element *e;
2754 struct skge_tx_desc *td;
2755 int i;
2756 u32 control, len;
2757 u64 map;
baef58b1 2758
5b057c6b 2759 if (skb_padto(skb, ETH_ZLEN))
baef58b1
SH		 2760 return NETDEV_TX_OK;
2761
513f533e 2762 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
baef58b1 2763 return NETDEV_TX_BUSY;
baef58b1 2764
7c442fa1 2765 e = skge->tx_ring.to_use;
baef58b1 2766 td = e->desc;
7c442fa1 2767 BUG_ON(td->control & BMU_OWN);
baef58b1
SH		 2768 e->skb = skb;
2769 len = skb_headlen(skb);
2770 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2771 pci_unmap_addr_set(e, mapaddr, map);
2772 pci_unmap_len_set(e, maplen, len);
2773
2774 td->dma_lo = map;
2775 td->dma_hi = map >> 32;
2776
84fa7933 2777 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d 2778 const int offset = skb_transport_offset(skb);
baef58b1
SH		 2779
2780 /* This seems backwards, but it is what the sk98lin
2781 * does. Looks like hardware is wrong?
2782 */
b0061ce4 2783 if (ipip_hdr(skb)->protocol == IPPROTO_UDP
981d0377 2784 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2785 control = BMU_TCP_CHECK;
2786 else
2787 control = BMU_UDP_CHECK;
2788
2789 td->csum_offs = 0;
2790 td->csum_start = offset;
ff1dcadb 2791 td->csum_write = offset + skb->csum_offset;
baef58b1
SH		 2792 } else
2793 control = BMU_CHECK;
2794
2795 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2796 control |= BMU_EOF| BMU_IRQ_EOF;
2797 else {
2798 struct skge_tx_desc *tf = td;
2799
2800 control |= BMU_STFWD;
2801 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2802 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2803
2804 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2805 frag->size, PCI_DMA_TODEVICE);
2806
2807 e = e->next;
7c442fa1 2808 e->skb = skb;
baef58b1 2809 tf = e->desc;
7c442fa1
SH		 2810 BUG_ON(tf->control & BMU_OWN);
2811
baef58b1
SH		 2812 tf->dma_lo = map;
2813 tf->dma_hi = (u64) map >> 32;
2814 pci_unmap_addr_set(e, mapaddr, map);
2815 pci_unmap_len_set(e, maplen, frag->size);
2816
2817 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2818 }
2819 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2820 }
2821 /* Make sure all the descriptors written */
2822 wmb();
2823 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2824 wmb();
2825
2826 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2827
7c442fa1 2828 if (unlikely(netif_msg_tx_queued(skge)))
0b2d7fea 2829 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
7c442fa1 2830 dev->name, e - skge->tx_ring.start, skb->len);
baef58b1 2831
7c442fa1 2832 skge->tx_ring.to_use = e->next;
992c9623
SH		 2833 smp_wmb();
2834
9db96479 2835 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
baef58b1
SH		 2836 pr_debug("%s: transmit queue full\n", dev->name);
2837 netif_stop_queue(dev);
2838 }
2839
c68ce71a
SH		 2840 dev->trans_start = jiffies;
2841
baef58b1
SH		 2842 return NETDEV_TX_OK;
2843}
2844
7c442fa1
SH		 2845
2846/* Free resources associated with this reing element */
2847static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2848 u32 control)
866b4f3e
SH		 2849{
2850 struct pci_dev *pdev = skge->hw->pdev;
866b4f3e 2851
7c442fa1
SH		 2852 /* skb header vs. fragment */
2853 if (control & BMU_STF)
866b4f3e 2854 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
7c442fa1
SH		 2855 pci_unmap_len(e, maplen),
2856 PCI_DMA_TODEVICE);
2857 else
2858 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2859 pci_unmap_len(e, maplen),
2860 PCI_DMA_TODEVICE);
866b4f3e 2861
7c442fa1
SH		 2862 if (control & BMU_EOF) {
2863 if (unlikely(netif_msg_tx_done(skge)))
2864 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2865 skge->netdev->name, e - skge->tx_ring.start);
866b4f3e 2866
513f533e 2867 dev_kfree_skb(e->skb);
baef58b1
SH		 2868 }
2869}
2870
7c442fa1 2871/* Free all buffers in transmit ring */
513f533e 2872static void skge_tx_clean(struct net_device *dev)
baef58b1 2873{
513f533e 2874 struct skge_port *skge = netdev_priv(dev);
7c442fa1 2875 struct skge_element *e;
baef58b1 2876
7c442fa1
SH		 2877 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2878 struct skge_tx_desc *td = e->desc;
2879 skge_tx_free(skge, e, td->control);
2880 td->control = 0;
2881 }
2882
2883 skge->tx_ring.to_clean = e;
513f533e 2884 netif_wake_queue(dev);
baef58b1
SH		 2885}
2886
2887static void skge_tx_timeout(struct net_device *dev)
2888{
2889 struct skge_port *skge = netdev_priv(dev);
2890
2891 if (netif_msg_timer(skge))
2892 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2893
2894 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
513f533e 2895 skge_tx_clean(dev);
baef58b1
SH		 2896}
2897
2898static int skge_change_mtu(struct net_device *dev, int new_mtu)
2899{
60b24b51
SH		 2900 struct skge_port *skge = netdev_priv(dev);
2901 struct skge_hw *hw = skge->hw;
2902 int port = skge->port;
7731a4ea 2903 int err;
60b24b51 2904 u16 ctl, reg;
baef58b1 2905
95566065 2906 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2907 return -EINVAL;
2908
7731a4ea
SH		 2909 if (!netif_running(dev)) {
2910 dev->mtu = new_mtu;
2911 return 0;
2912 }
2913
60b24b51
SH		 2914 skge_write32(hw, B0_IMSK, 0);
2915 dev->trans_start = jiffies; /* prevent tx timeout */
2916 netif_stop_queue(dev);
2917 napi_disable(&skge->napi);
2918
2919 ctl = gma_read16(hw, port, GM_GP_CTRL);
2920 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2921
2922 skge_rx_clean(skge);
2923 skge_rx_stop(hw, port);
baef58b1 2924
19a33d4e 2925 dev->mtu = new_mtu;
7731a4ea 2926
60b24b51
SH		 2927 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2928 if (new_mtu > 1500)
2929 reg |= GM_SMOD_JUMBO_ENA;
2930 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2931
2932 skge_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2933
2934 err = skge_rx_fill(dev);
2935 wmb();
2936 if (!err)
2937 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2938 skge_write32(hw, B0_IMSK, hw->intr_mask);
2939
7731a4ea
SH		 2940 if (err)
2941 dev_close(dev);
60b24b51
SH		 2942 else {
2943 gma_write16(hw, port, GM_GP_CTRL, ctl);
2944
2945 napi_enable(&skge->napi);
2946 netif_wake_queue(dev);
2947 }
baef58b1
SH		 2948
2949 return err;
2950}
2951
c4cd29d2
SH		 2952static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2953
2954static void genesis_add_filter(u8 filter[8], const u8 *addr)
2955{
2956 u32 crc, bit;
2957
2958 crc = ether_crc_le(ETH_ALEN, addr);
2959 bit = ~crc & 0x3f;
2960 filter[bit/8] |= 1 << (bit%8);
2961}
2962
baef58b1
SH		 2963static void genesis_set_multicast(struct net_device *dev)
2964{
2965 struct skge_port *skge = netdev_priv(dev);
2966 struct skge_hw *hw = skge->hw;
2967 int port = skge->port;
2968 int i, count = dev->mc_count;
2969 struct dev_mc_list *list = dev->mc_list;
2970 u32 mode;
2971 u8 filter[8];
2972
6b0c1480 2973 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2974 mode |= XM_MD_ENA_HASH;
2975 if (dev->flags & IFF_PROMISC)
2976 mode |= XM_MD_ENA_PROM;
2977 else
2978 mode &= ~XM_MD_ENA_PROM;
2979
2980 if (dev->flags & IFF_ALLMULTI)
2981 memset(filter, 0xff, sizeof(filter));
2982 else {
2983 memset(filter, 0, sizeof(filter));
c4cd29d2
SH		 2984
2985 if (skge->flow_status == FLOW_STAT_REM_SEND
2986 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2987 genesis_add_filter(filter, pause_mc_addr);
2988
2989 for (i = 0; list && i < count; i++, list = list->next)
2990 genesis_add_filter(filter, list->dmi_addr);
baef58b1
SH		 2991 }
2992
6b0c1480 2993 xm_write32(hw, port, XM_MODE, mode);
45bada65 2994 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2995}
2996
c4cd29d2
SH		 2997static void yukon_add_filter(u8 filter[8], const u8 *addr)
2998{
2999 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
3000 filter[bit/8] |= 1 << (bit%8);
3001}
3002
baef58b1
SH		 3003static void yukon_set_multicast(struct net_device *dev)
3004{
3005 struct skge_port *skge = netdev_priv(dev);
3006 struct skge_hw *hw = skge->hw;
3007 int port = skge->port;
3008 struct dev_mc_list *list = dev->mc_list;
c4cd29d2
SH		 3009 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
3010 || skge->flow_status == FLOW_STAT_SYMMETRIC);
baef58b1
SH		 3011 u16 reg;
3012 u8 filter[8];
3013
3014 memset(filter, 0, sizeof(filter));
3015
6b0c1480 3016 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 3017 reg |= GM_RXCR_UCF_ENA;
3018
8f3f8193 3019 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 3020 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3021 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
3022 memset(filter, 0xff, sizeof(filter));
c4cd29d2 3023 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
baef58b1
SH		 3024 reg &= ~GM_RXCR_MCF_ENA;
3025 else {
3026 int i;
3027 reg |= GM_RXCR_MCF_ENA;
3028
c4cd29d2
SH		 3029 if (rx_pause)
3030 yukon_add_filter(filter, pause_mc_addr);
3031
3032 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3033 yukon_add_filter(filter, list->dmi_addr);
baef58b1
SH		 3034 }
3035
3036
6b0c1480 3037 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 3038 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 3039 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 3040 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 3041 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 3042 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 3043 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 3044 (u16)filter[6] | ((u16)filter[7] << 8));
3045
6b0c1480 3046 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 3047}
3048
383181ac
SH		 3049static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3050{
3051 if (hw->chip_id == CHIP_ID_GENESIS)
3052 return status >> XMR_FS_LEN_SHIFT;
3053 else
3054 return status >> GMR_FS_LEN_SHIFT;
3055}
3056
baef58b1
SH		 3057static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3058{
3059 if (hw->chip_id == CHIP_ID_GENESIS)
3060 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3061 else
3062 return (status & GMR_FS_ANY_ERR) ||
3063 (status & GMR_FS_RX_OK) == 0;
3064}
3065
19a33d4e
SH		 3066
3067/* Get receive buffer from descriptor.
3068 * Handles copy of small buffers and reallocation failures
3069 */
c54f9765
SH		 3070static struct sk_buff *skge_rx_get(struct net_device *dev,
3071 struct skge_element *e,
3072 u32 control, u32 status, u16 csum)
19a33d4e 3073{
c54f9765 3074 struct skge_port *skge = netdev_priv(dev);
383181ac
SH		 3075 struct sk_buff *skb;
3076 u16 len = control & BMU_BBC;
3077
3078 if (unlikely(netif_msg_rx_status(skge)))
3079 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
c54f9765 3080 dev->name, e - skge->rx_ring.start,
383181ac
SH		 3081 status, len);
3082
3083 if (len > skge->rx_buf_size)
3084 goto error;
3085
3086 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3087 goto error;
3088
3089 if (bad_phy_status(skge->hw, status))
3090 goto error;
3091
3092 if (phy_length(skge->hw, status) != len)
3093 goto error;
19a33d4e
SH		 3094
3095 if (len < RX_COPY_THRESHOLD) {
c54f9765 3096 skb = netdev_alloc_skb(dev, len + 2);
383181ac
SH		 3097 if (!skb)
3098 goto resubmit;
19a33d4e 3099
383181ac 3100 skb_reserve(skb, 2);
19a33d4e
SH		 3101 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3102 pci_unmap_addr(e, mapaddr),
3103 len, PCI_DMA_FROMDEVICE);
d626f62b 3104 skb_copy_from_linear_data(e->skb, skb->data, len);
19a33d4e
SH		 3105 pci_dma_sync_single_for_device(skge->hw->pdev,
3106 pci_unmap_addr(e, mapaddr),
3107 len, PCI_DMA_FROMDEVICE);
19a33d4e 3108 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 3109 } else {
383181ac 3110 struct sk_buff *nskb;
c54f9765 3111 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
383181ac
SH		 3112 if (!nskb)
3113 goto resubmit;
19a33d4e 3114
901ccefb 3115 skb_reserve(nskb, NET_IP_ALIGN);
19a33d4e
SH		 3116 pci_unmap_single(skge->hw->pdev,
3117 pci_unmap_addr(e, mapaddr),
3118 pci_unmap_len(e, maplen),
3119 PCI_DMA_FROMDEVICE);
3120 skb = e->skb;
383181ac 3121 prefetch(skb->data);
19a33d4e 3122 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 3123 }
383181ac
SH		 3124
3125 skb_put(skb, len);
383181ac
SH		 3126 if (skge->rx_csum) {
3127 skb->csum = csum;
84fa7933 3128 skb->ip_summed = CHECKSUM_COMPLETE;
383181ac
SH		 3129 }
3130
c54f9765 3131 skb->protocol = eth_type_trans(skb, dev);
383181ac
SH		 3132
3133 return skb;
3134error:
3135
3136 if (netif_msg_rx_err(skge))
3137 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
c54f9765 3138 dev->name, e - skge->rx_ring.start,
383181ac
SH		 3139 control, status);
3140
3141 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3142 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
da00772f 3143 dev->stats.rx_length_errors++;
383181ac 3144 if (status & XMR_FS_FRA_ERR)
da00772f 3145 dev->stats.rx_frame_errors++;
383181ac 3146 if (status & XMR_FS_FCS_ERR)
da00772f 3147 dev->stats.rx_crc_errors++;
383181ac
SH		 3148 } else {
3149 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
da00772f 3150 dev->stats.rx_length_errors++;
383181ac 3151 if (status & GMR_FS_FRAGMENT)
da00772f 3152 dev->stats.rx_frame_errors++;
383181ac 3153 if (status & GMR_FS_CRC_ERR)
da00772f 3154 dev->stats.rx_crc_errors++;
383181ac
SH		 3155 }
3156
3157resubmit:
3158 skge_rx_reuse(e, skge->rx_buf_size);
3159 return NULL;
baef58b1
SH		 3160}
3161
7c442fa1 3162/* Free all buffers in Tx ring which are no longer owned by device */
513f533e 3163static void skge_tx_done(struct net_device *dev)
00a6cae2 3164{
7c442fa1 3165 struct skge_port *skge = netdev_priv(dev);
00a6cae2 3166 struct skge_ring *ring = &skge->tx_ring;
7c442fa1
SH		 3167 struct skge_element *e;
3168
513f533e 3169 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
00a6cae2 3170
866b4f3e 3171 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
992c9623 3172 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
00a6cae2 3173
992c9623 3174 if (control & BMU_OWN)
00a6cae2
SH		 3175 break;
3176
992c9623 3177 skge_tx_free(skge, e, control);
00a6cae2 3178 }
7c442fa1 3179 skge->tx_ring.to_clean = e;
866b4f3e 3180
992c9623
SH		 3181 /* Can run lockless until we need to synchronize to restart queue. */
3182 smp_mb();
3183
3184 if (unlikely(netif_queue_stopped(dev) &&
3185 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3186 netif_tx_lock(dev);
3187 if (unlikely(netif_queue_stopped(dev) &&
3188 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3189 netif_wake_queue(dev);
00a6cae2 3190
992c9623
SH		 3191 }
3192 netif_tx_unlock(dev);
3193 }
00a6cae2 3194}
19a33d4e 3195
bea3348e 3196static int skge_poll(struct napi_struct *napi, int to_do)
baef58b1 3197{
bea3348e
SH		 3198 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3199 struct net_device *dev = skge->netdev;
baef58b1
SH		 3200 struct skge_hw *hw = skge->hw;
3201 struct skge_ring *ring = &skge->rx_ring;
3202 struct skge_element *e;
00a6cae2
SH		 3203 int work_done = 0;
3204
513f533e
SH		 3205 skge_tx_done(dev);
3206
3207 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3208
1631aef1 3209 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 3210 struct skge_rx_desc *rd = e->desc;
19a33d4e 3211 struct sk_buff *skb;
383181ac 3212 u32 control;
baef58b1
SH		 3213
3214 rmb();
3215 control = rd->control;
3216 if (control & BMU_OWN)
3217 break;
3218
c54f9765 3219 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
19a33d4e 3220 if (likely(skb)) {
19a33d4e
SH		 3221 dev->last_rx = jiffies;
3222 netif_receive_skb(skb);
baef58b1 3223
19a33d4e 3224 ++work_done;
5a011447 3225 }
baef58b1
SH		 3226 }
3227 ring->to_clean = e;
3228
baef58b1
SH		 3229 /* restart receiver */
3230 wmb();
a9cdab86 3231 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 3232
bea3348e
SH		 3233 if (work_done < to_do) {
3234 spin_lock_irq(&hw->hw_lock);
3235 __netif_rx_complete(dev, napi);
3236 hw->intr_mask |= napimask[skge->port];
3237 skge_write32(hw, B0_IMSK, hw->intr_mask);
3238 skge_read32(hw, B0_IMSK);
3239 spin_unlock_irq(&hw->hw_lock);
3240 }
1631aef1 3241
bea3348e 3242 return work_done;
baef58b1
SH		 3243}
3244
f6620cab
SH		 3245/* Parity errors seem to happen when Genesis is connected to a switch
3246 * with no other ports present. Heartbeat error??
3247 */
baef58b1
SH		 3248static void skge_mac_parity(struct skge_hw *hw, int port)
3249{
f6620cab
SH		 3250 struct net_device *dev = hw->dev[port];
3251
da00772f 3252 ++dev->stats.tx_heartbeat_errors;
baef58b1
SH		 3253
3254 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 3255 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 3256 MFF_CLR_PERR);
3257 else
3258 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 3259 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 3260 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 3261 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3262}
3263
baef58b1
SH		 3264static void skge_mac_intr(struct skge_hw *hw, int port)
3265{
95566065 3266 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 3267 genesis_mac_intr(hw, port);
3268 else
3269 yukon_mac_intr(hw, port);
3270}
3271
3272/* Handle device specific framing and timeout interrupts */
3273static void skge_error_irq(struct skge_hw *hw)
3274{
1479d13c 3275 struct pci_dev *pdev = hw->pdev;
baef58b1
SH		 3276 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3277
3278 if (hw->chip_id == CHIP_ID_GENESIS) {
3279 /* clear xmac errors */
3280 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 3281 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 3282 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 3283 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 3284 } else {
3285 /* Timestamp (unused) overflow */
3286 if (hwstatus & IS_IRQ_TIST_OV)
3287 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 3288 }
3289
3290 if (hwstatus & IS_RAM_RD_PAR) {
1479d13c 3291 dev_err(&pdev->dev, "Ram read data parity error\n");
baef58b1
SH		 3292 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3293 }
3294
3295 if (hwstatus & IS_RAM_WR_PAR) {
1479d13c 3296 dev_err(&pdev->dev, "Ram write data parity error\n");
baef58b1
SH		 3297 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3298 }
3299
3300 if (hwstatus & IS_M1_PAR_ERR)
3301 skge_mac_parity(hw, 0);
3302
3303 if (hwstatus & IS_M2_PAR_ERR)
3304 skge_mac_parity(hw, 1);
3305
b9d64acc 3306 if (hwstatus & IS_R1_PAR_ERR) {
1479d13c
SH		 3307 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3308 hw->dev[0]->name);
baef58b1 3309 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 3310 }
baef58b1 3311
b9d64acc 3312 if (hwstatus & IS_R2_PAR_ERR) {
1479d13c
SH		 3313 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3314 hw->dev[1]->name);
baef58b1 3315 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 3316 }
baef58b1
SH		 3317
3318 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 3319 u16 pci_status, pci_cmd;
3320
1479d13c
SH		 3321 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3322 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
baef58b1 3323
1479d13c
SH		 3324 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3325 pci_cmd, pci_status);
b9d64acc
SH		 3326
3327 /* Write the error bits back to clear them. */
3328 pci_status &= PCI_STATUS_ERROR_BITS;
3329 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1479d13c 3330 pci_write_config_word(pdev, PCI_COMMAND,
b9d64acc 3331 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
1479d13c 3332 pci_write_config_word(pdev, PCI_STATUS, pci_status);
b9d64acc 3333 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 3334
050ec18a 3335 /* if error still set then just ignore it */
baef58b1
SH		 3336 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3337 if (hwstatus & IS_IRQ_STAT) {
1479d13c 3338 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
baef58b1
SH		 3339 hw->intr_mask &= ~IS_HW_ERR;
3340 }
3341 }
3342}
3343
3344/*
9cbe330f 3345 * Interrupt from PHY are handled in tasklet (softirq)
baef58b1
SH		 3346 * because accessing phy registers requires spin wait which might
3347 * cause excess interrupt latency.
3348 */
9cbe330f 3349static void skge_extirq(unsigned long arg)
baef58b1 3350{
9cbe330f 3351 struct skge_hw *hw = (struct skge_hw *) arg;
baef58b1
SH		 3352 int port;
3353
cfc3ed79 3354 for (port = 0; port < hw->ports; port++) {
baef58b1
SH		 3355 struct net_device *dev = hw->dev[port];
3356
cfc3ed79 3357 if (netif_running(dev)) {
9cbe330f
SH		 3358 struct skge_port *skge = netdev_priv(dev);
3359
3360 spin_lock(&hw->phy_lock);
baef58b1
SH		 3361 if (hw->chip_id != CHIP_ID_GENESIS)
3362 yukon_phy_intr(skge);
64f6b64d 3363 else if (hw->phy_type == SK_PHY_BCOM)
45bada65 3364 bcom_phy_intr(skge);
9cbe330f 3365 spin_unlock(&hw->phy_lock);
baef58b1
SH		 3366 }
3367 }
baef58b1 3368
7c442fa1 3369 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 3370 hw->intr_mask |= IS_EXT_REG;
3371 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3372 skge_read32(hw, B0_IMSK);
7c442fa1 3373 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 3374}
3375
7d12e780 3376static irqreturn_t skge_intr(int irq, void *dev_id)
baef58b1
SH		 3377{
3378 struct skge_hw *hw = dev_id;
cfc3ed79 3379 u32 status;
29365c90 3380 int handled = 0;
baef58b1 3381
29365c90 3382 spin_lock(&hw->hw_lock);
cfc3ed79
SH		 3383 /* Reading this register masks IRQ */
3384 status = skge_read32(hw, B0_SP_ISRC);
0486a8c8 3385 if (status == 0 || status == ~0)
29365c90 3386 goto out;
baef58b1 3387
29365c90 3388 handled = 1;
7c442fa1 3389 status &= hw->intr_mask;
cfc3ed79
SH		 3390 if (status & IS_EXT_REG) {
3391 hw->intr_mask &= ~IS_EXT_REG;
9cbe330f 3392 tasklet_schedule(&hw->phy_task);
cfc3ed79
SH		 3393 }
3394
513f533e 3395 if (status & (IS_XA1_F|IS_R1_F)) {
bea3348e 3396 struct skge_port *skge = netdev_priv(hw->dev[0]);
513f533e 3397 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
bea3348e 3398 netif_rx_schedule(hw->dev[0], &skge->napi);
baef58b1
SH		 3399 }
3400
7c442fa1
SH		 3401 if (status & IS_PA_TO_TX1)
3402 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
cfc3ed79 3403
d25f5a67 3404 if (status & IS_PA_TO_RX1) {
da00772f 3405 ++hw->dev[0]->stats.rx_over_errors;
7c442fa1 3406 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
d25f5a67
SH		 3407 }
3408
d25f5a67 3409
baef58b1
SH		 3410 if (status & IS_MAC1)
3411 skge_mac_intr(hw, 0);
95566065 3412
7c442fa1 3413 if (hw->dev[1]) {
bea3348e
SH		 3414 struct skge_port *skge = netdev_priv(hw->dev[1]);
3415
513f533e
SH		 3416 if (status & (IS_XA2_F|IS_R2_F)) {
3417 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
bea3348e 3418 netif_rx_schedule(hw->dev[1], &skge->napi);
7c442fa1
SH		 3419 }
3420
3421 if (status & IS_PA_TO_RX2) {
da00772f 3422 ++hw->dev[1]->stats.rx_over_errors;
7c442fa1
SH		 3423 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3424 }
3425
3426 if (status & IS_PA_TO_TX2)
3427 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3428
3429 if (status & IS_MAC2)
3430 skge_mac_intr(hw, 1);
3431 }
baef58b1
SH		 3432
3433 if (status & IS_HW_ERR)
3434 skge_error_irq(hw);
3435
7e676d91 3436 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3437 skge_read32(hw, B0_IMSK);
29365c90 3438out:
7c442fa1 3439 spin_unlock(&hw->hw_lock);
baef58b1 3440
29365c90 3441 return IRQ_RETVAL(handled);
baef58b1
SH		 3442}
3443
3444#ifdef CONFIG_NET_POLL_CONTROLLER
3445static void skge_netpoll(struct net_device *dev)
3446{
3447 struct skge_port *skge = netdev_priv(dev);
3448
3449 disable_irq(dev->irq);
7d12e780 3450 skge_intr(dev->irq, skge->hw);
baef58b1
SH		 3451 enable_irq(dev->irq);
3452}
3453#endif
3454
3455static int skge_set_mac_address(struct net_device *dev, void *p)
3456{
3457 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 3458 struct skge_hw *hw = skge->hw;
3459 unsigned port = skge->port;
3460 const struct sockaddr *addr = p;
2eb3e621 3461 u16 ctrl;
baef58b1
SH		 3462
3463 if (!is_valid_ether_addr(addr->sa_data))
3464 return -EADDRNOTAVAIL;
3465
baef58b1 3466 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 3467
9cbe330f
SH		 3468 if (!netif_running(dev)) {
3469 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3470 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3471 } else {
3472 /* disable Rx */
3473 spin_lock_bh(&hw->phy_lock);
3474 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3475 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
2eb3e621 3476
9cbe330f
SH		 3477 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3478 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
2eb3e621 3479
2eb3e621
SH		 3480 if (hw->chip_id == CHIP_ID_GENESIS)
3481 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3482 else {
3483 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3484 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3485 }
2eb3e621 3486
9cbe330f
SH		 3487 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3488 spin_unlock_bh(&hw->phy_lock);
3489 }
c2681dd8
SH		 3490
3491 return 0;
baef58b1
SH		 3492}
3493
3494static const struct {
3495 u8 id;
3496 const char *name;
3497} skge_chips[] = {
3498 { CHIP_ID_GENESIS, "Genesis" },
3499 { CHIP_ID_YUKON, "Yukon" },
3500 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3501 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 3502};
3503
3504static const char *skge_board_name(const struct skge_hw *hw)
3505{
3506 int i;
3507 static char buf[16];
3508
3509 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3510 if (skge_chips[i].id == hw->chip_id)
3511 return skge_chips[i].name;
3512
3513 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3514 return buf;
3515}
3516
3517
3518/*
3519 * Setup the board data structure, but don't bring up
3520 * the port(s)
3521 */
3522static int skge_reset(struct skge_hw *hw)
3523{
adba9e23 3524 u32 reg;
b9d64acc 3525 u16 ctst, pci_status;
64f6b64d 3526 u8 t8, mac_cfg, pmd_type;
981d0377 3527 int i;
baef58b1
SH		 3528
3529 ctst = skge_read16(hw, B0_CTST);
3530
3531 /* do a SW reset */
3532 skge_write8(hw, B0_CTST, CS_RST_SET);
3533 skge_write8(hw, B0_CTST, CS_RST_CLR);
3534
3535 /* clear PCI errors, if any */
b9d64acc
SH		 3536 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3537 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3538
b9d64acc
SH		 3539 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3540 pci_write_config_word(hw->pdev, PCI_STATUS,
3541 pci_status | PCI_STATUS_ERROR_BITS);
3542 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3543 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3544
3545 /* restore CLK_RUN bits (for Yukon-Lite) */
3546 skge_write16(hw, B0_CTST,
3547 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3548
3549 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
64f6b64d 3550 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
5e1705dd
SH		 3551 pmd_type = skge_read8(hw, B2_PMD_TYP);
3552 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3553
95566065 3554 switch (hw->chip_id) {
baef58b1 3555 case CHIP_ID_GENESIS:
64f6b64d
SH		 3556 switch (hw->phy_type) {
3557 case SK_PHY_XMAC:
3558 hw->phy_addr = PHY_ADDR_XMAC;
3559 break;
baef58b1
SH		 3560 case SK_PHY_BCOM:
3561 hw->phy_addr = PHY_ADDR_BCOM;
3562 break;
3563 default:
1479d13c
SH		 3564 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3565 hw->phy_type);
baef58b1
SH		 3566 return -EOPNOTSUPP;
3567 }
3568 break;
3569
3570 case CHIP_ID_YUKON:
3571 case CHIP_ID_YUKON_LITE:
3572 case CHIP_ID_YUKON_LP:
64f6b64d 3573 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
5e1705dd 3574 hw->copper = 1;
baef58b1
SH		 3575
3576 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3577 break;
3578
3579 default:
1479d13c
SH		 3580 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3581 hw->chip_id);
baef58b1
SH		 3582 return -EOPNOTSUPP;
3583 }
3584
981d0377
SH		 3585 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3586 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3587 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3588
3589 /* read the adapters RAM size */
3590 t8 = skge_read8(hw, B2_E_0);
3591 if (hw->chip_id == CHIP_ID_GENESIS) {
3592 if (t8 == 3) {
3593 /* special case: 4 x 64k x 36, offset = 0x80000 */
279e1dab
LT		 3594 hw->ram_size = 0x100000;
3595 hw->ram_offset = 0x80000;
baef58b1
SH		 3596 } else
3597 hw->ram_size = t8 * 512;
279e1dab
LT		 3598 }
3599 else if (t8 == 0)
3600 hw->ram_size = 0x20000;
3601 else
3602 hw->ram_size = t8 * 4096;
baef58b1 3603
4ebabfcb 3604 hw->intr_mask = IS_HW_ERR;
cfc3ed79 3605
4ebabfcb 3606 /* Use PHY IRQ for all but fiber based Genesis board */
64f6b64d
SH		 3607 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3608 hw->intr_mask |= IS_EXT_REG;
3609
baef58b1
SH		 3610 if (hw->chip_id == CHIP_ID_GENESIS)
3611 genesis_init(hw);
3612 else {
3613 /* switch power to VCC (WA for VAUX problem) */
3614 skge_write8(hw, B0_POWER_CTRL,
3615 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3616
050ec18a
SH		 3617 /* avoid boards with stuck Hardware error bits */
3618 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3619 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
1479d13c 3620 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
050ec18a
SH		 3621 hw->intr_mask &= ~IS_HW_ERR;
3622 }
3623
adba9e23
SH		 3624 /* Clear PHY COMA */
3625 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3626 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3627 reg &= ~PCI_PHY_COMA;
3628 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3629 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3630
3631
981d0377 3632 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3633 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3634 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3635 }
3636 }
3637
3638 /* turn off hardware timer (unused) */
3639 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3640 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3641 skge_write8(hw, B0_LED, LED_STAT_ON);
3642
3643 /* enable the Tx Arbiters */
981d0377 3644 for (i = 0; i < hw->ports; i++)
6b0c1480 3645 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3646
3647 /* Initialize ram interface */
3648 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3649
3650 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3651 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3652 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3653 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3654 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3655 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3656 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3657 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3658 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3659 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3660 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3661 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3662
3663 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3664
3665 /* Set interrupt moderation for Transmit only
3666 * Receive interrupts avoided by NAPI
3667 */
3668 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3669 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3670 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3671
baef58b1
SH		 3672 skge_write32(hw, B0_IMSK, hw->intr_mask);
3673
981d0377 3674 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3675 if (hw->chip_id == CHIP_ID_GENESIS)
3676 genesis_reset(hw, i);
3677 else
3678 yukon_reset(hw, i);
3679 }
baef58b1
SH		 3680
3681 return 0;
3682}
3683
678aa1f6
SH		 3684
3685#ifdef CONFIG_SKGE_DEBUG
3686
3687static struct dentry *skge_debug;
3688
3689static int skge_debug_show(struct seq_file *seq, void *v)
3690{
3691 struct net_device *dev = seq->private;
3692 const struct skge_port *skge = netdev_priv(dev);
3693 const struct skge_hw *hw = skge->hw;
3694 const struct skge_element *e;
3695
3696 if (!netif_running(dev))
3697 return -ENETDOWN;
3698
3699 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3700 skge_read32(hw, B0_IMSK));
3701
3702 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3703 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3704 const struct skge_tx_desc *t = e->desc;
3705 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3706 t->control, t->dma_hi, t->dma_lo, t->status,
3707 t->csum_offs, t->csum_write, t->csum_start);
3708 }
3709
3710 seq_printf(seq, "\nRx Ring: \n");
3711 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3712 const struct skge_rx_desc *r = e->desc;
3713
3714 if (r->control & BMU_OWN)
3715 break;
3716
3717 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3718 r->control, r->dma_hi, r->dma_lo, r->status,
3719 r->timestamp, r->csum1, r->csum1_start);
3720 }
3721
3722 return 0;
3723}
3724
3725static int skge_debug_open(struct inode *inode, struct file *file)
3726{
3727 return single_open(file, skge_debug_show, inode->i_private);
3728}
3729
3730static const struct file_operations skge_debug_fops = {
3731 .owner = THIS_MODULE,
3732 .open = skge_debug_open,
3733 .read = seq_read,
3734 .llseek = seq_lseek,
3735 .release = single_release,
3736};
3737
3738/*
3739 * Use network device events to create/remove/rename
3740 * debugfs file entries
3741 */
3742static int skge_device_event(struct notifier_block *unused,
3743 unsigned long event, void *ptr)
3744{
3745 struct net_device *dev = ptr;
3746 struct skge_port *skge;
3747 struct dentry *d;
3748
3749 if (dev->open != &skge_up || !skge_debug)
3750 goto done;
3751
3752 skge = netdev_priv(dev);
3753 switch(event) {
3754 case NETDEV_CHANGENAME:
3755 if (skge->debugfs) {
3756 d = debugfs_rename(skge_debug, skge->debugfs,
3757 skge_debug, dev->name);
3758 if (d)
3759 skge->debugfs = d;
3760 else {
3761 pr_info(PFX "%s: rename failed\n", dev->name);
3762 debugfs_remove(skge->debugfs);
3763 }
3764 }
3765 break;
3766
3767 case NETDEV_GOING_DOWN:
3768 if (skge->debugfs) {
3769 debugfs_remove(skge->debugfs);
3770 skge->debugfs = NULL;
3771 }
3772 break;
3773
3774 case NETDEV_UP:
3775 d = debugfs_create_file(dev->name, S_IRUGO,
3776 skge_debug, dev,
3777 &skge_debug_fops);
3778 if (!d || IS_ERR(d))
3779 pr_info(PFX "%s: debugfs create failed\n",
3780 dev->name);
3781 else
3782 skge->debugfs = d;
3783 break;
3784 }
3785
3786done:
3787 return NOTIFY_DONE;
3788}
3789
3790static struct notifier_block skge_notifier = {
3791 .notifier_call = skge_device_event,
3792};
3793
3794
3795static __init void skge_debug_init(void)
3796{
3797 struct dentry *ent;
3798
3799 ent = debugfs_create_dir("skge", NULL);
3800 if (!ent || IS_ERR(ent)) {
3801 pr_info(PFX "debugfs create directory failed\n");
3802 return;
3803 }
3804
3805 skge_debug = ent;
3806 register_netdevice_notifier(&skge_notifier);
3807}
3808
3809static __exit void skge_debug_cleanup(void)
3810{
3811 if (skge_debug) {
3812 unregister_netdevice_notifier(&skge_notifier);
3813 debugfs_remove(skge_debug);
3814 skge_debug = NULL;
3815 }
3816}
3817
3818#else
3819#define skge_debug_init()
3820#define skge_debug_cleanup()
3821#endif
3822
baef58b1 3823/* Initialize network device */
981d0377
SH		 3824static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3825 int highmem)
baef58b1
SH		 3826{
3827 struct skge_port *skge;
3828 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3829
3830 if (!dev) {
1479d13c 3831 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
baef58b1
SH		 3832 return NULL;
3833 }
3834
baef58b1
SH		 3835 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3836 dev->open = skge_up;
3837 dev->stop = skge_down;
2cd8e5d3 3838 dev->do_ioctl = skge_ioctl;
baef58b1
SH		 3839 dev->hard_start_xmit = skge_xmit_frame;
3840 dev->get_stats = skge_get_stats;
3841 if (hw->chip_id == CHIP_ID_GENESIS)
3842 dev->set_multicast_list = genesis_set_multicast;
3843 else
3844 dev->set_multicast_list = yukon_set_multicast;
3845
3846 dev->set_mac_address = skge_set_mac_address;
3847 dev->change_mtu = skge_change_mtu;
3848 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3849 dev->tx_timeout = skge_tx_timeout;
3850 dev->watchdog_timeo = TX_WATCHDOG;
baef58b1
SH		 3851#ifdef CONFIG_NET_POLL_CONTROLLER
3852 dev->poll_controller = skge_netpoll;
3853#endif
3854 dev->irq = hw->pdev->irq;
513f533e 3855
981d0377
SH		 3856 if (highmem)
3857 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3858
3859 skge = netdev_priv(dev);
bea3348e 3860 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
baef58b1
SH		 3861 skge->netdev = dev;
3862 skge->hw = hw;
3863 skge->msg_enable = netif_msg_init(debug, default_msg);
9cbe330f 3864
baef58b1
SH		 3865 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3866 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3867
3868 /* Auto speed and flow control */
3869 skge->autoneg = AUTONEG_ENABLE;
5d5c8e03 3870 skge->flow_control = FLOW_MODE_SYM_OR_REM;
baef58b1
SH		 3871 skge->duplex = -1;
3872 skge->speed = -1;
31b619c5 3873 skge->advertising = skge_supported_modes(hw);
5b982c5b
SH		 3874
3875 if (pci_wake_enabled(hw->pdev))
3876 skge->wol = wol_supported(hw) & WAKE_MAGIC;
baef58b1
SH		 3877
3878 hw->dev[port] = dev;
3879
3880 skge->port = port;
3881
64f6b64d 3882 /* Only used for Genesis XMAC */
9cbe330f 3883 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
64f6b64d 3884
baef58b1
SH		 3885 if (hw->chip_id != CHIP_ID_GENESIS) {
3886 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3887 skge->rx_csum = 1;
3888 }
3889
3890 /* read the mac address */
3891 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3892 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3893
3894 /* device is off until link detection */
3895 netif_carrier_off(dev);
3896 netif_stop_queue(dev);
3897
3898 return dev;
3899}
3900
3901static void __devinit skge_show_addr(struct net_device *dev)
3902{
3903 const struct skge_port *skge = netdev_priv(dev);
0795af57 3904 DECLARE_MAC_BUF(mac);
baef58b1
SH		 3905
3906 if (netif_msg_probe(skge))
0795af57
JP		 3907 printk(KERN_INFO PFX "%s: addr %s\n",
3908 dev->name, print_mac(mac, dev->dev_addr));
baef58b1
SH		 3909}
3910
3911static int __devinit skge_probe(struct pci_dev *pdev,
3912 const struct pci_device_id *ent)
3913{
3914 struct net_device *dev, *dev1;
3915 struct skge_hw *hw;
3916 int err, using_dac = 0;
3917
203babb6
SH		 3918 err = pci_enable_device(pdev);
3919 if (err) {
1479d13c 3920 dev_err(&pdev->dev, "cannot enable PCI device\n");
baef58b1
SH		 3921 goto err_out;
3922 }
3923
203babb6
SH		 3924 err = pci_request_regions(pdev, DRV_NAME);
3925 if (err) {
1479d13c 3926 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
baef58b1
SH		 3927 goto err_out_disable_pdev;
3928 }
3929
3930 pci_set_master(pdev);
3931
93aea718 3932 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
baef58b1 3933 using_dac = 1;
77783a78 3934 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
93aea718
SH		 3935 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3936 using_dac = 0;
3937 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3938 }
3939
3940 if (err) {
1479d13c 3941 dev_err(&pdev->dev, "no usable DMA configuration\n");
93aea718 3942 goto err_out_free_regions;
baef58b1
SH		 3943 }
3944
3945#ifdef __BIG_ENDIAN
8f3f8193 3946 /* byte swap descriptors in hardware */
baef58b1
SH		 3947 {
3948 u32 reg;
3949
3950 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3951 reg |= PCI_REV_DESC;
3952 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3953 }
3954#endif
3955
3956 err = -ENOMEM;
7e863061 3957 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
baef58b1 3958 if (!hw) {
1479d13c 3959 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
baef58b1
SH		 3960 goto err_out_free_regions;
3961 }
3962
baef58b1 3963 hw->pdev = pdev;
d38efdd6 3964 spin_lock_init(&hw->hw_lock);
9cbe330f
SH		 3965 spin_lock_init(&hw->phy_lock);
3966 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
baef58b1
SH		 3967
3968 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3969 if (!hw->regs) {
1479d13c 3970 dev_err(&pdev->dev, "cannot map device registers\n");
baef58b1
SH		 3971 goto err_out_free_hw;
3972 }
3973
baef58b1
SH		 3974 err = skge_reset(hw);
3975 if (err)
ccdaa2a9 3976 goto err_out_iounmap;
baef58b1 3977
7c7459d1
GKH		 3978 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3979 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
981d0377 3980 skge_board_name(hw), hw->chip_rev);
baef58b1 3981
ccdaa2a9
SH		 3982 dev = skge_devinit(hw, 0, using_dac);
3983 if (!dev)
baef58b1
SH		 3984 goto err_out_led_off;
3985
fae87592 3986 /* Some motherboards are broken and has zero in ROM. */
1479d13c
SH		 3987 if (!is_valid_ether_addr(dev->dev_addr))
3988 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
631ae320 3989
203babb6
SH		 3990 err = register_netdev(dev);
3991 if (err) {
1479d13c 3992 dev_err(&pdev->dev, "cannot register net device\n");
baef58b1
SH		 3993 goto err_out_free_netdev;
3994 }
3995
ccdaa2a9
SH		 3996 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3997 if (err) {
1479d13c 3998 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
ccdaa2a9
SH		 3999 dev->name, pdev->irq);
4000 goto err_out_unregister;
4001 }
baef58b1
SH		 4002 skge_show_addr(dev);
4003
981d0377 4004 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 4005 if (register_netdev(dev1) == 0)
4006 skge_show_addr(dev1);
4007 else {
4008 /* Failure to register second port need not be fatal */
1479d13c 4009 dev_warn(&pdev->dev, "register of second port failed\n");
baef58b1
SH		 4010 hw->dev[1] = NULL;
4011 free_netdev(dev1);
4012 }
4013 }
ccdaa2a9 4014 pci_set_drvdata(pdev, hw);
baef58b1
SH		 4015
4016 return 0;
4017
ccdaa2a9
SH		 4018err_out_unregister:
4019 unregister_netdev(dev);
baef58b1
SH		 4020err_out_free_netdev:
4021 free_netdev(dev);
4022err_out_led_off:
4023 skge_write16(hw, B0_LED, LED_STAT_OFF);
baef58b1
SH		 4024err_out_iounmap:
4025 iounmap(hw->regs);
4026err_out_free_hw:
4027 kfree(hw);
4028err_out_free_regions:
4029 pci_release_regions(pdev);
4030err_out_disable_pdev:
4031 pci_disable_device(pdev);
4032 pci_set_drvdata(pdev, NULL);
4033err_out:
4034 return err;
4035}
4036
4037static void __devexit skge_remove(struct pci_dev *pdev)
4038{
4039 struct skge_hw *hw = pci_get_drvdata(pdev);
4040 struct net_device *dev0, *dev1;
4041
95566065 4042 if (!hw)
baef58b1
SH		 4043 return;
4044
208491d8
SH		 4045 flush_scheduled_work();
4046
baef58b1
SH		 4047 if ((dev1 = hw->dev[1]))
4048 unregister_netdev(dev1);
4049 dev0 = hw->dev[0];
4050 unregister_netdev(dev0);
4051
9cbe330f
SH		 4052 tasklet_disable(&hw->phy_task);
4053
7c442fa1
SH		 4054 spin_lock_irq(&hw->hw_lock);
4055 hw->intr_mask = 0;
46a60f2d 4056 skge_write32(hw, B0_IMSK, 0);
78bc2186 4057 skge_read32(hw, B0_IMSK);
7c442fa1
SH		 4058 spin_unlock_irq(&hw->hw_lock);
4059
46a60f2d 4060 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 4061 skge_write8(hw, B0_CTST, CS_RST_SET);
4062
baef58b1
SH		 4063 free_irq(pdev->irq, hw);
4064 pci_release_regions(pdev);
4065 pci_disable_device(pdev);
4066 if (dev1)
4067 free_netdev(dev1);
4068 free_netdev(dev0);
46a60f2d 4069
baef58b1
SH		 4070 iounmap(hw->regs);
4071 kfree(hw);
4072 pci_set_drvdata(pdev, NULL);
4073}
4074
4075#ifdef CONFIG_PM
2a569579 4076static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 4077{
4078 struct skge_hw *hw = pci_get_drvdata(pdev);
a504e64a
SH		 4079 int i, err, wol = 0;
4080
e3b7df17
SH		 4081 if (!hw)
4082 return 0;
4083
a504e64a
SH		 4084 err = pci_save_state(pdev);
4085 if (err)
4086 return err;
baef58b1 4087
d38efdd6 4088 for (i = 0; i < hw->ports; i++) {
baef58b1 4089 struct net_device *dev = hw->dev[i];
a504e64a 4090 struct skge_port *skge = netdev_priv(dev);
baef58b1 4091
a504e64a
SH		 4092 if (netif_running(dev))
4093 skge_down(dev);
4094 if (skge->wol)
4095 skge_wol_init(skge);
d38efdd6 4096
a504e64a 4097 wol |= skge->wol;
baef58b1
SH		 4098 }
4099
d38efdd6 4100 skge_write32(hw, B0_IMSK, 0);
2a569579 4101 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 4102 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4103
4104 return 0;
4105}
4106
4107static int skge_resume(struct pci_dev *pdev)
4108{
4109 struct skge_hw *hw = pci_get_drvdata(pdev);
d38efdd6 4110 int i, err;
baef58b1 4111
e3b7df17
SH		 4112 if (!hw)
4113 return 0;
4114
a504e64a
SH		 4115 err = pci_set_power_state(pdev, PCI_D0);
4116 if (err)
4117 goto out;
4118
4119 err = pci_restore_state(pdev);
4120 if (err)
4121 goto out;
4122
baef58b1
SH		 4123 pci_enable_wake(pdev, PCI_D0, 0);
4124
d38efdd6
SH		 4125 err = skge_reset(hw);
4126 if (err)
4127 goto out;
baef58b1 4128
d38efdd6 4129 for (i = 0; i < hw->ports; i++) {
baef58b1 4130 struct net_device *dev = hw->dev[i];
d38efdd6 4131
d38efdd6
SH		 4132 if (netif_running(dev)) {
4133 err = skge_up(dev);
4134
4135 if (err) {
4136 printk(KERN_ERR PFX "%s: could not up: %d\n",
4137 dev->name, err);
edd702e8 4138 dev_close(dev);
d38efdd6
SH		 4139 goto out;
4140 }
baef58b1
SH		 4141 }
4142 }
d38efdd6
SH		 4143out:
4144 return err;
baef58b1
SH		 4145}
4146#endif
4147
692412b3
SH		 4148static void skge_shutdown(struct pci_dev *pdev)
4149{
4150 struct skge_hw *hw = pci_get_drvdata(pdev);
4151 int i, wol = 0;
4152
e3b7df17
SH		 4153 if (!hw)
4154 return;
4155
692412b3
SH		 4156 for (i = 0; i < hw->ports; i++) {
4157 struct net_device *dev = hw->dev[i];
4158 struct skge_port *skge = netdev_priv(dev);
4159
4160 if (skge->wol)
4161 skge_wol_init(skge);
4162 wol |= skge->wol;
4163 }
4164
4165 pci_enable_wake(pdev, PCI_D3hot, wol);
4166 pci_enable_wake(pdev, PCI_D3cold, wol);
4167
4168 pci_disable_device(pdev);
4169 pci_set_power_state(pdev, PCI_D3hot);
4170
4171}
4172
baef58b1
SH		 4173static struct pci_driver skge_driver = {
4174 .name = DRV_NAME,
4175 .id_table = skge_id_table,
4176 .probe = skge_probe,
4177 .remove = __devexit_p(skge_remove),
4178#ifdef CONFIG_PM
4179 .suspend = skge_suspend,
4180 .resume = skge_resume,
4181#endif
692412b3 4182 .shutdown = skge_shutdown,
baef58b1
SH		 4183};
4184
4185static int __init skge_init_module(void)
4186{
678aa1f6 4187 skge_debug_init();
29917620 4188 return pci_register_driver(&skge_driver);
baef58b1
SH		 4189}
4190
4191static void __exit skge_cleanup_module(void)
4192{
4193 pci_unregister_driver(&skge_driver);
678aa1f6 4194 skge_debug_cleanup();
baef58b1
SH		 4195}
4196
4197module_init(skge_init_module);
4198module_exit(skge_cleanup_module);
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