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8ceee660 | 1 | /**************************************************************************** |
177dfcd8 BH |
2 | * Driver for Solarflare Solarstorm network controllers and boards |
3 | * Copyright 2007-2008 Solarflare Communications Inc. | |
8ceee660 BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | #include <linux/delay.h> | |
da3bc071 | 11 | #include <linux/rtnetlink.h> |
8ceee660 BH |
12 | #include <linux/seq_file.h> |
13 | #include "efx.h" | |
8ceee660 BH |
14 | #include "mdio_10g.h" |
15 | #include "falcon.h" | |
16 | #include "phy.h" | |
3e6c4538 | 17 | #include "regs.h" |
e6fa2eb7 BH |
18 | #include "workarounds.h" |
19 | #include "selftest.h" | |
8ceee660 | 20 | |
e6fa2eb7 BH |
21 | /* We expect these MMDs to be in the package. SFT9001 also has a |
22 | * clause 22 extension MMD, but since it doesn't have all the generic | |
23 | * MMD registers it is pointless to include it here. | |
24 | */ | |
68e7f45e BH |
25 | #define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \ |
26 | MDIO_DEVS_PCS | \ | |
27 | MDIO_DEVS_PHYXS | \ | |
28 | MDIO_DEVS_AN) | |
8ceee660 | 29 | |
e6fa2eb7 BH |
30 | #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \ |
31 | (1 << LOOPBACK_PCS) | \ | |
32 | (1 << LOOPBACK_PMAPMD) | \ | |
33 | (1 << LOOPBACK_NETWORK)) | |
34 | ||
35 | #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \ | |
36 | (1 << LOOPBACK_PHYXS) | \ | |
37 | (1 << LOOPBACK_PCS) | \ | |
38 | (1 << LOOPBACK_PMAPMD) | \ | |
39 | (1 << LOOPBACK_NETWORK)) | |
3273c2e8 | 40 | |
8ceee660 BH |
41 | /* We complain if we fail to see the link partner as 10G capable this many |
42 | * times in a row (must be > 1 as sampling the autoneg. registers is racy) | |
43 | */ | |
44 | #define MAX_BAD_LP_TRIES (5) | |
45 | ||
46 | /* Extended control register */ | |
e6fa2eb7 BH |
47 | #define PMA_PMD_XCONTROL_REG 49152 |
48 | #define PMA_PMD_EXT_GMII_EN_LBN 1 | |
49 | #define PMA_PMD_EXT_GMII_EN_WIDTH 1 | |
50 | #define PMA_PMD_EXT_CLK_OUT_LBN 2 | |
51 | #define PMA_PMD_EXT_CLK_OUT_WIDTH 1 | |
52 | #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */ | |
53 | #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1 | |
54 | #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */ | |
55 | #define PMA_PMD_EXT_CLK312_WIDTH 1 | |
56 | #define PMA_PMD_EXT_LPOWER_LBN 12 | |
57 | #define PMA_PMD_EXT_LPOWER_WIDTH 1 | |
869b5b38 SH |
58 | #define PMA_PMD_EXT_ROBUST_LBN 14 |
59 | #define PMA_PMD_EXT_ROBUST_WIDTH 1 | |
e6fa2eb7 BH |
60 | #define PMA_PMD_EXT_SSR_LBN 15 |
61 | #define PMA_PMD_EXT_SSR_WIDTH 1 | |
8ceee660 BH |
62 | |
63 | /* extended status register */ | |
e6fa2eb7 | 64 | #define PMA_PMD_XSTATUS_REG 49153 |
e762cd70 | 65 | #define PMA_PMD_XSTAT_MDIX_LBN 14 |
8ceee660 BH |
66 | #define PMA_PMD_XSTAT_FLP_LBN (12) |
67 | ||
68 | /* LED control register */ | |
e6fa2eb7 | 69 | #define PMA_PMD_LED_CTRL_REG 49159 |
8ceee660 BH |
70 | #define PMA_PMA_LED_ACTIVITY_LBN (3) |
71 | ||
72 | /* LED function override register */ | |
e6fa2eb7 | 73 | #define PMA_PMD_LED_OVERR_REG 49161 |
8ceee660 BH |
74 | /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/ |
75 | #define PMA_PMD_LED_LINK_LBN (0) | |
76 | #define PMA_PMD_LED_SPEED_LBN (2) | |
77 | #define PMA_PMD_LED_TX_LBN (4) | |
78 | #define PMA_PMD_LED_RX_LBN (6) | |
79 | /* Override settings */ | |
80 | #define PMA_PMD_LED_AUTO (0) /* H/W control */ | |
81 | #define PMA_PMD_LED_ON (1) | |
82 | #define PMA_PMD_LED_OFF (2) | |
83 | #define PMA_PMD_LED_FLASH (3) | |
04cc8cac | 84 | #define PMA_PMD_LED_MASK 3 |
8ceee660 | 85 | /* All LEDs under hardware control */ |
dcf477b2 | 86 | #define SFT9001_PMA_PMD_LED_DEFAULT 0 |
8ceee660 | 87 | /* Green and Amber under hardware control, Red off */ |
dcf477b2 | 88 | #define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) |
8ceee660 | 89 | |
e6fa2eb7 BH |
90 | #define PMA_PMD_SPEED_ENABLE_REG 49192 |
91 | #define PMA_PMD_100TX_ADV_LBN 1 | |
92 | #define PMA_PMD_100TX_ADV_WIDTH 1 | |
93 | #define PMA_PMD_1000T_ADV_LBN 2 | |
94 | #define PMA_PMD_1000T_ADV_WIDTH 1 | |
95 | #define PMA_PMD_10000T_ADV_LBN 3 | |
96 | #define PMA_PMD_10000T_ADV_WIDTH 1 | |
97 | #define PMA_PMD_SPEED_LBN 4 | |
98 | #define PMA_PMD_SPEED_WIDTH 4 | |
99 | ||
307505e9 BH |
100 | /* Cable diagnostics - SFT9001 only */ |
101 | #define PMA_PMD_CDIAG_CTRL_REG 49213 | |
102 | #define CDIAG_CTRL_IMMED_LBN 15 | |
103 | #define CDIAG_CTRL_BRK_LINK_LBN 12 | |
104 | #define CDIAG_CTRL_IN_PROG_LBN 11 | |
105 | #define CDIAG_CTRL_LEN_UNIT_LBN 10 | |
106 | #define CDIAG_CTRL_LEN_METRES 1 | |
107 | #define PMA_PMD_CDIAG_RES_REG 49174 | |
108 | #define CDIAG_RES_A_LBN 12 | |
109 | #define CDIAG_RES_B_LBN 8 | |
110 | #define CDIAG_RES_C_LBN 4 | |
111 | #define CDIAG_RES_D_LBN 0 | |
112 | #define CDIAG_RES_WIDTH 4 | |
113 | #define CDIAG_RES_OPEN 2 | |
114 | #define CDIAG_RES_OK 1 | |
115 | #define CDIAG_RES_INVALID 0 | |
116 | /* Set of 4 registers for pairs A-D */ | |
117 | #define PMA_PMD_CDIAG_LEN_REG 49175 | |
118 | ||
e6fa2eb7 BH |
119 | /* Serdes control registers - SFT9001 only */ |
120 | #define PMA_PMD_CSERDES_CTRL_REG 64258 | |
121 | /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */ | |
122 | #define PMA_PMD_CSERDES_DEFAULT 0x000f | |
123 | ||
124 | /* Misc register defines - SFX7101 only */ | |
125 | #define PCS_CLOCK_CTRL_REG 55297 | |
8ceee660 BH |
126 | #define PLL312_RST_N_LBN 2 |
127 | ||
e6fa2eb7 | 128 | #define PCS_SOFT_RST2_REG 55302 |
8ceee660 BH |
129 | #define SERDES_RST_N_LBN 13 |
130 | #define XGXS_RST_N_LBN 12 | |
131 | ||
e6fa2eb7 | 132 | #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */ |
8ceee660 BH |
133 | #define CLK312_EN_LBN 3 |
134 | ||
3273c2e8 | 135 | /* PHYXS registers */ |
e6fa2eb7 BH |
136 | #define PHYXS_XCONTROL_REG 49152 |
137 | #define PHYXS_RESET_LBN 15 | |
138 | #define PHYXS_RESET_WIDTH 1 | |
139 | ||
3273c2e8 BH |
140 | #define PHYXS_TEST1 (49162) |
141 | #define LOOPBACK_NEAR_LBN (8) | |
142 | #define LOOPBACK_NEAR_WIDTH (1) | |
143 | ||
8ceee660 | 144 | /* Boot status register */ |
190dbcfd BH |
145 | #define PCS_BOOT_STATUS_REG 53248 |
146 | #define PCS_BOOT_FATAL_ERROR_LBN 0 | |
147 | #define PCS_BOOT_PROGRESS_LBN 1 | |
148 | #define PCS_BOOT_PROGRESS_WIDTH 2 | |
149 | #define PCS_BOOT_PROGRESS_INIT 0 | |
150 | #define PCS_BOOT_PROGRESS_WAIT_MDIO 1 | |
151 | #define PCS_BOOT_PROGRESS_CHECKSUM 2 | |
152 | #define PCS_BOOT_PROGRESS_JUMP 3 | |
153 | #define PCS_BOOT_DOWNLOAD_WAIT_LBN 3 | |
154 | #define PCS_BOOT_CODE_STARTED_LBN 4 | |
8ceee660 | 155 | |
e6fa2eb7 BH |
156 | /* 100M/1G PHY registers */ |
157 | #define GPHY_XCONTROL_REG 49152 | |
158 | #define GPHY_ISOLATE_LBN 10 | |
159 | #define GPHY_ISOLATE_WIDTH 1 | |
160 | #define GPHY_DUPLEX_LBN 8 | |
161 | #define GPHY_DUPLEX_WIDTH 1 | |
162 | #define GPHY_LOOPBACK_NEAR_LBN 14 | |
163 | #define GPHY_LOOPBACK_NEAR_WIDTH 1 | |
164 | ||
165 | #define C22EXT_STATUS_REG 49153 | |
166 | #define C22EXT_STATUS_LINK_LBN 2 | |
167 | #define C22EXT_STATUS_LINK_WIDTH 1 | |
168 | ||
af4ad9bc BH |
169 | #define C22EXT_MSTSLV_CTRL 49161 |
170 | #define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8 | |
171 | #define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9 | |
172 | ||
173 | #define C22EXT_MSTSLV_STATUS 49162 | |
174 | #define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10 | |
175 | #define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11 | |
e6fa2eb7 | 176 | |
8ceee660 BH |
177 | /* Time to wait between powering down the LNPGA and turning off the power |
178 | * rails */ | |
179 | #define LNPGA_PDOWN_WAIT (HZ / 5) | |
180 | ||
8ceee660 | 181 | struct tenxpress_phy_data { |
3273c2e8 | 182 | enum efx_loopback_mode loopback_mode; |
f8b87c17 | 183 | enum efx_phy_mode phy_mode; |
8ceee660 BH |
184 | int bad_lp_tries; |
185 | }; | |
186 | ||
e6fa2eb7 BH |
187 | static ssize_t show_phy_short_reach(struct device *dev, |
188 | struct device_attribute *attr, char *buf) | |
189 | { | |
190 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
191 | int reg; | |
192 | ||
68e7f45e BH |
193 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR); |
194 | return sprintf(buf, "%d\n", !!(reg & MDIO_PMA_10GBT_TXPWR_SHORT)); | |
e6fa2eb7 BH |
195 | } |
196 | ||
197 | static ssize_t set_phy_short_reach(struct device *dev, | |
198 | struct device_attribute *attr, | |
199 | const char *buf, size_t count) | |
200 | { | |
201 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
202 | ||
203 | rtnl_lock(); | |
68e7f45e BH |
204 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR, |
205 | MDIO_PMA_10GBT_TXPWR_SHORT, | |
206 | count != 0 && *buf != '0'); | |
e6fa2eb7 BH |
207 | efx_reconfigure_port(efx); |
208 | rtnl_unlock(); | |
209 | ||
210 | return count; | |
211 | } | |
212 | ||
213 | static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach, | |
214 | set_phy_short_reach); | |
215 | ||
190dbcfd | 216 | int sft9001_wait_boot(struct efx_nic *efx) |
8ceee660 | 217 | { |
190dbcfd | 218 | unsigned long timeout = jiffies + HZ + 1; |
8ceee660 BH |
219 | int boot_stat; |
220 | ||
190dbcfd | 221 | for (;;) { |
68e7f45e BH |
222 | boot_stat = efx_mdio_read(efx, MDIO_MMD_PCS, |
223 | PCS_BOOT_STATUS_REG); | |
190dbcfd BH |
224 | if (boot_stat >= 0) { |
225 | EFX_LOG(efx, "PHY boot status = %#x\n", boot_stat); | |
226 | switch (boot_stat & | |
227 | ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
228 | (3 << PCS_BOOT_PROGRESS_LBN) | | |
229 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | |
230 | (1 << PCS_BOOT_CODE_STARTED_LBN))) { | |
231 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
232 | (PCS_BOOT_PROGRESS_CHECKSUM << | |
233 | PCS_BOOT_PROGRESS_LBN)): | |
234 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
235 | (PCS_BOOT_PROGRESS_INIT << | |
236 | PCS_BOOT_PROGRESS_LBN) | | |
237 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | |
238 | return -EINVAL; | |
239 | case ((PCS_BOOT_PROGRESS_WAIT_MDIO << | |
240 | PCS_BOOT_PROGRESS_LBN) | | |
241 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | |
242 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | |
243 | 0 : -EIO; | |
244 | case ((PCS_BOOT_PROGRESS_JUMP << | |
245 | PCS_BOOT_PROGRESS_LBN) | | |
246 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | |
247 | case ((PCS_BOOT_PROGRESS_JUMP << | |
248 | PCS_BOOT_PROGRESS_LBN) | | |
249 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | |
250 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | |
251 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | |
252 | -EIO : 0; | |
253 | default: | |
254 | if (boot_stat & (1 << PCS_BOOT_FATAL_ERROR_LBN)) | |
255 | return -EIO; | |
256 | break; | |
257 | } | |
258 | } | |
259 | ||
260 | if (time_after_eq(jiffies, timeout)) | |
261 | return -ETIMEDOUT; | |
262 | ||
263 | msleep(50); | |
8ceee660 | 264 | } |
8ceee660 BH |
265 | } |
266 | ||
8ceee660 BH |
267 | static int tenxpress_init(struct efx_nic *efx) |
268 | { | |
e6fa2eb7 | 269 | int reg; |
8ceee660 | 270 | |
e6fa2eb7 BH |
271 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
272 | /* Enable 312.5 MHz clock */ | |
68e7f45e BH |
273 | efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG, |
274 | 1 << CLK312_EN_LBN); | |
e6fa2eb7 BH |
275 | } else { |
276 | /* Enable 312.5 MHz clock and GMII */ | |
68e7f45e | 277 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
e6fa2eb7 BH |
278 | reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) | |
279 | (1 << PMA_PMD_EXT_CLK_OUT_LBN) | | |
869b5b38 SH |
280 | (1 << PMA_PMD_EXT_CLK312_LBN) | |
281 | (1 << PMA_PMD_EXT_ROBUST_LBN)); | |
282 | ||
68e7f45e BH |
283 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
284 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, | |
285 | GPHY_XCONTROL_REG, 1 << GPHY_ISOLATE_LBN, | |
286 | false); | |
e6fa2eb7 | 287 | } |
8ceee660 | 288 | |
8ceee660 | 289 | /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */ |
e6fa2eb7 | 290 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
68e7f45e BH |
291 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG, |
292 | 1 << PMA_PMA_LED_ACTIVITY_LBN, true); | |
293 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, | |
dcf477b2 | 294 | SFX7101_PMA_PMD_LED_DEFAULT); |
e6fa2eb7 | 295 | } |
8ceee660 | 296 | |
190dbcfd | 297 | return 0; |
8ceee660 BH |
298 | } |
299 | ||
300 | static int tenxpress_phy_init(struct efx_nic *efx) | |
301 | { | |
302 | struct tenxpress_phy_data *phy_data; | |
c634263d | 303 | u16 old_adv, adv; |
8ceee660 BH |
304 | int rc = 0; |
305 | ||
44838a44 | 306 | falcon_board(efx)->type->init_phy(efx); |
981fc1b4 | 307 | |
8ceee660 | 308 | phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL); |
9b7bfc4c BH |
309 | if (!phy_data) |
310 | return -ENOMEM; | |
8ceee660 | 311 | efx->phy_data = phy_data; |
f8b87c17 | 312 | phy_data->phy_mode = efx->phy_mode; |
8ceee660 | 313 | |
e6fa2eb7 BH |
314 | if (!(efx->phy_mode & PHY_MODE_SPECIAL)) { |
315 | if (efx->phy_type == PHY_TYPE_SFT9001A) { | |
316 | int reg; | |
68e7f45e BH |
317 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
318 | PMA_PMD_XCONTROL_REG); | |
e6fa2eb7 | 319 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
68e7f45e BH |
320 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, |
321 | PMA_PMD_XCONTROL_REG, reg); | |
e6fa2eb7 BH |
322 | mdelay(200); |
323 | } | |
8ceee660 | 324 | |
68e7f45e | 325 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); |
e6fa2eb7 BH |
326 | if (rc < 0) |
327 | goto fail; | |
328 | ||
68e7f45e | 329 | rc = efx_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0); |
e6fa2eb7 BH |
330 | if (rc < 0) |
331 | goto fail; | |
332 | } | |
8ceee660 BH |
333 | |
334 | rc = tenxpress_init(efx); | |
335 | if (rc < 0) | |
336 | goto fail; | |
337 | ||
c634263d BH |
338 | /* Set pause advertising */ |
339 | old_adv = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE); | |
340 | adv = ((old_adv & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | | |
341 | mii_advertise_flowctrl(efx->wanted_fc)); | |
342 | if (adv != old_adv) { | |
343 | efx_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, adv); | |
344 | mdio45_nway_restart(&efx->mdio); | |
345 | } | |
346 | ||
e6fa2eb7 BH |
347 | if (efx->phy_type == PHY_TYPE_SFT9001B) { |
348 | rc = device_create_file(&efx->pci_dev->dev, | |
349 | &dev_attr_phy_short_reach); | |
350 | if (rc) | |
351 | goto fail; | |
352 | } | |
353 | ||
8ceee660 BH |
354 | schedule_timeout_uninterruptible(HZ / 5); /* 200ms */ |
355 | ||
e6fa2eb7 | 356 | /* Let XGXS and SerDes out of reset */ |
8ceee660 BH |
357 | falcon_reset_xaui(efx); |
358 | ||
359 | return 0; | |
360 | ||
361 | fail: | |
362 | kfree(efx->phy_data); | |
363 | efx->phy_data = NULL; | |
364 | return rc; | |
365 | } | |
366 | ||
e6fa2eb7 BH |
367 | /* Perform a "special software reset" on the PHY. The caller is |
368 | * responsible for saving and restoring the PHY hardware registers | |
369 | * properly, and masking/unmasking LASI */ | |
3273c2e8 BH |
370 | static int tenxpress_special_reset(struct efx_nic *efx) |
371 | { | |
372 | int rc, reg; | |
373 | ||
c8fcc49c BH |
374 | /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so |
375 | * a special software reset can glitch the XGMAC sufficiently for stats | |
1974cc20 | 376 | * requests to fail. */ |
55edc6e6 | 377 | falcon_stop_nic_stats(efx); |
3273c2e8 BH |
378 | |
379 | /* Initiate reset */ | |
68e7f45e | 380 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
3273c2e8 | 381 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
68e7f45e | 382 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
3273c2e8 | 383 | |
c8fcc49c | 384 | mdelay(200); |
3273c2e8 BH |
385 | |
386 | /* Wait for the blocks to come out of reset */ | |
68e7f45e | 387 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); |
3273c2e8 | 388 | if (rc < 0) |
1974cc20 | 389 | goto out; |
3273c2e8 BH |
390 | |
391 | /* Try and reconfigure the device */ | |
392 | rc = tenxpress_init(efx); | |
393 | if (rc < 0) | |
1974cc20 | 394 | goto out; |
3273c2e8 | 395 | |
e6fa2eb7 BH |
396 | /* Wait for the XGXS state machine to churn */ |
397 | mdelay(10); | |
1974cc20 | 398 | out: |
55edc6e6 | 399 | falcon_start_nic_stats(efx); |
c8fcc49c | 400 | return rc; |
3273c2e8 BH |
401 | } |
402 | ||
e6fa2eb7 | 403 | static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok) |
8ceee660 BH |
404 | { |
405 | struct tenxpress_phy_data *pd = efx->phy_data; | |
04cc8cac | 406 | bool bad_lp; |
8ceee660 BH |
407 | int reg; |
408 | ||
04cc8cac BH |
409 | if (link_ok) { |
410 | bad_lp = false; | |
411 | } else { | |
412 | /* Check that AN has started but not completed. */ | |
68e7f45e BH |
413 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1); |
414 | if (!(reg & MDIO_AN_STAT1_LPABLE)) | |
04cc8cac | 415 | return; /* LP status is unknown */ |
68e7f45e | 416 | bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE); |
04cc8cac BH |
417 | if (bad_lp) |
418 | pd->bad_lp_tries++; | |
419 | } | |
420 | ||
8ceee660 | 421 | /* Nothing to do if all is well and was previously so. */ |
04cc8cac | 422 | if (!pd->bad_lp_tries) |
8ceee660 BH |
423 | return; |
424 | ||
04cc8cac BH |
425 | /* Use the RX (red) LED as an error indicator once we've seen AN |
426 | * failure several times in a row, and also log a message. */ | |
427 | if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) { | |
68e7f45e BH |
428 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
429 | PMA_PMD_LED_OVERR_REG); | |
04cc8cac BH |
430 | reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN); |
431 | if (!bad_lp) { | |
432 | reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN; | |
433 | } else { | |
434 | reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN; | |
435 | EFX_ERR(efx, "appears to be plugged into a port" | |
436 | " that is not 10GBASE-T capable. The PHY" | |
437 | " supports 10GBASE-T ONLY, so no link can" | |
438 | " be established\n"); | |
439 | } | |
68e7f45e BH |
440 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, |
441 | PMA_PMD_LED_OVERR_REG, reg); | |
04cc8cac | 442 | pd->bad_lp_tries = bad_lp; |
8ceee660 | 443 | } |
8ceee660 BH |
444 | } |
445 | ||
e6fa2eb7 | 446 | static bool sfx7101_link_ok(struct efx_nic *efx) |
8ceee660 | 447 | { |
68e7f45e BH |
448 | return efx_mdio_links_ok(efx, |
449 | MDIO_DEVS_PMAPMD | | |
450 | MDIO_DEVS_PCS | | |
451 | MDIO_DEVS_PHYXS); | |
e6fa2eb7 BH |
452 | } |
453 | ||
454 | static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
455 | { | |
e6fa2eb7 BH |
456 | u32 reg; |
457 | ||
caa8d8bb | 458 | if (efx_phy_mode_disabled(efx->phy_mode)) |
e6fa2eb7 | 459 | return false; |
caa8d8bb BH |
460 | else if (efx->loopback_mode == LOOPBACK_GPHY) |
461 | return true; | |
e6fa2eb7 | 462 | else if (efx->loopback_mode) |
68e7f45e BH |
463 | return efx_mdio_links_ok(efx, |
464 | MDIO_DEVS_PMAPMD | | |
465 | MDIO_DEVS_PHYXS); | |
e6fa2eb7 BH |
466 | |
467 | /* We must use the same definition of link state as LASI, | |
468 | * otherwise we can miss a link state transition | |
469 | */ | |
470 | if (ecmd->speed == 10000) { | |
68e7f45e BH |
471 | reg = efx_mdio_read(efx, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); |
472 | return reg & MDIO_PCS_10GBRT_STAT1_BLKLK; | |
e6fa2eb7 | 473 | } else { |
68e7f45e | 474 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_STATUS_REG); |
e6fa2eb7 BH |
475 | return reg & (1 << C22EXT_STATUS_LINK_LBN); |
476 | } | |
8ceee660 BH |
477 | } |
478 | ||
e6fa2eb7 | 479 | static void tenxpress_ext_loopback(struct efx_nic *efx) |
3273c2e8 | 480 | { |
68e7f45e BH |
481 | efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1, |
482 | 1 << LOOPBACK_NEAR_LBN, | |
483 | efx->loopback_mode == LOOPBACK_PHYXS); | |
e6fa2eb7 | 484 | if (efx->phy_type != PHY_TYPE_SFX7101) |
68e7f45e BH |
485 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, GPHY_XCONTROL_REG, |
486 | 1 << GPHY_LOOPBACK_NEAR_LBN, | |
487 | efx->loopback_mode == LOOPBACK_GPHY); | |
e6fa2eb7 BH |
488 | } |
489 | ||
490 | static void tenxpress_low_power(struct efx_nic *efx) | |
491 | { | |
e6fa2eb7 | 492 | if (efx->phy_type == PHY_TYPE_SFX7101) |
68e7f45e | 493 | efx_mdio_set_mmds_lpower( |
e6fa2eb7 BH |
494 | efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER), |
495 | TENXPRESS_REQUIRED_DEVS); | |
3273c2e8 | 496 | else |
68e7f45e BH |
497 | efx_mdio_set_flag( |
498 | efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, | |
499 | 1 << PMA_PMD_EXT_LPOWER_LBN, | |
e6fa2eb7 | 500 | !!(efx->phy_mode & PHY_MODE_LOW_POWER)); |
3273c2e8 BH |
501 | } |
502 | ||
8ceee660 BH |
503 | static void tenxpress_phy_reconfigure(struct efx_nic *efx) |
504 | { | |
3273c2e8 | 505 | struct tenxpress_phy_data *phy_data = efx->phy_data; |
e6fa2eb7 | 506 | struct ethtool_cmd ecmd; |
8b9dc8dd | 507 | bool phy_mode_change, loop_reset; |
3273c2e8 | 508 | |
e6fa2eb7 | 509 | if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) { |
f8b87c17 | 510 | phy_data->phy_mode = efx->phy_mode; |
8ceee660 | 511 | return; |
f8b87c17 | 512 | } |
8ceee660 | 513 | |
e6fa2eb7 BH |
514 | tenxpress_low_power(efx); |
515 | ||
516 | phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL && | |
517 | phy_data->phy_mode != PHY_MODE_NORMAL); | |
e6fa2eb7 BH |
518 | loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, efx->phy_op->loopbacks) || |
519 | LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY)); | |
520 | ||
8b9dc8dd | 521 | if (loop_reset || phy_mode_change) { |
e6fa2eb7 BH |
522 | int rc; |
523 | ||
524 | efx->phy_op->get_settings(efx, &ecmd); | |
525 | ||
526 | if (loop_reset || phy_mode_change) { | |
527 | tenxpress_special_reset(efx); | |
528 | ||
529 | /* Reset XAUI if we were in 10G, and are staying | |
530 | * in 10G. If we're moving into and out of 10G | |
531 | * then xaui will be reset anyway */ | |
532 | if (EFX_IS10G(efx)) | |
533 | falcon_reset_xaui(efx); | |
534 | } | |
535 | ||
e6fa2eb7 BH |
536 | rc = efx->phy_op->set_settings(efx, &ecmd); |
537 | WARN_ON(rc); | |
3273c2e8 BH |
538 | } |
539 | ||
68e7f45e BH |
540 | efx_mdio_transmit_disable(efx); |
541 | efx_mdio_phy_reconfigure(efx); | |
e6fa2eb7 | 542 | tenxpress_ext_loopback(efx); |
3273c2e8 | 543 | |
3273c2e8 | 544 | phy_data->loopback_mode = efx->loopback_mode; |
f8b87c17 | 545 | phy_data->phy_mode = efx->phy_mode; |
8ceee660 BH |
546 | } |
547 | ||
fdaa9aed SH |
548 | static void |
549 | tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd); | |
550 | ||
551 | /* Poll for link state changes */ | |
552 | static bool tenxpress_phy_poll(struct efx_nic *efx) | |
8ceee660 | 553 | { |
fdaa9aed | 554 | struct efx_link_state old_state = efx->link_state; |
8ceee660 | 555 | |
e6fa2eb7 | 556 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
fdaa9aed SH |
557 | efx->link_state.up = sfx7101_link_ok(efx); |
558 | efx->link_state.speed = 10000; | |
559 | efx->link_state.fd = true; | |
560 | efx->link_state.fc = efx_mdio_get_pause(efx); | |
561 | ||
562 | sfx7101_check_bad_lp(efx, efx->link_state.up); | |
766ca0fa | 563 | } else { |
fdaa9aed | 564 | struct ethtool_cmd ecmd; |
8ceee660 | 565 | |
fdaa9aed SH |
566 | /* Check the LASI alarm first */ |
567 | if (efx->loopback_mode == LOOPBACK_NONE && | |
568 | !(efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT) & | |
569 | MDIO_PMA_LASI_LSALARM)) | |
570 | return false; | |
8ceee660 | 571 | |
fdaa9aed SH |
572 | tenxpress_get_settings(efx, &ecmd); |
573 | ||
574 | efx->link_state.up = sft9001_link_ok(efx, &ecmd); | |
575 | efx->link_state.speed = ecmd.speed; | |
576 | efx->link_state.fd = (ecmd.duplex == DUPLEX_FULL); | |
577 | efx->link_state.fc = efx_mdio_get_pause(efx); | |
578 | } | |
579 | ||
580 | return !efx_link_state_equal(&efx->link_state, &old_state); | |
8ceee660 BH |
581 | } |
582 | ||
583 | static void tenxpress_phy_fini(struct efx_nic *efx) | |
584 | { | |
585 | int reg; | |
586 | ||
2a7e637d | 587 | if (efx->phy_type == PHY_TYPE_SFT9001B) |
e6fa2eb7 BH |
588 | device_remove_file(&efx->pci_dev->dev, |
589 | &dev_attr_phy_short_reach); | |
2a7e637d BH |
590 | |
591 | if (efx->phy_type == PHY_TYPE_SFX7101) { | |
e6fa2eb7 BH |
592 | /* Power down the LNPGA */ |
593 | reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); | |
68e7f45e | 594 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
e6fa2eb7 BH |
595 | |
596 | /* Waiting here ensures that the board fini, which can turn | |
597 | * off the power to the PHY, won't get run until the LNPGA | |
598 | * powerdown has been given long enough to complete. */ | |
599 | schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */ | |
600 | } | |
8ceee660 BH |
601 | |
602 | kfree(efx->phy_data); | |
603 | efx->phy_data = NULL; | |
604 | } | |
605 | ||
606 | ||
398468ed BH |
607 | /* Override the RX, TX and link LEDs */ |
608 | void tenxpress_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) | |
8ceee660 BH |
609 | { |
610 | int reg; | |
611 | ||
398468ed BH |
612 | switch (mode) { |
613 | case EFX_LED_OFF: | |
614 | reg = (PMA_PMD_LED_OFF << PMA_PMD_LED_TX_LBN) | | |
615 | (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) | | |
616 | (PMA_PMD_LED_OFF << PMA_PMD_LED_LINK_LBN); | |
617 | break; | |
618 | case EFX_LED_ON: | |
619 | reg = (PMA_PMD_LED_ON << PMA_PMD_LED_TX_LBN) | | |
620 | (PMA_PMD_LED_ON << PMA_PMD_LED_RX_LBN) | | |
621 | (PMA_PMD_LED_ON << PMA_PMD_LED_LINK_LBN); | |
622 | break; | |
623 | default: | |
dcf477b2 BH |
624 | if (efx->phy_type == PHY_TYPE_SFX7101) |
625 | reg = SFX7101_PMA_PMD_LED_DEFAULT; | |
626 | else | |
627 | reg = SFT9001_PMA_PMD_LED_DEFAULT; | |
398468ed BH |
628 | break; |
629 | } | |
8ceee660 | 630 | |
68e7f45e | 631 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg); |
8ceee660 BH |
632 | } |
633 | ||
307505e9 | 634 | static const char *const sfx7101_test_names[] = { |
1796721a BH |
635 | "bist" |
636 | }; | |
637 | ||
638 | static int | |
307505e9 | 639 | sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags) |
8c8661e4 | 640 | { |
1796721a BH |
641 | int rc; |
642 | ||
643 | if (!(flags & ETH_TEST_FL_OFFLINE)) | |
644 | return 0; | |
645 | ||
8c8661e4 | 646 | /* BIST is automatically run after a special software reset */ |
1796721a BH |
647 | rc = tenxpress_special_reset(efx); |
648 | results[0] = rc ? -1 : 1; | |
649 | return rc; | |
8c8661e4 BH |
650 | } |
651 | ||
307505e9 BH |
652 | static const char *const sft9001_test_names[] = { |
653 | "bist", | |
654 | "cable.pairA.status", | |
655 | "cable.pairB.status", | |
656 | "cable.pairC.status", | |
657 | "cable.pairD.status", | |
658 | "cable.pairA.length", | |
659 | "cable.pairB.length", | |
660 | "cable.pairC.length", | |
661 | "cable.pairD.length", | |
662 | }; | |
663 | ||
664 | static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags) | |
665 | { | |
666 | struct ethtool_cmd ecmd; | |
22ef02c2 | 667 | int rc = 0, rc2, i, ctrl_reg, res_reg; |
307505e9 | 668 | |
22ef02c2 BH |
669 | if (flags & ETH_TEST_FL_OFFLINE) |
670 | efx->phy_op->get_settings(efx, &ecmd); | |
307505e9 BH |
671 | |
672 | /* Initialise cable diagnostic results to unknown failure */ | |
673 | for (i = 1; i < 9; ++i) | |
674 | results[i] = -1; | |
675 | ||
676 | /* Run cable diagnostics; wait up to 5 seconds for them to complete. | |
677 | * A cable fault is not a self-test failure, but a timeout is. */ | |
22ef02c2 BH |
678 | ctrl_reg = ((1 << CDIAG_CTRL_IMMED_LBN) | |
679 | (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN)); | |
680 | if (flags & ETH_TEST_FL_OFFLINE) { | |
681 | /* Break the link in order to run full diagnostics. We | |
682 | * must reset the PHY to resume normal service. */ | |
683 | ctrl_reg |= (1 << CDIAG_CTRL_BRK_LINK_LBN); | |
684 | } | |
68e7f45e BH |
685 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG, |
686 | ctrl_reg); | |
307505e9 | 687 | i = 0; |
68e7f45e | 688 | while (efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG) & |
307505e9 BH |
689 | (1 << CDIAG_CTRL_IN_PROG_LBN)) { |
690 | if (++i == 50) { | |
691 | rc = -ETIMEDOUT; | |
22ef02c2 | 692 | goto out; |
307505e9 BH |
693 | } |
694 | msleep(100); | |
695 | } | |
68e7f45e | 696 | res_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_RES_REG); |
307505e9 BH |
697 | for (i = 0; i < 4; i++) { |
698 | int pair_res = | |
699 | (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH)) | |
700 | & ((1 << CDIAG_RES_WIDTH) - 1); | |
68e7f45e BH |
701 | int len_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
702 | PMA_PMD_CDIAG_LEN_REG + i); | |
307505e9 BH |
703 | if (pair_res == CDIAG_RES_OK) |
704 | results[1 + i] = 1; | |
705 | else if (pair_res == CDIAG_RES_INVALID) | |
706 | results[1 + i] = -1; | |
707 | else | |
708 | results[1 + i] = -pair_res; | |
709 | if (pair_res != CDIAG_RES_INVALID && | |
710 | pair_res != CDIAG_RES_OPEN && | |
711 | len_reg != 0xffff) | |
712 | results[5 + i] = len_reg; | |
713 | } | |
714 | ||
22ef02c2 BH |
715 | out: |
716 | if (flags & ETH_TEST_FL_OFFLINE) { | |
717 | /* Reset, running the BIST and then resuming normal service. */ | |
718 | rc2 = tenxpress_special_reset(efx); | |
719 | results[0] = rc2 ? -1 : 1; | |
720 | if (!rc) | |
721 | rc = rc2; | |
722 | ||
723 | rc2 = efx->phy_op->set_settings(efx, &ecmd); | |
724 | if (!rc) | |
725 | rc = rc2; | |
726 | } | |
307505e9 BH |
727 | |
728 | return rc; | |
729 | } | |
730 | ||
af4ad9bc BH |
731 | static void |
732 | tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
04cc8cac | 733 | { |
af4ad9bc | 734 | u32 adv = 0, lpa = 0; |
04cc8cac BH |
735 | int reg; |
736 | ||
e6fa2eb7 | 737 | if (efx->phy_type != PHY_TYPE_SFX7101) { |
68e7f45e | 738 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL); |
af4ad9bc BH |
739 | if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN)) |
740 | adv |= ADVERTISED_1000baseT_Full; | |
68e7f45e | 741 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_STATUS); |
af4ad9bc | 742 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN)) |
e6fa2eb7 | 743 | lpa |= ADVERTISED_1000baseT_Half; |
af4ad9bc | 744 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN)) |
e6fa2eb7 BH |
745 | lpa |= ADVERTISED_1000baseT_Full; |
746 | } | |
68e7f45e BH |
747 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL); |
748 | if (reg & MDIO_AN_10GBT_CTRL_ADV10G) | |
af4ad9bc | 749 | adv |= ADVERTISED_10000baseT_Full; |
68e7f45e BH |
750 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); |
751 | if (reg & MDIO_AN_10GBT_STAT_LP10G) | |
04cc8cac | 752 | lpa |= ADVERTISED_10000baseT_Full; |
04cc8cac | 753 | |
68e7f45e | 754 | mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa); |
e6fa2eb7 | 755 | |
188586b2 | 756 | ecmd->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; |
e762cd70 | 757 | if (efx->phy_type != PHY_TYPE_SFX7101) { |
af4ad9bc BH |
758 | ecmd->supported |= (SUPPORTED_100baseT_Full | |
759 | SUPPORTED_1000baseT_Full); | |
e762cd70 BH |
760 | if (ecmd->speed != SPEED_10000) { |
761 | ecmd->eth_tp_mdix = | |
762 | (efx_mdio_read(efx, MDIO_MMD_PMAPMD, | |
763 | PMA_PMD_XSTATUS_REG) & | |
764 | (1 << PMA_PMD_XSTAT_MDIX_LBN)) | |
765 | ? ETH_TP_MDI_X : ETH_TP_MDI; | |
766 | } | |
767 | } | |
8b9dc8dd SH |
768 | |
769 | /* In loopback, the PHY automatically brings up the correct interface, | |
770 | * but doesn't advertise the correct speed. So override it */ | |
771 | if (efx->loopback_mode == LOOPBACK_GPHY) | |
772 | ecmd->speed = SPEED_1000; | |
af4ad9bc | 773 | else if (LOOPBACK_MASK(efx) & efx->phy_op->loopbacks) |
8b9dc8dd | 774 | ecmd->speed = SPEED_10000; |
04cc8cac BH |
775 | } |
776 | ||
af4ad9bc | 777 | static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
e6fa2eb7 | 778 | { |
af4ad9bc BH |
779 | if (!ecmd->autoneg) |
780 | return -EINVAL; | |
e6fa2eb7 | 781 | |
68e7f45e | 782 | return efx_mdio_set_settings(efx, ecmd); |
e6fa2eb7 BH |
783 | } |
784 | ||
af4ad9bc | 785 | static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising) |
e6fa2eb7 | 786 | { |
68e7f45e BH |
787 | efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, |
788 | MDIO_AN_10GBT_CTRL_ADV10G, | |
789 | advertising & ADVERTISED_10000baseT_Full); | |
e6fa2eb7 BH |
790 | } |
791 | ||
af4ad9bc | 792 | static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising) |
e6fa2eb7 | 793 | { |
68e7f45e BH |
794 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL, |
795 | 1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN, | |
796 | advertising & ADVERTISED_1000baseT_Full); | |
797 | efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, | |
798 | MDIO_AN_10GBT_CTRL_ADV10G, | |
799 | advertising & ADVERTISED_10000baseT_Full); | |
e6fa2eb7 BH |
800 | } |
801 | ||
802 | struct efx_phy_operations falcon_sfx7101_phy_ops = { | |
177dfcd8 | 803 | .macs = EFX_XMAC, |
8ceee660 BH |
804 | .init = tenxpress_phy_init, |
805 | .reconfigure = tenxpress_phy_reconfigure, | |
766ca0fa | 806 | .poll = tenxpress_phy_poll, |
8ceee660 | 807 | .fini = tenxpress_phy_fini, |
af4ad9bc BH |
808 | .get_settings = tenxpress_get_settings, |
809 | .set_settings = tenxpress_set_settings, | |
810 | .set_npage_adv = sfx7101_set_npage_adv, | |
307505e9 BH |
811 | .num_tests = ARRAY_SIZE(sfx7101_test_names), |
812 | .test_names = sfx7101_test_names, | |
813 | .run_tests = sfx7101_run_tests, | |
8ceee660 | 814 | .mmds = TENXPRESS_REQUIRED_DEVS, |
e6fa2eb7 BH |
815 | .loopbacks = SFX7101_LOOPBACKS, |
816 | }; | |
817 | ||
818 | struct efx_phy_operations falcon_sft9001_phy_ops = { | |
819 | .macs = EFX_GMAC | EFX_XMAC, | |
820 | .init = tenxpress_phy_init, | |
821 | .reconfigure = tenxpress_phy_reconfigure, | |
822 | .poll = tenxpress_phy_poll, | |
823 | .fini = tenxpress_phy_fini, | |
af4ad9bc BH |
824 | .get_settings = tenxpress_get_settings, |
825 | .set_settings = tenxpress_set_settings, | |
826 | .set_npage_adv = sft9001_set_npage_adv, | |
307505e9 BH |
827 | .num_tests = ARRAY_SIZE(sft9001_test_names), |
828 | .test_names = sft9001_test_names, | |
829 | .run_tests = sft9001_run_tests, | |
e6fa2eb7 BH |
830 | .mmds = TENXPRESS_REQUIRED_DEVS, |
831 | .loopbacks = SFT9001_LOOPBACKS, | |
8ceee660 | 832 | }; |