[net-next-2.6.git] / drivers / net / sfc / tenxpress.c

/****************************************************************************
 * Driver for Solarflare 802.3an compliant PHY
 * Copyright 2007 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#include <linux/delay.h>
#include <linux/seq_file.h>
#include "efx.h"
#include "gmii.h"
#include "mdio_10g.h"
#include "falcon.h"
#include "phy.h"
#include "falcon_hwdefs.h"
#include "boards.h"
#include "mac.h"

/* We expect these MMDs to be in the package */
/* AN not here as mdio_check_mmds() requires STAT2 support */
#define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_PMAPMD | \
				 MDIO_MMDREG_DEVS0_PCS    | \
				 MDIO_MMDREG_DEVS0_PHYXS)

#define TENXPRESS_LOOPBACKS ((1 << LOOPBACK_PHYXS) |	\
			     (1 << LOOPBACK_PCS) |	\
			     (1 << LOOPBACK_PMAPMD) |	\
			     (1 << LOOPBACK_NETWORK))

/* We complain if we fail to see the link partner as 10G capable this many
 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
 */
#define MAX_BAD_LP_TRIES	(5)

/* Extended control register */
#define	PMA_PMD_XCONTROL_REG 0xc000
#define	PMA_PMD_LNPGA_POWERDOWN_LBN 8
#define	PMA_PMD_LNPGA_POWERDOWN_WIDTH 1

/* extended status register */
#define PMA_PMD_XSTATUS_REG 0xc001
#define PMA_PMD_XSTAT_FLP_LBN   (12)

/* LED control register */
#define PMA_PMD_LED_CTRL_REG	(0xc007)
#define PMA_PMA_LED_ACTIVITY_LBN	(3)

/* LED function override register */
#define PMA_PMD_LED_OVERR_REG	(0xc009)
/* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
#define PMA_PMD_LED_LINK_LBN	(0)
#define PMA_PMD_LED_SPEED_LBN	(2)
#define PMA_PMD_LED_TX_LBN	(4)
#define PMA_PMD_LED_RX_LBN	(6)
/* Override settings */
#define	PMA_PMD_LED_AUTO	(0)	/* H/W control */
#define	PMA_PMD_LED_ON		(1)
#define	PMA_PMD_LED_OFF		(2)
#define PMA_PMD_LED_FLASH	(3)
/* All LEDs under hardware control */
#define PMA_PMD_LED_FULL_AUTO	(0)
/* Green and Amber under hardware control, Red off */
#define PMA_PMD_LED_DEFAULT	(PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)


/* Self test (BIST) control register */
#define PMA_PMD_BIST_CTRL_REG	(0xc014)
#define PMA_PMD_BIST_BER_LBN	(2)	/* Run BER test */
#define PMA_PMD_BIST_CONT_LBN	(1)	/* Run continuous BIST until cleared */
#define PMA_PMD_BIST_SINGLE_LBN	(0)	/* Run 1 BIST iteration (self clears) */
/* Self test status register */
#define PMA_PMD_BIST_STAT_REG	(0xc015)
#define PMA_PMD_BIST_ENX_LBN	(3)
#define PMA_PMD_BIST_PMA_LBN	(2)
#define PMA_PMD_BIST_RXD_LBN	(1)
#define PMA_PMD_BIST_AFE_LBN	(0)

/* Special Software reset register */
#define PMA_PMD_EXT_CTRL_REG 49152
#define PMA_PMD_EXT_SSR_LBN 15

#define BIST_MAX_DELAY	(1000)
#define BIST_POLL_DELAY	(10)

/* Misc register defines */
#define PCS_CLOCK_CTRL_REG 0xd801
#define PLL312_RST_N_LBN 2

#define PCS_SOFT_RST2_REG 0xd806
#define SERDES_RST_N_LBN 13
#define XGXS_RST_N_LBN 12

#define	PCS_TEST_SELECT_REG 0xd807	/* PRM 10.5.8 */
#define	CLK312_EN_LBN 3

/* PHYXS registers */
#define PHYXS_TEST1         (49162)
#define LOOPBACK_NEAR_LBN   (8)
#define LOOPBACK_NEAR_WIDTH (1)

/* Boot status register */
#define PCS_BOOT_STATUS_REG	(0xd000)
#define PCS_BOOT_FATAL_ERR_LBN	(0)
#define PCS_BOOT_PROGRESS_LBN	(1)
#define PCS_BOOT_PROGRESS_WIDTH	(2)
#define PCS_BOOT_COMPLETE_LBN	(3)
#define PCS_BOOT_MAX_DELAY	(100)
#define PCS_BOOT_POLL_DELAY	(10)

/* Time to wait between powering down the LNPGA and turning off the power
 * rails */
#define LNPGA_PDOWN_WAIT	(HZ / 5)

static int crc_error_reset_threshold = 100;
module_param(crc_error_reset_threshold, int, 0644);
MODULE_PARM_DESC(crc_error_reset_threshold,
		 "Max number of CRC errors before XAUI reset");

struct tenxpress_phy_data {
	enum efx_loopback_mode loopback_mode;
	atomic_t bad_crc_count;
	enum efx_phy_mode phy_mode;
	int bad_lp_tries;
};

void tenxpress_crc_err(struct efx_nic *efx)
{
	struct tenxpress_phy_data *phy_data = efx->phy_data;
	if (phy_data != NULL)
		atomic_inc(&phy_data->bad_crc_count);
}

/* Check that the C166 has booted successfully */
static int tenxpress_phy_check(struct efx_nic *efx)
{
	int phy_id = efx->mii.phy_id;
	int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY;
	int boot_stat;

	/* Wait for the boot to complete (or not) */
	while (count) {
		boot_stat = mdio_clause45_read(efx, phy_id,
					       MDIO_MMD_PCS,
					       PCS_BOOT_STATUS_REG);
		if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN))
			break;
		count--;
		udelay(PCS_BOOT_POLL_DELAY);
	}

	if (!count) {
		EFX_ERR(efx, "%s: PHY boot timed out. Last status "
			"%x\n", __func__,
			(boot_stat >> PCS_BOOT_PROGRESS_LBN) &
			((1 << PCS_BOOT_PROGRESS_WIDTH) - 1));
		return -ETIMEDOUT;
	}

	return 0;
}

static void tenxpress_reset_xaui(struct efx_nic *efx);

static int tenxpress_init(struct efx_nic *efx)
{
	int rc, reg;

	/* Turn on the clock  */
	reg = (1 << CLK312_EN_LBN);
	mdio_clause45_write(efx, efx->mii.phy_id,
			    MDIO_MMD_PCS, PCS_TEST_SELECT_REG, reg);

	rc = tenxpress_phy_check(efx);
	if (rc < 0)
		return rc;

	/* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
	reg = mdio_clause45_read(efx, efx->mii.phy_id,
				 MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG);
	reg |= (1 << PMA_PMA_LED_ACTIVITY_LBN);
	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
			    PMA_PMD_LED_CTRL_REG, reg);

	reg = PMA_PMD_LED_DEFAULT;
	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
			    PMA_PMD_LED_OVERR_REG, reg);

	return rc;
}

static int tenxpress_phy_init(struct efx_nic *efx)
{
	struct tenxpress_phy_data *phy_data;
	int rc = 0;

	phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
	if (!phy_data)
		return -ENOMEM;
	efx->phy_data = phy_data;
	phy_data->phy_mode = efx->phy_mode;

	rc = mdio_clause45_wait_reset_mmds(efx,
					   TENXPRESS_REQUIRED_DEVS);
	if (rc < 0)
		goto fail;

	rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
	if (rc < 0)
		goto fail;

	rc = tenxpress_init(efx);
	if (rc < 0)
		goto fail;

	schedule_timeout_uninterruptible(HZ / 5); /* 200ms */

	/* Let XGXS and SerDes out of reset and resets 10XPress */
	falcon_reset_xaui(efx);

	return 0;

 fail:
	kfree(efx->phy_data);
	efx->phy_data = NULL;
	return rc;
}

static int tenxpress_special_reset(struct efx_nic *efx)
{
	int rc, reg;

	EFX_TRACE(efx, "%s\n", __func__);

	/* Initiate reset */
	reg = mdio_clause45_read(efx, efx->mii.phy_id,
				 MDIO_MMD_PMAPMD, PMA_PMD_EXT_CTRL_REG);
	reg |= (1 << PMA_PMD_EXT_SSR_LBN);
	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
			    PMA_PMD_EXT_CTRL_REG, reg);

	msleep(200);

	/* Wait for the blocks to come out of reset */
	rc = mdio_clause45_wait_reset_mmds(efx,
					   TENXPRESS_REQUIRED_DEVS);
	if (rc < 0)
		return rc;

	/* Try and reconfigure the device */
	rc = tenxpress_init(efx);
	if (rc < 0)
		return rc;

	return 0;
}

static void tenxpress_set_bad_lp(struct efx_nic *efx, bool bad_lp)
{
	struct tenxpress_phy_data *pd = efx->phy_data;
	int reg;

	/* Nothing to do if all is well and was previously so. */
	if (!(bad_lp || pd->bad_lp_tries))
		return;

	reg = mdio_clause45_read(efx, efx->mii.phy_id,
				 MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG);

	if (bad_lp)
		pd->bad_lp_tries++;
	else
		pd->bad_lp_tries = 0;

	if (pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
		pd->bad_lp_tries = 0;	/* Restart count */
		reg &= ~(PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN);
		reg |= (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN);
		EFX_ERR(efx, "This NIC appears to be plugged into"
			" a port that is not 10GBASE-T capable.\n"
			" This PHY is 10GBASE-T ONLY, so no link can"
			" be established.\n");
	} else {
		reg |= (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN);
	}
	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
			    PMA_PMD_LED_OVERR_REG, reg);
}

/* Check link status and return a boolean OK value. If the link is NOT
 * OK we have a quick rummage round to see if we appear to be plugged
 * into a non-10GBT port and if so warn the user that they won't get
 * link any time soon as we are 10GBT only, unless caller specified
 * not to do this check (it isn't useful in loopback) */
static bool tenxpress_link_ok(struct efx_nic *efx, bool check_lp)
{
	bool ok = mdio_clause45_links_ok(efx, TENXPRESS_REQUIRED_DEVS);

	if (ok) {
		tenxpress_set_bad_lp(efx, false);
	} else if (check_lp) {
		/* Are we plugged into the wrong sort of link? */
		bool bad_lp = false;
		int phy_id = efx->mii.phy_id;
		int an_stat = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
						 MDIO_AN_STATUS);
		int xphy_stat = mdio_clause45_read(efx, phy_id,
						   MDIO_MMD_PMAPMD,
						   PMA_PMD_XSTATUS_REG);
		/* Are we plugged into anything that sends FLPs? If
		 * not we can't distinguish between not being plugged
		 * in and being plugged into a non-AN antique. The FLP
		 * bit has the advantage of not clearing when autoneg
		 * restarts. */
		if (!(xphy_stat & (1 << PMA_PMD_XSTAT_FLP_LBN))) {
			tenxpress_set_bad_lp(efx, false);
			return ok;
		}

		/* If it can do 10GBT it must be XNP capable */
		bad_lp = !(an_stat & (1 << MDIO_AN_STATUS_XNP_LBN));
		if (!bad_lp && (an_stat & (1 << MDIO_AN_STATUS_PAGE_LBN))) {
			bad_lp = !(mdio_clause45_read(efx, phy_id,
					MDIO_MMD_AN, MDIO_AN_10GBT_STATUS) &
					(1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN));
		}
		tenxpress_set_bad_lp(efx, bad_lp);
	}
	return ok;
}

static void tenxpress_phyxs_loopback(struct efx_nic *efx)
{
	int phy_id = efx->mii.phy_id;
	int ctrl1, ctrl2;

	ctrl1 = ctrl2 = mdio_clause45_read(efx, phy_id, MDIO_MMD_PHYXS,
					   PHYXS_TEST1);
	if (efx->loopback_mode == LOOPBACK_PHYXS)
		ctrl2 |= (1 << LOOPBACK_NEAR_LBN);
	else
		ctrl2 &= ~(1 << LOOPBACK_NEAR_LBN);
	if (ctrl1 != ctrl2)
		mdio_clause45_write(efx, phy_id, MDIO_MMD_PHYXS,
				    PHYXS_TEST1, ctrl2);
}

static void tenxpress_phy_reconfigure(struct efx_nic *efx)
{
	struct tenxpress_phy_data *phy_data = efx->phy_data;
	bool loop_change = LOOPBACK_OUT_OF(phy_data, efx,
					   TENXPRESS_LOOPBACKS);

	if (efx->phy_mode & PHY_MODE_SPECIAL) {
		phy_data->phy_mode = efx->phy_mode;
		return;
	}

	/* When coming out of transmit disable, coming out of low power
	 * mode, or moving out of any PHY internal loopback mode,
	 * perform a special software reset */
	if ((efx->phy_mode == PHY_MODE_NORMAL &&
	     phy_data->phy_mode != PHY_MODE_NORMAL) ||
	    loop_change) {
		tenxpress_special_reset(efx);
		falcon_reset_xaui(efx);
	}

	mdio_clause45_transmit_disable(efx);
	mdio_clause45_phy_reconfigure(efx);
	tenxpress_phyxs_loopback(efx);

	phy_data->loopback_mode = efx->loopback_mode;
	phy_data->phy_mode = efx->phy_mode;
	efx->link_up = tenxpress_link_ok(efx, false);
	efx->link_options = GM_LPA_10000FULL;
}

static void tenxpress_phy_clear_interrupt(struct efx_nic *efx)
{
	/* Nothing done here - LASI interrupts aren't reliable so poll  */
}


/* Poll PHY for interrupt */
static int tenxpress_phy_check_hw(struct efx_nic *efx)
{
	struct tenxpress_phy_data *phy_data = efx->phy_data;
	bool link_ok;

	link_ok = (phy_data->phy_mode == PHY_MODE_NORMAL &&
		   tenxpress_link_ok(efx, true));

	if (link_ok != efx->link_up)
		falcon_xmac_sim_phy_event(efx);

	if (phy_data->phy_mode != PHY_MODE_NORMAL)
		return 0;

	if (atomic_read(&phy_data->bad_crc_count) > crc_error_reset_threshold) {
		EFX_ERR(efx, "Resetting XAUI due to too many CRC errors\n");
		falcon_reset_xaui(efx);
		atomic_set(&phy_data->bad_crc_count, 0);
	}

	return 0;
}

static void tenxpress_phy_fini(struct efx_nic *efx)
{
	int reg;

	/* Power down the LNPGA */
	reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
			    PMA_PMD_XCONTROL_REG, reg);

	/* Waiting here ensures that the board fini, which can turn off the
	 * power to the PHY, won't get run until the LNPGA powerdown has been
	 * given long enough to complete. */
	schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */

	kfree(efx->phy_data);
	efx->phy_data = NULL;
}


/* Set the RX and TX LEDs and Link LED flashing. The other LEDs
 * (which probably aren't wired anyway) are left in AUTO mode */
void tenxpress_phy_blink(struct efx_nic *efx, bool blink)
{
	int reg;

	if (blink)
		reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) |
			(PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) |
			(PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN);
	else
		reg = PMA_PMD_LED_DEFAULT;

	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
			    PMA_PMD_LED_OVERR_REG, reg);
}

static void tenxpress_reset_xaui(struct efx_nic *efx)
{
	int phy = efx->mii.phy_id;
	int clk_ctrl, test_select, soft_rst2;

	/* Real work is done on clock_ctrl other resets are thought to be
	 * optional but make the reset more reliable
	 */

	/* Read */
	clk_ctrl = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
				      PCS_CLOCK_CTRL_REG);
	test_select = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
					 PCS_TEST_SELECT_REG);
	soft_rst2 = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
				       PCS_SOFT_RST2_REG);

	/* Put in reset */
	test_select &= ~(1 << CLK312_EN_LBN);
	mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
			    PCS_TEST_SELECT_REG, test_select);

	soft_rst2 &= ~((1 << XGXS_RST_N_LBN) | (1 << SERDES_RST_N_LBN));
	mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
			    PCS_SOFT_RST2_REG, soft_rst2);

	clk_ctrl &= ~(1 << PLL312_RST_N_LBN);
	mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
			    PCS_CLOCK_CTRL_REG, clk_ctrl);
	udelay(10);

	/* Remove reset */
	clk_ctrl |= (1 << PLL312_RST_N_LBN);
	mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
			    PCS_CLOCK_CTRL_REG, clk_ctrl);
	udelay(10);

	soft_rst2 |= ((1 << XGXS_RST_N_LBN) | (1 << SERDES_RST_N_LBN));
	mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
			    PCS_SOFT_RST2_REG, soft_rst2);
	udelay(10);

	test_select |= (1 << CLK312_EN_LBN);
	mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
			    PCS_TEST_SELECT_REG, test_select);
	udelay(10);
}

struct efx_phy_operations falcon_tenxpress_phy_ops = {
	.init             = tenxpress_phy_init,
	.reconfigure      = tenxpress_phy_reconfigure,
	.check_hw         = tenxpress_phy_check_hw,
	.fini             = tenxpress_phy_fini,
	.clear_interrupt  = tenxpress_phy_clear_interrupt,
	.reset_xaui       = tenxpress_reset_xaui,
	.mmds             = TENXPRESS_REQUIRED_DEVS,
	.loopbacks        = TENXPRESS_LOOPBACKS,
};
Commit	Line	Data
8ceee660 BH	1	/****************************************************************************
	2	* Driver for Solarflare 802.3an compliant PHY
	3	* Copyright 2007 Solarflare Communications Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published
	7	* by the Free Software Foundation, incorporated herein by reference.
	8	*/
	9
	10	#include <linux/delay.h>
	11	#include <linux/seq_file.h>
	12	#include "efx.h"
	13	#include "gmii.h"
	14	#include "mdio_10g.h"
	15	#include "falcon.h"
	16	#include "phy.h"
	17	#include "falcon_hwdefs.h"
	18	#include "boards.h"
	19	#include "mac.h"
	20
	21	/* We expect these MMDs to be in the package */
	22	/* AN not here as mdio_check_mmds() requires STAT2 support */
	23	#define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_PMAPMD \| \
	24	MDIO_MMDREG_DEVS0_PCS \| \
	25	MDIO_MMDREG_DEVS0_PHYXS)
	26
3273c2e8 BH	27	#define TENXPRESS_LOOPBACKS ((1 << LOOPBACK_PHYXS) \| \
	28	(1 << LOOPBACK_PCS) \| \
	29	(1 << LOOPBACK_PMAPMD) \| \
	30	(1 << LOOPBACK_NETWORK))
	31
8ceee660 BH	32	/* We complain if we fail to see the link partner as 10G capable this many
	33	* times in a row (must be > 1 as sampling the autoneg. registers is racy)
	34	*/
	35	#define MAX_BAD_LP_TRIES (5)
	36
	37	/* Extended control register */
	38	#define PMA_PMD_XCONTROL_REG 0xc000
	39	#define PMA_PMD_LNPGA_POWERDOWN_LBN 8
	40	#define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
	41
	42	/* extended status register */
	43	#define PMA_PMD_XSTATUS_REG 0xc001
	44	#define PMA_PMD_XSTAT_FLP_LBN (12)
	45
	46	/* LED control register */
	47	#define PMA_PMD_LED_CTRL_REG (0xc007)
	48	#define PMA_PMA_LED_ACTIVITY_LBN (3)
	49
	50	/* LED function override register */
	51	#define PMA_PMD_LED_OVERR_REG (0xc009)
	52	/* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
	53	#define PMA_PMD_LED_LINK_LBN (0)
	54	#define PMA_PMD_LED_SPEED_LBN (2)
	55	#define PMA_PMD_LED_TX_LBN (4)
	56	#define PMA_PMD_LED_RX_LBN (6)
	57	/* Override settings */
	58	#define PMA_PMD_LED_AUTO (0) /* H/W control */
	59	#define PMA_PMD_LED_ON (1)
	60	#define PMA_PMD_LED_OFF (2)
	61	#define PMA_PMD_LED_FLASH (3)
	62	/* All LEDs under hardware control */
	63	#define PMA_PMD_LED_FULL_AUTO (0)
	64	/* Green and Amber under hardware control, Red off */
	65	#define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
	66
	67
	68	/* Self test (BIST) control register */
	69	#define PMA_PMD_BIST_CTRL_REG (0xc014)
	70	#define PMA_PMD_BIST_BER_LBN (2) /* Run BER test */
	71	#define PMA_PMD_BIST_CONT_LBN (1) /* Run continuous BIST until cleared */
	72	#define PMA_PMD_BIST_SINGLE_LBN (0) /* Run 1 BIST iteration (self clears) */
	73	/* Self test status register */
	74	#define PMA_PMD_BIST_STAT_REG (0xc015)
	75	#define PMA_PMD_BIST_ENX_LBN (3)
	76	#define PMA_PMD_BIST_PMA_LBN (2)
	77	#define PMA_PMD_BIST_RXD_LBN (1)
	78	#define PMA_PMD_BIST_AFE_LBN (0)
	79
3273c2e8 BH	80	/* Special Software reset register */
	81	#define PMA_PMD_EXT_CTRL_REG 49152
	82	#define PMA_PMD_EXT_SSR_LBN 15
	83
8ceee660 BH	84	#define BIST_MAX_DELAY (1000)
	85	#define BIST_POLL_DELAY (10)
	86
	87	/* Misc register defines */
	88	#define PCS_CLOCK_CTRL_REG 0xd801
	89	#define PLL312_RST_N_LBN 2
	90
	91	#define PCS_SOFT_RST2_REG 0xd806
	92	#define SERDES_RST_N_LBN 13
	93	#define XGXS_RST_N_LBN 12
	94
	95	#define PCS_TEST_SELECT_REG 0xd807 /* PRM 10.5.8 */
	96	#define CLK312_EN_LBN 3
	97
3273c2e8 BH	98	/* PHYXS registers */
	99	#define PHYXS_TEST1 (49162)
	100	#define LOOPBACK_NEAR_LBN (8)
	101	#define LOOPBACK_NEAR_WIDTH (1)
	102
8ceee660 BH	103	/* Boot status register */
	104	#define PCS_BOOT_STATUS_REG (0xd000)
	105	#define PCS_BOOT_FATAL_ERR_LBN (0)
	106	#define PCS_BOOT_PROGRESS_LBN (1)
	107	#define PCS_BOOT_PROGRESS_WIDTH (2)
	108	#define PCS_BOOT_COMPLETE_LBN (3)
	109	#define PCS_BOOT_MAX_DELAY (100)
	110	#define PCS_BOOT_POLL_DELAY (10)
	111
	112	/* Time to wait between powering down the LNPGA and turning off the power
	113	* rails */
	114	#define LNPGA_PDOWN_WAIT (HZ / 5)
	115
	116	static int crc_error_reset_threshold = 100;
	117	module_param(crc_error_reset_threshold, int, 0644);
	118	MODULE_PARM_DESC(crc_error_reset_threshold,
	119	"Max number of CRC errors before XAUI reset");
	120
	121	struct tenxpress_phy_data {
3273c2e8	122	enum efx_loopback_mode loopback_mode;
8ceee660	123	atomic_t bad_crc_count;
f8b87c17	124	enum efx_phy_mode phy_mode;
8ceee660 BH	125	int bad_lp_tries;
	126	};
	127
8ceee660 BH	128	void tenxpress_crc_err(struct efx_nic *efx)
	129	{
	130	struct tenxpress_phy_data *phy_data = efx->phy_data;
	131	if (phy_data != NULL)
	132	atomic_inc(&phy_data->bad_crc_count);
	133	}
	134
	135	/* Check that the C166 has booted successfully */
	136	static int tenxpress_phy_check(struct efx_nic *efx)
	137	{
	138	int phy_id = efx->mii.phy_id;
	139	int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY;
	140	int boot_stat;
	141
	142	/* Wait for the boot to complete (or not) */
	143	while (count) {
	144	boot_stat = mdio_clause45_read(efx, phy_id,
	145	MDIO_MMD_PCS,
	146	PCS_BOOT_STATUS_REG);
	147	if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN))
	148	break;
	149	count--;
	150	udelay(PCS_BOOT_POLL_DELAY);
	151	}
	152
	153	if (!count) {
	154	EFX_ERR(efx, "%s: PHY boot timed out. Last status "
	155	"%x\n", __func__,
	156	(boot_stat >> PCS_BOOT_PROGRESS_LBN) &
	157	((1 << PCS_BOOT_PROGRESS_WIDTH) - 1));
	158	return -ETIMEDOUT;
	159	}
	160
	161	return 0;
	162	}
	163
	164	static void tenxpress_reset_xaui(struct efx_nic *efx);
	165
	166	static int tenxpress_init(struct efx_nic *efx)
	167	{
	168	int rc, reg;
	169
	170	/* Turn on the clock */
	171	reg = (1 << CLK312_EN_LBN);
	172	mdio_clause45_write(efx, efx->mii.phy_id,
	173	MDIO_MMD_PCS, PCS_TEST_SELECT_REG, reg);
	174
	175	rc = tenxpress_phy_check(efx);
	176	if (rc < 0)
	177	return rc;
	178
	179	/* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
	180	reg = mdio_clause45_read(efx, efx->mii.phy_id,
	181	MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG);
	182	reg \|= (1 << PMA_PMA_LED_ACTIVITY_LBN);
	183	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
	184	PMA_PMD_LED_CTRL_REG, reg);
	185
	186	reg = PMA_PMD_LED_DEFAULT;
	187	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
	188	PMA_PMD_LED_OVERR_REG, reg);
	189
	190	return rc;
	191	}
192
193	static int tenxpress_phy_init(struct efx_nic *efx)
194	{
195	struct tenxpress_phy_data *phy_data;
196	int rc = 0;
197
198	phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
9b7bfc4c BH	199	if (!phy_data)
9b7bfc4c BH	200	return -ENOMEM;
8ceee660	201	efx->phy_data = phy_data;
f8b87c17	202	phy_data->phy_mode = efx->phy_mode;
8ceee660	203
f8b87c17 BH	204	rc = mdio_clause45_wait_reset_mmds(efx,
	205	TENXPRESS_REQUIRED_DEVS);
	206	if (rc < 0)
	207	goto fail;
8ceee660 BH	208
	209	rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
	210	if (rc < 0)
	211	goto fail;
	212
	213	rc = tenxpress_init(efx);
	214	if (rc < 0)
	215	goto fail;
	216
	217	schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
	218
	219	/* Let XGXS and SerDes out of reset and resets 10XPress */
	220	falcon_reset_xaui(efx);
	221
	222	return 0;
	223
	224	fail:
	225	kfree(efx->phy_data);
	226	efx->phy_data = NULL;
	227	return rc;
	228	}
	229
3273c2e8 BH	230	static int tenxpress_special_reset(struct efx_nic *efx)
	231	{
	232	int rc, reg;
	233
	234	EFX_TRACE(efx, "%s\n", __func__);
	235
	236	/* Initiate reset */
	237	reg = mdio_clause45_read(efx, efx->mii.phy_id,
	238	MDIO_MMD_PMAPMD, PMA_PMD_EXT_CTRL_REG);
	239	reg \|= (1 << PMA_PMD_EXT_SSR_LBN);
	240	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
	241	PMA_PMD_EXT_CTRL_REG, reg);
	242
	243	msleep(200);
	244
	245	/* Wait for the blocks to come out of reset */
	246	rc = mdio_clause45_wait_reset_mmds(efx,
	247	TENXPRESS_REQUIRED_DEVS);
	248	if (rc < 0)
	249	return rc;
	250
	251	/* Try and reconfigure the device */
	252	rc = tenxpress_init(efx);
	253	if (rc < 0)
	254	return rc;
	255
	256	return 0;
	257	}
	258
dc8cfa55	259	static void tenxpress_set_bad_lp(struct efx_nic *efx, bool bad_lp)
8ceee660 BH	260	{
	261	struct tenxpress_phy_data *pd = efx->phy_data;
	262	int reg;
	263
	264	/* Nothing to do if all is well and was previously so. */
	265	if (!(bad_lp \|\| pd->bad_lp_tries))
	266	return;
	267
	268	reg = mdio_clause45_read(efx, efx->mii.phy_id,
	269	MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG);
	270
	271	if (bad_lp)
	272	pd->bad_lp_tries++;
	273	else
	274	pd->bad_lp_tries = 0;
	275
	276	if (pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
	277	pd->bad_lp_tries = 0; /* Restart count */
	278	reg &= ~(PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN);
	279	reg \|= (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN);
	280	EFX_ERR(efx, "This NIC appears to be plugged into"
	281	" a port that is not 10GBASE-T capable.\n"
	282	" This PHY is 10GBASE-T ONLY, so no link can"
	283	" be established.\n");
	284	} else {
	285	reg \|= (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN);
	286	}
	287	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
	288	PMA_PMD_LED_OVERR_REG, reg);
	289	}
	290
	291	/* Check link status and return a boolean OK value. If the link is NOT
	292	* OK we have a quick rummage round to see if we appear to be plugged
	293	* into a non-10GBT port and if so warn the user that they won't get
	294	* link any time soon as we are 10GBT only, unless caller specified
	295	* not to do this check (it isn't useful in loopback) */
dc8cfa55	296	static bool tenxpress_link_ok(struct efx_nic *efx, bool check_lp)
8ceee660	297	{
dc8cfa55	298	bool ok = mdio_clause45_links_ok(efx, TENXPRESS_REQUIRED_DEVS);
8ceee660 BH	299
8ceee660 BH	300	if (ok) {
dc8cfa55	301	tenxpress_set_bad_lp(efx, false);
8ceee660 BH	302	} else if (check_lp) {
8ceee660 BH	303	/* Are we plugged into the wrong sort of link? */
dc8cfa55	304	bool bad_lp = false;
8ceee660 BH	305	int phy_id = efx->mii.phy_id;
	306	int an_stat = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
	307	MDIO_AN_STATUS);
	308	int xphy_stat = mdio_clause45_read(efx, phy_id,
	309	MDIO_MMD_PMAPMD,
	310	PMA_PMD_XSTATUS_REG);
	311	/* Are we plugged into anything that sends FLPs? If
	312	* not we can't distinguish between not being plugged
	313	* in and being plugged into a non-AN antique. The FLP
	314	* bit has the advantage of not clearing when autoneg
	315	* restarts. */
	316	if (!(xphy_stat & (1 << PMA_PMD_XSTAT_FLP_LBN))) {
dc8cfa55	317	tenxpress_set_bad_lp(efx, false);
8ceee660 BH	318	return ok;
	319	}
	320
	321	/* If it can do 10GBT it must be XNP capable */
	322	bad_lp = !(an_stat & (1 << MDIO_AN_STATUS_XNP_LBN));
	323	if (!bad_lp && (an_stat & (1 << MDIO_AN_STATUS_PAGE_LBN))) {
	324	bad_lp = !(mdio_clause45_read(efx, phy_id,
	325	MDIO_MMD_AN, MDIO_AN_10GBT_STATUS) &
	326	(1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN));
	327	}
	328	tenxpress_set_bad_lp(efx, bad_lp);
	329	}
	330	return ok;
	331	}
	332
3273c2e8 BH	333	static void tenxpress_phyxs_loopback(struct efx_nic *efx)
	334	{
	335	int phy_id = efx->mii.phy_id;
	336	int ctrl1, ctrl2;
	337
	338	ctrl1 = ctrl2 = mdio_clause45_read(efx, phy_id, MDIO_MMD_PHYXS,
	339	PHYXS_TEST1);
	340	if (efx->loopback_mode == LOOPBACK_PHYXS)
	341	ctrl2 \|= (1 << LOOPBACK_NEAR_LBN);
	342	else
	343	ctrl2 &= ~(1 << LOOPBACK_NEAR_LBN);
	344	if (ctrl1 != ctrl2)
	345	mdio_clause45_write(efx, phy_id, MDIO_MMD_PHYXS,
	346	PHYXS_TEST1, ctrl2);
	347	}
	348
8ceee660 BH	349	static void tenxpress_phy_reconfigure(struct efx_nic *efx)
8ceee660 BH	350	{
3273c2e8	351	struct tenxpress_phy_data *phy_data = efx->phy_data;
dc8cfa55 BH	352	bool loop_change = LOOPBACK_OUT_OF(phy_data, efx,
dc8cfa55 BH	353	TENXPRESS_LOOPBACKS);
3273c2e8	354
f8b87c17 BH	355	if (efx->phy_mode & PHY_MODE_SPECIAL) {
f8b87c17 BH	356	phy_data->phy_mode = efx->phy_mode;
8ceee660	357	return;
f8b87c17	358	}
8ceee660	359
3273c2e8 BH	360	/* When coming out of transmit disable, coming out of low power
	361	* mode, or moving out of any PHY internal loopback mode,
	362	* perform a special software reset */
f8b87c17 BH	363	if ((efx->phy_mode == PHY_MODE_NORMAL &&
f8b87c17 BH	364	phy_data->phy_mode != PHY_MODE_NORMAL) \|\|
3273c2e8	365	loop_change) {
91ad757c	366	tenxpress_special_reset(efx);
3273c2e8 BH	367	falcon_reset_xaui(efx);
	368	}
	369
	370	mdio_clause45_transmit_disable(efx);
	371	mdio_clause45_phy_reconfigure(efx);
	372	tenxpress_phyxs_loopback(efx);
	373
3273c2e8	374	phy_data->loopback_mode = efx->loopback_mode;
f8b87c17	375	phy_data->phy_mode = efx->phy_mode;
dc8cfa55	376	efx->link_up = tenxpress_link_ok(efx, false);
8ceee660 BH	377	efx->link_options = GM_LPA_10000FULL;
	378	}
	379
	380	static void tenxpress_phy_clear_interrupt(struct efx_nic *efx)
	381	{
	382	/* Nothing done here - LASI interrupts aren't reliable so poll */
	383	}
	384
	385
	386	/* Poll PHY for interrupt */
	387	static int tenxpress_phy_check_hw(struct efx_nic *efx)
	388	{
	389	struct tenxpress_phy_data *phy_data = efx->phy_data;
dc8cfa55	390	bool link_ok;
8ceee660	391
f8b87c17 BH	392	link_ok = (phy_data->phy_mode == PHY_MODE_NORMAL &&
f8b87c17 BH	393	tenxpress_link_ok(efx, true));
8ceee660 BH	394
	395	if (link_ok != efx->link_up)
	396	falcon_xmac_sim_phy_event(efx);
	397
f8b87c17	398	if (phy_data->phy_mode != PHY_MODE_NORMAL)
8ceee660 BH	399	return 0;
	400
	401	if (atomic_read(&phy_data->bad_crc_count) > crc_error_reset_threshold) {
	402	EFX_ERR(efx, "Resetting XAUI due to too many CRC errors\n");
	403	falcon_reset_xaui(efx);
	404	atomic_set(&phy_data->bad_crc_count, 0);
	405	}
	406
	407	return 0;
	408	}
	409
	410	static void tenxpress_phy_fini(struct efx_nic *efx)
	411	{
	412	int reg;
	413
	414	/* Power down the LNPGA */
	415	reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
	416	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
	417	PMA_PMD_XCONTROL_REG, reg);
	418
	419	/* Waiting here ensures that the board fini, which can turn off the
	420	* power to the PHY, won't get run until the LNPGA powerdown has been
	421	* given long enough to complete. */
	422	schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
	423
	424	kfree(efx->phy_data);
	425	efx->phy_data = NULL;
	426	}
	427
	428
	429	/* Set the RX and TX LEDs and Link LED flashing. The other LEDs
	430	* (which probably aren't wired anyway) are left in AUTO mode */
dc8cfa55	431	void tenxpress_phy_blink(struct efx_nic *efx, bool blink)
8ceee660 BH	432	{
	433	int reg;
	434
	435	if (blink)
	436	reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) \|
	437	(PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) \|
	438	(PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN);
	439	else
	440	reg = PMA_PMD_LED_DEFAULT;
	441
	442	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
	443	PMA_PMD_LED_OVERR_REG, reg);
	444	}
	445
	446	static void tenxpress_reset_xaui(struct efx_nic *efx)
	447	{
	448	int phy = efx->mii.phy_id;
	449	int clk_ctrl, test_select, soft_rst2;
	450
	451	/* Real work is done on clock_ctrl other resets are thought to be
	452	* optional but make the reset more reliable
	453	*/
	454
	455	/* Read */
	456	clk_ctrl = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
	457	PCS_CLOCK_CTRL_REG);
	458	test_select = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
	459	PCS_TEST_SELECT_REG);
	460	soft_rst2 = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
	461	PCS_SOFT_RST2_REG);
	462
	463	/* Put in reset */
	464	test_select &= ~(1 << CLK312_EN_LBN);
	465	mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
	466	PCS_TEST_SELECT_REG, test_select);
	467
	468	soft_rst2 &= ~((1 << XGXS_RST_N_LBN) \| (1 << SERDES_RST_N_LBN));
	469	mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
	470	PCS_SOFT_RST2_REG, soft_rst2);
	471
	472	clk_ctrl &= ~(1 << PLL312_RST_N_LBN);
	473	mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
	474	PCS_CLOCK_CTRL_REG, clk_ctrl);
	475	udelay(10);
	476
	477	/* Remove reset */
	478	clk_ctrl \|= (1 << PLL312_RST_N_LBN);
	479	mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
	480	PCS_CLOCK_CTRL_REG, clk_ctrl);
	481	udelay(10);
	482
	483	soft_rst2 \|= ((1 << XGXS_RST_N_LBN) \| (1 << SERDES_RST_N_LBN));
	484	mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
	485	PCS_SOFT_RST2_REG, soft_rst2);
	486	udelay(10);
	487
	488	test_select \|= (1 << CLK312_EN_LBN);
	489	mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
	490	PCS_TEST_SELECT_REG, test_select);
	491	udelay(10);
	492	}
	493
	494	struct efx_phy_operations falcon_tenxpress_phy_ops = {
	495	.init = tenxpress_phy_init,
496	.reconfigure = tenxpress_phy_reconfigure,
497	.check_hw = tenxpress_phy_check_hw,
498	.fini = tenxpress_phy_fini,
499	.clear_interrupt = tenxpress_phy_clear_interrupt,
500	.reset_xaui = tenxpress_reset_xaui,
501	.mmds = TENXPRESS_REQUIRED_DEVS,
3273c2e8	502	.loopbacks = TENXPRESS_LOOPBACKS,
8ceee660	503	};