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sfc: Generate unique names for per-NIC workqueues
[net-next-2.6.git] / drivers / net / sfc / tenxpress.c
CommitLineData
8ceee660 1/****************************************************************************
177dfcd8
BH		 2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2007-2008 Solarflare Communications Inc.
8ceee660
BH		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include <linux/delay.h>
11#include <linux/seq_file.h>
12#include "efx.h"
8ceee660
BH		 13#include "mdio_10g.h"
14#include "falcon.h"
15#include "phy.h"
16#include "falcon_hwdefs.h"
17#include "boards.h"
e6fa2eb7
BH		 18#include "workarounds.h"
19#include "selftest.h"
8ceee660 20
e6fa2eb7
BH		 21/* We expect these MMDs to be in the package. SFT9001 also has a
22 * clause 22 extension MMD, but since it doesn't have all the generic
23 * MMD registers it is pointless to include it here.
24 */
27dd2cac
BH		 25#define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS_PMAPMD | \
26 MDIO_MMDREG_DEVS_PCS | \
04cc8cac
BH		 27 MDIO_MMDREG_DEVS_PHYXS | \
28 MDIO_MMDREG_DEVS_AN)
8ceee660 29
e6fa2eb7
BH		 30#define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
31 (1 << LOOPBACK_PCS) | \
32 (1 << LOOPBACK_PMAPMD) | \
33 (1 << LOOPBACK_NETWORK))
34
35#define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \
36 (1 << LOOPBACK_PHYXS) | \
37 (1 << LOOPBACK_PCS) | \
38 (1 << LOOPBACK_PMAPMD) | \
39 (1 << LOOPBACK_NETWORK))
3273c2e8 40
8ceee660
BH		 41/* We complain if we fail to see the link partner as 10G capable this many
42 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
43 */
44#define MAX_BAD_LP_TRIES (5)
45
e6fa2eb7
BH		 46/* LASI Control */
47#define PMA_PMD_LASI_CTRL 36866
48#define PMA_PMD_LASI_STATUS 36869
49#define PMA_PMD_LS_ALARM_LBN 0
50#define PMA_PMD_LS_ALARM_WIDTH 1
51#define PMA_PMD_TX_ALARM_LBN 1
52#define PMA_PMD_TX_ALARM_WIDTH 1
53#define PMA_PMD_RX_ALARM_LBN 2
54#define PMA_PMD_RX_ALARM_WIDTH 1
55#define PMA_PMD_AN_ALARM_LBN 3
56#define PMA_PMD_AN_ALARM_WIDTH 1
57
8ceee660 58/* Extended control register */
e6fa2eb7
BH		 59#define PMA_PMD_XCONTROL_REG 49152
60#define PMA_PMD_EXT_GMII_EN_LBN 1
61#define PMA_PMD_EXT_GMII_EN_WIDTH 1
62#define PMA_PMD_EXT_CLK_OUT_LBN 2
63#define PMA_PMD_EXT_CLK_OUT_WIDTH 1
64#define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */
65#define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
66#define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */
67#define PMA_PMD_EXT_CLK312_WIDTH 1
68#define PMA_PMD_EXT_LPOWER_LBN 12
69#define PMA_PMD_EXT_LPOWER_WIDTH 1
70#define PMA_PMD_EXT_SSR_LBN 15
71#define PMA_PMD_EXT_SSR_WIDTH 1
8ceee660
BH		 72
73/* extended status register */
e6fa2eb7 74#define PMA_PMD_XSTATUS_REG 49153
8ceee660
BH		 75#define PMA_PMD_XSTAT_FLP_LBN (12)
76
77/* LED control register */
e6fa2eb7 78#define PMA_PMD_LED_CTRL_REG 49159
8ceee660
BH		 79#define PMA_PMA_LED_ACTIVITY_LBN (3)
80
81/* LED function override register */
e6fa2eb7 82#define PMA_PMD_LED_OVERR_REG 49161
8ceee660
BH		 83/* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
84#define PMA_PMD_LED_LINK_LBN (0)
85#define PMA_PMD_LED_SPEED_LBN (2)
86#define PMA_PMD_LED_TX_LBN (4)
87#define PMA_PMD_LED_RX_LBN (6)
88/* Override settings */
89#define PMA_PMD_LED_AUTO (0) /* H/W control */
90#define PMA_PMD_LED_ON (1)
91#define PMA_PMD_LED_OFF (2)
92#define PMA_PMD_LED_FLASH (3)
04cc8cac 93#define PMA_PMD_LED_MASK 3
8ceee660
BH		 94/* All LEDs under hardware control */
95#define PMA_PMD_LED_FULL_AUTO (0)
96/* Green and Amber under hardware control, Red off */
97#define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
98
e6fa2eb7
BH		 99#define PMA_PMD_SPEED_ENABLE_REG 49192
100#define PMA_PMD_100TX_ADV_LBN 1
101#define PMA_PMD_100TX_ADV_WIDTH 1
102#define PMA_PMD_1000T_ADV_LBN 2
103#define PMA_PMD_1000T_ADV_WIDTH 1
104#define PMA_PMD_10000T_ADV_LBN 3
105#define PMA_PMD_10000T_ADV_WIDTH 1
106#define PMA_PMD_SPEED_LBN 4
107#define PMA_PMD_SPEED_WIDTH 4
108
109/* Serdes control registers - SFT9001 only */
110#define PMA_PMD_CSERDES_CTRL_REG 64258
111/* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */
112#define PMA_PMD_CSERDES_DEFAULT 0x000f
113
114/* Misc register defines - SFX7101 only */
115#define PCS_CLOCK_CTRL_REG 55297
8ceee660
BH		 116#define PLL312_RST_N_LBN 2
117
e6fa2eb7 118#define PCS_SOFT_RST2_REG 55302
8ceee660
BH		 119#define SERDES_RST_N_LBN 13
120#define XGXS_RST_N_LBN 12
121
e6fa2eb7 122#define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
8ceee660
BH		 123#define CLK312_EN_LBN 3
124
3273c2e8 125/* PHYXS registers */
e6fa2eb7
BH		 126#define PHYXS_XCONTROL_REG 49152
127#define PHYXS_RESET_LBN 15
128#define PHYXS_RESET_WIDTH 1
129
3273c2e8
BH		 130#define PHYXS_TEST1 (49162)
131#define LOOPBACK_NEAR_LBN (8)
132#define LOOPBACK_NEAR_WIDTH (1)
133
e6fa2eb7
BH		 134#define PCS_10GBASET_STAT1 32
135#define PCS_10GBASET_BLKLK_LBN 0
136#define PCS_10GBASET_BLKLK_WIDTH 1
137
8ceee660 138/* Boot status register */
e6fa2eb7 139#define PCS_BOOT_STATUS_REG 53248
8ceee660
BH		 140#define PCS_BOOT_FATAL_ERR_LBN (0)
141#define PCS_BOOT_PROGRESS_LBN (1)
142#define PCS_BOOT_PROGRESS_WIDTH (2)
143#define PCS_BOOT_COMPLETE_LBN (3)
e6fa2eb7 144
8ceee660
BH		 145#define PCS_BOOT_MAX_DELAY (100)
146#define PCS_BOOT_POLL_DELAY (10)
147
e6fa2eb7
BH		 148/* 100M/1G PHY registers */
149#define GPHY_XCONTROL_REG 49152
150#define GPHY_ISOLATE_LBN 10
151#define GPHY_ISOLATE_WIDTH 1
152#define GPHY_DUPLEX_LBN 8
153#define GPHY_DUPLEX_WIDTH 1
154#define GPHY_LOOPBACK_NEAR_LBN 14
155#define GPHY_LOOPBACK_NEAR_WIDTH 1
156
157#define C22EXT_STATUS_REG 49153
158#define C22EXT_STATUS_LINK_LBN 2
159#define C22EXT_STATUS_LINK_WIDTH 1
160
161#define C22EXT_MSTSLV_REG 49162
162#define C22EXT_MSTSLV_1000_HD_LBN 10
163#define C22EXT_MSTSLV_1000_HD_WIDTH 1
164#define C22EXT_MSTSLV_1000_FD_LBN 11
165#define C22EXT_MSTSLV_1000_FD_WIDTH 1
166
8ceee660
BH		 167/* Time to wait between powering down the LNPGA and turning off the power
168 * rails */
169#define LNPGA_PDOWN_WAIT (HZ / 5)
170
171static int crc_error_reset_threshold = 100;
172module_param(crc_error_reset_threshold, int, 0644);
173MODULE_PARM_DESC(crc_error_reset_threshold,
174 "Max number of CRC errors before XAUI reset");
175
176struct tenxpress_phy_data {
3273c2e8 177 enum efx_loopback_mode loopback_mode;
8ceee660 178 atomic_t bad_crc_count;
f8b87c17 179 enum efx_phy_mode phy_mode;
8ceee660
BH		 180 int bad_lp_tries;
181};
182
8ceee660
BH		 183void tenxpress_crc_err(struct efx_nic *efx)
184{
185 struct tenxpress_phy_data *phy_data = efx->phy_data;
186 if (phy_data != NULL)
187 atomic_inc(&phy_data->bad_crc_count);
188}
189
e6fa2eb7
BH		 190static ssize_t show_phy_short_reach(struct device *dev,
191 struct device_attribute *attr, char *buf)
192{
193 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
194 int reg;
195
196 reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
197 MDIO_PMAPMD_10GBT_TXPWR);
198 return sprintf(buf, "%d\n",
199 !!(reg & (1 << MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN)));
200}
201
202static ssize_t set_phy_short_reach(struct device *dev,
203 struct device_attribute *attr,
204 const char *buf, size_t count)
205{
206 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
207
208 rtnl_lock();
209 mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
210 MDIO_PMAPMD_10GBT_TXPWR,
211 MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN,
212 count != 0 && *buf != '0');
213 efx_reconfigure_port(efx);
214 rtnl_unlock();
215
216 return count;
217}
218
219static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach,
220 set_phy_short_reach);
221
8ceee660
BH		 222/* Check that the C166 has booted successfully */
223static int tenxpress_phy_check(struct efx_nic *efx)
224{
225 int phy_id = efx->mii.phy_id;
226 int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY;
227 int boot_stat;
228
229 /* Wait for the boot to complete (or not) */
230 while (count) {
231 boot_stat = mdio_clause45_read(efx, phy_id,
232 MDIO_MMD_PCS,
233 PCS_BOOT_STATUS_REG);
234 if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN))
235 break;
236 count--;
237 udelay(PCS_BOOT_POLL_DELAY);
238 }
239
240 if (!count) {
241 EFX_ERR(efx, "%s: PHY boot timed out. Last status "
242 "%x\n", __func__,
243 (boot_stat >> PCS_BOOT_PROGRESS_LBN) &
244 ((1 << PCS_BOOT_PROGRESS_WIDTH) - 1));
245 return -ETIMEDOUT;
246 }
247
248 return 0;
249}
250
8ceee660
BH		 251static int tenxpress_init(struct efx_nic *efx)
252{
e6fa2eb7
BH		 253 int phy_id = efx->mii.phy_id;
254 int reg;
255 int rc;
8ceee660 256
e6fa2eb7
BH		 257 if (efx->phy_type == PHY_TYPE_SFX7101) {
258 /* Enable 312.5 MHz clock */
259 mdio_clause45_write(efx, phy_id,
260 MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
261 1 << CLK312_EN_LBN);
262 } else {
263 /* Enable 312.5 MHz clock and GMII */
264 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
265 PMA_PMD_XCONTROL_REG);
266 reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) |
267 (1 << PMA_PMD_EXT_CLK_OUT_LBN) |
268 (1 << PMA_PMD_EXT_CLK312_LBN));
269 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
270 PMA_PMD_XCONTROL_REG, reg);
271 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
272 GPHY_XCONTROL_REG, GPHY_ISOLATE_LBN,
273 false);
274 }
8ceee660
BH		 275
276 rc = tenxpress_phy_check(efx);
277 if (rc < 0)
278 return rc;
279
280 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
e6fa2eb7
BH		 281 if (efx->phy_type == PHY_TYPE_SFX7101) {
282 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD,
283 PMA_PMD_LED_CTRL_REG,
284 PMA_PMA_LED_ACTIVITY_LBN,
285 true);
286 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
287 PMA_PMD_LED_OVERR_REG, PMA_PMD_LED_DEFAULT);
288 }
8ceee660
BH		 289
290 return rc;
291}
292
293static int tenxpress_phy_init(struct efx_nic *efx)
294{
295 struct tenxpress_phy_data *phy_data;
296 int rc = 0;
297
298 phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
9b7bfc4c
BH		 299 if (!phy_data)
300 return -ENOMEM;
8ceee660 301 efx->phy_data = phy_data;
f8b87c17 302 phy_data->phy_mode = efx->phy_mode;
8ceee660 303
e6fa2eb7
BH		 304 if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
305 if (efx->phy_type == PHY_TYPE_SFT9001A) {
306 int reg;
307 reg = mdio_clause45_read(efx, efx->mii.phy_id,
308 MDIO_MMD_PMAPMD,
309 PMA_PMD_XCONTROL_REG);
310 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
311 mdio_clause45_write(efx, efx->mii.phy_id,
312 MDIO_MMD_PMAPMD,
313 PMA_PMD_XCONTROL_REG, reg);
314 mdelay(200);
315 }
8ceee660 316
e6fa2eb7
BH		 317 rc = mdio_clause45_wait_reset_mmds(efx,
318 TENXPRESS_REQUIRED_DEVS);
319 if (rc < 0)
320 goto fail;
321
322 rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
323 if (rc < 0)
324 goto fail;
325 }
8ceee660
BH		 326
327 rc = tenxpress_init(efx);
328 if (rc < 0)
329 goto fail;
330
e6fa2eb7
BH		 331 if (efx->phy_type == PHY_TYPE_SFT9001B) {
332 rc = device_create_file(&efx->pci_dev->dev,
333 &dev_attr_phy_short_reach);
334 if (rc)
335 goto fail;
336 }
337
8ceee660
BH		 338 schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
339
e6fa2eb7 340 /* Let XGXS and SerDes out of reset */
8ceee660
BH		 341 falcon_reset_xaui(efx);
342
343 return 0;
344
345 fail:
346 kfree(efx->phy_data);
347 efx->phy_data = NULL;
348 return rc;
349}
350
e6fa2eb7
BH		 351/* Perform a "special software reset" on the PHY. The caller is
352 * responsible for saving and restoring the PHY hardware registers
353 * properly, and masking/unmasking LASI */
3273c2e8
BH		 354static int tenxpress_special_reset(struct efx_nic *efx)
355{
356 int rc, reg;
357
c8fcc49c
BH		 358 /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so
359 * a special software reset can glitch the XGMAC sufficiently for stats
e6fa2eb7 360 * requests to fail. Since we don't often special_reset, just lock. */
c8fcc49c 361 spin_lock(&efx->stats_lock);
3273c2e8
BH		 362
363 /* Initiate reset */
364 reg = mdio_clause45_read(efx, efx->mii.phy_id,
e6fa2eb7 365 MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
3273c2e8
BH		 366 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
367 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
e6fa2eb7 368 PMA_PMD_XCONTROL_REG, reg);
3273c2e8 369
c8fcc49c 370 mdelay(200);
3273c2e8
BH		 371
372 /* Wait for the blocks to come out of reset */
373 rc = mdio_clause45_wait_reset_mmds(efx,
374 TENXPRESS_REQUIRED_DEVS);
375 if (rc < 0)
c8fcc49c 376 goto unlock;
3273c2e8
BH		 377
378 /* Try and reconfigure the device */
379 rc = tenxpress_init(efx);
380 if (rc < 0)
c8fcc49c 381 goto unlock;
3273c2e8 382
e6fa2eb7
BH		 383 /* Wait for the XGXS state machine to churn */
384 mdelay(10);
c8fcc49c
BH		 385unlock:
386 spin_unlock(&efx->stats_lock);
387 return rc;
3273c2e8
BH		 388}
389
e6fa2eb7 390static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
8ceee660
BH		 391{
392 struct tenxpress_phy_data *pd = efx->phy_data;
04cc8cac
BH		 393 int phy_id = efx->mii.phy_id;
394 bool bad_lp;
8ceee660
BH		 395 int reg;
396
04cc8cac
BH		 397 if (link_ok) {
398 bad_lp = false;
399 } else {
400 /* Check that AN has started but not completed. */
401 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
402 MDIO_AN_STATUS);
403 if (!(reg & (1 << MDIO_AN_STATUS_LP_AN_CAP_LBN)))
404 return; /* LP status is unknown */
405 bad_lp = !(reg & (1 << MDIO_AN_STATUS_AN_DONE_LBN));
406 if (bad_lp)
407 pd->bad_lp_tries++;
408 }
409
8ceee660 410 /* Nothing to do if all is well and was previously so. */
04cc8cac 411 if (!pd->bad_lp_tries)
8ceee660
BH		 412 return;
413
04cc8cac
BH		 414 /* Use the RX (red) LED as an error indicator once we've seen AN
415 * failure several times in a row, and also log a message. */
416 if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
417 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
418 PMA_PMD_LED_OVERR_REG);
419 reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
420 if (!bad_lp) {
421 reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
422 } else {
423 reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
424 EFX_ERR(efx, "appears to be plugged into a port"
425 " that is not 10GBASE-T capable. The PHY"
426 " supports 10GBASE-T ONLY, so no link can"
427 " be established\n");
428 }
429 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
430 PMA_PMD_LED_OVERR_REG, reg);
431 pd->bad_lp_tries = bad_lp;
8ceee660 432 }
8ceee660
BH		 433}
434
e6fa2eb7 435static bool sfx7101_link_ok(struct efx_nic *efx)
8ceee660 436{
e6fa2eb7
BH		 437 return mdio_clause45_links_ok(efx,
438 MDIO_MMDREG_DEVS_PMAPMD |
439 MDIO_MMDREG_DEVS_PCS |
440 MDIO_MMDREG_DEVS_PHYXS);
441}
442
443static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd)
444{
445 int phy_id = efx->mii.phy_id;
446 u32 reg;
447
448 if (efx->loopback_mode == LOOPBACK_GPHY)
449 return true;
450 else if (efx_phy_mode_disabled(efx->phy_mode))
451 return false;
452 else if (efx->loopback_mode)
04cc8cac
BH		 453 return mdio_clause45_links_ok(efx,
454 MDIO_MMDREG_DEVS_PMAPMD |
455 MDIO_MMDREG_DEVS_PCS |
456 MDIO_MMDREG_DEVS_PHYXS);
e6fa2eb7
BH		 457
458 /* We must use the same definition of link state as LASI,
459 * otherwise we can miss a link state transition
460 */
461 if (ecmd->speed == 10000) {
462 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS,
463 PCS_10GBASET_STAT1);
464 return reg & (1 << PCS_10GBASET_BLKLK_LBN);
465 } else {
466 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT,
467 C22EXT_STATUS_REG);
468 return reg & (1 << C22EXT_STATUS_LINK_LBN);
469 }
8ceee660
BH		 470}
471
e6fa2eb7 472static void tenxpress_ext_loopback(struct efx_nic *efx)
3273c2e8
BH		 473{
474 int phy_id = efx->mii.phy_id;
3273c2e8 475
e6fa2eb7
BH		 476 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS,
477 PHYXS_TEST1, LOOPBACK_NEAR_LBN,
478 efx->loopback_mode == LOOPBACK_PHYXS);
479 if (efx->phy_type != PHY_TYPE_SFX7101)
480 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
481 GPHY_XCONTROL_REG,
482 GPHY_LOOPBACK_NEAR_LBN,
483 efx->loopback_mode == LOOPBACK_GPHY);
484}
485
486static void tenxpress_low_power(struct efx_nic *efx)
487{
488 int phy_id = efx->mii.phy_id;
489
490 if (efx->phy_type == PHY_TYPE_SFX7101)
491 mdio_clause45_set_mmds_lpower(
492 efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
493 TENXPRESS_REQUIRED_DEVS);
3273c2e8 494 else
e6fa2eb7
BH		 495 mdio_clause45_set_flag(
496 efx, phy_id, MDIO_MMD_PMAPMD,
497 PMA_PMD_XCONTROL_REG, PMA_PMD_EXT_LPOWER_LBN,
498 !!(efx->phy_mode & PHY_MODE_LOW_POWER));
3273c2e8
BH		 499}
500
8ceee660
BH		 501static void tenxpress_phy_reconfigure(struct efx_nic *efx)
502{
3273c2e8 503 struct tenxpress_phy_data *phy_data = efx->phy_data;
e6fa2eb7
BH		 504 struct ethtool_cmd ecmd;
505 bool phy_mode_change, loop_reset, loop_toggle, loopback;
3273c2e8 506
e6fa2eb7 507 if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) {
f8b87c17 508 phy_data->phy_mode = efx->phy_mode;
8ceee660 509 return;
f8b87c17 510 }
8ceee660 511
e6fa2eb7
BH		 512 tenxpress_low_power(efx);
513
514 phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
515 phy_data->phy_mode != PHY_MODE_NORMAL);
516 loopback = LOOPBACK_MASK(efx) & efx->phy_op->loopbacks;
517 loop_toggle = LOOPBACK_CHANGED(phy_data, efx, efx->phy_op->loopbacks);
518 loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, efx->phy_op->loopbacks) ||
519 LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));
520
521 if (loop_reset || loop_toggle || loopback || phy_mode_change) {
522 int rc;
523
524 efx->phy_op->get_settings(efx, &ecmd);
525
526 if (loop_reset || phy_mode_change) {
527 tenxpress_special_reset(efx);
528
529 /* Reset XAUI if we were in 10G, and are staying
530 * in 10G. If we're moving into and out of 10G
531 * then xaui will be reset anyway */
532 if (EFX_IS10G(efx))
533 falcon_reset_xaui(efx);
534 }
535
536 if (efx->phy_type != PHY_TYPE_SFX7101) {
537 /* Only change autoneg once, on coming out or
538 * going into loopback */
539 if (loop_toggle)
540 ecmd.autoneg = !loopback;
541 if (loopback) {
542 ecmd.duplex = DUPLEX_FULL;
543 if (efx->loopback_mode == LOOPBACK_GPHY)
544 ecmd.speed = SPEED_1000;
545 else
546 ecmd.speed = SPEED_10000;
547 }
548 }
549
550 rc = efx->phy_op->set_settings(efx, &ecmd);
551 WARN_ON(rc);
3273c2e8
BH		 552 }
553
554 mdio_clause45_transmit_disable(efx);
555 mdio_clause45_phy_reconfigure(efx);
e6fa2eb7 556 tenxpress_ext_loopback(efx);
3273c2e8 557
3273c2e8 558 phy_data->loopback_mode = efx->loopback_mode;
f8b87c17 559 phy_data->phy_mode = efx->phy_mode;
e6fa2eb7
BH		 560
561 if (efx->phy_type == PHY_TYPE_SFX7101) {
562 efx->link_speed = 10000;
563 efx->link_fd = true;
564 efx->link_up = sfx7101_link_ok(efx);
565 } else {
566 efx->phy_op->get_settings(efx, &ecmd);
567 efx->link_speed = ecmd.speed;
568 efx->link_fd = ecmd.duplex == DUPLEX_FULL;
569 efx->link_up = sft9001_link_ok(efx, &ecmd);
570 }
04cc8cac 571 efx->link_fc = mdio_clause45_get_pause(efx);
8ceee660
BH		 572}
573
8ceee660 574/* Poll PHY for interrupt */
766ca0fa 575static void tenxpress_phy_poll(struct efx_nic *efx)
8ceee660
BH		 576{
577 struct tenxpress_phy_data *phy_data = efx->phy_data;
766ca0fa
BH		 578 bool change = false, link_ok;
579 unsigned link_fc;
8ceee660 580
e6fa2eb7
BH		 581 if (efx->phy_type == PHY_TYPE_SFX7101) {
582 link_ok = sfx7101_link_ok(efx);
583 if (link_ok != efx->link_up) {
584 change = true;
585 } else {
586 link_fc = mdio_clause45_get_pause(efx);
587 if (link_fc != efx->link_fc)
588 change = true;
589 }
590 sfx7101_check_bad_lp(efx, link_ok);
766ca0fa 591 } else {
e6fa2eb7
BH		 592 u32 status = mdio_clause45_read(efx, efx->mii.phy_id,
593 MDIO_MMD_PMAPMD,
594 PMA_PMD_LASI_STATUS);
595 if (status & (1 << PMA_PMD_LS_ALARM_LBN))
766ca0fa
BH		 596 change = true;
597 }
8ceee660 598
766ca0fa 599 if (change)
177dfcd8 600 falcon_sim_phy_event(efx);
8ceee660 601
f8b87c17 602 if (phy_data->phy_mode != PHY_MODE_NORMAL)
766ca0fa 603 return;
8ceee660 604
e6fa2eb7
BH		 605 if (EFX_WORKAROUND_10750(efx) &&
606 atomic_read(&phy_data->bad_crc_count) > crc_error_reset_threshold) {
8ceee660
BH		 607 EFX_ERR(efx, "Resetting XAUI due to too many CRC errors\n");
608 falcon_reset_xaui(efx);
609 atomic_set(&phy_data->bad_crc_count, 0);
610 }
8ceee660
BH		 611}
612
613static void tenxpress_phy_fini(struct efx_nic *efx)
614{
615 int reg;
616
e6fa2eb7
BH		 617 if (efx->phy_type == PHY_TYPE_SFT9001B) {
618 device_remove_file(&efx->pci_dev->dev,
619 &dev_attr_phy_short_reach);
620 } else {
621 /* Power down the LNPGA */
622 reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
623 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
624 PMA_PMD_XCONTROL_REG, reg);
625
626 /* Waiting here ensures that the board fini, which can turn
627 * off the power to the PHY, won't get run until the LNPGA
628 * powerdown has been given long enough to complete. */
629 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
630 }
8ceee660
BH		 631
632 kfree(efx->phy_data);
633 efx->phy_data = NULL;
634}
635
636
637/* Set the RX and TX LEDs and Link LED flashing. The other LEDs
638 * (which probably aren't wired anyway) are left in AUTO mode */
dc8cfa55 639void tenxpress_phy_blink(struct efx_nic *efx, bool blink)
8ceee660
BH		 640{
641 int reg;
642
643 if (blink)
644 reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) |
645 (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) |
646 (PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN);
647 else
648 reg = PMA_PMD_LED_DEFAULT;
649
650 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
651 PMA_PMD_LED_OVERR_REG, reg);
652}
653
8c8661e4
BH		 654static int tenxpress_phy_test(struct efx_nic *efx)
655{
656 /* BIST is automatically run after a special software reset */
657 return tenxpress_special_reset(efx);
658}
659
04cc8cac
BH		 660static u32 tenxpress_get_xnp_lpa(struct efx_nic *efx)
661{
662 int phy = efx->mii.phy_id;
663 u32 lpa = 0;
664 int reg;
665
e6fa2eb7
BH		 666 if (efx->phy_type != PHY_TYPE_SFX7101) {
667 reg = mdio_clause45_read(efx, phy, MDIO_MMD_C22EXT,
668 C22EXT_MSTSLV_REG);
669 if (reg & (1 << C22EXT_MSTSLV_1000_HD_LBN))
670 lpa |= ADVERTISED_1000baseT_Half;
671 if (reg & (1 << C22EXT_MSTSLV_1000_FD_LBN))
672 lpa |= ADVERTISED_1000baseT_Full;
673 }
04cc8cac
BH		 674 reg = mdio_clause45_read(efx, phy, MDIO_MMD_AN, MDIO_AN_10GBT_STATUS);
675 if (reg & (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN))
676 lpa |= ADVERTISED_10000baseT_Full;
677 return lpa;
678}
679
e6fa2eb7 680static void sfx7101_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
04cc8cac
BH		 681{
682 mdio_clause45_get_settings_ext(efx, ecmd, ADVERTISED_10000baseT_Full,
683 tenxpress_get_xnp_lpa(efx));
684 ecmd->supported |= SUPPORTED_10000baseT_Full;
685 ecmd->advertising |= ADVERTISED_10000baseT_Full;
686}
687
e6fa2eb7
BH		 688static void sft9001_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
689{
690 int phy_id = efx->mii.phy_id;
691 u32 xnp_adv = 0;
692 int reg;
693
694 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
695 PMA_PMD_SPEED_ENABLE_REG);
696 if (EFX_WORKAROUND_13204(efx) && (reg & (1 << PMA_PMD_100TX_ADV_LBN)))
697 xnp_adv |= ADVERTISED_100baseT_Full;
698 if (reg & (1 << PMA_PMD_1000T_ADV_LBN))
699 xnp_adv |= ADVERTISED_1000baseT_Full;
700 if (reg & (1 << PMA_PMD_10000T_ADV_LBN))
701 xnp_adv |= ADVERTISED_10000baseT_Full;
702
703 mdio_clause45_get_settings_ext(efx, ecmd, xnp_adv,
704 tenxpress_get_xnp_lpa(efx));
705
706 ecmd->supported |= (SUPPORTED_100baseT_Half |
707 SUPPORTED_100baseT_Full |
708 SUPPORTED_1000baseT_Full);
709
710 /* Use the vendor defined C22ext register for duplex settings */
711 if (ecmd->speed != SPEED_10000 && !ecmd->autoneg) {
712 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT,
713 GPHY_XCONTROL_REG);
714 ecmd->duplex = (reg & (1 << GPHY_DUPLEX_LBN) ?
715 DUPLEX_FULL : DUPLEX_HALF);
716 }
717}
718
719static int sft9001_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
720{
721 int phy_id = efx->mii.phy_id;
722 int rc;
723
724 rc = mdio_clause45_set_settings(efx, ecmd);
725 if (rc)
726 return rc;
727
728 if (ecmd->speed != SPEED_10000 && !ecmd->autoneg)
729 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
730 GPHY_XCONTROL_REG, GPHY_DUPLEX_LBN,
731 ecmd->duplex == DUPLEX_FULL);
732
733 return rc;
734}
735
736static bool sft9001_set_xnp_advertise(struct efx_nic *efx, u32 advertising)
737{
738 int phy = efx->mii.phy_id;
739 int reg = mdio_clause45_read(efx, phy, MDIO_MMD_PMAPMD,
740 PMA_PMD_SPEED_ENABLE_REG);
741 bool enabled;
742
743 reg &= ~((1 << 2) | (1 << 3));
744 if (EFX_WORKAROUND_13204(efx) &&
745 (advertising & ADVERTISED_100baseT_Full))
746 reg |= 1 << PMA_PMD_100TX_ADV_LBN;
747 if (advertising & ADVERTISED_1000baseT_Full)
748 reg |= 1 << PMA_PMD_1000T_ADV_LBN;
749 if (advertising & ADVERTISED_10000baseT_Full)
750 reg |= 1 << PMA_PMD_10000T_ADV_LBN;
751 mdio_clause45_write(efx, phy, MDIO_MMD_PMAPMD,
752 PMA_PMD_SPEED_ENABLE_REG, reg);
753
754 enabled = (advertising &
755 (ADVERTISED_1000baseT_Half |
756 ADVERTISED_1000baseT_Full |
757 ADVERTISED_10000baseT_Full));
758 if (EFX_WORKAROUND_13204(efx))
759 enabled |= (advertising & ADVERTISED_100baseT_Full);
760 return enabled;
761}
762
763struct efx_phy_operations falcon_sfx7101_phy_ops = {
177dfcd8 764 .macs = EFX_XMAC,
8ceee660
BH		 765 .init = tenxpress_phy_init,
766 .reconfigure = tenxpress_phy_reconfigure,
766ca0fa 767 .poll = tenxpress_phy_poll,
8ceee660 768 .fini = tenxpress_phy_fini,
766ca0fa 769 .clear_interrupt = efx_port_dummy_op_void,
8c8661e4 770 .test = tenxpress_phy_test,
e6fa2eb7 771 .get_settings = sfx7101_get_settings,
177dfcd8 772 .set_settings = mdio_clause45_set_settings,
8ceee660 773 .mmds = TENXPRESS_REQUIRED_DEVS,
e6fa2eb7
BH		 774 .loopbacks = SFX7101_LOOPBACKS,
775};
776
777struct efx_phy_operations falcon_sft9001_phy_ops = {
778 .macs = EFX_GMAC | EFX_XMAC,
779 .init = tenxpress_phy_init,
780 .reconfigure = tenxpress_phy_reconfigure,
781 .poll = tenxpress_phy_poll,
782 .fini = tenxpress_phy_fini,
783 .clear_interrupt = efx_port_dummy_op_void,
784 .test = tenxpress_phy_test,
785 .get_settings = sft9001_get_settings,
786 .set_settings = sft9001_set_settings,
787 .set_xnp_advertise = sft9001_set_xnp_advertise,
788 .mmds = TENXPRESS_REQUIRED_DEVS,
789 .loopbacks = SFT9001_LOOPBACKS,
8ceee660 790};
Clone of davem's net-next-2.6 tree