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sfc: Extend loopback mode enumeration
[net-next-2.6.git] / drivers / net / sfc / qt202x_phy.c
CommitLineData
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1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2006-2008 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9/*
b37b62fe 10 * Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details
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11 */
12
13#include <linux/timer.h>
14#include <linux/delay.h>
15#include "efx.h"
8ceee660 16#include "mdio_10g.h"
8ceee660 17#include "phy.h"
177dfcd8 18#include "falcon.h"
8ceee660 19
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20#define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS | \
21 MDIO_DEVS_PMAPMD | \
22 MDIO_DEVS_PHYXS)
8ceee660 23
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24#define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) | \
25 (1 << LOOPBACK_PMAPMD) | \
e58f69f4 26 (1 << LOOPBACK_PHYXS_WS))
3273c2e8 27
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28/****************************************************************************/
29/* Quake-specific MDIO registers */
30#define MDIO_QUAKE_LED0_REG (0xD006)
31
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32/* QT2025C only */
33#define PCS_FW_HEARTBEAT_REG 0xd7ee
34#define PCS_FW_HEARTB_LBN 0
35#define PCS_FW_HEARTB_WIDTH 8
36#define PCS_UC8051_STATUS_REG 0xd7fd
37#define PCS_UC_STATUS_LBN 0
38#define PCS_UC_STATUS_WIDTH 8
39#define PCS_UC_STATUS_FW_SAVE 0x20
40#define PMA_PMD_FTX_CTRL2_REG 0xc309
41#define PMA_PMD_FTX_STATIC_LBN 13
42#define PMA_PMD_VEND1_REG 0xc001
43#define PMA_PMD_VEND1_LBTXD_LBN 15
44#define PCS_VEND1_REG 0xc000
45#define PCS_VEND1_LBTXD_LBN 5
46
b37b62fe 47void falcon_qt202x_set_led(struct efx_nic *p, int led, int mode)
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48{
49 int addr = MDIO_QUAKE_LED0_REG + led;
68e7f45e 50 efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
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51}
52
b37b62fe 53struct qt202x_phy_data {
f8b87c17 54 enum efx_phy_mode phy_mode;
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55};
56
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57#define QT2022C2_MAX_RESET_TIME 500
58#define QT2022C2_RESET_WAIT 10
8ceee660 59
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60static int qt2025c_wait_reset(struct efx_nic *efx)
61{
62 unsigned long timeout = jiffies + 10 * HZ;
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63 int reg, old_counter = 0;
64
65 /* Wait for firmware heartbeat to start */
66 for (;;) {
67 int counter;
68e7f45e 68 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
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69 if (reg < 0)
70 return reg;
71 counter = ((reg >> PCS_FW_HEARTB_LBN) &
72 ((1 << PCS_FW_HEARTB_WIDTH) - 1));
73 if (old_counter == 0)
74 old_counter = counter;
75 else if (counter != old_counter)
76 break;
77 if (time_after(jiffies, timeout))
78 return -ETIMEDOUT;
79 msleep(10);
80 }
81
82 /* Wait for firmware status to look good */
83 for (;;) {
68e7f45e 84 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
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85 if (reg < 0)
86 return reg;
87 if ((reg &
88 ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
89 PCS_UC_STATUS_FW_SAVE)
90 break;
91 if (time_after(jiffies, timeout))
92 return -ETIMEDOUT;
93 msleep(100);
94 }
95
96 return 0;
97}
98
b37b62fe 99static int qt202x_reset_phy(struct efx_nic *efx)
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100{
101 int rc;
102
d2d2c373 103 if (efx->phy_type == PHY_TYPE_QT2025C) {
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104 /* Wait for the reset triggered by falcon_reset_hw()
105 * to complete */
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106 rc = qt2025c_wait_reset(efx);
107 if (rc < 0)
108 goto fail;
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109 } else {
110 /* Reset the PHYXS MMD. This is documented as doing
111 * a complete soft reset. */
112 rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
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113 QT2022C2_MAX_RESET_TIME /
114 QT2022C2_RESET_WAIT,
115 QT2022C2_RESET_WAIT);
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116 if (rc < 0)
117 goto fail;
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118 }
119
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120 /* Wait 250ms for the PHY to complete bootup */
121 msleep(250);
122
123 /* Check that all the MMDs we expect are present and responding. We
124 * expect faults on some if the link is down, but not on the PHY XS */
b37b62fe 125 rc = efx_mdio_check_mmds(efx, QT202X_REQUIRED_DEVS, MDIO_DEVS_PHYXS);
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126 if (rc < 0)
127 goto fail;
128
44838a44 129 falcon_board(efx)->type->init_phy(efx);
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130
131 return rc;
132
133 fail:
f794fd44 134 EFX_ERR(efx, "PHY reset timed out\n");
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135 return rc;
136}
137
b37b62fe 138static int qt202x_phy_init(struct efx_nic *efx)
8ceee660 139{
b37b62fe 140 struct qt202x_phy_data *phy_data;
47c3d19f 141 u32 devid;
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142 int rc;
143
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144 rc = qt202x_reset_phy(efx);
145 if (rc) {
146 EFX_ERR(efx, "PHY init failed\n");
147 return rc;
148 }
149
b37b62fe 150 phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL);
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151 if (!phy_data)
152 return -ENOMEM;
d3208b5e 153 efx->phy_data = phy_data;
3273c2e8 154
47c3d19f 155 devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
3f39a5e9 156 EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
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157 devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
158 efx_mdio_id_rev(devid));
8ceee660 159
f8b87c17 160 phy_data->phy_mode = efx->phy_mode;
3273c2e8 161 return 0;
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162}
163
b37b62fe 164static int qt202x_link_ok(struct efx_nic *efx)
8ceee660 165{
b37b62fe 166 return efx_mdio_links_ok(efx, QT202X_REQUIRED_DEVS);
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167}
168
fdaa9aed 169static bool qt202x_phy_poll(struct efx_nic *efx)
8ceee660 170{
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171 bool was_up = efx->link_state.up;
172
173 efx->link_state.up = qt202x_link_ok(efx);
174 efx->link_state.speed = 10000;
175 efx->link_state.fd = true;
176 efx->link_state.fc = efx->wanted_fc;
177
178 return efx->link_state.up != was_up;
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179}
180
d3245b28 181static int qt202x_phy_reconfigure(struct efx_nic *efx)
8ceee660 182{
b37b62fe 183 struct qt202x_phy_data *phy_data = efx->phy_data;
3273c2e8 184
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185 if (efx->phy_type == PHY_TYPE_QT2025C) {
186 /* There are several different register bits which can
187 * disable TX (and save power) on direct-attach cables
188 * or optical transceivers, varying somewhat between
189 * firmware versions. Only 'static mode' appears to
190 * cover everything. */
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191 mdio_set_flag(
192 &efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
193 PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
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194 efx->phy_mode & PHY_MODE_TX_DISABLED ||
195 efx->phy_mode & PHY_MODE_LOW_POWER ||
196 efx->loopback_mode == LOOPBACK_PCS ||
197 efx->loopback_mode == LOOPBACK_PMAPMD);
198 } else {
199 /* Reset the PHY when moving from tx off to tx on */
200 if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
201 (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
b37b62fe 202 qt202x_reset_phy(efx);
d2d2c373 203
68e7f45e 204 efx_mdio_transmit_disable(efx);
d2d2c373 205 }
3273c2e8 206
68e7f45e 207 efx_mdio_phy_reconfigure(efx);
3273c2e8 208
f8b87c17 209 phy_data->phy_mode = efx->phy_mode;
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210
211 return 0;
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212}
213
b37b62fe 214static void qt202x_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
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215{
216 mdio45_ethtool_gset(&efx->mdio, ecmd);
217}
8ceee660 218
b37b62fe 219static void qt202x_phy_fini(struct efx_nic *efx)
8ceee660 220{
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221 /* Free the context block */
222 kfree(efx->phy_data);
223 efx->phy_data = NULL;
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224}
225
b37b62fe 226struct efx_phy_operations falcon_qt202x_phy_ops = {
177dfcd8 227 .macs = EFX_XMAC,
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228 .init = qt202x_phy_init,
229 .reconfigure = qt202x_phy_reconfigure,
230 .poll = qt202x_phy_poll,
231 .fini = qt202x_phy_fini,
b37b62fe 232 .get_settings = qt202x_phy_get_settings,
68e7f45e 233 .set_settings = efx_mdio_set_settings,
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234 .mmds = QT202X_REQUIRED_DEVS,
235 .loopbacks = QT202X_LOOPBACKS,
8ceee660 236};