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Merge branch 'master' of /repos/git/net-next-2.6
[net-next-2.6.git] / drivers / net / sfc / nic.c
CommitLineData
8e730c15
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
906bb26c 4 * Copyright 2006-2009 Solarflare Communications Inc.
8e730c15
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include <linux/seq_file.h>
16#include "net_driver.h"
17#include "bitfield.h"
18#include "efx.h"
19#include "nic.h"
20#include "regs.h"
21#include "io.h"
22#include "workarounds.h"
23
24/**************************************************************************
25 *
26 * Configurable values
27 *
28 **************************************************************************
29 */
30
31/* This is set to 16 for a good reason. In summary, if larger than
32 * 16, the descriptor cache holds more than a default socket
33 * buffer's worth of packets (for UDP we can only have at most one
34 * socket buffer's worth outstanding). This combined with the fact
35 * that we only get 1 TX event per descriptor cache means the NIC
36 * goes idle.
37 */
38#define TX_DC_ENTRIES 16
39#define TX_DC_ENTRIES_ORDER 1
40
41#define RX_DC_ENTRIES 64
42#define RX_DC_ENTRIES_ORDER 3
43
44/* RX FIFO XOFF watermark
45 *
46 * When the amount of the RX FIFO increases used increases past this
47 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
48 * This also has an effect on RX/TX arbitration
49 */
50int efx_nic_rx_xoff_thresh = -1;
51module_param_named(rx_xoff_thresh_bytes, efx_nic_rx_xoff_thresh, int, 0644);
52MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
53
54/* RX FIFO XON watermark
55 *
56 * When the amount of the RX FIFO used decreases below this
57 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
58 * This also has an effect on RX/TX arbitration
59 */
60int efx_nic_rx_xon_thresh = -1;
61module_param_named(rx_xon_thresh_bytes, efx_nic_rx_xon_thresh, int, 0644);
62MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
63
64/* If EFX_MAX_INT_ERRORS internal errors occur within
65 * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
66 * disable it.
67 */
68#define EFX_INT_ERROR_EXPIRE 3600
69#define EFX_MAX_INT_ERRORS 5
70
71/* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
72 */
73#define EFX_FLUSH_INTERVAL 10
74#define EFX_FLUSH_POLL_COUNT 100
75
76/* Size and alignment of special buffers (4KB) */
77#define EFX_BUF_SIZE 4096
78
79/* Depth of RX flush request fifo */
80#define EFX_RX_FLUSH_COUNT 4
81
90d683af
SH		 82/* Generated event code for efx_generate_test_event() */
83#define EFX_CHANNEL_MAGIC_TEST(_channel) \
d730dc52
SH		 84 (0x00010100 + (_channel)->channel)
85
90d683af
SH		 86/* Generated event code for efx_generate_fill_event() */
87#define EFX_CHANNEL_MAGIC_FILL(_channel) \
88 (0x00010200 + (_channel)->channel)
89
8e730c15
BH		 90/**************************************************************************
91 *
92 * Solarstorm hardware access
93 *
94 **************************************************************************/
95
96static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
97 unsigned int index)
98{
99 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
100 value, index);
101}
102
103/* Read the current event from the event queue */
104static inline efx_qword_t *efx_event(struct efx_channel *channel,
105 unsigned int index)
106{
107 return (((efx_qword_t *) (channel->eventq.addr)) + index);
108}
109
110/* See if an event is present
111 *
112 * We check both the high and low dword of the event for all ones. We
113 * wrote all ones when we cleared the event, and no valid event can
114 * have all ones in either its high or low dwords. This approach is
115 * robust against reordering.
116 *
117 * Note that using a single 64-bit comparison is incorrect; even
118 * though the CPU read will be atomic, the DMA write may not be.
119 */
120static inline int efx_event_present(efx_qword_t *event)
121{
122 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
123 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
124}
125
126static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
127 const efx_oword_t *mask)
128{
129 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
130 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
131}
132
133int efx_nic_test_registers(struct efx_nic *efx,
134 const struct efx_nic_register_test *regs,
135 size_t n_regs)
136{
137 unsigned address = 0, i, j;
138 efx_oword_t mask, imask, original, reg, buf;
139
140 /* Falcon should be in loopback to isolate the XMAC from the PHY */
141 WARN_ON(!LOOPBACK_INTERNAL(efx));
142
143 for (i = 0; i < n_regs; ++i) {
144 address = regs[i].address;
145 mask = imask = regs[i].mask;
146 EFX_INVERT_OWORD(imask);
147
148 efx_reado(efx, &original, address);
149
150 /* bit sweep on and off */
151 for (j = 0; j < 128; j++) {
152 if (!EFX_EXTRACT_OWORD32(mask, j, j))
153 continue;
154
155 /* Test this testable bit can be set in isolation */
156 EFX_AND_OWORD(reg, original, mask);
157 EFX_SET_OWORD32(reg, j, j, 1);
158
159 efx_writeo(efx, &reg, address);
160 efx_reado(efx, &buf, address);
161
162 if (efx_masked_compare_oword(&reg, &buf, &mask))
163 goto fail;
164
165 /* Test this testable bit can be cleared in isolation */
166 EFX_OR_OWORD(reg, original, mask);
167 EFX_SET_OWORD32(reg, j, j, 0);
168
169 efx_writeo(efx, &reg, address);
170 efx_reado(efx, &buf, address);
171
172 if (efx_masked_compare_oword(&reg, &buf, &mask))
173 goto fail;
174 }
175
176 efx_writeo(efx, &original, address);
177 }
178
179 return 0;
180
181fail:
182 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
183 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
184 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
185 return -EIO;
186}
187
188/**************************************************************************
189 *
190 * Special buffer handling
191 * Special buffers are used for event queues and the TX and RX
192 * descriptor rings.
193 *
194 *************************************************************************/
195
196/*
197 * Initialise a special buffer
198 *
199 * This will define a buffer (previously allocated via
200 * efx_alloc_special_buffer()) in the buffer table, allowing
201 * it to be used for event queues, descriptor rings etc.
202 */
203static void
204efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
205{
206 efx_qword_t buf_desc;
207 int index;
208 dma_addr_t dma_addr;
209 int i;
210
211 EFX_BUG_ON_PARANOID(!buffer->addr);
212
213 /* Write buffer descriptors to NIC */
214 for (i = 0; i < buffer->entries; i++) {
215 index = buffer->index + i;
216 dma_addr = buffer->dma_addr + (i * 4096);
217 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
218 index, (unsigned long long)dma_addr);
219 EFX_POPULATE_QWORD_3(buf_desc,
220 FRF_AZ_BUF_ADR_REGION, 0,
221 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
222 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
223 efx_write_buf_tbl(efx, &buf_desc, index);
224 }
225}
226
227/* Unmaps a buffer and clears the buffer table entries */
228static void
229efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
230{
231 efx_oword_t buf_tbl_upd;
232 unsigned int start = buffer->index;
233 unsigned int end = (buffer->index + buffer->entries - 1);
234
235 if (!buffer->entries)
236 return;
237
238 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
239 buffer->index, buffer->index + buffer->entries - 1);
240
241 EFX_POPULATE_OWORD_4(buf_tbl_upd,
242 FRF_AZ_BUF_UPD_CMD, 0,
243 FRF_AZ_BUF_CLR_CMD, 1,
244 FRF_AZ_BUF_CLR_END_ID, end,
245 FRF_AZ_BUF_CLR_START_ID, start);
246 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
247}
248
249/*
250 * Allocate a new special buffer
251 *
252 * This allocates memory for a new buffer, clears it and allocates a
253 * new buffer ID range. It does not write into the buffer table.
254 *
255 * This call will allocate 4KB buffers, since 8KB buffers can't be
256 * used for event queues and descriptor rings.
257 */
258static int efx_alloc_special_buffer(struct efx_nic *efx,
259 struct efx_special_buffer *buffer,
260 unsigned int len)
261{
262 len = ALIGN(len, EFX_BUF_SIZE);
263
264 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
265 &buffer->dma_addr);
266 if (!buffer->addr)
267 return -ENOMEM;
268 buffer->len = len;
269 buffer->entries = len / EFX_BUF_SIZE;
270 BUG_ON(buffer->dma_addr & (EFX_BUF_SIZE - 1));
271
272 /* All zeros is a potentially valid event so memset to 0xff */
273 memset(buffer->addr, 0xff, len);
274
275 /* Select new buffer ID */
276 buffer->index = efx->next_buffer_table;
277 efx->next_buffer_table += buffer->entries;
278
279 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
280 "(virt %p phys %llx)\n", buffer->index,
281 buffer->index + buffer->entries - 1,
282 (u64)buffer->dma_addr, len,
283 buffer->addr, (u64)virt_to_phys(buffer->addr));
284
285 return 0;
286}
287
288static void
289efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
290{
291 if (!buffer->addr)
292 return;
293
294 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
295 "(virt %p phys %llx)\n", buffer->index,
296 buffer->index + buffer->entries - 1,
297 (u64)buffer->dma_addr, buffer->len,
298 buffer->addr, (u64)virt_to_phys(buffer->addr));
299
300 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
301 buffer->dma_addr);
302 buffer->addr = NULL;
303 buffer->entries = 0;
304}
305
306/**************************************************************************
307 *
308 * Generic buffer handling
309 * These buffers are used for interrupt status and MAC stats
310 *
311 **************************************************************************/
312
313int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
314 unsigned int len)
315{
316 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
317 &buffer->dma_addr);
318 if (!buffer->addr)
319 return -ENOMEM;
320 buffer->len = len;
321 memset(buffer->addr, 0, len);
322 return 0;
323}
324
325void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
326{
327 if (buffer->addr) {
328 pci_free_consistent(efx->pci_dev, buffer->len,
329 buffer->addr, buffer->dma_addr);
330 buffer->addr = NULL;
331 }
332}
333
334/**************************************************************************
335 *
336 * TX path
337 *
338 **************************************************************************/
339
340/* Returns a pointer to the specified transmit descriptor in the TX
341 * descriptor queue belonging to the specified channel.
342 */
343static inline efx_qword_t *
344efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
345{
346 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
347}
348
349/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
350static inline void efx_notify_tx_desc(struct efx_tx_queue *tx_queue)
351{
352 unsigned write_ptr;
353 efx_dword_t reg;
354
355 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
356 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
357 efx_writed_page(tx_queue->efx, &reg,
358 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
359}
360
361
362/* For each entry inserted into the software descriptor ring, create a
363 * descriptor in the hardware TX descriptor ring (in host memory), and
364 * write a doorbell.
365 */
366void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
367{
368
369 struct efx_tx_buffer *buffer;
370 efx_qword_t *txd;
371 unsigned write_ptr;
372
373 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
374
375 do {
376 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
377 buffer = &tx_queue->buffer[write_ptr];
378 txd = efx_tx_desc(tx_queue, write_ptr);
379 ++tx_queue->write_count;
380
381 /* Create TX descriptor ring entry */
382 EFX_POPULATE_QWORD_4(*txd,
383 FSF_AZ_TX_KER_CONT, buffer->continuation,
384 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
385 FSF_AZ_TX_KER_BUF_REGION, 0,
386 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
387 } while (tx_queue->write_count != tx_queue->insert_count);
388
389 wmb(); /* Ensure descriptors are written before they are fetched */
390 efx_notify_tx_desc(tx_queue);
391}
392
393/* Allocate hardware resources for a TX queue */
394int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
395{
396 struct efx_nic *efx = tx_queue->efx;
397 BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 ||
398 EFX_TXQ_SIZE & EFX_TXQ_MASK);
399 return efx_alloc_special_buffer(efx, &tx_queue->txd,
400 EFX_TXQ_SIZE * sizeof(efx_qword_t));
401}
402
403void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
404{
405 efx_oword_t tx_desc_ptr;
406 struct efx_nic *efx = tx_queue->efx;
407
408 tx_queue->flushed = FLUSH_NONE;
409
410 /* Pin TX descriptor ring */
411 efx_init_special_buffer(efx, &tx_queue->txd);
412
413 /* Push TX descriptor ring to card */
414 EFX_POPULATE_OWORD_10(tx_desc_ptr,
415 FRF_AZ_TX_DESCQ_EN, 1,
416 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
417 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
418 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
419 FRF_AZ_TX_DESCQ_EVQ_ID,
420 tx_queue->channel->channel,
421 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
422 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
423 FRF_AZ_TX_DESCQ_SIZE,
424 __ffs(tx_queue->txd.entries),
425 FRF_AZ_TX_DESCQ_TYPE, 0,
426 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
427
428 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
a4900ac9 429 int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
8e730c15
BH		 430 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
431 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
432 !csum);
433 }
434
435 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
436 tx_queue->queue);
437
438 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
439 efx_oword_t reg;
440
441 /* Only 128 bits in this register */
a4900ac9 442 BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128);
8e730c15
BH		 443
444 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
a4900ac9 445 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
8e730c15
BH		 446 clear_bit_le(tx_queue->queue, (void *)&reg);
447 else
448 set_bit_le(tx_queue->queue, (void *)&reg);
449 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
450 }
451}
452
453static void efx_flush_tx_queue(struct efx_tx_queue *tx_queue)
454{
455 struct efx_nic *efx = tx_queue->efx;
456 efx_oword_t tx_flush_descq;
457
458 tx_queue->flushed = FLUSH_PENDING;
459
460 /* Post a flush command */
461 EFX_POPULATE_OWORD_2(tx_flush_descq,
462 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
463 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
464 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
465}
466
467void efx_nic_fini_tx(struct efx_tx_queue *tx_queue)
468{
469 struct efx_nic *efx = tx_queue->efx;
470 efx_oword_t tx_desc_ptr;
471
472 /* The queue should have been flushed */
473 WARN_ON(tx_queue->flushed != FLUSH_DONE);
474
475 /* Remove TX descriptor ring from card */
476 EFX_ZERO_OWORD(tx_desc_ptr);
477 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
478 tx_queue->queue);
479
480 /* Unpin TX descriptor ring */
481 efx_fini_special_buffer(efx, &tx_queue->txd);
482}
483
484/* Free buffers backing TX queue */
485void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
486{
487 efx_free_special_buffer(tx_queue->efx, &tx_queue->txd);
488}
489
490/**************************************************************************
491 *
492 * RX path
493 *
494 **************************************************************************/
495
496/* Returns a pointer to the specified descriptor in the RX descriptor queue */
497static inline efx_qword_t *
498efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
499{
500 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
501}
502
503/* This creates an entry in the RX descriptor queue */
504static inline void
505efx_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index)
506{
507 struct efx_rx_buffer *rx_buf;
508 efx_qword_t *rxd;
509
510 rxd = efx_rx_desc(rx_queue, index);
511 rx_buf = efx_rx_buffer(rx_queue, index);
512 EFX_POPULATE_QWORD_3(*rxd,
513 FSF_AZ_RX_KER_BUF_SIZE,
514 rx_buf->len -
515 rx_queue->efx->type->rx_buffer_padding,
516 FSF_AZ_RX_KER_BUF_REGION, 0,
517 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
518}
519
520/* This writes to the RX_DESC_WPTR register for the specified receive
521 * descriptor ring.
522 */
523void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
524{
525 efx_dword_t reg;
526 unsigned write_ptr;
527
528 while (rx_queue->notified_count != rx_queue->added_count) {
529 efx_build_rx_desc(rx_queue,
530 rx_queue->notified_count &
531 EFX_RXQ_MASK);
532 ++rx_queue->notified_count;
533 }
534
535 wmb();
536 write_ptr = rx_queue->added_count & EFX_RXQ_MASK;
537 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
538 efx_writed_page(rx_queue->efx, &reg,
539 FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
540}
541
542int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
543{
544 struct efx_nic *efx = rx_queue->efx;
545 BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 ||
546 EFX_RXQ_SIZE & EFX_RXQ_MASK);
547 return efx_alloc_special_buffer(efx, &rx_queue->rxd,
548 EFX_RXQ_SIZE * sizeof(efx_qword_t));
549}
550
551void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
552{
553 efx_oword_t rx_desc_ptr;
554 struct efx_nic *efx = rx_queue->efx;
555 bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0;
556 bool iscsi_digest_en = is_b0;
557
558 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
559 rx_queue->queue, rx_queue->rxd.index,
560 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
561
562 rx_queue->flushed = FLUSH_NONE;
563
564 /* Pin RX descriptor ring */
565 efx_init_special_buffer(efx, &rx_queue->rxd);
566
567 /* Push RX descriptor ring to card */
568 EFX_POPULATE_OWORD_10(rx_desc_ptr,
569 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
570 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
571 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
572 FRF_AZ_RX_DESCQ_EVQ_ID,
573 rx_queue->channel->channel,
574 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
575 FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
576 FRF_AZ_RX_DESCQ_SIZE,
577 __ffs(rx_queue->rxd.entries),
578 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
579 /* For >=B0 this is scatter so disable */
580 FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
581 FRF_AZ_RX_DESCQ_EN, 1);
582 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
583 rx_queue->queue);
584}
585
586static void efx_flush_rx_queue(struct efx_rx_queue *rx_queue)
587{
588 struct efx_nic *efx = rx_queue->efx;
589 efx_oword_t rx_flush_descq;
590
591 rx_queue->flushed = FLUSH_PENDING;
592
593 /* Post a flush command */
594 EFX_POPULATE_OWORD_2(rx_flush_descq,
595 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
596 FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
597 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
598}
599
600void efx_nic_fini_rx(struct efx_rx_queue *rx_queue)
601{
602 efx_oword_t rx_desc_ptr;
603 struct efx_nic *efx = rx_queue->efx;
604
605 /* The queue should already have been flushed */
606 WARN_ON(rx_queue->flushed != FLUSH_DONE);
607
608 /* Remove RX descriptor ring from card */
609 EFX_ZERO_OWORD(rx_desc_ptr);
610 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
611 rx_queue->queue);
612
613 /* Unpin RX descriptor ring */
614 efx_fini_special_buffer(efx, &rx_queue->rxd);
615}
616
617/* Free buffers backing RX queue */
618void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
619{
620 efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
621}
622
623/**************************************************************************
624 *
625 * Event queue processing
626 * Event queues are processed by per-channel tasklets.
627 *
628 **************************************************************************/
629
630/* Update a channel's event queue's read pointer (RPTR) register
631 *
632 * This writes the EVQ_RPTR_REG register for the specified channel's
633 * event queue.
8e730c15
BH		 634 */
635void efx_nic_eventq_read_ack(struct efx_channel *channel)
636{
637 efx_dword_t reg;
638 struct efx_nic *efx = channel->efx;
639
640 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
641 efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
642 channel->channel);
643}
644
645/* Use HW to insert a SW defined event */
646void efx_generate_event(struct efx_channel *channel, efx_qword_t *event)
647{
648 efx_oword_t drv_ev_reg;
649
650 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
651 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
652 drv_ev_reg.u32[0] = event->u32[0];
653 drv_ev_reg.u32[1] = event->u32[1];
654 drv_ev_reg.u32[2] = 0;
655 drv_ev_reg.u32[3] = 0;
656 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
657 efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
658}
659
660/* Handle a transmit completion event
661 *
662 * The NIC batches TX completion events; the message we receive is of
663 * the form "complete all TX events up to this index".
664 */
fa236e18 665static int
8e730c15
BH		 666efx_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
667{
668 unsigned int tx_ev_desc_ptr;
669 unsigned int tx_ev_q_label;
670 struct efx_tx_queue *tx_queue;
671 struct efx_nic *efx = channel->efx;
fa236e18 672 int tx_packets = 0;
8e730c15
BH		 673
674 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
675 /* Transmit completion */
676 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
677 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
678 tx_queue = &efx->tx_queue[tx_ev_q_label];
fa236e18
BH		 679 tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) &
680 EFX_TXQ_MASK);
681 channel->irq_mod_score += tx_packets;
8e730c15
BH		 682 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
683 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
684 /* Rewrite the FIFO write pointer */
685 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
686 tx_queue = &efx->tx_queue[tx_ev_q_label];
687
688 if (efx_dev_registered(efx))
689 netif_tx_lock(efx->net_dev);
690 efx_notify_tx_desc(tx_queue);
691 if (efx_dev_registered(efx))
692 netif_tx_unlock(efx->net_dev);
693 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
694 EFX_WORKAROUND_10727(efx)) {
695 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
696 } else {
697 EFX_ERR(efx, "channel %d unexpected TX event "
698 EFX_QWORD_FMT"\n", channel->channel,
699 EFX_QWORD_VAL(*event));
700 }
fa236e18
BH		 701
702 return tx_packets;
8e730c15
BH		 703}
704
705/* Detect errors included in the rx_evt_pkt_ok bit. */
706static void efx_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
707 const efx_qword_t *event,
708 bool *rx_ev_pkt_ok,
709 bool *discard)
710{
711 struct efx_nic *efx = rx_queue->efx;
712 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
713 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
714 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
715 bool rx_ev_other_err, rx_ev_pause_frm;
716 bool rx_ev_hdr_type, rx_ev_mcast_pkt;
717 unsigned rx_ev_pkt_type;
718
719 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
720 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
721 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
722 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
723 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
724 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
725 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
726 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
727 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
728 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
729 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
730 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
731 rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ?
732 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
733 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
734
735 /* Every error apart from tobe_disc and pause_frm */
736 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
737 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
738 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
739
740 /* Count errors that are not in MAC stats. Ignore expected
741 * checksum errors during self-test. */
742 if (rx_ev_frm_trunc)
743 ++rx_queue->channel->n_rx_frm_trunc;
744 else if (rx_ev_tobe_disc)
745 ++rx_queue->channel->n_rx_tobe_disc;
746 else if (!efx->loopback_selftest) {
747 if (rx_ev_ip_hdr_chksum_err)
748 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
749 else if (rx_ev_tcp_udp_chksum_err)
750 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
751 }
752
753 /* The frame must be discarded if any of these are true. */
754 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
755 rx_ev_tobe_disc | rx_ev_pause_frm);
756
757 /* TOBE_DISC is expected on unicast mismatches; don't print out an
758 * error message. FRM_TRUNC indicates RXDP dropped the packet due
759 * to a FIFO overflow.
760 */
761#ifdef EFX_ENABLE_DEBUG
762 if (rx_ev_other_err) {
763 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
764 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
765 rx_queue->queue, EFX_QWORD_VAL(*event),
766 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
767 rx_ev_ip_hdr_chksum_err ?
768 " [IP_HDR_CHKSUM_ERR]" : "",
769 rx_ev_tcp_udp_chksum_err ?
770 " [TCP_UDP_CHKSUM_ERR]" : "",
771 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
772 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
773 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
774 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
775 rx_ev_pause_frm ? " [PAUSE]" : "");
776 }
777#endif
778}
779
780/* Handle receive events that are not in-order. */
781static void
782efx_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index)
783{
784 struct efx_nic *efx = rx_queue->efx;
785 unsigned expected, dropped;
786
787 expected = rx_queue->removed_count & EFX_RXQ_MASK;
788 dropped = (index - expected) & EFX_RXQ_MASK;
789 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
790 dropped, index, expected);
791
792 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
793 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
794}
795
796/* Handle a packet received event
797 *
798 * The NIC gives a "discard" flag if it's a unicast packet with the
799 * wrong destination address
800 * Also "is multicast" and "matches multicast filter" flags can be used to
801 * discard non-matching multicast packets.
802 */
803static void
804efx_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event)
805{
806 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
807 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
808 unsigned expected_ptr;
809 bool rx_ev_pkt_ok, discard = false, checksummed;
810 struct efx_rx_queue *rx_queue;
811 struct efx_nic *efx = channel->efx;
812
813 /* Basic packet information */
814 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
815 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
816 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
817 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
818 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
819 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
820 channel->channel);
821
822 rx_queue = &efx->rx_queue[channel->channel];
823
824 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
825 expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK;
826 if (unlikely(rx_ev_desc_ptr != expected_ptr))
827 efx_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
828
829 if (likely(rx_ev_pkt_ok)) {
830 /* If packet is marked as OK and packet type is TCP/IP or
831 * UDP/IP, then we can rely on the hardware checksum.
832 */
833 checksummed =
834 likely(efx->rx_checksum_enabled) &&
835 (rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP ||
836 rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP);
837 } else {
838 efx_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok, &discard);
839 checksummed = false;
840 }
841
842 /* Detect multicast packets that didn't match the filter */
843 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
844 if (rx_ev_mcast_pkt) {
845 unsigned int rx_ev_mcast_hash_match =
846 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
847
848 if (unlikely(!rx_ev_mcast_hash_match)) {
849 ++channel->n_rx_mcast_mismatch;
850 discard = true;
851 }
852 }
853
854 channel->irq_mod_score += 2;
855
856 /* Handle received packet */
857 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
858 checksummed, discard);
859}
860
90d683af
SH		 861static void
862efx_handle_generated_event(struct efx_channel *channel, efx_qword_t *event)
863{
864 struct efx_nic *efx = channel->efx;
865 unsigned code;
866
867 code = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC);
868 if (code == EFX_CHANNEL_MAGIC_TEST(channel))
869 ++channel->magic_count;
870 else if (code == EFX_CHANNEL_MAGIC_FILL(channel))
871 /* The queue must be empty, so we won't receive any rx
872 * events, so efx_process_channel() won't refill the
873 * queue. Refill it here */
874 efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]);
875 else
876 EFX_LOG(efx, "channel %d received generated "
877 "event "EFX_QWORD_FMT"\n", channel->channel,
878 EFX_QWORD_VAL(*event));
879}
880
8e730c15
BH		 881/* Global events are basically PHY events */
882static void
883efx_handle_global_event(struct efx_channel *channel, efx_qword_t *event)
884{
885 struct efx_nic *efx = channel->efx;
886 bool handled = false;
887
888 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
889 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
890 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
891 /* Ignored */
892 handled = true;
893 }
894
895 if ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) &&
896 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
897 efx->xmac_poll_required = true;
898 handled = true;
899 }
900
901 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
902 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
903 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
904 EFX_ERR(efx, "channel %d seen global RX_RESET "
905 "event. Resetting.\n", channel->channel);
906
907 atomic_inc(&efx->rx_reset);
908 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
909 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
910 handled = true;
911 }
912
913 if (!handled)
914 EFX_ERR(efx, "channel %d unknown global event "
915 EFX_QWORD_FMT "\n", channel->channel,
916 EFX_QWORD_VAL(*event));
917}
918
919static void
920efx_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
921{
922 struct efx_nic *efx = channel->efx;
923 unsigned int ev_sub_code;
924 unsigned int ev_sub_data;
925
926 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
927 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
928
929 switch (ev_sub_code) {
930 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
931 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
932 channel->channel, ev_sub_data);
933 break;
934 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
935 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
936 channel->channel, ev_sub_data);
937 break;
938 case FSE_AZ_EVQ_INIT_DONE_EV:
939 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
940 channel->channel, ev_sub_data);
941 break;
942 case FSE_AZ_SRM_UPD_DONE_EV:
943 EFX_TRACE(efx, "channel %d SRAM update done\n",
944 channel->channel);
945 break;
946 case FSE_AZ_WAKE_UP_EV:
947 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
948 channel->channel, ev_sub_data);
949 break;
950 case FSE_AZ_TIMER_EV:
951 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
952 channel->channel, ev_sub_data);
953 break;
954 case FSE_AA_RX_RECOVER_EV:
955 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
956 "Resetting.\n", channel->channel);
957 atomic_inc(&efx->rx_reset);
958 efx_schedule_reset(efx,
959 EFX_WORKAROUND_6555(efx) ?
960 RESET_TYPE_RX_RECOVERY :
961 RESET_TYPE_DISABLE);
962 break;
963 case FSE_BZ_RX_DSC_ERROR_EV:
964 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
965 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
966 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
967 break;
968 case FSE_BZ_TX_DSC_ERROR_EV:
969 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
970 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
971 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
972 break;
973 default:
974 EFX_TRACE(efx, "channel %d unknown driver event code %d "
975 "data %04x\n", channel->channel, ev_sub_code,
976 ev_sub_data);
977 break;
978 }
979}
980
fa236e18 981int efx_nic_process_eventq(struct efx_channel *channel, int budget)
8e730c15
BH		 982{
983 unsigned int read_ptr;
984 efx_qword_t event, *p_event;
985 int ev_code;
fa236e18
BH		 986 int tx_packets = 0;
987 int spent = 0;
8e730c15
BH		 988
989 read_ptr = channel->eventq_read_ptr;
990
fa236e18 991 for (;;) {
8e730c15
BH		 992 p_event = efx_event(channel, read_ptr);
993 event = *p_event;
994
995 if (!efx_event_present(&event))
996 /* End of events */
997 break;
998
999 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1000 channel->channel, EFX_QWORD_VAL(event));
1001
1002 /* Clear this event by marking it all ones */
1003 EFX_SET_QWORD(*p_event);
1004
fa236e18
BH		 1005 /* Increment read pointer */
1006 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1007
8e730c15
BH		 1008 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1009
1010 switch (ev_code) {
1011 case FSE_AZ_EV_CODE_RX_EV:
1012 efx_handle_rx_event(channel, &event);
fa236e18
BH		 1013 if (++spent == budget)
1014 goto out;
8e730c15
BH		 1015 break;
1016 case FSE_AZ_EV_CODE_TX_EV:
fa236e18
BH		 1017 tx_packets += efx_handle_tx_event(channel, &event);
1018 if (tx_packets >= EFX_TXQ_SIZE) {
1019 spent = budget;
1020 goto out;
1021 }
8e730c15
BH		 1022 break;
1023 case FSE_AZ_EV_CODE_DRV_GEN_EV:
90d683af 1024 efx_handle_generated_event(channel, &event);
8e730c15
BH		 1025 break;
1026 case FSE_AZ_EV_CODE_GLOBAL_EV:
1027 efx_handle_global_event(channel, &event);
1028 break;
1029 case FSE_AZ_EV_CODE_DRIVER_EV:
1030 efx_handle_driver_event(channel, &event);
1031 break;
8880f4ec
BH		 1032 case FSE_CZ_EV_CODE_MCDI_EV:
1033 efx_mcdi_process_event(channel, &event);
1034 break;
8e730c15
BH		 1035 default:
1036 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1037 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1038 ev_code, EFX_QWORD_VAL(event));
1039 }
fa236e18 1040 }
8e730c15 1041
fa236e18 1042out:
8e730c15 1043 channel->eventq_read_ptr = read_ptr;
fa236e18 1044 return spent;
8e730c15
BH		 1045}
1046
1047
1048/* Allocate buffer table entries for event queue */
1049int efx_nic_probe_eventq(struct efx_channel *channel)
1050{
1051 struct efx_nic *efx = channel->efx;
1052 BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 ||
1053 EFX_EVQ_SIZE & EFX_EVQ_MASK);
1054 return efx_alloc_special_buffer(efx, &channel->eventq,
1055 EFX_EVQ_SIZE * sizeof(efx_qword_t));
1056}
1057
1058void efx_nic_init_eventq(struct efx_channel *channel)
1059{
8880f4ec 1060 efx_oword_t reg;
8e730c15
BH		 1061 struct efx_nic *efx = channel->efx;
1062
1063 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1064 channel->channel, channel->eventq.index,
1065 channel->eventq.index + channel->eventq.entries - 1);
1066
8880f4ec
BH		 1067 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
1068 EFX_POPULATE_OWORD_3(reg,
1069 FRF_CZ_TIMER_Q_EN, 1,
1070 FRF_CZ_HOST_NOTIFY_MODE, 0,
1071 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1072 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1073 }
1074
8e730c15
BH		 1075 /* Pin event queue buffer */
1076 efx_init_special_buffer(efx, &channel->eventq);
1077
1078 /* Fill event queue with all ones (i.e. empty events) */
1079 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1080
1081 /* Push event queue to card */
8880f4ec 1082 EFX_POPULATE_OWORD_3(reg,
8e730c15
BH		 1083 FRF_AZ_EVQ_EN, 1,
1084 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1085 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
8880f4ec 1086 efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
8e730c15
BH		 1087 channel->channel);
1088
1089 efx->type->push_irq_moderation(channel);
1090}
1091
1092void efx_nic_fini_eventq(struct efx_channel *channel)
1093{
8880f4ec 1094 efx_oword_t reg;
8e730c15
BH		 1095 struct efx_nic *efx = channel->efx;
1096
1097 /* Remove event queue from card */
8880f4ec
BH		 1098 EFX_ZERO_OWORD(reg);
1099 efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
8e730c15 1100 channel->channel);
8880f4ec
BH		 1101 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1102 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
8e730c15
BH		 1103
1104 /* Unpin event queue */
1105 efx_fini_special_buffer(efx, &channel->eventq);
1106}
1107
1108/* Free buffers backing event queue */
1109void efx_nic_remove_eventq(struct efx_channel *channel)
1110{
1111 efx_free_special_buffer(channel->efx, &channel->eventq);
1112}
1113
1114
d730dc52 1115void efx_nic_generate_test_event(struct efx_channel *channel)
8e730c15 1116{
90d683af
SH		 1117 unsigned int magic = EFX_CHANNEL_MAGIC_TEST(channel);
1118 efx_qword_t test_event;
1119
1120 EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1121 FSE_AZ_EV_CODE_DRV_GEN_EV,
1122 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1123 efx_generate_event(channel, &test_event);
1124}
1125
1126void efx_nic_generate_fill_event(struct efx_channel *channel)
1127{
1128 unsigned int magic = EFX_CHANNEL_MAGIC_FILL(channel);
8e730c15
BH		 1129 efx_qword_t test_event;
1130
1131 EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1132 FSE_AZ_EV_CODE_DRV_GEN_EV,
1133 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1134 efx_generate_event(channel, &test_event);
1135}
1136
1137/**************************************************************************
1138 *
1139 * Flush handling
1140 *
1141 **************************************************************************/
1142
1143
1144static void efx_poll_flush_events(struct efx_nic *efx)
1145{
1146 struct efx_channel *channel = &efx->channel[0];
1147 struct efx_tx_queue *tx_queue;
1148 struct efx_rx_queue *rx_queue;
1149 unsigned int read_ptr = channel->eventq_read_ptr;
1150 unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK;
1151
1152 do {
1153 efx_qword_t *event = efx_event(channel, read_ptr);
1154 int ev_code, ev_sub_code, ev_queue;
1155 bool ev_failed;
1156
1157 if (!efx_event_present(event))
1158 break;
1159
1160 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1161 ev_sub_code = EFX_QWORD_FIELD(*event,
1162 FSF_AZ_DRIVER_EV_SUBCODE);
1163 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1164 ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1165 ev_queue = EFX_QWORD_FIELD(*event,
1166 FSF_AZ_DRIVER_EV_SUBDATA);
a4900ac9 1167 if (ev_queue < EFX_TXQ_TYPES * efx->n_tx_channels) {
8e730c15
BH		 1168 tx_queue = efx->tx_queue + ev_queue;
1169 tx_queue->flushed = FLUSH_DONE;
1170 }
1171 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1172 ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1173 ev_queue = EFX_QWORD_FIELD(
1174 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1175 ev_failed = EFX_QWORD_FIELD(
1176 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
a4900ac9 1177 if (ev_queue < efx->n_rx_channels) {
8e730c15
BH		 1178 rx_queue = efx->rx_queue + ev_queue;
1179 rx_queue->flushed =
1180 ev_failed ? FLUSH_FAILED : FLUSH_DONE;
1181 }
1182 }
1183
1184 /* We're about to destroy the queue anyway, so
1185 * it's ok to throw away every non-flush event */
1186 EFX_SET_QWORD(*event);
1187
1188 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1189 } while (read_ptr != end_ptr);
1190
1191 channel->eventq_read_ptr = read_ptr;
1192}
1193
1194/* Handle tx and rx flushes at the same time, since they run in
1195 * parallel in the hardware and there's no reason for us to
1196 * serialise them */
1197int efx_nic_flush_queues(struct efx_nic *efx)
1198{
1199 struct efx_rx_queue *rx_queue;
1200 struct efx_tx_queue *tx_queue;
1201 int i, tx_pending, rx_pending;
1202
1203 /* If necessary prepare the hardware for flushing */
1204 efx->type->prepare_flush(efx);
1205
1206 /* Flush all tx queues in parallel */
1207 efx_for_each_tx_queue(tx_queue, efx)
1208 efx_flush_tx_queue(tx_queue);
1209
1210 /* The hardware supports four concurrent rx flushes, each of which may
1211 * need to be retried if there is an outstanding descriptor fetch */
1212 for (i = 0; i < EFX_FLUSH_POLL_COUNT; ++i) {
1213 rx_pending = tx_pending = 0;
1214 efx_for_each_rx_queue(rx_queue, efx) {
1215 if (rx_queue->flushed == FLUSH_PENDING)
1216 ++rx_pending;
1217 }
1218 efx_for_each_rx_queue(rx_queue, efx) {
1219 if (rx_pending == EFX_RX_FLUSH_COUNT)
1220 break;
1221 if (rx_queue->flushed == FLUSH_FAILED ||
1222 rx_queue->flushed == FLUSH_NONE) {
1223 efx_flush_rx_queue(rx_queue);
1224 ++rx_pending;
1225 }
1226 }
1227 efx_for_each_tx_queue(tx_queue, efx) {
1228 if (tx_queue->flushed != FLUSH_DONE)
1229 ++tx_pending;
1230 }
1231
1232 if (rx_pending == 0 && tx_pending == 0)
1233 return 0;
1234
1235 msleep(EFX_FLUSH_INTERVAL);
1236 efx_poll_flush_events(efx);
1237 }
1238
1239 /* Mark the queues as all flushed. We're going to return failure
1240 * leading to a reset, or fake up success anyway */
1241 efx_for_each_tx_queue(tx_queue, efx) {
1242 if (tx_queue->flushed != FLUSH_DONE)
1243 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1244 tx_queue->queue);
1245 tx_queue->flushed = FLUSH_DONE;
1246 }
1247 efx_for_each_rx_queue(rx_queue, efx) {
1248 if (rx_queue->flushed != FLUSH_DONE)
1249 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1250 rx_queue->queue);
1251 rx_queue->flushed = FLUSH_DONE;
1252 }
1253
8e730c15
BH		 1254 return -ETIMEDOUT;
1255}
1256
1257/**************************************************************************
1258 *
1259 * Hardware interrupts
1260 * The hardware interrupt handler does very little work; all the event
1261 * queue processing is carried out by per-channel tasklets.
1262 *
1263 **************************************************************************/
1264
1265/* Enable/disable/generate interrupts */
1266static inline void efx_nic_interrupts(struct efx_nic *efx,
1267 bool enabled, bool force)
1268{
1269 efx_oword_t int_en_reg_ker;
8880f4ec
BH		 1270
1271 EFX_POPULATE_OWORD_3(int_en_reg_ker,
63695459 1272 FRF_AZ_KER_INT_LEVE_SEL, efx->fatal_irq_level,
8e730c15
BH		 1273 FRF_AZ_KER_INT_KER, force,
1274 FRF_AZ_DRV_INT_EN_KER, enabled);
1275 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1276}
1277
1278void efx_nic_enable_interrupts(struct efx_nic *efx)
1279{
1280 struct efx_channel *channel;
1281
1282 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1283 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1284
1285 /* Enable interrupts */
1286 efx_nic_interrupts(efx, true, false);
1287
1288 /* Force processing of all the channels to get the EVQ RPTRs up to
1289 date */
1290 efx_for_each_channel(channel, efx)
1291 efx_schedule_channel(channel);
1292}
1293
1294void efx_nic_disable_interrupts(struct efx_nic *efx)
1295{
1296 /* Disable interrupts */
1297 efx_nic_interrupts(efx, false, false);
1298}
1299
1300/* Generate a test interrupt
1301 * Interrupt must already have been enabled, otherwise nasty things
1302 * may happen.
1303 */
1304void efx_nic_generate_interrupt(struct efx_nic *efx)
1305{
1306 efx_nic_interrupts(efx, true, true);
1307}
1308
1309/* Process a fatal interrupt
1310 * Disable bus mastering ASAP and schedule a reset
1311 */
1312irqreturn_t efx_nic_fatal_interrupt(struct efx_nic *efx)
1313{
1314 struct falcon_nic_data *nic_data = efx->nic_data;
1315 efx_oword_t *int_ker = efx->irq_status.addr;
1316 efx_oword_t fatal_intr;
1317 int error, mem_perr;
1318
1319 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1320 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1321
1322 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1323 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1324 EFX_OWORD_VAL(fatal_intr),
1325 error ? "disabling bus mastering" : "no recognised error");
8e730c15
BH		 1326
1327 /* If this is a memory parity error dump which blocks are offending */
97e1eaa0
SH		 1328 mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) ||
1329 EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER));
8e730c15
BH		 1330 if (mem_perr) {
1331 efx_oword_t reg;
1332 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1333 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1334 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1335 }
1336
1337 /* Disable both devices */
1338 pci_clear_master(efx->pci_dev);
1339 if (efx_nic_is_dual_func(efx))
1340 pci_clear_master(nic_data->pci_dev2);
1341 efx_nic_disable_interrupts(efx);
1342
1343 /* Count errors and reset or disable the NIC accordingly */
1344 if (efx->int_error_count == 0 ||
1345 time_after(jiffies, efx->int_error_expire)) {
1346 efx->int_error_count = 0;
1347 efx->int_error_expire =
1348 jiffies + EFX_INT_ERROR_EXPIRE * HZ;
1349 }
1350 if (++efx->int_error_count < EFX_MAX_INT_ERRORS) {
1351 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1352 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1353 } else {
1354 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1355 "NIC will be disabled\n");
1356 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1357 }
63695459 1358
8e730c15
BH		 1359 return IRQ_HANDLED;
1360}
1361
1362/* Handle a legacy interrupt
1363 * Acknowledges the interrupt and schedule event queue processing.
1364 */
1365static irqreturn_t efx_legacy_interrupt(int irq, void *dev_id)
1366{
1367 struct efx_nic *efx = dev_id;
1368 efx_oword_t *int_ker = efx->irq_status.addr;
1369 irqreturn_t result = IRQ_NONE;
1370 struct efx_channel *channel;
1371 efx_dword_t reg;
1372 u32 queues;
1373 int syserr;
1374
1375 /* Read the ISR which also ACKs the interrupts */
1376 efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1377 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1378
1379 /* Check to see if we have a serious error condition */
63695459
SH		 1380 if (queues & (1U << efx->fatal_irq_level)) {
1381 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1382 if (unlikely(syserr))
1383 return efx_nic_fatal_interrupt(efx);
1384 }
8e730c15 1385
8880f4ec
BH		 1386 if (queues != 0) {
1387 if (EFX_WORKAROUND_15783(efx))
1388 efx->irq_zero_count = 0;
1389
1390 /* Schedule processing of any interrupting queues */
1391 efx_for_each_channel(channel, efx) {
1392 if (queues & 1)
8e730c15 1393 efx_schedule_channel(channel);
8880f4ec 1394 queues >>= 1;
8e730c15 1395 }
8880f4ec
BH		 1396 result = IRQ_HANDLED;
1397
41b7e4c3 1398 } else if (EFX_WORKAROUND_15783(efx)) {
8880f4ec
BH		 1399 efx_qword_t *event;
1400
41b7e4c3
SH		 1401 /* We can't return IRQ_HANDLED more than once on seeing ISR=0
1402 * because this might be a shared interrupt. */
1403 if (efx->irq_zero_count++ == 0)
1404 result = IRQ_HANDLED;
1405
1406 /* Ensure we schedule or rearm all event queues */
8880f4ec
BH		 1407 efx_for_each_channel(channel, efx) {
1408 event = efx_event(channel, channel->eventq_read_ptr);
1409 if (efx_event_present(event))
1410 efx_schedule_channel(channel);
41b7e4c3
SH		 1411 else
1412 efx_nic_eventq_read_ack(channel);
8880f4ec 1413 }
8e730c15
BH		 1414 }
1415
1416 if (result == IRQ_HANDLED) {
1417 efx->last_irq_cpu = raw_smp_processor_id();
1418 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1419 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1420 }
1421
1422 return result;
1423}
1424
1425/* Handle an MSI interrupt
1426 *
1427 * Handle an MSI hardware interrupt. This routine schedules event
1428 * queue processing. No interrupt acknowledgement cycle is necessary.
1429 * Also, we never need to check that the interrupt is for us, since
1430 * MSI interrupts cannot be shared.
1431 */
1432static irqreturn_t efx_msi_interrupt(int irq, void *dev_id)
1433{
1434 struct efx_channel *channel = dev_id;
1435 struct efx_nic *efx = channel->efx;
1436 efx_oword_t *int_ker = efx->irq_status.addr;
1437 int syserr;
1438
1439 efx->last_irq_cpu = raw_smp_processor_id();
1440 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1441 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1442
1443 /* Check to see if we have a serious error condition */
63695459
SH		 1444 if (channel->channel == efx->fatal_irq_level) {
1445 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1446 if (unlikely(syserr))
1447 return efx_nic_fatal_interrupt(efx);
1448 }
8e730c15
BH		 1449
1450 /* Schedule processing of the channel */
1451 efx_schedule_channel(channel);
1452
1453 return IRQ_HANDLED;
1454}
1455
1456
1457/* Setup RSS indirection table.
1458 * This maps from the hash value of the packet to RXQ
1459 */
1460static void efx_setup_rss_indir_table(struct efx_nic *efx)
1461{
1462 int i = 0;
1463 unsigned long offset;
1464 efx_dword_t dword;
1465
1466 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1467 return;
1468
1469 for (offset = FR_BZ_RX_INDIRECTION_TBL;
1470 offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
1471 offset += 0x10) {
1472 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
a4900ac9 1473 i % efx->n_rx_channels);
8e730c15
BH		 1474 efx_writed(efx, &dword, offset);
1475 i++;
1476 }
1477}
1478
1479/* Hook interrupt handler(s)
1480 * Try MSI and then legacy interrupts.
1481 */
1482int efx_nic_init_interrupt(struct efx_nic *efx)
1483{
1484 struct efx_channel *channel;
1485 int rc;
1486
1487 if (!EFX_INT_MODE_USE_MSI(efx)) {
1488 irq_handler_t handler;
1489 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1490 handler = efx_legacy_interrupt;
1491 else
1492 handler = falcon_legacy_interrupt_a1;
1493
1494 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1495 efx->name, efx);
1496 if (rc) {
1497 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1498 efx->pci_dev->irq);
1499 goto fail1;
1500 }
1501 return 0;
1502 }
1503
1504 /* Hook MSI or MSI-X interrupt */
1505 efx_for_each_channel(channel, efx) {
1506 rc = request_irq(channel->irq, efx_msi_interrupt,
1507 IRQF_PROBE_SHARED, /* Not shared */
1508 channel->name, channel);
1509 if (rc) {
1510 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1511 goto fail2;
1512 }
1513 }
1514
1515 return 0;
1516
1517 fail2:
1518 efx_for_each_channel(channel, efx)
1519 free_irq(channel->irq, channel);
1520 fail1:
1521 return rc;
1522}
1523
1524void efx_nic_fini_interrupt(struct efx_nic *efx)
1525{
1526 struct efx_channel *channel;
1527 efx_oword_t reg;
1528
1529 /* Disable MSI/MSI-X interrupts */
1530 efx_for_each_channel(channel, efx) {
1531 if (channel->irq)
1532 free_irq(channel->irq, channel);
1533 }
1534
1535 /* ACK legacy interrupt */
1536 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1537 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
1538 else
1539 falcon_irq_ack_a1(efx);
1540
1541 /* Disable legacy interrupt */
1542 if (efx->legacy_irq)
1543 free_irq(efx->legacy_irq, efx);
1544}
1545
1546u32 efx_nic_fpga_ver(struct efx_nic *efx)
1547{
1548 efx_oword_t altera_build;
1549 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
1550 return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER);
1551}
1552
1553void efx_nic_init_common(struct efx_nic *efx)
1554{
1555 efx_oword_t temp;
1556
1557 /* Set positions of descriptor caches in SRAM. */
1558 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR,
1559 efx->type->tx_dc_base / 8);
1560 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
1561 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR,
1562 efx->type->rx_dc_base / 8);
1563 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
1564
1565 /* Set TX descriptor cache size. */
1566 BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
1567 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
1568 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
1569
1570 /* Set RX descriptor cache size. Set low watermark to size-8, as
1571 * this allows most efficient prefetching.
1572 */
1573 BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
1574 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
1575 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
1576 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
1577 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
1578
1579 /* Program INT_KER address */
1580 EFX_POPULATE_OWORD_2(temp,
1581 FRF_AZ_NORM_INT_VEC_DIS_KER,
1582 EFX_INT_MODE_USE_MSI(efx),
1583 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1584 efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
1585
63695459
SH		 1586 if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx))
1587 /* Use an interrupt level unused by event queues */
1588 efx->fatal_irq_level = 0x1f;
1589 else
1590 /* Use a valid MSI-X vector */
1591 efx->fatal_irq_level = 0;
1592
8e730c15
BH		 1593 /* Enable all the genuinely fatal interrupts. (They are still
1594 * masked by the overall interrupt mask, controlled by
1595 * falcon_interrupts()).
1596 *
1597 * Note: All other fatal interrupts are enabled
1598 */
1599 EFX_POPULATE_OWORD_3(temp,
1600 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
1601 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
1602 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
b17424b0
SH		 1603 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1604 EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1);
8e730c15
BH		 1605 EFX_INVERT_OWORD(temp);
1606 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
1607
1608 efx_setup_rss_indir_table(efx);
1609
1610 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
1611 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
1612 */
1613 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
1614 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
1615 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
1616 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
1617 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
1618 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
1619 /* Enable SW_EV to inherit in char driver - assume harmless here */
1620 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
1621 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
1622 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
286d47ba
BH		 1623 /* Disable hardware watchdog which can misfire */
1624 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
8e730c15
BH		 1625 /* Squash TX of packets of 16 bytes or less */
1626 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1627 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
1628 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
1629}
Clone of davem's net-next-2.6 tree