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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
906bb26c | 4 | * Copyright 2005-2009 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | /* Common definitions for all Efx net driver code */ | |
12 | ||
13 | #ifndef EFX_NET_DRIVER_H | |
14 | #define EFX_NET_DRIVER_H | |
15 | ||
62776d03 BH |
16 | #if defined(EFX_ENABLE_DEBUG) && !defined(DEBUG) |
17 | #define DEBUG | |
18 | #endif | |
19 | ||
8ceee660 BH |
20 | #include <linux/version.h> |
21 | #include <linux/netdevice.h> | |
22 | #include <linux/etherdevice.h> | |
23 | #include <linux/ethtool.h> | |
24 | #include <linux/if_vlan.h> | |
90d683af | 25 | #include <linux/timer.h> |
68e7f45e | 26 | #include <linux/mdio.h> |
8ceee660 BH |
27 | #include <linux/list.h> |
28 | #include <linux/pci.h> | |
29 | #include <linux/device.h> | |
30 | #include <linux/highmem.h> | |
31 | #include <linux/workqueue.h> | |
37b5a603 | 32 | #include <linux/i2c.h> |
8ceee660 BH |
33 | |
34 | #include "enum.h" | |
35 | #include "bitfield.h" | |
8ceee660 | 36 | |
8ceee660 BH |
37 | /************************************************************************** |
38 | * | |
39 | * Build definitions | |
40 | * | |
41 | **************************************************************************/ | |
c5d5f5fd | 42 | |
906bb26c | 43 | #define EFX_DRIVER_VERSION "3.0" |
8ceee660 BH |
44 | |
45 | #ifdef EFX_ENABLE_DEBUG | |
46 | #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) | |
47 | #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) | |
48 | #else | |
49 | #define EFX_BUG_ON_PARANOID(x) do {} while (0) | |
50 | #define EFX_WARN_ON_PARANOID(x) do {} while (0) | |
51 | #endif | |
52 | ||
8ceee660 BH |
53 | /************************************************************************** |
54 | * | |
55 | * Efx data structures | |
56 | * | |
57 | **************************************************************************/ | |
58 | ||
59 | #define EFX_MAX_CHANNELS 32 | |
8ceee660 BH |
60 | #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS |
61 | ||
a4900ac9 BH |
62 | /* Checksum generation is a per-queue option in hardware, so each |
63 | * queue visible to the networking core is backed by two hardware TX | |
64 | * queues. */ | |
65 | #define EFX_MAX_CORE_TX_QUEUES EFX_MAX_CHANNELS | |
66 | #define EFX_TXQ_TYPE_OFFLOAD 1 | |
67 | #define EFX_TXQ_TYPES 2 | |
68 | #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CORE_TX_QUEUES) | |
60ac1065 | 69 | |
8ceee660 BH |
70 | /** |
71 | * struct efx_special_buffer - An Efx special buffer | |
72 | * @addr: CPU base address of the buffer | |
73 | * @dma_addr: DMA base address of the buffer | |
74 | * @len: Buffer length, in bytes | |
75 | * @index: Buffer index within controller;s buffer table | |
76 | * @entries: Number of buffer table entries | |
77 | * | |
78 | * Special buffers are used for the event queues and the TX and RX | |
79 | * descriptor queues for each channel. They are *not* used for the | |
80 | * actual transmit and receive buffers. | |
8ceee660 BH |
81 | */ |
82 | struct efx_special_buffer { | |
83 | void *addr; | |
84 | dma_addr_t dma_addr; | |
85 | unsigned int len; | |
86 | int index; | |
87 | int entries; | |
88 | }; | |
89 | ||
127e6e10 BH |
90 | enum efx_flush_state { |
91 | FLUSH_NONE, | |
92 | FLUSH_PENDING, | |
93 | FLUSH_FAILED, | |
94 | FLUSH_DONE, | |
95 | }; | |
96 | ||
8ceee660 BH |
97 | /** |
98 | * struct efx_tx_buffer - An Efx TX buffer | |
99 | * @skb: The associated socket buffer. | |
100 | * Set only on the final fragment of a packet; %NULL for all other | |
101 | * fragments. When this fragment completes, then we can free this | |
102 | * skb. | |
b9b39b62 BH |
103 | * @tsoh: The associated TSO header structure, or %NULL if this |
104 | * buffer is not a TSO header. | |
8ceee660 BH |
105 | * @dma_addr: DMA address of the fragment. |
106 | * @len: Length of this fragment. | |
107 | * This field is zero when the queue slot is empty. | |
108 | * @continuation: True if this fragment is not the end of a packet. | |
109 | * @unmap_single: True if pci_unmap_single should be used. | |
8ceee660 BH |
110 | * @unmap_len: Length of this fragment to unmap |
111 | */ | |
112 | struct efx_tx_buffer { | |
113 | const struct sk_buff *skb; | |
b9b39b62 | 114 | struct efx_tso_header *tsoh; |
8ceee660 BH |
115 | dma_addr_t dma_addr; |
116 | unsigned short len; | |
dc8cfa55 BH |
117 | bool continuation; |
118 | bool unmap_single; | |
8ceee660 BH |
119 | unsigned short unmap_len; |
120 | }; | |
121 | ||
122 | /** | |
123 | * struct efx_tx_queue - An Efx TX queue | |
124 | * | |
125 | * This is a ring buffer of TX fragments. | |
126 | * Since the TX completion path always executes on the same | |
127 | * CPU and the xmit path can operate on different CPUs, | |
128 | * performance is increased by ensuring that the completion | |
129 | * path and the xmit path operate on different cache lines. | |
130 | * This is particularly important if the xmit path is always | |
131 | * executing on one CPU which is different from the completion | |
132 | * path. There is also a cache line for members which are | |
133 | * read but not written on the fast path. | |
134 | * | |
135 | * @efx: The associated Efx NIC | |
136 | * @queue: DMA queue number | |
8ceee660 BH |
137 | * @channel: The associated channel |
138 | * @buffer: The software buffer ring | |
139 | * @txd: The hardware descriptor ring | |
ecc910f5 | 140 | * @ptr_mask: The size of the ring minus 1. |
6bc5d3a9 | 141 | * @flushed: Used when handling queue flushing |
8ceee660 BH |
142 | * @read_count: Current read pointer. |
143 | * This is the number of buffers that have been removed from both rings. | |
dc8cfa55 | 144 | * @stopped: Stopped count. |
8ceee660 BH |
145 | * Set if this TX queue is currently stopping its port. |
146 | * @insert_count: Current insert pointer | |
147 | * This is the number of buffers that have been added to the | |
148 | * software ring. | |
149 | * @write_count: Current write pointer | |
150 | * This is the number of buffers that have been added to the | |
151 | * hardware ring. | |
152 | * @old_read_count: The value of read_count when last checked. | |
153 | * This is here for performance reasons. The xmit path will | |
154 | * only get the up-to-date value of read_count if this | |
155 | * variable indicates that the queue is full. This is to | |
156 | * avoid cache-line ping-pong between the xmit path and the | |
157 | * completion path. | |
b9b39b62 BH |
158 | * @tso_headers_free: A list of TSO headers allocated for this TX queue |
159 | * that are not in use, and so available for new TSO sends. The list | |
160 | * is protected by the TX queue lock. | |
161 | * @tso_bursts: Number of times TSO xmit invoked by kernel | |
162 | * @tso_long_headers: Number of packets with headers too long for standard | |
163 | * blocks | |
164 | * @tso_packets: Number of packets via the TSO xmit path | |
8ceee660 BH |
165 | */ |
166 | struct efx_tx_queue { | |
167 | /* Members which don't change on the fast path */ | |
168 | struct efx_nic *efx ____cacheline_aligned_in_smp; | |
a4900ac9 | 169 | unsigned queue; |
8ceee660 BH |
170 | struct efx_channel *channel; |
171 | struct efx_nic *nic; | |
172 | struct efx_tx_buffer *buffer; | |
173 | struct efx_special_buffer txd; | |
ecc910f5 | 174 | unsigned int ptr_mask; |
127e6e10 | 175 | enum efx_flush_state flushed; |
8ceee660 BH |
176 | |
177 | /* Members used mainly on the completion path */ | |
178 | unsigned int read_count ____cacheline_aligned_in_smp; | |
179 | int stopped; | |
180 | ||
181 | /* Members used only on the xmit path */ | |
182 | unsigned int insert_count ____cacheline_aligned_in_smp; | |
183 | unsigned int write_count; | |
184 | unsigned int old_read_count; | |
b9b39b62 BH |
185 | struct efx_tso_header *tso_headers_free; |
186 | unsigned int tso_bursts; | |
187 | unsigned int tso_long_headers; | |
188 | unsigned int tso_packets; | |
8ceee660 BH |
189 | }; |
190 | ||
191 | /** | |
192 | * struct efx_rx_buffer - An Efx RX data buffer | |
193 | * @dma_addr: DMA base address of the buffer | |
194 | * @skb: The associated socket buffer, if any. | |
195 | * If both this and page are %NULL, the buffer slot is currently free. | |
196 | * @page: The associated page buffer, if any. | |
197 | * If both this and skb are %NULL, the buffer slot is currently free. | |
198 | * @data: Pointer to ethernet header | |
199 | * @len: Buffer length, in bytes. | |
8ceee660 BH |
200 | */ |
201 | struct efx_rx_buffer { | |
202 | dma_addr_t dma_addr; | |
203 | struct sk_buff *skb; | |
204 | struct page *page; | |
205 | char *data; | |
206 | unsigned int len; | |
8ceee660 BH |
207 | }; |
208 | ||
62b330ba SH |
209 | /** |
210 | * struct efx_rx_page_state - Page-based rx buffer state | |
211 | * | |
212 | * Inserted at the start of every page allocated for receive buffers. | |
213 | * Used to facilitate sharing dma mappings between recycled rx buffers | |
214 | * and those passed up to the kernel. | |
215 | * | |
216 | * @refcnt: Number of struct efx_rx_buffer's referencing this page. | |
217 | * When refcnt falls to zero, the page is unmapped for dma | |
218 | * @dma_addr: The dma address of this page. | |
219 | */ | |
220 | struct efx_rx_page_state { | |
221 | unsigned refcnt; | |
222 | dma_addr_t dma_addr; | |
223 | ||
224 | unsigned int __pad[0] ____cacheline_aligned; | |
225 | }; | |
226 | ||
8ceee660 BH |
227 | /** |
228 | * struct efx_rx_queue - An Efx RX queue | |
229 | * @efx: The associated Efx NIC | |
8ceee660 BH |
230 | * @buffer: The software buffer ring |
231 | * @rxd: The hardware descriptor ring | |
ecc910f5 | 232 | * @ptr_mask: The size of the ring minus 1. |
8ceee660 BH |
233 | * @added_count: Number of buffers added to the receive queue. |
234 | * @notified_count: Number of buffers given to NIC (<= @added_count). | |
235 | * @removed_count: Number of buffers removed from the receive queue. | |
8ceee660 BH |
236 | * @max_fill: RX descriptor maximum fill level (<= ring size) |
237 | * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill | |
238 | * (<= @max_fill) | |
239 | * @fast_fill_limit: The level to which a fast fill will fill | |
240 | * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill) | |
241 | * @min_fill: RX descriptor minimum non-zero fill level. | |
242 | * This records the minimum fill level observed when a ring | |
243 | * refill was triggered. | |
8ceee660 BH |
244 | * @alloc_page_count: RX allocation strategy counter. |
245 | * @alloc_skb_count: RX allocation strategy counter. | |
90d683af | 246 | * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). |
6bc5d3a9 | 247 | * @flushed: Use when handling queue flushing |
8ceee660 BH |
248 | */ |
249 | struct efx_rx_queue { | |
250 | struct efx_nic *efx; | |
8ceee660 BH |
251 | struct efx_rx_buffer *buffer; |
252 | struct efx_special_buffer rxd; | |
ecc910f5 | 253 | unsigned int ptr_mask; |
8ceee660 BH |
254 | |
255 | int added_count; | |
256 | int notified_count; | |
257 | int removed_count; | |
8ceee660 BH |
258 | unsigned int max_fill; |
259 | unsigned int fast_fill_trigger; | |
260 | unsigned int fast_fill_limit; | |
261 | unsigned int min_fill; | |
262 | unsigned int min_overfill; | |
263 | unsigned int alloc_page_count; | |
264 | unsigned int alloc_skb_count; | |
90d683af | 265 | struct timer_list slow_fill; |
8ceee660 BH |
266 | unsigned int slow_fill_count; |
267 | ||
127e6e10 | 268 | enum efx_flush_state flushed; |
8ceee660 BH |
269 | }; |
270 | ||
271 | /** | |
272 | * struct efx_buffer - An Efx general-purpose buffer | |
273 | * @addr: host base address of the buffer | |
274 | * @dma_addr: DMA base address of the buffer | |
275 | * @len: Buffer length, in bytes | |
276 | * | |
754c653a | 277 | * The NIC uses these buffers for its interrupt status registers and |
8ceee660 BH |
278 | * MAC stats dumps. |
279 | */ | |
280 | struct efx_buffer { | |
281 | void *addr; | |
282 | dma_addr_t dma_addr; | |
283 | unsigned int len; | |
284 | }; | |
285 | ||
286 | ||
8ceee660 BH |
287 | enum efx_rx_alloc_method { |
288 | RX_ALLOC_METHOD_AUTO = 0, | |
289 | RX_ALLOC_METHOD_SKB = 1, | |
290 | RX_ALLOC_METHOD_PAGE = 2, | |
291 | }; | |
292 | ||
293 | /** | |
294 | * struct efx_channel - An Efx channel | |
295 | * | |
296 | * A channel comprises an event queue, at least one TX queue, at least | |
297 | * one RX queue, and an associated tasklet for processing the event | |
298 | * queue. | |
299 | * | |
300 | * @efx: Associated Efx NIC | |
8ceee660 | 301 | * @channel: Channel instance number |
8ceee660 BH |
302 | * @enabled: Channel enabled indicator |
303 | * @irq: IRQ number (MSI and MSI-X only) | |
0d86ebd8 | 304 | * @irq_moderation: IRQ moderation value (in hardware ticks) |
8ceee660 BH |
305 | * @napi_dev: Net device used with NAPI |
306 | * @napi_str: NAPI control structure | |
307 | * @reset_work: Scheduled reset work thread | |
308 | * @work_pending: Is work pending via NAPI? | |
309 | * @eventq: Event queue buffer | |
ecc910f5 | 310 | * @eventq_mask: Event queue pointer mask |
8ceee660 BH |
311 | * @eventq_read_ptr: Event queue read pointer |
312 | * @last_eventq_read_ptr: Last event queue read pointer value. | |
d730dc52 | 313 | * @magic_count: Event queue test event count |
6fb70fd1 BH |
314 | * @irq_count: Number of IRQs since last adaptive moderation decision |
315 | * @irq_mod_score: IRQ moderation score | |
8ceee660 BH |
316 | * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors |
317 | * and diagnostic counters | |
318 | * @rx_alloc_push_pages: RX allocation method currently in use for pushing | |
319 | * descriptors | |
8ceee660 | 320 | * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors |
8ceee660 BH |
321 | * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors |
322 | * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors | |
c1ac403b | 323 | * @n_rx_mcast_mismatch: Count of unmatched multicast frames |
8ceee660 BH |
324 | * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors |
325 | * @n_rx_overlength: Count of RX_OVERLENGTH errors | |
326 | * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun | |
8313aca3 | 327 | * @rx_queue: RX queue for this channel |
a4900ac9 BH |
328 | * @tx_stop_count: Core TX queue stop count |
329 | * @tx_stop_lock: Core TX queue stop lock | |
8313aca3 | 330 | * @tx_queue: TX queues for this channel |
8ceee660 BH |
331 | */ |
332 | struct efx_channel { | |
333 | struct efx_nic *efx; | |
8ceee660 | 334 | int channel; |
dc8cfa55 | 335 | bool enabled; |
8ceee660 | 336 | int irq; |
8ceee660 BH |
337 | unsigned int irq_moderation; |
338 | struct net_device *napi_dev; | |
339 | struct napi_struct napi_str; | |
dc8cfa55 | 340 | bool work_pending; |
8ceee660 | 341 | struct efx_special_buffer eventq; |
ecc910f5 | 342 | unsigned int eventq_mask; |
8ceee660 BH |
343 | unsigned int eventq_read_ptr; |
344 | unsigned int last_eventq_read_ptr; | |
d730dc52 | 345 | unsigned int magic_count; |
8ceee660 | 346 | |
6fb70fd1 BH |
347 | unsigned int irq_count; |
348 | unsigned int irq_mod_score; | |
349 | ||
8ceee660 BH |
350 | int rx_alloc_level; |
351 | int rx_alloc_push_pages; | |
8ceee660 BH |
352 | |
353 | unsigned n_rx_tobe_disc; | |
8ceee660 BH |
354 | unsigned n_rx_ip_hdr_chksum_err; |
355 | unsigned n_rx_tcp_udp_chksum_err; | |
c1ac403b | 356 | unsigned n_rx_mcast_mismatch; |
8ceee660 BH |
357 | unsigned n_rx_frm_trunc; |
358 | unsigned n_rx_overlength; | |
359 | unsigned n_skbuff_leaks; | |
360 | ||
361 | /* Used to pipeline received packets in order to optimise memory | |
362 | * access with prefetches. | |
363 | */ | |
364 | struct efx_rx_buffer *rx_pkt; | |
dc8cfa55 | 365 | bool rx_pkt_csummed; |
8ceee660 | 366 | |
8313aca3 BH |
367 | struct efx_rx_queue rx_queue; |
368 | ||
a4900ac9 BH |
369 | atomic_t tx_stop_count; |
370 | spinlock_t tx_stop_lock; | |
8313aca3 BH |
371 | |
372 | struct efx_tx_queue tx_queue[2]; | |
8ceee660 BH |
373 | }; |
374 | ||
398468ed BH |
375 | enum efx_led_mode { |
376 | EFX_LED_OFF = 0, | |
377 | EFX_LED_ON = 1, | |
378 | EFX_LED_DEFAULT = 2 | |
379 | }; | |
380 | ||
c459302d BH |
381 | #define STRING_TABLE_LOOKUP(val, member) \ |
382 | ((val) < member ## _max) ? member ## _names[val] : "(invalid)" | |
383 | ||
384 | extern const char *efx_loopback_mode_names[]; | |
385 | extern const unsigned int efx_loopback_mode_max; | |
386 | #define LOOPBACK_MODE(efx) \ | |
387 | STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) | |
388 | ||
389 | extern const char *efx_interrupt_mode_names[]; | |
390 | extern const unsigned int efx_interrupt_mode_max; | |
391 | #define INT_MODE(efx) \ | |
392 | STRING_TABLE_LOOKUP(efx->interrupt_mode, efx_interrupt_mode) | |
393 | ||
394 | extern const char *efx_reset_type_names[]; | |
395 | extern const unsigned int efx_reset_type_max; | |
396 | #define RESET_TYPE(type) \ | |
397 | STRING_TABLE_LOOKUP(type, efx_reset_type) | |
3273c2e8 | 398 | |
8ceee660 BH |
399 | enum efx_int_mode { |
400 | /* Be careful if altering to correct macro below */ | |
401 | EFX_INT_MODE_MSIX = 0, | |
402 | EFX_INT_MODE_MSI = 1, | |
403 | EFX_INT_MODE_LEGACY = 2, | |
404 | EFX_INT_MODE_MAX /* Insert any new items before this */ | |
405 | }; | |
406 | #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) | |
407 | ||
eb50c0d6 | 408 | #define EFX_IS10G(efx) ((efx)->link_state.speed == 10000) |
177dfcd8 | 409 | |
8ceee660 BH |
410 | enum nic_state { |
411 | STATE_INIT = 0, | |
412 | STATE_RUNNING = 1, | |
413 | STATE_FINI = 2, | |
3c78708f | 414 | STATE_DISABLED = 3, |
8ceee660 BH |
415 | STATE_MAX, |
416 | }; | |
417 | ||
418 | /* | |
419 | * Alignment of page-allocated RX buffers | |
420 | * | |
421 | * Controls the number of bytes inserted at the start of an RX buffer. | |
422 | * This is the equivalent of NET_IP_ALIGN [which controls the alignment | |
423 | * of the skb->head for hardware DMA]. | |
424 | */ | |
13e9ab11 | 425 | #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
8ceee660 BH |
426 | #define EFX_PAGE_IP_ALIGN 0 |
427 | #else | |
428 | #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN | |
429 | #endif | |
430 | ||
431 | /* | |
432 | * Alignment of the skb->head which wraps a page-allocated RX buffer | |
433 | * | |
434 | * The skb allocated to wrap an rx_buffer can have this alignment. Since | |
435 | * the data is memcpy'd from the rx_buf, it does not need to be equal to | |
436 | * EFX_PAGE_IP_ALIGN. | |
437 | */ | |
438 | #define EFX_PAGE_SKB_ALIGN 2 | |
439 | ||
440 | /* Forward declaration */ | |
441 | struct efx_nic; | |
442 | ||
443 | /* Pseudo bit-mask flow control field */ | |
444 | enum efx_fc_type { | |
3f926da8 BH |
445 | EFX_FC_RX = FLOW_CTRL_RX, |
446 | EFX_FC_TX = FLOW_CTRL_TX, | |
8ceee660 BH |
447 | EFX_FC_AUTO = 4, |
448 | }; | |
449 | ||
eb50c0d6 BH |
450 | /** |
451 | * struct efx_link_state - Current state of the link | |
452 | * @up: Link is up | |
453 | * @fd: Link is full-duplex | |
454 | * @fc: Actual flow control flags | |
455 | * @speed: Link speed (Mbps) | |
456 | */ | |
457 | struct efx_link_state { | |
458 | bool up; | |
459 | bool fd; | |
460 | enum efx_fc_type fc; | |
461 | unsigned int speed; | |
462 | }; | |
463 | ||
fdaa9aed SH |
464 | static inline bool efx_link_state_equal(const struct efx_link_state *left, |
465 | const struct efx_link_state *right) | |
466 | { | |
467 | return left->up == right->up && left->fd == right->fd && | |
468 | left->fc == right->fc && left->speed == right->speed; | |
469 | } | |
470 | ||
177dfcd8 BH |
471 | /** |
472 | * struct efx_mac_operations - Efx MAC operations table | |
473 | * @reconfigure: Reconfigure MAC. Serialised by the mac_lock | |
474 | * @update_stats: Update statistics | |
9007b9fa | 475 | * @check_fault: Check fault state. True if fault present. |
177dfcd8 BH |
476 | */ |
477 | struct efx_mac_operations { | |
d3245b28 | 478 | int (*reconfigure) (struct efx_nic *efx); |
177dfcd8 | 479 | void (*update_stats) (struct efx_nic *efx); |
9007b9fa | 480 | bool (*check_fault)(struct efx_nic *efx); |
177dfcd8 BH |
481 | }; |
482 | ||
8ceee660 BH |
483 | /** |
484 | * struct efx_phy_operations - Efx PHY operations table | |
c1c4f453 BH |
485 | * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, |
486 | * efx->loopback_modes. | |
8ceee660 BH |
487 | * @init: Initialise PHY |
488 | * @fini: Shut down PHY | |
489 | * @reconfigure: Reconfigure PHY (e.g. for new link parameters) | |
fdaa9aed SH |
490 | * @poll: Update @link_state and report whether it changed. |
491 | * Serialised by the mac_lock. | |
177dfcd8 BH |
492 | * @get_settings: Get ethtool settings. Serialised by the mac_lock. |
493 | * @set_settings: Set ethtool settings. Serialised by the mac_lock. | |
af4ad9bc | 494 | * @set_npage_adv: Set abilities advertised in (Extended) Next Page |
04cc8cac | 495 | * (only needed where AN bit is set in mmds) |
4f16c073 | 496 | * @test_alive: Test that PHY is 'alive' (online) |
c1c4f453 | 497 | * @test_name: Get the name of a PHY-specific test/result |
4f16c073 | 498 | * @run_tests: Run tests and record results as appropriate (offline). |
1796721a | 499 | * Flags are the ethtool tests flags. |
8ceee660 BH |
500 | */ |
501 | struct efx_phy_operations { | |
c1c4f453 | 502 | int (*probe) (struct efx_nic *efx); |
8ceee660 BH |
503 | int (*init) (struct efx_nic *efx); |
504 | void (*fini) (struct efx_nic *efx); | |
ff3b00a0 | 505 | void (*remove) (struct efx_nic *efx); |
d3245b28 | 506 | int (*reconfigure) (struct efx_nic *efx); |
fdaa9aed | 507 | bool (*poll) (struct efx_nic *efx); |
177dfcd8 BH |
508 | void (*get_settings) (struct efx_nic *efx, |
509 | struct ethtool_cmd *ecmd); | |
510 | int (*set_settings) (struct efx_nic *efx, | |
511 | struct ethtool_cmd *ecmd); | |
af4ad9bc | 512 | void (*set_npage_adv) (struct efx_nic *efx, u32); |
4f16c073 | 513 | int (*test_alive) (struct efx_nic *efx); |
c1c4f453 | 514 | const char *(*test_name) (struct efx_nic *efx, unsigned int index); |
1796721a | 515 | int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); |
8ceee660 BH |
516 | }; |
517 | ||
f8b87c17 BH |
518 | /** |
519 | * @enum efx_phy_mode - PHY operating mode flags | |
520 | * @PHY_MODE_NORMAL: on and should pass traffic | |
521 | * @PHY_MODE_TX_DISABLED: on with TX disabled | |
3e133c44 BH |
522 | * @PHY_MODE_LOW_POWER: set to low power through MDIO |
523 | * @PHY_MODE_OFF: switched off through external control | |
f8b87c17 BH |
524 | * @PHY_MODE_SPECIAL: on but will not pass traffic |
525 | */ | |
526 | enum efx_phy_mode { | |
527 | PHY_MODE_NORMAL = 0, | |
528 | PHY_MODE_TX_DISABLED = 1, | |
3e133c44 BH |
529 | PHY_MODE_LOW_POWER = 2, |
530 | PHY_MODE_OFF = 4, | |
f8b87c17 BH |
531 | PHY_MODE_SPECIAL = 8, |
532 | }; | |
533 | ||
534 | static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) | |
535 | { | |
8c8661e4 | 536 | return !!(mode & ~PHY_MODE_TX_DISABLED); |
f8b87c17 BH |
537 | } |
538 | ||
8ceee660 BH |
539 | /* |
540 | * Efx extended statistics | |
541 | * | |
542 | * Not all statistics are provided by all supported MACs. The purpose | |
543 | * is this structure is to contain the raw statistics provided by each | |
544 | * MAC. | |
545 | */ | |
546 | struct efx_mac_stats { | |
547 | u64 tx_bytes; | |
548 | u64 tx_good_bytes; | |
549 | u64 tx_bad_bytes; | |
550 | unsigned long tx_packets; | |
551 | unsigned long tx_bad; | |
552 | unsigned long tx_pause; | |
553 | unsigned long tx_control; | |
554 | unsigned long tx_unicast; | |
555 | unsigned long tx_multicast; | |
556 | unsigned long tx_broadcast; | |
557 | unsigned long tx_lt64; | |
558 | unsigned long tx_64; | |
559 | unsigned long tx_65_to_127; | |
560 | unsigned long tx_128_to_255; | |
561 | unsigned long tx_256_to_511; | |
562 | unsigned long tx_512_to_1023; | |
563 | unsigned long tx_1024_to_15xx; | |
564 | unsigned long tx_15xx_to_jumbo; | |
565 | unsigned long tx_gtjumbo; | |
566 | unsigned long tx_collision; | |
567 | unsigned long tx_single_collision; | |
568 | unsigned long tx_multiple_collision; | |
569 | unsigned long tx_excessive_collision; | |
570 | unsigned long tx_deferred; | |
571 | unsigned long tx_late_collision; | |
572 | unsigned long tx_excessive_deferred; | |
573 | unsigned long tx_non_tcpudp; | |
574 | unsigned long tx_mac_src_error; | |
575 | unsigned long tx_ip_src_error; | |
576 | u64 rx_bytes; | |
577 | u64 rx_good_bytes; | |
578 | u64 rx_bad_bytes; | |
579 | unsigned long rx_packets; | |
580 | unsigned long rx_good; | |
581 | unsigned long rx_bad; | |
582 | unsigned long rx_pause; | |
583 | unsigned long rx_control; | |
584 | unsigned long rx_unicast; | |
585 | unsigned long rx_multicast; | |
586 | unsigned long rx_broadcast; | |
587 | unsigned long rx_lt64; | |
588 | unsigned long rx_64; | |
589 | unsigned long rx_65_to_127; | |
590 | unsigned long rx_128_to_255; | |
591 | unsigned long rx_256_to_511; | |
592 | unsigned long rx_512_to_1023; | |
593 | unsigned long rx_1024_to_15xx; | |
594 | unsigned long rx_15xx_to_jumbo; | |
595 | unsigned long rx_gtjumbo; | |
596 | unsigned long rx_bad_lt64; | |
597 | unsigned long rx_bad_64_to_15xx; | |
598 | unsigned long rx_bad_15xx_to_jumbo; | |
599 | unsigned long rx_bad_gtjumbo; | |
600 | unsigned long rx_overflow; | |
601 | unsigned long rx_missed; | |
602 | unsigned long rx_false_carrier; | |
603 | unsigned long rx_symbol_error; | |
604 | unsigned long rx_align_error; | |
605 | unsigned long rx_length_error; | |
606 | unsigned long rx_internal_error; | |
607 | unsigned long rx_good_lt64; | |
608 | }; | |
609 | ||
610 | /* Number of bits used in a multicast filter hash address */ | |
611 | #define EFX_MCAST_HASH_BITS 8 | |
612 | ||
613 | /* Number of (single-bit) entries in a multicast filter hash */ | |
614 | #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) | |
615 | ||
616 | /* An Efx multicast filter hash */ | |
617 | union efx_multicast_hash { | |
618 | u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; | |
619 | efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; | |
620 | }; | |
621 | ||
64eebcfd BH |
622 | struct efx_filter_state; |
623 | ||
8ceee660 BH |
624 | /** |
625 | * struct efx_nic - an Efx NIC | |
626 | * @name: Device name (net device name or bus id before net device registered) | |
627 | * @pci_dev: The PCI device | |
628 | * @type: Controller type attributes | |
629 | * @legacy_irq: IRQ number | |
8d9853d9 BH |
630 | * @workqueue: Workqueue for port reconfigures and the HW monitor. |
631 | * Work items do not hold and must not acquire RTNL. | |
6977dc63 | 632 | * @workqueue_name: Name of workqueue |
8ceee660 BH |
633 | * @reset_work: Scheduled reset workitem |
634 | * @monitor_work: Hardware monitor workitem | |
635 | * @membase_phys: Memory BAR value as physical address | |
636 | * @membase: Memory BAR value | |
637 | * @biu_lock: BIU (bus interface unit) lock | |
638 | * @interrupt_mode: Interrupt mode | |
6fb70fd1 BH |
639 | * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues |
640 | * @irq_rx_moderation: IRQ moderation time for RX event queues | |
62776d03 | 641 | * @msg_enable: Log message enable flags |
8ceee660 BH |
642 | * @state: Device state flag. Serialised by the rtnl_lock. |
643 | * @reset_pending: Pending reset method (normally RESET_TYPE_NONE) | |
644 | * @tx_queue: TX DMA queues | |
645 | * @rx_queue: RX DMA queues | |
646 | * @channel: Channels | |
4642610c | 647 | * @channel_name: Names for channels and their IRQs |
ecc910f5 SH |
648 | * @rxq_entries: Size of receive queues requested by user. |
649 | * @txq_entries: Size of transmit queues requested by user. | |
0484e0db | 650 | * @next_buffer_table: First available buffer table id |
28b581ab | 651 | * @n_channels: Number of channels in use |
a4900ac9 BH |
652 | * @n_rx_channels: Number of channels used for RX (= number of RX queues) |
653 | * @n_tx_channels: Number of channels used for TX | |
8ceee660 BH |
654 | * @rx_buffer_len: RX buffer length |
655 | * @rx_buffer_order: Order (log2) of number of pages for each RX buffer | |
765c9f46 | 656 | * @rx_indir_table: Indirection table for RSS |
0484e0db BH |
657 | * @int_error_count: Number of internal errors seen recently |
658 | * @int_error_expire: Time at which error count will be expired | |
8ceee660 BH |
659 | * @irq_status: Interrupt status buffer |
660 | * @last_irq_cpu: Last CPU to handle interrupt. | |
661 | * This register is written with the SMP processor ID whenever an | |
754c653a | 662 | * interrupt is handled. It is used by efx_nic_test_interrupt() |
8ceee660 | 663 | * to verify that an interrupt has occurred. |
c28884c5 | 664 | * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 |
63695459 | 665 | * @fatal_irq_level: IRQ level (bit number) used for serious errors |
4a5b504d | 666 | * @spi_flash: SPI flash device |
76884835 | 667 | * This field will be %NULL if no flash device is present (or for Siena). |
4a5b504d | 668 | * @spi_eeprom: SPI EEPROM device |
76884835 | 669 | * This field will be %NULL if no EEPROM device is present (or for Siena). |
f4150724 | 670 | * @spi_lock: SPI bus lock |
76884835 | 671 | * @mtd_list: List of MTDs attached to the NIC |
8ceee660 BH |
672 | * @n_rx_nodesc_drop_cnt: RX no descriptor drop count |
673 | * @nic_data: Hardware dependant state | |
8c8661e4 BH |
674 | * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, |
675 | * @port_inhibited, efx_monitor() and efx_reconfigure_port() | |
8ceee660 | 676 | * @port_enabled: Port enabled indicator. |
fdaa9aed SH |
677 | * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and |
678 | * efx_mac_work() with kernel interfaces. Safe to read under any | |
679 | * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must | |
680 | * be held to modify it. | |
8c8661e4 | 681 | * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock |
8ceee660 BH |
682 | * @port_initialized: Port initialized? |
683 | * @net_dev: Operating system network device. Consider holding the rtnl lock | |
684 | * @rx_checksum_enabled: RX checksumming enabled | |
8ceee660 BH |
685 | * @mac_stats: MAC statistics. These include all statistics the MACs |
686 | * can provide. Generic code converts these into a standard | |
687 | * &struct net_device_stats. | |
688 | * @stats_buffer: DMA buffer for statistics | |
8c8661e4 | 689 | * @stats_lock: Statistics update lock. Serialises statistics fetches |
177dfcd8 | 690 | * @mac_op: MAC interface |
8ceee660 BH |
691 | * @mac_address: Permanent MAC address |
692 | * @phy_type: PHY type | |
ab867461 | 693 | * @mdio_lock: MDIO lock |
8ceee660 BH |
694 | * @phy_op: PHY interface |
695 | * @phy_data: PHY private data (including PHY-specific stats) | |
68e7f45e | 696 | * @mdio: PHY MDIO interface |
8880f4ec | 697 | * @mdio_bus: PHY MDIO bus ID (only used by Siena) |
8c8661e4 | 698 | * @phy_mode: PHY operating mode. Serialised by @mac_lock. |
9007b9fa | 699 | * @xmac_poll_required: XMAC link state needs polling |
d3245b28 | 700 | * @link_advertising: Autonegotiation advertising flags |
eb50c0d6 | 701 | * @link_state: Current state of the link |
8ceee660 BH |
702 | * @n_link_state_changes: Number of times the link has changed state |
703 | * @promiscuous: Promiscuous flag. Protected by netif_tx_lock. | |
704 | * @multicast_hash: Multicast hash table | |
04cc8cac | 705 | * @wanted_fc: Wanted flow control flags |
8be4f3e6 | 706 | * @mac_work: Work item for changing MAC promiscuity and multicast hash |
3273c2e8 BH |
707 | * @loopback_mode: Loopback status |
708 | * @loopback_modes: Supported loopback mode bitmask | |
709 | * @loopback_selftest: Offline self-test private state | |
8ceee660 | 710 | * |
754c653a | 711 | * This is stored in the private area of the &struct net_device. |
8ceee660 BH |
712 | */ |
713 | struct efx_nic { | |
714 | char name[IFNAMSIZ]; | |
715 | struct pci_dev *pci_dev; | |
716 | const struct efx_nic_type *type; | |
717 | int legacy_irq; | |
718 | struct workqueue_struct *workqueue; | |
6977dc63 | 719 | char workqueue_name[16]; |
8ceee660 BH |
720 | struct work_struct reset_work; |
721 | struct delayed_work monitor_work; | |
086ea356 | 722 | resource_size_t membase_phys; |
8ceee660 BH |
723 | void __iomem *membase; |
724 | spinlock_t biu_lock; | |
725 | enum efx_int_mode interrupt_mode; | |
6fb70fd1 BH |
726 | bool irq_rx_adaptive; |
727 | unsigned int irq_rx_moderation; | |
62776d03 | 728 | u32 msg_enable; |
8ceee660 | 729 | |
8ceee660 BH |
730 | enum nic_state state; |
731 | enum reset_type reset_pending; | |
732 | ||
8313aca3 | 733 | struct efx_channel *channel[EFX_MAX_CHANNELS]; |
efbc2d7c | 734 | char channel_name[EFX_MAX_CHANNELS][IFNAMSIZ + 6]; |
8ceee660 | 735 | |
ecc910f5 SH |
736 | unsigned rxq_entries; |
737 | unsigned txq_entries; | |
0484e0db | 738 | unsigned next_buffer_table; |
a4900ac9 BH |
739 | unsigned n_channels; |
740 | unsigned n_rx_channels; | |
741 | unsigned n_tx_channels; | |
8ceee660 BH |
742 | unsigned int rx_buffer_len; |
743 | unsigned int rx_buffer_order; | |
5d3a6fca | 744 | u8 rx_hash_key[40]; |
765c9f46 | 745 | u32 rx_indir_table[128]; |
8ceee660 | 746 | |
0484e0db BH |
747 | unsigned int_error_count; |
748 | unsigned long int_error_expire; | |
749 | ||
8ceee660 BH |
750 | struct efx_buffer irq_status; |
751 | volatile signed int last_irq_cpu; | |
c28884c5 | 752 | unsigned irq_zero_count; |
63695459 | 753 | unsigned fatal_irq_level; |
8ceee660 | 754 | |
4a5b504d BH |
755 | struct efx_spi_device *spi_flash; |
756 | struct efx_spi_device *spi_eeprom; | |
f4150724 | 757 | struct mutex spi_lock; |
76884835 BH |
758 | #ifdef CONFIG_SFC_MTD |
759 | struct list_head mtd_list; | |
760 | #endif | |
4a5b504d | 761 | |
8ceee660 BH |
762 | unsigned n_rx_nodesc_drop_cnt; |
763 | ||
8880f4ec | 764 | void *nic_data; |
8ceee660 BH |
765 | |
766 | struct mutex mac_lock; | |
766ca0fa | 767 | struct work_struct mac_work; |
dc8cfa55 | 768 | bool port_enabled; |
8c8661e4 | 769 | bool port_inhibited; |
8ceee660 | 770 | |
dc8cfa55 | 771 | bool port_initialized; |
8ceee660 | 772 | struct net_device *net_dev; |
dc8cfa55 | 773 | bool rx_checksum_enabled; |
8ceee660 | 774 | |
8ceee660 BH |
775 | struct efx_mac_stats mac_stats; |
776 | struct efx_buffer stats_buffer; | |
777 | spinlock_t stats_lock; | |
778 | ||
177dfcd8 | 779 | struct efx_mac_operations *mac_op; |
8ceee660 BH |
780 | unsigned char mac_address[ETH_ALEN]; |
781 | ||
c1c4f453 | 782 | unsigned int phy_type; |
ab867461 | 783 | struct mutex mdio_lock; |
8ceee660 BH |
784 | struct efx_phy_operations *phy_op; |
785 | void *phy_data; | |
68e7f45e | 786 | struct mdio_if_info mdio; |
8880f4ec | 787 | unsigned int mdio_bus; |
f8b87c17 | 788 | enum efx_phy_mode phy_mode; |
8ceee660 | 789 | |
9007b9fa | 790 | bool xmac_poll_required; |
d3245b28 | 791 | u32 link_advertising; |
eb50c0d6 | 792 | struct efx_link_state link_state; |
8ceee660 BH |
793 | unsigned int n_link_state_changes; |
794 | ||
dc8cfa55 | 795 | bool promiscuous; |
8ceee660 | 796 | union efx_multicast_hash multicast_hash; |
04cc8cac | 797 | enum efx_fc_type wanted_fc; |
8ceee660 BH |
798 | |
799 | atomic_t rx_reset; | |
3273c2e8 | 800 | enum efx_loopback_mode loopback_mode; |
e58f69f4 | 801 | u64 loopback_modes; |
3273c2e8 BH |
802 | |
803 | void *loopback_selftest; | |
64eebcfd BH |
804 | |
805 | struct efx_filter_state *filter_state; | |
8ceee660 BH |
806 | }; |
807 | ||
55668611 BH |
808 | static inline int efx_dev_registered(struct efx_nic *efx) |
809 | { | |
810 | return efx->net_dev->reg_state == NETREG_REGISTERED; | |
811 | } | |
812 | ||
813 | /* Net device name, for inclusion in log messages if it has been registered. | |
814 | * Use efx->name not efx->net_dev->name so that races with (un)registration | |
815 | * are harmless. | |
816 | */ | |
817 | static inline const char *efx_dev_name(struct efx_nic *efx) | |
818 | { | |
819 | return efx_dev_registered(efx) ? efx->name : ""; | |
820 | } | |
821 | ||
8880f4ec BH |
822 | static inline unsigned int efx_port_num(struct efx_nic *efx) |
823 | { | |
3df95ce9 | 824 | return efx->net_dev->dev_id; |
8880f4ec BH |
825 | } |
826 | ||
8ceee660 BH |
827 | /** |
828 | * struct efx_nic_type - Efx device type definition | |
ef2b90ee BH |
829 | * @probe: Probe the controller |
830 | * @remove: Free resources allocated by probe() | |
831 | * @init: Initialise the controller | |
832 | * @fini: Shut down the controller | |
833 | * @monitor: Periodic function for polling link state and hardware monitor | |
834 | * @reset: Reset the controller hardware and possibly the PHY. This will | |
835 | * be called while the controller is uninitialised. | |
836 | * @probe_port: Probe the MAC and PHY | |
837 | * @remove_port: Free resources allocated by probe_port() | |
838 | * @prepare_flush: Prepare the hardware for flushing the DMA queues | |
839 | * @update_stats: Update statistics not provided by event handling | |
840 | * @start_stats: Start the regular fetching of statistics | |
841 | * @stop_stats: Stop the regular fetching of statistics | |
06629f07 | 842 | * @set_id_led: Set state of identifying LED or revert to automatic function |
ef2b90ee BH |
843 | * @push_irq_moderation: Apply interrupt moderation value |
844 | * @push_multicast_hash: Apply multicast hash table | |
d3245b28 | 845 | * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY |
89c758fa BH |
846 | * @get_wol: Get WoL configuration from driver state |
847 | * @set_wol: Push WoL configuration to the NIC | |
848 | * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) | |
9bfc4bb1 | 849 | * @test_registers: Test read/write functionality of control registers |
0aa3fbaa | 850 | * @test_nvram: Test validity of NVRAM contents |
b895d73e | 851 | * @default_mac_ops: efx_mac_operations to set at startup |
daeda630 | 852 | * @revision: Hardware architecture revision |
8ceee660 BH |
853 | * @mem_map_size: Memory BAR mapped size |
854 | * @txd_ptr_tbl_base: TX descriptor ring base address | |
855 | * @rxd_ptr_tbl_base: RX descriptor ring base address | |
856 | * @buf_tbl_base: Buffer table base address | |
857 | * @evq_ptr_tbl_base: Event queue pointer table base address | |
858 | * @evq_rptr_tbl_base: Event queue read-pointer table base address | |
8ceee660 | 859 | * @max_dma_mask: Maximum possible DMA mask |
39c9cf07 BH |
860 | * @rx_buffer_hash_size: Size of hash at start of RX buffer |
861 | * @rx_buffer_padding: Size of padding at end of RX buffer | |
8ceee660 BH |
862 | * @max_interrupt_mode: Highest capability interrupt mode supported |
863 | * from &enum efx_init_mode. | |
864 | * @phys_addr_channels: Number of channels with physically addressed | |
865 | * descriptors | |
0228f5cd BH |
866 | * @tx_dc_base: Base address in SRAM of TX queue descriptor caches |
867 | * @rx_dc_base: Base address in SRAM of RX queue descriptor caches | |
c383b537 BH |
868 | * @offload_features: net_device feature flags for protocol offload |
869 | * features implemented in hardware | |
eb9f6744 BH |
870 | * @reset_world_flags: Flags for additional components covered by |
871 | * reset method RESET_TYPE_WORLD | |
8ceee660 BH |
872 | */ |
873 | struct efx_nic_type { | |
ef2b90ee BH |
874 | int (*probe)(struct efx_nic *efx); |
875 | void (*remove)(struct efx_nic *efx); | |
876 | int (*init)(struct efx_nic *efx); | |
877 | void (*fini)(struct efx_nic *efx); | |
878 | void (*monitor)(struct efx_nic *efx); | |
879 | int (*reset)(struct efx_nic *efx, enum reset_type method); | |
880 | int (*probe_port)(struct efx_nic *efx); | |
881 | void (*remove_port)(struct efx_nic *efx); | |
882 | void (*prepare_flush)(struct efx_nic *efx); | |
883 | void (*update_stats)(struct efx_nic *efx); | |
884 | void (*start_stats)(struct efx_nic *efx); | |
885 | void (*stop_stats)(struct efx_nic *efx); | |
06629f07 | 886 | void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); |
ef2b90ee BH |
887 | void (*push_irq_moderation)(struct efx_channel *channel); |
888 | void (*push_multicast_hash)(struct efx_nic *efx); | |
d3245b28 | 889 | int (*reconfigure_port)(struct efx_nic *efx); |
89c758fa BH |
890 | void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); |
891 | int (*set_wol)(struct efx_nic *efx, u32 type); | |
892 | void (*resume_wol)(struct efx_nic *efx); | |
9bfc4bb1 | 893 | int (*test_registers)(struct efx_nic *efx); |
0aa3fbaa | 894 | int (*test_nvram)(struct efx_nic *efx); |
b895d73e SH |
895 | struct efx_mac_operations *default_mac_ops; |
896 | ||
daeda630 | 897 | int revision; |
8ceee660 BH |
898 | unsigned int mem_map_size; |
899 | unsigned int txd_ptr_tbl_base; | |
900 | unsigned int rxd_ptr_tbl_base; | |
901 | unsigned int buf_tbl_base; | |
902 | unsigned int evq_ptr_tbl_base; | |
903 | unsigned int evq_rptr_tbl_base; | |
9bbd7d9a | 904 | u64 max_dma_mask; |
39c9cf07 | 905 | unsigned int rx_buffer_hash_size; |
8ceee660 BH |
906 | unsigned int rx_buffer_padding; |
907 | unsigned int max_interrupt_mode; | |
908 | unsigned int phys_addr_channels; | |
0228f5cd BH |
909 | unsigned int tx_dc_base; |
910 | unsigned int rx_dc_base; | |
c383b537 | 911 | unsigned long offload_features; |
eb9f6744 | 912 | u32 reset_world_flags; |
8ceee660 BH |
913 | }; |
914 | ||
915 | /************************************************************************** | |
916 | * | |
917 | * Prototypes and inline functions | |
918 | * | |
919 | *************************************************************************/ | |
920 | ||
f7d12cdc BH |
921 | static inline struct efx_channel * |
922 | efx_get_channel(struct efx_nic *efx, unsigned index) | |
923 | { | |
924 | EFX_BUG_ON_PARANOID(index >= efx->n_channels); | |
8313aca3 | 925 | return efx->channel[index]; |
f7d12cdc BH |
926 | } |
927 | ||
8ceee660 BH |
928 | /* Iterate over all used channels */ |
929 | #define efx_for_each_channel(_channel, _efx) \ | |
8313aca3 BH |
930 | for (_channel = (_efx)->channel[0]; \ |
931 | _channel; \ | |
932 | _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ | |
933 | (_efx)->channel[_channel->channel + 1] : NULL) | |
8ceee660 | 934 | |
8313aca3 BH |
935 | extern struct efx_tx_queue * |
936 | efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type); | |
f7d12cdc BH |
937 | |
938 | static inline struct efx_tx_queue * | |
939 | efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) | |
940 | { | |
941 | struct efx_tx_queue *tx_queue = channel->tx_queue; | |
942 | EFX_BUG_ON_PARANOID(type >= EFX_TXQ_TYPES); | |
8313aca3 | 943 | return tx_queue->channel ? tx_queue + type : NULL; |
f7d12cdc | 944 | } |
8ceee660 BH |
945 | |
946 | /* Iterate over all TX queues belonging to a channel */ | |
947 | #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ | |
8313aca3 | 948 | for (_tx_queue = efx_channel_get_tx_queue(channel, 0); \ |
a4900ac9 BH |
949 | _tx_queue && _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ |
950 | _tx_queue++) | |
8ceee660 | 951 | |
f7d12cdc BH |
952 | static inline struct efx_rx_queue * |
953 | efx_get_rx_queue(struct efx_nic *efx, unsigned index) | |
954 | { | |
955 | EFX_BUG_ON_PARANOID(index >= efx->n_rx_channels); | |
8313aca3 | 956 | return &efx->channel[index]->rx_queue; |
f7d12cdc BH |
957 | } |
958 | ||
f7d12cdc BH |
959 | static inline struct efx_rx_queue * |
960 | efx_channel_get_rx_queue(struct efx_channel *channel) | |
961 | { | |
8313aca3 BH |
962 | return channel->channel < channel->efx->n_rx_channels ? |
963 | &channel->rx_queue : NULL; | |
f7d12cdc BH |
964 | } |
965 | ||
8ceee660 BH |
966 | /* Iterate over all RX queues belonging to a channel */ |
967 | #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ | |
8313aca3 | 968 | for (_rx_queue = efx_channel_get_rx_queue(channel); \ |
a2589027 | 969 | _rx_queue; \ |
8313aca3 | 970 | _rx_queue = NULL) |
8ceee660 | 971 | |
ba1e8a35 BH |
972 | static inline struct efx_channel * |
973 | efx_rx_queue_channel(struct efx_rx_queue *rx_queue) | |
974 | { | |
8313aca3 | 975 | return container_of(rx_queue, struct efx_channel, rx_queue); |
ba1e8a35 BH |
976 | } |
977 | ||
978 | static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) | |
979 | { | |
8313aca3 | 980 | return efx_rx_queue_channel(rx_queue)->channel; |
ba1e8a35 BH |
981 | } |
982 | ||
8ceee660 BH |
983 | /* Returns a pointer to the specified receive buffer in the RX |
984 | * descriptor queue. | |
985 | */ | |
986 | static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, | |
987 | unsigned int index) | |
988 | { | |
989 | return (&rx_queue->buffer[index]); | |
990 | } | |
991 | ||
992 | /* Set bit in a little-endian bitfield */ | |
18c2fc04 | 993 | static inline void set_bit_le(unsigned nr, unsigned char *addr) |
8ceee660 BH |
994 | { |
995 | addr[nr / 8] |= (1 << (nr % 8)); | |
996 | } | |
997 | ||
998 | /* Clear bit in a little-endian bitfield */ | |
18c2fc04 | 999 | static inline void clear_bit_le(unsigned nr, unsigned char *addr) |
8ceee660 BH |
1000 | { |
1001 | addr[nr / 8] &= ~(1 << (nr % 8)); | |
1002 | } | |
1003 | ||
1004 | ||
1005 | /** | |
1006 | * EFX_MAX_FRAME_LEN - calculate maximum frame length | |
1007 | * | |
1008 | * This calculates the maximum frame length that will be used for a | |
1009 | * given MTU. The frame length will be equal to the MTU plus a | |
1010 | * constant amount of header space and padding. This is the quantity | |
1011 | * that the net driver will program into the MAC as the maximum frame | |
1012 | * length. | |
1013 | * | |
754c653a | 1014 | * The 10G MAC requires 8-byte alignment on the frame |
8ceee660 | 1015 | * length, so we round up to the nearest 8. |
cc11763b BH |
1016 | * |
1017 | * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an | |
1018 | * XGMII cycle). If the frame length reaches the maximum value in the | |
1019 | * same cycle, the XMAC can miss the IPG altogether. We work around | |
1020 | * this by adding a further 16 bytes. | |
8ceee660 BH |
1021 | */ |
1022 | #define EFX_MAX_FRAME_LEN(mtu) \ | |
cc11763b | 1023 | ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16) |
8ceee660 BH |
1024 | |
1025 | ||
1026 | #endif /* EFX_NET_DRIVER_H */ |